advertisement
Intel ®
Series
Celeron ® Processor 400 Δ
Datasheet
— Supporting the Intel
®
Celeron
®
450
Δ
processor 420
Δ
, 430
Δ
, 440
Δ
, and
August 2008
Document Number: 316963-002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT
INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Δ Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different processor families. See http://www.intel.com/products/processor_number for details. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are not intended to represent proportional or quantitative increases in any particular feature. Current roadmap processor number progression is not necessarily representative of future roadmaps. See www.intel.com/products/ processor_number for details.
Intel ® 64 requires a computer system with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for Intel 64. Processor will not operate (including 32-bit operation) without an Intel 64-enabled BIOS. Performance will vary depending on your hardware and software configurations. See http://www.intel.com/technology/intel64/index.htm for more information including details on which processors support Intel 64, or consult with your system vendor for more information.
Enabling Execute Disable Bit functionality requires a PC with a processor with Execute Disable Bit capability and a supporting operating system. Check with your PC manufacturer on whether your system delivers Execute Disable Bit functionality.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel ® Celeron ® processor 400 series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Intel, Celeron, Pentium, Intel Core, and the Intel logo are trademarks of Intel Corporation in the U.S. and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2007–2008 Intel Corporation.
2 Datasheet
Contents
Introduction ..............................................................................................................9
Terminology .......................................................................................................9
Processor Packaging Terminology ............................................................. 10
Electrical Specifications ........................................................................................... 13
Power and Ground Lands.................................................................................... 13
Voltage Identification ......................................................................................... 14
Reserved, Unused and TESTHI Signals ................................................................. 16
Absolute Maximum and Minimum Ratings .................................................. 17
DC Voltage and Current Specification ........................................................ 19
FSB Signal Groups.................................................................................. 23
CMOS and Open Drain Signals ................................................................. 25
Processor DC Specifications ..................................................................... 25
GTL+ Front Side Bus Specifications ............................................. 27
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking ............................ 28
FSB Frequency Select Signals (BSEL[2:0])................................................. 29
Phase Lock Loop (PLL) and Filter .............................................................. 29
BCLK[1:0] Specifications (CK505 based Platforms) ..................................... 30
BCLK[1:0] Specifications (CK410 based Platforms) ..................................... 32
Alphabetical Signals Reference ............................................................................ 66
Datasheet 3
On-Demand Mode...................................................................................80
PROCHOT# Signal ..................................................................................81
THERMTRIP# Signal ................................................................................81
Thermal Diode...................................................................................................82
Key Difference with Legacy Diode-Based Thermal Management .......84
PECI Device Address..................................................................86
PECI Command Support .............................................................86
PECI Fault Handling Requirements ...............................................86
PECI GetTemp0() Error Code Support ..........................................86
Features ..................................................................................................................87
Power-On Configuration Options ..........................................................................87
Clock Control and Low Power States.....................................................................87
Normal State .........................................................................................88
HALT and Extended HALT Powerdown States ..............................................88
HALT Powerdown State ..............................................................88
Extended HALT Powerdown State ................................................89
Stop Grant State ....................................................................................89
HALT Snoop State and Stop Grant Snoop State...........................................90
Boxed Processor Cooling Solution Dimensions.............................................92
Boxed Processor Fan Heatsink Weight .......................................................94
Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly .....94
Fan Heatsink Power Supply ......................................................................94
Boxed Processor Cooling Requirements......................................................95
Mechanical Considerations .......................................................................99
4 Datasheet
Figures
CC
Static and Transient Tolerance ............................................................................. 21
CC
Overshoot Example Waveform ............................................................................. 22
29 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view) .................... 96
30 Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)................... 96
Tables
3 Market Segment Selection Truth Table for MSID[1:0]
................................................... 16
CC
Static and Transient Tolerance ............................................................................. 20
CC
Overshoot Specifications ..................................................................................... 21
Datasheet 5
6 Datasheet
Revision History
Revision
Number
-001
-002
Description
• Initial release
• Added Intel ® Celeron ® processor 450
§
Date
June 2007
August 2008
Datasheet 7
8
Intel
®
Celeron
®
Series Features
Processor 400
• Available at 1.60 GHz, 1.8 GHz, 2.00 GHz,
2.2 GHz
• Supports Intel ® 64 architecture
• Supports Execute Disable Bit capability
• Binary compatible with applications running on previous members of the Intel microprocessor line
• FSB frequency at 800 MHz
• Advance Dynamic Execution
• Very deep out-of-order execution
• Enhanced branch prediction
• Optimized for 32-bit applications running on advanced 32-bit operating systems
• Two 32-KB Level 1 data caches
• 1 MB and 512KB Advanced Smart Cache
• Advanced Digital Media Boost
• Enhanced floating point and multimedia unit for enhanced video, audio, encryption, and 3D performance
• Power Management capabilities
• System Management mode
• Multiple low-power states
• 8-way cache associativity provides improved cache hit rate on load/store operations
• 775-land Package
The Intel Celeron processor 400 series delivers Intel's advanced, powerful processors for desktop PCs.
The processor is designed to deliver performance across applications and usages where end-users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multitasking user environments.
Intel ® 64 architecture enables the processor to execute operating systems and applications written to take advantage of the Intel 64 architecture. The Intel Celeron processor 400 series also include the
Execute Disable Bit capability. This feature, combined with a supported operating system, allows memory to be marked as executable or non-executable.
§
Datasheet
Introduction
1
Note:
Note:
1.1
Introduction
The Intel
®
Celeron
®
processor 400 series is a desktop processor that combines the performance of the previous generation of Desktop products with the power efficiencies of a low-power microarchitecture to enable smaller, quieter systems. Intel Celeron
Processor 400 is a 64-bit processor that maintain compatibility with IA-32 software.
The Intel Celeron processor 400 series uses a Flip-Chip Land Grid Array (FC-LGA6) package technology, and plugs into a 775-land surface mount, Land Grid Array (LGA) socket, referred to as the LGA775 socket.
In this document the Intel Celeron processor 400 series will be referred to as "the processor."
In this document the Intel Celeron processor 400 series refers to the Intel Celeron processors 420, 430, 440, and 450.
Based on 65 nm process technology, the Intel Celeron processor 400 series is a singlecore processor that features an 800 MHz front side bus (FSB), 1 MB or 512 KB L2 cache, and a thermal design power (TDP) of 35 W. The processor also supports the
Execute Disable Bit and Intel
®
64 architecture.
The processor front side bus (FSB) uses a split-transaction, deferred reply protocol like the Intel ® Pentium ® 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data to improve performance by transferring data four times per bus clock
(4X data transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address bus provide a data bus bandwidth of up to 6.4 GB/s.
Intel will enable support components for the processor including heatsink, heatsink retention mechanism, and socket. Supported platforms may need to be refreshed to ensure the correct voltage regulation (VRD11) and that PECI support is enabled.
Manufacturability is a high priority; hence, mechanical assembly may be completed from the top of the baseboard and should not require any special tooling.
The processor includes an address bus power-down capability which removes power from the address and data signals when the FSB is not in use. This feature is always enabled on the processor.
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active state when driven to a low level. For example, when RESET# is low, a reset has been requested. Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where the name does not imply an active state but describes part of a binary sequence (such as address or data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and
D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
Front Side Bus” refers to the interface between the processor and system core logic
(a.k.a. the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.
Datasheet 9
Introduction
1.1.1
Processor Packaging Terminology
Commonly used terms are explained here for clarification:
• Intel Celeron Processor 400 Series — Single core processor in the FC-LGA6 package with a 1 MB or 512 KB L2 cache.
• Processor — For this document, the term processor is the generic form of the Intel
Celeron processor 400 series. The processor is a single package that contains one exectution unit.
• Keep-out zone — The area on or near the processor that system design can not use.
• Processor core — Processor core die with integrated L2 cache.
• LGA775 socket — The Intel Celeron processor 400 series mates with the system board through a surface mount, 775-land, LGA socket.
• Integrated heat spreader (IHS) —A component of the processor package used to enhance the thermal performance of the package. Component thermal solutions interface with the processor at the IHS surface.
• Retention mechanism (RM) — Since the LGA775 socket does not include any mechanical features for heatsink attach, a retention mechanism is required.
Component thermal solutions should attach to the processor via a retention mechanism that is independent of the socket.
• FSB (Front Side Bus) — The electrical interface that connects the processor to the chipset. Also referred to as the processor system bus or the system bus. All memory and I/O transactions as well as interrupt messages pass between the processor and chipset over the FSB.
• Storage conditions — Refers to a non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor lands should not be connected to any supply voltages, have any I/Os biased, or receive any clocks.
Upon exposure to “free air”(i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.
• Functional operation — Refers to normal operating conditions in which all processor specifications, including DC, AC, system bus, signal quality, mechanical and thermal are satisfied.
• Execute Disable Bit — The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system.
If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer over run vulnerabilities and can thus help improve the overall security of the system. See the Intel for more detailed information.
®
Architecture Software Developer's Manual
• Intel ® 64 Architecture — An enhancement to Intel's IA-32 architecture, allowing the processor to execute operating systems and applications written to take advantage of the Intel ® 64 architecture. Further details on Intel ® 64 architecture and programming model can be found in the Intel Extended Memory 64 Technology
Software Developer Guide at http://developer.intel.com/technology/
64bitextensions/.
10 Datasheet
Introduction
1.2
Table 1.
References
Material and concepts available in the following documents may be beneficial when reading this document.
References
Intel ® Celeron ® Processor 400 Series Specification Update
Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and
Transportable LGA775 Socket
Document
Intel ® Celeron ® Processor 400 Series Thermal and Mechanical Design
Guidelines
LGA775 Socket Mechanical Design Guide
Location www.intel.com/ design/processor/ specupdt/316964.htm
www.intel.com/ design/processor/ designex/316965.htm
http://www.intel.com/ design/processor/ applnots/313214.htm
http://intel.com/ design/Pentium4/ guides/302666.htm
Intel
®
64 and IA-32 Architecture Software Developer’s Manuals
Intel ® 64 and IA-32 Architecture Software Developer’s Manual
Volume 1: Basic Architecture
Intel ® 64 and IA-32 Architecture Software Developer’s Manual
Volume 2A: Instruction Set Reference Manual A–M
Intel ® 64 and IA-32 Architecture Software Developer’s Manual
Volume 2B: Instruction Set Reference Manual, N–Z
Intel ® 64 and IA-32 Architecture Software Developer’s Manual
Volume 3A: System Programming Guide
Intel ® 64 and IA-32 Architecture Software Developer’s Manual
Volume 3B: System Programming Guide http://www.intel.com/ products/processor/ manuals/
§
Datasheet 11
Introduction
12 Datasheet
Electrical Specifications
2
2.1
2.2
2.2.1
2.2.2
Electrical Specifications
This chapter describes the electrical characteristics of the processor interfaces and signals. DC electrical characteristics are provided.
Power and Ground Lands
The processor has VCC (power), VTT and VSS (ground) inputs for on-chip power distribution. All power lands must be connected to V
CC
, while all VSS lands must be connected to a system ground plane. The processor VCC lands must be supplied the voltage determined by the Voltage IDentification (VID) lands.
The signals denoted as VTT, provide termination for the front side bus and power to the
I/O buffers. A separate supply must be implemented for these lands, that meets the
V
TT
specifications outlined in Table 5 .
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings. This may cause voltages on power planes to sag below their minimum specified values if bulk decoupling is not adequate. Larger bulk storage (C
BULK
), such as electrolytic or aluminum-polymer capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. Similarly, they act as a storage well for current when entering an idle condition from a running condition. The motherboard must be designed to ensure that the voltage provided to the processor remains within the specifications
listed in Table 5 . Failure to do so can result in timing violations or reduced lifetime of
the component.
V
CC
Decoupling
V
CC
regulator solutions need to provide sufficient decoupling capacitance to satisfy the processor voltage specifications. This includes bulk capacitance with low effective series resistance (ESR) to keep the voltage rail within specifications during large swings in load current. In addition, ceramic decoupling capacitors are required to filter high frequency content generated by the front side bus and processor activity. Consult the
Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable
LGA775 Socket for further information.
V
TT
Decoupling
Decoupling must be provided on the motherboard. Decoupling solutions must be sized to meet the expected load. To ensure compliance with the specifications, various factors associated with the power delivery solution must be considered including regulator type, power plane and trace sizing, and component placement. A conservative decoupling solution would consist of a combination of low ESR bulk capacitors and high frequency ceramic capacitors.
Datasheet 13
Electrical Specifications
2.2.3
2.3
FSB Decoupling
The processor integrates signal termination on the die. In addition, some of the high frequency capacitance required for the FSB is included on the processor package.
However, additional high frequency capacitance must be added to the motherboard to properly decouple the return currents from the front side bus. Bulk decoupling must also be provided by the motherboard for proper [A]GTL+ bus operation.
Voltage Identification
The Voltage Identification (VID) specification for the processor is defined by the Voltage
Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable LGA775. The voltage set by the VID signals is the reference VR output voltage to be delivered to the processor VCC pins (see
CC
overshoot specifications). Refer to
for the DC specifications for these signals. Voltages for each processor frequency is provided in
.
Individual processor VID values may be calibrated during manufacturing such that two devices at the same core speed may have different default VID settings. This is
reflected by the VID Range values provided in Table 5 . Refer to the Intel
®
Celeron
Processor 400 Series Specification Update for further details on specific valid core
® frequency and VID values of the processor. Please note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2).
The processor uses six voltage identification signals, VID[6:1], to support automatic selection of power supply voltages.
specifies the voltage level corresponding to the state of VID[6:1]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is empty (VID[6:1] = 111111), or the voltage regulation circuit cannot supply the voltage that is requested, it must disable itself. The Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and
Transportable LGA775 defines VID [7:0], VID7 and VID0 are not used on the processor; VID0 and VID7 is strapped to V
SS
on the processor package. VID0 and VID7 must be connected to the VR controller for compatibility with future processors.
The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V
CC
). This will represent a DC shift in the load line. It should be noted that a low-to-high or high-to-low voltage state change may result in as many VID transitions as necessary to reach the target core voltage.
Transitions above the specified VID are not permitted.
Table 5 includes VID step sizes
and DC shift ranges. Minimum and maximum voltages must be maintained as shown in
Figure 1 as measured across the VCC_SENSE and VSS_SENSE lands.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for dynamic VID transitions are included in Table 5
and Table 6 . Refer to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop
and Transportable LGA775 for further details.
14 Datasheet
Electrical Specifications
Table 2.
VID
6
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID
5
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Voltage Identification Definition
VID
4
0
0
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
VID
3
0
0
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
VID
2
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
VID
6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VID
1
1
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
V
CC_MAX
1.1500
1.1625
1.1750
1.1875
1.2000
1.2125
1.2250
1.0500
1.0625
1.0750
1.0875
1.1000
1.1125
1.1250
1.1375
0.9500
0.9625
0.9750
0.9875
1.0000
1.0125
1.0250
1.0375
0.8500
0.8625
0.8750
0.8875
0.9000
0.9125
0.9250
0.9375
VID
5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VID
1
0
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
V
CC_MAX
1.5375
1.5500
1.5625
1.5750
1.5875
1.6000
OFF
1.4375
1.4500
1.4625
1.4750
1.4875
1.5000
1.5125
1.5250
1.3375
1.3500
1.3625
1.3750
1.3875
1.4000
1.4125
1.4250
1.2375
1.2500
1.2625
1.2750
1.2875
1.3000
1.3125
1.3250
VID
2
1
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
VID
3
0
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
0
0
1
0
1
1
VID
4
0
0
0
0
0
0
0
1
0
1
1
1
1
1
1
0
1
0
0
0
0
0
0
1
0
1
1
1
1
1
1
Datasheet 15
Electrical Specifications
2.4
Table 3.
2.5
Market Segment Identification (MSID)
The MSID[1:0] signals may be used as outputs to determine the Market Segment of
the processor. Table 3 provides details regarding the state of MSID[1:0]. A circuit can
be used to prevent 130 W TDP processors from booting on boards optimized for 65 W
TDP.
Market Segment Selection Truth Table for MSID[1:0]
1, 2, 3, 4
MSID1
0
0
1
1
MSID0
0
1
0
1
Description
Intel ® Core™2 Duo desktop processor E6000 and E4000 series, Intel ®
Core™2 Extreme processor X6800, Intel ® Celeron ® Processor 400
Reserved
Reserved
Intel ® Core™2 Extreme Quad-Core Processor QX6700D and Intel ® Core™2
Quad Processor Q6000 series
NOTES:
1. The MSID[1:0] signals are provided to indicate the Market Segment for the processor and may be used for future processor compatibility or for keying. Circuitry on the motherboard may use these signals to identify the processor installed.
2. These signals are not connected to the processor die.
3. A logic 0 is achieved by pulling the signal to ground on the package.
4. A logic 1 is achieved by leaving the signal as a no connect on the package.
Reserved, Unused and TESTHI Signals
All RESERVED lands must remain unconnected. Connection of these lands to V
V
TT processor and the location of all RESERVED lands.
CC
, V
SS
,
, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors. See
Chapter 4 for a land listing of the
In a system level design, on-die termination has been included by the processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs should be left as no connects as GTL+ termination is provided on the processor silicon.
for details on GTL+ signals that do not include on-die termination.
Unused active high inputs, should be connected through a resistor to ground (V
SS
).
Unused outputs can be left unconnected, however this may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ± 20% of the impedance of the motherboard trace for front side bus signals. For unused GTL+ input or I/O signals, use pull-up resistors of the same value as the on-die termination resistors (R
TT
). For details see
TAP and CMOS signals do not include on-die termination. Inputs and utilized outputs must be terminated on the motherboard. Unused outputs may be terminated on the motherboard or left unconnected. Note that leaving unused outputs unterminated may interfere with some TAP functions, complicate debug probing, and prevent boundary scan testing.
All TESTHI[13:0] lands should be individually connected to V
TT which matches the nominal trace impedance.
via a pull-up resistor
16 Datasheet
Electrical Specifications
2.6
2.6.1
The TESTHI signals may use individual pull-up resistors or be grouped together as detailed below. A matched resistor must be used for each group:
• TESTHI[1:0]
• TESTHI[7:2]
• TESTHI8/FC42 – cannot be grouped with other TESTHI signals
• TESTHI9/FC43 – cannot be grouped with other TESTHI signals
• TESTHI10 – cannot be grouped with other TESTHI signals
• TESTHI11 – cannot be grouped with other TESTHI signals
• TESTHI12/FC44 – cannot be grouped with other TESTHI signals
• TESTHI13 – cannot be grouped with other TESTHI signals
However, using boundary scan test will not be functional if these lands are connected together. For optimum noise margin, all pull-up resistor values used for TESTHI[13:0] lands should have a resistance value within ± 20% of the impedance of the board transmission line traces. For example, if the nominal trace impedance is 50 Ω, then a value between 40 Ω and 60 Ω should be used.
Voltage and Current Specification
Absolute Maximum and Minimum Ratings
Table 4 specifies absolute maximum and minimum ratings only and lie outside the
functional limits of the processor. Within functional operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits, but within the absolute maximum and minimum ratings, the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time then, when returned to conditions within the functional operating condition limits, it will either not function, or its reliability will be severely degraded.
Although the processor contains protective circuitry to resist damage from static electric discharge, precautions should always be taken to avoid high static voltages or electric fields.
Datasheet 17
Electrical Specifications
Table 4.
Absolute Maximum and Minimum Ratings
Symbol Parameter Min Max Unit Notes 1, 2
V
V
CC
TT
Core voltage with respect to V
SS
FSB termination voltage with respect to V
SS
–0.3
–0.3
1.55
1.55
V
V
-
-
T
C
Processor case temperature
See
–40
See
85
°C -
T
STORAGE
Processor storage temperature °C 3, 4, 5
NOTES:
1.
For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.
2.
3.
4.
5.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive a clock, and no lands can be connected to a voltage bias.
Storage within these limits will not affect the long-term reliability of the device. For functional operation, refer to the processor case temperature specifications.
This rating applies to the processor and does not include any tray or packaging.
Failure to adhere to this specification can affect the long term reliability of the processor.
18 Datasheet
Electrical Specifications
2.6.2
DC Voltage and Current Specification
Table 5.
Voltage and Current Specifications
Symbol Parameter Min Typ Max Unit Notes 2, 15
VID Range
V
V
V
I
V
CC
CC_BOOT
CCPLL
CC
TT
VID
Processor Number
450
440
430
420
Core V
CC
2.2 GHz
2.0 GHz
1.8 GHz
1.6 GHz
Default V
CC
voltage for initial power up
PLL V
CC
Processor Number
450
440
430
420
I
CC
for
775_VR_CONFIG_06
2.2 GHz
2.0 GHz
1.8 GHz
1.6 GHz
FSB termination voltage
(DC + AC specifications)
1.0000
—
- 5%
—
1.14
—
1.10
1.50
—
1.20
1.3375
and
—
+ 5%
35
35
35
35
1.26
V
V
V
A
V
3
4, 5, 6
7
8
VTT_OUT_LEFT and
VTT_OUT_RIGHT
I
CC
I
I
I
TT
CC_VCCPLL
CC_GTLREF
DC Current that may be drawn from
VTT_OUT_LEFT and VTT_OUT_RIGHT per pin
— — 580 mA 9
I
CC
for V
TT
supply before V
CC
stable
I
CC
for V
TT
supply after V
CC
stable
I
CC for PLL land
I
CC
for GTLREF
—
—
—
—
—
—
4.5
4.6
130
200
A mA
μA
10
NOTES:
1.
Unless otherwise noted, all specification in this table are based on estimates and simulation or empirical data. These specifications will be updated with characterized data
2.
3.
from silicon measurements at a later date.
Adherence to the voltage specification for the processor are required to ensure reliable processor operation.
Each processor is programmed with a maximum valid voltage identification value (VID),
4.
5.
6.
7.
which is set at manufacturing and can not be altered. Individual maximum VID values are calibrated during manufacturing such that two processors at the same frequency may have different settings within the VID range. Please note this differs from the VID employed by the processor during a power management event (Thermal Monitor 2).
These voltages are targets only. A variable voltage source should exist on systems in the
event that a different voltage is required. See Section 2.3
for more information.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE lands at the socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the oscilloscope probe.
Refer to
Figure 1 for the minimum, typical, and maximum V
CC given current. The processor should not be subjected to any V
CC
and I
CC
allowed for a
combination wherein V
CC
I
CC_MAX
exceeds V
CC_MAX
for a given current.
specification is based on the V
CC_MAX loadline. Refer to
f or details.
Datasheet 19
Electrical Specifications
Table 6.
8.
9.
10.
11.
12.
V
TT
must be provided via a separate voltage source and not be connected to V specification is measured at the land.
Baseboard bandwidth is limited to 20 MHz.
This is maximum total current drawn from V
CC
. This
TT
plane by only the processor. This specification does not include the current coming from R
TT
(through the signal line). Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines For
Desktop LGA775 Socket to determine the total I
TT
drawn by the system. This parameter is based on design characterization and is not tested.
This is maximum total current drawn from V
TT
plane by only the processor. This specification does not include the current coming from R
TT
(through the signal line). Refer to the Voltage Regulator-Down (VRD) 11 Design Guide For Desktop and Transportable
LGA775 to determine the total I
TT characterization and is not tested.
drawn by the system. This parameter is based on design
Adherence to the voltage specifications for the processor are required to ensure reliable processor operation.
V
CC
Static and Transient Tolerance
Voltage Deviation from VID Setting (V) 1, 2, 3, 4
I
CC
(A)
Maximum Voltage
2.30 mΩ
Typical Voltage
2.40 mΩ
Minimum Voltage
2.50mΩ
0
5
10
15
20
25
30
35
0.000
-0.012
-0.023
-0.035
-0.046
-0.058
-0.069
-0.081
-0.019
-0.031
-0.043
-0.055
-0.067
-0.079
-0.091
-0.103
-0.038
-0.051
-0.063
-0.076
-0.088
-0.101
-0.113
-0.126
NOTES:
1.
2.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
.
This table is intended to aid in reading discrete points on Figure 1 .
3.
4.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 for socket loadline guidelines and VR implementation details.
Adherence to this loadline specification is required to ensure reliable processor operation.
20 Datasheet
Electrical Specifications
Figure 1.
2.6.3
Table 7.
V
CC
Static and Transient Tolerance
Icc [A]
VID - 0.075
VID - 0.088
VID - 0.100
VID - 0.113
VID - 0.125
VID - 0.138
VID - 0.150
VID - 0.000
0
VID - 0.013
VID - 0.025
VID - 0.038
VID - 0.050
VID - 0.063
Vcc Typical
10
Vcc Minimum
20
Vcc Maximum
30
NOTES:
1.
2.
The loadline specification includes both static and transient limits except for overshoot allowed as shown in
.
This loadline specification shows the deviation from the VID set point.
3.
The loadlines specify voltage limits at the die measured at the VCC_SENSE and
VSS_SENSE lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 for socket loadline guidelines and VR implementation details.
V
CC
Overshoot
The processor can tolerate short transient overshoot events where V
CC
exceeds the VID voltage when transitioning from a high to low current load condition. This overshoot cannot exceed VID + V
OS_MAX
(V
OS_MAX
is the maximum allowable overshoot voltage).
The time duration of the overshoot event must not exceed T
OS_MAX
(T
OS_MAX
is the maximum allowable time duration above VID). These specifications apply to the processor die voltage as measured across the VCC_SENSE and VSS_SENSE lands.
V
CC
Overshoot Specifications
Symbol Parameter Min Max Unit Figure Notes
V
T
OS_MAX
OS_MAX
Magnitude of V
CC
VID
overshoot above
Time duration of V
CC
VID
overshoot above
—
—
50
25 mV
μs
1
NOTES:
1.
Adherence to these specifications is required to ensure reliable processor operation.
Datasheet 21
Figure 2.
V
CC
Overshoot Example Waveform
Example Overshoot Waveform
V
OS
VID + 0.050
Electrical Specifications
VID - 0.000
2.6.4
2.7
0 5
T
OS
10
Time [us]
15
T
OS
: Overshoot time above VID
V
OS
: Overshoot above VID
20 25
NOTES:
1.
2.
V
T
OS
is measured overshoot voltage.
OS
is measured time duration above VID.
Die Voltage Validation
Overshoot events on processor must meet the specifications in
across the VCC_SENSE and VSS_SENSE lands. Overshoot events that are < 10 ns in duration may be ignored. These measurements of processor die level overshoot must be taken with a bandwidth limited oscilloscope set to a greater than or equal to
100 MHz bandwidth limit.
Signaling Specifications
Most processor Front Side Bus signals use Gunning Transceiver Logic (GTL+) signaling technology. This technology provides improved noise margins and reduced ringing through low voltage swings and controlled edge rates.
Platforms implement a termination voltage level for GTL+ signals defined as V
TT
. Because platforms implement
CC
and V separate power planes for each processor (and chipset), separate V
TT supplies are necessary. This configuration allows for improved noise tolerance as processor frequency increases. Speed enhancements to data and address busses have caused signal integrity considerations and platform design methods to become even more critical than with previous processor families.
The GTL+ inputs require a reference voltage (GTLREF) which is used by the receivers to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 14 for GTLREF specifications). Termination resistors (R
TT
GTL+ signals are provided on the processor silicon and are terminated to V chipsets will also provide on-die termination; thus, eliminating the need to terminate the bus on the motherboard for most GTL+ signals.
TT
) for
. Intel
22 Datasheet
Electrical Specifications
2.7.1
Table 8.
FSB Signal Groups
The front side bus signals have been combined into groups by buffer type. GTL+ input signals have differential input buffers, which use GTLREF[1:0] as a reference level. In this document, the term “GTL+ Input” refers to the GTL+ input group as well as the
GTL+ I/O group when receiving. Similarly, “GTL+ Output” refers to the GTL+ output group as well as the GTL+ I/O group when driving.
With the implementation of a source synchronous data bus comes the need to specify two sets of timing parameters. One set is for common clock signals which are dependent upon the rising edge of BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals which are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0. Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time during the
clock cycle. Table 8 identifies which signals are common clock, source synchronous,
and asynchronous.
FSB Signal Groups (Sheet 1 of 2)
Signal Group
GTL+ Common
Clock Input
GTL+ Common
Clock I/O
Type
Synchronous to
BCLK[1:0]
Synchronous to
BCLK[1:0]
Signals 1
BPRI#, DEFER#, RESET#, RS[2:0]#, TRDY#
ADS#, BNR#, BPM[5:0]#, BR0#, DBSY#, DRDY#, HIT#,
HITM#, LOCK#
GTL+ Source
Synchronous I/O
GTL+ Strobes
CMOS
Open Drain
Output
Open Drain
Input/Output
FSB Clock
Synchronous to assoc. strobe
Signals
REQ[4:0]#, A[16:3]# 3
A[35:17]#
3
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
ADSTB0#
ADSTB1#
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Synchronous to
BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
STPCLK#, PWRGOOD, TCK, TDI, TMS, TRST#,
BSEL[2:0], VID[6:1]
FERR#/PBE#, IERR#, THERMTRIP#, TDO
Clock
PROCHOT# 4
BCLK[1:0], ITP_CLK[1:0] 2
Datasheet 23
Electrical Specifications
.
Table 8.
Table 9.
Table 10.
FSB Signal Groups (Sheet 2 of 2)
Signal Group
Power/Other
Type Signals 1
VCC, VTT, VCCA, VCCIOPLL, VCCPLL, VSS, VSSA,
GTLREF[1:0], COMP[8,3:0], RESERVED, TESTHI[13:0],
VCC_SENSE, VCC_MB_REGULATION, VSS_SENSE,
VSS_MB_REGULATION, DBR# 2 , VTT_OUT_LEFT,
VTT_OUT_RIGHT, VTT_SEL, FCx, PECI
NOTES:
1.
2.
Refer to
In processor systems where no debug port is implemented on the system board, these signals are used to support a debug port interposer. In systems with the debug port implemented on the system board, these signals are no connects.
3.
4.
The value of these signals during the active-to-inactive edge of RESET# defines the
processor configuration options. See Section 6.1
for details.
PROCHOT# signal type is open drain output and CMOS input.
Signal Characteristics
Signals with R
TT
A[35:3]#, ADS#, ADSTB[1:0]#, BNR#, BPRI#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#,
DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#,
HITM#, LOCK#, PROCHOT#, REQ[4:0]#,
RS[2:0]#, TRDY#
Signals with No R
TT
A20M#, BCLK[1:0], BSEL[2:0],
COMP[8,3:0], IGNNE#, INIT#, ITP_CLK[1:0],
LINT0/INTR, LINT1/NMI, PWRGOOD,
RESET#, SMI#, STPCLK#, TESTHI[13:0],
VID[6:0], GTLREF[1:0], TCK, TDI, TMS,
TRST#
Open Drain Signals 1
THERMTRIP#, FERR#/PBE#, IERR#, BPM[5:0]#,
BR0#, TDO, VTT_SEL, FCx
NOTES:
1.
Signals that do not have R
TT
, nor are actively driven to their high-voltage level.
Signal Reference Voltages
GTLREF
BPM[5:0]#, RESET#, BNR#, HIT#, HITM#, BR0#,
A[35:0]#, ADS#, ADSTB[1:0]#, BPRI#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,
TRDY#
V
TT
/2
A20M#, LINT0/INTR, LINT1/NMI,
IGNNE#, INIT#, PROCHOT#,
PWRGOOD 1 , SMI#, STPCLK#, TCK
TDI 1 , TMS 1 , TRST# 1
1 ,
NOTE:
1.
These signals also have hysteresis added to the reference voltage. See
for more information.
24 Datasheet
Electrical Specifications
2.7.2
2.7.3
Table 11.
Table 12.
CMOS and Open Drain Signals
Legacy input signals such as A20M#, IGNNE#, INIT#, SMI#, and STPCLK# use CMOS input buffers. All of the CMOS and Open Drain signals are required to be asserted/deasserted for at least four BCLKs for the processor to recognize the proper signal state.
See
for the DC specifications. See Section 6.2
for additional timing requirements for entering and leaving the low power states.
Processor DC Specifications
The processor DC specifications in this section are defined at the processor core (pads) unless otherwise stated. All specifications apply to all frequencies and cache sizes unless otherwise stated.
GTL+ Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OH
I
OL
I
LI
I
LO
R
ON
Parameter
Input Low Voltage
Input High Voltage
Output High Voltage
Output Low Current
Input Leakage Current
Output Leakage Current
Buffer On Resistance
Min
-0.10
GTLREF + 0.10
V
TT
– 0.10
N/A
N/A
N/A
10
Max
GTLREF – 0.10
V
TT
+ 0.10
V
TT
V
TT_MAX
/
[(R
TT_MIN
)+(R
ON_MIN
)]
± 100
± 100
13
Unit Notes
V
V
V
A
µA
µA
Ω
2, 5
3, 4, 5
4, 5
-
6
7
1
5.
6.
7.
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical
3.
low value.
V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
4.
V
IH
and V
OH
may experience excursions above V
TT
. However, input signal drivers must comply with the signal quality specifications.
The V
TT
referred to in these specifications is the instantaneous V
TT
Leakage to V
Leakage to V
SS
with land held at V
TT
TT
.
with land held at 300 mV.
.
Open Drain and TAP Output Signal Group DC Specifications
Symbol
V
OL
I
OL
I
LO
Parameter
Output Low Voltage
Output Low Current
Output Leakage Current
Min
0
16
N/A
Max
0.20
50
± 200
Unit Notes 1
V mA
µA
-
2
3
NOTES:
1.
2.
3.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Measured at V
TT
* 0.2.
For Vin between 0 and V
OH
Datasheet 25
Electrical Specifications
.
Table 13.
CMOS Signal Group DC Specifications
Symbol
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
I
LI
I
LO
Parameter
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Current
Output High Current
Input Leakage Current
Output Leakage Current
Min
-0.10
V
TT
* 0.70
-0.10
0.90 * V
TT
1.70
1.70
N/A
N/A
Max
V
TT
* 0.30
V
TT
+ 0.10
V
TT
* 0.10
V
TT
+ 0.10
4.70
4.70
± 100
± 100
Unit Notes 1 mA mA
µA
µA
V
V
V
V
2, 3
4, 5, 3
3
6, 5, 3
3, 7
3, 7
8
9
3.
4.
5.
6.
7.
8.
9.
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
The V
V
V
I
IH
IH
TT
referred to in these specifications refers to instantaneous V
and V
OH
may experience excursions above V
All outputs are open drain.
OL is measured at 0.10 * V
Leakage to V
Leakage to V
TT
. .
TT.
I
OH is measured at 0.90 * V
SS
with land held at V
TT
TT
.
with land held at 300 mV
TT.
TT
.
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
26 Datasheet
Electrical Specifications
2.7.3.1
Table 14.
GTL+ Front Side Bus Specifications
In most cases, termination resistors are not required as these are integrated into the
processor silicon. See Table 9
for details on which GTL+ signals do not include on-die termination.
Valid high and low levels are determined by the input buffers by comparing with a reference voltage called GTLREF.
Table 14 lists the GTLREF specifications for both
50 Ohm and 60 Ohm platforms. The GTL+ reference voltage (GTLREF) should be generated on the system board using high precision voltage divider circuits.
GTL+ Bus Voltage Definitions
Symbol Parameter
GTLREF_PU GTLREF pull up resistor
GTLREF_PD GTLREF pull down resistor
R
TT
Termination Resistance
60 Ω Platform termination
Resistance
COMP[3:0]
50 Ω Platform termination
Resistance
COMP8
60 Ω Platform termination
Resistance
50 Ω Platform termination
Resistance
Min
124 * 0.99
210 * 0.99
45
Typ
124
210
50
Max
124 * 1.01
210 * 1.01
55
60.4 * 0.99
60.4
60.4 * 1.01
Units Notes 1
Ω
Ω
Ω
2, 4
3
Ω 4
49.9 * 0.99
49.9
49.9 * 1.01
30.1 * 0.99
30.1
30.1 * 1.01
24.9 * 0.99
24.9
24.9 * 1.01
Ω
Ω
Ω
4
4
4
NOTES:
1.
2.
3.
4.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
GTLREF is to be generated from V
TT
by a voltage divider of 1% resistors (one divider for each GTLEREF land).
R
TT
is the on-die termination resistance measured at V
COMP8 resistors are to V
SS
.
TT
/3 of the GTL+ output driver.
COMP resistance must be provided on the system board with 1% resistors. COMP[3:0] and
Datasheet 27
Electrical Specifications
2.8
2.8.1
Table 15.
Clock Specifications
Front Side Bus Clock (BCLK[1:0]) and Processor Clocking
BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor. As in previous generation processors, the processor’s core frequency is a multiple of the BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its
default ratio during manufacturing. Refer to Table 15
for the processor supported ratios.
The processor uses a differential clocking implementation. For more information on the processor clocking, contact your Intel field representative. Platforms using a CK505
Clock Synthhesizer/Driver should comply with the specifications in
.
Platforms using a CK410 Clock Synthesizer/Driver should comply with the specifications
Core Frequency to FSB Multiplier Configuration
Multiplication of System
Core Frequency to FSB
Frequency
1/6
1/7
1/8
1/9
1/10
1/11
1/12
1/13
1/14
Core Frequency
(200 MHz BCLK/800 MHz
FSB)
1.20 GHz
1.40 GHz
1.60 GHz
1.80 GHz
2 GHz
2.2 GHz
2.4 GHz
2.6 GHz
2.8 GHz
Notes 1, 2
-
-
-
-
-
-
-
-
-
NOTES:
1.
Individual processors operate only at or below the rated frequency.
2.
Listed frequencies are not necessarily committed production frequencies.
28 Datasheet
Electrical Specifications
2.8.2
Table 16.
2.8.3
FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock
defines the possible combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset, and clock synthesizer. All agents must operate at the same frequency.
The processor will operate at an 800 MHz FSB frequency (selected by a 200 MHz
BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.
BSEL[2:0] Frequency Table for BCLK[1:0]
BSEL2
H
H
L
H
H
L
L
L
BSEL1
H
L
H
H
L
L
L
H
BSEL0
H
H
L
L
L
L
H
H
FSB Frequency
RESERVED
RESERVED
RESERVED
200 MHz
RESERVED
RESERVED
RESERVED
RESERVED
Phase Lock Loop (PLL) and Filter
An on-die PLL filter solution will be implemented on the processor. The VCCPLL input is used for the PLL. Refer to
Table 5 for DC specifications.
Datasheet 29
Electrical Specifications
2.8.4
Table 17.
Figure 3.
BCLK[1:0] Specifications (CK505 based Platforms)
Front Side Bus Differential BCLK Specifications
Symbol
V
L
V
H
V
CROSS(abs)
ΔV
CROSS
V
OS
V
US
V
SWING
I
LI
Cpad
Parameter
Input Low Voltage
Input High Voltage
Absolute Crossing Point
Range of Crossing Points
Overshoot
Undershoot
Differential Output Swing
Input Leakage Current
Pad Capacitance
Min Typ
-0.30
N/A
0.300
N/A
N/A N/A
-0.300 N/A
0.300
-5
.95
N/A
N/A
1.2
N/A
N/A
N/A
N/A
Max
N/A
1.15
0.550
0.140
1.4
N/A
N/A
5
1.45
V
V
V
μA pF
V
V
V
V
Unit Figure Notes 1
4
4
2,4,6
-
5
5
6
8
3.
4.
5.
1.
2.
6.
7.
8.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
"Steady state" voltage, not including overshoot or undershoot.
Overshoot is defined as the absolute value of the maximum voltage. Undershoot is defined as the absolute value of the minimum voltage.
Measurement taken from differential waveform.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
Cpad includes die capacitance only. No package parasitics are included.
Differential Clock Waveform
CLK 0
V
CROSS
Median + 75 mV
V
CROSS median
V
CROSS
Median - 75 mV
CLK 1
V
CROSS
Max
500 mV
V
CROSS
Min
300 mV
High Time
Period
Low Time
V
CROSS median
30 Datasheet
Electrical Specifications
Figure 4.
Differential Clock Crosspoint Specification
650
600
550
500
450
400
350
550 + 0.5 (VHavg - 700)
550 mV
250 + 0.5 (VHavg - 700)
300
250
250 mV
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Figure 5.
Differential Measurements
Slew_ris e
+150 mV
0.0 V
-150 mV
D iff
V_swing
Slew _fall
+150 mV
0.0V
- 150 mV
Datasheet 31
Electrical Specifications
2.8.5
BCLK[1:0] Specifications (CK410 based Platforms)
Table 18.
Symbol
V
L
V
H
Front Side Bus Differential BCLK Specifications
Parameter
Input Low Voltage
Input High Voltage
Min
-0.150
0.660
Typ
0.00
0
0.70
0
V
CROSS(abs)
Absolute Crossing
Point
0.250
N/A
V
CROSS(rel)
Relative Crossing Point
0.250 +
0.5(
V
Havg
– 0.700)
N/A
N/A
N/A
Max
N/A
0.850
0.550
0.550 +
0.5(
V
Havg
– 0.700)
0.140
ΔV
CROSS
V
OS
V
US
V
RBM
V
TM
Range of Crossing
Points
Overshoot
Undershoot
Ringback Margin
Threshold Region
N/A N/A
-0.300 N/A
V
H
+ 0.3
N/A
0.200
N/A N/A
V
CROSS
– 0.100
N/A V
CROSS
+ 0.100
Unit Figure Notes 1
V
V
V
V
V
V
V
V
V
-
-
2, 8
3, 8, 9
-
6
7
4
5
3.
4.
5.
6.
NOTES:
1.
2.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of
BCLK0 equals the falling edge of BCLK1.
V
Havg
is the statistical average of the V
H
measured by the oscilloscope.
Overshoot is defined as the absolute value of the maximum voltage.
7.
8.
Undershoot is defined as the absolute value of the minimum voltage.
Ringback Margin is defined as the absolute voltage difference between the maximum
Rising Edge Ringback and the maximum Falling Edge Ringback.
Threshold Region is defined as a region entered around the crossing point voltage in which the differential receiver switches. It includes input threshold hysteresis.
The crossing point must meet the absolute and relative crossing point specifications
9.
simultaneously.
V
Havg
can be measured directly using “Vtop” on Agilent* oscilloscopes and “High” on
Tektronix* oscilloscopes.
32 Datasheet
Electrical Specifications
Figure 6.
Differential Clock Waveform
Threshold
Region
Tph
BCLK1
BCLK0
V
CROSS (ABS
) V
CROSS (ABS
)
Tpl
Tp
Tp = T1: BCLK[1:0] period
T2: BCLK[1:0] period stability (not shown)
Tph = T3: BCLK[1:0] pulse high time
Tpl = T4: BCLK[1:0] pulse low time
T5: BCLK[1:0] rise time through the threshold region
T6: BCLK[1:0] fall time through the threshold region
Ringback
Margin
Overshoot
VH
Rising Edge
Ringback
Falling Edge
Ringback
VL
Undershoot
Figure 7.
Differential Clock Crosspoint Specification
650
600
550
500
450
400
350
300
250
550 + 0.5 (VHavg - 700)
250 mV
550 mV
250 + 0.5 (VHavg - 700)
200
660 670 680 690 700 710 720 730 740 750 760 770 780 790 800 810 820 830 840 850
VHavg (mV)
Datasheet 33
Electrical Specifications
2.9
Table 19.
PECI DC Specifications
PECI is an Intel proprietary one-wire interface that provides a communication channel between Intel processors (may also include chipset components in the future) and external thermal monitoring devices. The processor contains Digital Thermal Sensors
(DTS) distributed throughout die. These sensors are implemented as analog-to-digital converters calibrated at the factory for reasonable accuracy to provide a digital representation of relative processor temperature. PECI provides an interface to relay the highest DTS temperature within a die to external management devices for thermal/ fan speed control. More detailed information is available in the Platform Environment
Control Interface (PECI) Specification.
PECI DC Electrical Limits
Symbol
V in
V hysteresis
V n
V p
I
I source
I
V
I sink leak+ leak-
C bus noise
Definition and Conditions
Input Voltage Range
Hysteresis
Negative-edge threshold voltage
Positive-edge threshold voltage
High level output source
(V
OH
= 0.75 * V
TT)
Low level output sink
(V
OL
= 0.25 * V
TT
)
High impedance state leakage to V
TT
High impedance leakage to GND
Bus capacitance per node
Signal noise immunity above 300 MHz
Min
-0.15
0.1 * V
TT
0.275 * V
TT
0.550 * V
TT
-6.0
0.5
N/A
N/A
—
0.1 * V
TT
Max
V
TT
+ 0.15
—
0.500 * V
TT
0.725 * V
TT
N/A
1.0
50
10
10
—
Units Notes
V
V
V
V 3 mA mA
µA
µA pF
V p-p
2
2
4
NOTE:
1.
2.
3.
4.
V
TT
supplies the PECI interface. PECI behavior does not affect V
TT
min/max specifications.
The leakage specification applies to powered devices on the PECI bus.
The input buffers use a Schmitt-triggered input design for improved noise immunity.
One node is counted for each client and one node for the system host. Extended trace lengths might appear as additional nodes.
§
34 Datasheet
Package Mechanical Specifications
3 Package Mechanical
Specifications
Figure 8.
The processor is packaged in a Flip-Chip Land Grid Array (FC-LGA6) package that interfaces with the motherboard via an LGA775 socket. The package consists of a processor core mounted on a substrate land-carrier. An integrated heat spreader (IHS) is attached to the package substrate and core and serves as the mating surface for
processor component thermal solutions, such as a heatsink. Figure 8
shows a sketch of the processor package components and how they are assembled together. Refer to the
LGA775 Socket Mechanical Design Guide for complete details on the LGA775 socket.
The package components shown in Figure 8 include the following:
• Integrated Heat Spreader (IHS)
• Thermal Interface Material (TIM)
• Processor core (die)
• Package substrate
• Capacitors
Processor Package Assembly Sketch
TIM
Substrate
IHS
Core (die)
Capacitors
LGA775 Socket
System Board
3.1
NOTE:
1.
Socket and motherboard are included for reference and are not part of processor package.
Package Mechanical Drawing
The package mechanical drawings are shown in
and
include dimensions necessary to design a thermal solution for the processor. These dimensions include:
• Package reference with tolerances (total height, length, width, etc.)
• IHS parallelism and tilt
• Land dimensions
• Top-side and back-side component keep-out dimensions
• Reference datums
• All drawing dimensions are in mm [in].
• Guidelines on potential IHS flatness variation with socket load plate actuation and installation of the cooling solution is available in the processor Thermal and
Mechanical Design Guidelines.
Datasheet 35
Figure 9.
Processor Package Drawing Sheet 1 of 3
Package Mechanical Specifications
36 Datasheet
Package Mechanical Specifications
Figure 10.
Processor Package Drawing Sheet 2 of 3
Datasheet 37
Figure 11.
Processor Package Drawing Sheet 3 of 3
Package Mechanical Specifications
38 Datasheet
Package Mechanical Specifications
3.2
3.3
.
Table 20.
3.4
Table 21.
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or land-side of the package substrate. See Figure 9 and
for keep-out zones. The location and quantity of package capacitors may change due to manufacturing efficiencies but will remain within the component keep-in.
Package Loading Specifications
provides dynamic and static load specifications for the processor package.
These mechanical maximum load limits should not be exceeded during heatsink assembly, shipping conditions, or standard use condition. Also, any mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum loading specification must be maintained by any thermal and mechanical solutions.
Processor Loading Specifications
Parameter
Static
Dynamic
Minimum
80 N [17 lbf]
-
Maximum
311 N [70 lbf]
756 N [170 lbf]
Notes
1, 2, 3
1, 3, 4
NOTES:
1.
These specifications apply to uniform compressive loading in a direction normal to the processor IHS.
2.
3.
4.
This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the minimum specified load on the processor package.
These specifications are based on limited testing for design characterization. Loading limits are for the package only and do not include the limits of the processor socket.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load requirement.
Package Handling Guidelines
includes a list of guidelines on package handling in terms of recommended maximum loading on the processor IHS relative to a fixed substrate. These package handling loads may be experienced during heatsink removal.
Package Handling Guidelines
Parameter
Shear
Tensile
Torque
Maximum Recommended
311 N [70 lbf]
111 N [25 lbf]
3.95 N-m [35 lbf-in]
Notes
1, 4
2, 4
3, 4
NOTES:
1.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2.
3.
A tensile load is defined as a pulling load applied to the IHS in a direction normal to the
IHS surface.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal
4.
to the IHS top surface.
These guidelines are based on limited testing for design characterization.
Datasheet 39
Package Mechanical Specifications
3.5
3.6
Package Insertion Specifications
The processor can be inserted into and removed from a LGA775 socket 15 times. The socket should meet the LGA775 requirements detailed in the LGA775 Socket
Mechanical Design Guide.
Processor Mass Specification
The typical mass of the processor is 21.5 g [0.76 oz]. This mass [weight] includes all the components that are included in the package.
3.7
Table 22.
Processor Materials
lists some of the package components and associated materials.
Processor Materials
Component
Integrated Heat Spreader (IHS)
Substrate
Substrate Lands
Material
Nickel Plated Copper
Fiber Reinforced Resin
Gold Plated Copper
3.8
Processor Markings
Figure 12 shows the topside markings on the processor. This diagram is to aid in the
identification of the processor.
Figure 12.
Processor Top-Side Marking Example
C E L E R O N ®
S L x x x [ C O O ]
2 . 0 0 G H Z / 5 1 2 / 8 0 0 / 0 6
[ F P O ] e 4
A T P O
S / N
40 Datasheet
Package Mechanical Specifications
3.9
Processor Land Coordinates
Figure 13 shows the top view of the processor land coordinates. The coordinates are
referred to throughout the document to identify processor lands.
.
Figure 13.
Processor Land Coordinates and Quadrants, Top View
V
CC
/
V
SS
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
W
V
U
AB
AA
Y
T
R
P
N
M
L
H
G
F
K
J
E
D
C
B
A
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
Preliminary
Socket 775
Quadrants
Top View
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
V
TT
/ Clocks Data
§
AN
AM
AL
AK
AJ
AH
AG
AF
AE
AD
AC
H
G
F
K
J
N
M
L
E
D
C
B
A
T
R
P
AB
AA
Y
W
V
U
Address/
Common Clock/
Async
Datasheet 41
Package Mechanical Specifications
42 Datasheet
Land Listing and Signal Descriptions
4
4.1
Land Listing and Signal
Descriptions
This chapter provides the processor land assignment and signal descriptions.
Processor Land Assignments
This section contains the land listings for the processor. The land-out footprint is shown
. These figures represent the land-out arranged by land number and they show the physical location of each signal on the package land array
(top view).
Table 23 is a listing of all processor lands ordered alphabetically by land
is also a listing of all processor lands; the ordering is by land number.
Datasheet 43
Land Listing and Signal Descriptions
C
B
A
F
E
D
V
U
Y
W
T
R
P
N
M
L
K
J
AH
AG
AF
AE
AM
AL
AK
AJ
AD
AC
AB
AA
AN
Figure 14.
land-out Diagram (Top View – Left Side)
30 29 28 27 26 25 24 23 22 21
VCC VCC VSS VSS VCC VCC VSS VSS VCC VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
H
G
20
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
19
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
18
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
17
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
16
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VCC
VCC VCC VCC VCC VCC VCC FC34 FC31 VCC
BSEL1
BSEL2 BSEL0 BCLK1 TESTHI4 TESTHI
VTT
FC15
RSVD
FC26
VTT
VSS VSS VSS
BCLK0 VTT_SEL TESTHI
VSS
VTT
VSS
VTT
VSS
VTT
VSS
TESTHI
3
TESTHI
2
VSS
VSS VSS VSS VSS VSS VSS VSS
TESTHI
6
RESET# D47# D44# DSTBN2# DSTBP2# D35#
TESTHI
7
FC10
RSVD
RSVD
VSS D43#
D45# D42#
D41#
VSS
VSS
D40#
D38#
D39#
VTT DBI2# VSS
VTT
VTT
VTT
30
VTT
VTT
VTT
29
VTT
VTT
VTT
28
VTT
VTT
VTT
27
VTT
VTT
VTT
26
VTT
VTT
VTT
25
VSS VCCPLL D46# VSS
VSS
VSS
VCCIO
PLL
VSS D58#
VSSA D63# D59#
D48#
DBI3#
VSS
FC23
24
VCCA D62# VSS
23 22 21
RSVD
20
VSS
D60#
D61#
19
D57#
VSS
18
VSS
D36#
D37#
VSS
D49#
D54# DSTBP3#
VSS
FC33
D32#
VSS
D34#
RSVD
VSS
FC32
D31#
D30#
D33#
VSS
D51#
D55# D53#
D56# DSTBN3# VSS
17 16 15
15
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
44 Datasheet
Land Listing and Signal Descriptions
Figure 15.
land-out Diagram (Top View – Right Side)
14 13 12 11 10 9
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
8
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC VSS
SKTOCC# VSS
7 6 5
VID_SEL
ECT
VSS_MB_
REGULATION
VCC_MB_
REGULATION
VID7
VSS
VSS
VSS
FC40
VID3
FC8
A35#
VID6
VID1
VSS
A34#
VSS
A29#
VSS
RSVD
A33#
A31#
A27#
VSS
VCC
VCC
VCC
VSS
VSS
VSS
A22#
VSS
A17#
ADSTB1#
A25#
A24#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
A19#
A18#
VSS
A10#
VSS
ADSTB0#
A4#
VSS
A23#
VSS
A16#
A14#
A12#
A9#
VSS
RSVD
RSVD
A32#
A30#
A28#
RSVD
VSS
RSVD
A26#
4
VSS_
SENSE
3
VCC_
SENSE
2
VSS
1
VSS AN
VSS
VID5
VID2 VID0 VSS
VRDSEL PROCHOT# THERMDA
VID4 ITP_CLK0
VSS ITP_CLK1
VSS
BPM0#
THERMDC
BPM1#
AM
AL
AK
AJ
VSS
BPM5#
VSS
FC18
FC36
VSS
FC37
RSVD
BPM3#
BPM4#
VSS
BPM2#
DBR#
IERR#
A21#
A20#
VSS
A15#
A13#
A11#
A8#
VSS
FC17
TESTHI1 TESTHI12
VSS RSVD
FC30
VSS
FERR#/
PBE#
FC39
VSS
FC29
FC4
VSS
VSS
TRST#
TDO
TCK
TDI
TMS
VSS
VTT_OUT_
RIGHT
FC0
MSID0
MSID1
FC28
COMP1
COMP3
AD
AC
AB
AH
AG
AF
AE
AA
R
Y
W
V
U
T
VSS
RSVD
INIT#
VSS
SMI# TESTHI11
IGNNE# PWRGOOD
P
N
VCC VCC VCC VCC VCC VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
REQ2#
VSS
REQ3#
REQ4#
A5#
A3#
VSS
REQ1#
A7#
A6#
REQ0#
VSS
VSS
VSS
A20M#
FC22
TESTHI13
VSS
FC3
LINT1
LINT0
VTT_OUT_
LEFT
M
L
K
J
H
VSS VSS VSS VSS VSS
D29# D27# DSTBN1# DBI1# FC38
D28#
VSS
VSS
D26#
RSVD D25#
D24#
DSTBP1#
VSS
D23#
VSS
VSS
D21#
D15# D22#
D52# VSS D14# D11# VSS
VSS
D16#
D18#
D19#
VSS
VSS
BPRI#
D17#
VSS
D12#
VSS
DEFER#
VSS
RSVD
D20#
RSVD DSTBN0# VSS
VSS
RSVD
FC21
RSVD
VSS
D3#
TESTHI10
PECI
RS1#
FC20
VSS
D1#
FC35
TESTHI9 TESTHI8
VSS
HITM#
HIT#
BR0#
TRDY#
VSS
VSS
VSS
LOCK#
GTLREF1
COMP2
FC5
VSS
ADS#
BNR#
GTLREF0
FC27
RSVD
DRDY#
G
F
E
D
C
VSS COMP8
D50# COMP0
14 13
D13#
VSS
12
VSS D10# DSTBP0#
D9# D8# VSS
11 10 9
VSS
DBI0#
8
D6#
D7#
7
D5#
VSS
6
VSS
D4#
5
D0#
D2#
4
RS0#
RS2#
3
DBSY#
VSS
2
VSS
1
B
A
Datasheet 45
Land Listing and Signal Descriptions
46
Table 23.
Alphabetical Land
Assignments
A27#
A28#
A29#
A30#
A31#
A32#
A33#
A34#
A19#
A20#
A21#
A22#
A23#
A24#
A25#
A26#
A35#
ADS#
A20M#
ADSTB0#
ADSTB1#
BCLK0
BCLK1
BNR#
A11#
A12#
A13#
A14#
A15#
A16#
A17#
A18#
A3#
A4#
A5#
A6#
A7#
A8#
A9#
A10#
Land Name
Land
#
Signal Buffer
Type
Direction
AG5
AH4
AH5
AJ5
AF5
AF4
AG6
AG4
AA5
AB5
AC5
AB4
Y6
Y4
AA4
AD6
V4
W5
AB6
W6
T4
U5
U4
V5
M4
R4
T5
U6
L5
P6
M5
L4
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
AD5
F28
G28
C2
AJ6 Source Synch Input/Output
D2 Common Clock Input/Output
K3
R6
Asynch GTL+ Input
Source Synch Input/Output
Source Synch Input/Output
Clock
Clock
Input
Input
Common Clock Input/Output
Table 23.
Alphabetical Land
Assignments
D8#
D9#
D10#
D11#
D12#
D13#
D14#
D15#
D0#
D1#
D2#
D3#
D4#
D5#
D6#
D7#
D16#
D17#
D18#
D19#
D20#
D21#
D22#
D23#
BSEL0
BSEL1
BSEL2
COMP0
COMP1
COMP2
COMP3
COMP8
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
BPRI#
BR0#
Land Name
Land
#
Signal Buffer
Type
Direction
D7
E10
D10
F11
G9
F8
F9
E9
T1
G2
R1
B13
G29
H30
G30
A13
AJ2 Common Clock Input/Output
AJ1 Common Clock Input/Output
AD2 Common Clock Input/Output
AG2 Common Clock Input/Output
AF2 Common Clock Input/Output
AG3 Common Clock Input/Output
G8
F3
Common Clock Input
Common Clock Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Input
Input
Input
Input
Input
A5
B6
B7
A7
B4
C5
A4
C6
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
A10 Source Synch Input/Output
A11 Source Synch Input/Output
B10 Source Synch Input/Output
C11 Source Synch Input/Output
D8 Source Synch Input/Output
B12 Source Synch Input/Output
C12
D11
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Alphabetical Land
Assignments
D48#
D49#
D50#
D51#
D52#
D53#
D54#
D55#
D40#
D41#
D42#
D43#
D44#
D45#
D46#
D47#
D56#
D57#
D58#
D59#
D60#
D61#
D62#
D63#
D32#
D33#
D34#
D35#
D36#
D37#
D38#
D39#
D24#
D25#
D26#
D27#
D28#
D29#
D30#
D31#
Land Name
Land
#
Signal Buffer
Type
Direction
G17
F17
F18
E18
G16
E15
E16
G18
F14
G14
F15
G15
F12
D13
E13
G13
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
G21
E22
D22
G22
E19
F20
E21
F21
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
D20
D17
Source Synch Input/Output
Source Synch Input/Output
A14 Source Synch Input/Output
C15 Source Synch Input/Output
C14 Source Synch Input/Output
B15 Source Synch Input/Output
C18 Source Synch Input/Output
B16 Source Synch Input/Output
A17 Source Synch Input/Output
B18 Source Synch Input/Output
C21 Source Synch Input/Output
B21 Source Synch Input/Output
B19 Source Synch Input/Output
A19 Source Synch Input/Output
A22 Source Synch Input/Output
B22 Source Synch Input/Output
Table 23.
Alphabetical Land
Assignments
FC18
FC20
FC21
FC22
FC23
FC26
FC27
FC28
FC0
FC3
FC4
FC5
FC8
FC10
FC15
FC17
FC29
FC30
FC31
FC32
FC33
FC34
FC35
FC36
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
DBI0#
DBI1#
DBI2#
DBI3#
DBR#
DBSY#
DEFER#
DRDY#
Land Name
Land
#
Signal Buffer
Type
A24
E29
G1
U1
AE3
E5
F6
J3
AK6
E24
H29
Y3
Y1
J2
T2
F2
H16
J17
H4
AD3
U2
U3
J16
H15
B9
E12
G19
C17
C8
G12
G20
A16
AC2
B2
G7
C1
A8
G11
D19
C20
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other Output
Common Clock Input/Output
Common Clock Input
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
47
Land Listing and Signal Descriptions
48
Table 23.
Alphabetical Land
Assignments
Table 23.
Alphabetical Land
Assignments
Land Name
LOCK#
MSID0
MSID1
PECI
PROCHOT#
PWRGOOD
REQ0#
REQ1#
REQ2#
REQ3#
REQ4#
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
FC37
FC38
FC39
FC40
FERR#/PBE#
GTLREF0
GTLREF1
HIT#
HITM#
IERR#
IGNNE#
INIT#
ITP_CLK0
ITP_CLK1
LINT0
LINT1
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
Land
#
Signal Buffer
Type
Direction Land Name
AC4
AE4
AE6
AH2
M6
K6
J6
A20
AL2
N1
K4
J5
C3
W1
V1
G5
E23
E6
E7
F23
C9
D1
D14
D16
AK3
AJ3
K1
L1
E4
AB2
N2
P3
AB3
G10
AA2
AM6
Power/Other
Power/Other
Power/Other
Power/Other
R3
H1
Asynch GTL+
Power/Other
Output
Input
H2 Power/Other Input
D4 Common Clock Input/Output
Common Clock Input/Output
Asynch GTL+ Output
Asynch GTL+
Asynch GTL+
TAP
TAP
Asynch GTL+
Asynch GTL+
Input
Input
Input
Input
Input
Input
Common Clock Input/Output
Power/Other
Power/Other
Power/Other
Output
Output
TESTHI0
TESTHI1
TESTHI10
TESTHI11
Asynch GTL+ Input/Output TESTHI12/
FC44
Power/Other Input
Source Synch Input/Output
TESTHI13
Source Synch Input/Output
TESTHI2
Source Synch Input/Output
TESTHI3
Source Synch Input/Output
TESTHI4
Source Synch Input/Output
TESTHI5
TESTHI6
TESTHI7
TESTHI8/
FC42
TESTHI9/
FC43
THERMDC
THERMDA
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCC
VCC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESET#
RS0#
RS1#
RS2#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
Land
#
Signal Buffer
Type
Direction
F26
W3
H5
P1
M3
AE1
AD1
AF1
F5
A3
AE8
P2
F29
G6
N4
N5
P5
V2
G23 Common Clock
B3 Common Clock
Input
Input
Common Clock
Common Clock
Power/Other
Asynch GTL+
Input
Input
Asynch GTL+
TAP
TAP
TAP
Input
Input
Input
Input
Power/Other
Power/Other
Power/Other
Power/Other
Output
Input
Input
Input
Input
W2
L2
F25
G25
G27
G26
G24
F24
G3
G4
Power/Other
Asynch GTL+
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AK1
AL1
M2
AC1
Power/Other
Power/Other
Asynch GTL+
TAP
E3
AG1
AA8
AB8
Common Clock
TAP
Power/Other
Power/Other
AC23 Power/Other
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Input
Input
Input
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AC24 Power/Other
AC25 Power/Other
AC26 Power/Other
AC27 Power/Other
AC28 Power/Other
AC29 Power/Other
AC30 Power/Other
AC8 Power/Other
AD23 Power/Other
AD24 Power/Other
AD25 Power/Other
AD26 Power/Other
AD27 Power/Other
AD28 Power/Other
AD29 Power/Other
AD30 Power/Other
AD8
AE11
AE12
AE14
AE15
AE18
AE19
AE21
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AE22
AE23
Power/Other
Power/Other
AE9 Power/Other
AF11 Power/Other
AF12 Power/Other
AF14 Power/Other
AF15 Power/Other
AF18 Power/Other
AF19 Power/Other
AF21 Power/Other
AF22 Power/Other
AF8 Power/Other
AF9 Power/Other
AG11 Power/Other
AG12 Power/Other
AG14 Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AJ15
AJ18
AJ19
AJ21
AJ22
AJ25
AJ26
AJ8
AG15 Power/Other
AG18 Power/Other
AG19 Power/Other
AG21 Power/Other
AG22 Power/Other
AG25 Power/Other
AG26 Power/Other
AG27 Power/Other
AG28 Power/Other
AG29 Power/Other
AG30 Power/Other
AG8 Power/Other
AG9 Power/Other
AH11 Power/Other
AH12 Power/Other
AH14 Power/Other
AH15 Power/Other
AH18 Power/Other
AH19 Power/Other
AH21 Power/Other
AH22 Power/Other
AH25 Power/Other
AH26 Power/Other
AH27 Power/Other
AH28 Power/Other
AH29 Power/Other
AH30 Power/Other
AH8 Power/Other
AH9
AJ11
AJ12
AJ14
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Direction
49
Land Listing and Signal Descriptions
50
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AJ9 Power/Other
AK11 Power/Other
AK12 Power/Other
AK14 Power/Other
AK15 Power/Other
AK18 Power/Other
AK19 Power/Other
AK21 Power/Other
AK22 Power/Other
AK25 Power/Other
AK26 Power/Other
AK8 Power/Other
AK9
AL11
AL12
AL14
Power/Other
Power/Other
Power/Other
Power/Other
AL15
AL18
AL19
AL21
AL22
AL25
AL26
AL29
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AL30
AL8
Power/Other
Power/Other
AL9 Power/Other
AM11 Power/Other
AM12 Power/Other
AM14 Power/Other
AM15 Power/Other
AM18 Power/Other
AM19 Power/Other
AM21 Power/Other
AM22 Power/Other
AM25 Power/Other
AM26 Power/Other
AM29 Power/Other
AM30 Power/Other
AM8 Power/Other
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Direction
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
J25
J26
J27
J28
J21
J22
J23
J24
J15
J18
J19
J20
J11
J12
J13
J14
K23
K24
K25
K26
J29
J30
J8
J9
AM9 Power/Other
AN11 Power/Other
AN12 Power/Other
AN14 Power/Other
AN15 Power/Other
AN18 Power/Other
AN19 Power/Other
AN21 Power/Other
AN22 Power/Other
AN25 Power/Other
AN26 Power/Other
AN29 Power/Other
AN30 Power/Other
AN8 Power/Other
AN9
J10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
T25
T26
T27
T28
P8
R8
T23
T24
N28
N29
N30
N8
N24
N25
N26
N27
U24
U25
U26
U27
T29
T30
T8
U23
M29
M30
M8
N23
M25
M26
M27
M28
K8
L8
M23
M24
K27
K28
K29
K30
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC_MB_
REGULATION
AN5
VCC_SENSE
VCCA
VCCIOPLL
VCCPLL
VID_SELECT AN7
VID0 AM2
VID1
VID2
AL5
AM3
AN3
A23
C23
D23
VID3
VID4
VID5
VID6
VID7
VRDSEL
VSS
VSS
AL6
AK4
AL4
AM5
AM7
AL3
A12
A15
W26
W27
W28
W29
W30
W8
Y23
Y24
U28
U29
U30
U8
V8
W23
W24
W25
Y25
Y26
Y27
Y28
Y29
Y30
Y8
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Output
Power/Other
Power/Other
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Output
Output
51
Land Listing and Signal Descriptions
52
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AE13
AE16
AE17
AE2
AE20
AE24
AE25
AE26
A18
A2
A21
A6
Power/Other
Power/Other
Power/Other
Power/Other
A9 Power/Other
AA23 Power/Other
AA24 Power/Other
AA25 Power/Other
AA26 Power/Other
AA27 Power/Other
AA28 Power/Other
AA29 Power/Other
AA3 Power/Other
AA30 Power/Other
AA6
AA7
Power/Other
Power/Other
AB1 Power/Other
AB23 Power/Other
AB24 Power/Other
AB25 Power/Other
AB26 Power/Other
AB27 Power/Other
AB28 Power/Other
AB29 Power/Other
AB30 Power/Other
AB7 Power/Other
AC3
AC6
Power/Other
Power/Other
AC7
AD4
AD7
AE10
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AE27
AE28
AE29
AE30
Power/Other
Power/Other
Power/Other
Power/Other
AE5
AE7
Power/Other
Power/Other
AF10 Power/Other
AF13 Power/Other
AF16 Power/Other
AF17 Power/Other
AF20 Power/Other
AF23 Power/Other
AF24 Power/Other
AF25 Power/Other
AF26 Power/Other
AF27 Power/Other
AF28 Power/Other
AF29 Power/Other
AF3 Power/Other
AF30 Power/Other
AF6
AF7
Power/Other
Power/Other
AG10 Power/Other
AG13 Power/Other
AG16 Power/Other
AG17 Power/Other
AG20 Power/Other
AG23 Power/Other
AG24 Power/Other
AG7 Power/Other
AH1 Power/Other
AH10 Power/Other
AH13 Power/Other
AH16 Power/Other
AH17 Power/Other
AH20 Power/Other
AH23 Power/Other
AH24 Power/Other
AH3
AH6
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
AH7
AJ10
AJ13
AJ16
AJ17
AJ20
AJ23
AJ24
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AJ27
AJ28
AJ29
AJ30
Power/Other
Power/Other
Power/Other
Power/Other
AJ4
AJ7
Power/Other
Power/Other
AK10 Power/Other
AK13 Power/Other
AK16 Power/Other
AK17 Power/Other
AK2 Power/Other
AK20 Power/Other
AK23 Power/Other
AK24 Power/Other
AK27 Power/Other
AK28 Power/Other
AK29 Power/Other
AK30 Power/Other
AK5
AK7
Power/Other
Power/Other
AL10
AL13
AL16
AL17
Power/Other
Power/Other
Power/Other
Power/Other
AL20
AL23
AL24
AL27
Power/Other
Power/Other
Power/Other
Power/Other
AL28
AL7
Power/Other
Power/Other
AM1 Power/Other
AM10 Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Direction
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
D12
D15
D18
D21
C22
C24
C4
C7
AM13 Power/Other
AM16 Power/Other
AM17 Power/Other
AM20 Power/Other
AM23 Power/Other
AM24 Power/Other
AM27 Power/Other
AM28 Power/Other
AM4
AN1
Power/Other
Power/Other
AN10 Power/Other
AN13 Power/Other
AN16 Power/Other
AN17 Power/Other
AN2 Power/Other
AN20 Power/Other
C10
C13
C16
C19
B20
B24
B5
B8
AN23 Power/Other
AN24 Power/Other
AN27 Power/Other
AN28 Power/Other
B1
B11
B14
B17
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Direction
53
Land Listing and Signal Descriptions
54
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
H18
H19
H20
H21
H12
H13
H14
H17
F4
F7
H10
H11
F13
F16
F19
F22
H26
H27
H28
H3
H22
H23
H24
H25
E27
E28
E8
F10
E2
E20
E25
E26
D9
E11
E14
E17
D24
D3
D5
D6
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Table 23.
Alphabetical Land
Assignments
Land Name
Land
#
Signal Buffer
Type
P26
P27
P28
P29
N7
P23
P24
P25
M1
M7
N3
N6
L3
L30
L6
L7
R23
R24
R25
R26
P30
P4
P7
R2
L26
L27
L28
L29
K7
L23
L24
L25
J4
J7
K2
K5
H6
H7
H8
H9
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 23.
Alphabetical Land
Assignments
Land Name
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS_MB_
REGULATION
VSS_SENSE
VSSA
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
Land
#
Signal Buffer
Type
V25
V26
V27
V28
T7
U7
V23
V24
R5
R7
T3
T6
R27
R28
R29
R30
V7
W4
W7
Y2
V29
V3
V30
V6
Y5
Y7
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AN6
AN4
B23
A25
A26
A27
A28
A29
A30
B25
B26
B27
B28
B29
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Power/Other Output
Output
Table 23.
Alphabetical Land
Assignments
Land Name
VTT
VTT
VTT
VTT
VTT
VTT_OUT_LEF
T
VTT_OUT_RIG
HT
VTT_SEL
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VTT
Land
#
Signal Buffer
Type
C28
C29
C30
D25
B30
C25
C26
C27
D26
D27
D28
D29
D30
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
J1
AA1
F27
Power/Other
Power/Other
Power/Other
Direction
Output
Output
Output
55
Land Listing and Signal Descriptions
56
Table 24.
Numerical Land
Assignment
Land
#
A30
B1
B2
B3
A26
A27
A28
A29
A22
A23
A24
A25
A18
A19
A20
A21
B8
B9
B10
B11
B4
B5
B6
B7
A14
A15
A16
A17
A10
A11
A12
A13
A6
A7
A8
A9
A2
A3
A4
A5
Direction
VTT
VTT
VTT
VTT
VTT
VSS
DBSY#
RS0#
VSS
D61#
RESERVED
VSS
D62#
VCCA
FC23
VTT
D8#
D9#
VSS
COMP0
D50#
VSS
DSTBN3#
D56#
VSS
RS2#
D2#
D4#
VSS
D7#
DBI0#
VSS
D0#
VSS
D5#
D6#
VSS
DSTBP0#
D10#
VSS
Power/Other
Common Clock Input
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Table 24.
Numerical Land
Assignment
Land
#
C10
C11
C12
C13
C6
C7
C8
C9
C2
C3
C4
C5
B28
B29
B30
C1
C18
C19
C20
C21
C14
C15
C16
C17
B24
B25
B26
B27
B20
B21
B22
B23
B16
B17
B18
B19
B12
B13
B14
B15
Direction
D3#
VSS
DSTBN0#
RESERVED
VSS
D11#
D14#
VSS
VTT
VTT
VTT
DRDY#
BNR#
LOCK#
VSS
D1#
D52#
D51#
VSS
DSTBP3#
D54#
VSS
DBI3#
D58#
VSS
D59#
D63#
VSSA
VSS
VTT
VTT
VTT
D13#
COMP8
VSS
D53#
D55#
VSS
D57#
D60#
Source Synch Input/Output
Power/Other Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
Common Clock Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land
#
D20
D21
D22
D23
D16
D17
D18
D19
D12
D13
D14
D15
D8
D9
D10
D11
D28
D29
D30
E2
D24
D25
D26
D27
D4
D5
D6
D7
C30
D1
D2
D3
C26
C27
C28
C29
C22
C23
C24
C25
Direction
D12#
VSS
D22#
D15#
VSS
D25#
RESERVED
VSS
RESERVED
D49#
VSS
DBI2#
D48#
VSS
D46#
VCCPLL
VTT
VTT
VTT
VSS
VSS
VTT
VTT
VTT
VSS
VCCIOPLL
VSS
VTT
VTT
VTT
VTT
VTT
VTT
RESERVED
ADS#
VSS
HIT#
VSS
VSS
D20#
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Power/Other
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Table 24.
Numerical Land
Assignment
Land
#
F3
F4
F5
F6
E27
E28
E29
F2
E23
E24
E25
E26
E19
E20
E21
E22
F11
F12
F13
F14
F7
F8
F9
F10
E15
E16
E17
E18
E11
E12
E13
E14
E7
E8
E9
E10
E3
E4
E5
E6
Direction
VSS
VSS
FC26
FC5
BR0#
VSS
RS1#
FC21
D40#
VSS
D42#
D45#
RESERVED
FC10
VSS
VSS
VSS
D17#
D18#
VSS
D23#
D24#
VSS
D28#
TRDY#
HITM#
FC20
RESERVED
RESERVED
VSS
D19#
D21#
VSS
DSTBP1#
D26#
VSS
D33#
D34#
VSS
D39#
Common Clock Input
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Power/Other
Common Clock
Power/Other
Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
57
Land Listing and Signal Descriptions
58
Table 24.
Numerical Land
Assignment
G4
G17
G18
G19
G20
G13
G14
G15
G16
G21
G22
G23
G24
G9
G10
G11
G12
G5
G6
G7
G8
Land
#
F27
F28
F29
G1
G2
F23
F24
F25
F26
F19
F20
F21
F22
F15
F16
F17
F18
G3
Direction
TESTHI9/
FC43
PECI
RESERVED
DEFER#
BPRI#
D16#
FC38
DBI1#
DSTBN1#
D27#
D29#
D31#
D32#
D36#
D35#
RESERVED
TESTHI7
TESTHI2
TESTHI0
VTT_SEL
BCLK0
RESERVED
FC27
COMP2
TESTHI8/
FC42
D30#
VSS
D37#
D38#
VSS
D41#
D43#
VSS
DSTBP2#
DSTBN2#
D44#
D47#
RESET#
TESTHI6
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Source Synch
Source Synch
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input
Input
Input
Output
Input
Input
Input
Input
Output
Common Clock
Common Clock
Input
Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Common Clock
Power/Other
Input
Input
Table 24.
Numerical Land
Assignment
Land
#
H23
H24
H25
H26
H19
H20
H21
H22
H27
H28
H29
H30
H15
H16
H17
H18
H11
H12
H13
H14
H7
H8
H9
H10
H3
H4
H5
H6
G29
G30
H1
H2
G25
G26
G27
G28
J1
J2
J3
J4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC32
FC33
VSS
VSS
TESTHI3
TESTHI5
TESTHI4
BCLK1
BSEL0
BSEL2
GTLREF0
GTLREF1
VSS
FC35
TESTHI10
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FC15
BSEL1
VTT_OUT_LE
FT
FC3
FC22
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Clock
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Input
Input
Input
Input
Output
Output
Input
Input
Input
Output
Output
Datasheet
Land Listing and Signal Descriptions
Datasheet
Land
#
K3
K4
K5
K6
J29
J30
K1
K2
J25
J26
J27
J28
J21
J22
J23
J24
K25
K26
K27
K28
K7
K8
K23
K24
J17
J18
J19
J20
J13
J14
J15
J16
J9
J10
J11
J12
J5
J6
J7
J8
Table 24.
Numerical Land
Assignment
Direction
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+
Power/Other
Asynch GTL+
Input
Input
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
LINT0
VSS
A20M#
REQ0#
VSS
REQ3#
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VCC
FC31
FC34
VCC
VCC
VCC
REQ1#
REQ4#
VSS
VCC
VCC
VCC
VCC
VCC
Table 24.
Numerical Land
Assignment
Land
#
M25
M26
M27
M28
M7
M8
M23
M24
M3
M4
M5
M6
L29
L30
M1
M2
N3
N4
N5
N6
M29
M30
N1
N2
L25
L26
L27
L28
L7
L8
L23
L24
L3
L4
L5
L6
K29
K30
L1
L2
Direction
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VCC
VCC
LINT1
TESTHI13
VSS
A06#
A03#
VSS
Power/Other
Power/Other
Asynch GTL+
Asynch GTL+
Input
Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
Power/Other
Power/Other
VSS Power/Other
THERMTRIP# Asynch GTL+
STPCLK#
A07#
A05#
REQ2#
Asynch GTL+
Output
Input
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
PWRGOOD
IGNNE#
VSS
RESERVED
RESERVED
VSS
Power/Other
Power/Other
Power/Other
Asynch GTL+
Input
Input
Power/Other
Power/Other
59
Land Listing and Signal Descriptions
60
Table 24.
Numerical Land
Assignment
Land
#
R3
R4
R5
R6
P29
P30
R1
R2
P25
P26
P27
P28
P7
P8
P23
P24
R25
R26
R27
R28
R7
R8
R23
R24
P3
P4
P5
P6
N29
N30
P1
P2
N25
N26
N27
N28
N7
N8
N23
N24
Direction
A08#
VSS
ADSTB0#
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
TESTHI11
SMI#
Power/Other
Power/Other
Power/Other
Asynch GTL+
Input
Input
INIT#
VSS
Asynch GTL+
Power/Other
Input
RESERVED
A04#
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
COMP3
VSS
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
FERR#/PBE# Asynch GTL+
Input
Output
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Table 24.
Numerical Land
Assignment
Land
#
U25
U26
U27
U28
U7
U8
U23
U24
U3
U4
U5
U6
T29
T30
U1
U2
V3
V4
V5
V6
U29
U30
V1
V2
T25
T26
T27
T28
T7
T8
T23
T24
T3
T4
T5
T6
R29
R30
T1
T2
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
FC28
FC29
FC30
A13#
A12#
A10#
VCC
VCC
MSID1
RESERVED
VSS
A15#
A14#
VSS
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
COMP1
FC4
VSS
A11#
A09#
VSS
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Input
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land
#
V25
V26
V27
V28
V7
V8
V23
V24
V29
V30
W1
VCC
VCC
FC0
VSS
VCC
VCC
VCC
VCC
TESTHI1
VSS
A16#
A18#
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VSS
MSID0
TESTHI12/
FC44
FC17
A20#
VSS
A19#
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
W2
Y7
Y8
Y23
Y24
Y3
Y4
Y5
Y6
Y25
Y26
Y27
Y28
W25
W26
W27
W28
W29
W30
Y1
Y2
W7
W8
W23
W24
W3
W4
W5
W6
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Input
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Source Synch Input/Output
Power/Other
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Input
Table 24.
Numerical Land
Assignment
Land
#
Y29
Y30
AA1
A17#
VSS
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IERR#
FC37
A26#
A24#
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VTT_OUT_RI
GHT
FC39
VSS
A21#
A23#
VSS
VSS
VSS
TMS
DBR#
VSS
RESERVED
A25#
VSS
AB24
AB25
AB26
AB27
AB28
AB29
AB30
AC1
AC2
AC3
AC4
AC5
AC6
AB2
AB3
AB4
AB5
AB6
AB7
AB8
AB23
AA24
AA25
AA26
AA27
AA28
AA29
AA30
AB1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA23
Power/Other
Power/Other
Power/Other
Direction
Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Asynch GTL+ Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Power/Other
Input
Output
Power/Other
Source Synch Input/Output
Power/Other
61
Land Listing and Signal Descriptions
62
Table 24.
Numerical Land
Assignment
Land
#
AD29
AD30
AE1
AE2
AE3
AE4
AE5
AE6
AD7
AD8
AD23
AD24
AD25
AD26
AD27
AD28
AE7
AE8
AE9
AE10
AE11
AE12
AE13
AE14
AC29
AC30
AD1
AD2
AD3
AD4
AD5
AD6
AC7
AC8
AC23
AC24
AC25
AC26
AC27
AC28
Direction
VCC
VCC
TCK
VSS
FC18
RESERVED
VSS
RESERVED
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
TDI
BPM2#
FC36
VSS
ADSTB1#
A22#
VCC
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
SKTOCC#
VCC
VSS
VCC
VCC
VSS
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Input
Common Clock Input/Output
Power/Other
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Input
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Land
#
AF9
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF5
AF6
AF7
AF8
AF1
AF2
AF3
AF4
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AE23
AE24
AE25
AE26
AE27
AE28
AE29
AE30
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
Table 24.
Numerical Land
Assignment
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Output
Common Clock Input/Output
Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
TDO
BPM4#
VSS
A28#
A27#
VSS
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VCC
VSS
VSS
VSS
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
Datasheet
Land Listing and Signal Descriptions
Datasheet
Table 24.
Numerical Land
Assignment
Land
#
AG19
AG20
AG21
AG22
AG23
AG24
AG25
AG26
AG11
AG12
AG13
AG14
AG15
AG16
AG17
AG18
AG27
AG28
AG29
AG30
AH1
AH2
AH3
AH4
AG3
AG4
AG5
AG6
AG7
AG8
AG9
AG10
AF25
AF26
AF27
AF28
AF29
AF30
AG1
AG2
Direction
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
TAP Input
Common Clock Input/Output
Common Clock Input/Output
Source Synch Input/Output
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VCC
VCC
VSS
RESERVED
VSS
A32#
BPM5#
A30#
A31#
A29#
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TRST#
BPM3#
Power/Other
Source Synch Input/Output
Table 24.
Numerical Land
Assignment
Land
#
AH29
AH30
AJ1
AJ2
AJ3
AJ4
AJ5
AJ6
AH21
AH22
AH23
AH24
AH25
AH26
AH27
AH28
AJ7
AJ8
AJ9
AJ10
AJ11
AJ12
AJ13
AJ14
AH13
AH14
AH15
AH16
AH17
AH18
AH19
AH20
AH5
AH6
AH7
AH8
AH9
AH10
AH11
AH12
Direction
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Common Clock Input/Output
Common Clock Input/Output
TAP
Power/Other
Input
Source Synch Input/Output
Source Synch Input/Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
BPM1#
BPM0#
ITP_CLK1
VSS
A34#
A35#
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
A33#
VSS
VSS
VCC
VCC
VSS
VCC
VCC
63
Land Listing and Signal Descriptions
64
Table 24.
Numerical Land
Assignment
Land
#
AK9
AK10
AK11
AK12
AK13
AK14
AK15
AK16
AK5
AK6
AK7
AK8
AK1
AK2
AK3
AK4
AK17
AK18
AK19
AK20
AK21
AK22
AK23
AK24
AJ23
AJ24
AJ25
AJ26
AJ27
AJ28
AJ29
AJ30
AJ15
AJ16
AJ17
AJ18
AJ19
AJ20
AJ21
AJ22
VSS
VCC
VCC
VSS
VCC
VSS
VCC
VCC
THERMDC
VSS
ITP_CLK0
VID4
VSS
FC8
VSS
VCC
VCC
VCC
VSS
VSS
VSS
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
Power/Other
Power/Other
TAP
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Input
Output
Table 24.
Numerical Land
Assignment
Land
#
AL19
AL20
AL21
AL22
AL23
AL24
AL25
AL26
AL11
AL12
AL13
AL14
AL15
AL16
AL17
AL18
AL27
AL28
AL29
AL30
AM1
AM2
AM3
AM4
AL7
AL8
AL9
AL10
AL3
AL4
AL5
AL6
AK25
AK26
AK27
AK28
AK29
AK30
AL1
AL2
Direction
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VCC
VCC
VSS
VSS
VCC
VCC
VCC
VSS
VCC
VSS
VSS
VCC
VCC
VSS
VID0
VID2
VSS
VCC
VCC
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VSS
Power/Other
Power/Other
THERMDA Power/Other
PROCHOT# Asynch GTL+ Input/Output
VRDSEL
VID5
VID1
VID3
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Output
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Output
Output
Datasheet
Land Listing and Signal Descriptions
Table 24.
Numerical Land
Assignment
Land
#
AM13
AM14
AM15
AM16
AM17
AM18
AM19
AM20
AM5
AM6
AM7
AM8
AM9
AM10
AM11
AM12
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VID6
FC40
VID7
VCC
VCC
VSS
VCC
VCC
AM21
AM22
AM23
AM24
AM25
AM26
AM27
AM28
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
AM29
AM30
AN1
AN2
VCC
VCC
VSS
VSS
Power/Other
Power/Other
Power/Other
Power/Other
AN3 VCC_SENSE Power/Other
AN4 VSS_SENSE Power/Other
AN5
VCC_MB_
REGULATION
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Direction
Output
Output
Output
Output
Output
Table 24.
Numerical Land
Assignment
Land
#
Direction
AN21
AN22
AN23
AN24
AN25
AN26
AN27
AN28
AN29
AN30
AN13
AN14
AN15
AN16
AN17
AN18
AN19
AN20
AN6
VSS_MB_
REGULATION
Power/Other Output
AN7 VID_SELECT Power/Other
AN8 VCC Power/Other
Output
AN9
AN10
AN11
AN12
VCC
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
VSS
VCC
VCC
VSS
VSS
VCC
VCC
VSS
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
VCC
VCC
VSS
VSS
VCC
VCC
VSS
VSS
VCC
VCC
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Power/Other
Datasheet 65
Land Listing and Signal Descriptions
4.2
Alphabetical Signals Reference
Table 25.
Signal Description ( (Sheet 1 of 9))
A[35:3]#
A20M#
ADS#
Name
ADSTB[1:0]#
Type
Input/
Output
Input
Input/
Output
Description
A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, these signals transmit the address of a transaction. In sub-phase 2, these signals transmit transaction type information. These signals must connect the appropriate pins/lands of all agents on the processor FSB. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# signals to determine power-on configuration. See
for more details.
If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. Assertion of A20M# is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# signals. All bus agents observe the ADS# activation to begin protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction.
Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below.
Input/
Output
Signals
REQ[4:0]#, A[16:3]#
A[35:17]#
Associated Strobe
ADSTB0#
ADSTB1#
BCLK[1:0]
BNR#
Input
Input/
Output
The differential pair BCLK (Bus Clock) determines the FSB frequency. All processor FSB agents must receive these signals to drive their outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V
CROSS
.
BNR# (Block Next Request) is used to assert a bus stall by any bus agent unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.
66 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 2 of 9))
Name
BPM[5:0]#
BPRI#
BR0#
BSEL[2:0]
COMP8
COMP[3:0]
Type
Input/
Output
Input
Input/
Output
Output
Analog
Description
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins/lands of all processor FSB agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor.
These signals do not have on-die termination. Refer to
for termination requirements.
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor FSB. It must connect the appropriate pins/lands of all processor FSB agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by de-asserting BPRI#.
BR0# drives the BREQ0# signal in the system and is used by the processor to request the bus. During power-on configuration this signal is sampled to determine the agent ID = 0.
This signal does not have on-die termination and must be terminated.
The BCLK[1:0] frequency select signals BSEL[2:0] are used to select
the processor input clock frequency. Table 15 defines the possible
combinations of the signals and the frequency associated with each combination. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. For more information about these signals, including termination recommendations refer to
.
COMP[3:0] and COMP8 must be terminated to V
SS board using precision resistors. on the system
Datasheet 67
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 3 of 9))
Name
D[63:0]#
Type Description
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor FSB agents, and must connect the appropriate pins/lands on all such agents. The data driver asserts
DRDY# to indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will, thus, be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#.
The following table shows the grouping of data signals to data strobes and DBI#.
Input/
Output
Quad-Pumped Signal Groups
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
DSTBN#/
DSTBP#
0
1
2
3
DBI#
0
1
2
3
DBI[3:0]#
Input/
Output
Furthermore, the DBI# signals determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high.
DBI[3:0]# (Data Bus Inversion) are source synchronous and indicate the polarity of the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the data bus is inverted. If more than half the data bits, within a 16-bit group, would have been asserted electrically low, the bus agent may invert the data bus signals for that particular sub-phase for that 16-bit group.
DBI[3:0] Assignment To Data Bus
Bus Signal
DBI3#
DBI2#
DBI1#
DBI0#
Data Bus Signals
D[63:48]#
D[47:32]#
D[31:16]#
D[15:0]#
DBR#
DBSY#
Output
Input/
Output
DBR# (Debug Reset) is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on the processor FSB to indicate that the data bus is in use. The data bus is released after DBSY# is de-asserted. This signal must connect the appropriate pins/lands on all processor FSB agents.
68 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 4 of 9))
Name
DEFER#
DRDY#
DSTBN[3:0]#
Type
Input
Input/
Output
Input/
Output
Description
DEFER# is asserted by an agent to indicate that a transaction cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or input/output agent. This signal must connect the appropriate pins/lands of all processor FSB agents.
DRDY# (Data Ready) is asserted by the data driver on each data transfer, indicating valid data on the data bus. In a multi-common clock data transfer, DRDY# may be de-asserted to insert idle clocks.
This signal must connect the appropriate pins/lands of all processor
FSB agents.
DSTBN[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBN0#
DSTBN1#
DSTBN2#
DSTBN3#
DSTBP[3:0]#
FCx
FERR#/PBE#
GTLREF[1:0]
Input/
Output
DSTBP[3:0]# are the data strobes used to latch in D[63:0]#.
Signals
D[15:0]#, DBI0#
D[31:16]#, DBI1#
D[47:32]#, DBI2#
D[63:48]#, DBI3#
Associated Strobe
DSTBP0#
DSTBP1#
DSTBP2#
DSTBP3#
Other
Output
Input
FC signals are signals that are available for compatibility with other processors.
FERR#/PBE# (floating point error/pending break event) is a multiplexed signal and its meaning is qualified by STPCLK#. When
STPCLK# is not asserted, FERR#/PBE# indicates a floating-point error and will be asserted when the processor detects an unmasked floating-point error. When STPCLK# is not asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MS-DOS*-type floating-point error reporting. When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the processor has a pending break event waiting for service. The assertion of FERR#/PBE# indicates that the processor should be returned to the Normal state.
For additional information on the pending break event functionality, including the identification of support of the feature and enable/ disable information, refer to volume 3 of the Intel Architecture
Software Developer's Manual and the Intel Processor Identification
and the CPUID Instruction application note.
GTLREF[1:0] determine the signal reference level for GTL+ input signals. GTLREF is used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.
Datasheet 69
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 5 of 9))
HIT#
Name
HITM#
IERR#
IGNNE#
INIT#
ITP_CLK[1:0]
LINT[1:0]
Type
Input/
Output
Input/
Output
Description
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation results. Any FSB agent may assert both HIT# and
HITM# together to indicate that it requires a snoop stall, which can be continued by reasserting HIT# and HITM# together.
Output
Input
Input
Input
Input
IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a
SHUTDOWN transaction on the processor FSB. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#.
This signal does not have on-die termination. Refer to
for termination requirements.
IGNNE# (Ignore Numeric Error) is asserted to the processor to ignore a numeric error and continue to execute noncontrol floatingpoint instructions. If IGNNE# is de-asserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/
Output Write bus transaction.
INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on
Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins/lands of all processor FSB agents.
ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board.
ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins/ lands of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and
LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the
Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/
INTR or LINT[1:0]. Because the APIC is enabled by default after
Reset, operation of these signals as LINT[1:0] is the default configuration.
70 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 6 of 9))
Name
LOCK#
PECI
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
RESERVED
Type
Input/
Output
Input/
Output
Input/
Output
Input
Input/
Output
Input
Description
LOCK# indicates to the system that a transaction must occur atomically. This signal must connect the appropriate pins/lands of all processor FSB agents. For a locked sequence of transactions,
LOCK# is asserted from the beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the processor FSB, it will wait until it observes LOCK# de-asserted.
This enables symmetric agents to retain ownership of the processor
FSB throughout the bus locked operation and ensure the atomicity of lock.
PECI is a proprietary one-wire bus interface. See Section 5.4
for details.
As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit (TCC) has been activated, if enabled. As an input, assertion of PROCHOT# by the system will activate the TCC, if enabled. The TCC will remain active until the
system de-asserts PROCHOT#. See Section 5.2.4
PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. ‘Clean’ implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins/ lands of all processor FSB agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#.
Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after V
CC
and BCLK have reached their proper specifications. On observing active RESET#, all FSB agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Section 6.1
.
This signal does not have on-die termination and must be terminated on the system board.
All RESERVED lands must remain unconnected. Connection of these lands to V CC , V
SS
, VTT, or to any other signal (including each other) can result in component malfunction or incompatibility with future processors.
Datasheet 71
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 7 of 9))
Name
RS[2:0]#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI[13:0]
Type
Input
Output
Input
Input
Input
Input
Output
Input
Description
RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins/lands of all processor FSB agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this signal to determine if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the FSB and APIC units.
The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is de-asserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
TDO provides the serial output needed for JTAG specification support.
TESTHI[13:0] must be connected to the processor’s appropriate power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal description) through a resistor for proper processor operation. See
for more details.
72 Datasheet
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 8 of 9))
Name
THERMTRIP#
TMS
TRDY#
TRST#
VCC
VCCPLL
VCC_SENSE
VCC_MB_
REGULATION
VID[6:1]
VID_SELECT
Type Description
Output
Input
Input
Input
Input
In the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached a temperature approximately 20 °C above the maximum T
C
. Assertion of
THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond where permanent silicon damage may occur. Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus, halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (V
CC
) must be removed following the assertion of THERMTRIP#. Driving of the THERMTRIP# signal is enabled within 10 μs of the assertion of PWRGOOD (provided V
TT
are valid) and is disabled on de-assertion of PWRGOOD (if
CC
are not valid, THERMTRIP# may also be disabled). Once and V
CC
V
TT
or V activated, THERMTRIP# remains latched until PWRGOOD, V
TT
, or
V
CC
is de-asserted. While the de-assertion of the PWRGOOD, V
TT
, or
V
CC
will de-assert THERMTRIP#, if the processor’s junction temperature remains at or above the trip level, THERMTRIP# will again be asserted within 10 μs of the assertion of PWRGOOD
(provided V
TT
and V
CC
are valid).
TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins/lands of all FSB agents.
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset.
VCC are the power pins for the processor. The voltage supplied to these pins is determined by the VID[6:0] pins.
Input VCCPLL provides isolated power for internal processor FSB PLLs.
Output
VCC_SENSE is an isolated low impedance connection to processor core power (V
CC
). It can be used to sense or measure voltage near the silicon with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
V
CC
. It is connected internally in the processor package to the sense point land U27 as described in the Voltage Regulator-Down (VRD)
11 Design Guide For Desktop and Transportable LGA775 Socket.
Output
Output
VID[6:1] (Voltage ID) signals are used to support automatic selection of power supply voltages (V
CC
). Refer to the appropriate
platform design guide or the Voltage Regulator-Down (VRD) 11
Design Guide For Desktop and Transportable LGA775 Socket for more information. The voltage supply for these signals must be valid before the VR can supply V
CC
to the processor. Conversely, the VR output must be disabled until the voltage supply for the VID signals becomes valid. The VID signals are needed to support the processor voltage specification variations. See
Table 2 for definitions of these
signals. The VR must supply the voltage that is requested by the signals, or disable itself.
This land is tied high on the processor package and is used by the
VR to choose the proper VID table. Refer to the Voltage Regulator-
Down (VRD) 11 Design Guide For Desktop and Transportable
LGA775 Socket for more information.
Datasheet 73
Land Listing and Signal Descriptions
Table 25.
Signal Description ( (Sheet 9 of 9))
Name
VRDSEL
VSS
VSSA
VSS_SENSE
VSS_MB_
REGULATION
VTT
VTT_OUT_LEFT
VTT_OUT_RIGHT
VTT_SEL
Type Description
Input
Input
This input should be left as a no connect in order for the processor to boot. The processor will not boot on legacy platforms where this land is connected to V
SS
.
VSS are the ground pins for the processor and should be connected to the system ground plane.
Input VSSA is the isolated ground for internal PLLs.
Output
VSS_SENSE is an isolated low impedance connection to processor core V
SS
. It can be used to sense or measure ground near the silicon with little noise.
Output
This land is provided as a voltage regulator feedback sense point for
V
SS
. It is connected internally in the processor package to the sense point land V27 as described in the Voltage Regulator-Down (VRD)
11 Design Guide For Desktop and Transportable LGA775 Socket.
Miscellaneous voltage supply.
Output
Output
The VTT_OUT_LEFT and VTT_OUT_RIGHT signals are included to provide a voltage supply for some signals that require termination to
V
TT
on the motherboard.
The VTT_SEL signal is used to select the correct V
TT the processor.
voltage level for
§
74 Datasheet
Thermal Specifications and Design Considerations
5
5.1
Note:
5.1.1
Thermal Specifications and
Design Considerations
Processor Thermal Specifications
The processor requires a thermal solution to maintain temperatures within the
operating limits as set forth in Section 5.1.1
. Any attempt to operate the processor outside these operating limits may result in permanent damage to the processor and potentially other components within the system. As processor technology changes, thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system operation.
A complete thermal solution includes both component and system level thermal management features. Component level thermal solutions can include active or passive heatsinks attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
Intel
®
Celeron
®
Processor 400 Series Thermal and Mechanical Design Guidelines.
The boxed processor will ship with a component thermal solution. Refer to Chapter 7
for details on the boxed processor.
Thermal Specifications
To allow for the optimal operation and long-term reliability of Intel processor-based systems, the system/processor thermal solution should be designed such that the processor remains within the minimum and maximum case temperature (T details on thermal solution design, refer to the Intel
Thermal and Mechanical Design Guidelines.
®
C
) specifications when operating at or below the Thermal Design Power (TDP) value listed
. Thermal solutions not designed to provide this level of thermal capability may affect the long-term reliability of the processor and system. For more
Celeron ® Processor 400 Series
The processor uses a methodology for managing processor temperatures which is intended to support acoustic noise reduction through fan speed control. Selection of the appropriate fan speed is based on the relative temperature data reported by the processor’s Platform Environment Control Interface (PECI) bus as described in
. The temperature reported over PECI is always a negative value and represents a delta below the onset of thermal control circuit (TCC) activation, as
indicated by PROCHOT# (see Section 5.2
). Systems that implement fan speed control must be designed to take these conditions in to account. Systems that do not alter the fan speed only need to guarantee the case temperature meets the thermal profile specifications.
To determine a processor's case temperature specification based on the thermal profile, it is necessary to accurately measure processor power dissipation. Intel has developed a methodology for accurate power measurement that correlates to Intel test temperature and voltage conditions. Refer to the Intel ® Celeron ® Processor 400 Series
Thermal and Mechanical Design Guidelines for the details of this methodology.
The case temperature is defined at the geometric top center of the processor. Analysis indicates that real applications are unlikely to cause the processor to consume maximum power dissipation for sustained time periods. Intel recommends that
Datasheet 75
Thermal Specifications and Design Considerations complete thermal solution designs target the Thermal Design Power (TDP) indicated in
instead of the maximum processor power consumption. The Thermal Monitor feature is designed to protect the processor in the unlikely event that an application exceeds the TDP recommendation for a sustained periods of time. For more details on the usage of this feature, refer to
. To ensure maximum flexibility for future
requirements, systems should be designed to the 775_VR_CONFIG_06 guidelines, even if a processor with a lower thermal dissipation is currently planned. In all cases the
Thermal Monitor or Thermal Monitor 2 feature must be enabled for the processor to remain within specification.
Table 26.
Processor Thermal Specifications
Processor
Number
Core
Frequency
(GHz)
Thermal
Design
Power (W)
Extended
HALT
Power (W) 1
775_VR_
CONFIG_06
Guidance 2
Minimum
T
C
(°C)
Maximum
T
C
(°C)
Notes
420
430
440
450
1.6
1.8
2.0
2.2
35.0
35.0
35.0
35.0
8
8
8
8
775_VR_CONFIG
_06
5
5
5
5
3, 4
3, 4
3, 4
3, 4
NOTES:
1. Specification is at 35 °C T
C
and typical voltage loadline.
2. 775_VR_CONFIG_06 guidelines provide a design target for meeting future thermal requirements.
3. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not the maximum power that the processor can dissipate.
4. This table shows the maximum TDP for a given frequency range. Individual processors may have a lower TDP. Therefore, the maximum T
C
will vary depending on the TDP of the individual processor. Refer to thermal profile figure and associated table for the allowed combinations of power and T
C
.
76 Datasheet
Thermal Specifications and Design Considerations
Table 27.
8
10
12
14
16
18
4
6
0
2
Thermal Profile
Power (W)
Maximum
Tc (°C)
43.2
44.2
45.2
46.1
47.1
48.1
49.1
50.1
51.0
52.0
Figure 16.
Thermal Profile
65.0
60.0
55.0
50.0
45.0
40.0
35.0
30.0
0 y = 0.49x + 43.3
10
Power
28
30
32
34
35
20
22
24
26
Maximum
Tc (°C)
53.0
54.0
55.0
55.9
56.9
57.9
58.9
59.9
60.4
Pow er (W )
20 30
Datasheet 77
Thermal Specifications and Design Considerations
5.1.2
Thermal Metrology
The maximum and minimum case temperatures (T
C
) for the processor is specified in
. This temperature specification is meant to help ensure proper operation of
the processor. Figure 17 illustrates where Intel recommends T
C
thermal measurements should be made. For detailed guidelines on temperature measurement methodology, refer to the Intel
Guidelines.
® Celeron ® Processor 400 Series Thermal and Mechanical Design
Figure 17.
Case Temperature (T
C
) Measurement Location
5.2
5.2.1
78
Processor Thermal Features
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the thermal control circuit (TCC) when the processor silicon reaches its maximum operating temperature. The TCC reduces processor power consumption by modulating (starting and stopping) the internal processor core clocks. The Thermal Monitor feature must
be enabled for the processor to be operating within specifications. The temperature at which Thermal Monitor activates the thermal control circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal manner, and interrupt requests are latched (and serviced during the time that the clocks are on) while the TCC is active.
When the Thermal Monitor feature is enabled, and a high temperature situation exists
(i.e., TCC is active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle specific to the processor (typically 30–50%). Clocks often will not be off for more than 3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will decrease as processor core frequencies increase. A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
With a properly designed and characterized thermal solution, it is anticipated that the
TCC would only be activated for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief
Datasheet
Thermal Specifications and Design Considerations
5.2.2
periods of TCC activation is expected to be so minor that it would be immeasurable. An under-designed thermal solution that is not able to prevent excessive activation of the
TCC in the anticipated ambient environment may cause a noticeable performance loss, and in some cases may result in a T
C
that exceeds the specified maximum temperature and may affect the long-term reliability of the processor. In addition, a thermal solution that is significantly under-designed may not be capable of cooling the processor even when the TCC is active continuously. Refer to the Intel solution.
® Celeron ® Processor 400 Series
Thermal and Mechanical Design Guidelines for information on designing a thermal
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and cannot be modified. The Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines.
Thermal Monitor 2
The processor also supports an additional power reduction capability known as Thermal
Monitor 2. This mechanism provides an efficient means for limiting the processor temperature by reducing the power consumption within the processor.
When Thermal Monitor 2 is enabled, and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a reduction to the processor power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each consisting of a specific operating frequency and voltage. The first operating point represents the normal operating condition for the processor. Under this condition, the core-frequency-to-FSB multiple used by the processor is that contained in the
CLK_GEYSIII_STAT MSR and the VID is that specified in Table 2
. These parameters represent normal system operation.
The second operating point consists of both a lower operating frequency and voltage.
When the TCC is activated, the processor automatically transitions to the new frequency. This transition occurs very rapidly (on the order of 5 μs). During the frequency transition, the processor is unable to service any bus requests, and consequently, all bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new core operating voltage by issuing a new VID code to the voltage regulator. The voltage regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes to reach the target operating voltage. Each step will likely be one VID table entry (see
Table 2 ). The processor continues to execute instructions during the voltage transition.
Operation at the lower voltage reduces the power consumption of the processor.
A small amount of hysteresis has been included to prevent rapid active/inactive transitions of the TCC when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. Transition of the VID code will occur first, in order to insure proper operation once the processor reaches its normal operating frequency. Refer to
Figure 18 for an illustration of this ordering.
Datasheet 79
Thermal Specifications and Design Considerations
Figure 18.
Thermal Monitor 2 Frequency and Voltage Ordering
T
TM2
f
MAX
f
TM2
VID
VID
TM2
Temperature
Frequency
VID
5.2.3
PROCHOT#
The PROCHOT# signal is asserted when a high temperature situation is detected, regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
It should be noted that the Thermal Monitor 2 TCC cannot be activated via the on demand mode. The Thermal Monitor TCC, however, can be activated through the use of the on demand mode.
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption. This mechanism is referred to as “On-
Demand” mode and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to reduce system level power consumption. Systems using the processor must not rely on software usage of this mechanism to limit the processor temperature.
If bit 4 of the ACPI P_CNT Control Register (located in the processor
IA32_THERM_CONTROL MSR) is written to a '1', the processor will immediately reduce its power consumption via modulation (starting and stopping) of the internal core clock, independent of the processor temperature. When using On-Demand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of the same ACPI P_CNT
Control Register. In On-Demand mode, the duty cycle can be programmed from 12.5% on/87.5% off, to 87.5% on/12.5% off in 12.5% increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty cycle of the
TCC will override the duty cycle selected by the On-Demand mode.
80 Datasheet
Thermal Specifications and Design Considerations
5.2.4
5.2.5
PROCHOT# Signal
An external signal, PROCHOT# (processor hot), is asserted when the processor core temperature has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the Thermal Monitor must be enabled for the processor to be operating within specification), the TCC will be active when PROCHOT# is asserted. The processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#.
As an output, PROCHOT# (Processor Hot) will go active when the processor temperature monitoring sensor detects that one or both cores has reached its maximum safe operating temperature. This indicates that the processor Thermal
Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system will activate the TCC, if enabled, for both cores. The TCC will remain active until the system de-asserts PROCHOT#.
PROCHOT# allows for some protection of various components from over-temperature situations. The PROCHOT# signal is bi-directional in that it can either signal when the processor (either core) has reached its maximum operating temperature or be driven from an external source to activate the TCC. The ability to activate the TCC via
PROCHOT# can provide a means for thermal protection of system components.
PROCHOT# can allow VR thermal designs to target maximum sustained current instead of maximum current. Systems should still provide proper cooling for the VR, and rely on PROCHOT# only as a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power. With a properly designed and characterized thermal solution, it is anticipated that PROCHOT# would only be asserted for very short periods of time when running the most power intensive applications. An under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may cause a noticeable performance loss. Refer to the Voltage Regulator-Down (VRD) 11 Design
Guide For Desktop and Transportable LGA775 Socket for details on implementing the bi-directional PROCHOT# feature.
THERMTRIP# Signal
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
). At this point, the FSB signal THERMTRIP# will go active and stay active as described in
Table 25 . THERMTRIP# activation is independent of processor activity and
does not generate any bus cycles.
Datasheet 81
Thermal Specifications and Design Considerations
5.3
Table 28.
Thermal Diode
The processor incorporates an on-die PNP transistor where the base emitter junction is used as a thermal "diode", with its collector shorted to ground. A thermal sensor located on the system board may monitor the die temperature of the processor for thermal management and fan speed control.
, and
provide the "diode" parameter and interface specifications. Two different sets of "diode"
parameters are listed in Table 28
and
Table 29 . The Diode Model parameters (
apply to traditional thermal sensors that use the Diode Equation to determine the
processor temperature. Transistor Model parameters ( Table 29 ) have been added to
support thermal sensors that use the transistor equation method. The Transistor Model may provide more accurate temperature measurements when the diode ideality factor is closer to the maximum or minimum limits. This thermal "diode" is separate from the
Thermal Monitor's thermal sensor and cannot be used to predict the behavior of the
Thermal Monitor.
T
CONTROL
is a temperature specification based on a temperature reading from the thermal diode. The value for T configured for each processor. The T
will be calibrated in manufacturing and
CONTROL
temperature for a given processor can be obtained by reading a MSR in the processor. The T
CONTROL
value that is read from the
MSR needs to be converted from Hexadecimal to Decimal and added to a base value of
50 °C.
The value of T
CONTROL
may vary from 00h to 1Eh (0 to 30 °C).
When T
T
DIODE
CONTROL
is above T
CONTROL
, then T
C
must be at or below T
(or lower) as measured by the thermal diode.
C_MAX
as defined by the thermal profile in
; otherwise, the processor temperature can be maintained at
Thermal “Diode” Parameters using Diode Model
Symbol
I
FW n
R
T
Parameter
Forward Bias Current
Diode Ideality Factor
Series Resistance
Min
5
1.000
2.79
Typ
—
1.009
4.52
Max
200
1.050
6.24
Unit
µA
-
Ω
Notes
1
2, 3, 4
2, 3, 5
NOTES:
1.
2.
3.
4.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Preliminary data. Will be characterized across a temperature range of 50–80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:
5.
I
FW
= I
S
* (e qV
D
/nkT
–1) where I
S
= saturation current, q = electronic charge, V
The series resistance, R
T junction temperature. R
T
D
= voltage across the diode,
, is provided to allow for a more accurate measurement of the
, as defined, includes the lands of the processor but does not include any socket resistance or board trace resistance between the socket and the external remote diode thermal sensor. R
T
can be used by remote diode thermal sensors with automatic series resistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calculated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation: where T error
T error
= [R
T
* (N–1) * I
FWmin
] / [nk/q * ln N]
= sensor temperature error, N = sensor current ratio, k = Boltzmann
Constant, q = electronic charge.
82 Datasheet
Thermal Specifications and Design Considerations
Table 29.
Table 30.
Thermal “Diode” Parameters using Transistor Model
Symbol
I
FW
I
E n
Q
Beta
R
T
Parameter
Forward Bias Current
Emitter Current
Transistor Ideality
Series Resistance
Min
5
5
0.997
0.391
2.79
Typ
—
—
1.001
—
4.52
Max
200
200
1.005
0.760
6.24
Unit
µA
-
Ω
Notes
1, 2
3, 4, 5
3, 4
3, 6
2.
3.
4.
5.
NOTES:
1.
Intel does not support or recommend operation of the thermal diode under reverse bias.
Same as I
FW
Preliminary data. Will be characterized across a temperature range of 50–80 °C.
Not 100% tested. Specified by design characterization.
The ideality factor, nQ, represents the deviation from ideal transistor model behavior as exemplified by the equation for the collector current:
6.
I
C
= I
S
* (e qV
BE
/n
Q kT
–1)
Where I
S
= saturation current, q = electronic charge, V
BE temperature (Kelvin).
The series resistance, R
T,
provided in the Diode Model Table ( Table 28 ) can be used for
more accurate readings as needed.
= voltage across the transistor base emitter junction (same nodes as VD), k = Boltzmann Constant, and T = absolute
The Intel
®
Celeron
®
processor 400 Series does not support the diode correction offset that exists on other Intel processors.
Thermal Diode Interface
Signal Name
THERMDA
THERMDC
Land Number
AL1
AK1
Signal
Description diode anode diode cathode
Datasheet 83
Thermal Specifications and Design Considerations
5.4
Platform Environment Control Interface (PECI)
5.4.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset components. It uses a single wire, thus alleviating routing congestion issues.
shows an example of the PECI topology in a system. PECI uses CRC checking on the host side to ensure reliable transfers between the host and client devices. Also, data transfer speeds across the PECI interface are negotiable within a wide range (2 Kbps to
2 Mbps). The PECI interface on the processor is disabled by default and must be enabled through BIOS.
Figure 19.
Processor PECI Topology
PECI Host
Controller
Land G5
Domain 0
5.4.1.1
Key Difference with Legacy Diode-Based Thermal Management
Fan speed control solutions based on PECI uses a T
CONTROL processor IA32_TEMPERATURE_TARGET MSR. The T
value stored in the
CONTROL
MSR uses the same offset temperature format as PECI though it contains no sign bit. Thermal management devices should infer the T should use the relative temperature value delivered over PECI in conjunction with the
T
CONTROL
CONTROL
value as negative. Thermal management algorithms
MSR value to control or optimize fan speeds.
fan control diagram using PECI temperatures.
The relative temperature value reported over PECI represents the delta below the onset of thermal control circuit (TCC) activation as indicated by PROCHOT# assertions. As the temperature approaches TCC activation, the PECI value approaches zero. TCC activates at a PECI count of zero.
84 Datasheet
Thermal Specifications and Design Considerations
.
Figure 20.
Conceptual Fan Control on PECI-Based Platforms
Fan Speed
(RPM)
T
CONTROL
Setting
Max
PECI = -10
TCC Activation
Temperature
PECI = 0
Min
PECI = -20
Temperature
Note: Not intended to depict actual implementation
.
Figure 21.
Conceptual Fan Control on Thermal Diode-Based Platforms
Fan Speed
(RPM)
T
CONTROL
Setting
TCC Activation
Temperature
Max
T
DIODE
= 80 °C
T
DIODE
= 90 °C
Min
T
DIODE
= 70 °C
Temperature
Datasheet 85
Thermal Specifications and Design Considerations
5.4.2
5.4.2.1
5.4.2.2
5.4.2.3
5.4.2.4
Table 31.
PECI Specifications
PECI Device Address
The PECI device address for the socket is 30h. For more information on PECI domains, refer to the Platform Environment Control Interface Specification.
PECI Command Support
PECI command support is covered in detail in the Platform Environment Control
Interface Specification. Refer to this document for details on supported PECI command function and codes.
PECI Fault Handling Requirements
PECI is largely a fault tolerant interface, including noise immunity and error checking improvements over other comparable industry standard interfaces. The PECI client is as reliable as the device that it is embedded in, and thus given operating conditions that fall under the specification, the PECI will always respond to requests and the protocol itself can be relied upon to detect any transmission failures. There are, however, certain scenarios where the PECI is know to be unresponsive.
Prior to a power on RESET# and during RESET# assertion, PECI is not ensured to provide reliable thermal data. System designs should implement a default power-on condition that ensures proper processor operation during the time frame when reliable data is not available via PECI.
To protect platforms from potential operational or safety issues due to an abnormal condition on PECI, the Host controller should take action to protect the system from possible damaging states. It is recommended that the PECI host controller take appropriate action to protect the client processor device if valid temperature readings have not been obtained in response to three consecutive gettemp()s or for a one second time interval. The host controller may also implement an alert to software in the event of a critical or continuous fault condition.
PECI GetTemp0() Error Code Support
The error codes supported for the processor GetTemp() command are listed in
.
GetTemp0() Error Codes
Error Code
8000h
8002h
Description
General sensor error
Sensor is operational, but has detected a temperature below its operational range (underflow).
§
86 Datasheet
Features
6 Features
6.1
Table 32.
6.2
Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware configuration at reset, on the active-to-inactive transition of RESET#. For
specifications on these options, refer to Table 32
.
The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset. All resets reconfigure the processor; for reset purposes, the processor does not distinguish between a
"warm" reset and a "power-on" reset.
Frequency determination functionality will exist on engineering sample processors which means that samples can run at varied frequencies. Production material will have the bus to core ratio locked and can only be operated at the rated frequency.
Power-On Configuration Option Signals
Configuration Option
Output tristate
Execute BIST
Disable dynamic bus parking
Symmetric agent arbitration ID
RESERVED
Signal 1,2
SMI#
A3#
A25#
BR0#
A[8:4]#, A[24:11]#, A[35:26]#
NOTE:
1.
2.
Asserting this signal during RESET# will select the corresponding option.
Address signals not identified in this table as configuration options should not be asserted during RESET#.
Clock Control and Low Power States
The processor allows the use of AutoHALT and Stop-Grant states which may reduce power consumption by stopping the clock to internal sections of the processor,
depending on each particular state. See Figure 22
for a visual representation of the processor low power states.
Datasheet 87
Figure 22.
Processor Low Power State Machine
Features
6.2.1
6.2.2
6.2.2.1
Normal State
This is the normal operating state for the processor.
HALT and Extended HALT Powerdown States
The processor supports the HALT or Extended HALT powerdown state. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification.
The Extended HALT state is a lower power state as compared to the Stop Grant State.
If Extended HALT is not enabled, the default Powerdown state entered will be HALT.
Refer to the sections below for details about the HALT and Extended HALT states.
HALT Powerdown State
HALT is a low power state entered when all the processor cores have executed the HALT or MWAIT instructions. When one of the processor cores executes the HALT instruction, that processor core is halted, however, the other processor continues normal operation.
The processor will transition to the Normal state upon the occurrence of SMI#, INIT#, or LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the Intel Architecture Software
Developer's Manual, Volume III: System Programmer's Guide for more information.
88 Datasheet
Features
6.2.2.2
6.2.3
The system can generate a STPCLK# while the processor is in the HALT Power Down state. When the system deasserts the STPCLK# interrupt, the processor will return execution to the HALT state.
While in HALT Power Down state, the processor will process bus snoops.
Extended HALT Powerdown State
Extended HALT is a low power state entered when all processor cores have executed the HALT or MWAIT instructions and Extended HALT has been enabled via the BIOS.
When one of the processor cores executes the HALT instruction, that logical processor is halted; however, the other processor continues normal operation. The Extended
HALT Powerdown must be enabled via the BIOS for the processor to remain within its specification.
The processor will automatically transition to a lower frequency and voltage operating point before entering the Extended HALT state. Note that the processor FSB frequency is not altered; only the internal core frequency is changed. When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the lower VID.
While in Extended HALT state, the processor will process bus snoops.
The processor exits the Extended HALT state when a break event occurs. When the processor exits the Extended HALT state, it will first transition the VID to the original value and then change the bus ratio back to the original value.
Stop Grant State
When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered
20 bus clocks after the response phase of the processor-issued Stop Grant
Acknowledge special bus cycle.
Since the GTL+ signals receive power from the FSB, these signals should not be driven
(allowing the level to return to V
TT
) for minimum power drawn by the termination resistors in this state. In addition, all other input signals on the FSB should be driven to the inactive state.
RESET# will cause the processor to immediately initialize itself, but the processor will stay in Stop-Grant state. A transition back to the Normal state will occur with the deassertion of the STPCLK# signal.
A transition to the Grant Snoop state will occur when the processor detects a snoop on the FSB (see
).
While in the Stop-Grant State, SMI#, INIT#, and LINT[1:0] will be latched by the processor, and only serviced when the processor returns to the Normal State. Only one occurrence of each event will be recognized upon return to the Normal state.
While in Stop-Grant state, the processor will process a FSB snoop.
Datasheet 89
Features
6.2.4
HALT Snoop State and Stop Grant Snoop State
The processor will respond to snoop transactions on the FSB while in Stop-Grant state or in HALT Power Down state. During a snoop transaction, the processor enters the
HALT Snoop State:Stop Grant Snoop state. The processor will stay in this state until the snoop on the FSB has been serviced (whether by the processor or another agent on the
FSB). After the snoop is serviced, the processor will return to the Stop Grant state or
HALT Power Down state, as appropriate.
§
90 Datasheet
Boxed Processor Specifications
7 Boxed Processor Specifications
The processor will also be offered as an Intel boxed processor. Intel boxed processors are intended for system integrators who build systems from baseboards and standard components. The boxed processor will be supplied with a cooling solution. This chapter documents baseboard and system requirements for the cooling solution that will be supplied with the boxed processor. This chapter is particularly important for OEMs that manufacture baseboards for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in millimeters and inches [in brackets].
mechanical representation of a boxed processor.
Note: Drawings in this chapter reflect only the specifications on the Intel boxed processor product. These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is the system designers’ responsibility to consider their proprietary cooling solution when designing to the required keep-out zone on their system platforms and chassis. Refer to the Intel ® Celeron ® Processor 400 Series Thermal and
Mechanical Design Guidelines for further guidance.
Figure 23.
Mechanical Representation of the Boxed Processor
Datasheet
NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.
91
Boxed Processor Specifications
7.1
Mechanical Specifications
7.1.1
Boxed Processor Cooling Solution Dimensions
This section documents the mechanical specifications of the boxed processor. The boxed processor will be shipped with an unattached fan heatsink.
mechanical representation of the boxed processor.
Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The physical space requirements and dimensions for the boxed processor with
assembled fan heatsink are shown in Figure 24
(Top View).
The airspace requirements for the boxed processor fan heatsink must also be incorporated into new baseboard and system designs. Airspace requirements are shown in
. Note that some figures have centerlines shown
(marked with alphabetic designations) to clarify relative dimensioning.
Figure 24.
Space Requirements for the Boxed Processor (Side View)
95.0
[3.74]
81.3
[3.2]
10.0
[0.39]
25.0
[0.98]
Boxed_Proc_SideView
92 Datasheet
Boxed Processor Specifications
Figure 25.
Space Requirements for the Boxed Processor (Top View)
NOTES:
1.
Diagram does not show the attached hardware for the clip design and is provided only as a mechanical representation.
Figure 26.
Space Requirements for the Boxed Processor (Overall View)
Datasheet
Boxed Proc OverallView
93
Boxed Processor Specifications
7.1.2
7.1.3
Boxed Processor Fan Heatsink Weight
The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5
and the Intel ® Celeron ® Processor 400 Series Thermal and Mechanical Design
Guidelines for details on the processor weight and heatsink requirements.
Boxed Processor Retention Mechanism and Heatsink
Attach Clip Assembly
The boxed processor thermal solution requires a heatsink attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed processor will ship with the heatsink attach clip assembly.
7.2
Electrical Requirements
7.2.1
Fan Heatsink Power Supply
The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be shipped with the boxed processor to draw power from a power header on the
baseboard. The power cable connector and pinout are shown in Figure 27
. Baseboards
must provide a matched power header to support the boxed processor. Table 33
contains specifications for the input and output signals at the fan heatsink connector.
The fan heatsink outputs a SENSE signal, which is an open- collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor provides V
OH
to match the system board-mounted fan speed monitor requirements, if applicable. Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should be tied to GND.
Figure 27.
Boxed Processor Fan Heatsink Power Cable Connector Description
94
NOTES:
1.
2.
3.
Pin 1: Ground; black wire.
Pin 2: Power, +12 V; yellow wire.
Pin 3: Signal, Open collector tachometer output signal requirement: 2 pulses per revolution; green wire.
Datasheet
Boxed Processor Specifications
Figure 28.
Baseboard Power Header Placement Relative to Processor Socket
R110
[4.33]
B
C
7.3
7.3.1
Boxed Proc PwrHeaderPlacement
Thermal Specifications
This section describes the cooling requirements of the fan heatsink solution used by the boxed processor.
Boxed Processor Cooling Requirements
The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's temperature specification is also a function of the thermal design of the entire system, and ultimately the responsibility of the system integrator. The processor temperature specification is listed in
Chapter 5 . The boxed processor fan heatsink is
able to keep the processor temperature within the specifications (see Table ) in chassis
that provide good thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the cooling efficiency and decreases fan life.
illustrate an acceptable airspace clearance for the fan heatsink. The air temperature entering the fan should be kept below 38 ºC. Again, meeting the processor's temperature specification is the responsibility of the system integrator.
Datasheet 95
Boxed Processor Specifications
Figure 29.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Top 1 view)
Figure 30.
Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)
96 Datasheet
Boxed Processor Specifications
7.3.2
Variable Speed Fan
The boxed processor fan will operate at different speeds over a short range of internal chassis temperatures. This allows the processor fan to operate at a lower speed and noise level, while internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set point, the fan speed will rise linearly with the internal temperature until the higher set point is reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise levels. Systems should be designed to provide adequate air around the boxed processor fan heatsink that remains
cooler then lower set point. These set points, represented in Figure 31
and
can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis temperature should be kept below 38 ºC. Meeting the processor's temperature specification (see
Chapter 5 ) is the responsibility of the system integrator.
The motherboard must supply a constant +12 V to the processor's power header to ensure proper operation of the variable speed fan for the boxed processor. Refer to
for the specific requirements.
Figure 31.
Boxed Processor Fan Heatsink Set Points
Higher Set Point
Highest Noise Level
Increasing Fan
Speed & Noise
Lower Set Point
Lowest Noise Level
X Y
Internal Chassis Temperature (Degrees C)
Z
Table 33.
Fan Heatsink Power and Signal Specifications
Boxed Processor Fan
Heatsink Set Point ( ° C)
Boxed Processor Fan Speed
X ≤ 30
Y = 35
Z ≥ 38
When the internal chassis temperature is below or equal to this set point, the fan operates at its lowest speed.
Recommended maximum internal chassis temperature for nominal operating environment.
When the internal chassis temperature is at this point, the fan operates between its lowest and highest speeds.
Recommended maximum internal chassis temperature for worst-case operating environment.
When the internal chassis temperature is above or equal to this set point, the fan operates at its highest speed.
NOTES:
1. Set point variance is approximately ± 1 °C from fan heatsink to fan heatsink.
Notes
1
-
-
Datasheet 97
§ §
Boxed Processor Specifications
98 Datasheet
Debug Tools Specifications
8
8.1
8.1.1
8.1.2
Debug Tools Specifications
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging systems. Tektronix and Agilent should be contacted to get specific information about their logic analyzer interfaces. The following information is general in nature. Specific information must be obtained from the logic analyzer vendor.
Due to the complexity of systems, the LAI is critical in providing the ability to probe and capture FSB signals. There are two sets of considerations to keep in mind when designing a r system that can make use of an LAI: mechanical and electrical.
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI lands plug into the processor socket, while the processor lands plug into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection between the processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor. System designers must make sure that the keepout volume remains unobstructed inside the system. Note that it is possible that the keepout volume reserved for the LAI may differ from the space normally occupied by the processor’s heatsink. If this is the case, the logic analyzer vendor will provide a cooling solution as part of the LAI.
Electrical Considerations
The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain electrical load models from each of the logic analyzers to be able to run system level simulations to prove that their tool will work in the system. Contact the logic analyzer vendor for electrical specifications and load models for the LAI solution it provides.
§
Datasheet 99
Debug Tools Specifications
100 Datasheet
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project
Key Features
- Intel® Celeron® 440 2 GHz
- 0.512 MB L2 LGA 775 (Socket T)
- Processor cores: 1 65 nm 64-bit 35 W