Dual-Core Intel® Xeon® Processor
7100 Series
Datasheet
September 2006
Reference Number: 314553 Revision: 002
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The Dual-Core Intel® Xeon® Processor 7100 Series, Processor 7110, 7120, 7130, 7140 and 7150 processor may contain design
defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available on request.
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed
by Intel. Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and
North American Philips Corporation.Contact your local Intel sales office or your distributor to obtain the latest specifications and
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64-bit computing on Intel architecture requires a computer system with a processor, chipset, BIOS, operating system, device
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Copyright © 2006 Intel Corporation.
2
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Contents
1
Introduction ............................................................................................................ 11
1.1
Terminology ..................................................................................................... 13
1.2
References ....................................................................................................... 14
1.3
State of Data .................................................................................................... 15
2
Electrical Specifications ........................................................................................... 17
2.1
Front Side Bus and GTLREF ................................................................................ 17
2.1.1 Front Side Bus Clock and Processor Clocking .............................................. 18
2.1.2 Front Side Bus Clock Select (BSEL[1:0]).................................................... 19
2.1.3 Phase Lock Loop (PLL) Power and Filter ..................................................... 20
2.2
Voltage Identification (VID) ................................................................................ 21
2.3
Cache Voltage Identification (CVID) ..................................................................... 22
2.4
Reserved, Unused, and TESTHI Pins..................................................................... 23
2.5
Mixing Processors.............................................................................................. 24
2.6
Front Side Bus Signal Groups .............................................................................. 24
2.7
GTL+ Asynchronous and AGTL+ Asynchronous Signals ........................................... 26
2.8
Test Access Port (TAP) Connection....................................................................... 27
2.9
Maximum Ratings.............................................................................................. 27
2.10 Processor DC Specifications ................................................................................ 28
2.10.1 Flexible Motherboard (FMB) Guidelines ...................................................... 28
2.10.2 VCC Overshoot Specification .................................................................... 34
2.10.3 VCACHE Overshoot Specification .............................................................. 35
2.10.4 Die Voltage Validation ............................................................................. 36
2.10.5 Clock, Miscellaneous and AGTL+ Specifications........................................... 36
2.11 AGTL+ Front Side Bus Specifications .................................................................... 40
3
Mechanical Specifications ........................................................................................ 41
3.1
Package Mechanical Drawing............................................................................... 42
3.2
Processor Component Keep-Out Zones ................................................................. 45
3.3
Package Loading Specifications ........................................................................... 45
3.4
Package Handling Guidelines............................................................................... 46
3.5
Package Insertion Specifications.......................................................................... 46
3.6
Processor Mass Specifications ............................................................................. 46
3.7
Processor Materials............................................................................................ 46
3.8
Processor Markings............................................................................................ 46
3.9
Processor Pin-Out Coordinates ............................................................................ 48
4
Pin Listing ............................................................................................................... 49
4.1
Dual-Core Intel® Xeon® Processor 7100 Series Pin Assignments ............................ 49
4.1.1 Pin Listing by Pin Name ........................................................................... 49
4.1.2 Pin Listing by Pin Number ........................................................................ 57
5
Signal Definitions .................................................................................................... 65
5.1
Signal Definitions .............................................................................................. 65
6
Thermal Specifications ............................................................................................ 73
6.1
Package Thermal Specifications ........................................................................... 73
6.1.1 Thermal Specifications ............................................................................ 73
6.1.2 Thermal Metrology ................................................................................. 77
6.2
Processor Thermal Features ................................................................................ 77
6.2.1 Thermal Monitor..................................................................................... 77
6.2.2 Thermal Monitor 2 .................................................................................. 78
6.2.3 On-Demand Mode .................................................................................. 79
6.2.4 PROCHOT# Signal Pin ............................................................................. 80
6.2.5 FORCEPR# Signal Pin.............................................................................. 80
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
3
6.2.6
6.2.7
6.2.8
THERMTRIP# Signal Pin ...........................................................................80
TCONTROL and Fan Speed Reduction ........................................................80
Thermal Diode........................................................................................81
7
Features ..................................................................................................................83
7.1
Power-On Configuration Options ..........................................................................83
7.2
Clock Control and Low Power States .....................................................................83
7.2.1 Normal State .........................................................................................84
7.2.2 HALT or Enhanced Power Down State ........................................................84
7.2.3 Stop-Grant State ....................................................................................85
7.2.4 Enhanced HALT Snoop State or HALT Snoop State,
Stop Grant Snoop State...........................................................................86
7.3
Enhanced Intel SpeedStep® Technology ...............................................................86
7.4
System Management Bus (SMBus) Interface .........................................................87
7.4.1 SMBus Device Addressing ........................................................................88
7.4.2 PIROM and Scratch EEPROM Supported SMBus Transactions.........................90
7.4.3 Processor Information ROM (PIROM) .........................................................90
7.4.4 Checksums .......................................................................................... 109
7.4.5 Scratch EEPROM ................................................................................... 110
7.4.6 SMBus Thermal Sensor.......................................................................... 110
7.4.7 Thermal Sensor Supported SMBus Transactions ........................................ 111
7.4.8 SMBus Thermal Sensor Registers ............................................................ 113
7.4.9 SMBus Thermal Sensor Alert Interrupt..................................................... 116
8
Boxed Processor Specifications.............................................................................. 117
8.1
Introduction .................................................................................................... 117
8.2
Mechanical Specifications .................................................................................. 118
8.2.1 Boxed Processor Heatsink Dimensions ..................................................... 118
8.2.2 Boxed Processor Heatsink Weight ........................................................... 125
8.2.3 Boxed Processor Retention Mechanism and Heatsink Supports .................... 125
8.3
Thermal Specifications...................................................................................... 125
8.3.1 Boxed Processor Cooling Requirements.................................................... 125
8.3.2 Boxed Processor Contents...................................................................... 126
9
Debug Tools Specifications .................................................................................... 127
9.1
Logic Analyzer Interface (LAI) ........................................................................... 127
9.1.1 Mechanical Considerations ..................................................................... 127
9.1.2 Electrical Considerations ........................................................................ 127
Figures
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
3-4
3-5
3-6
6-1
4
On-Die Front Side Bus Termination ......................................................................18
Phase Lock Loop (PLL) Filter Requirements............................................................20
Dual-Core Intel® Xeon® Processor 7100 Series Load Current vs. Time.....................30
VCC Static and Transient Tolerance ......................................................................32
VCACHE Static and Transient Tolerance at the Die Sense Location ............................33
VCACHE Static and Transient Tolerance at the Board ..............................................34
VCC Overshoot Example Waveform ......................................................................35
VCACHE Overshoot Example Waveform ................................................................36
Processor Package Assembly Sketch.....................................................................41
Processor Package Drawing (Sheet 1 of 2) ............................................................43
Processor Package Drawing (Sheet 2 of 2) ............................................................44
Processor Topside Markings.................................................................................47
Processor Bottom-Side Markings ..........................................................................47
Processor Pin-Out Coordinates, Top View ..............................................................48
150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile......................75
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
6-2
6-3
6-4
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile ....................... 76
Case Temperature (TCASE) Measurement Location ................................................ 77
Thermal Monitor 2 Frequency and Voltage Ordering ............................................... 79
Stop Clock State Machine ................................................................................... 85
Logical Schematic of SMBus Circuitry ................................................................... 88
Passive Dual-Core Intel® Xeon® Processor 7100 Series
Thermal Solution (3U and larger) ...................................................................... 118
Top Side Board Keep-Out Zones (Part 1) ............................................................ 119
Top Side Board Keep-Out Zones (Part 2) ............................................................ 120
Bottom Side Board Keep-Out Zones ................................................................... 121
Board Mounting-Hole Keep-Out Zones................................................................ 122
Thermal Solution Volumetric ............................................................................. 123
Recommended Processor Layout and Pitch.......................................................... 124
Tables
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
2-11
2-12
2-13
2-14
2-15
2-16
2-17
2-18
2-19
2-20
2-21
Features of the Dual-Core Intel® Xeon® Processor 7100 Series .............................. 12
166 MHz Core Frequency to Front Side Bus Multiplier Configuration.......................... 18
200 MHz Core Frequency to Front Side Bus Multiplier Configuration.......................... 19
BSEL[1:0] Frequency Table for BCLK[1:0] ............................................................ 19
Voltage Identification (VID) Definition .................................................................. 22
Cache Voltage Identification (CVID) Definition ....................................................... 23
Front Side Bus Pin Groups .................................................................................. 25
Signal Description Table ..................................................................................... 26
Signal Reference Voltages .................................................................................. 26
Processor Absolute Maximum Ratings................................................................... 27
Voltage and Current Specifications....................................................................... 28
VCC Static and Transient Tolerance ..................................................................... 31
VCACHE Static and Transient Tolerance at the Die Sense Location ........................... 33
VCACHE Static and Transient Tolerance at the Board.............................................. 34
VCC Overshoot Specification ............................................................................... 35
VCACHE Overshoot Specification ......................................................................... 35
Front Side Bus Differential BCLK Specifications ...................................................... 36
BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications .......................................... 37
VIDPWRGD DC Specifications.............................................................................. 37
AGTL+ Signal Group DC Specifications ................................................................. 38
PWRGOOD and TAP Signal Group DC Specifications................................................ 38
GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications .............................................................................................. 39
2-22 SMBus Signal Group DC Specifications ................................................................. 39
2-23 AGTL+ Bus Voltage Definitions ............................................................................ 40
3-1
Processor Loading Specifications ......................................................................... 45
3-2
Package Handling Guidelines............................................................................... 46
3-3
Processor Materials............................................................................................ 46
4-1
Pin Listing by Pin Name ...................................................................................... 49
4-2
Pin Listing by Pin Number ................................................................................... 57
5-1
Signal Definitions .............................................................................................. 65
6-1
Dual-Core Intel® Xeon® Processor 7100 Series Thermal Specifications .................... 74
6-2
150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile ..................... 75
6-3
95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile ....................... 76
7-1
Power-On Configuration Option Pins..................................................................... 83
7-2
Thermal Sensor SMBus Addressing ...................................................................... 89
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
5
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
6
Memory Device SMBus Addressing .......................................................................89
Read Byte SMBus Packet ....................................................................................90
Write Byte SMBus Packet ....................................................................................90
Processor Information ROM Data Sections .............................................................91
128 Byte ROM Checksum Values........................................................................ 109
Write Byte SMBus Packet .................................................................................. 111
Read Byte SMBus Packet .................................................................................. 111
Send Byte SMBus Packet .................................................................................. 111
Receive Byte SMBus Packet............................................................................... 111
ARA SMBus Packet ........................................................................................... 111
SMBus Thermal Sensor Command Byte Bit Assignments ....................................... 112
Thermal Value Register Encoding ....................................................................... 113
SMBus Thermal Sensor Status Register 1 ............................................................ 114
SMBus Thermal Sensor Status Register 2 ............................................................ 114
SMBus Thermal Sensor Configuration Register ..................................................... 114
SMBus Thermal Sensor Conversion Rate Register ................................................. 115
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Revision History
Document Number
Revision Number
Description
314553
001
•
Initial Release
314553
002
•
•
Added 3.5GHz at 667 ratio
Updated Processor Mixing
Release Date
August 2006
September 2006
§
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
7
8
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
„ Machine Check Architecture (MCA)
„ Available at 3.4, 3.33, 3.2, 3.16, 3.0, 2.6 or
2.5 GHz
„ Includes 16-KB Level 1 (L1) data cache
„ 65 nm process technology
„ 2 MB Advanced Transfer Cache (On-die, full
speed Level 2 (L2) Cache) with 8-way
associativity and Error Correcting Code (ECC)
„ Binary compatible with application running on
previous members of Intel's IA-32
microprocessor line
„ Intel® 64 architecture
„ Up to 16MB Level 3 (L3) Cache with 16-way
associativity and Error Correcting Code (ECC)
„ Intel NetBurst® microarchitecture
„ Intel® Cache Safe Technology
„ Hyper-Threading Technology
„ Fast 667 or 800 MHz system bus with Error
Correcting Code (ECC)
„ Hardware support for multithreaded
applications
„ Enables system support of up to 64 GB of
physical memory
„ Rapid Execution Engine: Arithmetic Logic
Units (ALUs) run at twice the processor core
frequency
„ Demand Based Switching (DBS) with
Enhanced Intel SpeedStep® Technology
„ Hyper Pipelined Technology
„ Enhanced thermal and power management
capabilities:
„ Advanced Dynamic Execution
— Thermal Monitor (TM1)
— Thermal Monitor 2 (TM2)
„ Very deep out-of-order execution
„ 144 Streaming SIMD Extensions 2 (SSE2)
instructions
„ Enhanced branch prediction
„ Intel® Virtualization Technology
„ 13 Streaming SIMD Extensions 3 (SSE3)
instructions
„ Execute Disable Bit
„ Enhanced floating-point and multimedia unit
for enhanced video, audio, encryption, and 3D
performance
„ System Management mode
The Dual-Core Intel® Xeon® processor 7100 series is designed for high-performance
multi-processor server applications for mid-tier enterprise serving and server consolidation.
Based on the Intel NetBurst® microarchitecture and the new Hyper-Threading Technology,
it is binary compatible with pervious Intel Architecture (IA-32) processors. The addition of
Intel® 64 architecture provides 64-bit computing and 40-bit addressing provides up to 1
Terabyte of direct memory addressability. The Dual-Core Intel Xeon processor 7100 series
is scalable to four processors and beyond in a multiprocessor system providing exceptional
performance for applications running on advanced operating systems such as Microsoft
Windows* 2003 server, and Linux* operating systems. The Dual-Core Intel Xeon processor
7100 series delivers compute power at unparalleled value and flexibility for internet
infrastructure and departmental server applications, including application servers,
databases, and business intelligence. The Intel NetBurst microarchitecture with
Hyper-Threading Technology and Intel 64 architecture delivers outstanding performance
and headroom from peak internet server workloads, resulting in faster response times,
support for more users, and improved scalability.
§
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
9
10
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Introduction
1
Introduction
The Dual-Core Intel® Xeon® Processor 7100 Series, Processor Number 7150, 7140,
7130, 7120 and 7110 is a dual core product for multi-processor servers. The Dual-Core
Intel Xeon processor 7100 series is a 64-bit server processor utilizing two physical Intel
NetBurst® microarchitecture cores in one package. It maintains the tradition of
compatibility with IA-32 software and includes features found in the Intel® Xeon®
processor such as Hyper Pipelined Technology, a Rapid Execution Engine, and an
Execution Trace Cache. Hyper Pipelined Technology includes a multi-stage pipeline,
allowing the processor to reach much higher core frequencies. The 667 MTS (Mega
Transfer per Seconds) front side bus is a quad-pumped bus running off a 166 MHz
system clock making 5.3 GB per second data transfer rates possible. The 800 MTS front
side bus (FSB) is a quad-pumped bus running off a 200 MHz system clock making
6.4 GB per second data transfer rates possible. The Execution Trace Cache is a level 1
(L1) cache that stores decoded micro-operations, which removes the decoder from the
main execution path, thereby increasing performance. In addition, the Dual-Core Intel
Xeon processor 7100 series includes the Intel® Extended Memory 64 Technology,
providing additional address capability.
In addition, enhanced thermal and power management capabilities are implemented,
including Thermal Monitor, Thermal Monitor 2 (TM2), and Enhanced Intel SpeedStep®
technology. Thermal Monitor and Thermal Monitor 2 provide efficient and effective
cooling in high temperature situations. Enhanced Intel SpeedStep technology allows
trade-offs to be made between performance and power consumption. This may lower
average power consumption (in conjunction with OS support).
The Dual-Core Intel Xeon processor 7100 series supports Hyper-Threading Technology.
This feature allows a single, physical processor to function as two logical processors.
While some execution resources such as caches, execution units, and buses are shared,
each logical processor has its own architectural state with its own set of generalpurpose registers, control registers to provide increased system responsiveness in
multitasking environments, and headroom for next generation multi-threaded
applications. More information on Hyper-Threading Technology can be found at
http://www.intel.com/technology/hyperthread.
Support for Intel's Execute Disable Bit functionality has been added which can prevent
certain classes of malicious “buffer overflow” attacks when combined with a supporting
operating system. Execute Disable Bit allows the processor to classify areas in memory
by where application code can execute and where it cannot. When a malicious worm
attempts to insert code in the buffer, the processor disables code execution, preventing
damage or worm propagation.
Other features within the Intel NetBurst microarchitecture include Advanced Dynamic
Execution, Advanced Transfer Cache, enhanced floating point and multi-media unit, and
Streaming SIMD Extensions 2 (SSE2). The Advanced Dynamic Execution improves
speculative execution and branch prediction internal to the processor. The Advanced
Transfer Cache is a 2 MB total on-die level 2 (L2) cache, organized as 1 MB dedicated
per core. The floating point and multi-media units include 128-bit wide registers and a
separate register for data movement. SSE2 instructions provide highly efficient doubleprecision floating point, SIMD integer, and memory management operations. In
addition, Streaming SIMD Extensions 3 (SSE3) instructions have been added to further
extend the capabilities of Intel processor technology. Other processor enhancements
include core frequency improvements and microarchitectural improvements.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
11
Introduction
The Dual-Core Intel Xeon processor 7100 series processor supports Intel® 64 as an
enhancement to Intel’s IA-32 architecture. This enhancement allows the processor to
execute operating systems and applications written to take advantage of the 64-bit
extension technology. Further details can be found in the 64-bit Extension Technology
Software Developer’s Guide at http://developer.intel.com/technology/64bitextensions/.
Dual-Core Intel Xeon processor 7100 series are intended for high performance multiprocessor server systems with support for up to two processors on a 667 or 800 MTS
FSB. Dual-Core Intel Xeon processor 7100 series will be available with 4 MB, 8 MB or
16 MB of on-die level 3 (L3) cache. All versions of the Dual-Core Intel Xeon processor
7100 series will include manageability features. Components of the manageability
features include an OEM EEPROM and Processor Information ROM which are accessed
through an SMBus interface and contain information relevant to the particular
processor and system in which it is installed.
Table 1-1.
Features of the Dual-Core Intel® Xeon® Processor 7100 Series
# of Supported
Symmetric Agents
Per FSB
Dual-Core Intel®
Xeon® Processor
7100 Series
1-2
L2 Advanced
Transfer Cache1
Integrated L3
Cache2
FSB
Frequency
2 MB total
(1 MB per core)
4 MB, 8 MB or
16 MB
667 or
800 MTS
Notes:
1.
Total accessible size of L2 caches may vary by one cache line pair (128 bytes) per core, depending on
usage and operating environment.
2.
Total accessible size of the L3 cache may vary by up to thirty-two (32) cache lines (64 bytes per line),
depending on usage and operating environment.
The Dual-Core Intel Xeon processor 7100 series is packaged in a 604-pin Flip-Chip
Micro Pin Grid Array (FC-mPGA6) package and utilizes a surface-mount Zero Insertion
Force (ZIF) mPGA604 socket. The Dual-Core Intel Xeon processor 7100 series supports
40-bit addressing, data bus ECC protection (single-bit error correction with double-bit
error detection), and the bus protocol addition of the Deferred Phase.
The Dual-Core Intel Xeon processor 7100 series uses a scalable system bus protocol
referred to as the “front side bus” in this document. The front side bus utilizes a splittransaction, deferred reply and Deferred Phase protocol. The front side bus uses
Source-Synchronous Transfer (SST) of address and data to improve performance. The
processor transfers data four times per bus clock (4X data transfer rate). Along with
the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a ‘double-clocked’, ‘double-pumped’, or the 2X address bus. In addition,
the Request Phase completes in one clock cycle. Working together, the 4X data bus and
2X address bus provide a data bus bandwidth of up to 5.3 GB (667 MTS) or 6.4 GB
(800 MTS) per second. Finally, the front side bus is also used to deliver interrupts.
The Dual-Core Intel Xeon processor 7100 series supports a threshold-based
mechanism for enhanced cache error reporting (IA32_MCG_CAP[11] = 1). Intel
recommends that fault prediction handlers rely on this mechanism to assess processor
cache health. Please refer to the IA-32 Intel® Architecture Software Developer’s
Manual, Volume 3A for more detailed information. Please note that the Dual-Core Intel
Xeon processor 7100 series does not support the newly added overwrite rules.
12
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Introduction
1.1
Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating that a signal
is in the asserted state when driven to a low level. For example, when RESET# is low
(i.e. when RESET# is asserted), a reset has been requested. Conversely, when NMI is
high (i.e. when NMI is asserted), a nonmaskable interrupt request has occurred. In the
case of signals where the name does not imply an active state but describes part of a
binary sequence (such as address or data), the ‘#’ symbol implies that the signal is
inverted. For example, D[3:0] = ‘HLHL’ refers to a hex ‘A’, and D[3:0]# = ‘LHLH’ also
refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“Front side bus” refers to the interface between the processor, system core logic (i.e.
the chipset components), and other bus agents. The front side bus supports
multiprocessing and cache coherency. For this document, “front side bus” is used as the
generic term for the “Dual-Core Intel Xeon processor 7100 series system bus”.
Commonly used terms are explained here for clarification:
• Enhanced Intel SpeedStep Technology — Enhanced Intel SpeedStep
Technology is the next generation implementation of the Geyserville technology
which extends power management capabilities of servers.
• FC-mPGA6 — The Dual-Core Intel Xeon processor 7100 series is available in a
Flip-Chip Micro Pin Grid Array 6 package, consisting of a processor core mounted
on a pinned substrate with an integrated heat spreader (IHS). This packaging
technology employs a 1.27 mm [0.05 in] pitch for the substrate pins.
• Front Side Bus (FSB) — The electrical interface that connects the processor to
the chipset. Also referred to as the processor system bus or the system bus. All
memory and I/O transactions as well as interrupt messages pass between the
processor and chipset over the FSB.
• Functional Operation — Refers to the normal operating conditions in which all
processor specifications, including DC, AC, system bus, signal quality, mechanical,
and thermal, are satisfied.
• Integrated Heat Spreader (IHS) — A component of the processor package used
to enhance the thermal performance of the package. Component thermal solutions
interface with the processor at the IHS surface.
• mPGA604 — The Dual-Core Intel Xeon processor 7100 series processor mates
with the system board through this surface mount, 604-pin, zero insertion force
(ZIF) socket.
• OEM — Original Equipment Manufacturer.
• Processor core — The processor’s execution engine. All AC timing and signal
integrity specifications are to the pads of the processor core.
• Processor Information ROM (PIROM) — A memory device located on the
processor and accessible via the System Management Bus (SMBus) which contains
information regarding the processor’s features. This device is shared with the
Scratch EEPROM, is programmed during manufacturing, and is write-protected.
• Scratch EEPROM (Electrically Erasable, Programmable Read-Only Memory)
— A memory device located on the processor and addressable via the SMBus which
can be used by the OEM to store information useful for system management.
• SMBus — System Management Bus. A two-wire interface through which simple
system and power management related devices can communicate with the rest of
the system. It is based on the principals of the operation of the I2C* two-wire serial
bus from Phillips Semiconductor.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
13
Introduction
Note:
I2C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset
of the I2C bus/protocol and was developed by Intel. Implementations of the I2C
bus/protocol or the SMBus bus/protocol may require licenses from various entities,
including Philips Electronics N.V. and North American Philips Corporation.
• Storage Conditions — Refers to a non-operational state. The processor may be
installed in a platform, in a tray, or loose. Processors may be sealed in packaging or
exposed to free air. Under these conditions, processor pins should not be connected
to any supply voltages, have any I/Os biased, or receive any clocks.
• Symmetric Agent - A symmetric agent is a processor which shares the same I/O
subsystem and memory array, and runs the same operating system as another
processor in a system. Systems using symmetric agents are known as Symmetric
MultiProcessing (SMP) systems. Dual-Core Intel Xeon processor 7100 series
processors should only be used in SMP systems which have two or fewer symmetric
agents per front side bus.
• Dual-Core Intel Xeon processor 7100 series — The entire product, including
processor core substrate and integrated heat spreader (IHS).
1.2
References
Material and concepts available in the following documents may be beneficial when
reading this document:
Document
Intel Order Number
Notes
AP-485, Intel® Processor Identification and the CPUID Instruction
241618
4
IA-32 Intel® Architecture Software Developer's Manual
• Volume 1: Basic Architecture
• Volume 2A: Instruction Set Reference, A-M
• Volume 2B: Instruction Set Reference, N-Z
• Volume 3A: System Programming Guide
• Volume 3B: System Programming Guide
253665
253666
253667
253668
253669
4
IA-32 Intel® Architecture Software Developer's Manual Documentation
Changes
252046
4
IA-32 Intel® Architecture Optimization Reference Manual
248966
4
Intel® Extended Memory 64 Technology Software Developer’s Manual
• Volume 1
• Volume 2
300834
300835
4
IA-32 Intel® Architecture and Intel® Extended Memory 64 Technology
Software Developer's Manual Documentation Changes
252046
Dual-Core Intel® Xeon® Processor 7100 Series Specification Update
314554
Dual-Core Intel® Xeon® Processor 7100 Series Boundary Scan
Descriptive Language (BSDL) Files
Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical
Design Guidelines
4
4
314555
4
Dual-Core Intel® Xeon® Processor 7100 Series Thermal Test Vehicle
and Cooling Solution Thermal Models
4
64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Cooling
Solution Mechanical Models
1
64-bit Intel® Xeon® Processor MP with up to 8MB L3 Cache Mechanical
Models
2
Cedar Mill Processor Family BIOS Writer’s Guide (BWG)
3
eXtended Debug Port: Debug Port Design Guide for MP Platforms
3
mPGA604 Socket Design Guidelines
14
4
254239
4
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Introduction
Document
Intel Order Number
Notes
Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator
Down (EVRD) 10.2 Design Guidelines
306760
4
VRM 9.1 DC-DC Converter Design Guidelines
306826
4
ATX/ATX12V Power Supply Design Guidelines
5
MPS Power Supply: A Server System Infrastructure (SSI) Specification
For Midrange Chassis Power Supplies
6
System Management Bus (SMBus) Specification
7
Notes:
1.
The Dual-Core Intel® Xeon® Processor 7100 Series utilizes the 64-bit Intel® Xeon® Processor MP with up
to 8MB L3 Cache Cooling Solution Mechanical Models in ProE* and IGES format which are available
electronically.
2.
The Dual-Core Intel® Xeon® Processor 7100 Series utilizes the 64-bit Intel® Xeon® Processor MP with up
to 8MB L3 Cache Mechanical Models in ProE* and IGES formats which are available electronically.
3.
Contact your Intel representative to receive the latest revisions of these documents.
4.
This collateral is available publicly at http://developer.intel.com.
5.
This document is available at http://www.formfactors.org.
6.
This document is available at http://www.ssiforum.org.
7.
This document is available at http://www.smbus.org.
1.3
State of Data
The data contained within this document is subject to change. It is the most accurate
information available by the publication date of this document. For processor stepping
info, refer to the Dual-Core Intel® Xeon® Processor 7100 Series Specification Update.
§
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
15
Introduction
16
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
2
Electrical Specifications
2.1
Front Side Bus and GTLREF
Most Dual-Core Intel® Xeon® Processor 7100 Series processor front side bus (FSB)
signals use Assisted Gunning Transceiver Logic (AGTL+) signaling technology. This
technology provides improved noise margins and reduced ringing through low voltage
swings and controlled edge rates. AGTL+ buffers are open-drain and require pull-up
resistors to provide the high logic level and termination. AGTL+ output buffers differ
from GTL+ buffers with the addition of an active pMOS pull-up transistor to “assist” the
pull-up resistors during the first clock of a low-to-high voltage transition. Platforms
implement a termination voltage level for AGTL+ signals defined as VTT. Because
platforms implement separate power planes for each processor, separate VCC and VTT
supplies are necessary. This configuration allows for improved noise tolerance as
processor frequency increases. Speed enhancements to data and address busses have
caused signal integrity considerations and platform design methods to become even
more critical than with previous processor families. Design guidelines for the processor
front side bus are detailed in the appropriate platform design guides (refer to
Section 1.2).
The AGTL+ inputs require a reference voltage (GTLREF) which is used by the receivers
to determine if a signal is a logical 0 or a logical 1. GTLREF must be generated on the
motherboard (see Table 2-23 for GTLREF specifications). Please refer to the appropriate
platform design guidelines for details. Termination resistors (RTT) for AGTL+ signals are
provided on the processor silicon and are terminated to VTT. The on-die termination
resistors are a selectable feature and can be enabled or disabled via the ODTEN signal.
For end bus agents, on-die termination resistors are enabled to control reflections on
the transmission line. For the middle bus agent, on-die termination RTT resistors must
be disabled. Intel chipsets will also provide on-termination, thus eliminating the need
to terminate the bus on the motherboard for most AGTL+ signals. Processor wired-OR
signals may also include additional on-die resistors (RL) to further ensure proper noise
margin and signal integrity. RL is not configurable and is always enabled for these
signals. See Table 2-7 for a list of these signals.
Figure 2-1 illustrates the active on-die termination.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
17
Electrical Specifications
Figure 2-1.
On-Die Front Side Bus Termination
End Agent
Middle Agent
V TT
R TT
Signal
Signal
RL
R TT - On-die termination resistors for AGTL+ signals
R L - Additional on-die resistance implemented for proper noise margin and
signal integrity (wired-OR signals only)
Note:
Some AGTL+ signals do not include on-die termination (RTT) and must be terminated
on the motherboard. See Table 2-7 for details regarding these signals.
2.1.1
Front Side Bus Clock and Processor Clocking
BCLK[1:0] directly controls the front side bus interface speed as well as the core
frequency of the processor. The Dual-Core Intel® Xeon® Processor 7100 Series
processor core frequency is a multiple of the BCLK[1:0] frequency. The processor bus
ratio multiplier will be set at its default ratio during manufacturing. The default setting
generates the maximum speed for the processor. It is possible to override this setting
using software. Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for details.
This will permit operation at a speed lower than the processor’s tested frequency.
The processor core frequency is configured during reset by using values stored
internally during manufacturing. The stored values set the highest bus fraction at which
the particular processor can operate. If lower speeds are desired, the appropriate bus
ratio multiplier can be configured by driving the A[21:16]# pins at reset. For details of
operation at core frequencies lower than the maximum rated processor speed, refer to
the Cedar Mill Processor Family BIOS Writer’s Guide.
The bus ratio multipliers supported are shown in Table 2-1 and Table 2-2. Other
combinations will not be validated or supported by Intel. For a given processor, only the
ratios which result in a core frequency equal to or less than the frequency marked on
the processor are supported.
Table 2-1.
18
166 MHz Core Frequency to Front Side Bus Multiplier Configuration
(Sheet 1 of 2)
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(166 MHz)
A21#
A20#
1/15
2.5 GHz
H
H
L
L
L
L
1/18
3 GHz
H
L
H
H
L
H
A19#
A18#
A17#
A16#
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-1.
166 MHz Core Frequency to Front Side Bus Multiplier Configuration
(Sheet 2 of 2)
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(166 MHz)
A21#
A20#
A19#
A18#
A17#
A16#
1/19
3.16 GHz
H
L
H
H
L
L
1/20
3.33 GHz
H
L
H
L
H
H
1/21
3.50 GHz
H
L
H
L
H
L
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series
Specification Update.
4.
As described in Section 1.1, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic
level (i.e. signal deasserted).
Table 2-2.
200 MHz Core Frequency to Front Side Bus Multiplier Configuration
Core Frequency
to Front Side Bus
Multiplier
Core Frequency
(200MHz)
A21#
A20#
A19#
A18#
A17#
A16#
1/13
2.6 GHz
H
H
L
L
H
L
1/15
3 GHz
H
H
L
L
L
L
1/16
3.20 GHz
H
L
H
H
H
H
1/17
3.40 GHz
H
L
H
H
H
L
Notes:
1.
Individual processors operate only at or below the frequency marked on the package.
2.
Listed frequencies are not necessarily committed production frequencies.
3.
For valid core frequencies of the processor, refer to the Dual-Core Intel® Xeon® Processor 7100 Series
Specification Update.
4.
As described in Section 1.1, “H” refers to a high logic level (i.e. signal asserted) and “L” refers to a low logic
level (i.e. signal deasserted).
The Dual-Core Intel Xeon processor 7100 series uses a differential clocking
implementation. For more information on the Dual-Core Intel Xeon processor 7100
series clocking, refer to the appropriate clock driver design guidelines.
2.1.2
Front Side Bus Clock Select (BSEL[1:0])
The BSEL[1:0] signals are used to select the frequency of the processor input clock
(BCLK[1:0]). Table 2-3 defines the possible combinations of the signals and the
frequency associated with each combination. The required frequency is determined by
the processor, chipset, and clock synthesizer. All processors must operate at the same
front side bus frequency.
The Dual-Core Intel Xeon processor 7100 series operates at a 667 MTS or 800 MTS
front side bus frequency (selected by a 166 MHz or 200 MHz BCLK[1:0] frequency).
Individual processors operate at the front side bus frequency specified by BSEL[1:0].
For more information about these pins, refer to Section 5.1 and the appropriate
platform design guide.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
19
Electrical Specifications
Table 2-3.
2.1.3
BSEL[1:0] Frequency Table for BCLK[1:0]
BSEL1
BSEL0
Function
0
0
RESERVED
0
1
RESERVED
1
0
200 MHz
1
1
166 MHz
Phase Lock Loop (PLL) Power and Filter
VCCA, VCCIOPLL, and VCCA_CACHE are power sources required by the PLL clock generators
on the Dual-Core Intel Xeon processor 7100 series. These are analog PLLs and they
require low noise power supplies for minimum jitter. These supplies must be low pass
filtered from VTT.
The AC low-pass requirements, with input at VTT, are as follows:
• < 0.2 dB gain in pass band
• < 0.5 dB attenuation in pass band < 1 Hz
• > 34 dB attenuation from 1 MHz to 66 MHz
• > 28 dB attenuation from 66 MHz to core frequency
The filter requirements are illustrated in Figure 2-2. For recommendations on
implementing the filter, refer to the appropriate platform design guide.
Figure 2-2.
Phase Lock Loop (PLL) Filter Requirements
0.2 dB
0 dB
-0.5 dB
forbidden
zone
-28 dB
forbidden
zone
-34 dB
DC
1 Hz
fpeak
1 MHz
66 MHz
fcore
high frequency
band
passband
Notes:
1.
Diagram not to scale.
2.
No specification for frequencies beyond fcore (core frequency).
20
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
3.
4.
2.2
fpeak, if existent, should be less than 0.05 MHz.
fcore represents the maximum core frequency supported by the platform.
Voltage Identification (VID)
The VID[5:0] pins supply the encodings that determine the voltage to be supplied by
the VCC (the core voltage for the Dual-Core Intel Xeon processor 7100 series) voltage
regulator. The VID specification for the Dual-Core Intel Xeon processor 7100 series is
defined by the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator
Down (EVRD) 10.2 Design Guidelines. The voltage set by the VID signals is the
maximum VCC voltage allowed by the processor. VID signals are open drain outputs,
which must be pulled up to VTT. Please refer to Table 2-17 for the DC specifications for
these signals. A minimum VCC voltage is provided in Table 2-10 and changes with
frequency. This allows processors running at a higher frequency to have a relaxed
minimum VCC voltage specification. The specifications have been set such that one
voltage regulator can work with all supported frequencies.
Individual processor VID values may be calibrated during manufacturing such that two
devices at the same core speed may have different default VID settings. Furthermore,
any Dual-Core Intel® Xeon® Processor 7100 Series processor, even those on the same
processor front side bus, can drive different VID settings during normal operation.
The Dual-Core Intel Xeon processor 7100 series uses six voltage identification pins,
VID[5:0], to support automatic selection of power supply voltages. Table 2-4 specifies
the voltage level corresponding to the state of VID[5:0]. A ‘1’ in this table refers to a
high voltage level and a ‘0’ refers to a low voltage level. If the processor socket is
empty (i.e. VID[5:0] = x11111), or the voltage regulation circuit cannot supply the
voltage that is requested, the processor’s voltage regulator must disable itself. See the
Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator-Down (EVRD)
10.2 Design Guidelines for more details.
The Dual-Core Intel Xeon processor 7100 series provides the ability to operate while
transitioning to an adjacent VID and its associated processor core voltage (VCC). This
will represent a DC shift in the load line. It should be noted that a low-to-high or highto-low voltage state change may result in as many VID transitions as necessary to
reach the target core voltage. Transitions above the specified VID are not permitted.
Table 2-10 includes VID step sizes and DC shift ranges. Minimum and maximum
voltages must be maintained as shown in Table 2-11 and Figure 2-4.
The VRM or VRD utilized must be capable of regulating its output to the value defined
by the new VID. DC specifications for VID transitions are included in Table 2-10 and
Table 2-11. Please refer to the Vcc Voltage Regulator Module (VRM) and Enterprise
Voltage Regulator-Down (EVRD) 10.2 Design Guidelines for further details.
Power source characteristics must be guaranteed to be stable whenever the supply to
the voltage regulator is stable.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
21
Electrical Specifications
Table 2-4.
VID5
VID4
Voltage Identification (VID) Definition
VID3
VID2
VID1
VID0
VID (V)
VID5
VID4
VID3
VID2
VID1
VID0
VID (V)
0
0
1
0
1
0
0.8375
0
1
1
0
1
0
1.2125
1
0
1
0
0
1
0.8500
1
1
1
0
0
1
1.2250
0
0
1
0
0
1
0.8625
0
1
1
0
0
1
1.2375
1
0
1
0
0
0
0.8750
1
1
1
0
0
0
1.2500
0
0
1
0
0
0
0.8875
0
1
1
0
0
0
1.2625
1
0
0
1
1
1
0.9000
1
1
0
1
1
1
1.2750
0
0
0
1
1
1
0.9125
0
1
0
1
1
1
1.2875
1
0
0
1
1
0
0.9250
1
1
0
1
1
0
1.3000
0
0
0
1
1
0
0.9375
0
1
0
1
1
0
1.3125
1
0
0
1
0
1
0.9500
1
1
0
1
0
1
1.3250
0
0
0
1
0
1
0.9625
0
1
0
1
0
1
1.3375
1
0
0
1
0
0
0.9750
1
1
0
1
0
0
1.3500
0
0
0
1
0
0
0.9875
0
1
0
1
0
0
1.3625
1
0
0
0
1
1
1.0000
1
1
0
0
1
1
1.3750
0
0
0
0
1
1
1.0125
0
1
0
0
1
1
1.3875
1
0
0
0
1
0
1.0250
1
1
0
0
1
0
1.4000
0
0
0
0
1
0
1.0375
0
1
0
0
1
0
1.4125
1
0
0
0
0
1
1.0500
1
1
0
0
0
1
1.4250
0
0
0
0
0
1
1.0625
0
1
0
0
0
1
1.4375
1
0
0
0
0
0
1.0750
1
1
0
0
0
0
1.4500
0
0
0
0
0
0
1.0875
0
1
0
0
0
0
1.4625
1
1
1
1
1
1
VRM off
1
0
1
1
1
1
1.4750
0
1
1
1
1
1
VRM off
0
0
1
1
1
1
1.4875
1
1
1
1
1
0
1.1000
1
0
1
1
1
0
1.5000
0
1
1
1
1
0
1.1125
0
0
1
1
1
0
1.5125
1
1
1
1
0
1
1.1250
1
0
1
1
0
1
1.5250
0
1
1
1
0
1
1.1375
0
0
1
1
0
1
1.5375
1
1
1
1
0
0
1.1500
1
0
1
1
0
0
1.5500
0
1
1
1
0
0
1.1625
0
0
1
1
0
0
1.5625
1
1
1
0
1
1
1.1750
1
0
1
0
1
1
1.5750
0
1
1
0
1
1
1.1875
0
0
1
0
1
1
1.5875
1
1
1
0
1
0
1.2000
1
0
1
0
1
0
1.6000
2.3
Cache Voltage Identification (CVID)
The CVID[3:0] pins supply the encodings that determine the voltage to be supplied by
the VCACHE (the L3 cache voltage for the Dual-Core Intel Xeon processor 7100 series)
voltage regulator. The CVID specification for the Dual-Core Intel Xeon processor 7100
22
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
series is defined by the VRM 9.1 DC-DC Converter Design Guidelines. The voltage set
by the CVID pins is the maximum VCACHE voltage allowed by the processor. A minimum
VCACHE voltage is provided in Table 2-10.
Dual-Core Intel Xeon processor 7100 series with the same front side bus frequency,
internal cache sizes, and stepping will have consistent CVID values.
The Dual-Core Intel Xeon processor 7100 series uses four voltage identification pins
(CVID[3:0]) to support automatic selection of power supply voltages. Table 2-5
specifies the voltage level corresponding to the state of CVID[3:0]. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the processor
socket is empty (in a single processor per regulator design), or if both processor
sockets are empty (in a two processors per regulator design), or the voltage regulation
circuit cannot supply the voltage that is requested, the processor’s voltage regulator
must disable itself. See the VRM 9.1 DC-DC Converter Design Guidelines for more
details.
Table 2-5.
Cache Voltage Identification (CVID) Definition
CVID3
CVID2
CVID1
CVID0
1
1
1
1
Off
1
1
1
0
1.100
1
1
0
1
1.125
1
1
0
0
1.150
1
0
1
1
1.175
1
0
1
0
1.200
1
0
0
1
1.225
1
0
0
0
1.250
0
1
1
1
1.275
0
1
1
0
1.300
0
1
0
1
1.325
0
1
0
0
1.350
0
0
1
1
1.375
0
0
1
0
1.400
0
0
0
1
1.425
0
0
0
0
1.450
Note:
2.4
CVID (V)
The voltage regulator will have a fifth VID input and, for VRM 10.2-compliant regulators, a sixth VID
input as well. The extra input(s) should be tied to a high voltage on the motherboard for correct
operation. Refer to the appropriate platform design guide for further implementation details.
Reserved, Unused, and TESTHI Pins
All RESERVED pins must be left unconnected. Connection of these pins to VCC, VSS, or
to any other signal (including each other) can result in component malfunction or
incompatibility with future processors. See Section 5 for a pin listing for the processor
and the location of all RESERVED pins.
For reliable operation, always terminate unused inputs or bidirectional signals to their
respective deasserted states. On-die termination has been included on the Dual-Core
Intel Xeon processor 7100 series to allow signals to be terminated within the processor
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
23
Electrical Specifications
silicon. Most unused AGTL+ inputs may be left as no-connects since AGTL+ termination
is provided on the processor silicon. See Table 2-7 for details on AGTL+ signals that do
not include on-die termination. Unused active-high inputs should be connected through
a resistor to ground (VSS). Unused outputs may be left unconnected. However, this may
interfere with some TAP functions, complicate debug probing, and prevent boundary
scan testing. A resistor must be used when tying bidirectional signals to power or
ground. When tying any signal to power or ground, a resistor will also allow for system
testability. For unused AGTL+ input or I/O signals, use pull-up resistors of the same
value as the on-die termination resistors (RTT). See Table 2-15.
Most TAP signals, GTL+ asynchronous inputs, and GTL+ asynchronous outputs do not
include on-die termination (see Table 2-7 for those signals which do not have on-die
termination). Inputs and used outputs must be terminated on the system board.
Unused outputs may be terminated on the system board or left connected. Note that
leaving unused outputs unterminated may interfere with some TAP functions,
complicate debug probing, and prevent boundary scan testing. Signal termination for
these signal types is discussed in the appropriate platform design guide and the
appropriate debug port design guide.
Don’t Care pins are pins on the processor package that are not connected to the
processor die. These pins can be connected on the motherboard in any way necessary
for compatible motherboard designs to support other processor versions.
The TESTHI pins should be tied to VTT using a matched resistor, where a matched
resistor has a resistance value within +/-20% of the impedance of the board
transmission line traces. For example, if the trace impedance is 50 Ω, then a value
between 40 Ω and 60 Ω is required.
The TESTHI pins may use individual pull-up resistors or be grouped together as
detailed below. Please note that utilization of boundary scan test will not be functional if
pins are connected together. A matched resistor should be used for each group:
• TESTHI[3:0]
• TESTHI[6:5]
• TESTHI4 --- cannot be grouped with other TESTHI signals
2.5
Mixing Processors
Intel supports and validates multi-processor configurations in which all processors
operate with the same front side bus frequency, core frequency and internal cache
sizes. Mixing processors operating at different internal clock frequencies is not
supported and will not be validated by Intel. Intel does not support or validate
operation of processors with different cache sizes. Mixing different processor steppings
but the same model (as per the CPUID instruction) is supported. Details on CPUID are
provided in the Cedar Mill Processor Family BIOS Writer’s Guide document and the
Intel® Processor Identification and the CPUID Instruction application note.
The Dual-Core Intel Xeon processor 7100 series does not support mixing of the 7110,
7120, 7130 or 7140 Processor Numbers. The Dual-Core Intel Xeon processor 7100
series does support mixing of the 7150 and 7140 Processor Numbers.
2.6
Front Side Bus Signal Groups
The front side bus signals are grouped by buffer type as listed in Table 2-6. The buffer
type indicates which AC and DC specifications apply to the signals. AGTL+ input signals
have differential input buffers that use GTLREF as a reference level. In this document,
24
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
the term “AGTL+ Input” refers to the AGTL+ input group as well as the AGTL+ I/O
group when receiving. Similarly, “AGTL+ Output” refers to the AGTL+ output group as
well as the AGTL+ I/O group when driving. AGTL+ asynchronous outputs can become
active anytime and include an active pMOS pull-up transistor to assist during the first
clock of a low-to-high voltage transition.
Implementing a source synchronous data bus requires specifying two sets of timing
parameters. One set is for common clock signals which are dependent upon the rising
edge of BCLK0 (ADS#, HIT#, HITM#, etc.). The second set is for the source
synchronous signals that are relative to their respective strobe lines (data and address)
as well as the rising edge of BCLK0. Asynchronous signals are present (A20M#,
IGNNE#, etc.) and can become active at any time during the clock cycle. Table 2-6
identifies signals as common clock, source synchronous, and asynchronous.
Table 2-6.
Front Side Bus Pin Groups
Signal Group
Signals1
Type
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, BR[3:1]#, DEFER#, ID[7:0]#, IDS#,
OOD#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#, BNR#, BPM[5:0]#,
BR0#, DBSY#, DP[3:0]#, DRDY#, HIT#,
HITM#, LOCK#, MCERR#
AGTL+ Source Synchronous I/
O
Synchronous to associated
strobe
Signals
REQ[4:0]#,
A[37:36,16:3]#
Associated Strobe
ADSTB0#
A[39:38,35:17]#
ADSTB1#
D[15:0]#,
DEP[1:0]#, DBI0#
DSTBP0#,
DSTBN0#
D[31:16]#,
DEP[3:2]#, DBI1#
DSTBP1#,
DSTBN1#
D[47:32]#,
DEP[5:4]#, DBI2#
DSTBP2#,
DSTBN2#
D[63:48]#,
DEP[7:6]#, DBI3#
DSTBP3#,
DSTBN3#
AGTL+ Strobe Input/Output
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL+ Asynchronous Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#
GTL+ Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#, STPCLK#
GTL+ Asynchronous Output
Asynchronous
THERMTRIP#
TAP Input
Synchronous to TCK
TCK, TDI, TMS
TAP Input
Asynchronous
TRST#
TAP Output
Synchronous to TCK
TDO
Front Side Bus Clock Input
Clock
BCLK[1:0]
SMBus
Synchronous to SM_CLK
SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP
Power/Other
Power/Other
BOOT_SELECT, BSEL[1:0], COMP0,
CVID[3:0], GTLREF[3:0], ODTEN, PWRGOOD,
RESERVED, SKTOCC#, SM_VCC, TEST_BUS,
TESTHI[6:0], VCACHE, VCC, VCCA,
VCC_CACHE_SENSE, VCCIOPLL, VCCPLL, VCCSENSE,
VID[5:0], VIDPWRGD, VSS, VSSA,
VSS_CACHE_SENSE, VSSSENSE, VTT, VTTEN
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
25
Electrical Specifications
Notes:
1.
Refer to Section 5.1 for signal descriptions.
Table 2-7.
Signal Description Table
Signals with RTT1
A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#, BNR#, BOOT_SELECT2, BPRI#, D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DEP[7:0]#, DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#, HIT#, HITM#, ID[7:0]#,
IDS#, LOCK#, MCERR#, OOD#, REQ[4:0]#, RS[2:0]#, RSP#, TRDY#
Signals with RL
BINIT#, BNR#, HIT#, HITM#, MCERR#
Notes:
1.
Signals not included in the “Signals with RTT” list require termination on the baseboard. Please refer to
Table 2-6 for the signal type and Table 2-17 to Table 2-22 for the corresponding DC specifications.
2.
The BOOT_SELECT pin is not terminated to RTT. It has a 500-5000 Ω internal pullup.
The ODTEN signals enables or disables RTT. Those signals affected by ODTEN still
present RTT termination to the signal’s pin when the processor is placed in tri-state
mode.
Furthermore, the following signals are not affected when the processor is placed in tristate mode: BSEL[1:0], CVID[3:0], SKTOCC#, SM_ALERT#, SM_CLK, SM_DAT,
SM_EP_A[2:0], SM_TS_A[1:0], SM_WP, TEST_BUS, TESTHI[6:0], VID[5:0], and
VTTEN.
Table 2-8.
Signal Reference Voltages
GTLREF
VTT / 2
A20M#, A[39:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#,
BINIT#, BNR#, BPM[5:0]#, BPRI#, BR[3:0]#,
D[63:0]#, DBI[3:0]#, DBSY#, DEFER#, DEP[7:0]#,
DP[3:0]#, DRDY#, DSTBN[3:0]#, DSTBP[3:0]#,
FORCEPR#, HIT#, HITM#, ID[7:0]#, IDS#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, LOCK#,
MCERR#, ODTEN, OOD#, REQ[4:0]#, RESET#,
RS[2:0]#, RSP#, SMI#, STPCLK#, TRDY#
BOOT_SELECT, PWRGOOD1, TCK1, TDI1, TMS1,
TRST#1, VIDPWRGD
Notes:
1.
These signals also have hysteresis added to the reference voltage. See Table 2-20 for more information.
2.7
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
The Dual-Core Intel® Xeon® Processor 7100 Series processor does not utilize CMOS
voltage levels on any signals that connect to the processor silicon. As a result, inputs
signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,
and STPCLK# utilize GTL buffers. Legacy output THERMTRIP# utilizes a GTL+ output
buffer. All of these asynchronous signals follow the same DC requirements as GTL+
signals; however, the outputs are not driven high (during the logical 0-to-1 transition)
by the processor. FERR#/PBE#, IERR#, and PROCHOT# have now been defined as
AGTL+ asynchronous signals as they include an active pMOS device. GTL+
asynchronous and AGTL+ asynchronous signals do not have setup or hold time
specifications in relation to BCLK[1:0]. However, all of the GTL+ asynchronous and
AGTL+ asynchronous signals are required to be asserted/deasserted for at least six
BCLKs in order for the processor to recognize the proper signal state, except during
power-on configuration. See Table 2-21 for the DC specifications for the GTL+
asynchronous and AGTL+ asynchronous signal groups.
26
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
2.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the TAP logic, Intel
recommends that the Dual-Core Intel® Xeon® Processor 7100 Series processor(s) be
first in the TAP chain, followed by any other components within the system. Use of a
translation buffer to connect to the rest of the chain is recommended unless one of the
other components is capable of accepting an input of the appropriate voltage. Similar
considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two copies of each
signal may be required, each driving a different voltage level.
2.9
Maximum Ratings
Table 2-9 specifies absolute maximum and minimum ratings. Within functional
operation limits, functionality and long-term reliability can be expected.
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. If a device is returned to conditions within functional operation limits after
having been subjected to conditions outside these limits, but within the absolute
maximum and minimum ratings, the device may be functional, but with its lifetime
degraded depending on exposure to conditions exceeding the functional operation
condition limits.
At conditions exceeding absolute maximum and minimum ratings, neither functionality
nor long-term reliability can be expected. Moreover, if a device is subjected to these
conditions for any length of time then, when returned to conditions within the
functional operating condition limits, it will either not function, or its reliability will be
severely degraded.
Although the processor contains protective circuitry to resist damage from static
electric discharge, precautions should always be taken to avoid high static voltages or
electric fields.
Table 2-9.
Processor Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Unit
VCC
Processor core supply voltage with
respect to VSS
-0.3
1.55
V
VCACHE
Processor L3 cache voltage with
respect to VSS
-0.3
1.55
V
VTT
Front side bus termination voltage
with respect to VSS
-0.3
1.55
V
TCASE
Processor case temperature
See Section 6
See Section 6
°C
TSTORAGE
Processor storage temperature
-40
85
°C
Notes1,2
3, 4
Notes:
1.
For functional operation, all processor electrical, signal quality, mechanical, and thermal specifications must
be satisfied.
2.
Overshoot and undershoot voltage guidelines for input, output, and I/O signals are outlined in Section 3.
Excessive overshoot or undershoot on any signal will likely result in permanent damage to the processor.
3.
Storage temperature is applicable to storage conditions only. In this scenario, the processor must not
receive a clock, and no pins can be connected to a voltage bias. Storage within these limits will not affect
the long-term reliability of the device. For functional operation, please refer to the processor case
temperature specifications.
4.
This rating applies to the processor and does not include any packaging or trays.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
27
Electrical Specifications
2.10
Processor DC Specifications
The following notes apply:
• The processor DC specifications in this section are defined at the processor core
silicon and not at the package pins unless noted otherwise.
• The notes associated with each parameter are part of the specification for that
parameter.
• Unless otherwise noted, all specifications in the tables apply to all frequencies and
cache sizes.
• Unless otherwise noted, all the specifications in the tables are based on estimates
and simulations. These specifications will be updated with characterized data from
silicon measurements at a later date.
See Section 5 for the pin signal definitions. Most of the signals on the processor front
side bus are in the AGTL+ signal group. The DC specifications for these signals are
listed in Table 2-19.
Table 2-10 through Table 2-22 list the DC specifications for the Dual-Core Intel®
Xeon® Processor 7100 Series processor and are valid only while meeting specifications
for case temperature, clock frequency, and input voltages.
2.10.1
Flexible Motherboard (FMB) Guidelines
The FMB guidelines are estimates of the maximum values that the Dual-Core Intel Xeon
processor 7100 series processor will have over certain time periods. The values are
only estimates as actual specifications for future processors may differ. The Dual-Core
Intel Xeon processor 7100 series may or may not have specifications equal to the FMB
value in the foreseeable future. System designers should meet the FMB values to
ensure that their systems will be compatible with future releases of the Dual-Core Intel
Xeon processor 7100 series.
Table 2-10. Voltage and Current Specifications (Sheet 1 of 2)
Symbol
Parameter
Core
Freq
VCC for processor core
All freq
VID step size during
transition
VID
Unit
Notes
1.1000 1.3500
V
1,2,3,
4,5,7
All freq.
± 12.5
mV
18
Total allowable DC load line
shift from VID steps
All freq.
450
mV
19
VCC for processor L3 cache
All freq.
1.1000 1.3500
V
17
VTT
FSB termination voltage
(DC specification)
All freq.
1.176
1.20
1.224
V
11,12,
13
VTT
FSB termination voltage
(AC specification)
All freq.
1.140
1.20
1.260
V
11,12,
13,14
SM_VCC
SMBus supply voltage
All freq.
3.135
3.300
3.465
V
13
ICC
ICC for processor core
All freq
135
A
7,10
ICC_TDC
Core Thermal Design
Current (TDC)
All freq
115
A
20
ICACHE
ICC for processor L3 cache
All freq
40
A
VID Range
VID Transition
CVID Range
28
Min
Typ
Max
Refer to Table 2-11
Refer to Table 2-12 or Table 2-13
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-10. Voltage and Current Specifications (Sheet 2 of 2)
Symbol
Parameter
Core
Freq
Min
Typ
Max
VID
Unit
Notes
Cache Thermal Design
Current (TDC)
All freq
35
A
ITT
FSB termination current
All freq.
4
A
11,15
ITT
FSB mid-agent current
All freq.
1.3
A
11,16
ICC for SMBus supply
All freq.
122.5
mA
11
ICACHE_TDC
ISM_VCC
100
ISGnt_CORE
ICC Stop-Grant Core
All freq.
70
A
6,9
ISGnt_CACHE
ICC Stop-Grant Cache
All freq.
35
A
6,9
ITCC
ICC TCC active
All freq.
ICC
A
8
ICC VCCA
ICC for PLL pin
All freq.
60
mA
ICC VCCIOPLL
ICC VCCA_CACHE
ICC GTLREF
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
ICC for I/O PLL pin
All freq.
60
mA
ICC for L3 cache PLL pin
All freq.
60
mA
ICC per GTLREF pin
All freq.
200
µA
Notes:
These voltages and frequencies are targets only. A variable voltage source should exist on systems in the event that a
different voltage is required. See Section 2.2 and Table 2-4 for more information.
The voltage specification requirements are measured across the VCCSENSE and VSSSENSE pins using an oscilloscope set to a
100 MHz bandwidth and probes that are 1.5 pF maximum capacitance and 1 MΩ minimum impedance at the processor socket.
The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not
coupled into the scope probe.
Refer to Table 2-11 for the minimum, typical, and maximum VCC allowed for a given current. The processor should not be
subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
Moreover, VCC should never exceed the VID voltage. Failure to adhere to this specification can shorten the processor lifetime.
VCC_MIN and VCC_MAX are defined at the frequency’s associated ICC_MAX on the VCC load line.
The current specified is also for the HALT State.
FMB is the Flexible Motherboard guideline. These guidelines are for estimation purposes only. See Section 2.10.1 for further
details on FMB guidelines.
The maximum instantaneous current the processor will draw while the thermal control circuit (TCC) is active as indicated by
the assertion of PROCHOT# is the same as the maximum ICC for the processor.
The core and cache portions of Stop-Grant current is specified at VCC and VCACHEmax.
Icc_Max specification is based on Vcc Maximum loadline. Refer to Figure 2-4 for details
These parameters are based on design characterization and are not tested.
VTT must be provided via a separate voltage source and must not be connected to VCC.
These specifications are measured at the package pin.
Baseboard bandwidth is limited to 20 MHz.
This specification refers to a single processor with RTT enabled.
This specification refers to a single processor with RTT disabled.
The voltage specification requirements are measured across the VCC_CACHE_SENSE and VSS_CACHE_SENSE pins at the socket with
a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum impedance. The maximum length
of ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the scope
probe.
This specification represents the VCC reduction due to each VID transition. See Section 2.2.
This specification refers to the total reduction of the load line due to VID transitions below the specified VID.
ICC_TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used for
the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and
asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for
further details. The processor is capable of drawing ICC_TDC indefinitely. Refer to Figure 2-3 for further details on the average
processor current draw over various time durations. This parameter is based on design characterization and is not tested.
ICACHE_TDC is the sustained (DC equivalent) current that the processor is capable of drawing indefinitely and should be used
for the voltage regulator temperature assessment. The voltage regulator is responsible for monitoring its temperature and
asserting the necessary signal to inform the processor of a thermal excursion. Please see the applicable design guidelines for
further details. The processor is capable of drawing ICACHE_TDC indefinitely. This parameter is based on design characterization
and is not tested.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
29
Electrical Specifications
Figure 2-3.
Dual-Core Intel® Xeon® Processor 7100 Series Load Current vs. Time
140
Sustained Current (A)
135
130
125
120
115
110
0 .0 1
0 .1
1
10
100
1000
T im e D u r a tio n (s )
Notes:
1.
Processor or voltage regulator thermal protection circuitry should not trip for load currents greater than
ICC_TDC.
2.
Not 100% tested. Specified by design characterization.
30
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-11. VCC Static and Transient Tolerance
ICC [A]
VCC_MAX [V]
VCC_TYP [V]
VCC_MIN [V]
Notes
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
80
85
90
95
100
105
110
115
120
125
130
135
VID - 0.000
VID - 0.006
VID - 0.013
VID - 0.019
VID - 0.025
VID - 0.031
VID - 0.038
VID - 0.044
VID - 0.050
VID - 0.056
VID - 0.063
VID - 0.069
VID - 0.075
VID - 0.081
VID - 0.087
VID - 0.094
VID - 0.100
VID - 0.106
VID - 0.113
VID - 0.119
VID - 0.125
VID - 0.131
VID - 0.138
VID - 0.144
VID - 0.150
VID - 0.156
VID - 0.163
VID - 0.169
VID - 0.020
VID - 0.026
VID - 0.033
VID - 0.039
VID - 0.045
VID - 0.051
VID - 0.058
VID - 0.064
VID - 0.070
VID - 0.076
VID - 0.083
VID - 0.089
VID - 0.095
VID - 0.101
VID - 0.108
VID - 0.114
VID - 0.120
VID - 0.126
VID - 0.133
VID - 0.139
VID - 0.145
VID - 0.151
VID - 0.158
VID - 0.164
VID - 0.170
VID - 0.176
VID - 0.183
VID - 0.189
VID - 0.040
VID - 0.046
VID - 0.053
VID - 0.059
VID - 0.065
VID - 0.071
VID - 0.078
VID - 0.084
VID - 0.090
VID - 0.096
VID - 0.103
VID - 0.109
VID - 0.115
VID - 0.121
VID - 0.128
VID - 0.134
VID - 0.140
VID - 0.146
VID - 0.153
VID - 0.159
VID - 0.165
VID - 0.171
VID - 0.178
VID - 0.184
VID - 0.190
VID - 0.196
VID - 0.203
VID - 0.209
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
1,2,3
Notes:
1.
The VCC_MIN and VCC_MAX load lines represent static and transient limits.
2.
This table is intended to aid in reading discrete points on Figure 2-4.
3.
The load lines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.2 Design
Guidelines for socket load line guidelines and VR implementation.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
31
Electrical Specifications
Figure 2-4.
VCC Static and Transient Tolerance
Icc [A]
0
5
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 135
VID - 0.000
VCC
Maximum
VID - 0.050
Vcc [V]
VID - 0.100
VID - 0.150
VCC
Typical
VID - 0.200
VCC
Minimum
VID - 0.250
Notes:
1.
The VCC_MIN and VCC_MAX load lines represent static and transient limits.
2.
Refer to Table 2-10 for processor VID information for VCC.
3.
The load lines specify voltage limits at the die measured at the VCCSENSE and VSSSENSE pins. Voltage
regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to
the Vcc Voltage Regulator Module (VRM) and Enterprise Voltage Regulator Down (EVRD) 10.2 Design
Guidelines for socket load line guidelines and VR implementation.
32
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-12. VCACHE Static and Transient Tolerance at the Die Sense Location
ICACHE [A]
V CACHE_MAX [V]
0
5
10
15
20
25
30
35
40
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
- 0.000
- 0.021
- 0.043
- 0.064
- 0.085
- 0.106
- 0.128
- 0.149
- 0.170
V CACHE_TYP [V]
V CACHE_MIN [V]
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
- 0.041
- 0.065
- 0.089
- 0.113
- 0.138
- 0.162
- 0.186
- 0.210
- 0.234
Notes
- 0.082
- 0.109
- 0.136
- 0.163
- 0.190
- 0.217
- 0.244
- 0.271
- 0.298
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Notes:
1.
ICACHE refers to the current drawn by a single Dual-Core Intel® Xeon® Processor 7100 Series cache. The
VCACHE_MIN loadline assumes two Dual-Core Intel® Xeon® Processor 7100 Series caches are powered off
one VRM and that the second cache is drawing ICACHE_MAX = 40A.
2.
VRM_MAX and VVRM_MIN are VRM voltage regulation requirements measured across the VCC_CACHE_SENSE and
VSS_CACHE_SENSE pins at the socket.
Figure 2-5.
VCACHE Static and Transient Tolerance at the Die Sense Location
Icache [A]
0
5
10
15
20
25
30
35
40
CV ID - 0.000
VCa ch e
Maxim um
CV ID - 0.050
Vcache [V]
CV ID - 0.100
CV ID - 0.150
CV ID - 0.200
VCa ch e
Typical
CV ID - 0.250
VCa ch e
Minim um
CV ID - 0.300
Notes:
1.
ICACHE refers to the current drawn by a single Dual-Core Intel Xeon processor 7100 series cache. The
VCACHE_MIN loadline assumes two Dual-Core Intel Xeon processor 7100 series caches are powered off one
VRM and that the second cache is drawing ICACHE_MAX = 40A.
2.
VRM_MAX and VVRM_MIN are VRM voltage regulation requirements measured across the VCC_CACHE_SENSE and
VSS_CACHE_SENSE pins at the socket.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
33
Electrical Specifications
Table 2-13. VCACHE Static and Transient Tolerance at the Board
ICACHE [A]
V CACHE_MAX [V]
0
5
10
15
20
25
30
35
40
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
- 0.000
- 0.003
- 0.006
- 0.009
- 0.011
- 0.014
- 0.017
- 0.020
- 0.023
V CACHE_TYP [V]
V CACHE_MIN [V]
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
CVID
- 0.041
- 0.044
- 0.048
- 0.051
- 0.055
- 0.058
- 0.061
- 0.065
- 0.068
Notes
- 0.082
- 0.086
- 0.090
- 0.094
- 0.098
- 0.102
- 0.106
- 0.110
- 0.114
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1,2
Notes:
1.
ICACHE refers to the current drawn by a single Dual-Core Intel Xeon processor 7100 series cache. The
VCACHE_MIN loadline assumes two Dual-Core Intel Xeon processor 7100 series caches are powered off one
VRM and that the second cache is drawing ICACHE_MAX = 40A.
2.
VVRM_MAX and VVRM_MIN are VRM voltage regulation requirements measured at the power plane reference
point (the VRM remote-sense point is on the system board, not at the socket.)
Figure 2-6.
VCACHE Static and Transient Tolerance at the Board
Icache [A]
0
5
10
15
20
25
30
35
40
CVID - 0.000
CVID - 0.020
VCache
Maximum
Vcache [V]
CVID - 0.040
CVID - 0.060
VCache
Typical
CVID - 0.080
VCache
Minimum
CVID - 0.100
CVID - 0.120
2.10.2
VCC Overshoot Specification
The Dual-Core Intel Xeon processor 7100 series can tolerate short transient overshoot
events where VCC exceeds the VID voltage when transitioning from a high-to-low
current load condition. This overshoot cannot exceed VID + VOS_MAX. (VOS_MAX is the
maximum allowable overshoot above VID). These specifications apply to the processor
die voltage as measured across the VCCSENSE and VSSSENSE pins.
34
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-14. VCC Overshoot Specification
Symbol
Parameter
VOS_MAX
TOS_MAX
Min
Max
Units
Figure
Magnitude of VCC
overshoot above VID
0.025
V
2-7
Time duration of VCC
overshoot above VID
5
μs
2-7
Figure 2-7.
VCC Overshoot Example Waveform
2.10.3
VCACHE Overshoot Specification
Notes
The Dual-Core Intel Xeon processor 7100 series can tolerate short transient overshoot
events where VCACHE exceeds the VCACHE maximum loadline voltage when transitioning
from a high-to-low current load condition. This overshoot cannot exceed VCACHE_MAX +
VOS_cache_MAX. (VOS_cache_MAX is the maximum allowable overshoot above
VCACHE_MAX at the low current load). These specifications apply to the processor cache
voltage as measured across the VCC_CACHE_SENSE and VSS_CACHE_SENSE pins.
Table 2-15. VCACHE Overshoot Specification
Symbol
Parameter
VOS_CACHE_MAX
TOS_CACHE_MAX
Min
Max
Units
Figure
Notes
Magnitude of VCACHE
overshoot above
VCACHE_MAX
0.025
V
2-8
1
Time duration of VCACHE
overshoot above
VCACHE_MAX
50
μs
2-8
Note:
1.
VCACHE_MAX is defined in Table 2-12 and Table 2-13 where ICACHE is the low, ending current of the high-tolow current load condition.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
35
Electrical Specifications
Figure 2-8.
VCACHE Overshoot Example Waveform
Vcache Overshoot Example Waveform
Vcache_max after
unloading transient
Vcache (10 mV per division)
VOS_cache
TOS_cache
Vcache_max prior to
unloading transient
Time (10 µs per division)
Notes:
1.
VOS_CACHE is measured overshoot voltage.
2.
TOS_CACHEis measured time duration above Vcache_max.
2.10.4
Die Voltage Validation
Overshoot events from application testing on the processor must meet the
specifications in Table 2-14 when measured across the VCCSENSE and VSSSENSE pins and
Table 2-15 when measured across the VCC_CACHE_SENSE and VSS_CACHE_SENSE pins.
Overshoot events that are < 10 ns in duration may be ignored. These measurements of
processor die level overshoot should be taken with a 100 MHz bandwidth limited
oscilloscope.
2.10.5
Clock, Miscellaneous and AGTL+ Specifications
Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
VL
Input Low Voltage
-0.150
0.000
N/A
V
VH
Input High Voltage
0.660
0.700
0.850
V
VCROSS(abs)
Absolute Crossing
Point
0.250
N/A
0.550
V
1,7
VCROSS(rel)
Relative Crossing
Point
0.250 + 0.5*
(VHavg - 0.700)
N/A
0.550 + 0.5*
(VHavg - 0.700)
V
2,7,8
Δ VCROSS
Range of Crossing
Point
N/A
N/A
0.140
V
Overshoot
N/A
N/A
+ 0.300
V
VOV
36
Notes
3
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-16. Front Side Bus Differential BCLK Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Notes
Undershoot
- 0.300
N/A
N/A
V
4
VRBM
Ringback Margin
0.200
N/A
N/A
V
5
VTM
Threshold Margin
VCROSS-0.100
VCROSS+0.100
V
6
VUS
Notes:
1.
Crossing voltage is defined as the instantaneous voltage value when the rising edge of BCLK0 is equal to
the falling edge of BCLK1.
2.
VHavg is the statistical average of the VH measured by the oscilloscope.
3.
Overshoot is defined as the absolute value of the maximum voltage.
4.
Undershoot is defined as the absolute value of the minimum voltage.
5.
Ringback Margin is defined as the absolute voltage difference between the maximum Rising Edge Ringback
and the maximum Falling Edge Ringback.
6.
Threshold Region is defined as a region entered around the crossing point voltage in which the differential
receiver switches. It includes input threshold hysteresis.
7.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
8.
VHavg can be measured directly using “Vtop” on Agilent scopes and “High” on Tektronix scopes.
Table 2-17.BSEL[1:0], VID[5:0], and CVID[3:0] DC Specifications
Symbol
RON
Rpull_up
Parameter
Typ
Buffer On Resistance
Pull up resistor to 3.3V
Max
Unit
Notes
80
Ω
1
Ω
2
1000
IOL
Max Pin Current
8
mA
ILO
Output Leakage Current
200
µA
3
Voltage Tolerance
3.3 * 1.05
V
4
VTOL
Notes:
1.
These parameters are not tested and are based on design simulations.
2.
Pull up each line to 3.3 V using 1 KΩ, 5% resistor. Refer to 64-bit Intel® Xeon™ Processor MP Platform
Design Guide.
3.
Leakage to VSS with pin held at 2.5 V.
4.
Represents the maximum allowable termination voltage.
Table 2-18. VIDPWRGD DC Specifications
Symbol
Parameter
Min
Max
Unit
VIL
Input Low Voltage
0.0
0.30
V
VIH
Input High Voltage
0.90
VTT
V
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Notes
37
Electrical Specifications
Table 2-19. AGTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
VIL
Input Low Voltage
0.0
GTLREF - (0.10 * VTT)
V
1,3
VIH
Input High Voltage
GTLREF + (0.10 * VTT)
VTT
V
2,3
VOH
Output High Voltage
0.90 * VTT
VTT
V
3
IOL
Output Low Current
N/A
VTT /
(0.50 * Rtt_min +
RON_min || RL)
mA
5
ILI
Input Leakage Current
N/A
4
Output Leakage Current
N/A
± 200
± 200
µA
ILO
µA
6
RON
Buffer On Resistance
8
12
Ω
Notes:
1.
VIL is defined as the voltage level at a receiving agent that will be interpreted as a logical low value.
2.
VIH is defined as the voltage level at a receiving agent that will be interpreted as a logical high value.
3.
The VTT referred to in these specifications refers to the instantaneous VTT.
4.
Leakage to VSS with pin held at VTT.
5.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6.
Leakage to VTT with pin held at 300 mV.
Table 2-20. PWRGOOD and TAP Signal Group DC Specifications
Symbol
VHYS
VT+
VTVOH
Parameter
Min
Max
Unit
Notes1
Input Hysteresis
120
396
mV
5
PWRGOOD Input Low to
High Threshold Voltage
0.5 (VTT + VHYS_MIN +
0.24)
0.5 * (VTT + VHYS_MAX +
0.24)
V
3, 6
TAP Input Low to High
Threshold Voltage
0.5 * (VTT + VHYS_MIN)
0.5 * (VTT + VHYS_MAX)
V
3
PWRGOOD Input High to
Low Threshold Voltage
0.4 * VTT
0.6 * VTT
V
3
TAP Input High to Low
Threshold Voltage
0.5 * (VTT - VHYS_MAX)
0.5 * (VTT - VHYS_MIN)
V
3
Output High Voltage
N/A
VTT
V
2,3
4
IOL
Output Low Current
45
mA
ILI
Input Leakage Current
±200
µA
ILO
Output Leakage Current
±200
µA
RON
Buffer On Resistance
8
12
Ω
RON
TDO Buffer On
Resistance
7
12
Ω
Notes:
1.
All outputs are open drain.
2.
TAP signal group must meet system signal quality specification in Chapter 3.
3.
The VTT referred to in these specifications refers to instantaneous VTT.
4.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
5.
VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT for all TAP inputs.
6.
0.24 V is defined at 20% of nominal VTT of 1.2 V.
38
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Electrical Specifications
Table 2-21. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
Symbol
VIL
Parameter
Min
Max
Unit
Notes
Input Low Voltage
0
GTLREF - (10% * VTT)
V
2
VIH
Input High Voltage
GTLREF + (10% * VTT)
VTT
V
3,4
VIL
A20M#, SMI#, IGNNE#
Input Low Voltage
0
0.4 * VTT
V
2
VIH
A20M#, SMI#, IGNNE#
Input High Voltage
0.6 * VTT
VTT
V
3,4
VOH
Output High Voltage
VTT
V
1,4
IOL
Output Low Current
ILI
Input Leakage Current
ILO
Output Leakage Current
Ron
Buffer On Resistance
50
mA
5
N/A
± 200
± 200
µA
6
µA
7
8
12
Ω
Notes:
1.
All outputs are open-drain.
2.
VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
4.
The VTT referred to in these specifications refers to instantaneous VTT.
5.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
6.
Leakage to VSS with pin held at VTT
7.
Leakage to VTT with pin held at 300 mV.
Table 2-22. SMBus Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Input Low Voltage
-0.30
0.30 * SM_VCC
V
VIH
Input High Voltage
0.70 * SM_VCC
3.465
V
VOL
Output Low Voltage
0
0.400
V
3.0
mA
VIL
IOL
Output Low Current
N/A
ILI
Input Leakage Current
N/A
ILO
Output Leakage Current
N/A
CSMB
SMBus Pin Capacitance
±
±
10
µA
10
µA
15.0
pF
Notes 1,2
3
Notes:
1.
These parameters are based on design characterization and are not tested.
2.
All DC specifications for the SMBus signal group are measured at the processor pins.
3.
Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
39
Electrical Specifications
2.11
AGTL+ Front Side Bus Specifications
Routing topology recommendations are in the appropriate platform design guide.
Termination resistors are not required for most AGTL+ signals because they are
integrated into the processor silicon.
Valid high and low levels are determined by the input buffers which compare a signal’s
voltage with a reference voltage called GTLREF.
Table 2-23 lists the GTLREF specifications. GTLREF should be generated on the system
board using high-precision voltage divider circuits. For more details on platform design,
see the appropriate platform design guide.
Table 2-23. AGTL+ Bus Voltage Definitions
Symbol
Parameter
Min
Typ
Max
Units
Notes
0.98 * (0.63 *
VTT)
0.63 * VTT
1.02 * (0.63 *
VTT)
V
1,2,6
45
50
55
Ω
3
Termination
Resistance (pulldown)
360
450
540
Ω
4
COMP Resistance
49.4
49.9
50.4
Ω
5
GTLREF
Bus Reference
Voltage
RTT
Termination
Resistance (pull-up)
RL
COMP0
Notes:
1.
The tolerances for this specification have been stated generically to enable system designers to calculate
the minimum values across the range of VTT.
2.
GTLREF is generated from VTT on the baseboard by a voltage divider of 1% resistors.
3.
RTT is the on-die termination resistance measured at VTT/2 of the AGTL+ output driver.
4.
RL is the on-die termination resistance for improved noise margin and signal integrity.
5.
The COMP0 resistor is provided by the baseboard with 1% resistors. See the appropriate platform design
guide for implementation details.
6.
The VTT referred to in these specifications refers to instantaneous VTT.
§
40
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Mechanical Specifications
3
Mechanical Specifications
The Dual-Core Intel Xeon processor 7100 series is packaged in a Flip-Chip Micro Pin
Grid Array 6 (FC-mPGA6) package that interfaces with the motherboard via a mPGA604
socket. The package consists of a processor core mounted on a substrate pin-carrier.
An integrated heat spreader (IHS) is attached to the package substrate and core and
serves as the mating surface for processor component thermal solutions, such as a
heatsink. Figure 3-1 shows a sketch of the processor package components and how
they are assembled together. Refer to the mPGA604 Socket Design Guidelines for
complete details on the mPGA604 socket.
The package components shown in Figure 3-1 include the following:
1. Integrated Heat Spreader (IHS)
2. Processor die
3. FC-mPGA6 package
4. Pin-side capacitors
5. Package pin
Figure 3-1.
Processor Package Assembly Sketch
1
2
3
4
Note:
5
This drawing is not to scale and is for reference only. The mPGA604 socket is not
shown.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
41
Mechanical Specifications
3.1
Package Mechanical Drawing
The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The
drawings include dimensions necessary to design a thermal solution for the processor.
These dimensions include:
1. Package reference with tolerances (total height, length, width, etc.)
2. IHS parallelism and tilt
3. Pin dimensions
4. Top-side and back-side component keep-out dimensions
5. Reference datums
All drawing dimensions are in millimeters.
42
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Mechanical Specifications
Figure 3-2.
Processor Package Drawing (Sheet 1 of 2)
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
43
Mechanical Specifications
Figure 3-3.
44
Processor Package Drawing (Sheet 2 of 2)
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Mechanical Specifications
3.2
Processor Component Keep-Out Zones
The processor may contain components on the substrate that define component keepout zone requirements. A thermal and mechanical solution design must not intrude into
the required keep-out zones. Decoupling capacitors are typically mounted to either the
topside or pin-side of the package substrate. See Figure 3-2 and Figure 3-3 for keepout
zones.
3.3
Package Loading Specifications
Table 3-1 provides dynamic and static load specifications for the processor package.
These mechanical load limits should not be exceeded during heatsink assembly,
shipping conditions, or standard use condition. Also, any mechanical system or
component testing should not exceed the maximum limits. The processor package
substrate should not be used as a mechanical reference or load-bearing surface for
thermal and mechanical solutions. The minimum loading specification must be
maintained by any thermal and mechanical solution.
Table 3-1.
Processor Loading Specifications
Parameter
Minimum
Maximum
Unit
Notes
Static Compressive
Load
44
10
222
50
N
lbf
1, 2, 3, 4
44
10
288
65
N
lbf
1, 2, 3, 5
222 N + 0.45 kg * 100 G
50 lbf (static) + 1 lbm * 100 G
N
lbf
1, 3, 4, 6, 7
288 N + 0.45 kg * 100 G
65 lbf (static) + 1 lbm * 100 G
N
lbf
1, 3, 5, 6, 7
445
100
N
lbf
1, 3, 8
Dynamic
Compressive Load
Transient
Notes:
1.
These specifications apply to uniform compressive loading in a direction perpendicular to the IHS top
surface.
2.
This is the minimum and maximum static force that can be applied by the heatsink and retention solution
to maintain the heatsink and processor interface.
3.
These parameters are based on limited testing for design characterization. Loading limits are for the
package only and do not include the limits of the processor socket.
4.
This specification applies for thermal retention solutions that allow baseboard deflection.
5.
This specification applies either for thermal retention solutions that prevent baseboard deflection or for the
Intel enabled reference solution (CEK).
6.
Dynamic loading is defined as an 11 ms duration average load superimposed on the static load
requirement.
7.
Experimentally validated test condition used a heatsink mass of 1 lbm (~0.45 kg) with 100 G acceleration
measured at heatsink mass. The dynamic portion of this specification in the product application can have
flexibility in specific values, but the ultimate product of mass times acceleration should not exceed this
validated dynamic load (1 lbm x 100 G = 100 lb).
8.
Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,
representative of loads experienced by the package during heatsink installation.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
45
Mechanical Specifications
3.4
Package Handling Guidelines
Table 3-2 includes a list of guidelines on package handling in terms of recommended
maximum loading on the processor IHS relative to a fixed substrate. These package
handling loads may be experienced during heatsink removal.
Table 3-2.
Package Handling Guidelines
Parameter
Maximum Recommended
Notes
Shear
356 N [80 lbf]
1, 4, 5
Tensile
156 N [35 lbf]
2, 4, 5
Torque
8 N-m [70 lbf-in]
3, 4, 5
Notes:
1.
A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.
2.
A tensile load is defined as a pulling load applied to the IHS in the direction normal to the IHS surface.
3.
A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top
surface.
4.
These guidelines are based on limited testing for design characterization and incidental applications (one
time only).
5.
Handling guidelines are for the package only and do not include the limits of the processor socket.
3.5
Package Insertion Specifications
The Dual-Core Intel Xeon processor 7100 series can be inserted into and removed from
a mPGA604 socket 15 times. The socket should meet the mPGA604 requirements
detailed in the mPGA604 Socket Design Guidelines.
3.6
Processor Mass Specifications
The typical mass of the Dual-Core Intel Xeon processor 7100 series is 34 g [1.20 oz].
This mass [weight] includes all the components that are included in the package.
3.7
Processor Materials
Table 3-3 lists some of the package components and associated materials.
Table 3-3.
3.8
Processor Materials
Component
Material
Integrated Heat Spreader (IHS)
Nickel Plated Copper
Substrate
Fiber-Reinforced Resin
Substrate Pins
Gold Plated Copper
Processor Markings
Figure 3-4 shows the topside markings and Figure 3-5 shows the bottom-side markings
on the processor. These diagrams are to aid in the identification of the Dual-Core Intel
Xeon processor 7100 series.
46
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Mechanical Specifications
Figure 3-4.
Processor Topside Markings
Processor Name
i(m) ©’05
2D Matrix
Includes ATPO and Serial
Number (front end mark)
Pin 1 Indicator
Notes:
1.
All characters will be in upper case.
2.
Drawing is not to scale.
Figure 3-5.
Processor Bottom-Side Markings
Pin 1 Indicator
Processor/Speed/Cache/Bus
Number
Pin Field
Cavity
with
Components
7140M 3400/16M/800
S-Spec
SL9HA COSTA RICA
Country of Assy
C0096109-0021
FPO – Serial #
(13 Characters)
Text Line1
Text Line2
Text Line3
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
47
Mechanical Specifications
3.9
Processor Pin-Out Coordinates
Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are
referred to throughout the document to identify processor pins.
Figure 3-6.
Processor Pin-Out Coordinates, Top View
COMMON
CLOCK
3
5
7
9
11
13
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
15
17
19
21
23
Async /
JTAG
25
27
29
31
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
Processor
Top View
Vcc/Vss
Vcc/Vcache/Vss
1
COMMON
CLOCK
ADDRESS
AD
AE
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
DATA
CLOCKS
= Signal
= VCC
= Ground
= VTT
= Reserved/No Connect
= VCache
§
48
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
4
Pin Listing
4.1
Dual-Core Intel® Xeon® Processor 7100 Series
Pin Assignments
Section 2.6 contains the front side bus signal groups for the Dual-Core Intel Xeon
processor 7100 series (see Table 2-6). This section provides a sorted pin list in
Table 4-1 and Table 4-2. Table 4-1 is a listing of all processor pins ordered
alphabetically by pin name. Table 4-2 is a listing of all processor pins ordered by pin
number.
4.1.1
Pin Listing by Pin Name
Table 4-1. Pin Listing by Pin Name
(Sheet 2 of 16)
Table 4-1. Pin Listing by Pin Name
(Sheet 1 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Direction
Pin Name
Pin No.
Signal Buffer
Type
Direction
A3#
A22
Source Sync
Input/Output
A30#
C11
Source Sync
Input/Output
A4#
A20
Source Sync
Input/Output
A31#
B7
Source Sync
Input/Output
A6
Source Sync
Input/Output
A5#
B18
Source Sync
Input/Output
A32#
A6#
C18
Source Sync
Input/Output
A33#
A7
Source Sync
Input/Output
C9
Source Sync
Input/Output
A7#
A19
Source Sync
Input/Output
A34#
A8#
C17
Source Sync
Input/Output
A35#
C8
Source Sync
Source Sync
F16
Source Sync
Source Sync
A9#
D17
Source Sync
Input/Output
A36#
A10#
A13
Source Sync
Input/Output
A37#
F22
Source Sync
Source Sync
A38#
B6
Source Sync
Source Sync
A11#
B16
Source Sync
Input/Output
A12#
B14
Source Sync
Input/Output
A39#
C16
Source Sync
Source Sync
A20M#
F27
Async GTL+
Input
A13#
B13
Source Sync
Input/Output
A14#
A12
Source Sync
Input/Output
ADS#
D19
Common Clk
Input/Output
F17
Source Sync
Input/Output
A15#
C15
Source Sync
Input/Output
ADSTB0#
A16#
C14
Source Sync
Input/Output
ADSTB1#
F14
Source Sync
Input/Output
AP0#
E10
Common Clk
Input/Output
A17#
D16
Source Sync
Input/Output
A18#
D15
Source Sync
Input/Output
AP1#
D9
Common Clk
Input/Output
BCLK0
Y4
FSB Clk
Input
A19#
F15
Source Sync
Input/Output
A20#
A10
Source Sync
Input/Output
BCLK1
W5
FSB Clk
Input
BINIT#
F11
Common Clk
Input/Output
A21#
B10
Source Sync
Input/Output
A22#
B11
Source Sync
Input/Output
BNR#
F20
Common Clk
Input/Output
G7
Power/Other
Input
A23#
C12
Source Sync
Input/Output
BOOT_SELECT
A24#
E14
Source Sync
Input/Output
BPM0#
F6
Common Clk
Input/Output
F8
Common Clk
Input/Output
A25#
D13
Source Sync
Input/Output
BPM1#
A26#
A9
Source Sync
Input/Output
BPM2#
E7
Common Clk
Input/Output
F5
Common Clk
Input/Output
A27#
B8
Source Sync
Input/Output
BPM3#
A28#
E13
Source Sync
Input/Output
BPM4#
E8
Common Clk
Input/Output
Input/Output
BPM5#
E4
Common Clk
Input/Output
A29#
D12
Source Sync
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
49
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 3 of 16)
50
Table 4-1. Pin Listing by Pin Name
(Sheet 4 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Direction
Pin Name
Pin No.
Signal Buffer
Type
Direction
BPRI#
D23
Common Clk
Input
D28#
AE20
Source Sync
Input/Output
BR0#
D20
Common Clk
Input/Output
D29#
AD21
Source Sync
Input/Output
BR1#
F12
Common Clk
Input
D30#
AD19
Source Sync
Input/Output
BR2#
E11
Common Clk
Input
D31#
AB17
Source Sync
Input/Output
BR3#
D10
Common Clk
Input
D32#
AB16
Source Sync
Input/Output
BSEL0
AA3
Power/Other
Output
D33#
AA16
Source Sync
Input/Output
BSEL1
AB3
Power/Other
Output
D34#
AC17
Source Sync
Input/Output
COMP0
AD16
Power/Other
Input
D35#
AE13
Source Sync
Input/Output
CVID0
E2
Power/Other
Output
D36#
AD18
Source Sync
Input/Output
CVID1
D1
Power/Other
Output
D37#
AB15
Source Sync
Input/Output
CVID2
C2
Power/Other
Output
D38#
AD13
Source Sync
Input/Output
CVID3
A2
Power/Other
Output
D39#
AD14
Source Sync
Input/Output
D0#
Y26
Source Sync
Input/Output
D40#
AD11
Source Sync
Input/Output
D1#
AA27
Source Sync
Input/Output
D41#
AC12
Source Sync
Input/Output
D2#
Y24
Source Sync
Input/Output
D42#
AE10
Source Sync
Input/Output
D3#
AA25
Source Sync
Input/Output
D43#
AC11
Source Sync
Input/Output
D4#
AD27
Source Sync
Input/Output
D44#
AE9
Source Sync
Input/Output
D5#
Y23
Source Sync
Input/Output
D45#
AD10
Source Sync
Input/Output
D6#
AA24
Source Sync
Input/Output
D46#
AD8
Source Sync
Input/Output
D7#
AB26
Source Sync
Input/Output
D47#
AC9
Source Sync
Input/Output
D8#
AB25
Source Sync
Input/Output
D48#
AA13
Source Sync
Input/Output
D9#
AB23
Source Sync
Input/Output
D49#
AA14
Source Sync
Input/Output
D10#
AA22
Source Sync
Input/Output
D50#
AC14
Source Sync
Input/Output
D11#
AA21
Source Sync
Input/Output
D51#
AB12
Source Sync
Input/Output
D12#
AB20
Source Sync
Input/Output
D52#
AB13
Source Sync
Input/Output
D13#
AB22
Source Sync
Input/Output
D53#
AA11
Source Sync
Input/Output
D14#
AB19
Source Sync
Input/Output
D54#
AA10
Source Sync
Input/Output
D15#
AA19
Source Sync
Input/Output
D55#
AB10
Source Sync
Input/Output
D16#
AE26
Source Sync
Input/Output
D56#
AC8
Source Sync
Input/Output
D17#
AC26
Source Sync
Input/Output
D57#
AD7
Source Sync
Input/Output
D18#
AD25
Source Sync
Input/Output
D58#
AE7
Source Sync
Input/Output
D19#
AE25
Source Sync
Input/Output
D59#
AC6
Source Sync
Input/Output
D20#
AC24
Source Sync
Input/Output
D60#
AC5
Source Sync
Input/Output
D21#
AD24
Source Sync
Input/Output
D61#
AA8
Source Sync
Input/Output
D22#
AE23
Source Sync
Input/Output
D62#
Y9
Source Sync
Input/Output
D23#
AC23
Source Sync
Input/Output
D63#
AB6
Source Sync
Input/Output
D24#
AA18
Source Sync
Input/Output
DBI0#
AC27
Source Sync
Input/Output
D25#
AC20
Source Sync
Input/Output
DBI1#
AD22
Source Sync
Input/Output
D26#
AC21
Source Sync
Input/Output
DBI2#
AE12
Source Sync
Input/Output
D27#
AE22
Source Sync
Input/Output
DBI3#
AB9
Source Sync
Input/Output
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 5 of 16)
Table 4-1. Pin Listing by Pin Name
(Sheet 6 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Direction
Pin Name
Pin No.
Signal Buffer
Type
Direction
DBSY#
F18
Common Clk
Input/Output
ID1#
B26
Common Clk
Input
DEFER#
C23
Common Clk
Input
ID2#
D25
Common Clk
Input
DEP0#
AD31
Source Sync
Input/Output
ID3#
D27
Common Clk
Input
DEP1#
AD30
Source Sync
Input/Output
ID4#
C28
Common Clk
Input
DEP2#
AE16
Source Sync
Input/Output
ID5#
B29
Common Clk
Input
DEP3#
AE15
Source Sync
Input/Output
ID6#
B30
Common Clk
Input
DEP4#
AE8
Source Sync
Input/Output
ID7#
A30
Common Clk
Input
DEP5#
AD6
Source Sync
Input/Output
IDS#
A28
Common Clk
Input
DEP6#
AC4
Source Sync
Input/Output
IERR#
E5
Async GTL+
Output
DEP7#
AA4
Source Sync
Input/Output
IGNNE#
C26
Async GTL+
Input
DP0#
AC18
Common Clk
Input/Output
INIT#
D6
Async GTL+
Input
DP1#
AE19
Common Clk
Input/Output
LINT0/INTR
B24
Async GTL+
Input
DP2#
AC15
Common Clk
Input/Output
LINT1/NMI
G23
Async GTL+
Input
DP3#
AE17
Common Clk
Input/Output
LOCK#
A17
Common Clk
Input/Output
DRDY#
E18
Common Clk
Input/Output
MCERR#
D7
Common Clk
Input/Output
DSTBN0#
Y21
Source Sync
Input/Output
ODTEN
B5
Power/Other
Input
DSTBN1#
Y18
Source Sync
Input/Output
OOD#
D29
Common Clk
Input
DSTBN2#
Y15
Source Sync
Input/Output
PROCHOT#
B25
Async GTL+
Output
DSTBN3#
Y12
Source Sync
Input/Output
PWRGOOD
AB7
Async GTL+
Input
DSTBP0#
Y20
Source Sync
Input/Output
REQ0#
B19
Source Sync
Input/Output
DSTBP1#
Y17
Source Sync
Input/Output
REQ1#
B21
Source Sync
Input/Output
DSTBP2#
Y14
Source Sync
Input/Output
REQ2#
C21
Source Sync
Input/Output
DSTBP3#
Y11
Source Sync
Input/Output
REQ3#
C20
Source Sync
Input/Output
Don’t Care
B4
REQ4#
B22
Source Sync
Input/Output
Don’t Care
A4
Reserved
A31
Don’t Care
C1
Reserved
E16
Don’t Care
C5
Reserved
W3
Don’t Care
AC1
Reserved
Y27
Don’t Care
AC30
Reserved
Y28
Don’t Care
AE2
Reserved
AE30
Don’t Care
AE3
RESET#
Y8
Common Clk
Input
FERR#/PBE#
E27
Async GTL+
Output
RS0#
E21
Common Clk
Input
FORCEPR#
A15
Power/Other
Input
RS1#
D22
Common Clk
Input
GTLREF0
W23
Power/Other
Input
RS2#
F21
Common Clk
Input
GTLREF1
W9
Power/Other
Input
RSP#
C6
Common Clk
Input
GTLREF2
F23
Power/Other
Input
SKTOCC#
A3
Power/Other
Output
GTLREF3
F9
Power/Other
Input
SM_ALERT#
AD28
SMBus
Output
HIT#
E22
Common Clk
Input/Output
SM_CLK
AC28
SMBus
Input
HITM#
A23
Common Clk
Input/Output
SM_DAT
AC29
SMBus
Input/Output
ID0#
A26
Common Clk
Input
SM_EP_A0
AA29
SMBus
Input
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
51
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 7 of 16)
52
Table 4-1. Pin Listing by Pin Name
(Sheet 8 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Direction
Pin Name
Pin No.
Signal Buffer
Type
SM_EP_A1
AB29
SMBus
Input
VCACHE
N3
Power/Other
SM_EP_A2
AB28
SMBus
Input
VCACHE
N5
Power/Other
SM_TS1_A0
AA28
SMBus
Input
VCACHE
N7
Power/Other
Input
VCACHE
N9
Power/Other
VCACHE
R1
Power/Other
SM_TS1_A1
Y29
SMBus
SM_VCC
AE28
Power/Other
SM_VCC
AE29
Power/Other
SM_WP
AD29
SMBus
SMI#
C27
STPCLK#
D4
TCK
E24
TDI
C24
VCACHE
R3
Power/Other
Input
VCACHE
R5
Power/Other
Async GTL+
Input
VCACHE
R7
Power/Other
Async GTL+
Input
VCACHE
R9
Power/Other
TAP
Input
VCACHE
U1
Power/Other
TAP
Input
VCACHE
U3
Power/Other
TDO
E25
TAP
Output
VCACHE
U5
Power/Other
TEST_BUS
A16
Power/Other
Input
VCACHE
U7
Power/Other
TESTHI0
W6
Power/Other
Input
VCACHE
U9
Power/Other
TESTHI1
W7
Power/Other
Input
VCC
A8
Power/Other
TESTHI2
W8
Power/Other
Input
VCC
A14
Power/Other
TESTHI3
Y6
Power/Other
Input
VCC
A18
Power/Other
TESTHI4
AA7
Power/Other
Input
VCC
A24
Power/Other
TESTHI5
AD5
Power/Other
Input
VCC
B20
Power/Other
TESTHI6
AE5
Power/Other
Input
VCC
C4
Power/Other
THERMTRIP#
F26
Async GTL+
Output
VCC
C22
Power/Other
TMS
A25
TAP
Input
VCC
C30
Power/Other
TRDY#
E19
Common Clk
Input
VCC
D8
Power/Other
Input
TRST#
F24
TAP
VCC
D14
Power/Other
VCACHE
H1
Power/Other
VCC
D18
Power/Other
VCACHE
H3
Power/Other
VCC
D24
Power/Other
VCACHE
H5
Power/Other
VCC
D31
Power/Other
VCACHE
H7
Power/Other
VCC
E6
Power/Other
VCACHE
H9
Power/Other
VCC
E20
Power/Other
VCACHE
K1
Power/Other
VCC
E26
Power/Other
VCACHE
K3
Power/Other
VCC
E28
Power/Other
VCACHE
K5
Power/Other
VCC
E30
Power/Other
VCACHE
K7
Power/Other
VCC
F1
Power/Other
VCACHE
K9
Power/Other
VCC
F4
Power/Other
VCACHE
M1
Power/Other
VCC
F29
Power/Other
VCACHE
M3
Power/Other
VCC
F31
Power/Other
VCACHE
M5
Power/Other
VCC
G2
Power/Other
VCACHE
M7
Power/Other
VCC
G4
Power/Other
VCACHE
M9
Power/Other
VCC
G6
Power/Other
VCACHE
N1
Power/Other
VCC
G8
Power/Other
Direction
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 9 of 16)
Pin Name
Pin No.
Signal Buffer
Type
VCC
G24
VCC
VCC
Table 4-1. Pin Listing by Pin Name
(Sheet 10 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Power/Other
VCC
P2
Power/Other
G26
Power/Other
VCC
P4
Power/Other
G28
Power/Other
VCC
P6
Power/Other
VCC
G30
Power/Other
VCC
P8
Power/Other
VCC
H23
Power/Other
VCC
P24
Power/Other
VCC
H25
Power/Other
VCC
P26
Power/Other
VCC
H27
Power/Other
VCC
P28
Power/Other
VCC
H29
Power/Other
VCC
P30
Power/Other
VCC
H31
Power/Other
VCC
R23
Power/Other
Direction
VCC
J2
Power/Other
VCC
R25
Power/Other
VCC
J4
Power/Other
VCC
R27
Power/Other
VCC
J6
Power/Other
VCC
R29
Power/Other
VCC
J8
Power/Other
VCC
R31
Power/Other
VCC
J24
Power/Other
VCC
T2
Power/Other
VCC
J26
Power/Other
VCC
T4
Power/Other
VCC
J28
Power/Other
VCC
T6
Power/Other
VCC
J30
Power/Other
VCC
T8
Power/Other
VCC
K23
Power/Other
VCC
T24
Power/Other
VCC
K25
Power/Other
VCC
T26
Power/Other
VCC
K27
Power/Other
VCC
T28
Power/Other
VCC
K29
Power/Other
VCC
T30
Power/Other
VCC
K31
Power/Other
VCC
U23
Power/Other
VCC
L2
Power/Other
VCC
U25
Power/Other
VCC
L4
Power/Other
VCC
U27
Power/Other
VCC
L6
Power/Other
VCC
U29
Power/Other
VCC
L8
Power/Other
VCC
U31
Power/Other
VCC
L24
Power/Other
VCC
V2
Power/Other
VCC
L26
Power/Other
VCC
V4
Power/Other
VCC
L28
Power/Other
VCC
V6
Power/Other
VCC
L30
Power/Other
VCC
V8
Power/Other
VCC
M23
Power/Other
VCC
V24
Power/Other
VCC
M25
Power/Other
VCC
V26
Power/Other
VCC
M27
Power/Other
VCC
V28
Power/Other
VCC
M29
Power/Other
VCC
V30
Power/Other
VCC
M31
Power/Other
VCC
W1
Power/Other
VCC
N23
Power/Other
VCC
W25
Power/Other
VCC
N25
Power/Other
VCC
W27
Power/Other
VCC
N27
Power/Other
VCC
W29
Power/Other
VCC
N29
Power/Other
VCC
W31
Power/Other
VCC
N31
Power/Other
VCC
Y2
Power/Other
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Direction
53
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 11 of 16)
Pin Name
Pin No.
Signal Buffer
Type
VCC
Y16
Power/Other
VCC
Y22
VCC
Y30
Table 4-1. Pin Listing by Pin Name
(Sheet 12 of 16)
Pin Name
Pin No.
Signal Buffer
Type
VSS
A29
Power/Other
Power/Other
VSS
B2
Power/Other
Power/Other
VSS
B9
Power/Other
Direction
VCC
AA1
Power/Other
VSS
B15
Power/Other
VCC
AA6
Power/Other
VSS
B17
Power/Other
VCC
AA20
Power/Other
VSS
B23
Power/Other
VCC
AA26
Power/Other
VSS
B28
Power/Other
VCC
AA31
Power/Other
VSS
C7
Power/Other
VCC
AB2
Power/Other
VSS
C13
Power/Other
VCC
AB8
Power/Other
VSS
C19
Power/Other
VCC
AB14
Power/Other
VSS
C25
Power/Other
VCC
AB18
Power/Other
VSS
C29
Power/Other
VCC
AB24
Power/Other
VSS
D2
Power/Other
VCC
AB30
Power/Other
VSS
D5
Power/Other
VCC
AC3
Power/Other
VSS
D11
Power/Other
VCC
AC16
Power/Other
VSS
D21
Power/Other
VCC
AC22
Power/Other
VSS
D28
Power/Other
VCC
AC31
Power/Other
VSS
D30
Power/Other
VCC
AD2
Power/Other
VSS
E9
Power/Other
VCC
AD20
Power/Other
VSS
E15
Power/Other
VCC
AD26
Power/Other
VSS
E17
Power/Other
VCC
AE14
Power/Other
VSS
E23
Power/Other
VCC
AE18
Power/Other
VSS
E29
Power/Other
VCC
AE24
Power/Other
VSS
E31
Power/Other
VCCA
AB4
Power/Other
Input
VSS
F2
Power/Other
VCC_CACHE_SENSE
B31
Power/Other
Output
VSS
F7
Power/Other
VCCIOPLL
AD4
Power/Other
Input
VSS
F13
Power/Other
VCCPLL
AD1
Power/Other
Input
VSS
F19
Power/Other
VCCSENSE
B27
Power/Other
Output
VSS
F25
Power/Other
54
VID0
F3
Power/Other
Output
VSS
F28
Power/Other
VID1
E3
Power/Other
Output
VSS
F30
Power/Other
VID2
D3
Power/Other
Output
VSS
G1
Power/Other
VID3
C3
Power/Other
Output
VSS
G3
Power/Other
VID4
B3
Power/Other
Output
VSS
G5
Power/Other
VID5
A1
Power/Other
Output
VSS
G9
Power/Other
Input
VIDPWRGD
B1
Power/Other
VSS
G25
Power/Other
VSS
A5
Power/Other
VSS
G27
Power/Other
VSS
A11
Power/Other
VSS
G29
Power/Other
VSS
A21
Power/Other
VSS
G31
Power/Other
VSS
A27
Power/Other
VSS
H2
Power/Other
Direction
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 13 of 16)
Pin Name
Pin No.
Signal Buffer
Type
VSS
H4
VSS
VSS
Table 4-1. Pin Listing by Pin Name
(Sheet 14 of 16)
Pin Name
Pin No.
Signal Buffer
Type
Power/Other
VSS
M26
Power/Other
H6
Power/Other
VSS
M28
Power/Other
H8
Power/Other
VSS
M30
Power/Other
VSS
H24
Power/Other
VSS
N2
Power/Other
VSS
H26
Power/Other
VSS
N4
Power/Other
VSS
H28
Power/Other
VSS
N6
Power/Other
VSS
H30
Power/Other
VSS
N8
Power/Other
VSS
J1
Power/Other
VSS
N24
Power/Other
VSS
J3
Power/Other
VSS
N26
Power/Other
VSS
J5
Power/Other
VSS
N28
Power/Other
VSS
J7
Power/Other
VSS
N30
Power/Other
Direction
VSS
J9
Power/Other
VSS
P1
Power/Other
VSS
J23
Power/Other
VSS
P3
Power/Other
VSS
J25
Power/Other
VSS
P5
Power/Other
VSS
J27
Power/Other
VSS
P7
Power/Other
VSS
J29
Power/Other
VSS
P9
Power/Other
VSS
J31
Power/Other
VSS
P23
Power/Other
VSS
K2
Power/Other
VSS
P25
Power/Other
VSS
K4
Power/Other
VSS
P27
Power/Other
VSS
K6
Power/Other
VSS
P29
Power/Other
VSS
K8
Power/Other
VSS
P31
Power/Other
VSS
K24
Power/Other
VSS
R2
Power/Other
VSS
K26
Power/Other
VSS
R4
Power/Other
VSS
K28
Power/Other
VSS
R6
Power/Other
VSS
K30
Power/Other
VSS
R8
Power/Other
VSS
L1
Power/Other
VSS
R24
Power/Other
VSS
L3
Power/Other
VSS
R26
Power/Other
VSS
L5
Power/Other
VSS
R28
Power/Other
VSS
L7
Power/Other
VSS
R30
Power/Other
VSS
L9
Power/Other
VSS
T1
Power/Other
VSS
L23
Power/Other
VSS
T3
Power/Other
VSS
L25
Power/Other
VSS
T5
Power/Other
VSS
L27
Power/Other
VSS
T7
Power/Other
VSS
L29
Power/Other
VSS
T9
Power/Other
VSS
L31
Power/Other
VSS
T23
Power/Other
VSS
M2
Power/Other
VSS
T25
Power/Other
VSS
M4
Power/Other
VSS
T27
Power/Other
VSS
M6
Power/Other
VSS
T29
Power/Other
VSS
M8
Power/Other
VSS
T31
Power/Other
VSS
M24
Power/Other
VSS
U2
Power/Other
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Direction
55
Pin Listing
Table 4-1. Pin Listing by Pin Name
(Sheet 15 of 16)
56
Pin Name
Pin No.
Signal Buffer
Type
VSS
U4
Power/Other
VSS
U6
VSS
U8
VSS
VSS
Table 4-1. Pin Listing by Pin Name
(Sheet 16 of 16)
Pin Name
Pin No.
Signal Buffer
Type
VSS
AA23
Power/Other
Power/Other
VSS
AA30
Power/Other
Power/Other
VSS
AB1
Power/Other
U24
Power/Other
VSS
AB5
Power/Other
U26
Power/Other
VSS
AB11
Power/Other
VSS
U28
Power/Other
VSS
AB21
Power/Other
VSS
U30
Power/Other
VSS
AB27
Power/Other
Direction
VSS
V1
Power/Other
VSS
AB31
Power/Other
VSS
V3
Power/Other
VSS
AC2
Power/Other
VSS
V5
Power/Other
VSS
AC7
Power/Other
VSS
V7
Power/Other
VSS
AC13
Power/Other
VSS
V9
Power/Other
VSS
AC19
Power/Other
VSS
V23
Power/Other
VSS
AC25
Power/Other
VSS
V25
Power/Other
VSS
AD3
Power/Other
VSS
V27
Power/Other
VSS
AD9
Power/Other
VSS
V29
Power/Other
VSS
AD15
Power/Other
VSS
V31
Power/Other
VSS
AD17
Power/Other
Direction
VSS
W2
Power/Other
VSS
AD23
Power/Other
VSS
W4
Power/Other
VSS
AE6
Power/Other
VSS
W24
Power/Other
VSS
AE11
Power/Other
VSS
W26
Power/Other
VSS
AE21
Power/Other
VSS
W28
Power/Other
VSS
AE27
Power/Other
VSS
W30
Power/Other
VSSA
AA5
Power/Other
Input
VSS
Y1
Power/Other
VSS_CACHE_SENSE
C31
Power/Other
Output
VSS
Y3
Power/Other
VSSSENSE
D26
Power/Other
Output
VSS
Y5
Power/Other
VTT
B12
Power/Other
VSS
Y7
Power/Other
VTT
C10
Power/Other
VSS
Y13
Power/Other
VTT
E12
Power/Other
VSS
Y19
Power/Other
VTT
F10
Power/Other
VSS
Y25
Power/Other
VTT
Y10
Power/Other
VSS
Y31
Power/Other
VTT
AA12
Power/Other
VSS
AA2
Power/Other
VTT
AC10
Power/Other
VSS
AA9
Power/Other
VTT
AD12
Power/Other
VSS
AA15
Power/Other
VTT
AE4
Power/Other
VSS
AA17
Power/Other
VTTEN
E1
Power/Other
Output
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
4.1.2
Pin Listing by Pin Number
Table 4-2.Pin Listing by Pin Number
(Sheet 2 of 16)
Table 4-2.Pin Listing by Pin Number
(Sheet 1 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Direction
A1
VID5
Power/Other
Output
Pin Name
Signal
Buffer Type
B9
VSS
Power/Other
A21#
Source Sync
Input/Output
Input/Output
Pin No.
Direction
A2
CVID3
Power/Other
Output
B10
A3
SKTOCC#
Power/Other
Output
B11
A22#
Source Sync
B12
VTT
Power/Other
Power/Other
B13
A13#
Source Sync
Input/Output
A12#
Source Sync
Input/Output
A4
Don’t Care
A5
VSS
A6
A32#
Source Sync
Input/Output
B14
A7
A33#
Source Sync
Input/Output
B15
VSS
Power/Other
B16
A11#
Source Sync
A8
VCC
Power/Other
A9
A26#
Source Sync
Input/Output
Input/Output
B17
VSS
Power/Other
Input/Output
B18
A5#
Source Sync
Input/Output
Input/Output
A10
A20#
Source Sync
A11
VSS
Power/Other
B19
REQ0#
Common Clk
VCC
Power/Other
A12
A14#
Source Sync
Input/Output
B20
A13
A10#
Source Sync
Input/Output
B21
REQ1#
Common Clk
Input/Output
B22
REQ4#
Common Clk
Input/Output
A14
VCC
Power/Other
A15
FORCEPR#
Power/Other
Input
B23
VSS
Power/Other
LINT0/INTR
Async GTL+
Input
A16
TEST_BUS
Power/Other
Input
B24
A17
LOCK#
Common Clk
Input/Output
B25
PROCHOT#
Power/Other
Output
B26
ID1#
Common Clk
Input
Input/Output
B27
VCCSENSE
Power/Other
Output
Input/Output
B28
VSS
Power/Other
A18
VCC
Power/Other
A19
A7#
Source Sync
A20
A4#
Source Sync
A21
VSS
Power/Other
B29
ID5#
Common Clk
Input
ID6#
Common Clk
Input
Power/Other
A22
A3#
Source Sync
Input/Output
B30
A23
HITM#
Common Clk
Input/Output
B31
VCC_CACHE_SENSE
C1
Don’t Care
Input
C2
CVID2
Power/Other
Output
Input
C3
VID3
Power/Other
Output
Power/Other
A24
VCC
Power/Other
A25
TMS
TAP
A26
ID0#
Common Clk
A27
VSS
Power/Other
C4
VCC
C5
Don’t Care
A28
IDS#
Common Clk
A29
VSS
Power/Other
Input
C6
RSP#
Common Clk
Common Clk
C7
VSS
Power/Other
Input
Input
A30
ID7#
A31
Reserved
C8
A35#
Source Sync
Input/Output
B1
VIDPWRGD
Power/Other
C9
A34#
Source Sync
Input/Output
B2
VSS
Power/Other
C10
VTT
Power/Other
C11
A30#
Source Sync
Input/Output
Input/Output
Input
B3
VID4
Power/Other
Output
B4
Don’t Care
Power/Other
C12
A23#
Source Sync
VSS
Power/Other
B5
ODTEN
Power/Other
Input
C13
B6
A38#
Source Sync
Input/Output
C14
A16#
Source Sync
Input/Output
A15#
Source Sync
Input/Output
A39#
Source Sync
Input/Output
B7
A31#
Source Sync
Input/Output
C15
B8
A27#
Source Sync
Input/Output
C16
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
57
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 3 of 16)
Table 4-2.Pin Listing by Pin Number
(Sheet 4 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Direction
Pin No.
Pin Name
Signal
Buffer Type
Direction
C17
A8#
Source Sync
Input/Output
D26
VSSSENSE
Power/Other
Output
C18
A6#
Source Sync
Input/Output
D27
ID3#
Common Clk
Input
C19
VSS
Power/Other
D28
VSS
Power/Other
C20
REQ3#
Common Clk
Input/Output
D29
OOD#
Common Clk
C21
REQ2#
Common Clk
Input/Output
D30
VSS
Power/Other
58
Input
C22
VCC
Power/Other
D31
VCC
Power/Other
C23
DEFER#
Common Clk
Input
E1
VTTEN
Power/Other
C24
TDI
TAP
Input
E2
CVID0
Power/Other
Output
C25
VSS
Power/Other
Input
E3
VID1
Power/Other
Output
C26
IGNNE#
Async GTL+
Input
E4
BPM5#
Common Clk
Input/Output
C27
SMI#
Async GTL+
Input
E5
IERR#
Common Clk
Output
C28
ID4#
Common Clk
Input
E6
VCC
Power/Other
C29
VSS
Power/Other
E7
BPM2#
Common Clk
Input/Output
C30
VCC
Power/Other
E8
BPM4#
Common Clk
Input/Output
C31
VSS_CACHE_SENSE
Power/Other
E9
VSS
Power/Other
D1
CVID1
Power/Other
D2
VSS
Power/Other
D3
VID2
Power/Other
Output
D4
STPCLK#
Async GTL+
Input
D5
VSS
Power/Other
D6
INIT#
Async GTL+
Input
D7
MCERR#
Common Clk
Input/Output
D8
VCC
Power/Other
D9
AP1#
Common Clk
D10
BR3#
Common Clk
D11
VSS
Power/Other
E20
VCC
Power/Other
D12
A29#
Source Sync
Input/Output
E21
RS0#
Common Clk
Input
D13
A25#
Source Sync
Input/Output
E22
HIT#
Common Clk
Input/Output
D14
VCC
Power/Other
E23
VSS
Power/Other
D15
A18#
Source Sync
Input/Output
E24
TCK
TAP
Input
D16
A17#
Source Sync
Input/Output
E25
TDO
TAP
Output
D17
A9#
Source Sync
Input/Output
E26
VCC
Power/Other
D18
VCC
Power/Other
E27
FERR#/PBE#
Async GTL+
D19
ADS#
Common Clk
Input/Output
E28
VCC
Power/Other
D20
BR0#
Common Clk
Input/Output
E29
VSS
Power/Other
Output
Output
E10
AP0#
Common Clk
Input/Output
E11
BR2#
Common Clk
Input
E12
VTT
Power/Other
E13
A28#
Source Sync
Input/Output
E14
A24#
Source Sync
Input/Output
E15
VSS
Power/Other
E16
Reserved
E17
VSS
Input/Output
E18
DRDY#
Common Clk
Input/Output
Input
E19
TRDY#
Common Clk
Input
Power/Other
D21
VSS
Power/Other
E30
VCC
Power/Other
D22
RS1#
Common Clk
Input
E31
VSS
Power/Other
D23
BPRI#
Common Clk
Input
F1
VCC
Power/Other
D24
VCC
Power/Other
F2
VSS
Power/Other
D25
ID2#
Common Clk
F3
VID0
Power/Other
Input
Output
Output
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 5 of 16)
Table 4-2.Pin Listing by Pin Number
(Sheet 6 of 16)
Pin No.
Pin Name
Signal
Buffer Type
F4
VCC
Power/Other
F5
BPM3#
Common Clk
Input/Output
F6
BPM0#
Common Clk
Input/Output
Direction
Pin No.
Pin Name
Signal
Buffer Type
G26
VCC
Power/Other
G27
VSS
Power/Other
G28
VCC
Power/Other
F7
VSS
Power/Other
G29
VSS
Power/Other
F8
BPM1#
Common Clk
Input/Output
G30
VCC
Power/Other
Input
G31
VSS
Power/Other
H1
VCACHE
Power/Other
F9
GTLREF3
Power/Other
F10
VTT
Power/Other
F11
BINIT#
Common Clk
Input/Output
H2
VSS
Power/Other
F12
BR1#
Common Clk
Input
H3
VCACHE
Power/Other
F13
VSS
Power/Other
H4
VSS
Power/Other
F14
ADSTB1#
Source Sync
Input/Output
H5
VCACHE
Power/Other
F15
A19#
Source Sync
Input/Output
H6
VSS
Power/Other
F16
A36#
Source Sync
Input/Output
H7
VCACHE
Power/Other
F17
ADSTB0#
Source Sync
Input/Output
H8
VSS
Power/Other
F18
DBSY#
Common Clk
Input/Output
H9
VCACHE
Power/Other
F19
VSS
Power/Other
F20
BNR#
Common Clk
F21
RS2#
F22
A37#
F23
GTLREF2
F24
TRST#
F25
VSS
Power/Other
F26
THERMTRIP#
Async GTL+
Output
F27
A20M#
Async GTL+
Input
F28
VSS
Power/Other
F29
VCC
F30
VSS
F31
G1
H23
VCC
Power/Other
Input/Output
H24
VSS
Power/Other
Common Clk
Input
H25
VCC
Power/Other
Source Sync
Input/Output
H26
VSS
Power/Other
Power/Other
Input
H27
VCC
Power/Other
TAP
Input
H28
VSS
Power/Other
H29
VCC
Power/Other
H30
VSS
Power/Other
H31
VCC
Power/Other
J1
VSS
Power/Other
Power/Other
J2
VCC
Power/Other
Power/Other
J3
VSS
Power/Other
VCC
Power/Other
J4
VCC
Power/Other
VSS
Power/Other
J5
VSS
Power/Other
G2
VCC
Power/Other
J6
VCC
Power/Other
G3
VSS
Power/Other
J7
VSS
Power/Other
G4
VCC
Power/Other
J8
VCC
Power/Other
G5
VSS
Power/Other
J9
VSS
Power/Other
G6
VCC
Power/Other
J23
VSS
Power/Other
G7
BOOT_SELECT
Power/Other
J24
VCC
Power/Other
G8
VCC
Power/Other
J25
VSS
Power/Other
G9
VSS
Power/Other
J26
VCC
Power/Other
G23
LINT1/NMI
Async GTL+
J27
VSS
Power/Other
G24
VCC
Power/Other
J28
VCC
Power/Other
G25
VSS
Power/Other
J29
VSS
Power/Other
Input
Input
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Direction
59
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 7 of 16)
Pin No.
Pin Name
Signal
Buffer Type
J30
VCC
J31
K1
K2
K3
K4
K5
K6
K7
K8
K9
K23
K24
60
Table 4-2.Pin Listing by Pin Number
(Sheet 8 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Power/Other
M3
VCACHE
Power/Other
VSS
Power/Other
M4
VSS
Power/Other
VCACHE
Power/Other
M5
VCACHE
Power/Other
VSS
Power/Other
M6
VSS
Power/Other
VCACHE
Power/Other
M7
VCACHE
Power/Other
VSS
Power/Other
M8
VSS
Power/Other
VCACHE
Power/Other
M9
VCACHE
Power/Other
VSS
Power/Other
M23
VCC
Power/Other
VCACHE
Power/Other
M24
VSS
Power/Other
VSS
Power/Other
M25
VCC
Power/Other
VCACHE
Power/Other
M26
VSS
Power/Other
VCC
Power/Other
M27
VCC
Power/Other
VSS
Power/Other
M28
VSS
Power/Other
K25
VCC
Power/Other
M29
VCC
Power/Other
K26
VSS
Power/Other
M30
VSS
Power/Other
K27
VCC
Power/Other
M31
VCC
Power/Other
K28
VSS
Power/Other
N1
VCACHE
Power/Other
K29
VCC
Power/Other
N2
VSS
Power/Other
K30
VSS
Power/Other
N3
VCACHE
Power/Other
K31
VCC
Power/Other
N4
VSS
Power/Other
L1
VSS
Power/Other
N5
VCACHE
Power/Other
L2
VCC
Power/Other
N6
VSS
Power/Other
L3
VSS
Power/Other
N7
VCACHE
Power/Other
L4
VCC
Power/Other
N8
VSS
Power/Other
L5
VSS
Power/Other
N9
VCACHE
Power/Other
L6
VCC
Power/Other
N23
VCC
Power/Other
L7
VSS
Power/Other
N24
VSS
Power/Other
L8
VCC
Power/Other
N25
VCC
Power/Other
L9
VSS
Power/Other
N26
VSS
Power/Other
L23
VSS
Power/Other
N27
VCC
Power/Other
L24
VCC
Power/Other
N28
VSS
Power/Other
L25
VSS
Power/Other
N29
VCC
Power/Other
L26
VCC
Power/Other
N30
VSS
Power/Other
L27
VSS
Power/Other
N31
VCC
Power/Other
L28
VCC
Power/Other
P1
VSS
Power/Other
L29
VSS
Power/Other
P2
VCC
Power/Other
L30
VCC
Power/Other
P3
VSS
Power/Other
L31
VSS
Power/Other
P4
VCC
Power/Other
M1
VCACHE
Power/Other
P5
VSS
Power/Other
M2
VSS
Power/Other
P6
VCC
Power/Other
Direction
Direction
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 9 of 16)
Pin No.
Pin Name
Signal
Buffer Type
P7
VSS
P8
P9
Table 4-2.Pin Listing by Pin Number
(Sheet 10 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Power/Other
T24
VCC
Power/Other
VCC
Power/Other
T25
VSS
Power/Other
VSS
Power/Other
T26
VCC
Power/Other
P23
VSS
Power/Other
T27
VSS
Power/Other
P24
VCC
Power/Other
T28
VCC
Power/Other
P25
VSS
Power/Other
T29
VSS
Power/Other
P26
VCC
Power/Other
T30
VCC
Power/Other
P27
VSS
Power/Other
T31
VSS
Power/Other
P28
VCC
Power/Other
U1
VCACHE
Power/Other
P29
VSS
Power/Other
U2
VSS
Power/Other
P30
VCC
Power/Other
U3
VCACHE
Power/Other
P31
VSS
Power/Other
U4
VSS
Power/Other
R1
VCACHE
Power/Other
U5
VCACHE
Power/Other
R2
VSS
Power/Other
U6
VSS
Power/Other
R3
VCACHE
Power/Other
U7
VCACHE
Power/Other
R4
VSS
Power/Other
U8
VSS
Power/Other
R5
VCACHE
Power/Other
U9
VCACHE
Power/Other
R6
VSS
Power/Other
U23
VCC
Power/Other
R7
VCACHE
Power/Other
U24
VSS
Power/Other
R8
VSS
Power/Other
U25
VCC
Power/Other
R9
VCACHE
Power/Other
U26
VSS
Power/Other
R23
VCC
Power/Other
U27
VCC
Power/Other
R24
VSS
Power/Other
U28
VSS
Power/Other
R25
VCC
Power/Other
U29
VCC
Power/Other
R26
VSS
Power/Other
U30
VSS
Power/Other
R27
VCC
Power/Other
U31
VCC
Power/Other
R28
VSS
Power/Other
V1
VSS
Power/Other
R29
VCC
Power/Other
V2
VCC
Power/Other
R30
VSS
Power/Other
V3
VSS
Power/Other
R31
VCC
Power/Other
V4
VCC
Power/Other
T1
VSS
Power/Other
V5
VSS
Power/Other
T2
VCC
Power/Other
V6
VCC
Power/Other
T3
VSS
Power/Other
V7
VSS
Power/Other
T4
VCC
Power/Other
V8
VCC
Power/Other
T5
VSS
Power/Other
V9
VSS
Power/Other
T6
VCC
Power/Other
V23
VSS
Power/Other
T7
VSS
Power/Other
V24
VCC
Power/Other
T8
VCC
Power/Other
V25
VSS
Power/Other
T9
VSS
Power/Other
V26
VCC
Power/Other
T23
VSS
Power/Other
V27
VSS
Power/Other
Direction
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Direction
61
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 11 of 16)
Pin No.
Pin Name
Signal
Buffer Type
V28
VCC
V29
V30
V31
W1
W2
VSS
W3
Reserved
62
Table 4-2.Pin Listing by Pin Number
(Sheet 12 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Power/Other
Y19
VSS
Power/Other
VSS
Power/Other
Y20
DSTBP0#
Source Sync
Input/Output
VCC
Power/Other
Y21
DSTBN0#
Source Sync
Input/Output
VSS
Power/Other
Y22
VCC
Power/Other
VCC
Power/Other
Y23
D5#
Source Sync
Input/Output
Power/Other
Y24
D2#
Source Sync
Input/Output
Y25
VSS
Power/Other
Source Sync
Input/Output
Input
Direction
W4
VSS
Power/Other
Y26
D0#
W5
BCLK1
FSB Clk
Input
Y27
Reserved
W6
TESTHI0
Power/Other
Input
Y28
Reserved
W7
TESTHI1
Power/Other
Input
Y29
SM_TS1_A1
SMBus
Direction
W8
TESTHI2
Power/Other
Input
Y30
VCC
Power/Other
W9
GTLREF1
Power/Other
Input
Y31
VSS
Power/Other
W23
GTLREF0
Power/Other
Input
AA1
VCC
Power/Other
W24
VSS
Power/Other
AA2
VSS
Power/Other
W25
VCC
Power/Other
AA3
BSEL0
Power/Other
Output
W26
VSS
Power/Other
AA4
DEP7#
Source Sync
Input/Output
W27
VCC
Power/Other
AA5
VSSA
Power/Other
Input
W28
VSS
Power/Other
AA6
VCC
Power/Other
W29
VCC
Power/Other
AA7
TESTHI4
Power/Other
Input
W30
VSS
Power/Other
AA8
D61#
Source Sync
Input/Output
W31
VCC
Power/Other
AA9
VSS
Power/Other
Y1
VSS
Power/Other
AA10
D54#
Source Sync
Input/Output
Y2
VCC
Power/Other
AA11
D53#
Source Sync
Input/Output
Y3
VSS
Power/Other
AA12
VTT
Power/Other
Y4
BCLK0
FSB Clk
AA13
D48#
Source Sync
Input/Output
Y5
VSS
Power/Other
AA14
D49#
Source Sync
Input/Output
Y6
TESTHI3
Power/Other
AA15
VSS
Power/Other
Y7
VSS
Power/Other
AA16
D33#
Source Sync
Y8
RESET#
Common Clk
Input
AA17
VSS
Power/Other
Y9
D62#
Source Sync
Input/Output
AA18
D24#
Source Sync
Input/Output
Y10
VTT
Power/Other
AA19
D15#
Source Sync
Input/Output
Y11
DSTBP3#
Source Sync
Input/Output
AA20
VCC
Power/Other
Y12
DSTBN3#
Source Sync
Input/Output
AA21
D11#
Source Sync
Input/Output
Y13
VSS
Power/Other
AA22
D10#
Source Sync
Input/Output
Input
Input
Input/Output
Y14
DSTBP2#
Source Sync
Input/Output
AA23
VSS
Power/Other
Y15
DSTBN2#
Source Sync
Input/Output
AA24
D6#
Source Sync
Input/Output
Y16
VCC
Power/Other
AA25
D3#
Source Sync
Input/Output
Y17
DSTBP1#
Source Sync
Input/Output
AA26
VCC
Power/Other
Y18
DSTBN1#
Source Sync
Input/Output
AA27
D1#
Source Sync
Input/Output
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 13 of 16)
Table 4-2.Pin Listing by Pin Number
(Sheet 14 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Direction
Pin No.
Pin Name
Signal
Buffer Type
Direction
AA28
SM_TS1_A0
SMBus
Input
AC6
D59#
Source Sync
Input/Output
AA29
SM_EP_A0
SMBus
Input
AA30
VSS
Power/Other
AA31
VCC
AB1
VSS
AC7
VSS
Power/Other
AC8
D56#
Source Sync
Input/Output
Power/Other
AC9
D47#
Source Sync
Input/Output
Power/Other
AC10
VTT
Power/Other
AB2
VCC
Power/Other
AC11
D43#
Source Sync
Input/Output
AB3
BSEL1
Power/Other
Output
AC12
D41#
Source Sync
Input/Output
AB4
VCCA
Power/Other
Input
AC13
VSS
Power/Other
AB5
VSS
Power/Other
AC14
D50#
Source Sync
Input/Output
AB6
D63#
Source Sync
Input/Output
AC15
DP2#
Common Clk
Input/Output
AB7
PWRGOOD
Async GTL+
Input
AC16
VCC
Power/Other
AB8
VCC
Power/Other
AC17
D34#
Source Sync
Input/Output
AB9
DBI3#
Source Sync
Input/Output
AC18
DP0#
Common Clk
Input/Output
AB10
D55#
Source Sync
Input/Output
AC19
VSS
Power/Other
AB11
VSS
Power/Other
AC20
D25#
Source Sync
Input/Output
AB12
D51#
Source Sync
Input/Output
AC21
D26#
Source Sync
Input/Output
AB13
D52#
Source Sync
Input/Output
AC22
VCC
Power/Other
AB14
VCC
Power/Other
AC23
D23#
Source Sync
Input/Output
AB15
D37#
Source Sync
Input/Output
AC24
D20#
Source Sync
Input/Output
AB16
D32#
Source Sync
Input/Output
AC25
VSS
Power/Other
AB17
D31#
Source Sync
Input/Output
AC26
D17#
Source Sync
Input/Output
AB18
VCC
Power/Other
AC27
DBI0#
Source Sync
Input/Output
AB19
D14#
Source Sync
Input/Output
AC28
SM_CLK
SMBus
Input
AB20
D12#
Source Sync
Input/Output
AC29
SM_DAT
SMBus
Output
AB21
VSS
Power/Other
AC30
Don’t Care
AB22
D13#
Source Sync
Input/Output
AC31
VCC
Power/Other
AB23
D9#
Source Sync
Input/Output
AD1
VCCPLL
Power/Other
AB24
VCC
Power/Other
AD2
VCC
Power/Other
AB25
D8#
Source Sync
Input/Output
AD3
VSS
Power/Other
AB26
D7#
Source Sync
Input/Output
AD4
VCCIOPLL
Power/Other
Input
AB27
VSS
Power/Other
AD5
TESTHI5
Power/Other
Input
AB28
SM_EP_A2
SMBus
Input
AD6
DEP5#
Source Sync
Input/Output
AB29
SM_EP_A1
SMBus
Input
AD7
D57#
Source Sync
Input/Output
AB30
VCC
Power/Other
AD8
D46#
Source Sync
Input/Output
AB31
VSS
Power/Other
AD9
VSS
Power/Other
AC1
Don’t Care
AD10
D45#
Source Sync
Input/Output
AC2
VSS
Power/Other
AD11
D40#
Source Sync
Input/Output
AC3
VCC
Power/Other
AD12
VTT
Power/Other
AC4
DEP6#
Source Sync
Input/Output
AD13
D38#
Source Sync
Input/Output
AC5
D60#
Source Sync
Input/Output
AD14
D39#
Source Sync
Input/Output
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Input
63
Pin Listing
Table 4-2.Pin Listing by Pin Number
(Sheet 15 of 16)
Table 4-2.Pin Listing by Pin Number
(Sheet 16 of 16)
Pin No.
Pin Name
Signal
Buffer Type
Pin No.
Pin Name
Signal
Buffer Type
Direction
AD15
VSS
Power/Other
AE8
DEP4#
Source Sync
Input/Output
AD16
COMP0
Power/Other
AD17
VSS
Power/Other
AE9
D44#
Source Sync
Input/Output
AE10
D42#
Source Sync
Input/Output
AD18
D36#
Source Sync
Input/Output
AD19
D30#
Source Sync
Input/Output
AE11
VSS
Power/Other
AE12
DBI2#
Source Sync
Input/Output
AD20
VCC
Power/Other
AD21
D29#
Source Sync
Input/Output
AE13
D35#
Source Sync
Input/Output
AE14
VCC
Power/Other
AD22
DBI1#
Source Sync
Input/Output
AD23
VSS
Power/Other
AE15
DEP3#
Source Sync
Input/Output
AE16
DEP2#
Source Sync
Input/Output
AD24
D21#
Source Sync
AD25
D18#
Source Sync
Input/Output
AE17
DP3#
Common Clk
Input/Output
Input/Output
AE18
VCC
Power/Other
AD26
VCC
Power/Other
AD27
D4#
Source Sync
Input/Output
AE19
DP1#
Common Clk
Input/Output
AE20
D28#
Source Sync
Input/Output
AD28
SM_ALERT#
SMBus
Output
AD29
SM_WP
SMBus
Input
AE21
VSS
Power/Other
AE22
D27#
Source Sync
Input/Output
AD30
DEP1#
Source Sync
AD31
DEP0#
Source Sync
Input/Output
AE23
D22#
Source Sync
Input/Output
Input/Output
AE24
VCC
Power/Other
AE2
AE3
Don’t Care
AE25
D19#
Source Sync
Input/Output
Don’t Care
AE26
D16#
Source Sync
Input/Output
AE4
VTT
AE5
TESTHI6
Power/Other
AE6
VSS
Power/Other
AE7
D58#
Source Sync
Direction
Input
Input
Input/Output
AE27
VSS
Power/Other
AE28
SM_VCC
Power/Other
AE29
SM_VCC
Power/Other
AE30
Reserved
§
64
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Signal Definitions
5
Signal Definitions
5.1
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 1 of 8)
Name
A[39:3]#
Type
Description
40
I/O
A[39:3]# (Address) define a 2 -byte physical memory address space. In subphase 1 of the address phase, these pins transmit the address of a transaction.
In sub-phase 2, these pins transmit transaction type information. These signals
must connect the appropriate pins of all agents on the Dual-Core Intel Xeon
processor 7100 series front side bus. A[39:3]# are protected by parity signals
AP[1:0]#. A[39:3]# are source synchronous signals and are latched into the
receiving buffers by ADSTB[1:0]#.
On the active-to-inactive transition of RESET#, the processors sample a subset
of the A[39:3]# pins to determine their power-on configuration. See
Section 7.1.
I
If A20M# (Address-20 Mask) is asserted, the processor masks physical address
bit 20 (A20#) before looking up a line in any internal cache and before driving
a read/write transaction on the bus. Asserting A20M# emulates the 8086
processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M#
is only supported in real mode.
A20M# is an asynchronous signal. However, to ensure recognition of this signal
following an I/O write instruction, it must be valid 6 clks before the I/O write’s
response.
ADS#
I/O
ADS# (Address Strobe) is asserted to indicate the validity of the transaction
address on the A[39:3]# and transaction request type on REQ[4:0]# pins. All
bus agents observe the ADS# activation to begin parity checking, protocol
checking, address decode, internal snoop, or deferred reply ID match
operations associated with the new transaction. This signal must connect the
appropriate pins on all Dual-Core Intel Xeon processor 7100 series processor
front side bus agents.
ADSTB[1:0]#
I/O
Address strobes are used to latch A[39:3]# and REQ[4:0]# on their rising and
falling edge.
AP[1:0]#
I/O
AP[1:0]# (Address Parity) are driven by the requestor one common clock after
ADS#, A[39:3]#, REQ[4:0]# are driven. A correct parity signal is electrically
high if an even number of covered signals are electrically low and electrically
low if an odd number of covered signals are electrically low. This allows parity
to be electrically high when all the covered signals are electrically high.
AP[1:0]# should connect the appropriate pins of all Dual-Core Intel Xeon
processor 7100 series front side bus agents. The following table defines the
coverage for these signals.
A20M#
BCLK[1:0]
I
Request Signals
Subphase 1
Subphase 2
A[39:24]#
AP0#
AP1#
A[23:3]#
AP1#
AP0#
REQ[4:0]#
AP1#
AP0#
The differential bus clock pair BCLK[1:0] determines the bus frequency. All
processor front side bus agents must receive these signals to drive their
outputs and latch their inputs.
All external timing parameters are specified with respect to the rising edge of
BCLK0 crossing the falling edge of BCLK1.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
65
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 2 of 8)
Name
Type
Description
BINIT#
I/O
BINIT# (Bus Initialization) may be observed and driven by all processor front
side bus agents. If used, BINIT# must connect the appropriate pins of all such
agents. If the BINIT# driver is enabled, BINIT# is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration (see
Section 7.1) and BINIT# is sampled asserted, symmetric agents reset their bus
LOCK# activity and bus request arbitration state machines. The bus agents do
not reset their I/O Queue (IOQ) and transaction tracking state machines upon
observation of BINIT# assertion. Once the BINIT# assertion has been
observed, the bus agents will re-arbitrate for the front side bus and attempt
completion of their bus queue and IOQ entries.
If BINIT# observation is enabled during power on configuration, a central
agent may handle an assertion of BINIT# as appropriate to the error handling
architecture of the system.
BNR#
I/O
BNR# (Block Next Request) is used to assert a bus stall by any bus agent who
is unable to accept new bus transactions. During a bus stall, the current bus
owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time,
BNR# is a wire-OR signal which must connect the appropriate pins of all
processor system bus agents. In order to avoid wire-OR glitches associated
with simultaneous edge transitions driven by multiple drivers, BNR# is
activated on specific clock edges and sampled on specific clock edges.
I
The BOOT_SELECT input informs the processor whether the platform supports
the Dual-Core Intel Xeon processor 7100 series. Incompatible platform designs
will have this input connected to VSS. Thus, this pin is essentially an electrical
key to prevent the Dual-Core Intel Xeon processor 7100 series from running in
a system that is not designed for it. For platforms that are designed to support
the Dual-Core Intel Xeon processor 7100 series, this pin should be changed to
a no-connect.
I/O
BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor
signals. They are outputs from the processor which indicate the status of
breakpoints and programmable counters used for monitoring processor
performance. BPM[5:0]# should connect the appropriate pins of all Dual-Core
Intel Xeon processor 7100 series front side bus agents.
BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is
a processor output used by debug tools to determine processor debug
readiness.
BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#
is a processor input and is used by debug tools to request debug operation of
the processors.
BPM[5:4]# must be bussed to all bus agents. Please refer to the appropriate
platform design guide for more detailed information.
I
BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor
front side bus. It must connect the appropriate pins of all processor front side
bus agents. Observing BPRI# active (as asserted by the priority agent) causes
all other agents to stop issuing new requests, unless such requests are part of
an ongoing locked operation. The priority agent keeps BPRI# asserted until its
requests are issued, then releases the bus by deasserting BPRI#.
BOOT_
SELECT
BPM[5:0]#
BPRI#
66
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 3 of 8)
Name
BR0#
BR[3:1]#
Type
I/O
I
Description
BR[3:0]# (Bus Request) drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual
processor pins. The tables below give the rotating interconnect between the
processor and bus signals for 3-load configurations.
BR[3:0]# Signals Rotating Interconnect, 3-Load Configuration
Bus Signal
Agent 0
Pins
Agent 1
Pins
BREQ0#
BR0#
BR1#
BREQ1#
BR1#
BR0#
BREQ2#
BR2#
BR3#
BREQ3#
BR3#
BR2#
During power-on configuration, the central agent must assert the BR0# bus
signal. All symmetric agents sample their BR[3:0]# pins on the active-toinactive transition of RESET#. The pin which the agent samples asserted
determines its agent ID.
BSEL[1:0]
O
These output signals are used to select the front side bus frequency. The
frequency is determined by the processor(s), chipset, and frequency
synthesizer capabilities. All front side bus agents must operate at the same
frequency. Individual processors will only operate at their specified front side
bus frequency. See the appropriate platform design guide for implementation
examples.
See Table 2-3 for output values. Refer to the appropriate platform design guide
for termination recommendations.
COMP0
I
COMP0 must be terminated to VSS on the baseboard using precision resistors.
This input configures the AGTL+ drivers of the processor. Refer to the
appropriate platform design guide and Table 2-23 for implementation details.
CVID[3:0]
O
CVID[3:0] (Cache Voltage ID) pins are used to support automatic selection of
VCACHE. These are open drain signals that are driven by the processor and must
be pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely,
the VCACHE VR output must be disabled prior to the voltage supply for these
pins becoming invalid. The CVID pins are needed to support processor voltage
specification variations. See Table 2-5 for definitions of these pins. The VCACHE
VR must supply the voltage that is requested by these pins, or disable itself.
D[63:0]#
I/O
D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path
between the processor front side bus agents, and must connect the
appropriate pins on all such agents. The data driver asserts DRDY# to indicate
a valid data transfer.
D[63:0]# are quad-pumped signals, and will thus be driven four times in a
common clock period. D[63:0]# are latched off the falling edge of both
DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to
a pair of one DSTBP# and one DSTBN#. The following table shows the
grouping of data signals to strobes and DBI#.
Furthermore, the DBI# pins determine the polarity of the data signals. Each
group of 16 data signals corresponds to one DBI# signal. When the DBI#
signal is active, the corresponding data group is inverted and therefore
sampled active high.
DBI[3:0]#
I/O
DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]#
and DEP[7:0]# signals. The DBI[3:0]# signals are activated when the data on
the data bus is inverted. If more than half the data bits, within an 18-bit group
(including ECC bits), would have been asserted electrically low, the bus agent
may invert the data bus and corresponding ECC signals for that particular subphase for that 18-bit group.
DBSY#
I/O
DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data
on the processor front side bus to indicate that the data bus is in use. The data
bus is released after DBSY# is deasserted. This signal must connect the
appropriate pins on all processor front side bus agents.
DEFER#
I
DEFER# is asserted by an agent to indicate that a transaction cannot be
guaranteed in-order completion. Assertion of DEFER# is normally the
responsibility of the addressed memory or I/O agent. This signal must connect
the appropriate pins of all processor front side bus agents.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
67
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 4 of 8)
Name
Type
Description
DEP[7:0]#
I/O
The DEP[7:0]# (data bus ECC protection) signals provide optional ECC
protection for the data bus. They are driven by the agent responsible for
driving D[63:0]#, and, if ECC is implemented, must connect the appropriate
pins of all bus agents which use them.
Furthermore, the DBI# pins determine the polarity of the ECC signals. Each
pair of 2 ECC signals corresponds to one DBI# signal. When the DBI# signal is
active, the corresponding ECC pair is inverted and therefore sampled active
high.
DP[3:0]#
I/O
DP[3:0]# (Data Parity) provide optional parity protection for the data bus.
They are driven by the agent responsible for driving D[63:0]#, and, if parity is
implemented, must connect the appropriate pins of all bus agents which use
them.
DRDY#
I/O
DRDY# (Data Ready) is asserted by the data driver on each data transfer,
indicating valid data on the data bus. In a multi-common clock data transfer,
DRDY# may be deasserted to insert idle clocks. This signal must connect the
appropriate pins of all processor front side bus agents.
DSTBN[3:0]#
I/O
Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
DSTBP[3:0]#
I/O
Data strobe used to latch in D[63:0]#, DEP[7:0]# and DBI[3:0]#.
FERR#/PBE#
O
FERR#/PBE# (floating-point error/pending break event) is a multiplexed signal
and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,
FERR#/PBE# indicates a floating-point error and will be asserted when the
processor detects an unmasked floating-point error. When STPCLK# is not
asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387
coprocessor, and is included for compatibility with systems using MS-DOS*type floating-point error reporting. When STPCLK# is asserted, an assertion of
FERR#/PBE# indicates that the processor has a pending break event waiting
for service. The assertion of FERR#/PBE# indicates that the processor should
be returned to the Normal state. For additional information on the pending
break event functionality, including the identification of support of the feature
and enable/disable information, refer to Vol 3 of the Intel ® Architecture
Software Developer’s Manual and the Intel® Processor Identification and the
CPUID Instruction application note.
FORCEPR#
I
This input can be used to force activation of the Thermal Control Circuit.
GTLREF[3:0]
I
GTLREF determines the signal reference level for AGTL+ input pins. GTLREF is
used by the AGTL+ receivers to determine if a signal is an electrical 0 or an
electrical 1. Please refer to Table 2-23 for further details.
I/O
I/O
HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop
operation results. Any front side bus agent may assert both HIT# and HITM#
together to indicate that it requires a snoop stall, which can be continued by
reasserting HIT# and HITM# together, every other common clock.
Since multiple agents may deliver snoop results at the same time, HIT# and
HITM# are wire-OR signals which must connect the appropriate pins of all
processor front side bus agents. In order to avoid wire-OR glitches associated
with simultaneous edge transitions driven by multiple drivers, HIT# and HITM#
are activated on specific clock edges and sampled on specific clock edges.
HIT#
HITM#
ID[7:0]#
68
I
ID[7:0]# are the Transaction ID signals. They are driven during the Deferred
Phase by the deferring agent.
IDS#
I
IDS# is the ID Strobe signal. It is asserted to begin the Deferred Phase.
IERR#
O
IERR# (Internal Error) is asserted by a processor as the result of an internal
error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction
on the processor front side bus. This transaction may optionally be converted
to an external error signal (e.g., NMI) by system core logic. The processor will
keep IERR# asserted until the assertion of RESET#.
IGNNE#
I
IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a
numeric error and continue to execute noncontrol floating-point instructions. If
IGNNE# is deasserted, the processor generates an exception on a noncontrol
floating-point instruction if a previous floating-point instruction caused an
error. IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.
IGNNE# is an asynchronous signal. However, to ensure recognition of this
signal following an I/O write instruction, it must be valid a 6 clks before the I/O
write’s response.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 5 of 8)
Name
Type
Description
INIT#
I
INIT# (Initialization), when asserted, resets integer registers inside all
processors without affecting their internal caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured
during power-on configuration. The processor continues to handle snoop
requests during INIT# assertion. INIT# is an asynchronous signal and must
connect the appropriate pins of all processor front side bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then
the processor executes its Built-in Self-Test (BIST).
LINT0/INTR
LINT1/NMI
I
LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all front
side bus agents. When the APIC functionality is disabled, the LINT0 signal
becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI,
a nonmaskable interrupt. INTR and NMI are backward compatible with the
signals of those names on the Pentium processor. Both signals are
asynchronous.
These signals must be software configured via BIOS programming of the APIC
register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is
enabled by default after Reset, operation of these pins as LINT[1:0] is the
default configuration.
LOCK#
I/O
LOCK# indicates to the system that a set of transactions must occur atomically.
This signal must connect the appropriate pins of all processor front side bus
agents. For a locked sequence of transactions, LOCK# is asserted from the
beginning of the first transaction to the end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the
processor front side bus, it will wait until it observes LOCK# deasserted. This
enables symmetric agents to retain ownership of the processor front side bus
throughout the bus locked operation and ensure the atomicity of lock.
MCERR#
I/O
MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error
or a bus protocol violation. It may be driven by all processor front side bus
agents.
MCERR# assertion conditions are configurable at a system level. Assertion
options are defined as follows:
• Enabled or disabled.
• Asserted, if configured, for internal errors along with IERR#.
• Asserted, if configured, by the request initiator of a bus transaction after it
observes an error.
• Asserted by any bus agent when it observes an error in a bus transaction.
For more details regarding machine check architecture, refer to the IA-32
Intel ® Software Developer’s Manual, Volume 3: System Programming Guide or
the BIOS Writer’s Guide which includes the Dual-Core Intel® Xeon® Processor
7100 Series processor.
Since multiple agents may drive this signal at the same time, MCERR# is a
wired-OR signal which must connect the appropriate pins of all processor front
side bus agents. In order to avoid wire-OR glitches associated with
simultaneous edge transitions driven by multiple drivers, MCERR# is activated
on specific clock edges and sampled on specific clock edges.
ODTEN
I
ODTEN (On-die termination enable) should be connected to VTT through a
resistor to enable on-die termination for end bus agents. For middle bus
agents, pull this signal down via a resistor to ground to disable on-die
termination. Whenever ODTEN is high, on-die termination will be active,
regardless of other states of the bus.
OOD#
I
OOD# allows data delivery to occur subsequent to IDS# assertion during the
Deferred Phase.
PROCHOT#
O
The assertion of PROCHOT# (processor hot) indicates that the processor die
temperature has reached its thermal limit. See Section 6.2.4 for more details.
PWRGOOD
I
PWRGOOD (Power Good) is an input. The processor requires this signal to be a
clean indication that all Dual-Core Intel Xeon processor 7100 series clocks and
power supplies are stable and within their specifications. “Clean” implies that
the signal will remain low (capable of sinking leakage current), without
glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high
state. PWRGOOD can be driven inactive at any time, but clocks and power
must again be stable before a subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor. This signal is used to
protect internal circuits against voltage sequencing issues. It should be driven
high throughout boundary scan operation.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
69
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 6 of 8)
Name
Type
Description
I/O
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor front side bus agents. They are asserted by the current bus owner to
define the currently active transaction type. These signals are source
synchronous to ADSTB[1:0]#. Refer to the AP[1:0]# signal description for
details on parity checking of these signals.
RESET#
I
Asserting the RESET# signal resets all processors to known states and
invalidates their internal caches without writing back any of their contents. For
a power-on Reset, RESET# must stay active for at least 1 ms after VCC and
BCLK have reached their specified levels. On observing active RESET#, all front
side bus agents will deassert their outputs within two clocks. RESET# must not
be kept asserted for more than 10 ms.
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in Section 7.1.
RS[2:0]#
I
RS[2:0]# (Response Status) are driven by the response agent (the agent
responsible for completion of the current transaction), and must connect to the
appropriate pins of all processor front side bus agents.
RSP#
I
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor front side bus agents.
A correct parity signal is electrically high if an even number of covered signals
are electrically low and electrically low if an odd number of covered signals are
electrically low. If RS[2:0]# are all electrically high, RSP# is also electrically
high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC#
O
SKTOCC# (Socket occupied) will be pulled to ground by the processor to
indicate that the processor is present. There is no connection to the processor
silicon for this signal.
SM_ALERT#
O
SM_ALERT# (SMBus Alert) is an asynchronous interrupt line associated with
the SMBus Thermal Sensor device. It is an open-drain output and the
processor includes a 10kΩ pull-up resistor to SM_VCC for this signal. For more
information on the usage of the SM_ALERT# pin, see Section 7.4.9.
SM_CLK
I/O
The SM_CLK (SMBus Clock) signal is an input clock to the system management
logic which is required for operation of the system management features of the
Dual-Core Intel Xeon processor 7100 series. This clock is driven by the SMBus
controller and is asynchronous to other clocks in the processor.The processor
includes a 10 kΩ pull-up resistor to SM_VCC for this signal.
SM_DAT
I/O
The SM_DAT (SMBus Data) signal is the data signal for the SMBus. This signal
provides the single-bit mechanism for transferring data between SMBus
devices. The processor includes a 10 kΩ pull-up resistor to SM_VCC for this
signal.
SM_EP_A[2:0]
I
The SM_EP_A (EEPROM Select Address) pins are decoded on the SMBus in
conjunction with the upper address bits in order to maintain unique addresses
on the SMBus in a system with multiple processors. To set an SM_EP_A line
high, a pull-up resistor should be used that is no larger than 1 kΩ. The
processor includes a 10 kΩ pull-down resistor to VSS for each of these signals.
For more information on the usage of these pins, see Section 7.4.1.
SM_TS_A[1:0]
I
The SM_TS_A (Thermal Sensor Select Address) pins are decoded on the SMBus
in conjunction with the upper address bits in order to maintain unique
addresses on the SMBus in a system with multiple processors.
The device’s addressing, as implemented, includes a Hi-Z state for both
address pins. The use of the Hi-Z state is achieved by leaving the input floating
(unconnected).
For more information on the usage of these pins, see Section 7.4.1.
SM_VCC
I
SM_VCC provides power to the SMBus components on the Dual-Core Intel
Xeon processor 7100 series package.
SM_WP
I
WP (Write Protect) can be used to write protect the Scratch EEPROM. The
Scratch EEPROM is write-protected when this input is pulled high to SM_VCC.
The processor includes a 10 kΩ pull-down resistor to VSS for this signal.
REQ[4:0]#
70
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 7 of 8)
Name
Type
Description
SMI#
I
SMI# (System Management Interrupt) is asserted asynchronously by system
logic. On accepting a System Management Interrupt, processors save the
current state and enter System Management Mode (SMM). An SMI
Acknowledge transaction is issued, and the processor begins program
execution from the SMM handler.
On the Dual-Core Intel Xeon processor 7100 series, it is required that SMI#
assertion be observed 8 BCLKs before the Response Status (RS[2:0]#) is
observed by the processor.
If SMI# is asserted during the deassertion of RESET#, the processor will tristate its outputs.
STPCLK#
I
STPCLK# (Stop Clock), when asserted, causes processors to enter a low power
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction,
and stops providing internal clock signals to all processor core units except the
front side bus and APIC units. The processor continues to snoop bus
transactions and service interrupts while in Stop-Grant state. When STPCLK# is
deasserted, the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#
is an asynchronous input.
TCK
I
TCK (Test Clock) provides the clock input for the processor Test Access Port.
TDI
I
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
TDO
O
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
TEST_BUS
I
Must be connected to all other processor TEST_BUS signals in the system. See
the appropriate platform design guideline for termination details.
TESTHI[6:0]
I
TESTHI[6:0] must be connected to a VTT power source through a resistor for
proper processor operation. See Section 2.4 for more details.
THERMTRIP#
O
Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction
temperature has reached a temperature beyond which permanent silicon
damage may occur. THERMTRIP# (Thermal Trip) will activate at a temperature
that is approximately 15°C above the maximum case temperature (TC).
Measurement of the temperature is accomplished through an internal thermal
sensor. Upon assertion of THERMTRIP#, the processor will shut off its internal
clocks (thus halting program execution) in an attempt to reduce the processor
junction temperature. To protect the processor its core voltage (VCC) must be
removed following the assertion of THERMTRIP#. Driving of the THERMTRIP#
signals is enabled within 10 µs of the assertion of PWRGOOD and is disabled on
de-assertion of PWRGOOD. Once activated, THERMTRIP# remains latched until
PWRGOOD is de-asserted. While the deassertion of the PWRGOOD signal will
de-assert THERMTRIP#, if the processor’s junction temperature remains at or
above the trip level, THERMTRIP# will again be asserted within 10 µs of the
assertion of PWRGOOD. Thermtrip should not be sampled until 10 µs after
PWRGOOD assertion at the processor.
TMS
I
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
TRDY#
I
TRDY# (Target Ready) is asserted by the target (chipset) to indicate that it is
ready to receive a write or implicit writeback data transfer. TRDY# must
connect the appropriate pins of all front side bus agents.
TRST#
I
TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be
driven electrically low during power on Reset. Please refer to the eXtended
Debug Port: Debug Port Design Guide for Twin Castle Chipset Platforms or the
eXtended Debug Port: Debug Port Design Guide for MP Platforms for details.
VCACHE
I
VCACHE provides power to the L3 cache on the Dual-Core Intel Xeon processor
7100 series.
VCC
I
VCC provides power to the core logic of the Dual-Core Intel Xeon processor
7100 series.
VCCA
I
VCCA provides isolated power for the analog portion of the internal PLL’s. Use a
discrete RLC filter to provide clean power. Refer to the appropriate platform
design guide for complete implementation details.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
71
Signal Definitions
Table 5-1.
Signal Definitions (Sheet 8 of 8)
Name
Type
Description
VCC_CACHE_SENSE
VSS_CACHE_SENSE
O
VCC_CACHE_SENSE and VSS_CACHE_SENSE provide isolated, low impedance
connections to the processor cache voltage (VCACHE) and ground (VSS). They
can be used to sense or measure voltage or ground near the silicon with little
noise.
VCCIOPLL
I
VCCIOPLL provides isolated power for digital portion of the internal PLL’s. Follow
the guidelines for VCCA, and refer to the appropriate platform design guide for
complete implementation details.
VCCPLL
I
The on-die PLL filter solution will not be implemented on this platform. The
VCCPLL input should be left unconnected.
VCCSENSE
VSSSENSE
O
VCCSENSE and VSSSENSE provide isolated, low impedance connections to the
processor core voltage (VCC) and ground (VSS). These signals must be
connected to the voltage regulator feedback signals, which ensure the output
voltage (i.e. processor voltage) remains within specification. Please see the
applicable platform design guide for implementation details.
VID[5:0]
O
VID[5:0] (Voltage ID) pins are used to support automatic selection of VCC.
These are open drain signals that are driven by the processor and must be
pulled to no more than 3.3 V (+5% tolerance) with a resistor. Conversely, the
VCC VR output must be disabled prior to the voltage supply for these pins
becoming invalid. The VID pins are needed to support processor voltage
specification variations. See Table 2-4 for definitions of these pins. The VCC VR
must supply the voltage that is requested by these pins, or disable itself.
VIDPWRGD
I
The processor requires this input to determine that the supply voltage for
BSEL[1:0], VID[5:0], and CVID[3:0] is stable and within specification.
VSS
I
VSS is the ground plane for the Dual-Core Intel Xeon processor 7100 series.
VSSA
I
VSSA provides an isolated, internal ground for internal PLL’s. Do not connect
directly to ground. This pin is to be connected to VCCA and VCCIOPLL through a
discrete filter circuit.
VTT
I
VTT is the front side bus termination voltage.
VTTEN
O
VTTEN can be used as an output enable for the VTT regulator. VTTEN is used as
an electrical key to prevent processors with mechanically-equivalent pinouts
from accidentally booting in a Dual-Core Intel Xeon processor 7100 series
platform. Since VTTEN is an open circuit on the processor package, VTTEN
must be pulled up on the motherboard. Refer to the appropriate platform
design guide for implementation details.
§
72
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Thermal Specifications
6
Thermal Specifications
6.1
Package Thermal Specifications
The Dual-Core Intel Xeon processor 7100 series requires a thermal solution to maintain
temperatures within operating limits. Any attempt to operate the processor outside
these operating limits may result in permanent damage to the processor and
potentially other components within the system. As processor technology changes,
thermal management becomes increasingly crucial when building computer systems.
Maintaining the proper thermal environment is key to reliable, long-term system
operation.
A complete solution includes both component and system level thermal management
features. Component level thermal solutions can include active or passive heatsinks
attached to the processor Integrated Heat Spreader (IHS). Typical system level thermal
solutions may consist of system fans combined with ducting and venting.
For more information on designing a component level thermal solution, refer to the
Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines.
Note:
The boxed processor will ship with a component thermal solution. Refer to Section 8 for
details on the boxed processor.
6.1.1
Thermal Specifications
To allow the optimal operation and long-term reliability of Intel processor-based
systems, the processor must remain within the minimum and maximum case
temperature (TCASE) specifications as defined by the applicable thermal profile (see
Table 6-1 and Figure 6-1or Figure 6-2). Thermal solutions not designed to provide this
level of thermal capability may affect the long-term reliability of the processor and
system. For more details on thermal solution design, please refer to the appropriate
processor thermal/mechanical design guidelines.
The Dual-Core Intel Xeon processor 7100 series uses a methodology for managing
processor temperatures which is intended to support acoustic noise reduction through
fan speed control and assure processor reliability. Selection of the appropriate fan
speed will be based on the temperature reported by the processor’s Thermal Diode. If
the diode temperature is greater than or equal to Tcontrol (see Section 6.2.7), then the
processor case temperature must remain at or below the temperature as specified by
the thermal profile (see Figure 6-1 or Figure 6-2). If the diode temperature is less than
Tcontrol, then the case temperature is permitted to exceed the thermal profile, but the
diode temperature must remain at or below Tcontrol. Systems that implement fan
speed control must be designed to take these conditions into account. Systems that do
not alter the fan speed only need to guarantee the case temperature meets the thermal
profile specifications.
The Dual-Core Intel Xeon processor 7100 series thermal profile ensures adherence to
Intel reliability requirements. The thermal profile is representative of a industry
enabled 2U heat sink. In this scenario, it is expected that the Thermal Control Circuit
(TCC) would only be activated for very brief periods of time when running the most
power intensive applications. Refer to the Dual-Core Intel® Xeon® Processor 7100
Series Thermal/Mechanical Design Guidelines for details on system thermal solution
design, thermal profiles, and environmental considerations.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
73
Thermal Specifications
The upper point of the thermal profile consists of the Thermal Design Power (TDP)
defined in Table 6-1and the associated TCASE value. The lower point of the thermal
profile consists of x = PCONTROL_BASE and y = TCASE_MAX @ PCONTROL_BASE. Pcontrol is
defined as the processor power at which TCASE, calculated from the thermal profile,
corresponds to the lowest possible value of Tcontrol. This point is associated with the
Tcontrol value (see Section 6.2.7). However, because Tcontrol represents a diode
temperature, it is necessary to define the associated case temperature. This is
TCASE_MAX @ PCONTROL_BASE. Please see Section 6.2.7 and the Dual-Core Intel® Xeon®
Processor 7100 Series Thermal/Mechanical Design Guidelines for proper usage of the
Tcontrol specification.
The case temperature is defined at the geometric top center of the processor IHS.
Analysis indicates that real applications are unlikely to cause the processor to consume
maximum power dissipation for sustained time periods. Intel recommends that
complete thermal solution designs target the TDP indicated in Table 6-1. The Thermal
Monitor feature is intended to help protect the processor in the event that an
application exceeds the TDP recommendation for a sustained time period. For more
details on this feature, refer to Section 6.2. To ensure maximum flexibility for future
requirements, systems should be designed to the Flexible Motherboard (FMB)
guidelines, even if a processor with a lower thermal dissipation is currently planned.
Thermal Monitor or Thermal Monitor 2 feature must be enabled for the
processor to remain within specification.
Table 6-1.
Dual-Core Intel® Xeon® Processor 7100 Series Thermal Specifications
Thermal
Design Power
(W)
Minimum
TCASE
(°C)
Maximum
TCASE
(°C)
Greater than 3.0 GHz
150
5
See Figure 6-1
and Table 6-2
1,2
Less than or equal to
3.0 GHz
95
5
See Figure 6-2
and Table 6-3
1,2
QDF / S-Spec
Frequency
Notes
Note:
1.
2.
74
Thermal Design Power (TDP) should be used for processor thermal solution design targets. The TDP is not
the maximum power that the processor can dissipate. TDP is measured at maximum TCASE.
FMB, or Flexible Motherboard, guidelines provide a design target for meeting future thermal requirements.
See Section 2.10.1 for further information on FMB.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Thermal Specifications
Figure 6-1.
150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile
70
T CASE_MAX [°C]
65
60
55
50
45
20
40
60
80
100
Power [W]
Note:
Table 6-2.
120
140
160
y = 0.158 * x + 45
Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for
system and environmental implementation details.
150W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile
Pow er [W ]
P CONTROL_BASE = 31
35
40
45
50
55
60
65
70
75
80
85
90
95
TCASE_M AX [°C]
50
51
51
52
53
54
54
55
56
57
58
58
59
60
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Pow er [W ]
100
105
110
115
120
125
130
135
140
145
150
TCASE_M AX [°C]
61
62
62
63
64
65
65
66
67
68
69
75
Thermal Specifications
Figure 6-2.
95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile
65
TCASE_MAX [°C]
60
55
50
45
40
35
-35
-25
-15
-5
5
15
25
35
Pow er [W]
45
55
65
75
85
95
y = 0.158 * x + 45
Notes:
1.
Refer to the Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for
system and environmental implementation details.
2.
The TCONTROL_OFFSET for 95W TDP parts is greater than or equal to 16 °C
Table 6-3.
95W Dual-Core Intel® Xeon® Processor 7100 Series Thermal Profile
Pow er [W ]
P CONTROL_BASE = -31
TCASE_M AX [°C]
40
Pow er [W ]
40
TCASE_M AX [°C]
51
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
35
41
42
43
43
44
45
46
47
47
48
85
50
51
45
50
55
60
65
70
75
80
85
90
95
52
53
54
54
55
56
57
58
85
59
60
Note:
76
The TCONTROL_OFFSET for 95W TDP parts is greater than or equal to 16 °C
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Thermal Specifications
6.1.2
Thermal Metrology
The maximum and minimum case temperatures (TCASE) specified in Table 6-1 are
measured at the geometric top center of the processor integrated heat spreader (IHS).
Figure 6-3 illustrates the location where TCASE temperature measurements should be
made. For detailed guidelines on temperature measurement methodology, refer to the
Dual-Core Intel® Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines.
Figure 6-3.
Case Temperature (TCASE) Measurement Location
Measure from edge of IHS
19.2 mm [0.756 in]
Measure T CASE at this point
(geometric center of IHS)
19.2 mm [0.756 in]
53.34 mm FC-mPGA4 Package
Thermal grease should cover
entire area of IHS
6.2
Processor Thermal Features
6.2.1
Thermal Monitor
The Thermal Monitor feature helps control the processor temperature by activating the
Thermal Control Circuit (TCC) when the processor silicon reaches its maximum
operating temperature. The TCC reduces processor power consumption as needed by
modulating (starting and stopping) the internal processor core clocks. The Thermal
Monitor (or Thermal Monitor 2) must be enabled for the processor to be operating
within specifications. The temperature at which Thermal Monitor activates the thermal
control circuit is not user configurable and is not software visible. Bus traffic is snooped
in the normal manner, and interrupt requests are latched (and serviced during the time
that the clocks are on) while the TCC is active.
When the Thermal Monitor is enabled and a high temperature situation exists (i.e. TCC
is active), the clocks will be modulated by alternately turning the clocks off and on at a
duty cycle specific to the processor (typically 30-50%). Clocks will not be off for more
than 3 microseconds when the TCC is active. Cycle times are processor speed
dependent and will decrease as processor core frequencies increase. A small amount of
hysteresis has been included to prevent rapid active/inactive transitions of the TCC
when the processor temperature is near its maximum operating temperature. Once the
temperature has dropped below the maximum operating temperature and the
hysteresis timer has expired, the TCC goes inactive and clock modulation ceases.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
77
Thermal Specifications
With a thermal solution designed to meet the thermal profile, it is anticipated that the
TCC would only be activated for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable. A
thermal solution that is significantly under-designed may not be capable of cooling the
processor even when the TCC is active continuously. Refer to the Dual-Core Intel®
Xeon® Processor 7100 Series Thermal/Mechanical Design Guidelines for information on
designing a thermal solution.
The duty cycle for the TCC, when activated by the Thermal Monitor, is factory
configured and cannot be modified. The Thermal Monitor does not require any
additional hardware, software drivers, or interrupt handling routines.
6.2.2
Thermal Monitor 2
The Dual-Core Intel Xeon processor 7100 series also supports an additional power
reduction capability known as Thermal Monitor 2 (TM2). This mechanism provides an
efficient means for limiting the processor temperature by reducing the power
consumption within the processor. The Thermal Monitor (or Thermal Monitor 2) feature
must be enabled for the processor to be operating within specifications.
When Thermal Monitor 2 is enabled and a high temperature situation is detected, the
Thermal Control Circuit (TCC) will be activated. The TCC causes the processor to adjust
its operating frequency (via the bus multiplier) and input voltage (via the VID signals).
This combination of reduced frequency and VID results in a decrease to the processor
power consumption.
A processor enabled for Thermal Monitor 2 includes two operating points, each
consisting of a specific operating frequency and voltage. The first operating point
represents the normal operating condition for the processor. Under this condition, the
core-frequency-to-system-bus multiplier utilized by the processor is that contained in
the IA32_FLEX_BRVID_SEL MSR and the VID is that specified in Table 2-10. These
parameters represent normal system operation.
The second point consists of both a lower operating frequency and voltage. When the
TCC is activated, the processor automatically transitions to the new frequency. This
transition occurs very rapidly (on the order of 5 microseconds). During the frequency
transition, the processor is unable to service any bus requests, and consequently, all
bus traffic is blocked. Edge-triggered interrupts will be latched and kept pending until
the processor resumes operation at the new frequency.
Once the new operating frequency is engaged, the processor will transition to the new
core operating voltage by issuing a new VID code to the voltage regulator. The voltage
regulator must support dynamic VID steps in order to support Thermal Monitor 2.
During the voltage change, it will be necessary to transition through multiple VID codes
to reach the target operating voltage. Each step will be one VID table entry (see
Table 2-10). The processor continues to execute instructions during the voltage
transition. Operation at the lower voltage reduces the power consumption of the
processor.
A small amount of hysteresis has been included to prevent rapid active/inactive
transitions of the TCC when the processor temperature is near its maximum operating
temperature. Once the temperature has dropped below the maximum operating
temperature, and the hysteresis timer has expired, the operating frequency and
voltage transition back to the normal system operating point. Transition of the VID code
will occur first, in order to ensure proper operation once the processor reaches its
normal operating frequency. Refer to Figure 6-4 for an illustration of this ordering.
78
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Thermal Specifications
Figure 6-4.
Thermal Monitor 2 Frequency and Voltage Ordering
TTM2
Temperature
fMAX
fTM2
Frequency
VNOM
VTM2
Vcc
Time
T(hysteresis)
The PROCHOT# signal is asserted when a high temperature situation is detected,
regardless of whether Thermal Monitor or Thermal Monitor 2 is enabled.
If a processor has its Thermal Control Circuit activated via a Thermal Monitor 2 event,
and an Enhanced Intel SpeedStep® Technology transition to a higher target frequency
(through the applicable MSR write) is attempted, this frequency transition will be
delayed until the TCC is deactivated and the TM2 event is complete.
Note:
Not all processors are capable of supporting Thermal Monitor 2. More details on which
processor frequencies will support this feature will be provided in future releases of the
NDA Specification Update.
6.2.3
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption. This mechanism is referred to as “OnDemand” mode and is distinct from the Thermal Monitor and Thermal Monitor 2
features. On-Demand mode is intended as a means to reduce system level power
consumption. Systems utilizing the Dual-Core Intel Xeon processor 7100 series
processor must not rely on software usage of this mechanism to limit the processor
temperature.
If bit 4 of the IA_32_CLOCK_MODULATION MSR is written to a ‘1’, the processor will
immediately reduce its power consumption via modulation (starting and stopping) of
the internal core clock, independent of the processor temperature. When using OnDemand mode, the duty cycle of the clock modulation is programmable via bits 3:1 of
the same IA_32_CLOCK_MODULATION MSR. In On-Demand mode, the duty cycle can
be programmed from 12.5% on / 87.5% off to 87.5% on / 12.5% off in 12.5%
increments. On-Demand mode may be used in conjunction with the Thermal Monitor or
Thermal Monitor 2. If Thermal Monitor is enabled and the system tries to enable OnDemand mode at the same time the TCC is engaged, the factory configured duty cycle
of the TCC will override the duty cycle selected by the On-Demand mode.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
79
Thermal Specifications
6.2.4
PROCHOT# Signal Pin
An external signal, PROCHOT# (processor hot), is asserted when the processor die
temperature has reached its factory configured trip point. If the Thermal Monitor is
enabled (note that the Thermal Monitor must be enabled for the processor to be
operating within specification), the TCC will be active when PROCHOT# is asserted. The
processor can be configured to generate an interrupt upon the assertion or deassertion of PROCHOT#. Refer to the IA-32 Intel® Architecture Software Developer’s
Manual and the Cedar Mill Processor Family BIOS Writer’s Guide for specific register
and programming details.
PROCHOT# is designed to assert at or a few degrees higher than maximum TCASE (as
specified by the thermal profile) when dissipating TDP power, and cannot be interpreted
as an indication of processor case temperature. This temperature delta accounts for
processor package, lifetime, and manufacturing variations and attempts to ensure the
Thermal Control Circuit is not activated below maximum TCASE when dissipating TDP
power. There is no defined or fixed correlation between the PROCHOT# trip
temperature, the case temperature, or the thermal diode temperature. Thermal
solutions must be designed to the processor specifications and cannot be adjusted
based on experimental measurements of TCASE, PROCHOT#, or Tdiode on random
processor samples.
6.2.5
FORCEPR# Signal Pin
The FORCEPR# (force power reduction) input can be used by the platform to force the
Dual-Core Intel Xeon processor 7100 series to activate the TCC. If the Thermal Monitor
is enabled, the TCC will be activated upon the assertion of the FORCEPR# signal. The
TCC will remain active until the system deasserts FORCEPR#. FORCEPR# is an
asynchronous input. FORCEPR# can be used to thermally protect other system
components. To use the voltage regulator (VR) as an example, when the FORCEPR# pin
is asserted, the TCC in the processor will activate, reducing the current consumption of
the processor and the corresponding temperature of the VR.
It should be noted that assertion of FORCEPR# does not automatically assert
PROCHOT#. As mentioned previously, the PROCHOT# signal is asserted when a high
temperature situation is detected. A minimum pulse width of 500 microseconds is
recommended when FORCEPR# is asserted by the system. Sustained activation of the
FORCEPR# pin may cause noticeable platform performance degradation.
Refer to the appropriate platform design guide for details on implementing the
FORCEPR# signal feature.
6.2.6
THERMTRIP# Signal Pin
Regardless of whether or not Thermal Monitor or Thermal Monitor 2 is enabled, in the
event of a catastrophic cooling failure, the processor will automatically shut down when
the silicon has reached an elevated temperature (refer to the THERMTRIP# definition in
Table 5-1). At this point, the system bus signal THERMTRIP# will go active and stay
active as described in Table 5-1. THERMTRIP# activation is independent of processor
activity and does not generate any bus cycles. Intel also recommends removal of VTT.
6.2.7
TCONTROL and Fan Speed Reduction
TCONTROL is a temperature specification based on a temperature reading from the
thermal diode. The value for TCONTROL_OFFSET will be calibrated in manufacturing and
configured for each processor. The TCONTROL temperature for a given processor can be
80
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Thermal Specifications
obtained by reading the IA32_TEMPERATURE_TARGET MSR in the processor. The
TCONTROL_OFFSET value that is read from the IA32_TEMPERATURE_TARGET MSR (1A2H)
must be converted from Hexadecimal to Decimal and added to a TCONTROL_BASE value of
50°C for 150W TDP parts and added to a TCONTROL_BASE value of 40°C for 95W TDP
parts.
The Platform Id Bits located in the IA32_PLATFORM_ID MSR (17H) Bits[52:50] may be
used by the BIOS to determine the TDP of the processor. A 150W TDP part has a
Platform ID of ‘001’(Processor Flag 1) and a 95W TDP part has a Platform ID of ‘101’
(Processor Flag 5). Refer to the Cedar Mill Processor Family BIOS Writers Guide for
specific register details.
The value of TCONTROL_OFFSET may vary from 0x00h to 0x1Eh. Refer to the Cedar Mill
Processor Family BIOS Writers Guide for specific register details.
When Tdiode is above TCONTROL, then TCASE must be at or below TCASE_MAX as defined
by the thermal profile (see Figure 6-1 and Table 6-2 or Figure 6-2 and Table 6-3).
Otherwise, the processor temperature can be maintained at TCONTROL.
6.2.8
Thermal Diode
The processor incorporates two on-die thermal diodes. A thermal sensor located on the
processor package monitors the die temperature of the processor for thermal
management/long term die temperature change purposes. The thermal diodes are
separate from the Thermal Monitor’s thermal sensor and cannot be used to predict the
behavior of the Thermal Monitor.
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
81
Thermal Specifications
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7
Features
7.1
Power-On Configuration Options
Several configuration options can be set by hardware. The Dual-Core Intel Xeon
processor 7100 series samples its hardware configuration at reset, on the active-toinactive transition of RESET#. For specifications on these options, refer to Table 7-1.
The sampled information configures the processor for subsequent operation. These
configuration options can only be changed by another reset. All resets configure the
processor. For reset purposes, the processor does not distinguish between a “warm”
reset and a “power-on” reset.
Table 7-1.
Power-On Configuration Option Pins
Pin1,2
Configuration Option
SMI#
Output tri state
or
A[39]# for Arb ID 3 (middle agent)
A[36]# for Arb ID 0 (end agent)
Execute BIST (Built-In Self Test)
INIT# or A[3]#
In Order Queue de-pipelining (set IOQ depth to 1)
A[7]#
Disable MCERR# observation
A[9]#
Disable BINIT# observation
APIC cluster ID
Disable bus parking
A[10]#
A[12:11]#
A[15]#
Core Frequency-to-Front Side Bus Multiplier
A[21:16]#
Symmetric agent arbitration ID
BR[1:0]#
Disable Hyper-Threading Technology (HT Technology)
A[31]#
Note:
1.
Asserting this signal during RESET# selects the corresponding option.
2.
Address pins not identified in this table as configuration options should not be asserted during RESET#.
7.2
Clock Control and Low Power States
The processor allows the use of HALT and Stop-Grant states to reduce power
consumption by stopping the clock to internal sections of the processor, depending on
each particular state. See Figure 7-1 for a visual representation of the processor low
power states.
The Dual-Core Intel Xeon processor 7100 series adds support for Enhanced HALT power
down state. Refer to Figure 7-1 and the following sections. For more configuration
details, also refer to the Cedar Mill Processor Family BIOS Writer’s Guide.
The Stop-Grant state requires chipset and BIOS support on multiprocessor systems. In
a multiprocessor system, all the STPCLK# signals are bussed together, thus all
processors are affected in unison. The Hyper-Threading Technology feature adds the
conditions that all logical processors share the same STPCLK# signal internally. When
the STPCLK# signal is asserted, the processor enters the Stop-Grant state, issuing a
Stop-Grant Special Bus Cycle (SBC) for each processor or logical processor. The chipset
needs to account for a variable number of processors asserting the Stop-Grant SBC on
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
83
Features
the bus before allowing the processor to be transitioned into one of the lower processor
power states. Refer to the applicable chipset specification and the Cedar Mill Processor
Family BIOS Writer’s Guide for more information.
7.2.1
Normal State
This is the normal operating state for the processor.
7.2.2
HALT or Enhanced Power Down State
The Enhanced HALT power down state is configured and enabled via the BIOS. Refer to
the Cedar Mill Processor Family BIOS Writer’s Guide for Enhanced HALT state
configuration information. If the Enhanced HALT state is not enabled, the default power
down state entered will be HALT. Refer to the section below for details on HALT and
Enhanced HALT states.
7.2.2.1
HALT Power Down State
HALT is a low power state entered when all logical processors have executed the HALT
or MWAIT instruction. When one of the logical processors executes the HALT or MWAIT
instruction, that logical processor is halted; however, the other processor continues
normal operation. The processor transitions to the Normal state upon the occurrence of
SMI#, BINIT#, INIT#, LINT[1:0] (NMI, INTR), or an interrupt delivered over the front
side bus. RESET# causes the processor to immediately initialize itself.
The return from a System Management Interrupt (SMI) handler can be to either
Normal Mode or the HALT Power Down state. See the IA-32 Intel®Architecture Software
Developer's Manual, Volume III: System Programming Guide for more information.
The system can generate a STPCLK# while the processor is in the HALT Power Down
state. When the system deasserts the STPCLK# interrupt, the processor returns
execution to the HALT state.
While in HALT Power Down state, the processor processes bus snoops and interrupts.
7.2.2.2
Enhanced HALT Power Down State
Enhanced HALT state is a low power state entered when all logical processors have
executed the HALT or MWAIT instructions and Enhanced HALT state has been enabled
via the BIOS. When one of the logical processors executes the HALT instruction, that
logical processor is halted; however, the other processor continues normal operation.
The Enhanced HALT state is generally a lower power state than the Stop Grant state.
The processor automatically transitions to a lower core frequency and voltage operating
point before entering the Enhanced HALT state. Note that the processor FSB frequency
is not altered; only the internal core frequency is changed. When entering the low
power state, the processor first switches to the lower bus ratio and then transitions to
the lower VID.
While in the Enhanced HALT state, the processor processes bus snoops.
The processor exits the Enhanced HALT state when a break event occurs. When the
processor exits the Enhanced HALT state, it first transitions the VID to the original
value and then changes the bus ratio back to the original value.
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Figure 7-1.
Stop Clock State Machine
HALT or MWAIT Instruction and
HALT Bus Cycle Generated
Normal State
Normal execution
S
De TPC
-a LK
ss #
er
te
d
STPCLK#
De-asserted
S
As TPC
se L
rte K#
d
STPCLK#
Asserted
INIT#, BINIT#, INTR, NMI, SMI#,
RESET#, FSB interrupts
Enhanced HALT or HALT State
BCLK running
Snoops and interrupts allowed
Snoop
Event
Occurs
Snoop
Event
Serviced
Enhanced HALT Snoop or HALT
Snoop State
BCLK running
Service snoops to caches
Stop Grant State
BCLK running
Snoops and interrupts allowed
7.2.3
Snoop Event Occurs
Snoop Event Serviced
Stop Grant Snoop State
BCLK running
Service snoops to caches
Stop-Grant State
When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20
bus clocks after the response phase of the processor-issued Stop Grant Acknowledge
special bus cycle. For the Dual-Core Intel Xeon processor 7100 series, both logical
processors must be in the Stop-Grant state before the deassertion of STPCLK#.
Since the AGTL+ signal pins receive power from the front side bus, these pins should
not be driven (allowing the level to return to VTT) for minimum power drawn by the
termination resistors in this state. In addition, all other input pins on the front side bus
should be driven to the inactive state.
BINIT# is not serviced while the processor is in Stop-Grant state. The event is latched
and can be serviced by software upon exit from the Stop-Grant state.
RESET# causes the processor to immediately initialize itself, but the processor will stay
in Stop-Grant state. A transition back to the Normal state occurs with the deassertion
of the STPCLK# signal.
A transition to the Grant Snoop state occurs when the processor detects a snoop on the
front side bus (see Section 7.2.4).
While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the
processor, and only serviced when the processor returns to the Normal state. Only one
occurrence of each event is recognized upon return to the Normal state.
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While in Stop-Grant state, the processor processes snoops on the front side bus and
latches interrupts delivered on the front side bus.
The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is
asserted if there is any pending interrupt latched within the processor. Pending
interrupts that are blocked by the EFLAGS.IF bit being clear still cause assertion of
PBE#. Assertion of PBE# indicates to system logic that it should return the processor to
the Normal state.
7.2.4
Enhanced HALT Snoop State or HALT Snoop State,
Stop Grant Snoop State
The Enhanced HALT Snoop state is used in conjunction with the Enhanced HALT state.
If Enhanced HALT state is not enabled in the BIOS, the default Snoop state entered will
be the HALT Snoop state. Refer to the sections below for details on HALT Snoop state,
Grant Snoop state and Enhanced HALT Snoop state.
7.2.4.1
HALT Snoop State, Stop Grant Snoop State
The processor responds to snoop or interrupt transactions on the front side bus while in
Stop-Grant state or in HALT Power Down state. During a snoop or interrupt transaction,
the processor enters the HALT/Grant Snoop state. The processor stays in this state
until the snoop on the front side bus has been serviced (whether by the processor or
another agent on the front side bus) or the interrupt has been latched. After the snoop
is serviced or the interrupt is latched, the processor will return to the Stop-Grant state
or HALT Power Down state, as appropriate.
7.2.4.2
Enhanced HALT Snoop State
The Enhanced HALT Snoop state is the default Snoop state when the Enhanced HALT
state is enabled via the BIOS. The processor remains in the lower bus ratio and VID
operating point of the Enhanced HALT state.
While in the Enhanced HALT Snoop state, snoops and interrupt transactions are
handled the same way as in the HALT Snoop state. After the snoop is serviced or the
interrupt is latched, the processor returns to the Enhanced HALT state.
7.3
Enhanced Intel SpeedStep® Technology
Enhanced Intel SpeedStep Technology enables the processor to switch between
frequency and voltage points, which may result in platform power savings. In order to
support this technology, the system must support dynamic VID transitions. Switching
between voltage/frequency states is software controlled. For more configuration details
also refer to the Cedar Mill Processor Family BIOS Writer's Guide.
Note:
Not all processors are capable of supporting Enhanced Intel SpeedStep Technology.
More details on which processor frequencies will support this feature will be provided in
future releases of the NDA Specification Update.
Enhanced Intel SpeedStep Technology is a technology that creates processor
performance states (P-states). P-states are power consumption and capability states
within the Normal state. Enhanced Intel SpeedStep technology enables real-time
dynamic switching between frequency and voltage points. It alters the performance of
the processor by changing the bus to core frequency ratio and voltage. This allows the
processor to run at different core frequencies and voltages to best serve the
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
performance and power requirements of the processor and system. Note that the front
side bus is not altered; only the internal core frequency is changed. In order to run at
reduced power consumption, the voltage is altered in step with the bus ratio.
The following are key features of Enhanced Intel SpeedStep technology:
• Voltage/frequency selection is software controlled by writing to processor MSR’s
(Model Specific Registers), thus eliminating chipset dependency.
— If the target frequency is higher than the current frequency, VCC is incremented
in steps (+12.5 mV) by placing a new value on the VID signals and the
processor shifts to the new frequency. Note that the top frequency for the
processor can not be exceeded.
— If the target frequency is lower than the current frequency, the processor shifts
to the new frequency and VCC is then decremented in steps (-12.5 mV) by
changing the target VID through the VID signals.
Refer to the Cedar Mill Processor Family BIOS Writer’s Guide for specific information to
enable and configure Enhanced Intel SpeedStep technology in BIOS.
7.4
System Management Bus (SMBus) Interface
The Dual-Core Intel Xeon processor 7100 series package includes an SMBus interface
which allows access to a memory component with two sections (referred to as the
Processor Information ROM and the Scratch EEPROM) and a thermal sensor on the
substrate. The SMBus thermal sensor may be used to read the thermal diode
mentioned in Section 6.2.8. These devices and their features are described below.
The SMBus thermal sensor and its associated thermal diode are not related to and are
completely independent of the precision, on-die temperature sensor and thermal
control circuit (TCC) of the Thermal Monitor or Thermal Monitor 2 features discussed in
Section 6.2.1.
The processor SMBus implementation uses the clock and data signals of the System
Management Bus (SMBus) Specification. It does not implement the SMBSUS# signal.
Layout and routing guidelines are available in the appropriate platform design guide
document.
For platforms which do not implement any of the SMBus features found on the
processor, all of the SMBus connections, except SM_VCC, to the socket pins may be
left unconnected (SM_ALERT#, SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0],
SM_WP).
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Features
Figure 7-2.
Logical Schematic of SMBus Circuitry
Note:
7.4.1
Actual implementation may vary. This figure is provided to offer a general understanding of the
architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form “1010XXXZb”. The “XXX” bits are defined by pull-up and pull-down resistors
on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The “Z” bit is the read/write bit for the serial bus transaction.
The thermal sensor internally decodes one of three upper address patterns from the
bus of the form “0011XXXZb”, “1001XXXZb”, or “0101XXXZb”. The device’s addressing,
as implemented, uses the SM_TS_A[1:0] pins in either the HI, LO, or Hi-Z state.
Therefore, the thermal sensor supports nine unique addresses. To set either pin for the
Hi-Z state, the pin must be left floating. As before, the “Z” bit is the read/write bit for
the serial transaction.
Note that addresses of the form “0000XXXXb” are Reserved and should not be
generated by an SMBus master. The thermal sensor samples and latches the
SM_TS_A[1:0] signals at power-up. System designers should ensure that these signals
are at valid VIH, VIL, or floating input levels prior to or while the thermal sensor’s
SM_VCC supply powers up. This should be done by pulling the pins to SM_VCC or VSS
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
via a 1 kΩ or smaller resistor, or leaving the pins floating to achieve the Hi-Z state. If
the system designer wants to drive the SM_TS_A[1:0] pins with logic, the designer
must still ensure that the pins are at valid input levels prior to or while the SM_VCC
supply ramps up. The system designer must also ensure that their particular
implementation does not add excessive capacitance to the address inputs. Excess
capacitance at the address inputs may cause address recognition problems. Refer to
the appropriate platform design guide document.
Figure 7-2 shows a logical diagram of the pin connections. Table 7-2 and Table 7-3
describe the address pin connections and how they affect the addressing of the
devices.
Table 7-2.
Thermal Sensor SMBus Addressing
Address
(Hex)
3Xh
5Xh
9Xh
Upper
Address1
Device Select
8-bit Address Word on Serial Bus
SM_TS_A1
SM_TS_A0
b[7:0]
0
0
0011000Xb
0011
0101
1001
2
0
Z
0011001Xb
0
1
0011010Xb
Z2
0
0101001Xb
Z2
2
Z
0101010Xb
Z2
1
0101011Xb
1
0
1001100Xb
1
Z2
1001101Xb
1
1
1001110Xb
Notes:
1.
Upper address bits are decoded in conjunction with the device select pins.
2.
A tri-state or “Z” state on this pin is achieved by leaving this pin unconnected.
Note:
System management software must be aware of the processor dependent addresses
for the thermal sensor.
Table 7-3.
Memory Device SMBus Addressing
Address
(Hex)
Upper
Address1
Device Select
R/W
bits 7-4
SM_EP_A2
bit 3
SM_EP_A1
bit 2
SM_EP_A0
bit 1
bit 0
A0h/A1h
1010
0
0
0
X
A2h/A3h
1010
0
0
1
X
A4h/A5h
1010
0
1
0
X
A6h/A7h
1010
0
1
1
X
A8h/A9h
1010
1
0
0
X
AAh/ABh
1010
1
0
1
X
ACh/ADh
1010
1
1
0
X
AEh/AFh
1010
1
1
1
X
Note:
1.
This addressing scheme will support up to 8 processors on a single SMBus.
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Features
7.4.2
PIROM and Scratch EEPROM Supported SMBus
Transactions
The Processor Information ROM (PIROM) responds to two SMBus packet types: Read
Byte and Write Byte. However, since the PIROM is write-protected, it will acknowledge a
Write Byte command but ignore the data. The Scratch EEPROM responds to Read Byte
and Write Byte commands. Table 7-4 diagrams the Read Byte command. Table 7-5
diagrams the Write Byte command. Following a write cycle to the scratch ROM,
software must allow a minimum of 10 ms before accessing either ROM of the processor.
In the tables, ‘S’ represents the SMBus start bit, ‘P’ represents a stop bit, ‘R’ represents
a read bit, ‘W’ represents a write bit, ‘A’ represents an acknowledge (ACK), and ‘///’
represents a negative acknowledge (NACK). The shaded bits are transmitted by the
Processor Information ROM or Scratch EEPROM, and the bits that aren’t shaded are
transmitted by the SMBus host controller. In the tables, the data addresses indicate 8
bits. The SMBus host controller should transmit 8 bits with the most significant bit
indicating which section of the EEPROM is to be addressed: the Processor Information
ROM (MSB = 0) or the Scratch EEPROM (MSB = 1).
Table 7-4.
Table 7-5.
7.4.3
Read Byte SMBus Packet
S
Slave
Addres
s
Write
A
Comman
d Code
A
S
Slave
Address
Read
A
Data
///
P
1
7-bits
1
1
8-bits
1
1
7-bits
1
1
8-bits
1
1
Write Byte SMBus Packet
S
Slave Address
Write
A
Command Code
A
Data
A
P
1
7-bits
1
1
8-bits
1
8-bits
1
1
Processor Information ROM (PIROM)
The lower half (128 bytes) of the SMBus memory component is an electrically
programmed read-only memory with information about the processor. This information
is permanently write-protected. Table 7-6 shows the data fields and Section 7.4.3
provides the formats of the data fields included in the Processor Information ROM
(PIROM).
The PIROM consists of the following sections:
• Header
• Processor Data
• Processor Core Data
• Cache Data
• Package Data
• Part Number Data
• Thermal Reference Data
• Feature Data
• Other Data
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Table 7-6.
Processor Information ROM Data Sections (Sheet 1 of 2)
Offset/Section
# of
Bits
Function
Notes
8
Data Format Revision
Two 4-bit hex digits
Header:
00h
01 - 02h
16
PIROM Size
Size in bytes (MSB first)
03h
8
Processor Data Address
Byte pointer, 00h if not present
04h
8
Processor Core Data
Address
Byte pointer, 00h if not present
05h
8
L3 Cache Data Address
Byte pointer, 00h if not present
06h
8
Package Data Address
Byte pointer, 00h if not present
07h
8
Part Number Data Address
Byte pointer, 00h if not present
08h
8
Thermal Reference Data
Address
Byte pointer, 00h if not present
09h
8
Feature Data Address
Byte pointer, 00h if not present
0Ah
0B - 0Ch
0Dh
8
Other Data Address
Byte pointer, 00h if not present
16
Reserved
Reserved
8
Checksum
1 byte checksum
Processor Data:
0E - 13h
48
S-spec/QDF Number
Six 8-bit ASCII characters
14h
6
2
Reserved
Sample/Production
Reserved (most significant bits)
00b = Sample, 01b = Production
15h
8
Checksum
1 byte checksum
2
Processor Core Type
From CPUID
4
Processor Core Family
From CPUID
4
Processor Core Model
From CPUID
4
Processor Core Stepping
From CPUID
2
Reserved
Reserved for future use
Processor Core
Data:
16 - 17h
18 - 19h
16
Reserved
Reserved for future use
1A - 1Bh
16
Front Side Bus Speed
16-bit binary number (in MHz)
2
6
Multiprocessor Support
Reserved
00b = UP,01b = DP,10b = RSVD,11b = MP
Reserved
1D - 1Eh
16
Maximum Core Frequency
16-bit binary number (in MHz)
1F - 20h
16
Maximum Core VID
Maximum VCC requested by VID outputs in
mV
21 - 22h
1Ch
16
Minimum Core Voltage
Minimum processor DC VCC in mV
23h
8
TCASE Maximum
Maximum case temperature spec in °C
24h
8
Checksum
1 byte checksum
Cache Data:
25 - 26h
16
Reserved
Reserved for future use
27 - 28h
16
L2 Cache Size
16-bit binary number (in KB)
29 - 2Ah
16
L3 Cache Size
16-bit binary number (in KB)
2B - 2Ch
16
Maximum Cache CVID
Maximum VCACHE requested by CVID
outputs in mV
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Features
Table 7-6.
Processor Information ROM Data Sections (Sheet 2 of 2)
# of
Bits
Function
Notes
2D - 2Eh
16
Minimum Cache Voltage
Minimum processor DC VCACHE in mV
2F - 30h
16
Reserved
Reserved
8
Checksum
1 byte checksum
Offset/Section
31h
Package Data:
32 - 35h
32
Package Revision
Four 8-bit ASCII characters
36h
8
Reserved
Reserved for future use
37h
8
Checksum
1 byte checksum
38 - 3Eh
56
Processor Part Number
Seven 8-bit ASCII characters
3F - 4Ch
112
Reserved
Reserved
4D - 54h
64
Processor Electronic
Signature
64-bit identification number
55 - 6Eh
208
Reserved
Reserved
8
Checksum
1 byte checksum
Part Number Data:
6Fh
Thermal Ref. Data:
70h
8
Reserved
Reserved
16
Reserved
Reserved
8
Checksum
1 byte checksum
32
Processor Core Feature
Flags
From CPUID function 1, EDX contents
78h
8
Processor Feature Flags
79h
8
Processor Thread and Core
Information
7Ah
8
Additional Processor Feature
Flags
[7] = Reserved
[6] = Intel® Cache Safe Technology
[5] = C1E State
[4] = Intel® Virtualization Technology
[3] = Execute Disable
[2] = Intel® 64
[1] = Thermal Monitor TM2
[0] = Enhanced Intel® SpeedStep
Technology
7B-7Ch
16
Thermal Adjustment Factors
(Pending)
[15:8] = Measurement Correction Factor
[7:0] = Temperature Target
7D-7Eh
16
Reserved
Reserved
8
Checksum
1 byte checksum
71 - 72h
73h
Feature Data:
74 - 77h
7Fh
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
=
=
=
=
=
=
=
=
Multi-Core
Serial Signature
Electronic Signature Present
Thermal Sense Device Present
Reserved
OEM EEPROM Present
Core VID Present
L3 Cache Present
[7:4] = Reserved
[3:2] = Number of cores
[1:0] = Number of threads per core
Details on each of these sections are described below.
Note:
92
Reserved fields or bits SHOULD be programmed to zeros. However, OEMs should not
rely on this model.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.1
Header
To maintain backward compatibility, the Header defines the starting address for each
subsequent section of the PIROM. Software should check for the offset before reading
data from a particular section of the ROM.
Example: Code looking for the cache data of a processor would read offset 05h to find
a value of 25h. 25h is the first address within the 'Cache Data' section of the PIROM.
7.4.3.1.1
DFR: Data Format Revision
This location identifies the data format revision of the PIROM data structure. Writes to
this register have no effect.
Offset:
00h
Bit
Description
7:0
Data Format Revision
The data format revision is used whenever fields within the PIROM are
redefined. The initial definition will begin at a value of 1. If a field, or bit
assignment within a field, is changed such that software needs to discern
between the old and new definition, then the data format revision field will be
incremented.
00h: Reserved
01h: Initial definition
02h: Second revision
03h: Third revision (Defined by this EMTS)
04h-FFh: Reserved
7.4.3.1.2
PISIZE: PIROM Size
This location identifies the PIROM size. Writes to this register have no effect.
Offset:
01h-02h
Bit
15:0
Description
PIROM Size
The PIROM size provides the size of the device in hex bytes. The MSB is at
location 01h, the LSB is at location 02h.
0000h - 007Fh: Reserved
0080h: 128 byte PIROM size
0081- FFFFh: Reserved
7.4.3.1.3
PDA: Processor Data Address
This location provides the offset to the Processor Data Section. Writes to this register
have no effect.
Offset:
03h
Bit
7:0
Description
Processor Data Address
Byte pointer to the Processor Data section
00h: Processor Data section not present
01h - 0Dh: Reserved
0Eh: Processor Data section pointer value
0Fh-FFh: Reserved
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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Features
7.4.3.1.4
PCDA: Processor Core Data Address
This location provides the offset to the Processor Core Data Section. Writes to this
register have no effect.
Offset:
04h
Bit
7:0
Description
Processor Core Data Address
Byte pointer to the Processor Data section
00h: Processor Core Data section not present
01h - 15h: Reserved
16h: Processor Core Data section pointer value
17h-FFh: Reserved
7.4.3.1.5
L3CDA: L3 Cache Data Address
This location provides the offset to the L3 Cache Data Section. Writes to this register
have no effect.
Offset:
05h
Bit
7:0
Description
L3 Cache Data Address
Byte pointer to the L3 Cache Data section
00h: L3 Cache Data section not present
01h - 24h: Reserved
25h: L3 Cache Data section pointer value
26h-FFh: Reserved
7.4.3.1.6
PKDA: Package Data Address
This location provides the offset to the Package Data Section. Writes to this register
have no effect.
Offset:
Bit
7:0
06h
Description
Package Data Address
Byte pointer to the Package Data section
00h: Package Data section not present
01h - 31h: Reserved
32h: Package Data section pointer value
33h-FFh: Reserved
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Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
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7.4.3.1.7
PNDA: Part Number Data Address
This location provides the offset to the Part Number Data Section. Writes to this
register have no effect.
Offset:
07h
Bit
Description
7:0
Part Number Data Address
Byte pointer to the Part Number Data section
00h: Part Number Data section not present
01h - 37h: Reserved
38h: Part Number Data section pointer value
39h-FFh: Reserved
7.4.3.1.8
TRDA: Thermal Reference Data Address
This location provides the offset to the Thermal Reference Data Section. Writes to this
register have no effect.
Offset:
08h
Bit
7:0
Description
Thermal Reference Data Address
Byte pointer to the Thermal Reference Data section
00h: Thermal Reference Data section not present
01h - 6Fh: Reserved
70h: Thermal Reference Data section pointer value
71h-FFh: Reserved
7.4.3.1.9
FDA: Feature Data Address
This location provides the offset to the Feature Data Section. Writes to this register
have no effect.
Offset:
09h
Bit
7:0
Description
Feature Data Address
Byte pointer to the Feature Data section
00h: Feature Data section not present
01h - 73h: Reserved
74h: Feature Data section pointer value
75h-FFh: Reserved
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
95
Features
7.4.3.1.10
ODA: Other Data Address
This location provides the offset to the Other Data Section. Writes to this register have
no effect.
Offset:
0Ah
Bit
7:0
Description
Other Data Address
Byte pointer to the Other Data section
00h: Other Data section not present
01h - 7Dh: Reserved
7Eh: Other Data section pointer value
7Fh- FFh: Reserved
7.4.3.1.11
RES1: Reserved 1
This locations are reserved. Writes to this register have no effect.
Offset:
0Bh-0Ch
Bit
15:0
Description
RESERVED
0000h-FFFFh: Reserved
7.4.3.1.12
HCKS: Header Checksum
This location provides the checksum of the Header Section. Writes to this register have
no effect.
Offset:
0Dh
Bit
7:0
Description
Header Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.2
Processor Data
This section contains two pieces of data:
• The S-spec/QDF of the part in ASCII format
• (1) 2-bit field to declare if the part is a pre-production sample or a production unit
7.4.3.2.1
SQNUM: S-Spec QDF Number
This location provides the S-SPec or QDF number of the processor. The S-spec/QDF
field is six ASCII characters wide and is programmed with the same S-spec/QDF value
as marked on the processor. If the value is less than six characters in length, leading
spaces (20h) are programmed in this field. Writes to this register have no effect.
Example: A processor with a QDF mark of QEU5 contains the following in field 0E-13h:
20, 20, 51, 45, 55, 35h. This data consists of two blanks at 0Eh and 0Fh followed by
the ASCII codes for QEU5 in locations 10 - 13h.
96
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
Offset:
0Eh-13h
Bit
47:40
Description
Character 6
S-SPEC or QDF character or 20h
00h-0FFh: ASCII character
39:32
Character 5
S-SPEC or QDF character or 20h
00h-0FFh: ASCII character
31:24
Character 4
S-SPEC or QDF character
00h-0FFh: ASCII character
23:16
Character 3
S-SPEC or QDF character
00h-0FFh: ASCII character
15:8
Character 2
S-SPEC or QDF character
00h-0FFh: ASCII character
7:0
Character 1
S-SPEC or QDF character
00h-0FFh: ASCII character
7.4.3.2.2
SAMPROD: Sample/Production
This location contains the sample/production field, which is a two-bit field and is LSB
aligned. All Q-spec material will use a value of 00b. All S-spec material will use a value
of 01b. All other values are reserved. Writes to this register have no effect.
Example: A processor with a Qxxx mark (engineering sample) will have offset 14h set
to 00h. A processor with an Sxxxx mark (production unit) will use 01h at offset 14h.
Offset:
14h
Bit
7:2
Description
RESERVED
000000b-111111b: Reserved
1:0
Sample/Production
Sample or Production indictor
00b: Sample
01b: Production
10b-11b: Reserved
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
97
Features
7.4.3.2.3
PDCKS: Processor Data Checksum
This location provides the checksum of the Processor Data Section. Writes to this
register have no effect.
Offset:
15h
Bit
Description
7:0
Processor Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.3
Processor Core Data
This section contains core silicon-related data.
7.4.3.3.1
CPUID: CPUID
This location contains the CPUID, Processor Type, Family, Model and Stepping. The
CPUID field is a copy of the results in EAX[13:0] from Function 1 of the CPUID
instruction. The MSB is at location 16h, the LSB is at location 17h. Writes to this
register have no effect.
Example: If the CPUID of a processor is 0F68h, then the value programmed into offset
16 - 17h of the PIROM is 3DA0h.
Note:
The field is not aligned on a byte boundary since the first two bits of the offset are
reserved. Thus, the data must be shifted right by two in order to obtain the same
results.
Note:
The first two bits of the PIROM are reserved, as highlighted in the example below.
CPUID instruction results
0000
1111
0110
1000 (0F68h)
PIROM content
0011
1101
1010
0000 (3DA0h)
Offset:
16h-17h
Bit
15:14
Description
Processor Type
00b-11b: Processor Type
13:10
Processor Family
00h-0Fh: Processor Family
9:6
Processor Model
00h-0Fh: Processor Model
5:2
Processor Stepping
00h-0Fh: Processor Stepping
1:0
Reserved
00b-11b: Reserved
98
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.3.2
RES2: Reserved 2
These locations are reserved. Writes to this register have no effect.
Offset:
18h-19h
Bit
15:0
Description
RESERVED 2
0000h-FFFFh: Reserved
7.4.3.3.3
FSB: Front Side Bus Speed
This location contains the front side bus frequency information. Systems may need to
read this offset to decide if all installed processors support the same front side bus
speed. Because the Intel NetBurst microarchitecture bus is described as a 4X data bus,
the frequency given in this field is currently 667 MHz or 800 MHz. The data provided is
the speed, rounded to a whole number, and reflected in hex. Writes to this register
have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series supports a 667 or 800 MHz
front side bus. Therefore, offset 1A - 1Bh has a value of 029Bh or 0320h.
Offset:
1Ah-1Bh
Bit
15:0
Description
Front Side Bus Speed
0000h-029Ah: Reserved
029Bh: 667 MHz
029Ch-031Fh: Reserved
0320h: 800 Mhz
0321h-FFFFh: Reserved
7.4.3.3.4
MPSUP: Multiprocessor Support
This location contains 2 bits for representing the supported number of physical
processors on the bus. These two bits are MSB aligned where 00b equates to singleprocessor operation, 01b is a dual-processor operation, and 11b represents multiprocessor operation. The Dual-Core Intel Xeon processor 7100 series is an MP
processor. The remaining six bits in this field are reserved for the future use. Writes to
this register have no effect.
Example: An MP processor will use C0h at offset 1Ch.
Offset:
1Ch
Bit
7:6
Description
Multiprocessor Support
UP, DP or MP indictor
00b:
01b:
10b:
11b:
5:0
UP
DP
Reserved
MP
RESERVED
000000b-111111b: Reserved
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
99
Features
7.4.3.3.5
MCF: Maximum Core Frequency
This location contains the maximum core frequency for the processor. The frequency
should equate to the markings on the processor and/or the QDF/S-spec speed even if
the parts are not limited or locked to the intended speed. Format of this field is in MHz,
rounded to a whole number, and encoded in hex format. Writes to this register have no
effect.
Example: A 3.40 GHz processor will have a value of 0D48h, which equates to 3400
decimal. Therefore, offset 1D - 1Eh has a value of 0D48.
Offset:
1Dh-1Eh
Bit
15:0
Description
Maximum Core Frequency
0000h-09C3: Reserved
09C4h: 2.5 Ghz
09C5h-0A27h: Reserved
0A28h: 2.6 GHz
0A29h-0BB7h: Reserved
0BB8h: 3.0 GHz
0BB9h-0C5Eh: Reserved
0C5Fh: 3.167 GHz
0C60h-0C7Fh: Reserved
0C80h: 3.2 GHz
0C81h-0D5Eh: Reserved
0D05h: 3.333 GHz
0D06h-0D47h: Reserved
0D48h: 3.4 GHz
0D49h-FFFFh: Reserved
7.4.3.3.6
MAXVID: Maximum Core VID
This location contains the maximum Core VID (Voltage Identification) voltage that may
be requested via the VID pins. This field, rounded to the next thousandth, is in mV and
is reflected in hex. Writes to this register have no effect.
Example: From Table 2-10 the maximum VID is 1.3500 V maximum voltage. Offset 1F
- 20h would contain 0546h (1350 decimal).
Offset:
1Fh-20h
Bit
15:0
Description
Maximum Core VID
0000h-0545h: Reserved
0546h: 1.35 V
0548h-FFFFh: Reserved
7.4.3.3.7
MINV: Minimum Core Voltage
This location contains the minimum Processor Core voltage. This field, rounded to the
next thousandth, is in mV and is reflected in hex. The minimum VCC reflected in this
field is the minimum allowable voltage assuming the FMB maximum current draw.
Writes to this register have no effect.
Note:
100
The minimum core voltage value in offset 21 - 22h is a single value that assumes the
FMB maximum current draw. Refer to Table 2-10 and Table 2-11 for the minimum core
voltage specifications based on actual real-time current draw.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is
0.991 V = 1.100 V (Min VID) - 0.209 V (Voltage Offset at maximum current). Offset 21
- 22h would contain 03DFh (0991 decimal).
Offset:
21h-22h
Bit
15:0
Description
Minimum Core Voltage
0000h-03DEh: Reserved
03DF: 0.991 V
03E0h-FFFFh: Reserved
7.4.3.3.8
TCASE: TCASE Maximum
This location provides the maximum TCASE for the processor. The field reflects
temperature in degrees Celsius in hex format. This data can be found in the Table 6-1.
The thermal specifications are specified at the case Integrated Heat Spreader
(IHS).Writes to this register have no effect.
Offset:
23h
Bit
7:0
Description
TCASE Maximum
00h-FFh: Maximum Case Temperature of the processor
7.4.3.3.9
PCDCKS: Processor Core Data Checksum
This location provides the checksum of the Processor Core Data Section. Writes to this
register have no effect.
Offset:
24h
Bit
7:0
Description
Processor Core Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.4
Cache Data
This section contains cache-related data.
7.4.3.4.1
RES3: Reserved 3
These locations are reserved. Writes to this register have no effect.
Offset:
25h-26h
Bit
15:0
Description
RESERVED 3
0000h-FFFFh: Reserved
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
101
Features
7.4.3.4.2
L2SIZE: L2 Cache Size
This location contains the size of the level two cache in kilobytes. Writes to this register
have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series has a 2 MB (2048 KB) L2
cache total (1 MB L2 cache per core). Thus, offset 27 - 28h will contain 0800h.
Offset:
27h-28h
Bit
15:0
Description
L2 Cache Size
0000h-07FFh: Reserved
0800h: 2 MB
0801h-FFFFh: Reserved
7.4.3.4.3
L3SIZE: L3 Cache Size
This location contains the size of the level three cache in kilobytes. Writes to this
register have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series has either a 4 MB
(4096 KB), 8 MB (8192 KB) or 16 MB (16384 KB) L3 cache. Thus, offset 29 - 2Ah will
contain 1000h (for 4 MB), 2000h (for 8 MB) or 4000h (for 16 MB).
Offset:
29h-2Ah
Bit
15:0
Description
L3 Cache Size
0000h-0FFFh: Reserved
1000h: 4MB
1001h-1FFFh: Reserved
2000h: 8MB
2001h-3FFFh: Reserved
4000h: 16MB
4001h-FFFFh: Reserved
7.4.3.4.4
MAXCVID: Maximum Cache VID
This location contains the maximum Cache VID (Voltage Identification) voltage that
may be requested via the CVID pins. This field, rounded to the next thousandth, is in
mV and is reflected in hex. Writes to this register have no effect.
Example: From Table 2-10 the maximum CVID is 1.3500 V maximum voltage. Offset
2B - 2Ch would contain 0546h (1350 decimal).
Offset:
2Bh-2Ch
Bit
15:0
Description
Maximum Cache VID
0000h-0545h: Reserved
0546h: 1.35 V
0548h-FFFFh: Reserved
102
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.4.5
MINCV: Minimum Cache Voltage
This location contains the minimum Cache voltage. This field, rounded to the next
thousandth, is in mV and is reflected in hex. The minimum VCACHE reflected in this field
is the minimum allowable voltage assuming the FMB maximum current draw for two
processors. Writes to this register have no effect.
Note:
The minimum core voltage value in offset 2D - 2Eh is a single value that assumes the
FMB maximum current draw for two processors. Refer to Table 2-10 and Table 2-12 for
the minimum cache voltage specifications based on actual real-time current draw.
Example: For a Dual-Core Intel Xeon processor 7100 series the minimum voltage is
0.802 V = 1.100 V (Min CVID) - 0.298 V (Voltage Offset at maximum current). Offset
2D - 2Eh would contain 0322h (0802 decimal).
Offset:
2Dh-2Eh
Bit
15:0
Description
Minimum Cache Voltage
0000h-0321h: Reserved
0322: 0.802 V
0323h-FFFFh: Reserved
7.4.3.4.6
RES4: Reserved 4
These locations are reserved. Writes to this register have no effect.
Offset:
2Fh-30h
Bit
15:0
Description
RESERVED 4
0000h-FFFFh: Reserved
7.4.3.4.7
CDCKS: Cache Data Checksum
This location provides the checksum of the Cache Data Section. Writes to this register
have no effect.
Offset:
31h
Bit
7:0
Description
Cache Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.5
Package Data
This section provides package revision information.
7.4.3.5.1
PREV: Package Revision
This location tracks the highest level package revision. It is provided in ASCII format of
four characters (8 bits x 4 characters = 32 bits). The package is documented as 1.0,
2.0, etc. If this only consumes three ASCII characters, a leading space is provided in
the data field.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
103
Features
Example: The A-0 and A-1 steppings of the Dual-Core Intel Xeon processor 7100
series utilizes the first revision package (FC-mPGA4). Thus, at offset 32-35h, the data
is a space followed by 1.0. In hex, this would be 20, 31, 2E, 30. The B-0 stepping of the
Dual-Core Intel Xeon processor 7100 series utilizes the second revision package
(FC-mPGA6). Thus, at offset 32-35h, the data is a space followed by 2.0. In hex, this
would be 20, 32, 2E, 30.
Offset:
32h-35h
Bit
31:24
Description
Character 4
ASCII character or 20h
00h-0FFh: ASCII character
23:16
Character 3
ASCII character
00h-0FFh: ASCII character
15:8
Character 2
ASCII character
00h-0FFh: ASCII character
7:0
Character 1
ASCII character
00h-0FFh: ASCII character
7.4.3.5.2
RES5: Reserved 5
This location is reserved. Writes to this register have no effect.
Offset:
36h
Bit
7:0
Description
RESERVED 5
00h-FFh: Reserved
7.4.3.5.3
PKDCKS: Package Data Checksum
This location provides the checksum of the Package Data Section. Writes to this register
have no effect.
Offset:
37h
Bit
7:0
Description
Package Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.6
Part Number Data
This section provides traceability. There are 208 available bytes in this section for
future use.
104
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.6.1
PREV: Package Revision
This location contains seven ASCII characters reflecting the Intel part number for the
processor. This information is typically marked on the outside of the processor. If the
part number is less than 7 characters, a leading space is inserted into the value. The
part number should match the information found in the marking specification found in
Section 3. Writes to this register have no effect.
Example: A processor with a part number of 80546KF will have data found at offset 38
- 3Eh is 38, 30, 35, 34, 36, 4B, 46.
Offset:
38h-3Eh
Bit
4F:48
Description
Character 7
ASCII character or 20h
00h-0FFh: ASCII character
47:40
Character 6
ASCII character or 20h
00h-0FFh: ASCII character
39:32
Character 5
ASCII character or 20h
00h-0FFh: ASCII character
31:24
Character 4
ASCII character
00h-0FFh: ASCII character
23:16
Character 3
ASCII character
00h-0FFh: ASCII character
15:8
Character 2
ASCII character
00h-0FFh: ASCII character
7:0
Character 1
ASCII character
00h-0FFh: ASCII character
7.4.3.6.2
RES6: Reserved 6
This location is reserved. Writes to this register have no effect.
Offset:
3Fh-4Ch
Bit
111:0
Description
RESERVED 6
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
105
Features
7.4.3.6.3
PSERSIG: Processor Serial/Electronic Signature
This location contains a 64-bit identification number. The value in this field is either a
serial signature or an electronic signature. Bits 5 & 6 of the Processor Feature Flags
(Offset 78h) indicates which signature is present. Intel does not guarantee that each
processor will have a unique value in this field. Writes to this register have no effect.
Offset:
4Dh=54h
Bit
63:0
Description
Processor Serial/Electronic Signature
00000000h-FFFFFFFFh: Electronic Signature
7.4.3.6.4
RES7: Reserved 7
This location is reserved. Writes to this register have no effect.
Offset:
55h-6Eh
Bit
207:0
7.4.3.6.5
Description
RESERVED 7
PNDCKS: Part Number Data Checksum
This location provides the checksum of the Part Number Data Section. Writes to this
register have no effect.
Offset:
6F
Bit
7:0
Description
Part Number Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.7
Thermal Reference Data
This section is reserved for future use.
7.4.3.7.1
RES8: Reserved 8
This location is reserved. Writes to this register have no effect.
Offset:
70h
Bit
7:0
106
Description
RESERVED 8
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.7.2
RES9: Reserved 9
This location is reserved. Writes to this register have no effect.
Offset:
71h-72h
Bit
15:0
7.4.3.7.3
Description
RESERVED 9
TRDCKS: Thermal Reference Data Checksum
This location provides the checksum of the Thermal Reference Data Section. Writes to
this register have no effect.
Offset:
73h
Bit
7:0
Description
Thermal Reference Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.3.8
Feature Data
This section provides information on key features that the platform may need to
understand without powering on the processor.
7.4.3.8.1
PCFF: Processor Core Feature Flags
This location contains a copy of results in EDX[31:0] from Function 1 of the CPUID
instruction. These details provide instruction and feature support by product family. A
decode of these bits is found in the Cedar Mill Processor Family BIOS Writers Guide or
the AP-485 Intel® Processor Identification and CPUID Instruction application note.
Writes to this register have no effect.
Offset:
74h-77h
Bit
31:0
Description
Processor Core Feature Flags
0000h-FFFFF: Feature Flags
7.4.3.8.2
PFF: Processor Feature Flags
This location contains additional feature information from the processor. Writes to this
register have no effect.
Note:
Bit 5 and Bit 6 are mutually exclusive (only one bit will be set).
Offset:
78h
Bit
Description
7
Multi-Core (set if the processor is a dual core processor)
6
Serial signature (set if there is a serial signature at offset 4D - 54h)
5
Electronic signature present (set if there is a electronic signature at 4D - 54h)
4
Thermal Sense Device present (set if an SMBus thermal sensor on package)
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
107
Features
Offset:
78h
Bit
7.4.3.8.3
Description
3
Reserved
2
OEM EEPROM present (set if there is a scratch ROM at offset 80 - FFh)
1
Core VID present (set if there is a VID provided by the processor)
0
L3 Cache present (set if there is a level 3 cache on the processor)
PTCI: Processor Thread and Core Information
This location contains information regarding the number of cores and threads on the
processor. Writes to this register have no effect.
Example: The Dual-Core Intel Xeon processor 7100 series has two cores and two
threads per core. Therefore, this register will have a value of 0Ah.
Offset:
79h
Bit
7.4.3.8.4
Description
7:4
Reserved
3:2
Number of cores
1:0
Number of threads per core
APFF: Additional Processor Feature Flags
This location contains additional feature information for the processor. This field is
defined as follows: Writes to this register have no effect.
Offset:
7Ah
Bit
Description
7
Reserved
6
Intel® Cache Safe Technology
5
C1E State
4
Intel® Virtualization Technology
3
Execute Disable
2
Intel® 64
1
Thermal Monitor 2
0
Enhanced Intel Speed Step® Technology
Bits are set when a feature is present, and cleared when they are not.
108
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.3.8.5
TAF: Thermal Adjustment Factors
This location contains information on thermal adjustment factors for the processor. This
field and it’s details are pending and will be updated in a future revision. Writes to this
register have no effect.
Offset:
7Bh-7Ch
Bit
15:8
7:0
Description
Measurement Correction Factor
Temperature Target
7.4.3.9
Other Data
7.4.3.9.1
RES10: Reserved 10
These locations are reserved. Writes to this register have no effect.
Offset:
7Dh-7Eh
Bit
15:0
7.4.3.9.2
Description
RESERVED
FDCKS: Feature Data Checksum
This location provides the checksum of the Feature Data Section. Writes to this register
have no effect.
Offset:
7Fh
Bit
7:0
Description
Feature Data Checksum
One Byte Checksum of the Header Section
00h- FFh: See Section 7.4.4 for calculation of the value
7.4.4
Checksums
The PIROM includes multiple checksums. Table 7-7 includes the checksum values for
each section defined in the 128 byte ROM.
Table 7-7.
128 Byte ROM Checksum Values
Section
Checksum Address
Header
0Dh
Processor Data
15h
Processor Core Data
24h
Cache Data
31h
Package Data
37h
Part Number Data
6Fh
Thermal Ref. Data
73h
Feature Data
7Fh
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
109
Features
Checksums are automatically calculated and programmed by Intel. The first step in
calculating the checksum is to add each byte from the field to the next subsequent
byte. This result is then negated to provide the checksum.
Example: For a byte string of AA445Ch, the resulting checksum will be B6h.
AA = 10101010
44 = 01000100
5C = 0101100
AA + 44 + 5C = 01001010
Negate the sum: 10110101 +1 = 101101 (B6h)
7.4.5
Scratch EEPROM
Also available in the memory component on the processor SMBus is an EEPROM which
may be used for other data at the system or processor vendor’s discretion. The data in
this EEPROM, once programmed, can be write-protected by asserting the active-high
SM_WP signal. This signal has a weak pull-down (10 kΩ) to allow the EEPROM to be
programmed in systems with no implementation of this signal. The Scratch EEPROM
resides in the upper half of the memory component (addresses 80 - FFh). The lower
half comprises the Processor Information ROM (addresses 00 - 7Fh), which is
permanently write-protected by Intel.
7.4.6
SMBus Thermal Sensor
The processor’s SMBus thermal sensor provides a means of acquiring thermal data
from the processor’s two thermal diodes. The thermal sensor is composed of control
logic, SMBus interface logic, a precision analog-to-digital converter, and a single bank
of precision current sources. The A/D converter and the current source are muxed
between the two sensor channels. The sensor drives a small current through the p-n
junction for the thermal diodes located on the processor core. The forward bias voltage
generated across each thermal diode is sensed and the precision A/D converter derives
a byte of thermal reference data, or a “thermal byte reading.” The resolution of the
least significant bit of a thermal byte is 1° Celsius.
The processor incorporates the SMBus thermal sensor onto the processor package.
Upper and lower thermal reference thresholds can be individually programmed for each
channel of the SMBus thermal sensor. Comparator circuits sample the register where
the single byte of thermal data (thermal byte reading) is stored. These circuits compare
the single-byte result against programmable threshold bytes. If enabled, the alert
signal on the processor SMBus (SM_ALERT#) will be asserted when the sensor detects
that either the high or low threshold is reached or crossed for each channel. Analysis of
SMBus thermal sensor data may be useful in detecting changes in the system
environment that may require attention.
The processor SMBus thermal sensor may be used to monitor long term temperature
trends, but can not be used to manage the short term temperature of the processor or
predict the activation of the thermal control circuit. As mentioned earlier, the
processor’s high thermal ramp rates make this infeasible. Refer to the thermal design
guidelines listed in Section 1.2 for more details.
The SMBus thermal sensor feature in the processor cannot be used to measure TCASE.
The TCASE specification in Section 6 must be met regardless of the reading of the
processor's thermal sensor in order to ensure adequate cooling for the entire processor.
The SMBus thermal sensor feature is only available while VCC and SM_VCC are at valid
levels and the processor is not in a low-power state.
110
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
7.4.7
Thermal Sensor Supported SMBus Transactions
The thermal sensor responds to five of the SMBus packet types: Write Byte, Read Byte,
Send Byte, Receive Byte, and Alert Response Address (ARA). The Send Byte packet can
be used for sending one-shot commands. The Receive Byte packet accesses the
register commanded by the last Read Byte packet and can be used to continuously read
from a register. If a Receive Byte packet was preceded by a Write Byte or send Byte
packet more recently than a Read Byte packet, then the behavior is undefined.
Table 7-8 through Table 7-12 diagram the five packet types. In these figures, ‘S’
represents the SMBus start bit, ‘P’ represents a stop bit, ‘Ack’ represents an
acknowledge, and ‘///’ represents a negative acknowledge (NACK). The shaded bits are
transmitted by the thermal sensor, and the bits that aren’t shaded are transmitted by
the SMBus host controller.
Table 7-8.
Table 7-9.
Write Byte SMBus Packet
S
Slave Address
Write
Ack
Command Code
Ack
Data
Ack
P
1
7-bits
0
1
8-bits
1
8-bits
1
1
Read Byte SMBus Packet
S
Slave
Address
Write
Ack
Command
Code
Ack
S
Slave
Address
Read
Ack
Data
1
7-bits
0
1
8-bits
1
1
7-bits
1
1
8bits
/
/
/
P
1
1
Table 7-10. Send Byte SMBus Packet
S
Slave Address
Write
Ack
Command Code
Ack
P
1
7-bits
0
1
8-bits
1
1
Table 7-11. Receive Byte SMBus Packet
S
Slave Address
Read
Ack
Data
///
P
1
7-bits
1
1
8-bits
1
1
Read
Ack
Address
///
P
1
1
Table 7-12. ARA SMBus Packet
S
1
ARA
0001 100
1
1
Device
Address1
Note:
1.
This is an 8-bit field. The device which sent the alert will respond to the ARA Packet with its address in the
seven most significant bits. The least significant bit is undefined and may return as a ‘1’ or ‘0’. See
Section 7.4.1 for details on the Thermal Sensor Device addressing.
2.
The shaded bits are transmitted by the thermal sensor, and the bits that aren’t shaded are transmitted by
the SMBus host controller.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
111
Features
Table 7-13. SMBus Thermal Sensor Command Byte Bit Assignments
Command
R/W
Lock4
RESERVED2
00h
N/A
N/A
RESERVED
Ch. 1 Temp. Value1
01h
R
N
0000 0000
Status Register 1
02h
R
N
Undefined
Configuration Register 1
03h
R
Y
0000 0000
Register
Conversion Rate Register
RESERVED2
Ch. 1 Temp. High
Limit1,4
Ch. 1 Temp. Low Limit1,4
Reset State
04h
R
Y
0000 0111
05h - 06h
N/A
N/A
RESERVED
07h
R
Y
0101 0101
08h
R
Y
0000 0000
Configuration Register
09h
W
Y
0000 0000
Conversion Rate Register
0Ah
W
Y
0000 0111
RESERVED2
0Bh - 0Ch
N/A
N/A
RESERVED
Ch. 1 Temp. High Limit1,4
0Dh
W
Y
0101 0101
Ch. 1 Temp. Low Limit1,4
0Eh
W
Y
0000 0000
One-shot
0Fh
W
N/A
N/A
10h
N/A
N/A
RESERVED
11h
R/W
Y
0000 0000
12h - 22h
N/A
N/A
RESERVED
23h
R
N
0000 0000
RESERVED
2
Ch. 1 Temp. Offset1
RESERVED2
Status Register 2
RESERVED2
24h - 29h
N/A
N/A
RESERVED
Ch. 2 Temp. Value
30h
R
N
0000 0000
Ch. 2 Temp. High Limit4
31h
R/W
Y
0101 0101
Ch. 2 Temp. Low Limit4
32h
R/W
Y
0000 0000
2
33h
R
N/A
0000 0000
34h
R/W
Y
0000 0000
RESERVED
Ch. 2 Temp. Offset
RESERVED2
35h - FDh
N/A
N/A
RESERVED
Manufacturer ID
FEh
R
N/A
0100 0001
Die Revision Code3
FFh
R
N/A
1001xxxx
Notes:
1.
Bit 3 of Configuration register 1 must be set to 0 (default value is 0).
2.
Writing to RESERVED bits may cause unexpected results. RESERVED bits that must be correctly
programmed are identified in the register definitions in the following section. Reading from RESERVED bits
will return unknown values.
3.
The 4 least significant bits of the thermal sensor die revision code may change and should not be used for
identification.
All of the commands in Table 7-13 are for reading or writing registers in the SMBus
thermal sensor, except the one-shot register (0Fh). The one-shot command forces the
immediate start of a new conversion cycle. If a conversion is in progress when the oneshot command is received, then the command is ignored. If the thermal sensor is in
stand-by mode when the one-shot command is received, a conversion is performed
and the sensor returns to stand-by mode. The one-shot command is not supported
when the thermal sensor is in auto-convert mode.
Note:
112
Writing to a read-command register or reading from a write-command register will
produce invalid results.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
The default command after reset is to a reserved value (00h). After reset, Receive Byte
SMBus packets will return invalid data until another command is sent to the thermal
sensor.
7.4.8
SMBus Thermal Sensor Registers
7.4.8.1
Thermal Value Registers
Once the SMBus thermal sensor reads a processor thermal diode, it performs an analog
to digital conversion and stores the data in a temperature value register. The supported
range is +127 to 0 decimal and is expressed as an eight-bit number representing
temperature in degrees Celsius. This eight-bit value consists of seven bits of data and a
sign bit (MSB) where the sign is always positive (sign = 0) and is shown in Table 7-14.
The values shown are also used to program the Thermal Limit Registers.
The values of these registers should be treated as saturating values. Values above 127
are represented at 127 decimal, and values of zero and below may be represented as 0
to -127 decimal. If the device returns a value where the sign bit is set (1) and the data
is 000_0000 through 111_1110, the temperature should be interpreted as 0° Celsius.
Table 7-14. Thermal Value Register Encoding
7.4.8.2
Temperature
(°C)
Register Value
(binary)
+127
0 111 1111
+126
0 111 1110
+100
0 110 0100
+50
0 011 0010
+25
0 001 1001
+1
0 000 0001
0
0 000 0000
Thermal Limit Registers
The SMBus thermal sensor has high and low Thermal Limit Registers for each channel.
These registers allow the user to define high and low limits for the processor core
thermal diode readings. The encoding for these registers is the same as for the thermal
reference registers shown in Table 7-14. If either processor thermal diode reading
equals or exceeds one of these limits, then the alarm bit (R1HIGH, R1LOW, R2HIGH, or
R2LOW) in the Thermal Sensor Status Register is triggered.
7.4.8.3
Status Registers
The Status Registers shown in Table 7-15 and Table 7-16 indicates which, if any,
thermal value thresholds for the processor core thermal diode have been exceeded. It
also indicates whether a conversion is in progress or an open circuit has been detected
in either processor core thermal diode connection. Once set, alarm bits stay set until
they are cleared by a Status Register read. A successful read to the Status Register will
clear any alarm bits that may have been set (unless the alarm condition persists). If
the SM_ALERT# signal is enabled via the Thermal Sensor Configuration Register and a
thermal diode threshold is exceeded, an alert will be sent to the platform via the
SM_ALERT# signal.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
113
Features
Table 7-15. SMBus Thermal Sensor Status Register 1
Bit
Name
Reset State
Function
7 (MSB)
BUSY
N/A
6
RESERVED
RESERVED
Reserved for future use.
5
RESERVED
RESERVED
Reserved for future use.
4
R1HIGH
0
If set, indicates the processor core 1 thermal diode high
temperature alarm has activated.
3
R1LOW
0
If set, indicates the processor core 1 thermal diode low
temperature alarm has activated.
2
R1OPEN
0
If set, indicates an open fault in the connection to the
processor core 1 diode.
1
RESERVED
RESERVED
Reserved for future use.
0 (LSB)
RESERVED
RESERVED
Reserved for future use.
If set, indicates that the device’s analog to digital
converter is busy.
Table 7-16. SMBus Thermal Sensor Status Register 2
Bit
7.4.8.4
Name
Reset State
Function
7 (MSB)
RESERVED
RESERVED
Reserved for future use.
6
RESERVED
RESERVED
Reserved for future use.
5
RESERVED
RESERVED
Reserved for future use.
4
R2HIGH
0
If set, indicates the processor core 2 thermal diode high
temperature alarm has activated.
3
R2LOW
0
If set, indicates the processor core 2 thermal diode low
temperature alarm has activated.
2
R2OPEN
0
If set, indicates an open fault in the connection to the
processor core 2 diode.
1
RESERVED
RESERVED
0 (LSB)
ALERT
0
Reserved for future use.
If set, indicates the ALERT pin has been asserted low.
This bit gets reset when the ALERT output gets reset.
Configuration Register
The Configuration Register controls several functions of the temperature sensor such as
ALERT# masking, stand-by mode, and others. Table 7-17 and Table 7-18 shows the bit
definitions of the Configuration Registers.
Table 7-17. SMBus Thermal Sensor Configuration Register (Sheet 1 of 2)
114
Bit
Name
Reset State
Function
7 (MSB)
MASK
0
Mask SM_ALERT# bit. Clear the bit to allow interrupts
via SM_ALERT# and allow the thermal sensor to
respond to the ARA command when an alarm is active.
Set the bit to disable interrupt mode. The bit is not used
to clear the state of the SM_ALERT# output. An ARA
command may not be recognized if the mask is enabled.
6
RUN/STOP
0
Stand-by mode control bit. If set, the device
immediately stops converting and enters stand-by
mode. It will perform new temperature measurements
when a one-shot is performed. If cleared, the device
automatically updates on a timed basis.
5
AL/TH
0
This bit selects the function of pin 13. Default = 0 =
ALERT. Always set this bit to 0.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Features
Table 7-17. SMBus Thermal Sensor Configuration Register (Sheet 2 of 2)
Bit
7.4.8.5
Name
Reset State
Function
4
RESERVED
RESERVED
3
Remote 1/2
0
Setting this bit to 1 enables the user to read the
processor core 2 values from the processor core 1
registers. Default = 0 means Read processor core 1
values from the processor core 1 registers. Always set
this bit to 0.
2
Temp Range
0
Setting this bit to 1 enables the extended temperature
measurement range (-50 °C to +150 °C). Default = 0 =
(0 °C to 127 °C). Always set this bit to 0.
1
Mask R1
0
Setting this bit to 1 masks ALERTS due to the processor
core 1 temperature exceeding a programmed limit.
Default = 0. Always set this bit to 0.
0
Mask R2
0
Setting this bit to 1 masks ALERTS due to the processor
core 2 temperature exceeding a programmed limit.
Default = 0. Always set this bit to 0.
Reserved for future use.
Conversion Rate Register
The contents of the Conversion Rate Registers determine the nominal rate at which
analog-to-digital conversions happen when the SMBus thermal sensor is in autoconvert mode. There are two Conversion Rate Registers: address 04h for reading the
conversion rate value; and address 0Ah for writing the value. Table 7-18 shows the
mapping between Conversion Rate Register values and the conversion rate. As
indicated in Table 7-13, the Conversion Rate Register is set to its default state of 1000b
(16 Hz nominally) when the thermal sensor is powered up. There is a ±30% error
tolerance between the conversion rate indicated in the conversion rate register and the
actual conversion rate.
Table 7-18. SMBus Thermal Sensor Conversion Rate Register
Bit
Name
Reset State
7 (MSB)
Averaging
0
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Function
Setting this bit to 1 disables averaging of the
temperature measurements at the slower conversion
rates. Default = 0 = Averaging enabled.
115
Features
Table 7-18. SMBus Thermal Sensor Conversion Rate Register
Bit
7.4.9
Name
Reset State
6
RESERVED
RESERVED
5:4
Channel Selector
00
3:0
Conversion Rates
1000
Function
Reserved for future use.
These bits are used to select the temperature
measurement channels.
00 = Round robin
01 = Local Temperature
10 = Processor Core 1 Temperature
11 = Processor Core 2 Temperature
Default = 00. Always set these bits to 00
These bits determine how often the temperature sensor
measures each temperature channel.
Bit encoding = Conversions / sec
0000 = 0.0625
0001 = 0.125
0010 = 0.25
0011 = 0.5
0100 = 1
0101 = 2
0110 = 4
0111 = 8
1000 = 16 = default
1001 = 32
1010 = Continuous Measurements
SMBus Thermal Sensor Alert Interrupt
The SMBus thermal sensor located on the processor includes the ability to interrupt the
SMBus when a fault condition exists. The fault conditions consist of:
1. a processor thermal diode value measurement that exceeds a user-defined high or
low threshold programmed into the Command Register; or
2. disconnection of the processor thermal diode from the thermal sensor.
The interrupt can be enabled and disabled via the thermal sensor Configuration
Register and is delivered to the system board via the SM_ALERT# open drain output.
Once latched, the SM_ALERT# should only be cleared by reading the Alert Response
byte from the Alert Response Address of the thermal sensor. The Alert Response
Address is a special slave address shown in Table 7-12. The SM_ALERT# will be cleared
once the SMBus master device reads the slave ARA unless the fault condition persists.
Reading the Status Register or setting the mask bit within the Configuration Register
does not clear the interrupt.
§
116
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Boxed Processor Specifications
8
Boxed Processor Specifications
8.1
Introduction
Intel boxed processors are intended for system integrators who build systems from
components available through distribution channels. Future revisions may have
solutions that differ from those discussed here.
The thermal solution for the boxed Dual-Core Intel Xeon processor 7100 series, for
each processor frequency, includes an unattached passive heatsink. This solution is
targeted at chassis which are 3U and above in height.
This section documents baseboard and platform requirements for the thermal solution,
supplied with the boxed Dual-Core Intel Xeon processor 7100 series. This section is
particularly important to companies that design and manufacture baseboards, chassis
and complete systems. Figure 8-1 shows the conceptual drawing of the boxed
processor thermal solution.
Drawings in this section reflect only the specifications on the Intel boxed processor
product. These dimensions should not be used as a generic keep-out zone for all
cooling solutions. It is the system designer’s responsibility to consider their proprietary
cooling solution when designing to the required keep-out zone on their system platform
and chassis.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
117
Boxed Processor Specifications
Figure 8-1.
Passive Dual-Core Intel® Xeon® Processor 7100 Series
Thermal Solution (3U and larger)
Note:
1.
The heatsink in this image is for reference only.
2.
This drawing shows the retention scheme for the boxed processor.
8.2
Mechanical Specifications
This section documents the mechanical specifications of the boxed processor passive
heatsink.
8.2.1
Boxed Processor Heatsink Dimensions
The boxed processor is shipped with an unattached passive heatsink. Clearance is
required around the heatsink to ensure unimpeded airflow for proper cooling. The
physical space requirements and dimensions for the boxed processor and assembled
heatsink are shown in the following figures.
118
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Boxed Processor Specifications
Figure 8-2.
Top Side Board Keep-Out Zones (Part 1)
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
119
Boxed Processor Specifications
Figure 8-3.
120
Top Side Board Keep-Out Zones (Part 2)
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Boxed Processor Specifications
Figure 8-4.
Bottom Side Board Keep-Out Zones
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
121
Boxed Processor Specifications
Figure 8-5.
122
Board Mounting-Hole Keep-Out Zones
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Boxed Processor Specifications
Figure 8-6.
Thermal Solution Volumetric
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
123
Boxed Processor Specifications
Figure 8-7.
124
Recommended Processor Layout and Pitch
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Boxed Processor Specifications
8.2.2
Boxed Processor Heatsink Weight
The boxed processor heatsink weight is approximately 530 grams. See Section 3 of this
document for details on the processor weight and the Dual-Core Intel® Xeon®
Processor 7100 Series Thermal/Mechanical Design Guidelines for the enabled heatsink
requirements.
8.2.3
Boxed Processor Retention Mechanism and Heatsink
Supports
Baseboards and chassis’s designed for use by system integrators should include holes
that are in proper alignment with each other to support the boxed processor. See
Figure 8-7 for example of processor pitch and layout.
Figure 8-1 illustrates the retention solution. This is designed to extend air-cooling
capability through the use of larger heatsinks with minimal airflow blockage and
minimal bypass. These retention mechanisms can allow the use of much heavier
heatsink masses compared to legacy solution limitations by using a load path attached
to the chassis pan. The CEK spring on the under side of the baseboard provides the
necessary compressive load for the thermal interface material. The baseboard is
intended to be isolated such that the dynamic loads from the heatsink are transferred
to the chassis pan via the heatsink screws and heatsink standoffs. This reduces the risk
of package pullout and solder joint failures in a shock and vibe situation.
The assembly requires larger diameter holes to compensate for the CEK spring
embosses. See Figure 8-2 and Figure 8-3 for processor mounting thru holes. For
further details on the solution, refer to the Dual-Core Intel® Xeon® Processor 7100
Series Thermal/Mechanical Design Guidelines.
8.3
Thermal Specifications
This section describes the cooling requirements of the heatsink solution utilized by the
boxed processor.
8.3.1
Boxed Processor Cooling Requirements
The boxed processor will be cooled by forcing ducted chassis fan airflow through the
passive heat sink solution. Meeting the processor’s temperature specifications is a
function of the thermal design of the entire system, and ultimately the responsibility of
the system integrator. The processor temperature specification is found in Section 6 of
this document. For the boxed processor passive heatsink to operate properly, chassis
air movement devices are required. Necessary airflow and associated flow impedance is
29 cfm at 0.14” H2O.
In addition, the processor pitch should be 3.25 inches, or slightly more, when placed in
side by side orientation. Figure 8-7 illustrates the side by side orientation and pitch.
Note that the heatsinks are interleaved to reduce air bypass.
It is also recommended that the ambient air temperature outside of the chassis be kept
at or below 35 °C. The air passing directly over the processor heatsink should not be
preheated by other system components (such as another processor), and should be
kept at or below 40 °C. Again, meeting the processor’s temperature specification is the
responsibility of the system integrator.
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
125
Boxed Processor Specifications
8.3.2
Boxed Processor Contents
The boxed processor will include the following items:
• Dual-Core Intel Xeon processor 7100 series
• Unattached Passive Heatsink with captive screws
• Thermal Interface Material (pre-attached)
• Warranty / Installation manual with Intel Inside logo
The other items listed in Figure 8-1, required with this thermal solution should be
shipped with either the chassis or the mainboard. They include:
• CEK Spring (typically included with mainboard)
• Chassis Standoffs
• System fans
§
126
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
Debug Tools Specifications
9
Debug Tools Specifications
Please refer to the eXtended Debug Port: Debug Port Design Guide for MP Platforms,
and the appropriate platform design guide for more detailed information regarding
debug tools specifications.
9.1
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces
(LAIs) for use in debugging Dual-Core Intel® Xeon® Processor 7100 Series processor
systems. Tektronix and Agilent should be contacted to get specific information about
their logic analyzer interfaces. The following information is general in nature. Specific
information must be obtained from the logic analyzer vendor.
Due to the complexity of Dual-Core Intel® Xeon® Processor 7100 Series processorbased multiprocessor systems, the LAI is critical in providing the ability to probe and
capture front side bus signals. There are two sets of considerations to keep in mind
when designing a Dual-Core Intel® Xeon® Processor 7100 Series processor-based
system that can make use of an LAI: mechanical and electrical.
9.1.1
Mechanical Considerations
The LAI is installed between the processor socket and the processor. The LAI pins plug
into the socket, while the processor pins plug into a socket on the LAI. Cabling that is
part of the LAI egresses the system to allow an electrical connection between the
processor and a logic analyzer. The maximum volume occupied by the LAI, known as
the keepout volume, as well as the cable egress restrictions, should be obtained from
the logic analyzer vendor. System designers must make sure that the keepout volume
remains unobstructed inside the system. Note that it is possible that the keepout
volume reserved for the LAI may differ from the space normally occupied by the DualCore Intel® Xeon® Processor 7100 Series processor heatsink. If this is the case, the
logic analyzer vendor will provide a cooling solution as part of the LAI.
9.1.2
Electrical Considerations
The LAI will also affect the electrical performance of the front side bus; therefore, it is
critical to obtain electrical load models from each of the logic analyzer vendors to be
able to run system level simulations to prove that their tool will work in the system.
Contact the logic analyzer vendor for electrical specifications and load models for the
LAI solution they provide.
§
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet
127
Debug Tools Specifications
128
Dual-Core Intel® Xeon® Processor 7100 Series Datasheet