Audio Modulated Matrix LED Driver - SI-EN

SN3728
Audio Modulated Matrix LED Driver
General Description
Features
SN3728 is a general purpose 8×8 LED matrix driver
which features an audio frequency equalizer (EQ) mode
or a general LED dot matrix display mode. The general
LED matrix display defaults to an 8×8 configuration,
however, it can be configured for a 5×11, 6×10, 7×9 dot
matrix display. The matrix picture brightness can be
modulated by audio. In either the audio EQ mode or
matrix display mode, the array is internally scanned, and
requires only one-time programming, thus eliminating
the need for real time system resource utilization.
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It programs the LED array through I2C interface. In the
general purpose display mode, each dot of the LED array
is independently programmed on or off over time. In the
audio EQ mode, the X axis (column) represents the
frequency bands while the Y axis (row) represents the
strength of the input audio signal in each band. The
number of LEDs lit in a column is proportional to the
strength of the audio signal in the corresponding band in
a thermometer-coded manner.
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SN3728 is available in QFN-24(4mm × 4mm). It
operates from 2.7V to 5.5V over the temperature range
of -40°C to +85°C.
5~8 current source outputs for row control
8~11 outputs for column scan control
Programmable 8×8, 7×9, 6×10, 5×11 matrix
One-time programming, internal scan
Full scale LED current controlled by internal
register setting or audio signal
Audio frequency EQ display with programmable
input gain
LED matrix brightness can be modulated with audio
Signal
One address pin with 4 logic levels to allow four
I2C slave addresses
I2C interface
2.7V to 5.5V supply
Over-temperature protection
QFN -24(4mm × 4mm) package
Applications
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Mobile phones and other hand-held devices for
LED displays.
Audio frequency equalizer display
Typical Application Circuit
Figure 1
Typical Application Circuit
Note: The IC should be placed far away from the mobile antenna in order to prevent the EMI.
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SI-EN Technology
SN3728
Pin Configuration
23 C2
22 C3
21 C4
20 GND
R3 9
R4 10
VCC 11
19 C5
24 C1
R2 8
Pin Configuration (Top View)
R1 7
Package
R5 12
QFN-24
Pin Description
No.
Pin
Description
1
SDA
Serial data.
2
SCL
Serial clock.
3
SDB
Shutdown the chip when pull to low.
4
IN
5
C_FILT
6
AD
7~10, 12
R1~R5
11
VCC
13~15
R6/C11, R7/C10, R8/C9
16~19, 21~24
C8~C1
20
GND
Audio input.
Low pass filter cap for audio control.
I2C Address setting.
Current source outputs.
Power supply.
CMOS outputs.
Current sink outputs.
Ground.
Thermal Pad
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Connect to GND.
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SI-EN Technology
SN3728
Ordering Information
Order Number
Package Type
QTY/Reel
Operating Temperature Range
SN3728I424E
QFN-24
2500
-40°C ~ +85°C
SN3728
□
□
□
□
Environmental Code
E: RoHS
Pin Code
24:24 Pins
Package Type
4: QFN, 4mm × 4mm
Temperature Code
I: Industrial, -40°C ~ +85°C
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SI-EN Technology
SN3728
Absolute Maximum Ratings
Supply voltage, VCC --------------------------------------------------------------------------------------------------- -0.3 V ~ +6.0V
Voltage at any input pin ------------------------------------------------------------------------------------------- -0.3V ~ VCC+0.3V
Maximum junction temperature, TJMAX ---------------------------------------------------------------------------------------- 150°C
Operating temperature range, TA ------------------------------------------------------------------------------------ -40°C ~ +85°C
Storage temperature range, TSTG ----------------------------------------------------------------------------------- –65°C ~ +150°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other condition beyond those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Electrical Characteristics
TA = -40°C ~ +85°C, VCC = 2.7V ~ 5.5V, unless otherwise noted. Typical value are TA = +25°C.
Symbol
Parameter
VCC
Supply voltage
ICC
Quiescent
current
ISD
Shutdown current
IOUT
VHR
power
Condition
Min.
Typ.
2.7
supply
Output current of R1~R8
Max.
Unit
5.5
V
VIN = 0V, register CD1:CD11 = 0
dot matrix display mode without
audio modulation
4.1
5.0
mA
VSDB = 0V
0.2
1.0
μA
VSDB = 5V, software shutdown
1.7
3.0
μA
Dot matrix display mode without
audio modulation
Dot matrix display mode with
audio modulation
VIN = 1.8Vp-p, 1kHz square wave,
audio gain = 0dB
42.8
mA
(Note 1)
42.3
mA
(Note 1)
Current sink (ISINK, C1:C8)
I
= 320mA (Note 2)
headroom voltage and current SINK
source (IOUT, R1:R8) headroom
IOUT = 40mA
voltage
300
mV
200
Logic Electrical Characteristics
VIL
Logic low input voltage
VCC = 2.7V
VIH
Logic high input voltage
VCC = 5.5V
IIL
Logic low input current
VINPUT = 0V
(Note 3)
IIH
Logic high input current
VINPUT = VCC
(Note 3)
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0.4
1.4
V
5
5
4
V
nA
nA
SI-EN Technology
SN3728
Digital Input Switching Characteristics (Note 3)
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
400
kHz
fSCL
Serial-Clock Frequency
tBUF
Bus Free Time Between a STOP and a
START Condition
1.3
μs
tHD, STA
Hold Time (Repeated) START Condition
0.6
μs
tSU, STA
Repeated START Condition Setup Time
0.6
μs
tSU, STO
STOP Condition Setup Time
0.6
μs
tHD, DAT
Data Hold Time
tSU, DAT
Data Setup Time
100
ns
tLOW
SCL Clock Low Period
1.3
μs
tHIGH
SCL Clock High Period
0.7
μs
0.9
μs
tR
Rise Time of Both SDA and SCL Signals,
Receiving
(Note 4)
20 + 0.1Cb
300
ns
tF
Fall Time of Both SDA and SCL Signals,
Receiving
(Note 4)
20 + 0.1Cb
300
ns
Note 1: Current of single LED in RX(x=1~8) is IOUT/8.
Note 2: All row drivers are on.
Note 3: Guaranteed by design.
Note 4: Cb = total capacitance of one bus line in pF. ISINK ≤ 6mA. tR and tF measured between 0.3 × VCC and 0.7 × VCC.
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SI-EN Technology
SN3728
Detailed Description
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
I2C Interface
The SN3728 uses a serial bus, which conforms to the I2C
protocol, to control the chip’s functions with two wires:
SCL and SDA. The SN3728 has a 7-bit slave address
(A6:A0). The bit A1 and bit A0 are decided by the
connection of AD pin.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL level
is high.
The complete slave address is:
After the last bit of the chip address is sent, the master
checks for the SN3728’s acknowledge. The master
releases the SDA line high (through a pull-up resistor).
Then the master sends an SCL pulse. If the SN3728 has
received the address correctly, then it holds the SDA line
low during the SCL pulse. If the SDA line is not low,
then the master should send a “STOP” signal (discussed
later) and abort the transfer.
Table1 Slave Address (Write only):
Bit
A7:A3
A2:A1
A0
Value
11000
AD
0
AD connected to GND, AD=00;
AD connected to VCC, AD=11;
AD connected to SCL, AD=01;
AD connected to SDA, AD=10;
Following acknowledge of SN3728, the register address
byte is sent, most significant bit first. SN3728 must
generate another acknowledge indicating that the
register address has been received.
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the slave
is the SN3728.
Then 8-bit of data byte are sent next, most significant bit
first. Each data bit should be valid while the SCL level is
stable high. After the data byte is sent, the SN3728 must
generate another acknowledge to indicate that the data
was received.
The timing diagram for the I2C is shown in Figure 2. The
SDA is latched in on the stable high level of the SCL.
When there is no interface activity, the SDA line should
be held high.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
Figure 2 Writing to SN3728
Figure 3 Interface Timing
Figure 4
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Bit Transfer
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SI-EN Technology
SN3728
Registers Definition
00h
0Ch Update Column Register
The data sent to the column data registers will be stored
in temporary registers. A write operation of any 8-bit
value to the Update Column Register is required to
update the Column Data Registers (01h: 0Bh).
Configuration Register
Bit
D7
D6:D3
D2
Name
SSD
-
Audio_EN
Default
0
0000
0
D1
D0
ADM
0
0
The Configuration Register sets operation mode of
SN3728.
SSD
0
1
0Dh
Software Shutdown Enable
Normal operation
Software shutdown mode
Array Mode Selection
8×8 Dot matrix display mode
7×9 Dot matrix display mode
6×10 Dot matrix display mode
5×11 Dot matrix display mode
01h~0Bh
Column Data Register (CD1~CD11)
Bit
D7:D0
Name
R8:R1
Default
00000000
The column data registers store the on or off state of each
LED in the array.
Rx
0
1
LED State
LED off
LED on
D7
D6:D4
D3:D0
Name
-
AGS
CS
Default
0
000
0000
AGS
000
001
010
011
100
101
110
111
Audio Input Gain Selection
0dB
+3dB
+6dB
+9dB
+12dB
+15dB
+18dB
-6dB
CS
0000
0001
... ...
0111
1000
1001
... ...
1110
Full Current Setting For Each Row Output
40mA
45mA
0Fh
The data in the column data registers is valid only when
the chip is configured in general purpose dot matrix
display mode. 11 registers are assigned to CD1~CD11
columns respectively; the LED at a particular (row,
column) location will be turned on when the respective
data is set to 1. When configured to other than 8×8 dot
matrix display mode operation, only the required number
of LSBs is used in each column register. For example,
in 5×11 dot matrix display mode, only bits R5 through
R1 are used, and bits R8 through R6 are ignored.
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Bit
The Lighting Effect Register stores the intensity control
settings for all of the LEDs in the array.
Audio_EN
Audio Input Enable
0
Matrix intensity is controlled by the current
setting in the Lighting Effect Register (0Dh)
1
Enable audio signal to modulate the intensity
of the matrix in dot matrix display mode
ADM
00
01
10
11
Lighting Effect Register
75mA
5mA
10mA
35mA
Audio_EQ Register
Bit
D7
D6
D5:D0
Name
-
AE_EN
-
Default
0
0
000000
The Audio_EQ Register enables the audio frequency
equalizer (audio EQ) mode.
AE_EN
0
1
7
Audio EQ Mode
Disable
Enable
SI-EN Technology
SN3728
Application Information
Audio Frequency Equalizer (Audio EQ) Mode
32us
The SN3728 features audio frequency equalizer mode, or
audio EQ mode.
Load Column data at each rising edge
1us
C1
C2
The current of the matrix is adjusted by Lighting Effect
Register as dot matrix display mode.
C3
In the audio EQ mode, only 8 columns are valid and
display the three bands of the audio signal. When the
SN3728 is configured as 7×9, 6×10 or 5×11, only
columns C1 thru C8 will be used, and the remaining
columns will always be off.
Cn
n=8~11
Row output
Column
data 1
Column
data 2
Column
data 3
Column
data n
Column
data 1
Figure 6 Dot Matrix Display Timing Diagram
8×8 Dot Matrix Display Mode
The application example in Figure 1 shows the SN3728
in the 8×8 LED dot matrix display mode.
Signal Strength
The LED columns have common cathodes and are
connected to the C1:C8 outputs. The rows are connected
to the row drivers. Each of the 64 LEDs can be
addressed separately. The columns are selected via the
registers 01h~08h as described in the registers definition
section.
5×11 Dot Matrix Display Mode
Figure 5
Audio EQ Mode
By setting D1&D0 of the Configuration Register to 11,
the SN3728 will operate in the 5×11 LED dot matrix
display mode.
General Purpose Dot Matrix Display Mode
The LED columns have common cathodes and are
connected to the C1:C11 outputs. The rows are
connected to the row drivers. Each of the 55 LEDs can
be addressed separately. The three MSBs of each register,
R8~R6, are ignored. The columns are selected via the
registers as described in the registers definition section.
The general purpose dot matrix display timing diagram is
shown in Figure 6. The SN3728 is configured as general
purpose 8×8 dot matrix display mode at initial power up.
Column controls C[8:1] scans the eight columns at a rate
of 3.79KHz, or 264µs per frame. Each column is
effective for 32us. The non-overlap interval between
adjacent columns is 1us.
Dot Matrix
Modulation
The SN3728 also can be configured as 7×9, 6×10 or
5×11 dot matrix display mode. The frame period is
changed slightly depending on the number of columns
required to scan by an additional time of 33us per column.
For example, when in 7×9 dot matrix display mode, the
column data registers’ MSB will be invalid and column
controls C[9:1] scans the nine columns 297us per frame.
Display
Mode
With
Audio
When the SN3728 operates in any of the Dot Matrix
modes, if the bit Audio_EN in Configuration register is
set to 1, the panel will get the effect of audio modulation
Initial Power-Up
On initial power-up, the SN3728 registers are reset to
their default values for a blank display. At this time, all
registers should be programmed for the desired
operation.
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SI-EN Technology
SN3728
Software Shutdown Mode
The SN3728 devices feature a software shutdown mode,
wherein they consume only 1.7μA (typ.) current.
Shutdown mode is entered via a write to the
Configuration Register. When the SN3728 is in shutdown
mode, all current sources and digital drivers are switched
off, so that the array is blanked.
Shutdown mode can either be used as a means of
reducing power consumption or generating a flashing
display (repeatedly entering and leaving shutdown
mode).
Note: During shutdown mode all registers retain their
data.
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SI-EN Technology
SN3728
Classification Reflow Profiles
Profile Feature
Pb-Free Assembly
Preheat & Soak
Temperature min (Tsmin)
Temperature max (Tsmax)
Time (Tsmin to Tsmax) (ts)
150°C
200°C
60-120 seconds
Average ramp-up rate (Tsmax to Tp)
3°C/second max.
Liquidous temperature (TL)
Time at liquidous (tL)
217°C
60-150 seconds
Peak package body temperature (Tp)*
Max 260°C
Time (tp)** within 5°C of the specified
classification temperature (Tc)
Max 30 seconds
Average ramp-down rate (Tp to Tsmax)
6°C/second max.
Time 25°C to peak temperature
8 minutes max.
Figure 7
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Classification Profile
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SN3728
Tape and Reel Information
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SI-EN Technology
SN3728
Package Information
QFN-24
Note: All dimensions in millimeters unless otherwise stated.
IMPORTANT NOTICE
SI-EN Technology cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a
SI-EN Technology product. SI-EN Technology reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its specifications, products and services at any time and to discontinue any
product or service without notice. Customers should obtain the latest relevant information before placing orders and
should verify that such information is current and complete.
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