SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK

DATASHEET
SERIAL PROGRAMMABLE QUAD PLL VERSACLOCK SYNTHESIZER
ICS308
Description
Features
The ICS308 is a versatile serially programmable, quad
PLL clock source. The ICS308 can generate any
frequency from 250 kHz to 200 MHz, and up to 6
different output frequencies simultaneously. The
outputs can be reprogrammed on the fly, and will lock to
a new frequency in 10 ms or less. Smooth transitions
(in which the clock duty cycle remains roughly 50%) are
guaranteed if the output divider is not changed.
• Packaged in 20-pin SSOP (QSOP) – Pb-free, RoHS
The device includes a PDTS pin which tri-states the
output clocks and powers down the entire chip.
• Eliminates need for custom quartz oscillators
• Input crystal frequency of 5 - 27 MHz
•Optional programmable on-chip crystal capacitors
• Output clock frequencies up to 200 MHz
• Reference clock output
• Power down tri-state mode
• Very low jitter
compliant
• Operating voltage of 3.3 V
• Highly accurate frequency generation
• M/N Multiplier PLL: M = 1..2048, N = 1..1024
• Serially programmable: user determines the output
frequency via a 3-wire interface
The ICS308 default for non-programmed start-up are
buffered reference clock outputs on all clock output
pins.
Block Diagram
V DD
3
CLK1
P LL1
CLK2
STROBE
SCLK
Divide
Logic
and
Output
Enable
Control
P LL2
DATA
P LL3
C rystal or
clock input
P LL4
X 1/IC LK
CLK3
CLK4
CLK5
CLK6
CLK7
CLK8
C rystal
O scillator
CLK9
X2
E xternal capacitors are
required w ith a crystal input.
GND
2
P D TS
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Pin Assignment
D AT A
1
20
ST R O BE
X2
2
19
SC LK
X1/IC LK
3
18
PD T S
C LK9
4
17
VD D
VDD
5
16
VD D
GND
6
15
GND
C LK1
7
14
C LK5
C LK2
8
13
C LK6
C LK3
9
12
C LK7
C LK4
10
11
C LK8
20 pin (150 m il) SSOP (QSOP)
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
DATA
Input
2
X2
XO
Crystal Output. Connect this pin to a crystal. Float for clock input.
3
X1/ICLK
XI
Connect this pin to a crystal or external clock input.
4
CLK9
Output
Output clock 9. Default of Reference frequency output when unprogrammed.
5
VDD
Power
Connect to +3.3 V.
6
GND
Power
Connect to Ground.
7
CLK1
Output
Output clock 1. Default of Reference frequency output when unprogrammed.
8
CLK2
Output
Output clock 2. Default of Reference frequency output when unprogrammed.
9
CLK3
Output
Output clock 3. Default of Reference frequency output when unprogrammed.
10
CLK4
Output
Output clock 4. Default of Reference frequency output when unprogrammed.
11
CLK8
Output
Output clock 8. Default of Reference frequency output when unprogrammed.
12
CLK7
Output
Output clock 7. Default of Reference frequency output when unprogrammed.
13
CLK6
Output
Output clock 6. Default of Reference frequency output when unprogrammed.
14
CLK5
Output
Output clock 5. Default of Reference frequency output when unprogrammed.
15
GND
Power
Connect to Ground.
16
VDD
Power
Connect to +3.3 V.
17
VDD
Power
Connect to +3.3 V.
18
PDTS
Input
Powers down entire chip, tri-states all outputs when low. Internal pull-up.
19
SCLK
Input
Serial Shift register clock. See timing diagram.
20
STROBE
Input
Strobe to load data. See timing diagram. Use external 250 kOhm pull-up.
Serial data input.
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Configuring the ICS308
Initial State: The ICS308 may be configured to have up to nine frequency outputs, utilizing the four
on-board PLLs. Unprogrammed, the part has the following outputs, related to the reference input clock:
Default Outputs
Output
Clock 1-9 (Pins 4, 10 - 14)
Frequency
Reference Output
The STROBE pin must have an external 250 kOhm pull-up resistor to achieve the Initial State.
The input crystal range for the ICS308 is 5 MHz to 27 MHz.
The ICS308 can be programmed to set the output functions and frequencies. 160 data bits generated by
the VersaClockTM software are written in DATA pin in this order: MSB (left most bit) first.
As show in Figure 2, after these 160 bits are clocked into the ICS308, taking STROBE high will send this
data to the internal hatch and the CLK output will lock within 10 ms.
Note: STROBE utilizes a transparent latch that is latched when in the high state. If STROBE is in the high
state and SCLK is pulsed, DATA is clocked directly to the internal latch and the output conditions will
change accordingly. Although this will not damage the ICS308, it is recommended that STROBE be kept
low while DATA is being clocked into the ICS308 in order to avoid unintended changes on the output clocks.
All outputs may be turned off during initialization by bringing the PDTS pin to Ground. When PDTS is
brought high, after the Strobe pin in brought high, the programmed output frequencies will be available.
AC Parameters for Writing to the ICS308
Parameter
Condition
Min.
tSETUP
Setup time
10
ns
tHOLD
Hold time after SCLK
10
ns
tW
Data wait time
10
ns
tS
Strobe pulse width
40
ns
SCLK Frequency
DATA
Bit160
t setup
Bit159
Bit158
Bit3
Bit2
Max.
30
Units
MHz
Bit1
t hold
SCLK
tw
ts
STROBE
Figure 2. Tim ing Diagram for Program m ing the ICS308
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External Components
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
STROBE Pull-up Resistor
In order for the device to start up in the default state, a
250 kOhm pull-up resistor is required.
Decoupling Capacitors
to the VDD pin as possible. No vias should be used
between decoupling capacitor and VDD pin. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to each clock output.
As with any high-performance mixed-signal IC, the
ICS308 must be isolated from system power supply
noise to perform optimally.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane.
ICS308 Configuration Capabilities
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors must
be connected from each of the pins X1 and X2 to
ground.
The value (in pF) of these crystal caps should equal (CL
-6 pF)*2. In this equation, CL= crystal load capacitance
in pF. Example: For a crystal with a 16 pF load
capacitance, each crystal capacitor would be 20 pF
[(16-6) x 2 = 20].
The architecture of the ICS308 allows the user to easily
configure the device to a wide range of output
frequencies, for a given input reference frequency.
The frequency multiplier PLL provides a high degree of
precision. The M/N values (the multiplier/divide values
available to generate the target VCO frequency) can be
set within the range of M = 1 to 2048 and N = 1 to 1024.
The ICS308 also provides separate output divide
values, from 2 through 20, to allow the two output clock
banks to support widely differing frequency values from
the same PLL.
Each output frequency can be represented as:
Output Freq. = (Ref. Freq)*(M/N)/Output Divide
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
1) Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
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VersaClock Software
IDT applies years of PLL optimization experience into a user friendly software that accepts the user’s target
reference clock and output frequencies and generates the lowest jitter, lowest power configuration, with
only a press of a button. The user does not need to have prior PLL experience or determine the optimal
VCO frequency to support multiple output frequencies.
VersaClock software quickly evaluates accessible VCO frequencies with available output divide values and
provides an easy to understand, bar code rating for the target output frequencies. The user may evaluate
output accuracy, performance trade-off scenarios in seconds.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS308. These ratings, which
are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Parameter
Item
Min.
Supply Voltage, VDD
Referenced to GND
Inputs
Referenced to GND
Clock Outputs
Referenced to GND
Storage Temperature
Soldering Temperature
Typ.
Max.
Units
7
V
-0.5
VDD+ 0.5
V
-0.5
VDD+ 0.5
V
-65
150
°C
260
°C
Max 10 seconds
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
Units
Ambient Operating Temperature (ICS308R)
0
+70
°C
Ambient Operating Temperature (ICS308RI)
-40
+85
°C
Power Supply Voltage (measured in respect to GND)
+3.0
+3.6
V
4
ms
Power Supply Ramp Time
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DC Electrical Characteristics
VDD=3.3 V ±10%, Ambient temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Operating Voltage
VDD
Operating Supply Current
Input High Voltage
IDD
Conditions
Typ.
3.00
Max.
Units
3.60
V
Configuration
Dependent
mA
Ex. 25 MHz crystal,
VDD=3.3 V, No load,
25
mA
PDTS = 0
20
µA
Input High Voltage
VIH
X1/ICLK only
Input Low Voltage
VIL
X1/ICLK only
Input High Voltage
VIH
Input Low Voltage
VIL
PDTS, SRCLOCK,
DATA, STROBE
Output High Voltage
VOH
IOH = -8 mA
Output Low Voltage
VOL
IOL = 8 mA
Output High Voltage,
CMOS level
VOH
IOH = -4 mA
Short Circuit Current
Min.
(VDD/2)+1
V
(VDD/2)-1
VDD-0.5
CLK outputs
V
V
0.8
2.4
V
V
0.4
VDD-0.4
V
V
+70
mA
4
pF
Input Capacitance
CIN
PDTS pin
Internal Pull-down
Resistor
RPD
CLK outputs
525
kΩ
Internal Pull-up Resistor
RPU
PDTS pin
250
kΩ
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AC Electrical Characteristics
VDD = 3.3 V±10%, Ambient Temperature -40 to +85° C, unless stated otherwise
Parameter
Symbol
Input Frequency
FIN
Conditions
Fundamental crystal
Input Clock
VDD=3.3 V
Output Frequency
Min.
Typ.
Max. Units
5
27
MHz
2
0.25
50
200
MHz
MHz
Output Clock Rise Time
tOR
20% to 80%, Note 1
0.8
ns
Output Clock Fall Time
tOF
80% to 20%, Note 1
0.8
ns
Output Clock Duty Cycle
Note 2
Power-up Time
40
49-51
60
%
STROBE goes high until
stable CLK out
3
10
ms
PDTS goes high until
stable CLK out
.2
2
ms
Maximum Output Jitter, short term
tj
Reference Clock
±300
ps
Maximum Output Jitter, short term
tj
All other clocks,
CL=15 pF, configuration
dependent
±200
ps
Pin-to-Pin Skew
Low Skew Outputs
-250
250
ps
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are min 45% / max 55%
Thermal Characteristics
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Symbol
Conditions
Min.
Typ.
Max. Units
θ JA
Still air
135
° C/W
θ JA
1 m/s air flow
93
° C/W
θ JA
3 m/s air flow
78
° C/W
60
° C/W
θ JC
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Package Outline and Package Dimensions (20-pin SSOP, 150 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
20
Symbol
E1
A
A1
A2
b
c
D
E
E1
e
L
α
aaa
E
INDEX
AREA
1 2
D
A
A2
Min
Inches*
Max
Min
1.35
1.75
0.10
0.25
-1.50
0.20
0.30
0.18
0.25
8.55
8.75
5.80
6.20
3.80
4.00
.635 Basic
0.40
1.27
0°
8°
-0.10
Max
0.053
0.069
0.004
0.010
-0.059
0.008
0.012
0.007
0.010
0.337
0.344
0.228
0.244
0.150
0.157
.025 Basic
0.016
0.050
0°
8°
-0.004
*For reference only. Controlling dimensions in mm.
A1
c
-Ce
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
308RLF
308RLFT
308RILF
308RILFT
308RLF
Tubes
Tape and Reel
Tubes
Tape and Reel
20-pin SSOP
20-pin SSOP
20-pin SSOP
20-pin SSOP
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
308RILF
“LF” suffix to the part number denotes Pb-Free configuration, RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result
from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any
circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or
critical medical instruments.
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