AK4112B - uri=media.digikey

ASAHI KASEI
[AK4112B]
AK4112B
High Feature 96kHz 24bit DIR
GENERAL DESCRIPTION
The AK4112B is a digital audio receiver (DIR) compatible with 96kHz, 24bits. The channel status
decoding supports both consumer and professional modes. The AK4112B can automatically detect a
Non-PCM bit stream. When combined with an AK4527B multi channel codec, the two chips provide a
system solution for AC-3 applications. The dedicated pins or a serial µP I/F can control the mode setting.
The small package, 28pin VSOP saves the board space.
*AC-3 is a trademark of Dolby Laboratories.
FEATURES
† Supports AES/EBU, IEC958, S/PDIF, EIAJ CP1201
† Low jitter Analog PLL
† PLL Lock Range: 22k~108kHz
† Clock Source: PLL or X'tal
† 4 channel Receivers input and 1 through transmission output
† Auxiliary digital input
† De-emphasis for 32kHz, 44.1kHz, 48kHz and 96kHz
† Dedicated Detect Pins
- Non-PCM Bit Stream Detect Pin
- Validity Flag Detect Pin
- 96kHz Sampling Detect Pin
- Unlock & Parity Error Detect Pin
† Supports up to 24bit Audio Data Format
† Audio I/F: Master or Slave Mode
† 32bits Channel Status Buffer
† Burst Preamble bit Pc, Pd Buffer for Non-PCM bit stream
† Serial µP I/F
† Two Master Clock Outputs: 128fs/256fs/512fs
† Operating Voltage: 2.7 to 3.6V with 5V tolerance
† Small Package: 28pin VSOP
† Ta: -40~85°C
MS0078-E-02
2004/04
-1-
ASAHI KASEI
[AK4112B]
AVSS
RX1
RX2
Input
RX3
Selector
AVDD
R
MCKO1
MCKO2
Clock
Clock
Recovery
Generator
XTI
XTO
X'tal
Oscillator
RX4
96kHz
Detect
V/TX
FS96
DAUX
DAIF
LRCK
DEM
Decoder
DVDD
Audio
BICK
I/F
SDTO
DVSS
TVDD
CSN
System
PDN
AC-3/MPEG
Control
Error
µp I/F
CDTO
Detect
Detect
CCLK
CDTI
AUTO
ERF
P/S="L"
Serial Control Mode
AVSS
RX1
AVDD
R
MCKO1
MCKO2
Clock
Clock
Recovery
Generator
XTI
XTO
X'tal
Oscillator
96kHz
Detect
DAUX
LRCK
DAIF
V
BICK
DEM
Audio
Decoder
DVDD
FS96
4
I/F
SDTO
DIF0
DIF1
DVSS
DIF2
OCKS0
OCKS1
TVDD
System
CM0
CM1
Control
OCKS0
AC-3/MPEG
Detect
Error
OCKS1
Detect
CM0
PDN
CM1
AUTO
ERF
P/S="H"
Parallel Control Mode
MS0078-E-02
2004/04
-2-
ASAHI KASEI
[AK4112B]
„ Ordering Guide
-40 ~ +85 °C
AK4112BVF
28pin VSOP (0.65mm pitch)
„ Pin Layout
DVDD
1
28
CM0/CDTO
DVSS
2
27
CM1/CDTI
TVDD
3
26
OCKS1/CCLK
V/TX
4
25
OCKS0/CSN
XTI
5
24
MCKO1
XTO
6
23
MCKO2
PDN
7
22
DAUX
R
8
21
BICK
AVDD
9
20
SDTO
AVSS
10
19
LRCK
RX1
11
18
ERF
RX2/DIF0
12
17
FS96
RX3/DIF1
13
16
P/SN
RX4/DIF2
14
15
AUTO
Top
View
MS0078-E-02
2004/04
-3-
ASAHI KASEI
[AK4112B]
PIN/FUNCTION
No.
1
2
3
5
6
Pin Name
DVDD
DVSS
TVDD
V
TX
XTI
XTO
9
AVDD
-
Function
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Input Buffer Power Supply Pin, 3.3V or 5V
Validity Flag Output Pin in Parallel Mode
Transmit channel (through data) Output Pin in Serial Mode
X'tal Input Pin
X'tal Output Pin
Power-Down Mode Pin
When “L”, the AK4112B is powered-down and reset.
External Resistor Pin
18kΩ +/-1% resistor to AVSS externally.
Analog Power Supply Pin
7
PDN
I
8
R
-
10
AVSS
-
Analog Ground Pin
11
RX1
I
DIF0
RX2
DIF1
RX3
DIF2
RX4
I
I
I
I
I
I
15
AUTO
O
16
P/S
I
17
FS96
O
18
ERF
O
19
20
21
22
23
24
LRCK
SDTO
BICK
DAUX
MCK02
MCK01
OCKS0
CSN
OCKS1
CCLK
CM1
CDTI
4
12
13
14
25
26
27
28
CM0
I/O
O
O
I
O
I/O
O
I/O
I
O
O
I
I
I
I
I
I
I
Receiver Channel 1
This channel is selected in Parallel Mode or default of Serial Mode.
Audio Data Interface Format 0 Pin in Parallel Mode
Receiver Channel 2 in Serial Mode
Audio Data Interface Format 1 Pin in Parallel Mode
Receiver Channel 3 in Serial Mode
Audio Data Interface Format 2 Pin in Parallel Mode
Receiver Channel 4 in Serial Mode
Non-PCM Detect Pin
“L”: No detect, “H”: Detect
Parallel/Serial Select Pin
“L”: Serial Mode, “H”: Parallel Mode
96kHz Sampling Detect Pin
(RX Mode)
“H”: fs=88.2kHz or more, “L”: fs=54kHz or less.
(X’tal Mode) “H”: XFS96=1, “L”: XFS96=0.
Unlock & Parity Error Output Pin
“L”: No Error, “H”: Error
Output Channel Clock Pin
Audio Serial Data Output Pin
Audio Serial Data Clock Pin
Auxiliary Audio Data Input Pin
Master Clock #2 Output Pin
Master Clock #1 Output Pin
Output Clock Select 0 Pin in Parallel Mode
Chip Select Pin in Serial Mode
Output Clock Select 1 Pin in Parallel Mode
Control Data Clock Pin in Serial Mode
Master Clock Operation Mode Pin0 in Parallel Mode
Control Data Input Pin in Serial Mode
Master Clock Operation Mode Pin1 in Parallel Mode
CDTO
O
Control Data Output Pin in Serial Mode
Note 1: All input pins except internal pull-down pins should not be left floating.
MS0078-E-02
2004/04
-4-
ASAHI KASEI
[AK4112B]
ABSOLUTE MAXIMUM RATINGS
(AVSS, DVSS=0V; Note 2)
Parameter
Power Supplies:
Analog
Digital
Input Buffer
|AVSS-DVSS|
(Note 3)
Input Current, Any Pin Except Supplies
Input Voltage (Except XTI pin)
Input Voltage (XTI pin)
Symbol
min
max
Units
AVDD
DVDD
TVDD
∆ GND
IIN
VIN
VINX
-0.3
-0.3
-0.3
4.6
4.6
6.0
0.3
±10
TVDD+0.3
DVDD+0.3
V
V
V
V
mA
V
V
-0.3
-0.3
°C
°C
Ambient Temperature (power applied)
Ta
-40
85
Storage Temperature
Tstg
-65
150
Note 2: All voltages with respect to ground.
Note 3: AVSS and DVSS must be connected to the same ground.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS
(AVSS, DVSS=0V;Note 2)
Parameter
Power Supplies:
Analog
Digital
Input Buffer
Note 2: All voltages with respect to ground.
Symbol
min
typ
max
Units
AVDD
DVDD
TVDD
2.7
2.7
DVDD
3.3
3.3
3.3
3.6
AVDD
5.5
V
V
V
typ
max
Units
S/PDIF RECEIVER CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V)
Parameter
Input Resistance
Symbol
min
Zin
Input Voltage
Input Hysteresis
Input Sample Frequency
VTH
VHY
fs
350
22
10
kΩ
130
-
mVpp
mV
kHz
108
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD=2.7~3.6V;TVDD=2.7~5.5V; unless otherwise specified)
Parameter
Symbol
min
Power Supply Current
Normal operation : PDN = “H” (Note 4)
Power down: PDN = “L” (Note 5)
High-Level Input Voltage (Except XTI pin)
VIH
70%DVDD
High-Level Input Voltage (XTI pin)
VIH
70%DVDD
Low-Level Input Voltage
VIL
DVSS-0.3
High-Level Output Voltage
(Iout=-400µA)
VOH
DVDD-0.4
Low-Level Output Voltage
(Iout=400µA)
VOL
Input Leakage Current
Iin
Note 4: AVDD, DVDD=3.3V, TVDD=5.0V, CL=20pF, fs=96kHz, X'tal=12.288MHz,
Clock Operation Mode 2, OCKS1=1, OCKS0=0.
AVDD=8mA(typ), DVDD=12mA(typ), TVDD=10µA(typ)
Note 5: RX inputs are open and all digital input pins are held DVDD or DVSS.
MS0078-E-02
typ
max
Units
20
10
-
40
100
TVDD
DVDD
30%DVDD
0.4
± 10
mA
µA
V
V
V
V
V
µA
2004/04
-5-
ASAHI KASEI
[AK4112B]
SWITCHING CHARACTERISTICS
(Ta=25°C; DVDD, AVDD2.7~3.6V, TVDD=2.7~5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Crystal Resonator
Frequency
fXTAL
11.2896
24.576
MHz
External Clock
Frequency
Duty
Frequency
Duty
fECLK
dECLK
fMCK1
dMCK1
11.2896
40
5.632
40
24.576
60
27.648
60
MHz
%
MHz
%
Frequency
Duty
fMCK2
dMCK2
fpll
fs
dLCK
2.816
40
22
22
45
27.648
60
108
108
55
MHz
%
kHz
kHz
%
tBCK
tBCKL
tBCKH
tLRB
tBLR
tLRM
tBSD
tDXH
tDXS
140
60
60
30
30
MCKO1 Output
MCKO2 output
PLL Clock Recover Frequency (RX1-4)
LRCK Frequency
Duty Cycle
Audio Interface Timing
Slave Mode
BICK Period
BICK Pulse Width Low
Pulse Width High
LRCK Edge to BICK “↑”
(Note 6)
BICK “↑” to LRCK Edge
(Note 6)
LRCK to SDTO (MSB)
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
Master Mode
BICK Frequency
BICK Duty
BICK “↓” to LRCK
BICK “↓” to SDTO
DAUX Hold Time
DAUX Setup Time
Control Interface Timing
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDTI Setup Time
CDTI Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK "↑" to CSN “↑”
CDTO Delay
CSN “↑” to CDTO Hi-Z
fBCK
dBCK
tMBLR
tBSD
tDXH
tDXS
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tDCD
tCCZ
50
50
50
48
35
35
20
20
64fs
50
-20
20
40
20
20
200
80
80
50
50
150
50
50
45
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Reset Timing
PDN Pulse Width
tPW
150
Note 6: BICK rising edge must not occur at the same time as LRCK edge.
ns
MS0078-E-02
2004/04
-6-
ASAHI KASEI
[AK4112B]
„ Timing Diagram
50%DVDD
LRCK
tBLR
tLRB
tBCKL
tBCKH
BICK
50%DVDD
tLRM
tBSD
50%DVDD
SDTO
tDXS
tDXH
50%DVDD
DAUX
Serial Interface Timing (Slave Mode)
LRCK
50%DVDD
tMBLR
50%DVDD
BICK
tBSD
50%DVDD
SDATA
tDXS
tDXH
50%DVDD
DAUX
Serial Interface Timing (Master Mode)
50%DVDD
CSN
tCSS
tCCKL tCCKH
50%DVDD
CCLK
tCDH
tCDS
CDTI
CDTO
C0
C0
R/W
A4
50%DVDD
Hi-Z
WRITE/READ Command Input Timing
MS0078-E-02
2004/04
-7-
ASAHI KASEI
[AK4112B]
tCSW
50%DVDD
CSN
tCSH
50%DVDD
CCLK
CDTI
D3
D2
D1
50%DVDD
D0
Hi-Z
CDTO
WRITE Data Input Timing
CSN
50%DVDD
CCLK
50%DVDD
CDTI
A1
50%DVDD
A0
tDCD
Hi-Z
CDTO
D7
D6
D5
50%DVDD
READ Data Output Timing 1
tCSW
CSN
50%DVDD
tCSH
CCLK
50%DVDD
CDTI
50%DVDD
tCCZ
CDTO
D3
D2
D1
D0
50%DVDD
READ Data Input Timing 2
tPW
PDN
30%DVDD
Power Down & Reset Timing
MS0078-E-02
2004/04
-8-
ASAHI KASEI
[AK4112B]
OPERATION OVERVIEW
„ Non-PCM (AC-3, MPEG, etc.) Stream Detect
The AK4112B has a Non-PCM steam auto detect function. When the 32bit mode Non-PCM preamble based on Dolby
“AC-3 Data Stream in IEC958 Interface” is detected, the AUTO goes “H”. The 96bit sync code consists of 0x0000,
0x0000, 0x0000, 0x0000, 0xF872 and 0x4E1F. Detection of this pattern will set the AUTO “H”. Once the AUTO is set
“H”, it will remain “H” until 4096 frames pass through the chip without additional sync pattern being detected. When
those preambles are detected, the burst preambles Pc and Pd that follow those sync codes are stored to registers
0DH-10H.
„ Clock Recovery and 96kHz Detect
On chip low jitter PLL has a wide lock range with 22kHz to 108kHz and the lock time is less than 20ms. The 96kHz
detect output pin FS96 goes “H” when the sampling rate is 88.2kHz or more and “L” at 54kHz or less. In X’tal Mode, the
FS96 pin outputs the value which is set by XFS96. PLL loses lock when the received sync interval is incorrect.
„ Master Clock
The AK4112B has two clock outputs, MCKO1 and MCKO2. These clocks are derived from either the recovered clock or
from the X'tal oscillator. The frequencies of the master clock outputs (MCKO1 & MCKO2) are set by OCKS0 and
OCKS1 as shown in Table 1. 96kHz sampling is not supported at No.2.
No.
0
1
2
3
OCKS1
0
0
1
1
OCKS0
0
1
0
1
MCKO1
256fs
256fs
512fs
MCKO2
256fs
128fs
256fs
X’tal
256fs
256fs
512fs
Test Mode
fs (kHz)
32, 44.1, 48, 96
32, 44.1, 48, 96
32, 44.1, 48
Default
Table 1. Master clock frequencies select
„ Clock Operation Mode
The CM0 and CM1 select the clock source of MCKO1/2 and the data source of SDTO via the dedicated pins or the
control register. In Mode 2, the clock source is switched from PLL to X'tal when PLL goes unlock state. In Mode3, the
clock source is fixed to X'tal, but PLL is also operating and the recovered data such as C bits can be monitored.
Mode
CM1
CM0
UNLOCK
PLL
X'tal
Clock source
FS96
0
1
0
0
0
1
-
ON
OFF
OFF
ON
PLL
X'tal
SDTO
RFS96
XFS96
RX
DAUX
2
1
0
0
1
ON
ON
PLL
RFS96
XFS96
ON
ON
X'tal
ON
ON
X'tal
XFS96
ON: Oscillation (Power-up), OFF: STOP (Power-down)
RX
DAUX
DAUX
3
1
1
Default
Table 2. Clock Operation Mode select
MS0078-E-02
2004/04
-9-
ASAHI KASEI
[AK4112B]
„ Clock Source
The following circuits are available to feed the clock to XTI pin (#5 pin) of AK4112B.
1) X’tal
XTI
XTO
AK4112B
Note: External capacitance depends on the crystal oscillator (Typ. 10-40pF)
2) External clock
XTI
External Clock
XTO
AK4112B
Note: Input clock must not exceed DVDD.
3) Fixed to the Clock Operation Mode 0
XTI
XTO
AK4112B
MS0078-E-02
2004/04
- 10 -
ASAHI KASEI
[AK4112B]
„ Sampling Frequency and Pre-emphasis Detect
The AK4112B outputs the encoded information of sampling frequency and pre-emphasis in channel status to FS0, FS1
and PEM bits in control register. These information are output from channel 1 at default. It can be switched to channel 2
by CS12 bit in control register.
FS1
FS0
fs
Byte 3
Bits 0-3
0
0
1
1
0
1
0
1
44.1kHz
Reserved
48kHz
32kHz
0000
all others
0100
1100
Table 3. fs information in Consumer Mode
FS1
FS0
fs
Byte 0
Bits 6-7
0
0
1
1
0
1
0
1
44.1kHz
Reserved
48kHz
32kHz
10
00
01
11
Table 4. fs information in Profession Mode
PEM
Pre-emphasis
Byte 0
Bits 3-5
0
1
OFF
ON
≠ 0X100
0X100
Table 5. PEM in Consumer Mode
PEM
Pre-emphasis
Byte 0
Bits 2-4
0
1
OFF
ON
≠110
110
Table 6. PEM in professional Mode
MS0078-E-02
2004/04
- 11 -
ASAHI KASEI
[AK4112B]
„ De-emphasis Filter Control
The AK4112B includes the digital de-emphasis filter (tc=50/15µs) by IIR filter corresponding to four sampling
frequencies (32kHz, 44.1kHz, 48kHz and 96kHz). When DEAU bit=“1”, the de-emphasis filter is enabled automatically
by sampling frequency and pre-emphasis information in the channel status. The AK4112B goes this mode at default.
Therefore, in Parallel Mode, the AK4112B is always placed in this mode and the de-emphasis filter is controlled by the
status bits in channel 1. In Serial Mode, DEM0/1 and DFS bits can control the de-emphasis filter when DEAU is “0”.
When the “0” data is input to the de-emphasis filter, the output data will be “0” or “-1”. The internal de-empahsis filter is
bypassed and the recovered data is output without any change if either pre-emphasis or de-emphasis Mode is OFF.
FS96
FS1
FS0
Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
Table 7. De-emphasis Auto Control at DEAU=“1” and PEM=“1”
DFS
DEM1
DEM0
Mode
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
44.1kHz
OFF
48kHz
32kHz
OFF
OFF
96kHz
OFF
Default
Table 8. De-emphasis Manual Control at DEAU=“0” and PEM=“1”
MS0078-E-02
2004/04
- 12 -
ASAHI KASEI
[AK4112B]
„ System Reset and Power-Down
The AK4112B has a power-down mode for all circuits by PDN pin can be partially powerd-down by PWN bit. The
RSTN bit initializes the register and resets the internal timing. In Parallel Mode, only the control by PDN pin is enabled.
The AK4112B should be reset once by bringing PDN pin = “L” upon power-up.
PDN Pin (Pin #7):
All analog and digital circuit are placed in the power-down and reset mode by bringing PDN= “L”. All the
registers are initialized, and clocks are stopped. Reading/Witting to the register are disabled.
RSTN Bit (Address 00H; D0):
All the registers except PWN and RSTN are initialized by bringing RSTN bit = “0”. The internal timings are
also initialized. Witting to the register is not available except PWN and RSTN. Reading to the register is
disabled.
PWN Bit (Address 00H; D1):
The clock recovery part is initialized by bringing PWN bit = “0”. In this case, clocks are stopped. The registers
are not initialized and the mode settings are kept. Writing and Reading to the registers are enabled.
„ Biphase Input and Through Output
Four receiver inputs (RX1-4) are available in Serial Control Mode. Each input includes amplifier corresponding to
unbalance mode and can accept the signal of 350mV or more. IPS0-1 selects the receiver channel, and OPS0-1 selects the
source of the bit stream driving the transmit channel (TX). The TX output can be stopped by setting TXE bit “0”.
IPS1
IPS0
INPUT Data
0
0
1
1
0
1
0
1
RX1
RX2
RX3
RX4
Default
Table 9. Recovery data select
OPS1
OPS0
INPUT Data
0
0
1
1
0
1
0
1
RX1
RX2
RX3
RX4
Default
Table 10. Output data select
MS0078-E-02
2004/04
- 13 -
ASAHI KASEI
[AK4112B]
0.1uF
RX
75Ω
Coax
75Ω
0.47nF
Note
AK4112B
Figure 1. Consumer Input Circuit (Coaxial Input)
Note: In case of coaxial input, if a coupling level to this input from the next RX input line
pattern exceeds 50mV, there is a possibility to occur an incorrect operation. In this case, it is
possible to lower the coupling level by adding this decoupling capacitor.
Optical Receiver
Optical
Fiber
470
RX
O/E
AK4112B
Figure 2. Consumer Input Circuit (Optical Input)
In case of coaxial input, as the input level of RX line is small, in Serial Mode, be careful not to crosstalk among RX input
lines. For example, by inserting the shield pattern among them. In Parallel Mode, only one channel input (RX1) is
available and RX2-4 change to other pins for audio format control. Those pins must be fixed to “H” or “L”.
The AK4112B includes the TX output buffer. The output level meets combination 0.5V+/-20% using the external resistor
network. The T1 in Figure 3 is a transformer of 1:1.
R1
TX
75Ω cable
R2
DVSS
T1
Vdd
R1
R2
3.3V 240Ω 150Ω
3.0V 220Ω 150Ω
Figure 3. TX External Resistor Network
MS0078-E-02
2004/04
- 14 -
ASAHI KASEI
[AK4112B]
„ Error Handling
There are the following five factors which ERF pin goes “H”. ERF pin shows the status of the internal PLL operation and
it is “L” when the PLL is OFF (Clock Operation Mode 1).
1. Unlock Error
2. Parity Error
3. Biphase Error
4. Frame length Error
5. STC (Status Change) flag=“1”
: “H” when the PLL goes UNLOCK state.
: Updated every sub-frame cycle.
: Updated every sub-frame cycle
: Updated every sub-frame cycle
: Holds “1” until reading 03H.
In Parallel Mode, ERF pin outputs the ORed signal including the factors of 1,2,3 and 4. Once ERF pin goes ”H”, it
maintains “H” for 1024/fs cycles after the all error factors are removed. Table 11 shows the state of each output pins
when the ERF pin is “H”. The Frame length Error is occurred when the interval of preamble in biphase signal is incorrect.
When unlock state, the channel status bits are not updated and the previous data is maintained.
Error
AUTO
SDTO
V
Unlock Error
Parity Error
Biphase Error
Frame Length Error
“L”
Output
Output
Output
“L”
Previous Data
Previous Data
Previous Data
“L”
Output
Output
Output
Table 11. Error handling (Parallel Mode)
In Serial Mode, ERF pin outputs the ORed signal including the factors of 1,2,3,4 and 5. However, Parity, Biphase and
Frame Length Error can be masked by MPAR bit, and the STC flag can be masked by MSTC bit. When those are masked
by each bit, the error factor does not affect ERF pin operation. The STC flag is set whenever a comparison between the
last sample of bits D5-0 of the receiver status 1 register (03H) and the new sample are different This comparison is made
every fs cycle. The STC flag is reset by reading the register 03H. This flag is also disabled during the first block after
reset.
Once ERF pin goes ”H”, it maintains “H” for 1024/fs cycles (can be changed by ERFH0-1 bits) after the all error factors
(In case of STC, from STC flag “1” to reading 03H) are removed. Once PAR, BIP, FRERR, V or UNLOCK bit goes “1”,
it returns “0” by reading Receiver Status 2 (04H). When unlock state, the channel status bits are not updated and the
previous data is maintained.
Error
& Status
Unlock Error
Parity Error
Biphase Error
Frame Length Error
Status change
UNLOCK
1
0
0
0
0
Register
PAR BIP FRERR
0
1
0
0
0
0
0
1
0
0
0
0
0
1
0
Pin
STC
AUTO
SDTO
V
TX
0
0
0
0
1
“L”
Output
Output
Output
Output
“L”
Previous Data
Previous Data
Previous Data
Output
“L”
Output
Output
Output
Output
Output
Output
Output
Output
Output
Table 12. Error handling (Serial Mode; MPAR=1, MSTC=1)
MS0078-E-02
2004/04
- 15 -
ASAHI KASEI
[AK4112B]
(status change )
(ch. status )
STC bit
(state A )
(state B)
Reset
Hold “1”
Command
READ 03H
ERF
ERF Hold Time
MCKO, BICK,
LRCK
SDTO
V
ERF pin timing at Status Change
error(UNLOCK,
PAR, BIP, FRERR)
(error)
ERF
ERF Hold Time
register (UNOCK,
PAR, BIP, FRERR)
Reset
Hold ”1”
Command
READ 04H
(fs: around 20kHz)
MCKO,BICK,LRCK
(UNLOCK)
Free Run
MCKO,BICK,LRCK
(except UNLOCK)
SDTO(UNLOCK)
SDTO
(except UNLOCK)
Previous Data
Vpin (UNLOCK)
Vpin
(except UNLOCK)
ERF pin timing at UNLOCK, PAR, BIP, FRERR error
MS0078-E-02
2004/04
- 16 -
ASAHI KASEI
[AK4112B]
PD pin ="L" to "H"
Initialize
Read 03H
STC is reset, ERF pin ="L"
Read 04H
ERF pin ="H"
YES
Mute = "H"
Read 03H
Mute="L"
STC is reset, ERF pin ="L"
Read 04H
NO
ERF pin ="H"
YES
Figure 4. Error handling sequence Example
MS0078-E-02
2004/04
- 17 -
ASAHI KASEI
[AK4112B]
„ Audio Serial Interface Format
The DIF0, DIF1 and DIF2 pins as shown in Table 13 can select eight serial data formats. In all formats the serial data is
MSB-first, 2's compliment format. The SDTO is clocked out on the falling edge of BICK and the DAUX is latched on
the rising edge of BICK. BICK outputs 64fs clock in Mode 0-5. Mode 6-7 are Slave Modes, and BICK is available up to
128fs at fs=48kHz. In the format equal or less than 20bit (Mode0-2), LSBs in sub-frame are truncated. In Mode 3-7, the
last 4LSBs are auxiliary data (see Figure 5).
When the Parity Error, Biphase Error or Frame Length Error occurs in a sub-frame, AK4112B continues to output the
last normal sub-frame data from SDTO repeatedly until the error is removed. When the Unlock Error occurs, AK4112B
output “0” from SDTO. In case of using DAUX pin, the data is transformed and output from SDTO. DAUX pin is used
in Clock Operation Mode 1, 3 and unlock state of Mode 2.
The input data format to DAUX should be left justified except in Mode5 and 7(Table 13). In Mode5 or 7, both the input
data format of DAUX and output data format of SDTO are I2S. Mode6 and 7 are Slave Mode that is corresponding to the
Master Mode of Mode4 and 5. In salve Mode, LRCK and BICK should be fed with synchronizing to MCKO1/2.
The initial state of the audio format is the Master Mode upon the power-up. Therefore, if the audio format is changed to
the Slave Mode after power-up, the setting of the external clocks should be careful until completing to set the control
registers.
sub-frame of IEC958
0
3 4
preamble
7 8
11 12
27 28 29 30 31
Aux.
V U C P
LSB
MSB
MSB
LSB
23
0
AK4112B Audio Data (MSB First)
Figure 5. Bit configuration
Mode
DIF2
DIF1
DIF0
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
DAUX
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
SDTO
16bit, Right justified
18bit, Right justified
20bit, Right justified
24bit, Right justified
24bit, Left justified
24bit, I2S
24bit, Left justified
24bit, I2S
LRCK
I/O
H/L
O
H/L
O
H/L
O
H/L
O
H/L
O
L/H
O
H/L
I
L/H
I
BICK
64fs
64fs
64fs
64fs
64fs
64fs
64-128fs
64-128fs
I/O
O
O
O
O
O
O
I
I
Default
Table 13. Audio data format
MS0078-E-02
2004/04
- 18 -
ASAHI KASEI
[AK4112B]
LRCK(0)
0
1
2
15
16
17
31
0
1
2
15
16
17
31
0
1
0
1
0
1
BICK
(0:64fs)
15
14
1
0
15
14
1
0
SDTO(0)
15:MSB, 0:LSB
Rch Data
Lch Data
Figure 5. Mode 0 Timing
LRCK(0)
0
1
2
9
10
12
11
31
0
1
2
9
10
11
12
31
BICK
(0:64fs)
23
22
21
20
1
0
23
22
21
20
1
0
SDTO(0)
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 6. Mode 3 Timing
LRCK
0
1
2
21
22
24
23
31
0
1
2
21
22
23
24
31
BICK
(64fs)
23
22 21
2
1
0
23 22
3
2
1
0
23 22
SDTO(0)
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 7. Mode 4, 6 Timing
Mode 4: LRCK, BICK: Output
Mode 6: LRCK, BICK: Input
LRCK
0
1
2
22
24
23
25
31
0
1
2
21
22
23
24
25
31
0
1
BICK
(64fs)
SDTO(0)
23
22 21
2
1
23 22
0
3
2
1
0
23
23:MSB, 0:LSB
Rch Data
Lch Data
Figure 8. Mode 5, 7 Timing
MS0078-E-02
Mode 5: LRCK, BICK: Output
Mode 7: LRCK, BICK: Input
2004/04
- 19 -
ASAHI KASEI
[AK4112B]
„ Serial Control Interface
The internal registers may be either written or read by the 4-wire µP interface pins: CSN, CCLK, CDTI & CDTO. The
data on this interface consists of Chip address (2bits, C0/1 are fixed to “00”), Read/Write (1bit), Register address (MSB
first, 5bits) and Control data (MSB first, 8bits). Address and data is clocked in on the rising edge of CCLK and data is
clocked out on the falling edge. For write operations, data is latched after the 16th rising edge of CCLK, after a
high-to-low transition of CSN. For read operations, the CDTO output goes high impedance after a low-to-high transition
of CSN. The maximum speed of CCLK is 5MHz. PDN= “L” resets the registers to their default values. When the state of
P/S pin is changed, the AK4112B should be reset by PDN= “L”.
CSN
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CCLK
CDTI
WRITE
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
CDTI
READ
C1 C0 R/W A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
CDTO
C1-C0:
R/W:
A4-A0:
D7-D0:
D7 D6 D5 D4 D3 D2 D1 D0
Hi-Z
Chip Address (Fixed to “00”)
READ/WRITE (0:READ, 1:WRITE)
Register Address
Control Data
Figure 10. Control I/F Timing
MS0078-E-02
2004/04
- 20 -
ASAHI KASEI
[AK4112B]
„ Register Map
Addr Register Name
D7
D6
D5
D4
D3
D2
OCKS1 OCKS0
D1
D0
00H
Clock & Power down Control
0
BCU
CM1
CM0
PWN
RSTN
01H
Input/Output Control
MPAR
MSTC
CS12
TXE
IPS1
IPS0
OPS1
OPS0
02H
Format & De-emphasis Control
V/TX
DIF2
DIF1
DIF0
DEAU
DEM1
DEM0
DFS
03H
Receiver status 1
ERF
0
AUDION
AUTO
PEM
FS1
FS0
RFS96
04H
Receiver status 2
CV
STC
CRC
UNLOCK
V
FRERR
BIP
PAR
05H
Channel A Status Byte 0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
06H
Channel A Status Byte 1
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
07H
Channel A Status Byte 2
CA23
CA22
CA21
CA20
CA19
CA18
CA17
CA16
08H
Channel A Status Byte 3
CA31
CA30
CA29
CA28
CA27
CA26
CA25
CA24
09H
Channel B Status Byte 0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
0AH Channel B Status Byte 1
CB15
CB14
CB13
CB12
CB11
CB10
CB9
CB8
0BH Channel B Status Byte 2
CB23
CB22
CB21
CB20
CB19
CB18
CB17
CB16
0CH Channel B Status Byte 3
CB31
CB30
CB29
CB28
CB27
CB26
CB25
CB24
0DH Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
0EH Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
0FH
Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10H
Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
11H
Count Control
0
0
0
0
0
EFH1
EFH0
XFS96
Notes:
For addresses from 12H to 1FH, data must not be written.
When PDN pin goes “L”, the registers are initialized to their default values.
When RSTN bit goes “0”, the internal timing is reset and the registers are initialized to their default values.
All data can be written to the register even if PWN bit is “0”.
MS0078-E-02
2004/04
- 21 -
ASAHI KASEI
[AK4112B]
„ Register Definitions
Reset & Initialize
Addr
Register Name
D7
D6
D5
D4
00H
Clock & Power down Control
0
BCU
CM1
CM0
RD
0
R/W
0
R/W
0
R/W
0
R/W
default
D3
D2
OCKS1 OCKS0
R/W
0
D1
D0
PWN
RSTN
R/W
1
R/W
1
R/W
0
RSTN:
Timing Reset & Register Initialize
0: Reset & Initialize
1: Normal Operation
PWN:
Power Down
0: Power down
1: Normal Operation
OCKS1-0: Master Clock frequency Select
CM1-0: Master Clock Operation Mode Select
BCU:
Block start & C/U output Mode
When BCU=1, the 3 output pins change another function.
MCKO2 pin→ B; block start signal
AUTO pin→ C bit
FS96 pin→ U bit
The block signal goes high at the start of frame 0 and remains high until the end of frame 31.
(B, C, U, V output timing at RX mode, Master mode)
B
C (or U,V)
C(R191)
C(L0)
C(R0)
C(L1)
C(L31)
C(R31) C(L32)
1/4fs
LRCK
SDTO
(I2S)
SDTO
(except I2S)
L191
R191
L0
R0
R30
L31
R31
R190
L191
R191
L0
L30
R30
L31
MS0078-E-02
2004/04
- 22 -
ASAHI KASEI
[AK4112B]
Input/Output Control
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
MPAR
MSTC
CS12
TXE
IPS1
IPS0
OPS1
OPS0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
default
1
0
0
1
0
0
0
0
01H Input/Output Control
OPS1-0: Output Through Data Select
IPS1-0: Input Recovery Data Select
TXE:
TX Output Enable
0: Disable. TX output pin is placed in a high impedance state.
1: Enable
CS12:
Channel Status Select
0: Channel 1
1: Channel 2
Selects which channel status is used to derive AUDION, PEM, FS1 and FS0.
The de-emphasis filter, however, is always controlled by channel 1 in the Parallel Mode.
MSTC: Status change flag mask bit
This bit is low to mask status change from being reported by ERF.
MPAR: Parity mask bit
This bit is low to mask Parity Error, Biphase Error and Frame Length Error from being reported by
ERF.
Format & De-emphasis Control
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
02H Format & De-emphasis Control
V/TX
DIF2
DIF1
DIF0
DEAU
DEM1
DEM0
DFS
R/W
default
R/W
0
R/W
1
R/W
0
R/W
0
R/W
1
R/W
0
R/W
1
R/W
0
V/TX:
V/TX Output Select
0: Validity Flag Output. This output is updated every fs cycle.
1: TX
DFS:
96kHz De-emphasis Control
DEM1-0: 32, 44.1, 48kHz De-emphasis Control
DEAU: De-emphasis Auto Detect Enable
0: Disable
1: Enable
DIF2-0: Audio Data Format Control
MS0078-E-02
2004/04
- 23 -
ASAHI KASEI
[AK4112B]
Receiver Status 1
Addr
Register Name
03H Receiver status 1
D7
D6
D5
D4
D3
D2
D1
D0
ERF
0
AUDION
AUTO
PEM
FS1
FS0
RFS96
R/W
RD
RD
RD
RD
RD
RD
RD
RD
default
0
0
0
0
0
0
0
0
RFS96:
96kHz Sampling Detect at Recovery Mode.
0: fs=54kHz or less.
1: fs=88.2kHz or more
FS1-0:
Sampling Frequency Output
PEM:
Pre-emphasis Output
0: OFF
1: ON
This bit is made by encoding channel status bits.
AUTO: Non-PCM Auto Detect
0: No detect
1: Detect
This function is the same as AUTO pin.
AUDION: Audio bit Output
0: Audio
1: Non Audio
ERF:
Unlock or Parity Error or Status change
0: No Error or No change
1: Error or Change
This function is the same as ERF pin. This bit goes “1” when Unlock Error, Parity Error, Biphase
Error, Frame Length Error or Status Change occurs. If MPAR=0 & MSTC=0, only an unlock error
is reported.
Receiver Status 2
Addr
Register Name
04H Receiver status 2
R/W
default
D7
D6
D5
D4
D3
D2
D1
D0
CV
STC
CRC
UNLOCK
V
FRERR
BIP
PAR
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
RD
0
PAR:
Parity Status (0:No Error, 1:Error)
It is high if Parity Error is detected in the sub-frame. PAR is unaffected by the state of MPAR.
BIP:
Biphase Status (0:No Error, 1:Error)
FRERR: Frame Error Status (0:No Error, 1:Error)
V:
Validity bit (0:No Error, 1:Error)
UNLOCK: PLL Lock status (0:Lock, 1:Unlock)
CRC:
Cyclic Redundancy Check (0:No Error, 1:Error on either channel)
STC:
Status change flag of Receiver status 1 (0:No change, 1:change)
This flag goes “H” when the latest value of D5-0 in Receiver Status 1(03H) is different from the
previous value. This comparison is made at every fs cycle. This bit returns to “L” by reading
Receiver Status 1(03H). The flag is disabled during the first block after Reset.
CV:
Channel Status Validity (0:Valid, 1:Not Valid, data is updating)
This signal goes “H” at the start of frame 0 and maintains “H” until the end of frame 31.
MS0078-E-02
2004/04
- 24 -
ASAHI KASEI
[AK4112B]
Channel Status
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
05H Channel A Status Byte 0
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0
06H Channel A Status Byte 1
CA15
CA14
CA13
CA12
CA11
CA10
CA9
CA8
07H Channel A Status Byte 2
CA23
CA22
CA21
CA20
CA19
CA18
CA17
CA16
08H Channel A Status Byte 3
CA31
CA30
CA29
CA28
CA27
CA26
CA25
CA24
09H Channel B Status Byte 0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
0AH Channel B Status Byte 1
CB15
CB14
CB13
CB12
CB11
CB10
CB9
CB8
0BH Channel B Status Byte 2
CB23
CB22
CB21
CB20
CB19
CB18
CB17
CB16
0CH Channel B Status Byte 3
CB31
CB30
CB29
CB28
CB27
CB26
CB25
CB24
R/W
RD
default
Not initialized
CA31-0: Channel A Status Byte 4-1
CB31-0: Channel B Status Byte 4-1
Bit definition changes depending upon PRO bit setting. When CV=1, these bits are updating and
may be invalid.
Burst Preamble Pc/Pd in non-PCM encoded Audio bitstreams
Addr
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0DH Burst Preamble Pc Byte 0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
0EH Burst Preamble Pc Byte 1
PC15
PC14
PC13
PC12
PC11
PC10
PC9
PC8
0FH Burst Preamble Pd Byte 0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
10H Burst Preamble Pd Byte 1
PD15
PD14
PD13
PD12
PD11
PD10
PD9
PD8
R/W
RD
default
Not initialized
PC15-0: Burst Preamble Pc Byte 1, 0
PD15-0: Burst Preamble Pd Byte 1, 0
Count Control
Addr
11H
Register Name
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
EFH1
EFH0
XFS96
R/W
RD
RD
RD
RD
RD
R/W
R/W
R/W
default
0
0
0
0
0
0
1
0
Count Control
XFS96:
FS96 output select at X’tal Mode (clock Operation Mode1, Mode3 and Unlock state of Mode2)
1: FS96pin=“H”
0: FS96pin=“L”
EFH1-0: Error Flag Hold Count Select
00: 512 LRCK
01: 1024 LRCK
10: 2048 LRCK
11: 4096 LRCK
MS0078-E-02
2004/04
- 25 -
ASAHI KASEI
[AK4112B]
„ Burst preambles in non-PCM bitstreams
sub-frame of IEC958
0
3 4
preamble
7 8
Aux.
11 12
27 28 29 30 31
LSB
MSB V U C P
16 bits of bitstream
0
Pa Pb Pc Pd
15
Burst_payload
stuffing
repetition time of the burst
Preamble word
Pa
Pb
Pc
Pd
Length of field
16 bits
16 bits
16 bits
16 bits
Contents
sync word 1
sync word 2
Burst info
Length code
value
0xF872
0x4E1F
see Table 15.
numbers of bits
Table 14. Burst preamble words
Bits of Pc
value
0-4
5, 6
7
8-12
13-15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16-31
0
0
1
0
contents
repetition time of burst
in IEC958 frames
data type
NULL data
Dolby AC-3 data
reserved
PAUSE
MPEG-1 Layer1 data
MPEG-1 Layer2 or 3 data or MPEG-2 without extension
MPEG-2 data with extension
MPEG-2 AAC ADTS
MPEG-2, Layer1 Low sample rate
MPEG-2, Layer2 or 3 Low sample rate
reserved
DTS type I
DTS type II
DTS type III
ATRAC
ATRAC2/3
reserved
reserved, shall be set to “0”
error-flag indicating a valid burst_payload
error-flag indicating that the burst_payload may contain
errors
data type dependent info
bit stream number, shall be set to “0”
≤4096
1536
384
1152
1152
1024
384
1152
512
1024
2048
512
1024
Table 15. Fields of burst info Pc
MS0078-E-02
2004/04
- 26 -
ASAHI KASEI
[AK4112B]
„ Non-PCM Bitstream timing
1) When Non-PCM preamble is not coming within 4096 frames,
PDN pin
Bit stream
Pa Pb Pc1 Pd1
Pa Pb Pc2 Pd2
Repetition time
Pa Pb Pc3 Pd3
>4096 frames
AUTO
Pc Register
“0”
Pd Register
“0”
Pc1
Pc2
Pd1
Pc3
Pd2
Pd3
2) When Non-PCM bitstream stops
ERF hold time
ERF pin
<20mS (Lock time)
Bit stream
Pa Pb Pc1 Pd1
Stop
Pa Pb Pcn Pdn
2~3 Syncs (B,M or W)
<Repetition time
AUTO
Pc Register
Pd Register
Pc0
Pc1
Pd0
Pcn
Pd1
MS0078-E-02
Pdn
2004/04
- 27 -
ASAHI KASEI
[AK4112B]
SYSTEM DESIGN
Figure 11 shows the example of system connection diagram for Serial Mode.
3.3V Supply
10u 0.1u
+
1
DVDD
CDTO
28
2
DVSS
CDTI
27
3
TVDD
CCLK
26
4
V/TX
CSN
25
5
XTI
MCKO1
24
6
XTO
MCKO2
23
7
PDN
DAUX
22
3.3~5V Supply
+
0.1u
10u
C
(Note 8)
C
AK4112B
Microcontroller
18k
3.3V Supply
10u
+
0.1u
(see Figure 1,2)
8
R
BICK
21
9
AVDD
SDTO
20
10
AVSS
LRCK
19
11
RX1
ERF
18
12
RX2
FS96
17
13
RX3
P/SN
16
14
RX4
AUTO
15
DSP
and
AD/DA
Figure 11. Typical Connection Diagram (Serial Mode)
Notes:
- “C” depends on the crystal oscillator (Typ. 10-40pF)
- AVSS and DVSS must be connected the same ground plane
- Digital signals, especially clocks, should be kept away from the R pin in order to avoid an effect to the clock
jitter performance.
.
MS0078-E-02
2004/04
- 28 -
ASAHI KASEI
[AK4112B]
PACKAGE
28pin VSOP (Unit: mm)
*9.8±0.2
1.25±0.2
0.675
28
A
7.6±0.2
*5.6±0.2
15
14
1
+0.1
0.15-0.05
0.65
0.22±0.1
0.1±0.1
0.5±0.2
Detail A
Seating Plane
0.10
NOTE: Dimension "*" does not include mold flash.
0-10°
„ Material & Lead finish
Package molding compound: Epoxy
Lead frame material:
Cu
Lead frame surface treatment: Solder plate
MS0078-E-02
2004/04
- 29 -
ASAHI KASEI
[AK4112B]
MARKING
AKM
AK4112BVF
XXXBYYYYC
XXXXBYYYYC:
XXXB:
YYYYC:
Date code identifier
Lot number (X : Digit number, B : Alpha character )
Assembly date (Y : Digit number C : Alpha character)
IMPORTANT NOTICE
• These products and their specifications are subject to change without notice. Before considering
any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or
authorized distributor concerning their current status.
• AKM assumes no liability for infringement of any patent, intellectual property, or other right in the
application or use of any information contained herein.
• Any export of these products, or devices or systems containing them, may require an export license
or other official approval under the law and regulations of the country of export pertaining to
customs and tariffs, currency exchange, or strategic materials.
• AKM products are neither intended nor authorized for use as critical components in any safety, life
support, or other hazard related device or system, and AKM assumes no responsibility relating to
any such use, except with the express written consent of the Representative Director of AKM. As
used here:
(a) A hazard related device or system is one designed or intended for life support or maintenance
of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its
failure to function or perform may reasonably be expected to result in loss of life or in significant
injury or damage to person or property.
(b) A critical component is one whose failure to function or perform may reasonably be expected to
result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or
system containing it, and which must therefore meet very high standards of performance and
reliability.
• It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or
otherwise places the product with a third party to notify that party in advance of the above content
and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability
for and hold AKM harmless from any and all claims arising from the use of said product in the
absence of such notification.
MS0078-E-02
2004/04
- 30 -
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