M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
240pin Unbuffered DDR2 SDRAM MODULE
Based on 128Mx8 DDR2 SDRAM G-die
Features
Performance:
PC2-6400
Speed Sort
-AC
*
DIMM  Latency
Unit
5
f CK Clock Frequency
400
t CK Clock Cycle
2.5
MHz
ns
f DQ DQ Burst Frequency
800
Mbps
•Programmable Operation:
- Device  Latency: 5
- Burst Length: 4, 8
• Auto Refresh (CBR) and Self Refresh Modes
• Automatic and controlled precharge commands
• 14/10/1 Addressing (row/column/rank) – 1GB
• 14/10/2 Addressing (row/column/rank) – 2GB
• Serial Presence Detect
• On Die Termination (ODT)
• OCD impedance adjustment.
• Gold contacts
• SDRAMs in 60-ball BGA Package
• RoHs Compliance.
• JEDEC Standard 240-pin Dual In-Line Memory Module
• 128Mx64 and 256Mx64 DDR2 Unbuffered DIMM based on
Elixir 128Mx8 DDR2 SDRAM G-die component
• Double Data Rate architecture; two data transfer per clock cycle
• Differential bi-directional data strobe (DQS & )
• DQS is edge-aligned with data for reads and is center-aligned
with data for writes
• Differential clock inputs (CK & )
• Intended for 400MHz applications
• Inputs and outputs are SSTL-18 compatible
• VDD = VDDQ = 1.8V ± 0.1V
• 7.8 μs Max. Average Periodic Refresh Interval
Description
M2Y(F)1G64TU88G7(4)B and M2Y(F)2G64TU8HG5(4)B are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual
In-Line Memory Module (UDIMM), organized as one rank 128Mx64 and two ranks 256Mx64 high-speed memory array.
M2Y(F)1G64TU88G7(4)B uses eight 128Mx8 DDR2 SDRAMs and M2Y(F)2G64TU8G5(4)B uses sixteen 128Mx8 DDR2 SDRAMs in
BGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of
these common design files minimizes electrical variation between suppliers. All Elixir DDR2 SDRAM DIMMs provide a high-performance,
flexible 8-byte interface in a 5.25” long space-saving footprint.
The DIMM is intended for use in applications operating up to 400MHz clock speeds and achieves high-speed data transfer rates of up to
800Mbps. Prior to any access operation, the device  latency and burst / length /operation type must be programmed into the DIMM
by address inputs A0-A13 and I/O inputs BA0, BA1 and BA2 using the mode register set cycle.
The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of
serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer.
REV 1.0
10/2010
1
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Ordering Information
Part Number
Speed
M2Y1G64TU88G7B-AC
400MHz (2.50ns @ CL = 5)
Organization
DDR2-800
Leads
Power
PC2-6400
Rohs compliance
128Mx64
M2F1G64TU88G4B-AC
400MHz (2.50ns @ CL = 5)
DDR2-800
PC2-6400
M2Y2G64TU8HG5B-AC
400MHz (2.50ns @ CL = 5)
DDR2-800
PC2-6400
GOLD
1.8V
400MHz (2.50ns @ CL = 5)
DDR2-800
Rohs compliance and
Halogen-Free
Rohs compliance
256Mx64
M2F2G64TU8HG4B-AC
Note
Rohs compliance and
Halogen-Free
PC2-6400
Pin Description
CK0~CK2

CKE0, CKE1
Differential Clock Inputs
Clock Enable

Row Address Strobe

Column Address Strobe

Write Enable
, 
Chip Selects
A0-A9, A0-A13
A10/AP
BA0 ~ BA2
RESET
ODT0, ODT1
NC
Note:
DQ0-DQ63
DQS0-DQS8
DM0-DM8
-
Address Inputs
Data input/output
Bidirectional data strobes
Input Data Mask
Differential data strobes
VDD
Power (1.8V)
VREF
Ref. Voltage for SSTL_18 inputs
VDDSPD
Serial EEPROM positive power supply
Column Address Input/Auto-precharge
VSS
Ground
SDRAM Bank Address Inputs
SCL
Serial Presence Detect Clock Input
SDA
Serial Presence Detect Data input/output
Reset pin
On-die termination control lines
SA0 ~ SA2
Serial Presence Detect Address Inputs
No Connect
ODT1, CKE1 and are only support in 2GB module type.
REV 1.0
10/2010
2
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Pinout
Pin
Front
Pin
Front
Pin
Front
Pin
Back
Pin
Back
Pin
Back
1
VREF
42
NC
2
VSS
43
NC
82
VSS
83

121
VSS
122
DQ4
162
NC
202
DM4
163
VSS
203
NC
3
DQ0
44
4
DQ1
45
VSS
84
NC
85
DQS4
123
VSS
124
DQ5
164
NC
204
VSS
VSS
165
NC
205
DQ38
5
VSS
6

46
NC
47
VSS
86
DQ34
87
DQ35
125
DM0
166
VSS
206
DQ39
126
NC
167
NC
207
7
DQS0
48
NC
88
VSS
VSS
127
VSS
168
NC
208
DQ44
8
VSS
9
DQ2
49
NC
50
VSS
89
DQ40
128
DQ6
169
VSS
209
DQ45
90
DQ41
129
DQ7
170
VDDQ
210
VSS
10
DQ3
11
VSS
51
VDDQ
52
CKE0
91
VSS
130
VSS
171
NC,CKE1
211
DM5
92

131
DQ12
172
VDD
212
NC
12
DQ8
13
DQ9
53
54
VDD
93
DQS5
132
DQ13
173
NC
213
VSS
BA2
94
VSS
133
VSS
174
NC
214
DQ46
14
VSS
55
NC
95
DQ42
134
DM1
175
VDDQ
215
DQ47
15

16
DQS1
56
VDDQ
96
DQ43
135
NC
176
A12
216
VSS
57
A11
97
VSS
136
VSS
177
A9
217
DQ52
17
VSS
18
NC
58
A7
98
DQ48
137
CK1
178
VDD
218
DQ53
59
VDD
99
DQ49
138

179
A8
219
VSS
19
20
NC
60
A5
100
VSS
139
VSS
180
A6
220
CK2
VSS
61
A4
101
SA2
140
DQ14
181
VDDQ
221
21

DQ10
62
VDDQ
102
NC
141
DQ15
182
A3
222
VSS
22
DQ11
63
A2
103
VSS
142
VSS
183
A1
223
DM6
23
VSS
64
VDD
104

143
DQ20
184
VDD
224
NC
24
DQ16
25
DQ17
65
26
VSS
27

28
KEY
105
DQS6
144
DQ21
VSS
106
VSS
145
VSS
185
KEY
225
VSS
CK0
226
DQ54
66
VSS
107
DQ50
146
DM2
67
VDD
108
DQ51
147
NC
186

227
DQ55
187
VDD
228
DQS2
68
NC
109
VSS
148
VSS
VSS
188
A0
229
DQ60
29
VSS
69
VDD
110
DQ56
30
DQ18
70
A10/AP
111
DQ57
149
DQ22
189
VDD
230
DQ61
150
DQ23
190
BA1
231
VSS
31
DQ19
71
BA0
112
VSS
32
VSS
72
VDDQ
113

151
VSS
191
VDDQ
232
DM7
152
DQ28
192

233
NC
33
DQ24
73

114
34
DQ25
74

115
DQS7
153
DQ29
193

234
VSS
VSS
154
VSS
194
VDDQ
235
DQ62
35
VSS
75
VDDQ
116
DQ58
155
DM3
195
ODT0
236
DQ63
36

76
37
DQS3
77
NC, 
117
DQ59
156
NC
196
A13
237
VSS
NC,ODT1
118
VSS
157
VSS
197
VDD
238
VDDSPD
38
VSS
78
39
DQ26
79
VDDQ
119
SDA
158
DQ30
198
VSS
239
SA0
VSS
120
SCL
159
DQ31
199
DQ36
240
SA1
40
DQ27
80
41
VSS
81
DQ32
160
VSS
200
DQ37
DQ33
161
NC
201
VSS
Note: 1. NC = No Connect.
2. , ODT1 and CKE1 (Pins 76, 77 and 171) are only support in 2GB module type.
REV 1.0
10/2010
3
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Input/Output Functional Description
Symbol
Type
Polarity
Function
CK0, CK1, CK2
(SSTL)
The positive line of the differential pair of system clock inputs which drives the input to
Positive
the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the
Edge
rising edge of their associated clocks.
, , 
(SSTL)
Negative The negative line of the differential pair of system clock inputs which drives the input to
Edge the on-DIMM PLL.
CKE0, CKE1
(SSTL)
Active
High
Activates the SDRAM CK signal when high and deactivates the CK signal when low. By
deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh
mode. CKE1 apply on 2GB UDIMM only.
, 
(SSTL)
Active
Low
Enables the associated SDRAM command decoder when low and disables the
command decoder when high. When the command decoder is disabled, new commands
are ignored but previous operations continue.  apply on 2GB UDIMM only.
, , 
(SSTL)
Active
Low
When sampled at the positive rising edge of the clock, , ,  define the
operation to be executed by the SDRAM.
VREF
Supply
Reference voltage for SSTL-18 inputs
VDDQ
Supply
Isolated power supply for the DDR SDRAM output buffers to provide improved noise
immunity
ODT0, ODT1
Input
Active
High
BA0 – BA2
(SSTL)
-
Selects which SDRAM bank is to be active.
During a Bank Activate command cycle, A0-A13 defines the row address (RA0-RA13)
when sampled at the rising clock edge.
During a Read or Write command cycle, A0-A9 defines the column address (CA0-CA9)
when sampled at the rising clock edge. In addition to the column address, AP is used to
invoke “Autoprecharge” operation at the end of the Burst Read or Write cycle. If AP is
high, Autoprecharge’s selected and BA0/BA1 defines the bank to be precharged. If AP is
low, autoprecharge is disabled. During a Precharge command cycle, AP is used in
conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks
will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are
used to define which bank to pre-charge.
A0 - A9
A10/AP
A11 - A13
(SSTL)
-
DQ0 – DQ63
(SSTL)
Active
High
VDD, VSS
Supply
DQS0 – DQS8
 – 
(SSTL)
DM0 – DM8
Input
On-Die Termination control signals. ODT1 apply on 2GB UDIMM only.
Data and Check Bit Input /Output pins.
Power and ground for the DDR2 SDRAM input buffers and core logic
Negative
and
Data strobe for input and output data
Positive
Edge
Active
High
The data write masks, associated with one data byte. In Write mode, DM operates as a
byte mask by allowing input data to be written if it is low but blocks the write operation if it
is high. In Read mode, DM lines have no effect. DM8 is associated with check bits
CB0-CB7, and is not used on x64 modules.
SA0 – SA2
-
Address inputs. Connected to either VDD or VSS on the system board to configure the
Serial Presence Detect EEPROM address.
SDA
-
This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor
must be connected from the SDA bus line to V DD to act as a pull-up.
SCL
-
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be
connected from the SCL bus time to V DD to act as a pull-up.
V DDSPD
REV 1.0
10/2010
Supply
Serial EEPROM positive power supply.
4
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Functional Block Diagram (1GB, 1 Rank, 128Mx8 DDR2 SDRAMs)
CS 0
DQS 0
DQS4
DQS0
DM 0
DQS4
DM 4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D0
DQS 1
DQS5
DQS 1
DM1
DQS 5
DM5
DQ8
DQ 9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
DQ 40
DQ 41
DQ 42
DQ 43
DQ 44
DQ 45
DQ 46
DQ 47
D1
DQS2
DQS6
DQS 2
DM 2
DQS6
DM 6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D2
DQS 3
DQS 7
DQS 3
DM 3
DQS 7
DM 7
DQ 24
DQ 25
DQ 26
DQ 27
DQ 28
DQ 29
DQ 30
DQ 31
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS
DQS
D4
DQS DQS
D5
DQS DQS
D6
DQS
DQS
D7
Serial PD
SCL
WP A0
SA0
BA0- BA2
A0 - A13
RAS
CAS
WE
CKE0
ODT0
REV 1.0
10/2010
BA0- BA2: SDRAMs D 0-D7
A0 - A13: SDRAMs D 0-D7
RAS : SDRAMs D 0-D7
CAS : SDRAMs D 0-D7
WE : SDRAMs D 0-D7
CKE : SDRAMs D 0-D7
ODT : SDRAMs D 0-D7
VDDSPD
A1
A2
SA1
SA2
SDA
SPD
VDD /VDDQ
D0 - D 7
V REF
D0 - D 7
VSS
D0 - D 7
5
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Functional Block Diagram (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
CS 1
CS 0
DQS0
DQS 4
DQS 0
DM 0
DQS 4
DM 4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D0
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
D8
DQS1
DQS5
DQS 1
DM1
DQS 5
DM 5
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS
DQS DQS
D1
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
D9
DQS2
DQS 6
DQS 2
DM 2
DQS 6
DM 6
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS
DQS DQS
D2
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
D 10
DQS3
DQS7
DQS3
DM 3
DQS 7
DM 7
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
BA0 -BA2
A0-A13
RAS
CAS
WE
CKE0
CKE1
ODT0
ODT1
REV 1.0
10/2010
DQS DQS
D3
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
BA0 - BA2 : SDRAMs D 0 -D15
A0 - A13 : SDRAMs D 0-D15
RAS : SDRAMs D 0-D15
CAS : SDRAMs D 0-D15
WE : SDRAMs D 0-D15
CKE : SDRAMs D 0-D7
CKE : SDRAMs D 8-D15
ODT : SDRAMs D 0-D7
ODT : SDRAMs D 8-D15
CS
DQS DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
D 11
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
D4
SA0
DQS DQS
D5
DM CS
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
DQS DQS
CS
Serial PD
D6
D7
V DDSPD
SCL
WP A0
DQS DQS
A1
A2
SA1
SA2
SDA
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D12
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
CS
DQS DQS
D13
DQS DQS
D 14
DQS DQS
D 15
SPD
VDD /VDDQ
D 0- D 15
V REF
VSS
D 0- D 15
D 0- D 15
6
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Serial Presence Detect (1GB – 1 Rank, DDR2 SDRAMs)
Serial Presence Detect [1GB –1 Rank, DDR2 SDRAMs]
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46-61
62
63
64-71
72
73-91
92-255
REV 1.0
10/2010
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks, Package, and Height
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time (tac) from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes:  Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=4
Maximum Data Access Time from Clock at CL=4
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active delay (tRRD)
Minimum  to  delay (tRCD)
Minimum Active to Precharge Time (tRAS)
Module Rank Density
Address and Command Setup Time Before Clock (tIS)
Address and Command Hold Time After Clock (tIH)
Data Input Setup Time Before Clock (tDS)
Data Input Hold Time After Clock (tDH)
Write Recovery Time (tWR)
Internal Write to Read Command delay (tWTR)
Internal Read to Precharge delay (tRTP)
Reserved
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
Min. Auto Refresh Command Cycle Time (tRFC)
Maximum Clock Cycle Time (tCK)
Max. DQS-DQ Skew Factor (tQHS)
Read Data Hold Skew Factor (tQHS)
Reserved
SPD Reversion
Checksum for Byte 0-62
Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Part number
Reserved
SPD Data Entry (Hex.)
-AC
80
08
08
0E
0A
60
40
00
05
25
40
00
82
08
00
00
0C
08
38
01
02
00
03
3D
50
50
60
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
36
39
7F
80
14
1E
-13
F9
-00
---
7
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Serial Presence Detect (2GB – 2 Ranks, DDR2 SDRAMs)
Serial Presence Detect [2GB – 2 Ranks, DDR2 SDRAMs]
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46-61
62
63
64-71
72
73-91
92-255
REV 1.0
10/2010
Description
Number of Serial PD Bytes Written during Production
Total Number of Bytes in Serial PD device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on Assembly
Number of DIMM Ranks, Package, and Height
Data Width of Assembly
Reserved
Voltage Interface Level of this Assembly
DDR2 SDRAM Device Cycle Time at CL=5
DDR2 SDRAM Device Access Time (tac) from Clock at CL=5
DIMM Configuration Type
Refresh Rate/Type
Primary DDR2 SDRAM Width
Error Checking DDR2 SDRAM Device Width
Reserved
DDR2 SDRAM Device Attributes: Burst Length Supported
DDR2 SDRAM Device Attributes: Number of Device Banks
DDR2 SDRAM Device Attributes:  Latencies Supported
DIMM Mechanical Characteristics
DDR2 SDRAM DIMM Type Information
DDR2 SDRAM Module Attributes
DDR2 SDRAM Device Attributes: General
Minimum Clock Cycle at CL=4
Maximum Data Access Time from Clock at CL=4
Minimum Clock Cycle Time at CL=3
Maximum Data Access Time from Clock at CL=3
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active delay (tRRD)
Minimum  to  delay (tRCD)
Minimum Active to Precharge Time (tRAS)
Module Rank Density
Address and Command Setup Time Before Clock (tIS)
Address and Command Hold Time After Clock (tIH)
Data Input Setup Time Before Clock (tDS)
Data Input Hold Time After Clock (tDH)
Write Recovery Time (tWR)
Internal Write to Read Command delay (tWTR)
Internal Read to Precharge delay (tRTP)
Reserved
Extension of Byte 41 tRC and Byte 42 tRFC
Minimum Core Cycle Time (tRC)
Min. Auto Refresh Command Cycle Time (tRFC)
Maximum Clock Cycle Time (tCK)
Max. DQS-DQ Skew Factor (tQHS)
Read Data Hold Skew Factor (tQHS)
Reserved
SPD Reversion
Checksum for Byte 0-62
Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Part number
Reserved
SPD Data Entry (Hex.)
-AC
80
08
08
0E
0A
61
40
00
05
25
40
00
82
08
00
00
0C
08
38
01
02
00
03
3D
50
50
60
32
1E
32
2D
01
17
25
05
12
3C
1E
1E
00
36
39
7F
80
14
1E
-13
FA
-00
---
8
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Absolute Maximum Ratings
Symbol
Rating
Units
Voltage on any pin relative to Vss
-0.5 to 2.3
V
VDDQ
Voltage on VDDQ supply relative to Vss
-0.5 to 2.3
V
VDDQL
Voltage on VDDQL supply relative to Vss
-0.5 to 2.3
V
Voltage on VDD supply relative to Vss
-1.0 to +2.3
V
VIN, VOUT
VDD
Parameter
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is stress
rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DC Operating Conditions
Symbol
Parameter
TCASE
Operating Temperature (Ambient)
TSTG
Storage Temperature (Plastic)
IL
Short Circuit Output Current
Rating
Units
Note
0 to 95
°C
1,2,3
-55 to 100
°C
-5 to 5
Μa
Note:
1. Case temperature is measured at top and center side of any DRAMs.
2. tCASE > 85°C  tREFI = 3.9 μs
3. All DRAM specification only support 0°C < tCASE < 85°C
DC Electrical Characteristics and Operating Conditions
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics)
Symbol
VDD
Parameter
Min
Max
Units
Notes
Supply Voltage
1.7
1.9
V
1
VDDQ
Supply Voltage for Output
1.7
1.9
V
1, 3
VDDL
Supply Voltage for VDDQL
1.7
1.9
V
3
VREF
Input Reference Voltage
0.49VDDQ
0.51VDDQ
Mv
2
4
Termination Voltage
VREF – 0.04
VREF + 0.04
V
VIH (DC)
Input High (Logic1) Voltage
VREF + 0.125
VDDQ + 0.3
V
VIL (DC)
Input Low (Logic0) Voltage
-0.3
VREF – 0.125
V
VTT
Note:
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same.
Peak-to-peak noise on VREF may not exceed 2% of the DC value.
3. VDDQ tracks with VDD, VDDL tracks with VDD.
4. VTT of transmitting device track VREF of receiving device.
Environmental Parameters
Symbol
TOPR
HOPR
Parameter
Rating
Units
Note
Module Operating Temperature Range (ambient)
0 to 55
°C
3
Operating Humidity (relative)
10 to 90
%
-55 to 100
°C
1
5 to 95
%
1
105 to 69
K Pascal
1,2
TSTG
Storage Temperature (Plastic)
HSTG
Storage Humidity (without condensation)
PBAR
Barometric Pressure (operating & storage)
Note:
1. Stresses greater than those listed may cause permanent damage to the device. This is a tress rating only and device functional
operation at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.
2. Up to 9850 ft.
3. The component maximum case temperature shall not exceed the value specified in the component spec.
REV 1.0
10/2010
9
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.8V ± 0.1V (1GB, 1 Rank, 128Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-6400
Unit
I DD0
Operating Current: one bank; active/precharge; Trc = Trc (MIN); Tck = Tck (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs changing once per clock cycle
616
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; Trc = Trc (MIN); CL=2.5; Tck = Tck
(MIN); IOUT = 0Ma; address and control inputs changing once per clock cycle
748
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE  VIL (MAX);
Tck = Tck (MIN)
79
mA
I DD2N
Idle Standby Current: CS  VIH (MIN); all banks idle; CKE  VIH (MIN); Tck = Tck (MIN); address and
control inputs changing once per clock cycle
352
mA
I DD2Q
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE is HIGH; tCK = tCK (MIN); Other
control and address inputs are stable, Data bus inputs are floating.
308
mA
I DD3PF
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to low (Fast
Power-down Exit).
264
mA
I DD3PS
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is LOW; Other control and
address inputs are STABLE, Data bus inputs are floating. MRS A12 bit is set to high (Slow
Power-down Exit).
88
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS  VIH (MIN); CKE  VIH (MIN); Trc = Tras
(MAX); Tck = Tck (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and
control inputs changing once per clock cycle
440
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs
changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; Tck
= Tck (MIN)
1056
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs
changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5;
Tck = Tck (MIN); IOUT = 0Ma
1056
mA
I DD5
Auto-Refresh Current: Trc = Trfc (MIN)
1540
mA
I DD6
Self-Refresh Current: CKE  0.2V
79
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs
randomly changing; 50% of data changing at every transfer; Trc = Trc (min); IOUT = 0Ma.
2200
mA
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
REV 1.0
10/2010
10
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Operating, Standby, and Refresh Currents
TCASE = 0 °C ~ 85 °C; VDDQ = VDD = 1.8V ± 0.1V (2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
Symbol
Parameter/Condition
PC2-6400
Unit
I DD0
Operating Current: one bank; active/precharge; Trc = Trc (MIN); Tck = Tck
(MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
968
mA
I DD1
Operating Current: one bank; active/read/precharge; Burst = 2; Trc = Trc
(MIN); CL=2.5; Tck = Tck (MIN); IOUT = 0Ma; address and control inputs
changing once per clock cycle
1100
mA
I DD2P
Precharge Power-Down Standby Current: all banks idle; power-down
mode; CKE  VIL (MAX); Tck = Tck (MIN)
158
mA
I DD2N
Idle Standby Current: CS  VIH (MIN); all banks idle; CKE  VIH (MIN); Tck
= Tck (MIN); address and control inputs changing once per clock cycle
704
mA
I DD2Q
Precharge Quiet Standby Current: All banks idle;  is HIGH; CKE is
HIGH; tCK = tCK (MIN); Other control and address inputs are stable, Data
bus inputs are floating.
616
mA
I DD3PF
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to low (Fast Power-down Exit).
528
mA
I DD3PS
Active Power-Down Current: All banks open; Tck = Tck (MIN), CKE is
LOW; Other control and address inputs are STABLE, Data bus inputs
are floating. MRS A12 bit is set to high (Slow Power-down Exit).
176
mA
I DD3N
Active Standby Current: one bank; active/precharge; CS  VIH (MIN);
CKE  VIH (MIN); Trc = Tras (MAX); Tck = Tck (MIN); DQ, DM, and DQS
inputs changing twice per clock cycle; address and control inputs
changing once per clock cycle
792
mA
I DD4W
Operating Current: one bank; Burst = 2; writes; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
inputs changing twice per clock cycle; CL=2.5; Tck = Tck (MIN)
1408
mA
I DD4R
Operating Current: one bank; Burst = 2; reads; continuous burst;
address and control inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 2.5; Tck = Tck (MIN); IOUT =
0Ma
1408
mA
I DD5
Auto-Refresh Current: Trc = Trfc (MIN)
1892
mA
I DD6
Self-Refresh Current: CKE  0.2V
158
mA
I DD7
Operating Current: four bank; four bank interleaving with BL = 4,
address and control inputs randomly changing; 50% of data changing at
every transfer; Trc = Trc (min); IOUT = 0Ma.
2552
mA
Note: Module IDD was calculated from component IDD. It may differ from the actual measurement.
REV 1.0
10/2010
11
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 1 of 2)
Symbol
Max.
Tck
Clock Cycle Time (Average)
2500
8000
ps
CK high-level width (Average)
0.48
0.52
Tck
Tcl
CK low-level width (Average)
0.48
0.52
Tck
WL
Write command to DQS associated clock edge
Tdqss
Write command to 1st DQS latching transition
Tdss
Tdsh
RL-1
Nck
-0.25
0.25
Tck
DQS falling edge to CK setup time (write cycle)
0.2
-
Tck
DQS falling edge hold time from CK (write cycle)
0.2
-
Tck
DQS input low (high) pulse width (write cycle)
0.35
-
Tck
Twpre
Write preamble
0.35
-
Tck
Twpst
Write postamble
0.4
0.6
Tck
Tis
Address and control input setup time
175
-
ps
Tih
Address and control input hold time
250
-
ps
Tipw
Input pulse width
0.6
-
Tck
Tds
DQ and DM input setup time (differential data
strobe)
50
-
ps
Tdh
DQ and DM input hold time(differential data
strobe)
125
-
ps
Tdipw
Tac
Tdqsck
Thz
DQ and DM input pulse width (each input)
0.35
-
Tck
DQ output access time from CK/
-400
400
ps
DQS output access time from CK/
-350
350
ps
Data-out high-impedance time from CK/
Tlz(DQS)
DQS low-impedance time from CK/
Tlz(DQ)
DQ low-impedance time from CK/
Tdqsq
DQS-DQ skew (DQS & associated DQ signals)
Thp
Minimum half clk period for any given cycle;
defined by clk high (Tch) or clk low (Tcl) time
Tqhs
Data hold Skew Factor
Tqh
Data output hold time from DQS
Trpre
-
tACmax
ps
tACmin
tACmax
ps
2tAC min
tAC max
ps
-
200
ps
Min(Tch(abs),
Tcl(abs))
-
ps
-
300
ps
Thp – Tqhs
-
ps
Read preamble
0.9
1.1
Tck
Trpst
Read postamble
0.4
0.6
Tck
Trrd
Active bank A to Active bank B command
7.5
-
ns
Tfaw
Four Activate Window for 1KB page size
products
35
-
ns
Tccd
 to 
2
Twr
Write recovery time without Auto-Precharge
15
-
ns
Tdal
Auto precharge write recovery + precharge time
WR+tnRP
-
Nck
Twtr
Internal write to read command delay
7.5
-
ns
Trtp
Internal read to precharge command delay
7.5
ns
Tcke
CKE minimum pulse width
Txsnr
Exit self refresh to a Non-read command
Txsrd
Exit self refresh to a Read command
Txp
10/2010
Unit
Min.
Tch
Tdqsl,(H)
REV 1.0
PC2-6400
Parameter
Exit precharge power down to any Non- read
command
Nck
3
Nck
Trfc+10
ns
200
Nck
2
-
Nck
12
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
AC Timing Specifications for DDR2 SDRAM Devices Used on Module
(TCASE = 0 °C ~ 85 °C; VDDQ = 1.8V ± 0.1V; VDD = 1.8V ± 0.1V, See AC Characteristics) (Part 2 of 2)
Symbol
Parameter
Txard
Txards
Taond
PC2-6400
Unit
Min.
Max.
Exit active power down to read command
2
-
Exit active power down to read command
8-AL
ODT turn-on delay
2
2
Nck
ns
Nck
Nck
Taon
ODT turn-on
Tac (min)
Tac
Taonpd
ODT turn-on (Power down mode)
Tac (min)
+2
2Tck +
Tac(max)
+1
ns
Taofd
ODT turn-off delay
2.5
2.5
Nck
Tac(max)
+0.6
ns
(max)+0.7
Taof
ODT turn-off
Tac(min)
Taofpd
ODT turn-off (Power down mode)
2.5Tck +
Tac (min)+2 Tac(max)
+1
ns
Tanpd
ODT to power down entry latency
3
Nck
Taxpd
ODT power down exit latency
8
Tmrd
Mode register set command cycle time
2
-
Nck
Tmod
MRS command to ODT update delay
0
12
ns
Toit
OCD drive mode output delay
0
12
ns
tDelay
Minimum time clocks remains ON after CKE
asynchronously drops Low
Tis + Tck +
Tih
-
ns
Trfc
Refresh to active/Refresh command time
127.5
ns
Average Periodic Refresh Interval
(85ºC < TCASE ≤ 95ºC)
3.9
μs
Average Periodic Refresh Interval
(0ºC ≤ TCASE ≤ 85ºC)
7.8
μs
Trefi
-
Nck
Speed Grade Definition
PC2-6400
Symbol
Parameter
Unit
Min
Max
Tras
Row Active Time
45
70,000
ns
Trc
Row Cycle Time
57.5
-
ns
Trcd
RAS to CAS delay
12.5
-
ns
Trp
Row Precharge Time
12.5
-
ns
REV 1.0
10/2010
13
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Package Dimensions
(Raw Card Version: D, 1GB, 1 Rank, 128Mx8 DDR2 SDRAMs)
FRONT
131. 35
5. 171
128. 95
5. 077
Detail A
 2.5
0. 098
Detail B
2.30
0.091
10.0
0.394
17.80
0.700
30.00
1.180
(2X) 4.00
0.157
133. 35
5. 250
BACK
63. 00
2. 480
55. 00
2. 165
SIDE
3.80
0.15
Detail A
2. 50
0. 10
4.00
0.157
3.18 Max
0. 125
5. 00
0. 20
1. 50 +/- 0.1
0. 059 +/- 0. 004
1. 27 +/- 0. 10
0. 050 +/- 0. 004
Detail B
0. 8 +/- 0.5
0. 031 +/- 0. 02
1. 00 Pitch
0.039
Note: All dimensions are typical with tolerances of +/- 0. 15 (0. 006 ) unless otherwise stated
.
Units:Millimeters ( Inches)
REV 1.0
10/2010
14
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Package Dimensions
(Raw Card Version: E, 2GB, 2 Ranks, 128Mx8 DDR2 SDRAMs)
FRONT
131. 35
5. 171
128. 95
5. 077
Detail A
 2.5
0. 098
Detail B
2.30
0.091
10.0
0.394
17.80
0.700
30.00
1.180
(2X) 4.00
0.157
133. 35
5. 250
BACK
63. 00
2. 480
55. 00
2. 165
SIDE
3.80
0.15
Detail A
2. 50
0. 10
4.00
0.157
4.00 Max
0. 157
5. 00
0. 20
1. 50 +/- 0.1
0.059 +/- 0. 004
1. 27 +/- 0. 10
0. 050 +/- 0. 004
Detail B
0. 8 +/- 0.5
0. 031 +/- 0. 02
1. 00 Pitch
0.039
Note: All dimensions are typical with tolerances of +/- 0. 15 (0. 006 ) unless otherwise stated
.
Units:Millimeters ( Inches)
REV 1.0
10/2010
15
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
M2Y(F)1G64TU88G7(4) B / M2Y(F)2G64TU8HG5(4) B
1GB: 128M x 64 / 2GB: 256M x 64
Unbuffered DDR2 SDRAM DIMM
Revision Log
Rev
Date
0.1
01/2010
Preliminary Edition
1.0
10/2010
Official Release
REV 1.0
10/2010
Modification
16
© NANYA TECHNOLOGY CORP.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.