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FEATURES
Ultralow input noise at maximum gain
0.80 nV/√Hz, 3.0 pA/√Hz
2 independent linear-in-dB channels
Absolute gain range per channel programmable
0 dB to 48 dB (preamplifier gain = 14 dB) through 6 dB to
54 dB (preamplifier gain = 20 dB)
±1.0 dB gain accuracy
Bandwidth: 40 MHz (−3 dB)
Input resistance: 300 kΩ
Variable gain scaling: 20 dB/V through 40 dB/V
Stable gain with temperature and supply variations
Single-ended unipolar gain control
Power shutdown at lower end of gain control
Drive ADCs directly
Dual, Ultralow Noise
Variable Gain Amplifier
AD604
FUNCTIONAL BLOCK DIAGRAM
PAOx –DSXx +DSXx VGNx
PAIx
DIFFERENTIAL
ATTENUATOR
R-1.5R
LADDER NETWORK
0dB TO –48.4dB
PROGRAMMABLE
ULTRALOW NOISE
PREAMPLIFIER
G = 14dB TO 20dB
PRECISION PASSIVE
INPUT ATTENUATOR
Figure 1.
GAIN CONTROL
AND SCALING
AFA
FIXED GAIN
AMPLIFIER
34.4dB
APPLICATIONS
Ultrasound and sonar time-gain controls
High performance AGC systems
Signal measurement www.BDTIC.com/ADI
The AD604 is an ultralow noise, very accurate, dual-channel, Preamplifier gains between 5 and 10 (14 dB and 20 dB) provide overall gain ranges per channel of 0 dB through 48 dB and 6 dB linear-in-dB variable gain amplifier (VGA) optimized for timethrough 54 dB. The two channels of the AD604 can be cascaded based variable gain control in ultrasound applications; however, to provide greater levels of gain range by bypassing the preamplifier it supports any application requiring low noise, wide bandwidth, of the second channel. However, in multiple channel systems, variable gain control. Each channel of the AD604 provides a cascading the AD604 with other devices in the AD60x VGA 300 kΩ input resistance and unipolar gain control for ease of family that do not include a preamplifier may provide a more use. User-determined gain ranges, gain scaling (dB/V), and dc efficient solution. The AD604 provides access to the output of level shifting of output further optimize performance. the preamplifier, allowing for external filtering between the
Each channel of the AD604 uses a high performance preamplifier and the differential attenuator stage. preamplifier that provides an input-referred noise voltage of
Note that scale factors up to 40 dB/V are achievable with reduced 0.8 nV/√Hz. The very accurate linear-in-dB response of the accuracy for scales above 30 dB/V. The gain scales linearly in AD604 is achieved with the differential input exponential decibels with control voltages of 0.4 V to 2.4 V with the 20 dB/V amplifier (DSX-AMP) architecture. Each DSX-AMP comprises scale. Below and above this gain control range, the gain begins a variable attenuator of 0 dB to 48.36 dB followed by a high to deviate from the ideal linear-in-dB control law. The gain speed fixed-gain amplifier. The attenuator is a 7-stage control region below 0.1 V is not used for gain control. When R-1.5R ladder network. The attenuation between tap points is the gain control voltage is <50 mV, the amplifier channel is 6.908 dB and 48.36 dB for the ladder network. powered down to 1.9 mA.
The equation for the linear-in-dB gain response is
The AD604 is available in 24-lead SSOP, SOIC, and PDIP
G (dB) = packages and is guaranteed for operation over the −40°C to
(Gain Scaling (dB/V) × VGN (V)) + (Preamp Gain (dB) – 19 dB)
+85°C temperature range.
VREF
OUTx
VOCM
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1996–2008 Analog Devices, Inc. All rights reserved.
AD604
TABLE OF CONTENTS
Applications Information .............................................................. 18
Ultralow Noise AGC Amplifier with 82 dB to 96 dB
Gain Range .................................................................................. 19
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Ultralow Noise, Differential Input-Differential
Output VGA ................................................................................ 21
Revision History ............................................................................... 2
Medical Ultrasound TGC Driving the AD9050, a 10-Bit,
40 MSPS ADC............................................................................. 22
Absolute Maximum Ratings ............................................................ 5
Evaluation Board ............................................................................ 24
ESD Caution .................................................................................. 5
Using the Preamplifier ............................................................... 24
Pin Configuration and Function Descriptions ............................. 6
DSX Input Connections ............................................................ 24
Typical Performance Characteristics ............................................. 7
Preamplifier Gain ....................................................................... 25
Theory of Operation ...................................................................... 13
Outputs ........................................................................................ 25
Preamplifier ................................................................................. 14
DC Operating Conditions ......................................................... 25
Differential Ladder (Attenuator) .............................................. 15
Evaluation Board Artwork and Schematic ............................. 26
AC Coupling ............................................................................... 16
Outline Dimensions ....................................................................... 28
Gain Control Interface ............................................................... 16
Ordering Guide .......................................................................... 29
Active Feedback Amplifier (Fixed-Gain Amp) ...................... 16
REVISION HISTORY
www.BDTIC.com/ADI
Changes to Figure 1 .......................................................................... 1
Changes to Figure 37 ...................................................................... 13
1/04—Rev. 0 to Rev. A
Changes to Specifications .................................................................2
Changes to Absolute Maximum Ratings ........................................3
Changes to Figure 41 ...................................................................... 15 Changes to Ordering Guide .............................................................3
Changes to Figure 1 Caption............................................................5 Changes to Evaluation Board Model Name ................................ 24
Changes to Ordering Guide .......................................................... 29
1/08—Rev. C to Rev. D
Changes to AC Coupling Section ................................................. 16
Changes to Applications Information Section ............................ 18
Changes to An Ultralow Noise AGC Amplifier with 82 dB to
Changes to Figure 11 Caption .........................................................6
Changes to Figure 17 .........................................................................6
Changes to Figure 51 ...................................................................... 17
Updated Outline Dimensions ....................................................... 18
10/96—Revision 0: Initial Version
96 dB Gain Range Section ............................................................. 19
Changes to Figure 55 and Figure 56 ............................................. 24
Changes to Cascaded DSX Section and Outputs Section ......... 25
Changes to Figure 57 to Figure 60 ................................................ 26
Changes to Figure 61 and Table 6 ................................................. 27
Changes to Ordering Guide .......................................................... 29
3/07—Rev. B to Rev. C
Added Evaluation Board Section ................................................. 24
Added Evaluation Board Artwork and Schematics Section ..... 26
Changes to Ordering Guide .......................................................... 29
12/06—Rev. A to Rev. B
Changes to General Description .................................................... 1
Changes to Figure 54 ...................................................................... 23
Changes to Ordering Guide .......................................................... 25
Rev. E | Page 2 of 32
AD604
SPECIFICATIONS
Each amplifier channel at T
A
= 25°C, V
S
= ±5 V, R
S
= 50 Ω, R
L
= 500 Ω, C
L
= 5 pF, V
REF
= 2.50 V (scaling = 20 dB/V), 0 dB to 48 dB gain
Table 1.
Parameter
INPUT CHARACTERISTICS
Preamplifier
Input Resistance
Input Capacitance
Input Bias Current
Peak Input Voltage
Input Voltage Noise
Input Current Noise
Noise Figure
DSX
Input Resistance
Input Capacitance
Peak Input Voltage
Conditions
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
VGN = 2.9 V, R
S
= 0 Ω
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
Independent of gain
R
S
= 50 Ω, f = 10 MHz, VGN = 2.9 V
R
S
= 200 Ω, f = 10 MHz, VGN = 2.9 V
Min Typ
300
8.5
−27
±400
±200
0.8
0.73
3.0
2.3
1.1
175
3.0
2.5 ± 2
Input Voltage Noise
Input Current Noise
Noise Figure
Common-Mode Rejection Ratio
VGN = 2.9 V
VGN = 2.9 V
R
S
= 50 Ω, f = 10 MHz, VGN = 2.9 V
R
S
= 200 Ω, f = 10 MHz, VGN = 2.9 V f = 1 MHz, VGN = 2.65 V
1.8
2.7
8.4
12
−20
Max Unit kΩ pF mA mV mV nV/√Hz nV/√Hz pA/√Hz dB dB
Ω pF
V nV/√Hz pA/√Hz dB dB dB
OUTPUT CHARACTERISTICS
−3 dB Bandwidth
Slew Rate
Output Signal Range
Output Impedance
Output Short-Circuit Current
Harmonic Distortion
HD2
HD3
HD2
HD3
Two-Tone Intermodulation Distortion (IMD)
Third-Order Intercept
1 dB Compression Point
Channel-to-Channel Crosstalk
Group Delay Variation
VOCM Input Resistance
Constant with gain
VGN = 1.5 V, output = 1 V step
R
L
≥ 500 Ω f = 10 MHz
VGN = 1 V, V
OUT
= 1 V p-p f = 1 MHz f = 1 MHz f = 10 MHz f = 10 MHz
VGN = 2.9 V, V
OUT
= 1 V p-p f = 1 MHz f = 10 MHz f = 10 MHz, VGN = 2.65 V, V
OUT
= 1 V p-p, input referred f = 1 MHz, VGN = 2.9 V, output referred
V
OUT
= 1 V p-p, f = 1 MHz,
Channel 1: VGN = 2.65 V, inputs shorted,
Channel 2: VGN = 1.5 V (mid gain)
1 MHz < f < 10 MHz, full gain range
40
170
2.5 ± 1.5
2
±40
−54
−67
−43
−48
−74
−71
−12.5
15 dBm
−30 dB
±2
45 dBc dBc dBc dBc dBc dBc dBm
MHz
V/μs
V
Ω mA ns kΩ
Rev. E | Page 3 of 32
AD604
Parameter
ACCURACY
Absolute Gain Error
0 dB to 3 dB
3 dB to 43 dB
43 dB to 48 dB
Gain Scaling Error
Output Offset Voltage
Output Offset Variation
GAIN CONTROL INTERFACE
Gain Scaling Factor
Gain Range
Input Voltage (VGN) Range
Input Bias Current
Conditions
0.25 V < VGN < 0.400 V
0.400 V < VGN < 2.400 V
2.400 V < VGN < 2.65 V
0.400 V < VGN < 2.400 V
VREF = 2.500 V, VOCM = 2.500 V
VREF = 2.500 V, VOCM = 2.500 V
VREF = 2.5 V, 0.4 V < VGN < 2.4 V
VREF = 1.67 V
Preamplifier gain = 14 dB
Preamplifier gain = 20 dB
20 dB/V, VREF = 2.5 V
19
Min Typ
−1.2 +0.75
−1.0 ±0.3
−3.5 −1.25
±0.25
−50 ±30
30
20
30
0 to 48
6 to 54
0.1 to 2.9
−0.4
21
Max Unit
+3 dB
+1.0 dB
+1.2 dB dB/V
+50 mV
50 mV dB/V dB/V dB dB
V
μA
Input Resistance
Response Time
VREF Input Resistance
POWER SUPPLY
48 dB gain change
2
0.2
10
MΩ
μs kΩ
Specified Operating Range
Power Dissipation
One complete channel
One DSX only
One complete channel
One DSX only
±5
5
220
95
V
V mW mW
Quiescent Supply Current
Powered Down
VPOS, one complete channel
VPOS, one DSX only
VNEG, one preamplifier only
VPOS, VGN < 50 mV, one channel
32
19
−15 −12
1.9
36
23 mA mA mA
3.0 mA
Power-Up Response Time
Power-Down Response Time
VNEG, VGN < 50 mV, one channel
48 dB gain change, V
OUT
= 2 V p-p
−150
0.6
0.4
μA
μs
μs
Rev. E | Page 4 of 32
AD604
ABSOLUTE MAXIMUM RATINGS
Table 2.
Rating
Supply Voltage ±V
S
Pin 17 to Pin 20 (with Pin 16, Pin 22 = 0 V) ±6.5 V
Input Voltages
Pin 1, Pin 2, Pin 11, Pin 12
Pin 4, Pin 9
Pin 5, Pin 8
VPOS/2 ± 2 V continuous
±2 V
VPOS, VNEG
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Pin 6, Pin 7, Pin 13, Pin 14, Pin 23, Pin 24
Internal Power Dissipation
PDIP (N)
SOIC (RW)
VPOS, 0 V
2.2 W
1.7 W
SSOP (RS)
Operating Temperature Range
Storage Temperature Range
1.1 W
−40°C to +85°C
−65°C to +150°C
Lead Temperature, Soldering 60 sec
θ
300°C
AD604AN 105°C/W
AD604AR 73°C/W
AD604ARS 112°C/W
θ
AD604AN 35°C/W www.BDTIC.com/ADI
1 Pin 1, Pin 2, Pin 11 to Pin 14, Pin 23, and Pin 24 are part of a single-supply circuit. The part is likely to suffer damage if any of these pins are accidentally connected to VN.
2 When driven from an external low impedance source.
3 Using MIL-STD-883 test method G43-87 with a 1S (2-layer) test board.
Rev. E | Page 5 of 32
AD604
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
–DSX1
1
+DSX1
2
PAO1
3
FBK1
4
PAI1 5
COM1 6
COM2 7
PAI2 8
FBK2 9
PAO2 10
+DSX2 11
–DSX2 12
AD604
TOP VIEW
(Not to Scale)
20
19
18
17
24
23
22
21
16
15
14
13
VGN1
VREF
OUT1
GND1
VPOS
VNEG
VNEG
VPOS
GND2
OUT2
VOCM
VGN2
Figure 2. Pin Configuration
14
15
16
17
18
19
20
21
22
23
24
4
5
6
7
8
9
10
11
12
13
Table 3. Pin Function Descriptions
Pin No.
1
2
3
Mnemonic
–DSX1
+DSX1
PAO1
Description
Channel 1 Negative Signal Input to DSX1.
Channel 1 Positive Signal Input to DSX1.
Channel 1 Preamplifier Output.
FBK1
PAI1
–DSX2
VGN2
Channel 1 Preamplifier Feedback Pin.
Channel 1 Preamplifier Positive Input.
COM1
COM2
PAI2
FBK2
Channel 1 Signal Ground. When this pin is connected to positive supply, Preamplifier 1 shuts down.
Channel 2 Signal Ground. When this pin is connected to positive supply, Preamplifier 2 shuts down. www.BDTIC.com/ADI
PAO2 Channel 2 Preamplifier Output.
+DSX2 Channel 2 Positive Signal Input to DSX2.
VOCM
OUT2
GND2
VPOS
VNEG
VNEG
VPOS
GND1
OUT1
VREF
VGN1
Channel 2 Negative Signal Input to DSX2.
Channel 2 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive voltage increases gain.
Input to this pin defines the common mode of the output at OUT1 and OUT2.
Channel 2 Signal Output.
Ground.
Positive Supply.
Negative Supply.
Negative Supply.
Positive Supply.
Ground.
Channel 1 Signal Output.
Input to this pin sets gain scaling for both channels to 2.5 V = 20 dB/V and 1.67 V = 30 dB/V.
Channel 1 Gain Control Input and Power-Down Pin. If this pin is grounded, the device is off; otherwise, positive voltage increases gain.
Rev. E | Page 6 of 32
AD604
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G (preamplifier) = 14 dB, VREF = 2.5 V (20 dB/V scaling), f = 1 MHz, R
L
= 500 Ω, C
L
= 5 pF, T
A
= 25°C, and
V
SS
= ±5 V.
50 40.0
40
30
20
10
0
3 CURVES
–40°C,
+25°C,
+85°C
–10
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
2.5
Figure 3. Gain vs. VGN for Three Temperatures
2.9
37.5
35.0
32.5
30.0
27.5
ACTUAL
THEORETICAL
25.0
22.5
20.0
1.25
1.50
1.75
VREF (V)
2.00
Figure 6. Gain Scaling vs. VREF
2.25
2.50
0
–10
20
10
40
30
60
50
G (PREAMP) = +20dB
(+6dB TO +54dB)
G (PREAMP) = +14dB
(0dB TO +48dB)
DSX ONLY
(–14dB TO +34dB)
–20
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
2.5
Figure 4. Gain vs. VGN for Different Preamplifier Gains
2.9
30
20
50
40
10
0
30dB/V
VREF = 1.67V
ACTUAL
20dB/V
VREF = 2.5V
ACTUAL
–10
0.1
0.5
0.9
1.3
VGN (V)
1.7
2.1
2.5
Figure 5. Gain vs. VGN for Different Gain Scalings
2.9
Rev. E | Page 7 of 32
2.0
1.5
0
–0.5
–1.0
–1.5
–2.0
0.2
0.7
1.2
–40°C +25°C
+85°C
1.7
VGN (V)
Figure 7. Gain Error vs. VGN
2.2
2.7
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
FREQ = 1MHz
FREQ = 10MHz
FREQ = 5MHz
–2.0
0.2
0.7
1.2
1.7
2.2
VGN (V)
Figure 8. Gain Error vs. VGN at Different Frequencies
2.7
AD604
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
30dB/V
VREF = 1.67V
20dB/V
VREF = 2.5V
–2.0
0.2
0.7
1.2
1.7
2.2
VGN (V)
Figure 9. Gain Error vs. VGN for Two Gain Scaling Values
2.7
25
N = 50
VGN1 = 1.0V
VGN2 = 1.0V
ΔG(dB) =
G(CH1) – G(CH2)
10
5
20
15
0
–1.0
–0.8
–0.6
–0.4
–0.2
0.1
DELTA GAIN (dB)
0.3
0.5
Figure 10. Gain Match; VGN1 = VGN2 = 1.0 V
0.7
0.9
25
20
N = 50
VGN1 = 2.50V
VGN2 = 2.50V
ΔG(dB) =
G(CH1) – G(CH2)
15
10
5
0
–1.0
–0.8
–0.6
–0.4
–0.2
0.1
DELTA GAIN (dB)
0.3
0.5
Figure 11. Gain Match; VGN1 = VGN2 = 2.50 V
0.7
0.9
10
0
–10
–20
50
40
30
20
VGN = 2.5V
VGN = 1.5V
VGN = 0.5V
VGN = 0.1V
VGN = 2.9V
–30
VGN = 0V
–40
–50
100k 1M
FREQUENCY (Hz)
10M
Figure 12. AC Response for Various Values of VGN
100M
2.55
VOCM = 2.5V
2.54
2.53
2.52
2.51
2.50
–40°C
+25°C
2.47
+85°C
2.46
2.45
0.2
0.7
1.2
1.7
2.2
VGN (V)
Figure 13. Output Offset vs. VGN for Three Temperatures
2.7
210
190
170
150
+85°C
130
+25°C
110
–40°C
90
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
2.5
2.9
Figure 14. Output Referred Noise vs. VGN for Three Temperatures
Rev. E | Page 8 of 32
10
VGN = 2.9V
1
AD604
1000
100
10
1 R
SOURCE
ALONE
0.1
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
Figure 15. Input Referred Noise vs. VGN
2.5
2.9
0.1
1 10 100
R
SOURCE
(Ω)
Figure 18. Input Referred Noise vs. R
SOURCE
900
850
800
VGN = 2.9V
13
12
11
10
16
15
14
600
–40
9
750
700
650
8
7
6 www.BDTIC.com/ADI
4
3
2
1
1 –20 0 20 40 60 80 90 10 100 1k
VGN = 2.9V
10k
TEMPERATURE (°C) R
SOURCE
(Ω)
Figure 16. Input Referred Noise vs. Temperature Figure 19. Noise Figure vs. R
SOURCE
770
VGN = 2.9V
765
760
755
750
745
740
100k 1M
FREQUENCY (Hz)
Figure 17. Input Referred Noise vs. Frequency
10M
15
10
5
0
0
30
25
20
40
35
R
S
= 240Ω
0.4
0.8
1.2
1.6
VGN (V)
2.0
Figure 20. Noise Figure vs. VGN
2.4
2.8
1k
Rev. E | Page 9 of 32
AD604
–40
V
O
= 1V p-p
VGN = 1V
–45
–50
HD2
–55
–60
–65
HD3
–70
100k 1M
FREQUENCY (Hz)
10M
Figure 21. Harmonic Distortion vs. Frequency
100M
–50
–60
–70
–80
–90
–100
–110
–120
–20
–30
–40
V
O
= 1V p-p
VGN = 1V
9.96
9.98
10.00
FREQUENCY (MHz)
10.02
Figure 24. Intermodulation Distortion
10.04
–60
–65
–70
–75
–80
0.5
–45
–50
–55
–30
V
O
= 1V p-p
–35
–40
HD2 (10MHz)
5
0
–5
–10
INPUT
SIGNAL
LIMIT
800mV p-p
10MHz
HD3 (10MHz) –15
1MHz www.BDTIC.com/ADI
HD2 (1MHz)
HD3 (1MHz)
–20
–25
–30
0.9
1.3
1.7
VGN (V)
2.1
Figure 22. Harmonic Distortion vs. VGN
2.5
2.9
–35
0.1
0.5
0.9
1.3
1.7
VGN (V)
2.1
Figure 25. 1 dB Compression vs. VGN
2.5
2.9
–20
–30
–40
–50
–60
–70
R
S
50Ω
DUT
500Ω
HD2 (10MHz)
V
O
= 1V p-p
VGN = 1V
HD3 (10MHz)
HD2 (1MHz)
HD3 (1MHz)
–80
0 50 100 150
R
SOURCE
(Ω)
200
Figure 23. Harmonic Distortion vs. R
SOURCE
250
15
10
25
20
–5
–10
5
0
–15
0.4
f = 1MHz f = 10MHz
V
O
= 1V p-p
0.9
1.4
1.9
2.4
VGN (V)
Figure 26. Third-Order Intercept vs. VGN
2.9
Rev. E | Page 10 of 3 2
2V
V
O
= 2V p-p
VGN = 1.5V
–2V
253ns 100ns/DIV
Figure 27. Large Signal Pulse Response
1.253µs
200
V
O
= 200mV p-p
VGN = 1.5V
TRIG'D
–200
253ns 100ns/DIV
Figure 28. Small Signal Pulse Response
1.253µs
2.9V
100
90
500mV
0V
10
0%
500mV 200ns
Figure 29. Power-Up/Power-Down Response
AD604
2.9V
100
90
500mV
0.1V
10
0%
500mV 100ns
Figure 30. Gain Response
0
–10
VGN1 = 1V
V
OUT1
V
IN2
= 1V p-p
= GND
–20
–30
VGN2 = 2.9V
–40
VGN2 = 2V
VGN2 = 1.5V
VGN2 = 0.1V
–70
100k 1M
FREQUENCY (Hz)
10M 100M
Figure 31. Crosstalk (Channel 1 to Channel 2) vs. Frequency
0
–10
–20
–30
–40
VGN = 2.9V
VGN = 2.5V
VGN = 2V
–50
VGN = 0.1V
–60
100k 1M
FREQUENCY (Hz)
10M 100M
Figure 32. DSX Common-Mode Rejection Ratio vs. Frequency
Rev. E | Page 11 of 32
AD604
1M
100k
10k
1k
100
10
1
1k 10k 100k 1M
FREQUENCY (Hz)
10M
Figure 33. Input Impedance vs. Frequency
100M
27.6
27.4
27.2
27.0
26.8
26.6
26.4
26.2
26.0
25.8
–40 –20 0 20 40
TEMPERATURE (°C)
60
Figure 34. Input Bias Current vs. Temperature
80 90
20
18
16
14
12
15
10
5
30
25
20
40
35
+I
S
–I
S
(AD604) = +I
S
(AD604) = –I
S
(PA) + +I
S
(PA)
(DSX)
DSX (+I
S
)
+I
S
(VGN = 0)
AD604 (+I
PREAMP (±I
S
)
S
)
0
–40 –20 0 20 40
TEMPERATURE (°C)
60 80 90
Figure 35. Supply Current (One Channel) vs. Temperature
VGN = 0.1V
VGN = 2.9V
6
100k 1M
FREQUENCY (Hz)
10M
Figure 36. Group Delay vs. Frequency
100M
Rev. E | Page 12 of 32
AD604
THEORY OF OPERATION
The AD604 is a dual-channel VGA with an ultralow noise
preamplifier. Figure 37 shows the simplified block diagram of
one channel. Each identical channel consists of a preamplifier with gain setting resistors (R5, R6, and R7) and a single-supply
X-AMP® (hereafter called DSX, differential single-supply X-AMP) made up of the following:
• A precision passive attenuator (differential ladder).
• A gain control block.
• A VOCM buffer with supply splitting resistors
(R3 and R4).
• An active feedback amplifier (AFA) with gain setting resistors (R1 and R2). To understand the active-feedback amplifier topology, refer to the AD830 data sheet. The
AD830 is a practical implementation of the idea. example, if the preamp gain is set to 14 dB and VREF is set to
2.50 V (to establish a gain scaling of 20 dB/V), the gain equation simplifies to
G (dB) = 20 (dB/V) × VGN (V) – 5 dB
The desired gain can then be achieved by setting the unipolar gain control (VGN) to a voltage within its nominal operating range of 0.25 V to 2.65 V (for 20 dB/V gain scaling). The gain is monotonic for a complete gain control voltage range of 0.1 V to
2.9 V. Maximum gain can be achieved at a VGN of 2.9 V.
The preamplifier is powered by a ±5 V supply, while the DSX uses a single +5 V supply. The linear-in-dB gain response of the
AD604 can generally be described by
The inputs VREF and VOCM are common to both channels.
They are decoupled to ground, minimizing interchannel crosstalk. For the highest gain scaling accuracy, VREF should have an external low impedance voltage source. For low accuracy
20 dB/V applications, the VREF input can be decoupled with a capacitor to ground. In this mode, the gain scaling is determined by the midpoint between VPOS and GND; therefore, care should be taken to control the supply voltage to 5 V. The input resistance looking into the VREF pin is 10 kΩ ± 20%.
The DSX portion of the AD604 is a single-supply circuit, and G (dB) = Gain Scaling (dB/V) × Gain Control (V) +
(Preamp Gain (dB) − 19 dB) (1)
Each channel provides between 0 dB to 48.4 dB and 6 dB to 54.4 dB of gain, depending on the user-determined preamplifier www.BDTIC.com/ADI of the preamplifier is typically either 14 dB or 20 dB but can be of this portion of the circuit. The VOCM pin only needs an external decoupling capacitor to ground to center the midpoint between the supply voltages (5 V, GND); however, the VOCM can be adjusted to other voltage levels if the dc common-mode level of the output is important to the user (for example, see the
section entitled Medical Ultrasound TGC Driving the AD9050,
set to intermediate values by a single external resistor (see the
a 10-Bit, 40 MSPS ADC). The input resistance looking into the
Preamplifier section for details). The gain of the DSX can vary
VOCM pin is 45 kΩ ± 20%. from −14 dB to +34.4 dB, as determined by the gain control voltage (VGN). The VREF input establishes the gain scaling; the VOCM pin is used to establish the dc level of the midpoint the useful gain scaling range is between 20 dB/V and 40 dB/V for a VREF voltage of 2.5 V and 1.25 V, respectively. For
VREF
VGNx
PAIx
VOCM
EXT.
C3
GAIN
CONTROL
PAOx C1 +DSXx
R7
40Ω
R5
32Ω
VPOS
R3
200kΩ
R6
8Ω
COMx
EXT.
FBKx C2 –DSXx
175Ω
175Ω
DIFFERENTIAL
ATTENUATOR
R2
20Ω
R4
200kΩ
G1
DISTRIBUTED G
M
G2
Ao
R1
820Ω
OUTx
Figure 37. Simplified Block Diagram of a Single Channel of the AD604
Rev. E | Page 13 of 32
AD604
PREAMPLIFIER
preamplifier to be 17.7 dB. The −3 dB small signal bandwidth of one complete channel of the AD604 (preamplifier and DSX) is
The input capability of the following single-supply DSX (2.5 ± 2 V for a +5 V supply) limits the maximum input voltage of the
40 MHz and is independent of gain. preamplifier to ±400 mV for the 14 dB gain configuration or
±200 mV for the 20 dB gain configuration.
The preamplifier gain can be programmed to 14 dB or 20 dB by either shorting the FBK1 node to PAO1 (14 dB) or by leaving the FBK1 node open (20 dB). These two gain settings are very accurate because they are set by the ratio of the on-chip resistors.
Any intermediate gain can be achieved by connecting the appropriate resistor value between PAO1 and FBK1 according to Equation 2 and Equation 3.
G
=
V
OUT
V
IN
=
(
R 7 || R
EXT
)
R 6
+
R
EXT
=
[
R 6
R 7
−
×
G
(
R 6
−
×
(
R 5
G
+
R 5
+
R 6
20
19
17
R 6
) ]
R 5
+
×
R 7
R 6
)
) 16
(3)
15
Because the internal resistors have an absolute tolerance of ±20%, the gain can be in error by as much as 0.33 dB when R
EXT
is 30 Ω, where it is assumed that R
EXT
is exact.
Figure 38 shows how the preamplifier is set to gains of 14 dB,
To achieve optimum specifications, power and ground management are critical to the AD604. Large dynamic currents result because of the low resistances needed for the desired noise performance. Most of the difficulty is with the very low gain setting resistors of the preamplifier that allow for a total input referred noise, including the DSX, as low as 0.8 nV/√Hz. The consequently large dynamic currents have to be carefully handled to maintain performance even at large signal levels.
14
13
12
11
V
IN
IN
50Ω
8Ω 32Ω
40Ω
40Ω
SHORT
150Ω
R
EXT
OPEN
17.5 dB, and 20 dB. The gain range of a single channel of the 10
100k 1M 10M
FREQUENCY (Hz)
AD604 is 0 dB to 48 dB when the preamplifier is set to 14 dB www.BDTIC.com/ADI
100M
Figure 39. AC Response for Preamplifier Gains of 14 dB, 17.5 dB, and 20 dB
The preamplifier uses a dual ±5 V supply to accommodate large dynamic currents and a ground referenced input. The preamplifier
PAI1 output is also ground referenced and requires a common-mode
PAO1 level shift into the single-supply DSX. The two external coupling
R7
40Ω R6
8Ω
R5
32Ω
capacitors (C1 and C2 in Figure 37) connected to the PAO1 and
COM1 FBK1 +DSXx, and –DSXx, nodes and ground, respectively, perform
this function (see the AC Coupling section). In addition, they
eliminate any offset that would otherwise be introduced by the a. PREAMP GAIN = 14dB
PAI1
COM1
R6
8Ω
R5
32Ω
R7
40Ω
PAO1
FBK1
R10
40Ω preamplifier. It should be noted that an offset of 1 mV at the input of the DSX is amplified by 34.4 dB (× 52.5) when the gain control voltage is at its maximum; this equates to 52.5 mV at the output. AC coupling is consequently required to keep the offset from degrading the output signal range.
PAI1 b. PREAMP GAIN = 17.5dB
R6
8Ω
R5
32Ω
R7
40Ω
PAO1
The gain-setting preamplifier feedback resistors are small enough (8 Ω and 32 Ω) that even an additional 1 Ω in the ground connection at Pin COM1 (the input common-mode reference) seriously degrades gain accuracy and noise performance.
This node is sensitive, and careful attention is necessary to
COM1 FBK1 c. PREAMP GAIN = 20dB minimize the ground impedance. All connections to the COM1 node should be as short as possible.
Figure 38. Preamplifier Gain Programmability
For a preamplifier gain of 14 dB, the −3 dB small signal bandwidth of the preamplifier is 130 MHz. When the gain is at its maximum
of 20 dB, the bandwidth is reduced by half to 65 MHz. Figure 39
shows the ac response for the three preamp gains shown in
The preamplifier, including the gain setting resistors, has a noise performance of 0.71 nV/√Hz and 3 pA/√Hz. Note that a significant portion of the total input referred voltage noise is due to the feedback resistors. The equivalent noise resistance presented by R5 and R6 in parallel is nominally 6.4 Ω, which
Figure 38. Note that the gain for an R
EXT
of 40 Ω should be
17.5 dB, but the mismatch between the internal resistors and contributes 0.33 nV/√Hz to the total input referred voltage noise. the external resistor causes the actual gain for this particular
Rev. E | Page 14 of 32
AD604
The larger portion of the input referred voltage noise comes from the amplifier with 0.63 nV/√Hz. The current noise is independent of gain and depends only on the bias current in the input stage of the preamplifier, which is 3 pA/√Hz.
A unique circuit technique is used to interpolate continuously among the tap points, thereby providing continuous attenuation from 0 dB to −48.36 dB. The ladder network, together with the interpolation mechanism, can be considered a voltage-controlled potentiometer.
The preamplifier can drive 40 Ω (the nominal feedback resistors) and the following 175 Ω ladder load of the DSX with low distortion. For example, at 10 MHz and 1 V at the output, the
Because the DSX circuit uses a single voltage power supply, the input biasing is provided by the VOCM buffer driving the MID preamplifier has less than −45 dB of second and third harmonic distortion when driven from a low (25 Ω) source resistance.
In applications that require more than 48 dB of gain range, two
AD604 channels can be cascaded. Because the preamplifier has a limited input signal range and consumes over half (120 mW)
node (see Figure 41). Without internal biasing, the user would
have to dc bias the inputs externally. If not done carefully, the biasing network can introduce additional noise and offsets. By providing internal biasing, the user is relieved of this task and only needs to ac-couple the signal into the DSX. Note that the of the total power (220 mW), and its ultralow noise is not necessary after the first AD604 channel, a shutdown mechanism that disables only the preamplifier is provided. To shut down the preamplifier, connect the COM1 pin and/or COM2 pin to the positive supply; the DSX is unaffected. For additional details,
refer to the Applications Information section.
input to the DSX is still fully differential if driven differentially; that is, Pin +DSXx and Pin −DSXx see the same signal but with
opposite polarity (see the Ultralow Noise, Differential Input-
Differential Output VGA section).
What changes is the load seen by the driver; it is 175 Ω when each input is driven single-ended but 350 Ω when driven differentially. This is easily explained by thinking of the ladder
1 –DSX1 VGN1 24 network as two 175 Ω resistors connected back-to-back with
2 +DSX1 VREF 23 the middle node, MID, being biased by the VOCM buffer. A
3 PAO1
–DSX2
OUT1
VGN2
22 differential signal applied between the +DSXx and −DSXx
4 FBK1
+DSX2
GND1
VOCM
21
PAI1
COM1
AD604
COM2
PAI2
PAO2
17 nodes results in zero current into the MID node, but a single-
5
6
7
9
10
20
19
18 www.BDTIC.com/ADI
16
15 ended signal applied to either input, +DSXx or –DSXx, while the other input is ac-grounded causes the current delivered by the source to flow into the VOCM buffer via the MID node.
FBK2
VPOS
VNEG
VNEG
VPOS
GND2
OUT2
The ladder resistor value of 175 Ω provides the optimum balance between the load driving capability of the preamplifier
11 14 and the noise contribution of the resistors. An advantage of the
12 13
X-AMP architecture is that the output referred noise is constant
Figure 40. Shutdown of Preamplifiers Only
vs. gain over most of the gain range. Figure 41 shows that the
tap resistance is equal for all taps after only a few taps away
DIFFERENTIAL LADDER (ATTENUATOR)
The attenuator before the fixed-gain amplifier of the DSX is realized by a differential 7-stage R-1.5R resistive ladder network with an untrimmed input resistance of 175 Ω single-ended or
350 Ω differential. The signal applied at the input of the ladder network is attenuated by 6.908 dB per tap; thus, the attenuation at the first tap is 0 dB, at the second, 13.816 dB, and so on, all from the inputs. The resistance seen looking into each tap is
54.4 Ω, which makes 0.95 nV/√Hz of Johnson noise spectral density. Because there are two attenuators, the overall noise contribution of the ladder network is √2 times 0.95 nV/√Hz or 1.34 nV/√Hz, a large fraction of the total DSX noise. The balance of the DSX circuit components contributes another
1.2 nV/√Hz, which together with the attenuator produces
1.8 nV/√Hz of total DSX input referred noise. the way to the last tap where the attenuation is 48.356 dB
R R R R R R
+DSXx
R –6.908dB
–13.82dB
–20.72dB
–27.63dB
–34.54dB
–41.45dB
–48.36dB
1.5R
MID
R
–DSXx
NOTES
1. R = 96Ω
2. 1.5R = 144Ω
1.5R
R
1.5R
1.5R
R
1.5R
1.5R
R
1.5R
1.5R
R
1.5R
1.5R
R
1.5R
1.5R
R
1.5R
1.5R
175Ω
175Ω
Figure 41. R-1.5R Dual Ladder Network
Rev. E | Page 15 of 32
AD604
From these equations, it can be seen that all gain curves intercept at
AC COUPLING
the same −5 dB point; this intercept is +6 dB higher (+1 dB) if
The DSX portion of the AD604 is a single-supply circuit and, the preamplifier gain is set to +20 dB or +14 dB lower (−19 dB) therefore, its inputs need to be ac-coupled to accommodate if the preamplifier is not used at all. Outside the central linear
ground-based signals. External Capacitors C1 and C2 in Figure 37
range, the gain starts to deviate from the ideal control law but level shift the ground referenced preamplifier output from still provides another 8.4 dB of range. For a given gain scaling, ground to the dc value established by VOCM (nominal 2.5 V).
V
REF
can be calculated as shown in Equation 7.
C1 and C2, together with the 175 Ω looking into each of the
DSX inputs (+DSXx and −DSXx), act as high-pass filters with 2 .
500 V
×
20 dB/V corner frequencies depending on the values chosen for C1 and
VREF
=
(7)
Gain Scale
C2. As an example, for values of 0.1 μF at C1 and C2, combined
Usable gain control voltage ranges are 0.1 V to 2.9 V for the with the 175 Ω input resistance at each side of the differential
20 dB/V scale and 0.1 V to 1.45 V for the 40 dB/V scale. VGN ladder of the DSX, the −3 dB high-pass corner is 9.1 kHz. voltages of less than 0.1 V are not used for gain control because
If the AD604 output needs to be ground referenced, another below 50 mV the channel (preamplifier and DSX) is powered ac coupling capacitor is required for level shifting. This down. This can be used to conserve power and, at the same capacitor also eliminates any dc offsets contributed by the DSX. time, to gate off the signal. The supply current for a powered-
With a nominal load of 500 Ω and a 0.1 μF coupling capacitor, down channel is 1.9 mA; the response time to power the device this adds a high-pass filter with −3 dB corner frequency at about on or off is less than 1 μs.
3.2 kHz.
ACTIVE FEEDBACK AMPLIFIER (FIXED-GAIN AMP)
The choice for all three of these coupling capacitors depends on
To achieve single-supply operation and a fully differential input the application. They should allow the signals of interest to pass to the DSX, an active feedback amplifier (AFA) is used. The unattenuated while, at the same time, they can be used to limit
AFA is an op amp with two g m
stages; one of the active stages is the low frequency noise in the system.
GAIN CONTROL INTERFACE
The gain control interface provides an input resistance of www.BDTIC.com/ADI
20 dB/V to 40 dB/V for VREF input voltages of 2.5 V to 1.25 V, respectively. The gain scales linearly in decibels for the center 40 used in the feedback path (therefore the name), while the other is used as a differential input. Note that the differential input is an open-loop g m
stage that requires it to be highly linear over the expected input signal range. In this design, the g m
stage that senses the voltages on the attenuator is a distributed one; for example, there are as many g m
stages as there are taps on the dB of gain range, which for VGN is equal to 0.4 V to 2.4 V for ladder network. Only a few of them are on at any one time,
the 20 dB/V scale and 0.2 V to 1.2 V for the 40 dB/V scale. Figure
depending on the gain control voltage.
42 shows the ideal gain curves for a nominal preamplifier gain
The AFA makes a differential input structure possible because of 14 dB, which are described by the following equations: one of its inputs (G1) is fully differential; this input is made up
G (20 dB/V) = 20 × VGN – 5, VREF = 2.500 V (4) of a distributed g m
stage. The second input (G2) is used for feedback. The output of G1 is some function of the voltages
G (20 dB/V) = 30 × VGN – 5, VREF = 1.666 V (5)
G (20 dB/V) = 40 × VGN – 5, VREF = 1.250 V
50
45
40
(6) sensed on the attenuator taps, which is applied to a high-gain amplifier (A0). Because of negative feedback, the differential input to the high-gain amplifier has to be zero; this in turn implies that the differential input voltage to G2 times g m2
(the transconductance of G2) has to be equal to the differential input voltage to G1 times g m1
(the transconductance of G1).
35
40dB/V 30dB/V 20dB/V
Therefore, the overall gain function of the AFA is
30
25
20
15
LINEAR-IN-dB RANGE
OF AD604 WITH
PREAMPLIFIER
SET TO 14dB
V
OUT
V
ATTEN
= g m1 g m2
×
R 1
+
R 2
R 2
(8)
10
5
0 where:
V
OUT
is the output voltage.
V
ATTEN
is the effective voltage sensed on the attenuator.
0.5
1.0
1.5
2.0
GAIN CONTROL VOLTAGE (VGN)
2.5
3.0
(R1 + R2)/R2 = 42 g m1
/g m2
= 1.25
–5
Figure 42. Ideal Gain Curves vs. VGN
The overall gain is thus 52.5 (34.4 dB).
Rev. E | Page 16 of 32
The AFA offers the following additional features:
• The ability to invert the signal by switching the positive and negative inputs to the ladder network
• The possibility of using DSX1 input as a second signal input
• Fully differential high-impedance inputs when both preamplifiers are used with one DSX (the other DSX could still be used alone)
• Independent control of the DSX common-mode voltage
AD604
Under normal operating conditions, it is best to connect a decoupling capacitor to VOCM, in which case, the commonmode voltage of the DSX is half the supply voltage, which allows for maximum signal swing. Nevertheless, the common-mode voltage can be shifted up or down by directly applying a voltage to VOCM. It can also be used as another signal input, the only limitation being the rather low slew rate of the VOCM buffer.
If the dc level of the output signal is not critical, another coupling capacitor is normally used at the output of the DSX; again, this is done for level shifting and to eliminate any dc offsets contributed
by the DSX (see the AC Coupling section).
www.BDTIC.com/ADI
Rev. E | Page 17 of 32
AD604
APPLICATIONS INFORMATION
The basic circuit in Figure 43 shows the connections for one
channel of the AD604. The signal is applied at Pin 5. RGN is normally 0, in which case the preamplifier is set to a gain of 5
(14 dB). When FBK1 is left open, the preamplifier is set to a gain of 10 (20 dB), and the gain range shifts up by 6 dB. The ac coupling capacitors before −DSX1 and +DSX1 should be selected according to the required lower cutoff frequency. In this example, the 0.1 μF capacitors, together with the 175 Ω seen looking into each of the DSXx input pins, provide a −3 dB high-pass corner of about 9.1 kHz. The upper cutoff frequency is determined by the bandwidth of the channel, which is 40 MHz. Note that the signal can be simply inverted by connecting the output of the preamplifier to −DSX1 instead of +DSX1; this is due to the fully differential input of the DSX.
0.1µF
VGN
0.1µF
RGN
V
IN
1
2
3
4
5
–DSX1
+DSX1
PAO1
VGN1 24
VREF 23
OUT1 22
FBK1
AD604
PAI1
GND1
VPOS
21
20
6
7
8
9
10
COM1
COM2
PAI2
FBK2
PAO2
11 +DSX2
–DSX2
VNEG 19
VNEG 18
VPOS 17
GND2 16
OUT2 15
VOCM 14
VGN2 13
0.1µF
+2.5V
R
L
500Ω
0.1µF
OUT
+5V
–5V
Figure 43. Basic Connections for a Single Channel
In Figure 43, the output is ac-coupled for optimum performance.
For dc coupling, as shown in Figure 52, the capacitor can be
eliminated if VOCM is biased at the same 3.3 V common-mode voltage as the analog-to-digital converter, AD9050 .
VREF requires a voltage of 1.25 V to 2.5 V, with between 40 dB/V and 20 dB/V gain scaling, respectively. Voltage VGN controls the gain; its nominal operating range is from 0.25 V to 2.65 V for 20 dB/V gain scaling and 0.125 V to 1.325 V for 40 dB/V scaling. When VGNx is grounded, the channel powers down and disables its output.
COM1 is the main signal ground for the preamplifier and needs to be connected with as short a connection as possible to the input ground. Because the internal feedback resistors of the preamplifier are very small for noise reasons (8 Ω and 32 Ω nominally), it is of utmost importance to keep the resistance in this connection to a minimum. Furthermore, excessive inductance in this connection can lead to oscillations.
Because of the ultralow noise and wide bandwidth of the
AD604, large dynamic currents flow to and from the power supply. To ensure the stability of the part, careful attention to supply decoupling is required. A large storage capacitor in parallel with a smaller high-frequency capacitor connected at the supply pins, together with a ferrite bead coming from the supply, should be used to ensure high-frequency stability.
To provide for additional flexibility, COM1 can be used to disable the preamplifier. When COM1 is connected to VP, the preamplifier is off, yet the DSX portion can be used independently.
This may be of value when cascading the two DSX stages in the
AD604. In this case, the first DSX output signal with respect to noise is large and using the second preamplifier at this point
would waste power (see Figure 44).
Rev. E | Page 18 of 32
AD604
C2
0.1µF
C1
0.1µF
1
–DSX1 VGN1 24
2
3
+DSX1 VREF
AD604
PAO1 OUT1
23
22
4 FBK1 GND1 21
VREF
VSET (<0V)
VIN
(MAX
800mV p-p)
VPOS 20 +5V R8
2kΩ
C11
1µF
R1
49.9Ω
5 PAI1
6 COM1 VNEG 19 –5V
– (V1) 2
1V
7 COM2 VNEG 18 –5V
C8
0.33µF
R4
2kΩ
+5V
LOW-
PASS
FILTER
7 6
X2 VP
AD835
Y2 VN
2 3
–5V
R5
2kΩ
Z
4
5
W
R6
2kΩ
R7
1kΩ
C10
1µF
1
OFFS
NULL
2
3
4 –V
S
NC 8
+V
S
AD711
OUT
7
6
OFFS
NULL
5
– (A) 2
2
IF V1 = A × cos (wt)
+5V
8 PAI2 VPOS 17 +5V
V1 = V
IN
× G
9 FBK2 GND2 16
C7
0.33µF
C12
0.1µF
C3
0.1µF
10
11
12
PAO2
+DSX2
–DSX2
OUT2
VOCM
VGN2
15
14
13
C7
0.1µF C6
0.56µF
R2
453Ω
R3
1kΩ
C4
0.1µF
RF OUT
FB
FB
+5V
–5V
C13
0.1µF
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
C9
0.33µF
8
X1
Y1
1
–5V
Figure 44. AGC Amplifier with 82 dB of Gain Range
ULTRALOW NOISE AGC AMPLIFIER WITH 82 dB TO
Figure 44 shows an implementation of an AGC amplifier with
82 dB of gain range using a single AD604. The signal is applied
Figure 45 and Figure 46 show the gain range and gain error for
the AD604 connected as shown in Figure 44. The gain range is
−14 dB to +82 dB; the useful range is 0 dB to +82 dB if the RF output amplitude is controlled to ±400 mV (+2 dBm). The main limitation on the lower end of the signal range is the input to connector VIN and, because the signal source is 50 Ω, a capability of terminating resistor (R1) of 49.9 Ω is added. The signal is then the preamplifier. This limitation can be overcome by adding an amplified by 14 dB (Pin FBK1 shorted to PAO1) through the attenuator in front of the preamplifier, but that would defeat the
Channel 1 preamplifier and is further processed by the Channel 1 advantage of the ultralow noise preamplifier. It should be noted
DSX. Next, the signal is applied directly to the Channel 2 DSX. The that the second preamplifier is not used because its ultralow second preamplifier is powered down by connecting its COM2 pin noise and the associated high-power consumption are overkill
to the positive supply as explained in the Preamplifier section.
after the first DSX stage. It is disabled in this application by connecting the COM2 pin to the positive supply. Nevertheless, C1 and C2 level shift the signal from the preamplifier into the first DSX and, at the same time, eliminate any offset contribution of the preamplifier. C3 and C4 have the same offset cancellation purpose for the second DSX. Each set of capacitors, combined with the 175 Ω input resistance of the corresponding DSX, provides a high-pass filter with a −3 dB corner frequency of about 9.1 kHz. VOCM is decoupled to ground by a 0.1 μF the second preamplifier can be used, if so desired, and the useful gain range increases by 14 dB to encompass 0 dB to
96 dB of gain. For the same +2 dBm output, this allows signals as small as −94 dBm to be measured.
To achieve the highest gains, the input signal must be bandlimited to reduce the noise; this is especially true if the second capacitor, while VREF can be externally provided; in this application, the gain scale is set to 20 dB/V by applying 2.500 V.
Because each DSX amplifier operates from a single 5 V supply, the output is ac-coupled via C6 and C7. The output signal can be monitored at the connector labeled RF OUT. preamplifier is used. If the maximum signal at OUT2 of the AD604 is limited to ±400 mV (+2 dBm), the input signal level at the
AGC threshold is +25 μV rms (−79 dBm). The circuit as shown in
Figure 44 has about 40 MHz of noise bandwidth; the 0.8 nV/√Hz
of input referred voltage noise spectral density of the AD604 results in an rms noise of 5.05 μV in the 40 MHz bandwidth.
VG
Rev. E | Page 19 of 32
AD604
The 50 Ω termination resistor, in parallel with the 50 Ω source resistance of the signal generator, forms an effective resistance of
25 Ω as seen by the input of the preamplifier, creating 4.07 μV of rms noise at a bandwidth of 40 MHz. The noise floor of this channel is consequently 6.5 μV rms, the rms sum of these two main noise sources. The minimum detectable signal (MDS) for this circuit is +6.5 μV rms (−90.7 dBm). Generally, the measured signal should be about a factor of three larger than the noise floor, in this case 19.5 μV rms. Note that the 25 μV rms signal that this AGC circuit can correct for is just slightly above the
MDS. Of course, the sensitivity of the input can be improved by band-limiting the signal; if the noise bandwidth is reduced by a factor of four to 10 MHz, the noise floor of the AGC circuit with a
50 Ω termination resistor drops to +3.25 μV rms (−96.7 dBm).
Further noise improvement can be achieved by an input matching network or by transformer coupling of the input signal.
90
80
70 f = 1MHz the incoming signal frequency, while passing the low frequency
AM information. The following integrator with a time constant of
2 ms set by R8 and C11 integrates the error signal presented by the low-pass filter and changes VG until the error signal is equal to V
SET
.
For example, if the signal presented to the detector is V1 = A ×
cos(ωt) as indicated in Figure 44, the output of the squarer is
−(V1) 2 /1 V. The reason for all the minus signs in the detection circuitry is the necessity of providing negative feedback in the control loop; actually, if V
SET
becomes greater than 0 V, the control loop provides positive feedback. Squaring A × cos(ωt) results in two terms, one at dc and one at 2ω; the following lowpass filter passes only the −(A) 2 /2 dc term. This dc voltage is now forced equal to the voltage, V
SET
, by the control loop. The squarer, together with the low-pass filter, functions as a meansquare detector. As should be evident by controlling the value of
V
SET
, the amplitude of the voltage V1 can be set at the input of the AD835; if V
SET
equals −80 mV, the AGC output signal amplitude is ±400 mV.
60
50
40
30
Figure 47 shows the control voltage, VGN, vs. the input power at
frequencies of 1 MHz (solid line) and 10 MHz (dashed line) at an output regulated level of 2 dBm (800 mV p-p). The AGC
20
10
0
–10
–20
–30
0.1
0.5
www.BDTIC.com/ADI
0.9
1.3
1.7
2.1
2.5
2.9
power that can still be accommodated is about +3 dBm. At this level, the output starts being distorted because of clipping in the preamplifier.
4.5
4.0
VGN (V)
Figure 45. Cascaded Gain vs. VGN (Based on Figure 44)
threshold is evident at a P
IN
of about −79 dBm; the highest input
3.5
4
3.0
f = 1MHz
3
2.5
2
2.0
10MHz
1 1MHz
1.5
0
1.0
–1
–2
–3
0.5
–80 –70 –60 –50 –40
P
IN
–30
(dBm)
–20 –10 0 10
Figure 47. Control Voltage vs. Input Power of the Circuit in Figure 44
–4
0.2
0.7
1.2
VGN (V)
1.7
2.2
2.7
Figure 46. Cascaded Gain Error vs. VGN (Based on Figure 44)
The descriptions of the detector circuitry functions, comprising a squarer, a low-pass filter, and an integrator, follow. At this point, it is necessary to make some assumptions about the input signal. The following explanation of the detector circuitry presumes an amplitude modulated RF carrier where the modulating signal is at a much lower frequency than the RF signal. The AD835 multiplier functions as the detector by squaring the output signal presented to it by the AD604. A low-pass filter following the squaring operation removes the RF signal component at twice
As previously mentioned, the second preamplifier can be used
to extend the range of the AGC circuit in Figure 44. Figure 48
shows the modifications that must be made to Figure 46 to achieve
96 dB of gain and dynamic range. Because of the extremely high gain, the bandwidth must be limited to reject some of the noise.
Furthermore, limiting the bandwidth helps suppress highfrequency oscillations. The added components act as a low-pass filter and dc block (C5 decouples the 2.5 V common-mode output of the first DSX). The ferrite bead has an impedance of about 5 Ω at 1 MHz, 30 Ω at 10 MHz, and 70 Ω at 100 MHz.
The bead, combined with R2 and C6, forms a 1 MHz low-pass filter.
Rev. E | Page 20 of 32
NOTES
1. THE OUTPUT AFTER 10× ATTENUATER FORMED
BY 453Ω TOGETHER WITH 50Ω OF 7A24 PLUG-IN.
Figure 51. Output of VGA in Figure 50 for VGN = 1 V
AD604
At 1 MHz, the attenuation is about −0.2 dB, increasing to −6 dB at 10 MHz and −28 dB at 100 MHz. Signals less than approximately
1 MHz are not significantly affected.
−95 dBm. The output signal level is set to 800 mV p-p by applying
−80 mV to the V
SET
connector.
C5
0.1µF
R2
499Ω
FB
C6
560pF
C3
0.1µF
1
2
3
4
5
6
–DSX1
+DSX1
PAO1
FBK1
VGN1 24
VREF 23
OUT1 22
GND1 21
PAI1
COM1
AD604
VPOS
VNEG
20
19
7
8
COM2
PAI2
9
10
FBK2
PAO2
11 +DSX2
12 –DSX2
VNEG
VPOS
18
17
GND2 16
OUT2 15
VOCM 14
VGN2 13 the signal amplitude compared with when they are driven single-ended.
AD604
C1
0.1µF
VIN+
VIN–
C4
0.1µF
C2
0.1µF
C3
0.1µF
C12
0.1µF
1
2
3
4
–DSX1
+DSX1
PAO1
FBK1
PAI1
5
6
7
8
COM1
COM2
PAI2
9
10
FBK2
PAO2
11
12
+DSX2
–DSX2
VGN1 24
VREF 23
OUT1 22
GND1 21
VPOS 20
VNEG 19
VNEG 18
VPOS 17
GND2 16
OUT2 15
VOCM 14
VGN2 13
+5V
–5V
–5V
+5V
C7
0.1µF
C6
0.1µF
R1
453Ω
R2
453Ω
VREF
VOUT+
VOUT
VG
C5
0.1µF
FB
FB
+5V
–5V
C13
0.1µF
ALL SUPPLY PINS ARE DECOUPLED AS SHOWN.
–
Figure 50. Ultralow Noise, Differential Input-Differential Output VGA
FAIR-RITE
#2643000301
Figure 51 displays the output signals VOUT+ and VOUT− after
Figure 48. Modifications of the AGC Amplifier to Create 96 dB of Gain Range
in Figure 50 and the 50 Ω loads presented by the oscilloscope
4.5
4.0
3.5
3.0
2.5
plug-in. R1 and R2 are inserted to ensure a nominal load of 500 Ω at each output. The differential gain of the circuit is set to 20 dB www.BDTIC.com/ADI and the differential input amplitude is 100 mV p-p. The resulting differential output amplitude is 1 V p-p as can be seen on the
1MHz
2.0
a −20 dB attenuator formed between the 453 Ω resistors shown scope photo when reading the vertical scale as 200 mV/div.
1.5
20mV 20ns 1.0
ACTUAL
V
OUT
+500mV 0.5
100
90
0
–100 –90 –80 –70 –60 –50 –40 –30 –20 –10
P
IN
(dBm)
0 10
Figure 49. Control Voltage vs. Input Power of the Circuit in Figure 48
ULTRALOW NOISE, DIFFERENTIAL INPUT-
DIFFERENTIAL OUTPUT VGA
Figure 50 shows how to use both preamplifiers and DSXs to
create a high impedance, differential input-differential output
VGA. This application takes advantage of the differential inputs to the DSXs. Note that the input is not truly differential in the sense that the common-mode voltage needs to be at ground to achieve maximum input signal swing. This has largely to do with the limited output swing capability of the output drivers of the preamplifiers; they clip around ±2.2 V due to having to drive an effective load of about 30 Ω. If a different input common-mode
voltage needs to be accommodated, ac coupling (as in Figure 48)
is recommended. The differential gain range of this circuit runs from 6 dB to 54 dB, which is 6 dB higher than each individual channel of the AD604 because the DSX inputs now see twice
10
0%
20mV
–500mV
Rev. E | Page 21 of 3 2
AD604
MEDICAL ULTRASOUND TGC DRIVING THE
AD9050, A 10-BIT, 40 MSPS ADC
The AD604 is an ideal candidate for the time gain control (TGC) amplifier that is required in medical ultrasound systems to limit the dynamic range of the signal that is presented to the ADC.
Figure 52 shows a schematic of an AD604 driving an
AD9050 in a typical medical ultrasound application.
The gain is controlled by means of a digital byte that is input to an AD7226 DAC that outputs the analog gain control signal.
The output common-mode voltage of the AD604 is set to VPOS/2 by means of an internal voltage divider. The VOCM pin is bypassed with a 0.1 μF capacitor to ground.
The DSX output is optionally filtered and then buffered by an AD9631 op amp, a low distortion, low noise amplifier. The op amp output is ac-coupled into the self-biasing input of an
AD9050 ADC that is capable of outputting 10 bits at a 40 MSPS sampling rate.
ANALOG
INPUT
J2
0.1µF
0.1µF
0.1µF
50Ω
50Ω
1
2
3
4
5
6
7
8
9
10
11
–DSX1
+DSX1
PAO1
FBK1
PAI1
COM1
COM2
PAI2
FBK2
PAO2
VGN1 24
VREF 23
OUT1 22
GND1 21
VPOS 20
VNEG
VNEG
19
18
VPOS 17
GND2 16
OUT2 15
VOCM
14
0.1µF
0.1µF
FILTER
+5V
0.1µF
–5V
0.1µF
1kΩ
2
3
–IN
+IN
1kΩ
AD9631
OUT
6
OPTIONAL
0.1µF
3
4
5
6
9
10
13
14
(MSB) D9 15
AD9050
VREF
OUT
VREF
IN
COMP
D8 16
D7
D6
D5
17
18
19
REF
BP
AINB
AIN
ENCODE
OR
D4
D3
D2
24
25
26
D1 27
(LSB) D0 28
V
DD
20
V
DD
22 +DSX2
12
2
13 –DSX2 VGN2
0.1µF
1
AD604
100Ω
1kΩ
0.1µF 0.1µF
CLK www.BDTIC.com/ADI
20
0.1µF
V
OUT
B V
OUT
C
V
OUT
A V
OUT
D 19
V
SS
V
AD7226
REF
V
DD
A0
+15V
VREF
3
4
18
17
A/D
OUTPUT
5
6
7
8
AGND
DGND
DB7
(MSB)
DB6
9
10
DB5
DB4
A1
WR
DB0
(LSB)
DB1
16
15
14
13
DB2 12
DB3
11
DIGITAL GAIN CONTROL
Figure 52. TGC Circuit for Medical Ultrasound Application
Rev. E | Page 22 of 32
PAO1
IN1
C1
0.1µF
NOTE 2 R2
RGN
C3
0.1µF
1 –DSX1
2 +DSX1
3 PAO1
VGN1
24
VREF 23
OUT1 22
4
5
FBK1 GND1
AD604
PAI1 VPOS
21
20
6
COM1 VNEG
19
VG1
VREF
C4
0.1µF
C2
5pF
C12
0.1µF
C11
0.1µF
OUT1
R1
500Ω
NOTE 3
OPTIONAL
+5V
7 COM2 VNEG
18
C10
0.1µF
–5V
IN2 8 PAI2 VPOS
17
C9
0.1µF NOTE 3
9 FBK2 GND2
16
R3
RGN
C8
5pF
R4
500Ω
PAO2
10 PAO2 OUT2
15
OUT2
C6
0.1µF
C7
0.1µF
11
+DSX2 VOCM
14 VOCM
0.1µF
12 –DSX2 VGN2
13
C5
0.1µF
NOTES
1. PAO1 AND PAO2 ARE USED TO MEASURE PREAMPS.
VG2
2. RGN = 0 NOMINALLY; PREAMP GAIN = 5, RGN = OPEN; PREAMP GAIN = 10.
3. WHEN M EASURING BW WITH 50Ω SPECTRUM ANALYZER, USE 450Ω IN SERIES.
Figure 53. Basic Test Board
HP3577B
HP11636B
POWER
SPLITTER
OUT
PAI
R A www.BDTIC.com/ADI
0.1µF
450Ω
50Ω
AD604
DUT
49.9Ω
Figure 54. Setup for Gain Measurements
AD604
Rev. E | Page 23 of 32
AD604
EVALUATION BOARD
Figure 55 is a photograph of the AD604 evaluation board assembly.
Multiple input connections, test points, jumper selectable options, and on-board trims offer convenience when configuring the
AD604 in various operating modes.
The evaluation board requires only a dual 5 V supply capable of
200 mA or higher to operate both channels. Prior to shipment, the evaluation board is fully tested. Users need only attach power supply leads and the appropriate test equipment to the board.
Because of this flexibility, not all component positions on the board are populated when the board is shipped. Installing or changing additional parts is optional.
The AD604-EVALZ is fabricated on a 4-layer board with inner power and ground layers. The AD604 is a stable, trouble-free device; however, as with all high-frequency integrated circuits, power and ground planes help to ensure consistency in performance.
Figure 56. AD604 Evaluation Board—Component Side Silk Screen
DSX INPUT CONNECTIONS
www.BDTIC.com/ADI configurations. SMA connectors are provided for each of the inputs and are labeled CHx VGA IN (+) and CHx VGA IN (−).
JP6 and JP15 select between the preamplifier outputs and the
DSX inputs.
Figure 55. AD604 Evaluation Board Assembly
USING THE PREAMPLIFIER
To use the preamplifiers, simply connect a signal source to CH1
PREAMP IN and/or CH2 PREAMP IN via the SMA connectors.
Referring to the schematic in Figure 61, the input lines are
terminated with 50 Ω resistors at locations R7 and R8.
To enable the preamplifiers, insert jumpers in the JP8 and JP9 rightmost positions; this connects COM1 and COM2 to ground.
Power down the preamplifiers by inserting jumpers in the JP8 and JP9 leftmost positions.
For direct drive of the Channel 1 VGA, insert a jumper in the top position of JP6. For direct drive of the Channel 2 VGA, insert a jumper in JP14 and verify that there are no jumpers in
JP12 and JP13. Refer to the schematic shown in Figure 61 for
circuit details.
Differential DSX Inputs
Differential inputs are possible using both polarities of the
VGA SMA connectors and appropriate jumpers. Inserting a jumper in the lower position of JP5 selects the negative input of Channel 1. A jumper in the top position of JP6 selects the positive input of Channel 1. A jumper in the JP16 rightmost position selects the negative input of Channel 2, and a jumper in JP14 selects the positive input. Verify that there are no jumpers in JP15 or JP13.
Because the VGA section of the AD604 uses a single 5 V supply, the DSX inputs are ac-coupled. Decoupling capacitors are provided on the evaluation board.
The DSX input impedance is approximately 200 Ω. Optional
66.5 Ω resistors can be installed across the inputs at positions
R5, R6, R9, and R10 to establish a 50 Ω terminating load.
Rev. E | Page 24 of 3 2
AD604
Connecting the DSX Inputs to the Preamplifiers
To connect the DSX inputs to the preamplifiers, install jumpers in the JP6 lower position and in JP15. Verify that the jumpers in
JP13 and JP14 are removed.
Cascaded DSX
To channel-cascade the two channels, insert a jumper in JP13.
The resulting single-channel gain range is 96 dB. Verify that
JP14 and JP15 are removed.
The gains of cascaded VGAs can be controlled independently or in common. For common control, insert a jumper in the top position of JP4. To use the trimmer as a gain control, insert a jumper in JP1. For external control, remove JP1 and connect a signal source at VGN1 or VGN2 test loop.
PREAMPLIFIER GAIN
Jumpers in JP7 and JP12 select between two preamplifier gains:
14 dB and 20 dB. Intermediate gains are derived by installing resistors in the R11 and R12 positions. The 14 dB and 20 dB preset gains are accurate due to close matching of thin film resistors. The gain accuracy after installing external resistors is subject to inherent tolerance of absolute accuracy.
OUTPUTS
The DSX outputs are available on OUT1 and OUT2 SMA connectors and are series terminated with decoupling capacitors and 49.9 Ω series resistors. These components can be replaced to accommodate other output impedances.
DC OPERATING CONDITIONS
Table 4 lists the trimmers and their functions provided for
convenient dc level adjustments of gain, reference voltage,
and output common-mode voltage. Table 5 lists the jumpers
and their functions.
Table 4. Trimmer Functions
Trimmer Function
R1 Gain of Channel 1
R2
R3
R4
Reference voltage adjustment
Output common-mode voltage adjustment
Channel 2 gain adjustment
8
9
12
13
4
5
6
7
14
15
16
1
2
3
Table 5. Jumpers
Jumper No. Function www.BDTIC.com/ADI
Connects R2 reference voltage trimmer to VREF input.
Connects common-mode voltage trimmer to VOCM.
Connects VGN2 to R4 Channel 2 gain trimmer or to VGN1 or common gain adjustment.
Connects –DSX1 to CH1 VGA IN (−) or to ground.
Connects +DSX1 (ac-coupled) to preamplifier output of Channel 1 or to the CH 1 VGA IN (+) SMA connector.
When open, the Preamp 1 gain is 20 dB; Preamp 1 gain is 14 dB when a shunt is installed.
Shunt in left position disables Preamp 1; shunt in rightmost position enables Preamp 1.
Shunt in left position disables Preamp 2; shunt in rightmost position enables Preamp 2.
When open, the Preamp 2 gain is 20 dB; Preamp 2 gain is 14 dB when a shunt is installed.
Cascades DSX2 with DSX 1 when a jumper is inserted.
Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2 or to the CH 2 VGA IN (+) SMA connector.
Connects +DSX2 (ac-coupled) to preamplifier output of Channel 2.
Connects –DSX2 to CH2 VGA IN (−) or to ground.
Rev. E | Page 25 of 32
AD604
EVALUATION BOARD ARTWORK AND SCHEMATIC
Figure 57. Component Side Copper Figure 59. Internal Ground Plane www.BDTIC.com/ADI
Figure 58. Secondary Side Copper
Rev. E | Page 26 of 3 2
Figure 60. Internal Power Plane
AD604
J1
CH1 VGA
IN (–)
–DSX1
JP5
A
R5
B
C8
0.1µF
J2
CH1 VGA
IN (+)
+DSX1
A
JP6
R6
B
PAO1
C9
0.1µF
J5
CH 1 PREAMP
IN
PAI1
J6
CH 2 PREAMP
IN
+5V
R7
49.9Ω
PAI2
JP9
R9 JP13
J8
CH1 VGA
IN (–)
–DSX2
JP16
R10
A
B
JP7 R11
JP8
R8
49.9Ω
J7
CH2 VGA
IN (+)
+DSX2
JP14
JP12
JP15
PAO2
R12
C10
0.1µF
C11
0.1µF
+5V
GND1 GND2 GND3 GND4
R1
10kΩ
GN1
ADJ
1
2
3
AD604
U1
–DSX1 VGN1
24
VGN1
C5
1nF
+DSX1 VREF
23
OUT1
PAO1 OUT1
22
VREF
JP1
C6
0.1µF
4
FBK1 GND1
21
+5V
JP2
R13
49.9Ω
5
PAI1 VPOS
20
–5V
+5V
C13
0.1µF
R2
10kΩ
VREF
ADJ
+5V
GND
J3
OUT1
6
COM1 VNEG
19
7
COM2 VNEG
18
C4
0.1µF +
C3
10µF
10V
–5V
8
PAI2
9
FBK2
10
PAO2
11
+DSX2
12
–DSX2
VPOS
17
GND2
16
OUT2
15
VOCM
14
VGN2
13
C2
0.1µF
OUT2
R14
49.9Ω
VOCM
C7
0.1µF
C14
0.1µF
JP3
+
C1
10µF
10V
+5V
J4
OUT2
R3
1kΩ
VOCM
ADJ
VGN2
C12
1nF
A
B
JP4
GN2
ADJ
+5V
R4
1kΩ
Table 6. Bill of Materials
Qty. Type Description
1 Test Red
Reference Designator
8
8
6
4
4
1 Test Blue
5 Test loop Black GND, GND1, GND2, GND3, GND4
+DSX1, +DSX2, −DSX1, −DSX2, OUT1, OUT2, PAI1,
PAI2, PAO1, PAO2, VGN1, VGN2, VOCM, VREF
2 Capacitor Tantalum 10 μF, 10 V, A size C1, C3
10 Capacitor 0.1 μF, 50 V, 20%, 0805 C2, C4, C6, C7, C8, C9, C10, C11, C13, C14
2 Capacitor SM, 1000 pF, 50 V, 0805 C5, C12
Connector SMA FEM PC Mount, RA
Header
Header
Trimmer
Resistor
0.1” center 2-pin
0.1” center 3-pin
10 kΩ, 1/4" SM
49.9 Ω, 1%, 1/10 W, 0805
J1, J2, J3, J4, J5, J6, J7, J8
JP1, JP2, JP3, JP7, JP12, JP13, JP14, JP15
JP4, JP5, JP6, JP8, JP9, JP16
R1, R2, R3, R4
R7, R8, R13, R14
1 Integrated circuit
40 MHz dual low noise VGA
10 Jumper Mini jumper; install in headers at JP1, JP2, JP3,
JP4 lower, JP5 lower, JP6 lower, JP8 right, JP9 right,
JP15, JP16 left
Manufacturer
Nichicon
Panasonic
Panasonic
Amphenol
Berg
Molex
Bourns
Panasonic
Part Number
Components Corp. TP-104-01-00
Components Corp. TP-104-01-07
F931A106MAA
PCC1840CT-ND
ECU-V1H102KBN
901-143-6RFX
69157-2
22-11-2032
3361P-1-103G
ERJ-6ENF49R9
Rev. E | Page 27 of 32
AD604
OUTLINE DIMENSIONS
1.280 (32.51)
1.250 (31.75)
1.230 (31.24)
24
1
13
12
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.015
(0.38)
MIN
0.015 (0.38)
GAUGE
PLANE
SEATING
PLANE
0.005 (0.13)
MIN
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.210 (5.33)
MAX
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
COMPLIANT TO JEDEC STANDARDS MS-001
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 62. 24-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-24-1)
Dimensions shown in inches and (millimeters) www.BDTIC.com/ADI
15.60 (0.6142)
15.20 (0.5984)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
24
1
13
12
7.60 (0.2992)
7.40 (0.2913)
10.65 (0.4193)
10.00 (0.3937)
1.27 (0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
2.65 (0.1043)
2.35 (0.0925)
SEATING
PLANE
8°
0°
0.33 (0.0130)
0.20 (0.0079)
0.75 (0.0295)
0.25 (0.0098)
45°
COMPLIANT TO JEDEC STANDARDS MS-013-AD
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 63. 24-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-24)
Dimensions shown in millimeters and (inches)
1.27 (0.0500)
0.40 (0.0157)
Rev. E | Page 28 of 32
AD604
8.50
8.20
7.90
24
1
13
12
5.60
5.30
5.00
8.20
7.80
7.40
2.00 MAX
1.85
1.75
1.65
0.25
0.09
0.05 MIN
COPLANARITY
0.10
0.65 BSC
0.38
0.22
SEATING
PLANE
8°
4°
0°
0.95
0.75
0.55
COMPLIANT TO JEDEC STANDARDS MO-150-AG
Figure 64. 24-Lead Shrink Small Outline Package [SSOP]
(RS-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD604AN
Temperature Range
−40°C to +85°C
Package Description
24-Lead Plastic Dual In-Line Package [PDIP]
Package Option
N-24-1
AD604AR
AD604AR-REEL
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Plastic Dual In-Line Package [PDIP]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Standard Small Outline Package [SOIC_W]
N-24-1
RW-24
RW-24
RW-24
AD604ARS
AD604ARS-REEL
AD604ARS-REEL7
1 Z = RoHS Compliant Part.
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
24-Lead Standard Small Outline Package [SOIC_W]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
24-Lead Shrink Small Outline Package [SSOP]
RW-24
RS-24
RS-24
RS-24
RS-24
RS-24
RS-24
Rev. E | Page 29 of 32
AD604
NOTES www.BDTIC.com/ADI
Rev. E | Page 30 of 32
NOTES www.BDTIC.com/ADI
AD604
Rev. E | Page 31 of 32
AD604
NOTES www.BDTIC.com/ADI
©1996–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00540-0-10/08(E)
Rev. E | Page 32 of 32
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Table of contents
- 1 FEATURES
- 1 APPLICATIONS
- 1 FUNCTIONAL BLOCK DIAGRAM
- 1 GENERAL DESCRIPTION
- 2 TABLE OF CONTENTS
- 2 REVISION HISTORY
- 3 SPECIFICATIONS
- 5 ABSOLUTE MAXIMUM RATINGS
- 5 ESD CAUTION
- 6 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
- 7 TYPICAL PERFORMANCE CHARACTERISTICS
- 13 THEORY OF OPERATION
- 14 PREAMPLIFIER
- 15 DIFFERENTIAL LADDER (ATTENUATOR)
- 16 AC COUPLING
- 16 GAIN CONTROL INTERFACE
- 16 ACTIVE FEEDBACK AMPLIFIER (FIXED-GAIN AMP)
- 18 APPLICATIONS INFORMATION
- 19 ULTRALOW NOISE AGC AMPLIFIER WITH 82 dB TO 96 dB GAIN RANGE
- 21 ULTRALOW NOISE, DIFFERENTIAL INPUT-DIFFERENTIAL OUTPUT VGA
- 22 MEDICAL ULTRASOUND TGC DRIVING THE AD9050, A 10-BIT, 40 MSPS ADC
- 24 EVALUATION BOARD
- 24 USING THE PREAMPLIFIER
- 24 DSX INPUT CONNECTIONS
- 24 Differential DSX Inputs
- 25 Connecting the DSX Inputs to the Preamplifiers
- 25 Cascaded DSX
- 25 PREAMPLIFIER GAIN
- 25 OUTPUTS
- 25 DC OPERATING CONDITIONS
- 26 EVALUATION BOARD ARTWORK AND SCHEMATIC
- 28 OUTLINE DIMENSIONS
- 29 ORDERING GUIDE