CY7C1344H

2-Mbit (64K x 36) Flow-Through Sync SRAM

Features

• 64K x 36 common I/O

• 3.3V core power supply

• 3.3V/2.5V I/O supply

• Fast clock-to-output times

— 6.5 ns (133-MHz version)

— 8.0 ns (100-MHz version)

• Provide high-performance 2-1-1-1 access rate

• User-selectable burst counter supporting Intel

®

Pentium

®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• Offered in JEDEC-standard lead-free 100-pin TQFP package

• “ZZ” Sleep Mode option

Functional Description

[1]

The CY7C1344H is a 64K x 36 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is

6.5 ns (133-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. All synchronous inputs are gated by registers controlled by a positive-edge-triggered

Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable

(CE

1

), depth-expansion Chip Enables (CE

2

and CE

3

), Burst

Control inputs (ADSC, ADSP, and ADV), Write Enables

(BW

[A:D]

and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin.

The CY7C1344H allows either interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the

Processor Address Strobe (ADSP) or the cache Controller

Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input.

Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or

Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV).

The CY7C1344H operates from a +3.3V core power supply while all outputs may operate with either a +3.3V/2.5V supply.

All inputs and outputs are JEDEC-standard

JESD8-5-compatible.

Logic Block Diagram

A0, A1, A

MODE

ADV

CLK

ADDRESS

REGISTER

BURST

COUNTER

Q1

AND LOGIC

CLR

Q0

A

[1:0]

ADSC

ADSP

BW D

BW C

BW B

BW A

BWE

GW

CE1

CE2

CE3

OE

DQ D

, DQP D

DQ

C

, DQP

C

BYTE

WRITE REGISTER

DQ B

, DQP

B

BYTE

WRITE REGISTER

DQ

A

, DQP

A

BYTE

WRITE REGISTER

ENABLE

REGISTER

DQ D , DQP D

BYTE

WRITE REGISTER

DQ C

, DQP C

BYTE

WRITE REGISTER

DQ B

, DQP B

BYTE

WRITE REGISTER

DQ A

, DQP A

BYTE

WRITE REGISTER

MEMORY

ARRAY

SENSE

AMPS

OUTPUT

BUFFERS

ZZ

SLEEP

CONTROL

Note:

1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.

INPUT

REGISTERS

DQs

DQP A

DQP B

DQP

C

DQP D

Cypress Semiconductor Corporation

Document #: 001-00211 Rev. *B

• 198 Champion Court • San Jose

,

CA 95134-1709 • 408-943-2600

Revised April 26, 2006

[+] Feedback

Selection Guide

Maximum Access Time

Maximum Operating Current

Maximum Standby Current

Pin Configurations

BYTE C

BYTE D

DQ

C

DQ

C

V

SSQ

V

DDQ

DQ

C

DQ

C

NC

DQP

C

DQ

C

DQ

C

V

DDQ

V

SSQ

DQ

C

DQ

C

V

DD

NC

V

SS

DQ

D

DQ

D

V

DDQ

V

SSQ

DQ

D

DQ

D

DQ

D

DQ

D

V

SSQ

V

DDQ

DQ

D

DQ

D

DQP

D

14

15

16

17

18

19

20

21

22

7

8

9

5

6

3

4

1

2

10

11

12

13

23

24

25

26

27

28

29

30

133 MHz

6.5

225

40

100-pin TQFP Pinout

100 MHz

8.0

205

40

CY7C1344H

Unit ns mA mA

CY7C1344H

DQP

B

DQ

B

DQ

B

V

DDQ

V

SSQ

DQ

B

DQ

B

DQ

B

DQ

B

V

SSQ

V

DDQ

DQ

B

DQ

B

V

SS

NC

V

DD

ZZ

DQ

A

DQ

A

V

DDQ

V

SSQ

DQ

A

DQ

A

DQ

A

DQ

A

V

SSQ

V

DDQ

DQ

A

DQ

A

DQP

A

68

67

66

65

64

72

71

70

69

63

62

61

60

76

75

74

73

80

79

78

77

59

58

57

56

55

54

53

52

51

BYTE B

BYTE A

Document #: 001-00211 Rev. *B Page 2 of 15

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CY7C1344H

Pin Definitions

Name

A0, A1,

A

BW

BW

A

B

BW

C

,

BW

D

GW

,

I/O

Input-

Synchronous

Description

Address Inputs used to select one of the 64K address locations. Sampled at the rising edge of the

CLK if ADSP or ADSC is active LOW, and CE

1 counter.

, CE

2

, and CE

3 are sampled active. A

[1:0]

feed the 2-bit

Input-

Synchronous

Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes to the SRAM.

Sampled on the rising edge of CLK.

BWE

CLK

CE

CE

CE

OE

1

2

3

Input-

Synchronous

Input-

Synchronous

Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global

Write is conducted (ALL bytes are written, regardless of the values on BW

[A:D]

and BWE).

Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted

LOW to conduct a Byte Write.

Input-Clock Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation.

Input-

Synchronous

Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

2 and CE

3

to select/deselect the device. ADSP is ignored if CE new external address is loaded.

1

is HIGH. CE

1

is sampled only when a

Input-

Synchronous

Input-

Synchronous

Input-

Asynchronous

Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction with CE

1 and CE

3

to select/deselect the device. CE

2 is sampled only when a new external address is loaded.

Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE

1 and CE

2

to select/deselect the device. CE

3

is sampled only when a new external address is loaded.

Output Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.

ADV

ADSP

ADSC

ZZ

DQs

DQP

A,

DQP

B

DQP

C,

DQP

V

DD

D

Input-

Synchronous

Advance Input signal, sampled on the rising edge of CLK. When asserted, it automatically increments the address in a burst cycle.

Input-

Synchronous

Input-

Synchronous

Address Strobe from Processor, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE

1

is deasserted HIGH

Address Strobe from Controller, sampled on the rising edge of CLK, active LOW. When asserted

LOW, addresses presented to the device are captured in the address registers. A

[1:0]

are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.

Input-

Asynchronous

ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a non-time-critical “sleep” condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.

I/O-

Synchronous

Power

Supply

Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the Read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and

DQP

[A:D]

are placed in a tri-state condition.

Power supply inputs to the core of the device.

V

SS

V

DDQ

V

SSQ

MODE

NC

Ground

I/O Power

Supply

Ground for the core of the device.

Power supply for the I/O circuitry.

I/O Ground Ground for the I/O circuitry.

Input-

Static

Selects Burst Order. When tied to GND selects linear burst sequence. When tied to V

Mode pin has an internal pull-up.

DD

or left floating selects interleaved burst sequence. This is a strap pin and should remain static during device operation.

No Connects. Not Internally connected to the die. 4M, 9M,1 8M, 72M, 144M, 288M, 576M, and 1G are address expansion pins and are not internally connected to the die.

Document #: 001-00211 Rev. *B Page 3 of 15

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Functional Overview

All synchronous inputs pass through input registers controlled by the rising edge of the clock. Maximum access delay from the clock rise (t

CDV

) is 6.5 ns (133-MHz device).

The CY7C1344H supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486™ processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user-selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor

Address Strobe (ADSP) or the Controller Address Strobe

(ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW[A:D]) inputs. A Global Write

Enable (GW) overrides all Byte Write inputs and writes data to all four bytes. All Writes are simplified with on-chip synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE

1

, CE

2

, CE

3

) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. ADSP is ignored if CE

1 is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions are satisfied at clock rise: (1) CE

1

, CE

2

, and CE

3

are all asserted active, and (2) ADSP or ADSC is asserted LOW (if the access is initiated by ADSC, the write inputs must be deasserted during this first cycle). The address presented to the address inputs is latched into the address register and the burst counter/control logic and presented to the memory core.

If the OE input is asserted LOW, the requested data will be available at the data outputs a maximum to t

CDV

after clock rise. ADSP is ignored if CE

1

is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are satisfied at clock rise: (1) CE

1

, CE

2

, CE

3

are all asserted active, and (2) ADSP is asserted LOW. The addresses presented are loaded into the address register and the burst inputs (GW, BWE, and BW[A:D]) are ignored during this first clock cycle. If the write inputs are asserted active (see Write

Cycle Descriptions table for appropriate states that indicate a

Write) on the next clock rise, the appropriate data will be latched and written into the device. Byte Writes are allowed.

During Byte Writes, BWA controls DQA and BWB controls

DQB, BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated during a Byte Write. Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are satisfied at clock rise: (1) CE

1

, CE

2

, and CE

3

are all asserted

CY7C1344H active, (2) ADSC is asserted LOW, (3) ADSP is deasserted

HIGH, and (4) the Write input signals (GW, BWE, and

BW[A:D]) indicate a write access. ADSC is ignored if ADSP is active LOW.

The addresses presented are loaded into the address register and the burst counter/control logic and delivered to the memory core. The information presented to DQ[D:A] will be written into the specified address location. Byte Writes are allowed. During byte writes, BWA controls DQA, BWB controls

DQB, BWC controls DQC, and BWD controls DQD. All I/Os are tri-stated when a Write is detected, even a Byte Write.

Since this is a common I/O device, the asynchronous OE input signal must be deasserted and the I/Os must be tri-stated prior to the presentation of data to DQs. As a safety precaution, the data lines are tri-stated once a Write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1344H provides an on-chip two-bit wraparound burst counter inside the SRAM. The burst counter is fed by

A[1:0], and can follow either a linear or interleaved burst order.

The burst order is determined by the state of the MODE input.

A LOW on MODE will select a linear burst sequence. A HIGH on MODE will select an interleaved burst order. Leaving

MODE unconnected will cause the device to default to a interleaved burst sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation “sleep” mode. Two clock cycles are required to enter into or exit from this “sleep” mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the “sleep” mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the “sleep” mode. CEs, ADSP, and ADSC must remain inactive for the duration of t

ZZREC

LOW.

after the ZZ input returns

Interleaved Burst Address Table

(MODE = Floating or V

DD

)

First

Address

A1, A0

00

01

10

11

Second

Address

A1, A0

01

00

11

10

Third

Address

A1, A0

10

11

00

01

Fourth

Address

A1, A0

11

10

01

00

Linear Burst Address Table (MODE = GND)

First

Address

A

1

, A

0

00

01

10

11

Second

Address

A

1

, A

0

01

10

11

00

Third

Address

A

1

, A

0

10

11

00

01

Fourth

Address

A

1

, A

0

11

00

01

10

Document #: 001-00211 Rev. *B Page 4 of 15

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CY7C1344H

ZZ Mode Electrical Characteristics

Parameter

I

DDZZ t

ZZS t

ZZREC t

ZZI t

RZZI

Description

Sleep mode standby current

Device operation to ZZ

ZZ recovery time

ZZ Active to sleep current

ZZ Inactive to exit sleep current

Truth Table

[2, 3, 4, 5, 6]

Test Conditions

ZZ > V

DD

– 0.2V

ZZ > V

DD

– 0.2V

ZZ < 0.2V

This parameter is sampled

This parameter is sampled

Min.

2t

CYC

0

Max.

40

2t

CYC

2t

CYC

Unit mA ns ns ns ns

Cycle Description

Deselected Cycle,

Power-down1

Deselected Cycle,

Power-down

Deselected Cycle,

Power-down

Address

Used

None

None

None

Deselected Cycle,

Power-down

Deselected Cycle,

Power-down

Sleep Mode, Power-down

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Write Cycle, Begin Burst

None

None

Read Cycle, Begin Burst

Read Cycle, Begin Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Read Cycle, Continue Burst

Write Cycle, Continue Burst

Write Cycle, Continue Burst

Next

Next

Next

Next

Read Cycle, Suspend Burst Current

Read Cycle, Suspend Burst Current

Read Cycle, Suspend Burst Current

Read Cycle, Suspend Burst Current

None

External

External

External

External

External

Next

Next

CE

H

L

L

L

X

X

L

L

L

L

L

X

X

H

H

X

H

X

X

H

H

1

CE

X

L

X

L

X

X

H

H

H

H

H

X

X

X

X

X

X

X

X

X

X

2

CE

X

X

H

X

X

X

L

L

L

L

L

X

X

X

X

X

X

X

X

X

X

3

ZZ

L

L

L

L

L

H

L

L

L

L

L

L

L

L

L

L

L

L

L

L

L

ADSP

X

L

L

H

H

X

L

L

H

H

H

H

H

X

X

H

X

H

H

X

X

ADSC

L

X

X

L

L

X

X

X

L

L

L

H

H

H

H

H

H

H

H

H

H

ADV WRITE OE CLK

X

X

X

X

X

X

X

X

X

X

X

L

L

L

L

L

L

H

H

H

H

X

X

X

X

X

X

X

X

L

H

H

H

H

H

H

L

L

H

H

H

H

X

X

X

X

X

X

L

H

X

L-H

L-H

L-H

L-H

L-H

X

L-H

L-H

L-H

L L-H

H L-H Tri-State

L L-H

H L-H Tri-State

L L-H

X L-H

X L-H

DQ

Tri-State

Tri-State

Tri-State

Tri-State

Tri-State

Tri-State

Q

Tri-State

D

Q

Q

Q

H L-H Tri-State

D

D

L L-H Q

H L-H Tri-State

L L-H Q

H L-H Tri-State

Write Cycle, Suspend Burst

Write Cycle, Suspend Burst

Current

Current

X

H

X

X

X

X

L

L

H

X

H

H

H

H

L

L

X

X

L-H

L-H

D

D

Notes:

2. X = “Don't Care.” H =Logic HIGH, L =Logic LOW.

3. WRITE = L when any one or more Byte Write Enable signals (BW

A

(BW

A

, BW

B

, BW

C

, BW

D

), BWE, GW = H.

, BW

B

, BW

C

, BW

D

) and BWE = L or GW= L. WRITE = H when all Byte Write Enable signals

4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

5. The SRAM always initiates a Read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW

[A: D]

. Writes may occur only on subsequent clocks after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to tri-state. OE is a don't care for the remainder of the Write cycle.

6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

Document #: 001-00211 Rev. *B Page 5 of 15

[+] Feedback

Truth Table for Read/Write

[2, 3]

Function

Read

Read

Write Byte (A, DQP

A

)

Write Byte (B, DQP

B

)

Write Bytes (B, A, DQP

A

, DQP

B

)

Write Byte (C, DQP

C

)

Write Bytes (C, A, DQP

C

, DQP

A

)

Write Bytes (C, B, DQP

C

, DQP

B

)

Write Bytes (C, B, A, DQP

C

, DQP

B

, DQP

A

)

Write Byte (D, DQP

D

)

Write Bytes (D, A, DQP

D

, DQP

A

)

Write Bytes (D, B, DQP

D

, DQP

A

)

Write Bytes (D, B, A, DQP

D

, DQP

B

, DQP

A

)

Write Bytes (D, B, DQP

D

, DQP

B

)

Write Bytes (D, B, A, DQP

D

, DQP

C

, DQP

A

)

Write Bytes (D, C, A, DQP

D

, DQP

B

, DQP

A

)

Write All Bytes

Write All Bytes

CY7C1344H

H

H

H

H

H

H

H

H

H

L

H

H

H

H

H

H

GW

H

H

L

L

L

L

H

L

H

H

L

X

L

L

BW

D

X

H

H

H

H

H

L

L

L

L

L

L

L

L

L

X

L

L

BWE

H

L

L

L

L

L

L

H

H

L

L

H

H

L

L

X

H

L

BW

B

X

H

L

H

H

L

H

L

H

H

L

H

L

L

L

X

L

L

BW

C

X

H

H

L

H

H

L

H

L

H

L

H

L

H

L

X

L

H

BW

A

X

H

L

H

L

H

Document #: 001-00211 Rev. *B Page 6 of 15

[+] Feedback

CY7C1344H

Maximum Ratings

(Above which the useful life may be impaired. For user guidelines, not tested.)

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with

Power Applied............................................. –55°C to +125°C

Supply Voltage on V

DD

Relative to GND........ –0.5V to +4.6V

Supply Voltage on V

DDQ

Relative to GND ...... –0.5V to +V

DD

DC Voltage Applied to Outputs in Tri-State........................................... –0.5V to V

DDQ

+ 0.5V

Electrical Characteristics

Over the Operating Range

[7, 8]

DC Input Voltage ................................... –0.5V to V

DD

+ 0.5V

Current into Outputs (LOW)......................................... 20 mA

Static Discharge Voltage.......................................... > 2001V

(per MIL-STD-883, Method 3015)

Latch-up Current.................................................... > 200 mA

Operating Range

Range

Ambient

Temperature

]

V

DD

V

DDQ

Commercial 0°C to +70°C 3.3V

−5%/+10% 2.5V –5%

Industrial –40°C to +85°C to V

DD

I

I

I

Parameter

V

DD

V

DDQ

Description

Power Supply Voltage

I/O Supply Voltage

V

V

V

V

X

OH

OL

IH

IL

OZ

DD

Test Conditions

Output HIGH Voltage

Output LOW Voltage

Input HIGH Voltage

[7] for 3.3V I/O for 2.5V I/O for 3.3V I/O, I

OH

= –4.0 mA for 2.5V I/O, I

OH

= –1.0 mA for 3.3V I/O, I

OL

= 8.0 mA for 2.5V I/O, I

OL

= 1.0 mA for 3.3V I/O

Input LOW Voltage

[7] for 2.5V I/O for 3.3V I/O

Input Leakage Current except ZZ and MODE for 2.5V I/O

GND

≤ V

I

≤ V

DDQ

Input Current of MODE Input = V

SS

Input = V

DD

Input Current of ZZ

V

DD

Operating Supply

Current

Input = V

SS

Input = V

DD

Output Leakage Current GND

≤ V

I

≤ V

DDQ

, Output Disabled

V

DD

= Max., I

OUT

= 0 mA, f = f

MAX

= 1/t

CYC

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

I

I

SB1

SB2

Automatic CE Power-Down

Current—TTL Inputs

Max. V

DD

V

IN

≥ V

IH

, Device Deselected,

or V

IN inputs switching

≤ V

IL

, f = f

MAX,

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

Automatic CE Power-Down

Current—CMOS Inputs

Max. V

DD

V

IN

≥ V

DD

, Device Deselected,

– 0.3V or V f = 0, inputs static

IN

≤ 0.3V,

All speeds

I

I

SB3

SB4

Automatic CE Power-Down

Current—CMOS Inputs

Max. V

V

IN f = f

≥ V

DD

MAX

, Device Deselected,

DDQ

– 0.3V or V

IN

≤ 0.3V,

, inputs switching

Automatic CE Power-Down

Current—TTL Inputs

Max. V

DD

V

IN

≥ V

DD

, Device Deselected,

– 0.3V or V f = 0, inputs static

IN

≤ 0.3V,

7.5-ns cycle, 133 MHz

10-ns cycle, 100 MHz

All speeds

Notes:

7. Overshoot: V

IH

(AC) < V

DD

+1.5V (Pulse width less than t

8. T

Power-up

: Assumes a linear ramp from 0v to V

DD

CYC

/2), undershoot: V

IL

(AC) > –2V (Pulse width less than t

CYC

/2).

(min.) within 200 ms. During this time V

IH

< V

DD

and V

DDQ

< V

DD

.

Min.

3.135

3.135

2.375

2.4

2.0

2.0

1.7

–0.3

–0.3

−5

–30

–5

–5

Max.

3.6

V

DD

2.625

0.4

0.4

V

V

DD

+ 0.3V

V

V

DD

+ 0.3V

0.8

V

0.7

5

µA

5

30

5

225

205

90

80

40

75

65

45

µA

µA

µA

µA

µA mA mA mA mA

Unit

V

V

V

V mA mA mA mA

Document #: 001-00211 Rev. *B Page 7 of 15

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CY7C1344H

Capacitance

[9]

Parameter

C

IN

C

CLK

C

I/O

Thermal Resistance

[9]

Description

Input Capacitance

Clock Input Capacitance

Input/Output Capacitance

Test Conditions

T

A

= 25

°C, f = 1 MHz,

V

DD

= 3.3V.

V

DDQ

= 2.5V

100 TQFP

Max.

5

5

5

Unit pF pF pF

Θ

JA

Parameter Description

Thermal Resistance

(Junction to Ambient)

Θ

JC

(Junction to Case)

AC Test Loads and Waveforms

3.3V I/O Test Load

Test Conditions

Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51

100 TQFP

Package

30.32

6.85

Unit

°C/W

°C/W

OUTPUT

Z

0

= 50

Ω

3.3V

R

L

= 50

Ω

OUTPUT

5 pF

V

(a)

L

= 1.5V

INCLUDING

JIG AND

SCOPE

2.5V I/O Test Load

OUTPUT

Z

0

= 50

Ω

V

T

2.5V

R

L

= 50

Ω

OUTPUT

= 1.25V

5 pF

INCLUDING

JIG AND

SCOPE

(a)

(b)

(b)

R = 317

Ω

R = 351

Ω

V

DDQ

10%

GND

≤ 1 ns

ALL INPUT PULSES

90%

90%

10%

≤ 1 ns

(c)

R = 1667

Ω

R =1538

Ω

V

DDQ

10%

GND

≤ 1 ns

ALL INPUT PULSES

90%

90%

10%

≤ 1 ns

(c)

Note:

9. Tested initially and after any design or process change that may affect these parameters.

Document #: 001-00211 Rev. *B Page 8 of 15

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CY7C1344H

Switching Characteristics

Over the Operating Range

[10, 11]

Parameter t

POWER

Clock

V

DD

Description

(Typical) to the First Access

[12] t

CYC t

CH

Clock Cycle Time

Clock HIGH t

CL

Output Times

Clock LOW t

CDV t

DOH t

CLZ t

CHZ

Data Output Valid after CLK Rise

Data Output Hold after CLK Rise

Clock to Low-Z

Clock to High-Z

[13, 14, 15]

[13, 14, 15] t

OEV t

OELZ

OE LOW to Output Valid

OE LOW to Output Low-Z

[13, 14, 15] t

OEHZ

Set-up Times

OE HIGH to Output High-Z

[13, 14, 15]

133 MHz

Min.

1

7.5

2.5

2.5

2.0

0

0

Max.

6.5

3.5

3.5

3.5

Min.

1

10

4.0

4.0

2.0

0

0

100 MHz

Max.

8.0

3.5

3.5

3.5

Unit ms ns ns ns ns ns ns ns ns ns ns t

AS t

ADS t

ADVS t

WES t

DS t

CES

Hold Times

Address Set-up before CLK Rise

ADSP, ADSC Set-up before CLK Rise

ADV Set-up before CLK Rise

GW, BWE, BW

[A:D]

Set-up before CLK Rise

Data Input Set-up before CLK Rise

Chip Enable Set-up

1.5

1.5

1.5

1.5

1.5

1.5

2.0

2.0

2.0

2.0

2.0

2.0

ns ns ns ns ns ns t

AH t

ADH t

WEH t

ADVH

Address Hold after CLK Rise

ADSP, ADSC Hold after CLK Rise

GW, BWE, BW

[A:D]

Hold after CLK Rise

ADV Hold after CLK Rise

0.5

0.5

0.5

0.5

0.5

0.5

0.5

0.5

ns ns ns ns t

DH t

CEH

Data Input Hold after CLK Rise

Chip Enable Hold after CLK Rise

0.5

0.5

0.5

0.5

ns ns

Notes:

10. Timing reference level is 1.5V when V

DDQ

= 3.3V and 1.25V when V

DDQ

= 2.5V.

11. Test conditions shown in (a) of AC Test Loads unless otherwise noted.

12. This part has a voltage regulator internally; t

POWER can be initiated.

is the time that the power needs to be supplied above V

DD

(minimum) initially before a Read or Write operation

13. t

CHZ

, t

CLZ

, t

OELZ

, and t

OEHZ

are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.

14. At any given voltage and temperature, t

OEHZ

is less than t

OELZ

and t

CHZ

is less than t

CLZ

to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions.

15. This parameter is sampled and not 100% tested.

Document #: 001-00211 Rev. *B Page 9 of 15

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CY7C1344H

Timing Diagrams

Read Cycle Timing

[16] tCYC

CLK t

CH t

CL tADS tADH

ADSP tADS tADH

ADSC

ADDRESS tAS tAH

A1 A2 t

WES t

WEH

GW, BWE,BW

[A:D]

Deselect Cycle tCES tCEH

CE t

ADVS t

ADVH

ADV

ADV suspends burst.

OE tOEV tCLZ tOEHZ tOELZ tCDV tDOH tCHZ

Data Out (Q) High-Z tCDV

Q(A1) Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A2 + 2)

Burst wraps around to its initial state

Single READ BURST

READ

UNDEFINED DON’T CARE

Note:

16. On this diagram, when CE is LOW, CE

1

is LOW, CE

2

is HIGH and CE

3

is LOW. When CE is HIGH, CE

1

is HIGH or CE

2

is LOW or CE

3

is HIGH.

Document #: 001-00211 Rev. *B Page 10 of 15

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CY7C1344H

Timing Diagrams

(continued)

Write Cycle Timing

[16, 17] tCYC

CLK t

CH t

CL tADS tADH

ADSP tADS tADH

ADSC extends burst.

tADS tADH

ADSC

ADDRESS tAS tAH

A1 A2

Byte write signals are ignored for first cycle when

ADSP initiates burst.

A3 tWES tWEH

BWE,

BW [A:D] t

WES t

WEH

GW tCES tCEH

CE tADVS tADVH

ADV

ADV suspends burst.

OE t

DS t

DH

Data in (D) High-Z t

OEHZ

D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3)

Data Out (Q)

BURST READ Single WRITE BURST WRITE

DON’T CARE UNDEFINED

Note:

17. Full width Write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BW

[A:D]

LOW.

D(A3) D(A3 + 1) D(A3 + 2)

Extended BURST WRITE

Document #: 001-00211 Rev. *B Page 11 of 15

[+] Feedback

CY7C1344H

Timing Diagrams

(continued)

Read/Write Timing

[16, 18, 19] tCYC

CLK t

CH t

CL tADS tADH

ADSP

ADSC

ADDRESS A1 tAS tAH

A2

BWE, BW [A:D]

CE tCES tCEH

A3 t

WES t

WEH

A4 A5 A6

ADV

OE tDS tDH

D(A3) tOELZ

Data In (D)

Data Out (Q)

High-Z t

OEHZ

Q(A1) Q(A2)

Back-to-Back READs Single WRITE tCDV

Q(A4) Q(A4+1) Q(A4+2) Q(A4+3)

BURST READ

DON’T CARE UNDEFINED

Notes:

18. The data bus (Q) remains in High-Z following a Write cycle unless an ADSP, ADSC, or ADV cycle is performed.

19. GW is HIGH.

D(A5) D(A6)

Back-to-Back

WRITEs

Document #: 001-00211 Rev. *B Page 12 of 15

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CY7C1344H

Timing Diagrams

(continued)

ZZ Mode Timing

[20, 21]

CLK t

ZZ

ZZ t

ZZI

I

SUPPLY

ALL INPUTS

(except ZZ)

I

DDZZ t

ZZREC t

RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes:

20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device.

21. DQs are in High-Z when exiting ZZ sleep mode.

Document #: 001-00211 Rev. *B Page 13 of 15

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CY7C1344H

Ordering Information

“Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit www.cypress.com

for actual products offered”.

Speed

(MHz) Ordering Code

133 CY7C1344H-133AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1344H-133AXI

100 CY7C1344H-100AXC 51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

CY7C1344H-100AXI

Package

Diagram Package Type

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

51-85050 100-pin Thin Quad Flat Pack (14 x 20 x 1.4 mm) Lead-Free

Operating

Range

Commercial

Industrial

Commercial

Industrial

Package Diagram

1

100

100-pin TQFP (14 x 20 x 1.4 mm) (51-85050)

16.00±0.20

14.00±0.10

81

80

0.30±0.08

1.40±0.05

0.65

TYP.

12°±1°

(8X)

SEE DETAIL

A

30

31 50

51

0.20 MAX.

1.60 MAX.

R 0.08 MIN.

0.20 MAX.

0° MIN.

GAUGE PLANE

0.25

STAND-OFF

0.05 MIN.

0.15 MAX.

SEATING PLANE

NOTE:

1. JEDEC STD REF MS-026

2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH

MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.0098 in (0.25 mm) PER SIDE

BODY LENGTH DIMENSIONS ARE MAX PLASTIC BODY SIZE INCLUDING MOLD MISMATCH

3. DIMENSIONS IN MILLIMETERS

0°-7°

0.60±0.15

R 0.08 MIN.

0.20 MAX.

1.00 REF.

0.20 MIN.

DETAIL

A

51-85050-*B

Intel and Pentium are registered trademarks and i486 is a trademark of Intel Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 001-00211 Rev. *B Page 14 of 15

© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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CY7C1344H

Document History Page

Document Title: CY7C1344H 2-Mbit (64K x 36) Flow-Through Sync SRAM

Document Number: 001-00211

REV.

**

*A

ECN NO.

347377

428408

Issue Date

See ECN

See ECN

Orig. of

Change

PCI

NXR

New Data Sheet

Description of Change

Changed address of Cypress Semiconductor Corporation on Page# 1 from

“3901 North First Street” to “198 Champion Court”

Changed Three-State to Tri-State.

Modified “Input Load” to “Input Leakage Current except ZZ and MODE” in the

Electrical Characteristics Table.

Modified test condition from V

IH

< V

DD to V

IH

< V

DD

Replaced Package Name column with Package Diagram in the Ordering

Information table.

Replaced Package Diagram of 51-85050 from *A to *B

*B 459347 See ECN NXR Converted from Preliminary to Final

Included 2.5V I/O option

Updated the Ordering Information table.

Document #: 001-00211 Rev. *B Page 15 of 15

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