19-2916; Rev 1; 10/03
KIT
ATION
EVALU
E
L
B
AVAILA
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Applications
Narrowband/Wideband CDMA Handsets
and PDAs
Features
♦ Integrated Dual 8-Bit ADCs and Dual 10-Bit DACs
♦ Ultra-Low Power
75.6mW at fCLK = 40MHz (Transceiver Mode)
64mW at fCLK = 22MHz (Transceiver Mode)
Low-Current Idle and Shutdown Modes
♦ Excellent Dynamic Performance
48.4dB SINAD at fIN = 5.5MHz (ADC)
70dB SFDR at fOUT = 2.2MHz (DAC)
♦ Excellent Gain/Phase Match
±0.2° Phase, ±0.05dB Gain at fIN = 5.5MHz (ADC)
♦ Internal/External Reference Option
♦ +1.8V to +3.3V Digital Output Level (TTL/CMOS
Compatible)
♦ Multiplexed Parallel Digital Input/Output for
ADCs/DACs
♦ Miniature 48-Pin Thin QFN Package (7mm ✕ 7mm)
♦ Evaluation Kit Available (Order MAX5865EVKIT)
Functional Diagram
IA+
QA-
ID-
QD-
PIN-PACKAGE
MAX5865ETM
-40°C to +85°C
48 Thin QFN-EP*
(7mm x 7mm)
MAX5865E/D
-40°C to +85°C
Dice**
*EP = Exposed paddle.
**Contact factory for dice specifications.
ADC
CLK
3G Wireless Terminals
TEMP RANGE
DA0–DA7
ID+
QD+
PART
ADC
OUTPUT
MUX
QA+
Fixed/Mobile Broadband Wireless Modems
Ordering Information
ADC
IA-
DAC
DAC
INPUT
MUX
DAC
REFP
COM
REFN
REFIN
DD0–DD9
REF AND
BIAS
SERIAL
INTERFACE
AND SYSTEM
CONTROL
DIN
SCLK
CS
MAX5865
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX5865
General Description
The MAX5865 ultra-low-power, highly integrated analog
front end is ideal for portable communication equipment
such as handsets, PDAs, WLAN, and 3G wireless terminals. The MAX5865 integrates dual 8-bit receive ADCs
and dual 10-bit transmit DACs while providing the highest dynamic performance at ultra-low power. The ADCs’
analog I-Q input amplifiers are fully differential and
accept 1VP-P full-scale signals. Typical I-Q channel
phase matching is ±0.2° and amplitude matching is
±0.05dB. The ADCs feature 48.4dB SINAD and 70dBc
spurious-free dynamic range (SFDR) at fIN = 5.5MHz and
fCLK = 40MHz. The DACs’ analog I-Q outputs are fully
differential with ±400mV full-scale output, and 1.4V common-mode level. Typical I-Q channel phase matching is
±0.15° and gain matching is ±0.05dB. The DACs also
feature dual 10-bit resolution with 72dBc SFDR, and
57dB SNR at fOUT = 2.2MHz and fCLK = 40MHz.
The ADCs and DACs operate simultaneously or independently for frequency-division duplex (FDD) and time-division duplex (TDD) modes. A 3-wire serial interface
controls power-down and transceiver modes of operation. The typical operating power is 75.6mW at fCLK =
40Msps with the ADCs and DACs operating simultaneously in transceiver mode. The MAX5865 features an
internal 1.024V voltage reference that is stable over the
entire operating power-supply range and temperature
range. The MAX5865 operates on a +2.7V to +3.3V analog power supply and a +1.8V to +3.3V digital I/O power
supply for logic compatibility. The quiescent current is
8.5mA in idle mode and 1µA in shutdown mode. The
MAX5865 is specified for the extended (-40°C to +85°C)
temperature range and is available in a 48-pin thin QFN
package.
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
ABSOLUTE MAXIMUM RATINGS
VDD to GND, OVDD to OGND................................-0.3V to +3.3V
GND to OGND.......................................................-0.3V to +0.3V
IA+, IA-, QA+, QA-, ID+, ID-, QD+, QD-, REFP, REFN,
REFIN, COM to GND ..............................-0.3V to (VDD + 0.3V)
DD0–DD9, SCLK, DIN, CS, CLK,
DA0–DA7 to OGND .............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
48-Pin Thin QFN (derate 26.3mW/°C above
+70°C)..............................................................................2.1W
Thermal Resistance θJA .................................................+38°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2.7
3.0
3.3
V
VDD
V
POWER REQUIREMENTS
Analog Supply Voltage
VDD
Output Supply Voltage
OVDD
VDD Supply Current
OVDD Supply Current
2
1.8
ADC operating mode, fIN = 5.5MHz, fCLK =
40MHz, DAC operating mode, fOUT = 2.2MHz
25.2
ADC operating mode (Rx), fIN = 5.5MHz,
fCLK = 40MHz, DAC digital inputs at zero or
OVDD
21
DAC operating mode (Tx), fOUT = 2.2MHz,
fCLK = 40MHz, ADC off
12.8
32
mA
Standby mode, DAC digital inputs and CLK
at zero or OVDD
2.0
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 40MHz
11
Shutdown mode, digital inputs and CLK at
zero or OVDD, CS = OVDD
1
µA
ADC operating mode, fIN = 5.5MHz, fCLK =
40Msps, DAC operating mode, fOUT =
2.2MHz
3.8
mA
Idle mode, DAC digital inputs at zero or
OVDD, fCLK = 40MHz
37.4
Shutdown mode, DAC digital inputs and
CLK at zero or OVDD, CS = OVDD
1
µA
_______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC DC ACCURACY
Resolution
8
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Bits
±0.15
No missing codes over temperature
±0.15
Offset Error
Residual DC offset error
±0.22
Gain Error
Includes reference error
DC Gain Matching
Offset Matching
Gain Temperature Coefficient
Power-Supply Rejection
PSRR
LSB
LSB
±5
%FS
±0.48
±5
%FS
±0.03
±0.25
dB
±3
LSB
±42
ppm/°C
Offset error (VDD ±5%)
±0.2
Gain error (VDD ±5%)
±0.07
Differential or single-ended inputs
±0.512
V
VDD / 2
V
120
kΩ
5
pF
LSB
ADC ANALOG INPUT
Input Differential Range
VID
Input Common-Mode Voltage
Range
RIN
Input Impedance
Switched capacitor load
CIN
ADC CONVERSION RATE
Maximum Clock Frequency
fCLK
Data Latency
(Note 2)
40
Channel I
5
Channel Q
5.5
MHz
Clock
cycles
ADC DYNAMIC CHARACTERISTICS (Note 3)
Signal-to-Noise Ratio
SNR
Signal-to-Noise and Distortion
Ratio
SINAD
Spurious-Free Dynamic Range
SFDR
Third-Harmonic Distortion
HD3
Intermodulation Distortion
Third-Order Intermodulation
Distortion
Total Harmonic Distortion
THD
fIN = 5.5MHz
47
fIN = 20MHz
fIN = 5.5MHz
dB
48.2
46.5
fIN = 20MHz
fIN = 5.5MHz
48.5
48.4
dB
48.2
58
70
fIN = 20MHz
70
dBc
fIN = 5.5MHz
-75.4
fIN = 20MHz
-75
IMD
f1 = 2MHz, -7dBFS; f2 = 2.01MHz, -7dBFS
-66
dBc
IM3
f1 = 2MHz, -7dBFS; f2 = 2.01MHz, -7dBFS
-70
dBc
fIN = 5.5MHz
-71
fIN = 20MHz
-70
dBc
-57
dBc
_______________________________________________________________________________________
3
MAX5865
ELECTRICAL CHARACTERISTICS (continued)
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
Large-Signal Bandwidth
FBW
AIN = -0.5dBFS
Aperture Delay
Aperture Jitter
1.5 × full-scale input
Overdrive Recovery Time
440
MHz
3.3
ns
2.7
psRMS
2
ns
-75
dB
ADC INTERCHANNEL CHARACTERISTICS
Crosstalk Rejection
fINX = 5.5MHz at -0.5dBFS, fINY = 0.3MHz at
-0.5dBFS (Note 5)
Amplitude Matching
fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.05
dB
Phase Matching
fIN = 5.5MHz at -0.5dBFS (Note 6)
±0.2
Degrees
DAC DC ACCURACY
Resolution
N
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
10
Guaranteed monotonic
Zero-Scale Error
Residual DC offset
Full-Scale Error
Include reference error
Bits
±1
LSB
±0.5
LSB
±3
LSB
-35
+35
LSB
DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
(Note 2)
40
Msps
Noise over Nyquist
ND
fOUT = 2.2MHz, fCLK = 40MHz
-130.6
dBc/Hz
Output-of-Band Noise Power
Density
NO
fOUT = 1.2MHz, fCLK = 22MHz,
offset = 10MHz
-130.9
dBc/Hz
10
pVs
Glitch Impulse
fCLK = 40MHz
fOUT = 2.2MHz
fCLK = 22MHz
fOUT = 200kHz
59
72.3
Spurious-Free Dynamic Range
SFDR
dBc
Total Harmonic Distortion
(to Nyquist)
THD
fCLK = 40MHz, fOUT = 2.2MHz
-70
Signal-to-Noise Ratio
(to Nyquist)
SNR
fCLK = 40MHz, fOUT = 2.2MHz
57
dB
DAC-to-DAC Output Isolation
fOUTX, Y = 2.2MHz, fOUTX, Y = 2.0MHz
80
dB
Gain Mismatch Between DAC
Outputs
fOUT = 2.2MHz, fCLK = 40MHz
0.05
dB
Phase Mismatch Between DAC
Outputs
fOUT = 2.2MHz, fCLK = 40MHz
±0.15
Degrees
73.5
-58.5
dB
DAC INTERCHANNEL CHARACTERISTICS
4
_______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DAC ANALOG OUTPUT
Full-Scale Output Voltage
±400
VFS
Output Common-Mode Range
1.29
mV
1. 5
V
ADC-DAC INTERCHANNEL CHARACTERISTICS
ADC-DAC Isolation
ADC fINI = fINQ = 5.5MHz, DAC fOUTI =
fOUTQ = 2.2MHz, fCLK = 40MHz
75
dB
ADC-DAC TIMING CHARACTERISTICS
CLK Rise to I-ADC Channel-I
Output Data Valid
tDOI
Figure 3 (Note 4)
7.4
9
ns
CLK Fall to Q-ADC Channel-Q
Output Data Valid
tDOQ
Figure 3 (Note 4)
6.9
9
ns
I-DAC Data to CLK Fall Setup
Time
tDSI
Figure 4 (Note 4)
10
ns
Q-DAC Data to CLK Rise Setup
Time
tDSQ
Figure 4 (Note 4)
10
ns
CLK Fall to I-DAC Data Hold Time
tDHI
Figure 4 (Note 4)
0
ns
CLK Rise to Q-DAC Data Hold Time
tDHQ
Figure 4 (Note 4)
0
Clock Duty Cycle
ns
50
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
%
±15
%
2.6
ns
SERIAL INTERFACE TIMING CHARACTERISTICS
Falling Edge of CS to Rising Edge
of First SCLK Time
tCSS
Figure 5 (Note 4)
10
ns
DIN to SCLK Setup Time
tDS
Figure 5 (Note 4)
10
ns
DIN to SCLK Hold Time
tDH
Figure 5 (Note 4)
0
ns
SCLK Pulse Width High
tCH
Figure 5 (Note 4)
25
ns
SCLK Pulse Width Low
tCL
Figure 5 (Note 4)
25
ns
SCLK Period
tCP
Figure 5 (Note 4)
50
ns
SCLK to CS Setup Time
tCS
Figure 5 (Note 4)
0
ns
tCSW
Figure 5 (Note 4)
80
ns
CS High Pulse Width
MODE RECOVERY TIMING CHARACTERISTICS
Shutdown Wake-Up Time
tWAKE,SD
From shutdown to Rx mode, Figure 6, ADC
settles to within 1dB
20
From shutdown to Tx mode, Figure 6, DAC
settles to within 10 LSB error
40
µs
_______________________________________________________________________________________
5
MAX5865
ELECTRICAL CHARACTERISTICS (continued)
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
From idle to Rx mode with CLK present
during idle, Figure 6, ADC settles to within
1dB SINAD
Idle Wake-Up Time (with CLK)
Standby Wake-Up Time
TYP
MAX
10
µs
tWAKE,ST0
tWAKE,ST1
UNITS
From idle to Tx mode with CLK present
during idle, Figure 6, DAC settles to 10 LSB
error
10
From standby to Rx mode, Figure 6, ADC
settles to within 1dB SINAD
10
From standby to Tx mode, Figure 6, DAC
settles to 10 LSB error
40
µs
Enable Time from Xcvr or Tx to Rx
tENABLE, Rx ADC settles to within 1dB SINAD
10
µs
Enable Time from Xcvr or Rx to Tx
tENABLE, Tx DAC settles to 10 LSB error
10
µs
0.256
V
-0.256
V
VDD / 2
V /2
VDD / 2 DD
- 0.15
+ 0.15
V
INTERNAL REFERENCE (REFIN = VDD. VREFP, VREFN and VCOM are generated internally.)
Positive Reference
VREFP - VCOM
Negative Reference
VREFN - VCOM
Common-Mode Output Voltage
VCOM
Differential Reference Output
VREF
Differential Reference
Temperature Coefficient
VREFP - VREFN
+0.49
+0.512 +0.534
V
REFTC
±30
ppm/°C
Maximum REFP/REFN/COM
Source Current
ISOURCE
2
mA
Maximum REFP/REFN/COM
Sink Current
ISINK
2
mA
BUFFERED EXTERNAL REFERENCE (REFIN = 1.024V. VREFP, VREFN, and VCOM are generated internally.)
Reference Input
VREFIN
Differential Reference Output
VDIFF
Common-Mode Output Voltage
VREFP - VREFN
1.024
V
0.512
V
VCOM
VDD / 2
V
Maximum REFP/REFN/COM
Source Current
ISOURCE
2
mA
Maximum REFP/REFN/COM
Sink Current
ISINK
2
mA
>500
kΩ
-0.7
µA
REFIN Input Resistance
REFIN Input Current
DIGITAL INPUTS (CLK, SCLK, DIN, CS, DD0–DD9)
Input High Threshold
6
VINH
DD0–DD9, CLK, SCLK, DIN, CS
0.7 x
OVDD
_______________________________________________________________________________________
V
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz, ADC input amplitude = -0.5dBFS,
DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN = CCOM = 0.33µF, Xcvr mode, unless
otherwise noted. Typical values are at TA = +25°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.3 x
OVDD
Input Low Threshold
VINL
DD0–DD9, CLK, SCLK, DIN, CS
Input Leakage
DIIN
DD0–DD9, CLK, SCLK, DIN, CS = OGND or
OVDD
Input Capacitance
DCIN
V
±5
µA
5
pF
DIGITAL OUTPUTS (DA0–DA7)
0.2 x
OVDD
Output Voltage Low
VOL
ISINK = 200µA
Output Voltage High
VOH
ISOURCE = 200µA
Tri-State Leakage Current
ILEAK
Tri-State Output Capacitance
COUT
V
0.8 x
OVDD
V
±5
µA
5
pF
Note 1: Specifications from TA = +25°C to +85°C are guaranteed by product tests. Specifications from TA = +25°C to -40°C are
guaranteed by design and characterization.
Note 2: The minimum clock frequency for the MAX5865 is 22MHz.
Note 3: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 4: Guaranteed by design and characterization.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tone bins.
Note 6: Amplitude/phase matching is measured by applying the same signal to each channel, and comparing the magnitude and
phase of the fundamental bin on the calculated FFT.
Typical Operating Characteristics
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
IA
-40
-50
-60
HD3
HD2
-70
QA
-30
QA
MAX5865 toc02
-20
-40
-50
HD3
-60
IA
HD2
0
-10
-70
-30
-50
-60
-70
-80
-90
-90
-90
-100
-100
-100
0
4
8
12
FREQUENCY (MHz)
16
20
f1
-40
-80
-110
fCLK = 40MHz
f1 = 1.8MHz
f2 = 2.2MHz
AIA = AQA = -7dBFS PER TONE
8192-POINT DATA RECORD
f2
-20
AMPLITUDE (dBFS)
-30
fCLK = 40MHz
fIA = 12.499MHz
fQA = 19.99MHz
AIA = AQA = 0.5dBFS
8192-POINT DATA RECORD
-10
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-20
MAX5865 toc01
fCLK = 40MHz
fIA = 12.499MHz
fQA = 19.99MHz
AIA = AQA = 0.5dBFS
8192-POINT DATA RECORD
-10
ADC CHANNEL-IA TWO-TONE FFT PLOT
ADC CHANNEL-QA FFT PLOT
0
MAX5865 toc03
ADC CHANNEL-IA FFT PLOT
0
-80
-110
-110
0
4
8
12
FREQUENCY (MHz)
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
_______________________________________________________________________________________
7
MAX5865
ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
-30
-40
IA
49.5
-60
QA
48.0
47.5
47.5
47.0
47.0
46.5
46.5
-110
46.0
46.0
0
4
8
12
16
20
0
25
50
75
100
0
125
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
-45
80
MAX5865 toc08
MAX5865 toc07
80
75
MAX5865 toc09
FREQUENCY (MHz)
-40
SINGLE-ENDED
75
70
-50
SFDR (dBc)
-60
-65
SFDR (dBc)
70
-55
65
65
50
55
60
-70
50
55
-75
-80
45
50
25
50
75
100
125
40
0
25
50
75
100
0
125
25
50
75
100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT POWER
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. ANALOG INPUT POWER
ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT POWER
50
fIN = 10.0732MHz
-30
50
-35
SINAD (dB)
IA
30
QA
fIN = 10.0732MHz
-40
-45
40
THD (dB)
40
60
MAX5865 toc11
fIN = 10.0732MHz
125
MAX5865 toc12
ANALOG INPUT FREQUENCY (MHz)
MAX5865 toc10
0
60
QA
48.0
-80
-90
THD (dB)
48.5
-70
-100
IA
49.0
48.5
MAX5865 toc06
49.5
49.0
f1
-50
50.0
SINAD (dB)
f2
SNR (dB)
AMPLITUDE (dBFS)
-20
50.0
MAX5865 toc05
fCLK = 40MHz
f1 = 1.8MHz
f2 = 2.2MHz
AIA = -7dBFS PER TONE
8192-POINT DATA RECORD
MAX5865 toc04
0
-10
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. ANALOG INPUT FREQUENCY
ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
ADC CHANNEL-QA TWO-TONE FFT PLOT
SNR (dB)
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
30
-50
-55
-60
20
20
10
10
0
0
-65
-70
-75
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
8
-4
0
-80
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
-4
0
-24
-20
-16
-12
-8
ANALOG INPUT POWER (dBFS)
_______________________________________________________________________________________
-4
0
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
70
65
QA
49
SINAD (dB)
55
fIN = 10.0732MHz
IA
48
60
SNR (dB)
SFDR (dBc)
fIN = 10.0732MHz
QA
49
50
MAX5865 toc14
fIN = 10.0732MHz
75
50
MAX5865 toc13
80
ADC SIGNAL-TO-NOISE AND DISTORTION RATIO
vs. SAMPLING RATE
MAX5865 toc15
ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT POWER
47
50
48
IA
47
46
45
40
46
45
35
44
30
-24
-16
-12
-8
-4
24
26
28
30
32
34
36
38
22
40
24
26
28
30
32
34
36
38
ANALOG INPUT POWER (dBFS)
SAMPLING RATE (MHz)
SAMPLING RATE (MHz)
ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING RATE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
fIN = 10.0732MHz
75
50
49
IA
-65
SNR (dB)
70
SFDR (dBc)
-60
40
MAX5865 toc18
80
MAX5865 toc17
fIN = 10.0732MHz
-55
THD (dB)
45
22
0
MAX5865 toc16
-50
-20
65
48
QA
47
-70
60
-75
55
-80
50
46
fIN = 10.0732MHz
22
24
26
28
30
32
34
36
38
40
45
22
24
26
28
30
32
34
36
38
30
40
40
45
50
55
60
65
70
CLOCK DUTY CYCLE (%)
ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
49
fIN = 10.0732MHz
-62
-64
QA
80
MAX5865 toc20
MAX5865 toc19
-60
fIN = 10.0732MHz
75
-66
IA
47
70
SFDR (dBc)
THD (dB)
48
-68
-70
-72
-76
55
-78
fIN = 10.0732MHz
45
50
-80
30
35
40
45
65
60
-74
46
MAX5865 toc21
SAMPLING RATE (MHz)
50
SINAD (dB)
35
SAMPLING RATE (MHz)
50
55
60
CLOCK DUTY CYCLE (%)
65
70
30
50
60
40
CLOCK DUTY CYCLE (%)
70
30
40
50
60
CLOCK DUTY CYCLE (%)
_______________________________________________________________________________________
70
9
MAX5865
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
ADC GAIN ERROR
vs. TEMPERATURE
1.6
GAIN ERROR (%FS)
0.4
1.8
0.2
0
-0.2
-0.4
1.2
1.0
0.8
0.6
0.4
-0.8
0.2
-1.0
-15
10
35
60
85
Rx MODE ONLY
IDD
20
15
10
IOVDD
5
0
-40
0
-40
-15
10
35
60
22
85
26
30
34
38
TEMPERATURE (°C)
TEMPERATURE (°C)
SAMPLING RATE (MHz)
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING RATE
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT POWER
75
74
68
66
64
SFDR (dBc)
SFDR (dBc)
70
fOUT = 2MHz
80
70
70
72
MAX5865 toc27
76
90
MAX5865 toc26
fOUT = fCLK/10
78
80
MAX5865 toc25
80
SFDR (dBc)
1.4
-0.6
25
SUPPLY CURRENT (mA)
0.6
MAX5865 toc23
0.8
OFFSET ERROR (%FS)
2.0
MAX5865 toc22
1.0
SUPPLY CURRENT
vs. SAMPLING RATE
MAX5865 toc24
ADC OFFSET ERROR
vs. TEMPERATURE
65
60
60
50
55
40
62
26
28
30
32
34
36
38
0
40
5
10
15
-20
-15
-10
-5
SAMPLING RATE (MHz)
FREQUENCY (MHz)
OUTPUT POWER (dBFS)
DAC CHANNEL-ID SPECTRAL PLOT
DAC CHANNEL-QD SPECTRAL PLOT
DAC CHANNEL-ID TWO-TONE
SPECTRAL PLOT
-30
fID
-40
-50
-60
fQD = 5.498MHz
-20
AMPLITUDE (dB)
-20
0
-10
-30
fQD
0
-40
-50
-60
-20
-50
-60
-70
-80
-80
-80
-90
-90
-90
-100
-100
-100
10
15
0
5
10
FREQUENCY (MHz)
15
f2
-40
-70
FREQUENCY (MHz)
f1
-30
-70
5
f1 = 4MHz, f2 = 4.5MHz, -7dBFS
-10
AMPLITUDE (dB)
fID = 5.498MHz
MAX5865 toc29
0
-10
0
-25
-30
20
0.5
4.0
7.5
11.0
14.5
FREQUENCY (MHz)
______________________________________________________________________________________
18.0
0
MAX5865 toc30
24
MAX5865 toc28
22
10
30
50
60
AMPLITUDE (dB)
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
SUPPLY CURRENT
vs. SAMPLING RATE
f2
-40
-50
-60
-70
-80
IDD
0.4
0.3
0.2
20
INL (LSB)
SUPPLY CURRENT (mA)
f1
-30
15
10
0.1
0
-0.1
-0.2
5
-0.3
IOVDD
-0.4
-90
-0.5
0
-100
7.5
11.0
14.5
18.0
22
24
26
28
30
32
34
36
0
40
38
32
64
0.3
0.8
0.6
0.4
0.1
0.2
INL (LSB)
0.2
0
MAX5865 toc36
1.0
MAX5865 toc35
0.4
128 160 192 224 256
DAC INTEGRAL NONLINEARITY
ADC DIFFERENTIAL NONLINEARITY
0.5
96
DIGITAL OUTPUT CODE
SAMPLING RATE (MHz)
FREQUENCY (MHz)
0
-0.1
-0.2
-0.2
-0.4
-0.3
-0.6
-0.4
-0.8
-1.0
-0.5
0
32
64
96
0
128 160 192 224 256
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
DIGITAL INPUT CODE
DAC DIFFERENTIAL NONLINEARITY
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
0.520
MAX5865 toc37
0.5
0.4
0.3
MAX5865 toc38
4.0
DNL (LSB)
VREFP - VREFN
0.515
0.2
VREFP - VREFN (V)
0.5
DNL (LSB)
AMPLITUDE (dB)
-20
Xcvr MODE
25
0.5
MAX5865 toc33
f1 = 4MHz, f2 = 4.5MHz, -7dBFS
-10
ADC INTEGRAL NONLINEARITY
30
MAX5865 toc31
0
MAX5865 toc34
DAC CHANNEL-QD TWO-TONE
SPECTRAL PLOT
0.1
0
-0.1
0.510
-0.2
0.505
-0.3
-0.4
-0.5
0.500
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________
11
MAX5865
Typical Operating Characteristics (continued)
(VDD = DVDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL ≈ 10pF on all digital outputs, fCLK = 40MHz 50% duty cycle, ADC
input amplitude = -0.5dBFS, DAC output amplitude = 0dBFS, differential ADC input, differential DAC output, CREFP = CREFN =
CCOM = 0.33µF, Xcvr mode, TA = +25°C, unless otherwise noted.)
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
MAX5865
Pin Description
PIN
NAME
1
REFP
2, 8, 43
VDD
Analog Supply Voltage. Bypass VDD to GND with a combination of a 2.2µF capacitor in parallel with a
0.1µF capacitor.
3
IA+
Channel IA Positive Analog Input. For single-ended operation, connect signal source to IA+.
4
IA-
Channel IA Negative Analog Input. For single-ended operation, connect IA- to COM.
5, 7, 12, 37,
42
GND
Analog Ground. Connect all pins to GND ground plane.
6
CLK
Conversion Clock Input. Clock signal for both ADCs and DACs.
9
QA-
Channel QA Negative Analog Input. For single-ended operation, connect QA- to COM.
10
QA+
Channel QA Positive Analog Input. For single-ended operation, connect signal source to QA+.
11, 33, 39
VDD
Analog Supply Voltage. Connect to VDD power plane as close to the device as possible.
13–16, 19–22
DA0–DA7
17
OGND
Output Driver Ground
18
OVDD
Output Driver Power Supply. Supply range from +1.8V to VDD to accommodate most logic levels.
Bypass OVDD to OGND with a combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
23–32
DD0–DD9
34
DIN
35
SCLK
36
CS
38
N.C.
40, 41
QD+, QD-
DAC Channel-QD Differential Voltage Output
44, 45
ID-, ID+
DAC Channel-ID Differential Voltage Output
46
REFIN
Reference Input. Connect to VDD for internal reference.
47
COM
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
48
REFN
Negative Reference I/O. Conversion range is ±(VREFP - VREFN). Bypass REFN to GND with a 0.33µF
capacitor.
—
EP
12
FUNCTION
Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
ADC Tri-State Digital Output Bits. DA7 is the most significant bit (MSB), and DA0 is the least
significant bit (LSB).
DAC Digital Input Bits. DD9 is the MSB, and DD0 is the LSB.
3-Wire Serial Interface Data Input. Data is latched on the rising edge of the SCLK.
3-Wire Serial Interface Clock Input
3-Wire Serial Interface Chip Select Input. Apply logic low enables the serial interface.
No Connection
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
The MAX5865 integrates dual 8-bit receive ADCs and
dual 10-bit transmit DACs while providing ultra-low
power and highest dynamic performance at a conversion rate of 40Msps. The ADCs’ analog input amplifiers
are fully differential and accept 1VP-P full-scale signals.
The DACs’ analog outputs are fully differential with
±400mV full-scale output range at 1.4V common mode.
The MAX5865 includes a 3-wire serial interface to control operating modes and power management. The serial interface is SPI™ and MICROWIRE™ compatible.
The MAX5865 serial interface selects shutdown, idle,
standby, transmit, receive, and transceiver modes.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
IA+
OUT
C2a
S4c
S1
OUT
IAS4b
C1b
C2b
S3b
S5b
S2b
INTERNAL
BIAS
COM
INTERNAL
BIAS
COM
HOLD
CLK
HOLD
TRACK
TRACK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
S5a
S2a
C1a
S3a
S4a
QA+
OUT
C2a
S4c
S1
MAX5865
OUT
QAS4b
C1b
C2b
S3b
S2b
INTERNAL
BIAS
S5b
COM
Figure 1. MAX5865 ADC Internal T/H Circuits
SPI is a trademark of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________
13
MAX5865
The MAX5865 can operate in FDD or TDD applications
by configuring the device for transmit, receive, or transceiver modes through a 3-wire serial interface. In TDD
mode, the digital bus for receive ADC and transmit
DAC can be shared to reduce the digital I/O to a single
10-bit parallel multiplexed bus. In FDD mode, the
MAX5865 digital I/O can be configured for an 18-bit,
parallel multiplexed bus to match the dual 8-bit ADC
and dual 10-bit DAC.
The MAX5865 features an internal precision 1.024V
bandgap reference that is stable over the entire powersupply and temperature ranges.
Detailed Description
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Dual 8-Bit ADC
The ADC uses a seven-stage, fully differential,
pipelined architecture that allows for high-speed conversion while minimizing power consumption. Samples
taken at the inputs move progressively through the
pipeline stages every half-clock cycle. Including the
delay through the output latch, the total clock-cycle
latency is 5 clock cycles for channel IA and 5.5 clock
cycles for channel QA. The ADC’s full-scale analog
input range is ±VREF with a common-mode input range
of VDD/2 ±0.2V. VREF is the difference between VREFP
and VREFN. See the Reference Configurations section
for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified functional diagram of the
ADC’s input T/H circuitry. In track mode, switches S1,
S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully
differential circuits sample the input signals onto the
two capacitors (C2a and C2b) through switches S4a
and S4b. S2a and S2b set the common mode for the
amplifier input, and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and
S5b are then opened before switches S3a and S3b
connect capacitors C1a and C1b to the output of the
amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b.
The amplifiers charge capacitors C1a and C1b to the
same values originally held on C2a and C2b. These values are then presented to the first-stage quantizers and
isolate the pipelines from the fast-changing inputs. The
wide input bandwidth T/H amplifiers allow the ADC to
track and sample/hold analog inputs of high frequencies (> Nyquist). Both ADC inputs (IA+, QA+, IA-, and
QA-) can be driven either differentially or single ended.
Match the impedance of IA+ and IA-, as well as QA+
and QA-, and set the common-mode voltage to midsupply (VDD/2) for optimum performance.
ADC Digital Output Data (DA0–DA7)
DA0–DA7 are the ADCs’ digital logic outputs. The logic
level is set by OVDD from 1.8V to VDD. The digital output coding is offset binary (Table 1, Figure 2). The
capacitive load on digital outputs DA0–DA7 should be
kept as low as possible (<15pF) to avoid large digital
currents feeding back into the analog portion of the
MAX5865 and degrading its dynamic performance.
Buffers on the digital outputs isolate them from heavy
capacitive loads. Adding 100Ω resistors in series with
the digital outputs close to the MAX5865 helps improve
ADC performance. Refer to the MAX5865 EV kit
schematic for an example of the digital outputs driving
a digital buffer through 100Ω series resistors.
Table 1. Output Codes vs. Input Voltage
DIFFERENTIAL
INPUT VOLTAGE
14
DIFFERENTIAL INPUT
(LSB)
OFFSET BINARY
(DA7–DA0)
OUTPUT DECIMAL
CODE
VREF ×
127
128
127
(+full scale - 1LSB)
1111 1111
255
VREF ×
126
128
126
(+full scale - 2LSB)
1111 1110
254
VREF ×
1
128
+1
1000 0001
129
VREF ×
0
128
0
(bipolar zero)
1000 0000
128
− VREF ×
1
128
-1
0111 1111
127
− VREF ×
127
128
-127
(-full scale + 1LSB)
0000 0001
1
− VREF ×
128
128
-128
(-full scale)
0000 0000
0
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
1 LSB =
2 x VREF
256
VREF = VREFP - VREFN
VREF
VREF
1000 0001
1000 0000
0111 1111
(COM)
VREF
OFFSET BINARY OUTPUT CODE (LSB)
VREF
1111 1111
1111 1110
1111 1101
0000 0011
0000 0010
0000 0001
0000 0000
-128 -127 -126 -125
-1
0
+1
+125 +126 +127 +128
(COM)
INPUT VOLTAGE (LSB)
puts. CHI data is updated on the rising edge and CHQ
data is updated on the falling edge of the CLK.
Including the delay through the output latch, the total
clock-cycle latency is 5 clock cycles for CHI and 5.5
clock cycles for CHQ.
Dual 10-Bit DAC
The 10-bit DACs are capable of operating with clock
speeds up to 40MHz. The DAC’s digital inputs,
DD0–DD9, are multiplexed on a single 10-bit bus. The
voltage reference determines the data converters’ fullscale output voltages. See the Reference Configurations
section for setting reference voltage. The DACs utilize a
current-array technique with a 1mA (with 1.024V reference) full-scale output current driving a 400Ω internal
resistor resulting in a ±400mV full-scale differential output voltage. The MAX5865 is designed for differential
output only and is not intended for single-ended application. The analog outputs are biased at 1.4V common
mode and designed to drive a differential input stage
with input impedance ≥70kΩ. This simplifies the analog
interface between RF quadrature upconverters and the
MAX5865. RF upconverters require a 1.3V to 1.5V common-mode bias. The internal DC common-mode bias
eliminates discrete level setting resistors and code-generated level-shifting while preserving the full dynamic
range of each transmit DAC. Table 2 shows the output
voltage vs. input code.
Figure 2. ADC Transfer Function
5 CLOCK-CYCLE LATENCY (CHI), 5.5 CLOCK-CYCLE LATENCY (CHQ)
CHI
CHQ
CLK
tDOQ
DA0–DA7
tDOI
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
Figure 3. ADC System Timing Diagram
______________________________________________________________________________________
15
MAX5865
ADC System Timing Requirements
Figure 3 shows the relationship between the clock, analog inputs, and the resulting output data. Channel IA
(CHI) and channel QA (CHQ) are simultaneously sampled on the rising edge of the clock signal (CLK) and
the resulting data is multiplexed at the DA0–DA7 out-
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Table 2. DAC Output Voltage vs. Input Codes (Internal Reference Mode VREFDAC =
1.024V, External Reference Mode VREFDAC = VREFIN)
OFFSET BINARY
(DD0–DD9)
INPUT DECIMAL CODE
VREFDAC 1023
×
2.56
1023
11 1111 1111
1023
VREFDAC 1021
×
2.56
1023
11 1111 1110
1022
3
VREFDAC
×
2.56
1023
10 0000 0001
513
1
VREFDAC
×
2.56
1023
10 0000 0000
512
DIFFERENTIAL OUTPUT VOLTAGE
− VREFDAC
2.56
− VREFDAC
2.56
− VREFDAC
2.56
×
1
1023
01 1111 1111
511
×
1021
1023
00 0000 0001
1
×
1023
1023
00 0000 0000
0
CLK
tDHQ
tDSQ
DD0–DD9
Q: N-2
I: N-1
Q: N-1
tDSI
Q: N
I: N
I: N+1
tDHI
ID
N-2
N-1
N
QD
N-2
N-1
N
Figure 4. DAC System Timing Diagram
DAC Timing
Figure 4 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel (ID) is
latched on the falling edge of the clock signal, and Qchannel (QD) data is latched on the rising edge of the
clock signal. Both I and Q outputs are simultaneously
updated on the next rising edge of the clock signal.
16
3-Wire Serial Interface and
Operation Modes
The 3-wire serial interface controls the MAX5865 operation modes. Upon power-up, the MAX5865 must be programmed to operate in the desired mode. Use the 3-wire
serial interface to program the device for the shutdown,
idle, standby, Rx, Tx, or Xcvr mode. An 8-bit data register
sets the operation modes as shown in Table 3. The serial
interface remains active in all six modes.
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
MAX5865
Table 3. MAX5865 Operation Modes
D7
(MSB)
D6
D5
D4
D3
D2
D1
D0
Shutdown
Device shutdown. REF is off, ADCs are
off, and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
X
X
X
X
X
0
0
0
Idle
REF and CLK are on, ADCs are off,
and the ADC bus is tri-stated; DACs
are off and the DAC input bus must be
set to zero or OVDD.
X
X
X
X
X
0
0
1
Rx
REF is on, ADCs are on; DACs are off,
and the DAC input bus must be set to
zero or OVDD.
X
X
X
X
X
0
1
0
Tx
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are on.
X
X
X
X
X
0
1
1
REF is on, ADCs and DACs are on.
X
X
X
X
X
1
0
0
REF is on, ADCs are off, and the ADC
bus is tri-stated; DACs are off and the
DAC input bus must be set to zero or
OVDD.
X
X
X
X
X
1
0
1
FUNCTION
Xcvr
Standby
DESCRIPTION
X = Don’t care.
Shutdown mode offers the most dramatic power savings by shutting down all the analog sections of the
MAX5865 and placing the ADCs’ digital outputs in tristate mode. When the ADCs’ outputs transition from tristate to on, the last converted word is placed on the
digital outputs. The DACs’ digital bus inputs must be
zero or OVDD because the bus is not internally pulled
up. The DACs’ previously stored data is lost when coming out of shutdown mode. The wake-up time from shutdown mode is dominated by the time required to
charge the capacitors at REFP, REFN, and COM. In
internal reference mode and buffered external reference mode, the wake-up time is typically 40µs to enter
Xcvr mode, 20µs to enter Rx mode, and 40µs to enter
Tx MODE.
In idle mode, the reference and clock distribution circuits are powered, but all other functions are off. The
ADCs’ outputs are forced to tri-state. The DACs’ digital
bus inputs must be zero or OVDD, because the bus is
not internally pulled up. The wake-up time from the idle
mode is 10µs required for the ADCs and DACs to be
fully operational. When the ADCs’ outputs transition
from tri-state to on, the last converted word is placed
on the digital outputs. In the idle mode, the supply cur-
rent is lowered if the clock input is set to zero or OVDD;
however, the wake-up time extends to 40µs.
In standby mode, only the ADCs’ reference is powered;
the rest of the device’s functions are off. The pipeline
ADCs are off and DA0 to DA7 are in tri-state mode. The
DACs’ digital bus inputs must be zero or OV DD
because the bus is not internally pulled up. The wakeup time from standby mode to the Xcvr mode is dominated by the 40µs required to activate the pipeline
ADCs and DACs. When the ADC outputs transition from
tri-state to active, the last converted word is placed on
the digital outputs.
The serial digital interface is a standard 3-wire connection compatible with SPI/QSPI™/MICROWIRE/DSP
interfaces. Set CS low to enable the serial data loading
at DIN. Following CS high-to-low transition, data is shifted synchronously, MSB first, on the rising edge of the
serial clock (SCLK). After 8 bits are loaded into the serial input register, data is transferred to the latch. CS
must transition high for a minimum of 80ns before the
next write sequence. The SCLK can idle either high or
low between transitions. Figure 5 shows the detailed
timing diagram of the 3-wire serial interface.
QSPI is a trademark of Motorola, Inc.
______________________________________________________________________________________
17
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
tCSW
CS
tCSS
tCP
tCH
tCL
tCS
SCLK
tDS
DIN
LSB
MSB
tDH
Figure 5. 3-Wire Serial Interface Timing Diagram
CS
SCLK
DIN
8-BIT DATA
tWAKE, SD, ST_ (Rx) OR tENABLE, Rx
DAO–DA7
ID/QD
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
DAC ANALOG OUTPUT. OUTPUT
SETTLES TO 10 LSB ERROR
tWAKE, SD, ST_ (Tx) OR tENABLE TX
Figure 6. MAX5865 Mode Recovery Timing Diagram
Mode Recovery Timing
Figure 6 shows the mode recovery timing diagram.
tWAKE is the wake-up time when exiting shutdown, idle,
or standby mode and entering into Rx, Tx, or Xcvr
mode. tENABLE is the recovery time when switching
between any Rx, Tx, or Xcvr mode. tWAKE or tENABLE is
the time for the ADC to settle within 1dB of specified
SINAD performance and DAC settling to 10 LSB error.
tWAKE or tENABLE times are measured after the 8-bit
serial command is latched into the MAX5865 by CS
transition high. tENABLE for Xcvr mode is dominated by
the DAC wake-up time. The recovery time is 10µs to
switch between Xcvr, Tx, or Rx modes. The recovery
time is 40µs to switch from shutdown or standby mode
to Xcvr mode.
System Clock Input (CLK)
CLK input is shared by both the ADCs and DACs. It
accepts a CMOS-compatible signal level set by OVDD
from 1.8V to VDD. Since the interstage conversion of the
device depends on the repeatability of the rising and
falling edges of the external clock, use a clock with low
jitter and fast rise and fall times (<2ns). Specifically,
sampling occurs on the rising edge of the clock signal,
requiring this edge to provide the lowest possible jitter.
Any significant clock jitter limits the SNR performance
of the on-chip ADCs as follows:


1
SNR = 20 × log 

2
×
π
×
t
×
t

IN
AJ 
where fIN represents the analog input frequency and
tAJ is the time of the clock jitter.
18
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Reference Configurations
The MAX5865 features an internal precision 1.024V
bandgap reference that is stable over the entire power
supply and temperature range. The REFIN input provides two modes of reference operation. The voltage at
REFIN (VREFIN) sets reference operation mode (Table 4).
In internal reference mode, connect REFIN to V DD.
VREF is an internally generated 0.512V. COM, REFP,
and REFN are low-impedance outputs with VCOM =
VDD/2, VREFP = VDD/2 + VREF/2, and VREFN = VDD/2 VREF/2. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor.
In buffered external reference mode, apply 1.024V
±10% at REFIN. In this mode, COM, REFP, and REFN
are low-impedance outputs with VCOM = VDD/2, VREFP
= VDD/2 + VREFIN/4, and VREFN = VDD/2 - VREFIN/4.
Bypass REFP, REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a 0.1µF capacitor. In this mode, the DAC’s full-scale output voltage
and common-mode voltage are proportional to the
external reference. For example, if the V REFIN is
increased by 10% (max), the DACs’ full-scale output
voltage is also increased by 10% or to ±440mV, and
the common-mode voltage increases by 10%.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 7) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
provides a VDD/2 DC level shift to the input. A 1:1 transformer can be used, or a step-up transformer can be
selected to reduce the drive requirements. In general,
the MAX5865 provides better SFDR and THD with fully
differential input signals than single-ended signals,
especially for high-input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IA+, IA-, QA+, QA-) are balanced, and each of the
ADC inputs only requires half the signal swing compared to single-ended mode. Figure 8 shows an RF
transformer converting the MAX5865 DACs’ differential
analog outputs to single ended.
25Ω
IA+
0.1µF
22pF
VIN
COM
0.33µF
IA25Ω 22pF
MAX5865
Table 4. Reference Modes
VREFIN
REFERENCE MODE
>0. 8 x VDD
Internal reference mode. VREF is internally
generated to be 0.512V. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor.
1.024V ±10%
Buffered external reference mode. An
external 1.024V ±10% reference voltage
is applied to REFIN. VREF is internally
generated to be VREFIN/2. Bypass REFP,
REFN, and COM each with a 0.33µF
capacitor. Bypass REFIN to GND with a
0.1µF capacitor.
0.1µF
25Ω
QA+
0.1µF
22pF
VIN
0.33µF
0.1µF
QA25Ω 22pF
Figure 7. Balun-Transformer Coupled Single-Ended to
Differential Input Drive for ADCs
______________________________________________________________________________________
19
MAX5865
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX5865 clock input operates
with an OVDD/2 voltage threshold and accepts a 50%
±15% duty cycle.
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
MAX5865
Using Op-Amp Coupling
ID+
VOUT
MAX5865
ID-
QD+
VOUT
QD-
Figure 8. Balun-Transformer Coupled Differential to SingleEnded Output Drive for DACs
REFP
1kΩ
VIN
0.1µF
RISO
50Ω
INA+
100Ω
CIN
22pF
1kΩ
COM
REFN
0.1µF
RISO
50Ω
INA-
100Ω
CIN
22pF
REFP
VIN
0.1µF
1kΩ
MAX5865
RISO
50Ω
INB+
100Ω
1kΩ
REFN
CIN
22pF
0.1µF
RISO
50Ω
100Ω
INBCIN
22pF
Figure 9. Single-Ended Drive for ADCs
20
Drive the MAX5865 ADCs with op amps when a balun
transformer is not available. Figures 9 and 10 show the
ADCs being driven by op amps for AC-coupled singleended, and DC-coupled differential applications.
Amplifiers such as the MAX4354/MAX4454 provide
high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. Figure 10 can
also be used to interface with the DAC differential analog outputs to provide gain or buffering. The DAC differential analog outputs cannot be used in singleended mode because of the internally generated
1.4VDC common-mode level. Also, the DAC analog
outputs are designed to drive a differential input stage
with input impedance ≥70kΩ. If single-ended outputs
are desired, use an amplifier to provide differential to
single-ended conversion and select an amplifier with
proper input common-mode voltage range.
FDD and TDD Modes
The MAX5865 can be used in diverse applications
operating FDD or TDD modes. The MAX5865 operates
in Xcvr mode for FDD applications such as WCDMA3GPP (FDD) and 4G technologies. Also, the MAX5865
can switch between Tx and Rx modes for TDD applications like TD-SCDMA, WCDMA-3GPP (TDD),
IEEE802.11a/b/g, and IEEE802.16.
In FDD mode, the ADC and DAC operate simultaneously.
The ADC bus and DAC bus are dedicated and must be
connected in 18-bit parallel (8-bit ADC and 10-bit DAC)
to the digital baseband processor. Select Xcvr mode
through the 3-wire serial interface and use the conversion
clock to latch data. In FDD mode, the MAX5865 uses
75.6mW power at fCLK = 40MHz. This is the total power
of the ADC and DAC operating simultaneously.
In TDD mode, the ADC and DAC operate independently. The ADC and DAC bus are shared and can be connected together, forming a single 10-bit parallel bus to
the digital baseband processor. Using the 3-wire serial
interface, select between Rx mode to enable the ADC
and Tx mode to enable the DAC. When operating in Rx
mode, the DAC does not transmit because the core is
disabled and in Tx mode, the ADC bus is tri-state. This
eliminates any unwanted spurious emissions and prevents bus contention. In TDD mode, the MAX5865 uses
63mW power in Rx mode at fCLK = 40MHz, and the
DAC uses 38.4mW in Tx mode.
Figure 11 illustrates the MAX5865 working with the
MAX2820 in TDD mode to provide a complete 802.11b
radio front-end solution. Because the MAX5865 DAC has
full differential analog outputs with a common-mode level
of 1.4V, and the ADC has wide-input common-mode
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
MAX5865
R4
600Ω
R5
600Ω
MAX5865
RISO
22Ω
R1
600Ω
INACIN
5pF
R2
600Ω
R6
600Ω
R7
600Ω
R8
600Ω
R9
600Ω
COM
R3
600Ω
RISO
22Ω
CIN
5pF
R10
600Ω
INA+
R11
600Ω
Figure 10. ADC DC-Coupled Differential Drive
CLK
ADC
MAX2391
QUADRATURE
DEMODULATOR
ADC
T/R
10 BIT
MAX2395
QUADRATURE
TRANSMITTER
DAC
DIGITAL BASEBAND
PROCESSOR
ADC
OUTPUT
MUX
DAC
INPUT
MUX
DAC
MAX5865
SERIAL BUS
Figure 11. Typical Application Circuit for TDD
______________________________________________________________________________________________________
21
range, it can interface directly with RF transceivers while
eliminating discrete components and amplifiers used for
level-shifting circuits. Also, the DAC’s full dynamic range
is preserved because the internally generated commonmode level eliminates code-generated level shifting or
attenuation due to resistor level shifting. The MAX5865
ADC has 1VP-P full-scale range and accepts input common-mode levels of VDD/2 (±200mV). These features
simplify the analog interface between RF quadrature
demodulator and ADC while eliminating discrete gain
amplifiers and level-shifting components.
Grounding, Bypassing, and
Board Layout
The MAX5865 requires high-speed board layout design
techniques. Refer to the MAX5865 EV kit data sheet for
a board layout reference. Locate all bypass capacitors
as close to the device as possible, preferably on the
same side of the board as the device, using surfacemount devices for minimum inductance. Bypass VDD to
GND with a 0.1µF ceramic capacitor in parallel with a
2.2µF capacitor. Bypass OVDD to OGND with a 0.1µF
ceramic capacitor in parallel with a 2.2µF capacitor.
Bypass REFP, REFN, and COM each to GND with a
0.33µF ceramic capacitor. Bypass REFIN to GND with
a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical location of the analog ground (GND) and the digital output
driver ground (OGND) on the device package. Connect
the MAX5865 exposed backside paddle to the GND
plane. Join the two ground planes at a single point
such that the noisy digital ground currents do not interfere with the analog ground plane. The ideal location
for this connection can be determined experimentally at
a point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
Route high-speed digital signal traces away from sensitive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90° turns.
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static linearity parameters for the device are measured using
the end-point method. (DAC Figure 12a).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 12b).
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
7
6
ANALOG OUTPUT VALUE
6
ANALOG OUTPUT VALUE
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
5
4
AT STEP
011 (1/2 LSB )
3
2
AT STEP
001 (1/4 LSB )
1
DIFFERENTIAL LINEARITY
ERROR (-1/4 LSB)
4
3
1 LSB
2
DIFFERENTIAL
LINEARITY ERROR (+1/4 LSB)
1
0
0
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 12a. Integral Nonlinearity
22
1 LSB
5
110
111
000
001
010
011
100
101
DIGITAL INPUT CODE
Figure 12b. Differential Nonlinearity
___________________________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of deviation between the measured transition point and the
ideal transition point with the offset error removed.
ADC Dynamic Parameter Definitions
MAX5865
DAC Offset Error
Offset error (Figure 12a) is the difference between the
ideal and actual offset point. The offset point is the output value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
CLK
ANALOG
INPUT
tAD
tAJ
SAMPLED
DATA (T/H)
T/H
TRACK
HOLD
TRACK
Aperture Jitter
Figure 13 depicts the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Figure 13. T/H Aperture Timing
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 13).
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
SNR(max) = 6.02dB x N + 1.76dB (in dB)
In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral
components to the Nyquist frequency excluding the
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ENOB = (SINAD - 1. 76) / 6.02
 (V22 + V32 + V42 + V52 + V62
THD = 20log 
V1

)


where V1 is the fundamental amplitude and V2–V6 are
the amplitudes of the 2nd- through 6th-order harmonics.
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious
component, excluding DC offset.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ±f2), (2 ✕ f1), (2 ✕ f2), (2 ✕ f1 ±f2), (2 ✕ f2
±f1). The individual input tone levels are at -7dBFS.
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst third-order intermodulation product relative to the input power of either input
tone when two tones, f 1 and f 2 , are present at the
inputs. The 3rd-order intermodulation products are (2 x
f1 ±f2), (2 ✕ f2 ±f1). The individual input tone levels are
at -7dBFS.
______________________________________________________________________________________
23
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed ±5%.

THD = 20log 


(V22
+ V32
+ ...+ Vn2 )
V1




where V1 is the fundamental amplitude and V2 through
Vn are the amplitudes of the 2nd through nth harmonic
up to the Nyquist frequency.
VDD
N.C.
GND
37
35
3
34
4
33
GND
CLK
5
32
GND
VDD
7
30
8
29
QAQA+
VDD
9
28
10
27
11
26
GND
12
25
6
31
DIN
VDD
DD9
DD8
DD7
DD6
DD5
DD4
DD3
DD2
24
23
22
21
CS
SCLK
DA7
DD0
DD1
20
DA5
DA6
19
18
17
16
MAX5865
QFN
Chip Information
TRANSISTOR COUNT: 16,765
PROCESS: CMOS
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
24
38
39
40
GND
QDQD+
41
42
43
ID+
IDVDD
45
44
COM
REFIN
47
46
REFPN
48
36
2
15
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
1
14
DAC Dynamic Parameter Definitions
REFP
VDD
IA+
IA-
13
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the fullpower bandwidth frequency.
TOP VIEW
DA1
DA2
DA3
OGND
OVDD
DA4
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
Pin Configuration
DA0
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
______________________________________________________________________________________
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
32, 44, 48L QFN .EPS
D2
D
CL
D/2
b
D2/2
k
E/2
E2/2
E
CL
(NE-1) X e
E2
k
L
DETAIL A
e
(ND-1) X e
CL
CL
L
L
e
A1
A2
e
A
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
B
1
2
______________________________________________________________________________________
25
MAX5865
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX5865
Ultra-Low-Power, High-DynamicPerformance, 40Msps Analog Front End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
EXPOSED PAD VARIATIONS
** NOTE: T4877-1 IS A CUSTOM 48L PKG. WITH 4 LEADS DEPOPULATED.
TOTAL NUMBER OF LEADS ARE 44.
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48L QFN THIN, 7x7x0.8 mm
APPROVAL
DOCUMENT CONTROL NO.
21-0144
REV.
B
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
26 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.