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GE
Intelligent Platforms
Hardware Reference Manual
IPN250 6U OpenVPX GPGPU Processor
Edition 3
Publication No. IPN250-HRM/3
Document History
2
3
Edition
First
Date
July 2010
August 2010
Board Artwork Revision
Rev 1
Rev 3
February 2011 Rev 3
3 + Addendum March 2011 Addendum section 4.3.6
3 + Errata March 2011 Errata section 4.7
NOTE
This manual only describes boards with artwork revision 3. For infomation on boards with artwork revision 1, see the first edition, available in the on-line archive.
Waste Electrical and Electronic Equipment (WEEE) Returns
GE Intelligent Platforms Limited is registered with an approved Producer Compliance Scheme
(PCS) and, subject to suitable contractual arrangements being in place, will ensure WEEE is processed in accordance with the requirements of the WEEE Directive.
GE Intelligent Platforms Limited. will evaluate requests to take back products purchased by our customers before August 13, 2005 on a case by case basis. A WEEE management fee may apply.
Publication No. IPN250-HRM/3 2
About This Manual
Conventions
Numbers
All numbers are expressed in decimal, except addresses and memory or register data, which are expressed in hexadecimal. Where confusion may occur, decimal numbers have a “D” subscript and binary numbers have a “b” subscript. The prefix “0x” shows a hexadecimal number, following the ‘C’ programming language convention. Thus:
One dozen = 12D = 0x0C = 1100b
The multipliers “k”, “M” and “G” have their conventional scientific and engineering meanings of *10
3
, *10
6
and *10
9 respectively. The only exception to this is in the description of the size of memory areas, when “K”, “M” and “G” mean *2
10
, *2
20
and *2
30
respectively.
NOTE
When describing transfer rates, “k”, “M” and “G” mean *10
3
, *10
6
and *10
9
not *2
10
, *2
20
and *2
30
.
Multiple bit fields are numbered from 0 to n, where 0 is the LSB and n is the MSB.
Text
Signal names ending with a tilde (~) denote active low signals; all other signals are active high.
Notices
This guide uses the following types of notice:
NOTE
Notes call attention to important features or instructions.
WARNING
Warnings alert you to the risk of severe personal injury.
CAUTION
Cautions alert you to system danger or loss of data.
TIP
Tips give helpful hints on how to achieve things.
LINK
Links take you to other documents or web sites. The purple link color may also be used within a body of text or paragraph to indicate a link (or hyperlink) to a different part of the same document.
Publication No. IPN250-HRM/3 About This Manual 3
Further Information
GE Manuals
This document is distributed via CD ROM and the internet. The CD ROM allows privileged access to an Internet resource containing the latest updated documents. Alternatively, you may register for access to all manuals via the web site whose link is given below.
LINK
IPN250RTM Hardware Reference Manual, publication number IPN250RTM-HRM.
LINK
FABRTMP1 Hardware Reference Manual, publication number FABRTMP1-HRM.
LINK
SCVPX6U Hardware Reference Manual, publication number SCVPX6U-HRM.
LINK
VPX I/O Modules Hardware Reference Manual, publication number VPXIOM-0HH.
GE Websites
Information regarding all GE Intelligent Platforms products can be found on the following website:
LINK http://www.ge-ip.com/products/family/embedded-systems .
Third Party Manuals
ANSI/VITA 46.0‐2007 VPX Baseline Standard.
VITA 65 OpenVPX System Specification Rev 1.04 Jan 1 2010.
IEEE 1101.1‐1998 IEEE Standard for Mechanical Core Specifications for
Microcomputers.
IEEE 1101.2‐1992 Conduction cooled VME mechanics.
IEEE 1101.10‐1996 Additional Mechanical Specifications.
NVIDIA GT215 Datasheet ‐ DS‐04802‐001_v01 (August 2009)
These are the latest versions at time of writing; check web sites for later updates.
NOTE
Registration may be required for access to some of these documents.
4 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Third Party Web Sites
LINK http://www.vita.com/vso for standards.
LINK http://www.intel.com
for processor and chip set information.
LINK http://www.nvidia.com
for GPU information.
Technical Support
Technical assistance contact details can be found on the web site Support Locator page. The appropriate product category is headed “DSP, SBCs, Multiprocessors and Graphics (formerly Radstone)”
LINK http://www.ge-ip.com/support/embeddedsupport/locator .
Queries will be logged on the Technical Support database and allocated a unique
Service Request (SR) number for use in future correspondence.
Alternatively, you may also contact GE Intelligent Platformsʹ Technical Support via:
LINK [email protected]
.
TELEPHONE
+44 (0) 1327 322760
Returns
If you need to return a product, there is a Return Materials Authorization (RMA) request form that can be printed out and filled in, available via the web site
Repairs page.
LINK http://www.ge-ip.com/support/embeddedsupport/rmalocator .
Follow the “Download
RMA Request Form (Word Doc)” hyperlink under “DSP,
SBCs, Multiprocessors and Graphics (Formerly Radstone)”.
Do not return products without first contacting the factory.
Publication No. IPN250-HRM/3 About This Manual 5
Table of Contents
6 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Publication No. IPN250-HRM/3 Table of Contents 7
8 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
List of Figures
Publication No. IPN250-HRM/3 List of Figures 9
List of Tables
10 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Publication No. IPN250-HRM/3 List of Tables 11
1 • Introduction
GE Intelligent Platforms’ IPN250 is the first in a new family of rugged COTS,
GPGPU, 6U OpenVPX processors aimed at signal, image, data processing and display applications that require best Size, Weight and Power (SWaP) for deployed Intelligence, Reconnaissance and Surveillance (ISR) payloads on airborne, land based and underwater vehicles.
IPN250 is an integrated PC‐like platform that includes an Intel Core2Duo CPU
(Montevina chip set), an Nvidia GT215‐350
1
CUDA GPU and PCIe, 10GE and
GbE switched fabrics to support high speed data interfaces as well as multi‐board system scaling within a standard OpenVPX system architecture.
The IPN250 can be used as a stand alone solution or in conjunction with a variety of GEIP and third party 6U OpenVPX SBCs and peripherals, including the GEIP
NPN240 dual node Nvidia GT240 peripheral GPGPU processor card and the
GEIP GBX460 Switch Fabric module.
The IPN250 is supplied with a BIOS supporting various 32‐ and 64‐bit operating systems such as Windows 7 and Linux (CentOS, Ubuntu, Red Hawk, etc).
1.1 Features
• 2.26 GHz Intel Core2 Duo Processor (Penryn)
• Two DDR3 SDRAM banks ‐ up to 4 GBytes per bank
• Nvidia GT215‐350 96‐core CUDA‐enabled Graphics Processor
• Dual 10G Ethernet data plane
• Dual 8‐lane 2.5 Gbps Gen1 PCIe expansion plane
• 8 GByte SATA Flash Disk
• Ethernet/Serial/USB/SATA interfaces
Figure 1-1 IPN250
1. The GT215 GPU is commercially available on Nvidia’s family of GeForce GT240 PCIe cards.
12 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
1.2 Safety Notices
The following general safety precautions represent warnings of certain dangers of which GE Intelligent Platforms is aware. Failure to comply with these or with specific Warnings and/or Cautions elsewhere in this manual violates safety standards of design, manufacture and intended use of the equipment. GEIP assumes no liability for the user’s failure to comply with these requirements.
Also follow all warning instructions contained in associated system equipment manuals.
WARNING
To minimize shock hazard, connect the equipment chassis and rack/enclosure to an electrical ground. If AC power is supplied to the rack/enclosure, the power jack and mating plug of the power cable must meet IEC safety standards.
1.2.1 Flammability
The IPN250 circuit board is made by a UL‐recognized manufacturer and has a flammability rating of UL94V‐1.
1.2.2 EMI/EMC Regulatory Compliance
CAUTION
This equipment generates, uses and can radiate electromagnetic energy. It may cause or be susceptible to EMI if not installed and used in a cabinet with adequate EMI protection.
The IPN250 is designed using good EMC practices and, when used in a suitably
EMC‐compliant chassis, should maintain the compliance of the total system. The
IPN250 also complies with EN60950 (product safety), which is essentially the requirement for the Low Voltage Directive (73/23/EEC).
Air‐cooled build levels of the IPN250 are designed for use in systems meeting
VDE class B, EN and FCC regulations for EMC emissions and susceptibility.
Conduction‐cooled build levels of the IPN250 are designed for integration into
EMC hardened cabinets/boxes.
1.2.3 Cooling
CAUTION
The IPN250 requires air-flow of at least 300 feet/minute for build levels 1 and 2, and at least
600 feet/minute for build level 3. If a conduction-cooled (level 4 or 5) IPN250 is operating on an extender card, it requires air-flow of at least 300 feet/minute across it.
1.2.4 Safety Ground
CAUTION
The IPN250 metalwork, heatsink and safety ground are connected to signal ground.
The IPN250 does not comply with rules 3-1 and 3-15 of ANSI/VITA 46.0.
Publication No. IPN250-HRM/3 Introduction 13
1.2.5 Handling
CAUTION
Only handle the IPN250 by the edges or front panel
Figure 1-2 ESD Label (Present on Board Packaging)
1.2.6 Heatsink
CAUTION
Do not remove the heatsink. There are no user-alterable components underneath the heatsink, so users should have no reason to remove it. Users should not attempt reattachment of the heatsink, as this requires precise torque on the screws attaching the heatsink to the PCB. Over-tightening the screws may cause the heatsink to damage components beneath it. Removal and re attachment of the heatsink should only be carried out by the factory.
14 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
2 • Unpacking
On receipt of the shipping container, if there is any evidence of physical damage, the Terms and Conditions of Sale (supplied with your delivery) give information on what to do. If you need to return the product, contact your local GEIP Sales
Office or Agent.
The IPN250 is sealed into an antistatic bag and housed in a padded cardboard box. Failure to use the correct packaging when storing or shipping the board may invalidate the warranty.
2.1 Box Contents Checklist
1. IPN250 in antistatic packaging.
2. Manual CD‐ROM (design may vary).
3. Embedded Software License (GFJ‐353).
Figure 2-1 Box Contents
3
Manuals CD-ROM ducts 2010
GE
Intell
©2010 GE Intelligent
Platforms,
Platf orms
2
D-RO
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Manu
Digita als C essin ducts
2010
1
Publication No. IPN250-HRM/3 Unpacking 15
2.2 Identifying Your Board
The IPN250 is identified by labels at strategic positions. These can be cross‐ checked against the Advice Note provided with your delivery.
Identification labels, similar to that shown in Figure 2‐2, attached to the shipping box and the antistatic bag provide identical information: IPN250 product code, product description, equipment number and board revision.
Figure 2-2 Product Label (Packaging)
On the board within the antistatic bag, there is an identifying label similar to the example shown in Figure 2‐3 attached to the PCB.
Figure 2-3 Product Label (Product)
On the conduction‐cooled version of the board (build level 4), there is also a label similar to the example shown in Figure 2‐4 attached to the front panel.
Figure 2-4 Product Label (Conduction-cooled Product)
See the
section in Appendix A for more details on the product code (IPN250‐xxxxxxxxx).
16 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
3 • Installation and Power Up/Reset
Review the
Safety Notices section before installing the board. The following
notices also apply:
CAUTION
Consult the enclosure documentation to ensure that the IPN250's power requirements (see overleaf) are compatible with those supplied by the backplane.
3.1 Configuration
All user‐configurable options are selected via backplane strapping signals (see
for more details). There are no user‐configurable links.
3.2 Board Keying
The VPX specification defines three keying pins. The keying pin at Position 1
(adjacent to the P0 connector) defines the voltage present on the Vs1 and Vs2 supply pins on the backplane J0 connector. The IPN250 uses these supplies, and the Open VPX specification requires 315° keying in Position 1.
The keying pins at Position 2 (adjacent to the P3 connector) and Position 3
(adjacent to the P6 connector) define slot‐specific keying. The IPN250 is delivered with module keying devices of the unkeyed type in these positions to allow the board to be fitted to any backplane slot. Contact the factory to discuss any specific keying requirements.
3.3 Board Installation Notes
Publication No. IPN250-HRM/3
1. The IPN250 uses the OpenVPX SLT6‐PAY‐4F1Q2U2T‐10.2.1 Slot Profile and the MOD6‐PAY‐4F1Q2U2T‐12.2.1‐8 Module Profile.
CAUTION
Take care to ensure that the pinout of the IPN250 matches that of the backplane slot before insertion.
2. Air‐cooled versions of the IPN250 have an injector/ejector handle to ensure that the backplane connectors mate properly with the backplane. The captive screws at the top and bottom of the front panel allow the IPN250 to be tightly secured in position, which provides continuity with the chassis ground of the system.
3. Conduction‐cooled versions of the IPN250 have screw‐driven wedgelocks at the top and bottom of the board to provide the necessary mechanical/ thermal interface. Correct adjustment requires a calibrated torque wrench with a hexagonal head of size
3
/
32
” (2.38 mm), set to between 0.6 and 0.8 Nm.
4. In an air‐cooled development enclosure, when taking I/O connections from the backplane connectors, use of GEIP I/O modules (or some equivalent system) ensures optimum operation of the IPN250 with regard to EMI. See overleaf for more details on the I/O modules.
Installation and Power Up/Reset 17
3.4 Power Requirements
The IPN250 has the following power requirements:
• 84 W maximum from Vs1 and Vs2 (+12 V)
• 60 W maximum from Vs3 (+5 V)
• 1.65 W maximum from P3V3_AUX (+3.3 V)
The maximum Thermal Design Power (TDP) is 120 W.
To keep the Real Time Clock (RTC) running, power must be applied to either the
P3V3_AUX or the VBAT supply.
For more details, see the Electrical Specification in Appendix A.
3.5 Connecting to IPN250
To interact with the BIOS requires the IPN250 to be connected to, as a minimum, a
USB keyboard and a VGA monitor on the GMCH video output channel. The BIOS can alternatively be configured to use the GPU video output channel 1, but the
GMCH video output channel is the default.
For development systems, front panel‐accessible Serial and Ethernet ports are available via the P82 connector (present on convection‐cooled build levels only).
A suitable breakout cable for this connector is the IPN250FPCBL‐11.
Connection to the USB and Graphics ports (together with other rear I/O) can be achieved using a Rear Transition Module. This converts the condensed pin out of the backplane connectors to pinouts suitable for use by industry standard connectors. The following items are required as a minimum:
• The IPN250
• A rear transition module (IPN250RTM)
• A USB keyboard and mouse
• A VGA monitor and suitable cables
The VPX I/O Modules manual contains more details on fitting backplane modules.
LINK
VPX I/O Modules Manual, publication number VPXIOM-0HH .
Similar antistatic and safety precautions apply when handling and/or installing
I/O modules as for the IPN250.
COM1 and COM2 are configurable for RS232 or RS422 via the BIOS. The default is RS232.
18 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
3.6 Power-up
As the IPN250 runs through its boot sequence, the LEDs light. See the
section for the functions of the LEDs.
3.6.1 Power-up/Reset Sequence
From the application of 12 V and 5 V power, to the board starting to boot the operating system typically takes 7 seconds.
Since the ramp‐up times of the 12 V and 5 V system PSU and the on‐board PSUs will vary with load, the time taken for the IPN250 to come out of reset will vary from system to system. It is the system designer’s responsibility to account for this.
The IPN250ʹs power‐on/reset sequence has the following order:
1. Wait for the 3.3 V Auxiliary supply (P3V3_AUX), main 12 V (P12V) and 5 V
(P5V) VPX power rails to be within specification.
2. Wait for the backplane SEQ_IN pin to go high or 500 mS timeout.
3. Start all on‐board power supplies and power‐up external GPU(s) on connected NPN240(s).
4. The processor fetches the first instruction from the SPI Flash and runs the
BIOS.
5. The processor boots the operating system from an external SATA disk or from the on‐board SATA Flash disk.
3.7 Inter-board Sequencing
The IPN250 supports inter‐board sequencing. This allows for the sequencing of power between several boards in a system to be controlled.
The power manager holds off all on‐board supplies (except the P3V3_AUX supply) when the backplane SEQ_IN signal is held low. The power manager initiates the power‐on sequence if the SEQ_IN signal remains low 500 ms after the off‐board supplies are within specification (allowing for the possibility that the previous board in the chain has failed).
The power manager drives the open‐drain backplane SEQ_OUT signal low while the backplane supplies are out of specification and until it is deemed that inrush currents associated with power‐on have subsided.
NOTE
If inter-board sequencing is not required, SEQ_IN/SEQ_OUT may be left unconnected.
Publication No. IPN250-HRM/3 Installation and Power Up/Reset 19
3.8 GPU Control Ports
The IPN250 has two GPU control ports, which can be used to control power‐up/ power‐down, resetting and system management of two external GPUs. These ports are intended to be connected to the GPU control ports of a GEIP NPN240.
The following table shows the available control signals:
Table 3-1 GPU Control Port Signal Functions
Signal Function
GPUn_SEQ_IN Driven low to power-down the GPU
GPUn_SEQ_OUT Asserted by the GPU when power-up is complete
GPUn_NODE_RESET~ PCIe fundamental reset
GPUn_POWR_SDA
GPUn_POWR_SCL
SMBus signals to SMBus switch
Where “n” = 1 for GPU control port 1 and “2” for port 2.
20 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4 • Functional Description
Figure 4-1 Block Diagram
4.1 Processor
The IPN250 is fitted with an Intel 45nm 2.26 GHz Core2 Duo SP9300 SV Penryn
SFF CPU with a FSB frequency of 1066 MHz.
LINK
For more details on the processors, see http://www.intel.com
.
Publication No. IPN250-HRM/3 Functional Description 21
4.2 Graphics and Memory Controller Hub (GMCH)
The IPN250 uses the Intel Cantiga GS45 GMCH. The 16‐lane PCIe interface is connected to the I/O subsystem PCIe switch.
4.2.1 GMCH Memory
The IPN250 uses two DDR3 SO‐DIMMs to provide the system memory. Standard unregistered 1066 MHz DDR3 SO‐DIMM modules of 2 GByte or 4 GByte capacity are supported, offering 4 or 8 GBytes total capacity.
NOTE
ECC is not supported.
NOTE
SO-DIMM modules are not user-exchangeable.
4.2.2 Internal Graphics
A single component analog video output channel (RGBHV) is connected from the
GMCH to the backplane
for connection of a console display. This video channel is not intended for high quality/high resolution use. To use this video channel, it must be enabled in the BIOS.
Applications that require high quality/high resolution graphics should use one or both of the GPU video outputs instead (see
NOTE
Operating Systems may not support simultaneous use of the Internal Graphics and GPU Video outputs.
22 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4.3 I/O Controller Hub (ICH)
The IPN250 uses the Intel ICH9M I/O Controller Hub.
4.3.1 Integrated LAN
The ICH9M Integrated LAN is not used on the IPN250.
4.3.2 Front-Panel Ethernet Controller
The IPN250 uses the Intel 82574 Ethernet Controller (Hartwell) to provide a front‐ panel 10/100/1000BaseT Ethernet Port through the
on build levels 1 to 3).
An EEPROM connected to the 82574 is used for configuration and MAC address storage. This EEPROM is write‐protected when the backplane NVMRO signal is asserted. The Ethernet Controller does not support Wake On LAN.
4.3.3 USB Ports
2
6
8
Four of the ICH9B high speed USB 2.0 ports are connected to the P3 connector
as detailed in the following table. The remaining USB ports are unused.
Table 4-1 USB Port Usage
ICH9M USB Port Backplane USB Port
0 0
1
2
3
4.3.4 SATA Ports
1
5
Two of the ICH9M SATA ports are connected to the backplane P3 connector and
one port to the Flash Disk. The remaining SATA port is unused. To minimize bandwidth bottlenecks, the SATA ports are split between the two ICH9M EHCI controllers as detailed in the following table.
Table 4-2 SATA Port Usage
ICH9M SATA Port SATA Port Usage
0 Backplane Port 0
Backplane Port 1
Flash Disk
4.3.5 ICH PCIe Ports
The six ICH9M PCIe ports are configured for single lane (x1) operation and connected as follows:
• Three ports (1 to 3) connected to the backplane P3 connector
• One port (4) connected to the Graphics Subsystem Video Decoder. See
• One port (5) connected to the I/O Subsystem Quad Ethernet Controller
• One port (6) connected to the front panel Ethernet Controller
Publication No. IPN250-HRM/3 Functional Description 23
Addendum
March 2011
4.3.6 Flash Disk
Component obsolesence has required the use of two different Flash Disk devices on the IPN250.
Although both parts are described as 8 GByte, the new parts are closer to
7 GBytes.
The IPN250 uses a Marvell MV88SA8052A1 SATA to PATA bridge to interface to an on‐board 8 GByte NAND Flash Drive. The BIOS provides an option to enable the Flash Disk to be write‐protected using the backplane NVMRO signal.
4.3.7 High Definition Audio
An IDT STAC9200X audio CODEC is connected to the ICH9M high definition
audio interface to provide stereo line in and line out on the P3 connector .
The sizes are 8,001,552,384 bytes (7683 MBytes reported by the ‘FDISK’ utility) for the old
SST85LD1008M device and 7,314,628,608 bytes
(6981 MBytes reported by
‘FDISK’) for the new
SST85LP1008B device.
4.3.8 SPI Flash
A 16 Mbit SPI Flash device (SST25VF016B), connected to the SPI bus, is provided for storage of BIOS and BIT.
An interface on the backplane
P4 connector is provided to support in‐circuit
programming of the SPI Flash devices using a Dediprog SF100 programmer.
The position of the device on the back of the board is
4.3.9 LPC Interface
The following devices are connected to the LPC bus on the IPN250:
Super I/O
The IPN250 provides an SMSC SCH3116 PC System & I/O Controller.
COM1 and COM2 Serial Ports
The IPN250 provides two external serial ports, COM1 and COM2. Each port is configurable in the BIOS for RS232 operation with hardware flow control
(default) or RS422 operation with no hardware flow control.
The function of the signals associated with each port depends on the mode selected, as detailed in the following table:
Table 4-3 COM1/2 Port Signal Functions
Signal RS232 Function RS422 Function
COMx_RXD_RXN RXD RXA
COMx_CTS_RXP CTS
COMx_TXD_TXN TXD
COMx_RTS_TXP RTS
RXB
TXA
TXB
Termination resistors for RS422 operation must be provided externally if required.
A backplane strapping pin, COM12_FRONT~, is provided on the
enable the COM1 and COM2 serial ports to either be connected to the front panel
(where available) or to the backplane
COM3 and COM4 Serial Ports
COM3 is unused. COM4 is used to interface to the BMM.
Keyboard & Mouse
No PS2 Keyboard or Mouse interfaces are provided on the IPN250. USB
Keyboard and Mouse may be used via the USB ports.
CPLD
The IPN250 uses a Lattice MachXO LCMX01200 CPLD to provide ‘glue logic’ and
LPC Bus Control/Status Registers (see
24 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Port 80 Debug
Socket
The IPN250 provides an 11‐way socket, P80S
(mounted on the back of the board), for connection of a P80BPROG board to facilitate debug and board bring‐up. This can be used to display the BIOS POST codes.
LINK
The BIOS POST codes are detailed in http://www.ami.com/support/ downloaddoc.cfm?DLFile=support/doc/
AMIBIOS8_Checkpoint_and_Beep_Code_List_PUB.pdf&FileID=928 .
4.3.10 SMBus Interface
The SMBus is connected to the devices shown in the following table, which also gives the address map:
Table 4-4 SMBus Address Map
Function Address (Binary) Address (Hexadecimal)
LM92 DDR3 Thermal Sensor 1001011X 0x96/0x97
DDR3 SO-DIMM #1
DDR3 SO-DIMM #2
CK505 clock generator
82574 Ethernet Controller
PEX8664 PCIe Bridge
PCA9546A SMBus Switch
POWR1014A a
1010000X
1010010X
1101001X
1100001X
0011011X
1110000X
TBD
0xA0/0xA1
0xA4/0xA5
0xD2/0xD3
0xC2/0xC3
0x36/0x37
0xE0/0xE1
TBD a. Either the on-board GPU’s Power Manager or an external NPN240’s Power Manager depending on the setting of the I
2
C switch.
The IPN250 provides the SMBus devices detailed below, connected to the
Southbridge:
Thermal Sensor
An LM92 thermal sensor, located close to the GMCH DDR3 SO‐DIMMs.
BMM
The CPU communicates with the Board Management Microcontroller (BMM) using serial port COM4.
Backplane SMBus
Switch
1
2
3
A 4‐port PCA9546A SMBus switch with ports connected as detailed in the following table:
Table 4-5 PCA9546A SMBus Switch Port Usage
PCA9546A Port Port Usage
0 On-board POWR1014A Power Manager
External SMBus port 1
External SMBus port 2
Unused
One port is connected to the graphics subsystem’s Lattice POWR1014A Power
Manager, and two ports are connected to backplane
ports. The backplane SMBus ports are used to enable BIT to access the Power Manager(s) on an NPN240 board.
NOTE
The SMBus switch is used to reduce SMBus loading and to prevent address conflicts, as the Power
Manager on the IPN250 has the same SMBus address as the Power Managers on the NPN240.
Publication No. IPN250-HRM/3 Functional Description 25
4.4 Graphics Subsystem
The NVIDIA GT215‐350 is a 96‐core CUDA‐enabled GPU. It operates at a core speed of 540 MHz, with a shader clock speed of 1.3 GHz and a Memory Clock of
750 MHz. The GPU generates all of its clocks from a single 27 MHz clock input, which is derived from a 27 MHz 25 ppm Crystal Oscillator.
Figure 4-2 Graphics Subsystem Architecture
26 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4.4.1 GPU Power Control
The backplane signals SPARE1, SPARE2 and SPARE3 (on the P4 connector)
control whether the on‐board GPU and two external GPUs (on an NPN240) are powered up or kept in a powered down state as shown in the following table:
Table 4-6 GPU Power Control Strapping
Signal Function when Logic 1 Function when Logic 0
SPARE_1 Enables on-board GPU Disables on-board GPU
SPARE_2 Enables off-board GPU1 Disables off-board GPU1
SPARE_3 Enables off-board GPU2 Disables off-board GPU2
These signals connect to the CPLD and it is possible for software to override the setting of these signals (see
4.4.2 GPU Resources
DDR SDRAM
The GT215 requires the use of external RAM. The IPN250 provides 1 GB (8 x 64M x 16) of DDR3 graphics SDRAM. The NVIDIA BIOS has timing parameters specifically tuned for Hynix H5TQ1G63BFR‐12HC. The memory is split into
Frame Buffer Interfaces, each having a data bus width of 64 bits. The memory operates at a clock speed of up to 750 MHz.
Video BIOS ROM
The Graphics Subsystem includes a SPI Flash ROM of 512 Kbits for use by a Video
BIOS.
4.4.3 External Interfaces
Video Output
The GT215 supports two independent video feeds (A and B). Driver software independently configures each feed to be output using either the Digital Port or
Analog port (as shown in the following table), but not both simultaneously.
Table 4-7 Video Output Feeds
Feed Mode Analog Output Digital Output
A
B
Analog RGB 1
Digital Not used
Analog RGB 2 a
Digital Not used
Not used
DVI-DL
Not used
HDMI/DVI-SL
a. By default, RGB output port 2 does not support DDC (see the DDC section)
Analog RGB
Output
NOTE
Operating Systems may not support simultaneous use of the Internal Graphics and GPU Video outputs.
The GT215 provides two RGB analog output channels from two independent
DACs. Both analog output channels have provision for red, green, blue, horizontal sync and vertical sync. The red, green and blue signals are intended for
75 terminated applications. These signals are band‐limited by 500 MHz EMI filters. The sync outputs are TTL level.
The Graphics subsystem achieves display resolutions up to 1920 x 1200 @ 60 Hz on both RGB analog output channels.
Publication No. IPN250-HRM/3 Functional Description 27
Digital Display
Ports
TV Input Video
Decoder
DVI-DL Output
The GT215 provides one Dual Link DVI interface. The interface consists of six differential data channels and a single differential clock channel. Display resolutions up to 2560 x 1600 @ 60 Hz can be achieved when connected to a suitable monitor. The Graphics Subsystem supports hot plug detect on the DVI port.
HDMI/DVI-SL Output
The GT215 supports a single HDMI v1.3a port. The interface consists of three differential data channels and a single differential clock channel. The HDMI port is capable of displaying resolutions up to 1080p when connected via an HDMI connector on a suitable monitor.
This port may alternatively be used as a Single Link DVI port by connecting to a
DVI input on a monitor. The Single Link DVI port achieves display resolutions up to 1920 x 1200 @ 60 Hz when connected to a suitable Single Link DVI monitor.
The GT125 does not support the CEC (Consumer Electronics Control) Interface.
DDC
Two of the GPUs I
2
C interfaces are used to provide DDC ports for the connection of up to two monitors on the IPN250. DDC port 1 can be used for either RGB output port 1 or the DVI‐DL output port without any hardware configuration changes. By default, DDC port 2 is used for the HDMI/DVI‐SL port, but it can be reconfigured (by factory build option) to be used with RGB output port 2.
5 volt supplies for the DDC circuitry of the connected monitors are provided via independent resettable fuses.
The Graphics subsystem includes a Conexant CX23885 video decoder that can perform video (TV) capture from one channel (although additional drivers are required before this can be activated). The video decoder supports up to four composite inputs and two SVideo inputs.
NOTE
Component video (YPbPr) is not currently supported.
The following table shows the mapping between TV Input signals at the
and the CX23885 TV Capture inputs:
Table 4-8 TV Input to TV Capture Signal Mapping
P2 Input Signal CX23885 Input
CVBS1_Y1 VIN1
CVBS2_C1_Pb VIN5
CVBS3_C2 VIN6
CVBS4_Y2_Pr VIN8
TV formats supported are PAL and NTSC.
NOTE
HDTV is not supported.
The CX23885 uses a 24AA02 256‐byte Serial I
2
C EEPROM for storing driver settings.
28 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
PCI Express
The GPUs x16 PCIe Gen 1 bus interface is connected to the PCIe switch. The GPU supports lane and polarity reversal.
The Conexant CX23885 video decoder is connected to a x1 PCIe Gen 1 port on the
4.5 I/O Subsystem
4.5.1 PCIe Switch and Expansion Plane
The IPN250 provides a 64‐lane PLX PEX8664 Gen2 PCIe switch with ports connected as follows:
• One 16‐lane port (Station 0 Port 0) connected to the GMCH
• One 16‐lane port (Station 4 Port 16) connected to the GPU
• One 8‐lane port (Station 5 Port 20) connected to the Data Plane Ethernet
Controller
• 16 lanes (Station 1 Ports 4 to 7) connected to the P2 expansion plane. These
are configurable (see below) using pins on the backplane P3 connector
An SPI EEPROM is provided for configuration of the PCIe switch.
Port Width
Configuration
The 16 lanes on the PCIe expansion plane on the
P2 connector can be configured
as shown in the following table:
Table 4-9 P2 Expansion Plane Port Width Configuration
P2 Expansion Plane Configuration
EP_PCFG1 EP_PCFG0*
Port 4 Port 5 Port 6 Port 7
0
0
0 x16 (EP00-EP15) -
1 (or open) x4 (EP12-EP15) x4 (EP08-EP011) x4 (EP04-EP07) x4 (EP00-EP03)
1 (or open) 0 x8 (EP08 - EP15) x4 (EP04-EP07) x4 (EP00-EP03) -
1 (or open) 1 (or open) x8 (EP08 - EP15) x8 (EP00 - EP07) -
The default is two 8‐lane ports.
4.5.2 GPIO
The IPN250 uses PCIe switch GPIO signals to provide eight TTL GPIO signals, connected to the backplane signals as detailed in the following table. The
OpenVPX GDISCRETE1 signal is not implemented on the IPN250.
Table 4-10 PEX8664 GPIO Signals
PEX8664 Pin Signal Backplane Pin
GPIO24
GPIO25
GPIO26
GPIO27
GPIO28
GPIO29
GPIO30
GPIO31
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
P4 G1
P4 G3
P4 G5
P4 G7
P4 G9
P4 G11
P4 G13
P4 G15 a a. This signal is not functional, and must be configured as an input on PWB artwork revisions less than 4.
Publication No. IPN250-HRM/3 Functional Description 29
I
OL
I
OH
V
IL
V
IH
The signals default to being inputs and have 4.7 pull‐up resistors to 3.3V. The following table gives the GPIO signal DC characteristics.
Table 4-11 GPIO Signal DC Characteristics
Symbol Parameter Minimum Maximum Unit Conditions
Output Low Current 13 32
Output High Current -8
Input Low Voltage -0.3
Input High Voltage 1.7
-27
0.7
5.5
mA V
OLmax
= 0.7 V mA V
OHmax
= 1.7 V
V
V
4.5.3 Quad Ethernet Control Plane
The IPN250 uses an Intel 82580 (Barton Hills) Ethernet controller to provide the
• Two 10/100/1000BaseT thin pipes
• Two 1000base‐KX ultra thin pipes
1
2
3
The following table shows 82580 port assignment:
Table 4-12 82580 Port Assignment
82580 Port Backplane Port
0 10/100/1000BaseT Control Plane Thin Pipe (CPTP) 1
10/100/1000BaseT Control Plane Thin Pipe (CPTP) 2
1000Base-Bx Control Plane Ultra Thin Pipe (CPUTP) 1
1000Base-Bx Control Plane Ultra Thin Pipe (CPUTP) 2
An EEPROM connected to the 82580 is used for configuration and MAC address storage.
4.5.4 Dual Ethernet Data Plane
0
1
The IPN250 uses an Intel 82599 (Niantic) Ethernet controller to provide two
10Gbase‐KX4 Data Plane ports on the backplane P1 connector
as shown in the following table.
Table 4-13 82599 Ports
82599 Port Backplane Port
10GBase-KX4 Data Plane Fat Pipe 2
10GBase-KX4 Data Plane Fat Pipe 1
XAUI & 10GBase‐CX4 build options are also available. 10GBase‐KX4 is not currently supported by the standard Intel driver under Windows 7. If this is required, consult the factory for more information.
An EEPROM connected to the 82599 is used for configuration and MAC address storage.
30 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4.6 CPLD
The CPU CPLD is a Lattice MACHXO 1200‐macrocell CPLD LCMXO1200C‐
3FTN256I in a 256‐ball BGA package. The CPLD implements the following functions:
• Power supply sequencing/synchronization logic
• Reset logic
• LPCBus Control and Status registers
The CPLD provides the following 8‐bit LPCBus I/O space registers at a base address of 0x0600:
Table 4-14 CPLD Address Map
Byte Offset Function
6
7
4
5
2
3
0
1
8
9
10 to 15 Reserved
4.6.1 Revision Register
This read‐only register holds the PCB artwork revision and the CPLD code revision, as follows:
Table 4-15 Revision Register
Bits Description
7 to 4 PCB artwork revision, e.g. 0001 b
= Rev 1
3 to 0 CPLD code revision, e.g. 0001 b
= Rev 1
Publication No. IPN250-HRM/3 Functional Description 31
4.6.2 VPX Status Register
This read‐only register gives the status of various VPX backplane signals, as follows:
Table 4-16 VPX Status Register
Bits Description
7
Geographic Address parity GAP~ ( P0 G5 )
6 to 2
Geographic address GA0~ to GA4~ ( P0 )
1
1 = non-volatile memory is write-protected,
0 = non-volatile memory is write-enabled
0
The inverse of the SYSCON~ signal (
1 = this IPN250 is System Controller,
0 = this IPN250 is not System Controller
1
0
0
1
0
1
1
0
1
0
Table 4-17 Geographic Addressing
GAP GA4 GA3 GA2 GA1 GA0 Hex Slot GAP GA4 GA3 GA2 GA1 GA0 Hex Slot
1 1 1 1 1 0 3E 1 0 1 0 0 1 1 13 12
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
0
1
0
3D
1C
3B
1A
2
3
4
5
1
1
0
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
1
32
31
10
2F
13
14
15
16
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
19
38
37
16
15
34
6
7
8
9
10
11
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0E 17
0D 18
2C 19
0B 20
2A 21
32 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4.6.3 General Control Register
This read‐write register provides miscellaneous control functions, as follows:
Table 4-18 General Control Register
Bits Description
7
6
5
4
3
2
1
0
GPU2 Enable. See section 4.4.1
and below.
0 = Power to off-board GPU2 is disabled
1 = Power to off-board GPU2 is enabled
GPU1 Enable. See section 4.4.1
and below.
0 = Power to off-board GPU1 is disabled.
1 = Power to off-board GPU1 is enabled
GPU0 Enable. See section 4.4.1
and below.
0 = Power to on-board GPU is disabled
1 = Power to on-board GPU is enabled
COM2 Mode.
0 = RS232 (default)
1 = RS422
COM1 Mode.
0 = RS232 (default)
1 = RS422
section.
0 = LED is lit (default)
1 = LED is off
MPE LED 1 (DS10S). See LEDs section.
0 = LED is lit (default)
1 = LED is off
section.
0 = LED is lit (default)
1 = LED is off
Bits 7, 6 and 5 are asynchronously loaded from the SPARE3, SPARE2 and SPARE1
backplane signals (on connector P4
) respectively when power is cycled. These bits control whether the respective GPU is powered up when the IPN250 next enters the S0 power state.
NOTE
Software (e.g. BIOS) changes to these bits do not immediately turn on/off the respective GPU - the board must enter an S3, S4, or S5 power state before the change takes effect.
Bits 4 and 3 are reset to 0 to select RS232 by default. If RS422 operation is required, the BIOS must change these bits before the COM ports are used.
The COM1/COM2 transceivers are disabled following a reset, and are enabled when this register is first written to. BIOS software must therefore write to this register with the appropriate bit 3 and 4 settings before attempting to use the
COM ports.
Publication No. IPN250-HRM/3 Functional Description 33
4.6.4 BMM Control/Status Register
2
1
0
6
5
4
This read‐write register provides control over the BMM and other miscellaneous functions, as follows:
Table 4-19 BMM Control/Status Register
Bits Description
7 Flashdisk Write Mode.
0 = Flashdisk is write protected when NVMRO = 1 (default)
1 = Flashdisk is always write enabled
3
VPP. Used to program the BMM. 0 by default
PGC. Used to program the BMM. 0 by default
PGD. Used to program the BMM and can also control the BIT Fail LED (see below).
0 by default
PGD_OE. Used to program the BMM and can also control the BIT Fail LED (see below).
0 by default
PGM. Used to program the BMM. 0 by default
Reserved. 0 by default
TOR flag. This determines whether BIT or an application runs on exiting reset:
1 = BIT
0 = Application
This bit defaults to 1 when backplane power is applied to the IPN250 and the board is turned on by the BMM, so that BIT is run initially. On completion, BIT firmware should clear this bit and reset the board, so that the application then runs. If BIT is required to be repeated on subsequent resets, application software should set this bit to 1
The BIT Fail LED (DS13) is normally controlled by the BMM. If the BMM is unprogrammed, this LED can be controlled using the PGD and PGD_OE bits. To turn on the LED, set PGD to 0 and PGD_OE to 1; to turn off the LED, set PGD to 0 and PGD_OE to 0
4.6.5 AXIS Timestamp Registers 0 to 5
These read‐only registers can be used to read the 48‐bit timestamp. Register 0 contains the least significant byte and register 5 holds the most significant byte.
When register 0 is read, the current timestamp value is latched in registers 1 to 5, so always read register 0 first.
The AXIS timestamp counter is clocked at a fixed frequency of 10 MHz (VPX
REFCLK divided by 2.5). The counter is reset whenever the VPX SYSRESET signal is asserted.
34 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
4.7 LEDs
Figure 4-3 LED Positions and Numbering
Errata
March
2011
The following LEDs are available on the rear of the PWB.
Table 4-20 LED Meanings
LED Color Meaning
Processor Subsystem
DS5S
DS7S
DS8S
DS9S
Yellow
Green
Yellow
Yellow
DS10S Yellow
Sustained +3.3V power
SATA LED. Lit when any of the SATA ports are active
MPE LED 0. Shows progress through BIT during boot-up. Once BIT is complete, unassigned.
Controlled by the General Control Register
MPE LED 2. Shows progress through BIT during boot-up. Once BIT is complete, unassigned.
Controlled by the General Control Register
MPE LED 1. Shows progress through BIT during boot-up. Once BIT is complete, unassigned.
Controlled by the General Control Register
Publication No. IPN250-HRM/3 Functional Description 35
Table 4-20 LED Meanings
LED Color Meaning
DS11S Tri-color When blinking (POST progress indicator)
Red = in ROM bootstrap code
Yellow = transitioning from bootstrap to POST
Green = executing POST
Errata
March
2011
Non-blinking (status indicator)
Red = halted (fail)
Yellow = sleeping
Green = operating
Processor hot or CPLD initialization failure DS12S Red
DS13S
DS20S
Red
Yellow
DS21S Blue
DS22S Blue
DS23S
DS24S
Blue
Blue
BIT fail
SATA Flash Disk activity
Processor core power good
DDR3 SDRAM power good
1.05 V power good
1.5 V power good
DS25S Blue
Graphics Subsystem
CPU 3.3 V power good
DS101A Red
DS102A Red
DS103A Yellow
DS104A Yellow
+12 V power supply failure
+5 V power supply failure
P3V3_AUX power good
+3.3 V power good
DS105A
DS106A
DS107A
I/O Subsystem
DS101 Yellow
DS102 Blue
DS103 Green
DS104 Yellow
DS105
DS106
DS107
DS108
DS109 Yellow
DS110 Yellow
DS111 Yellow
DS112 Green
DS113
DS114
DS115
DS116
Green
Green
Blue
Yellow
Yellow
Yellow
Yellow
Blue
Yellow
Yellow
Green
+3.3 V I/O power good
PCIe enabled
Unused
PEX8664 PCIe Switch error. Note that this LED lights during normal operation
Front panel Gigabit Ethernet 82574 1000 Mbps
Front panel Gigabit Ethernet 82574 Link/Activity
Front panel Gigabit Ethernet 82574 100 Mbps
PEX8664 PCIe Switch port 20 good
PEX8664 PCIe Switch port 16 good
PEX8664 PCIe Switch port 7 good
PEX8664 PCIe Switch port 6 good
PEX8664 PCIe Switch port 5 good
PEX8664 PCIe Switch 4 port good
PEX8664 PCIe Switch port 0 good
10G Ethernet port 1 link up
10G Ethernet port 1 10G operation
10G Ethernet port 1 link/inactive
10G Ethernet port 1 1G operation
10G Ethernet port 2 link up
36 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Table 4-20 LED Meanings
LED Color Meaning
DS117 Blue
DS118 Yellow
10G Ethernet port 2 10G operation
10G Ethernet port 2 link/inactive
DS119 Yellow
DS120 Blue
DS121 Green
DS122 Yellow
10G Ethernet port 2 1G operation
+1.2 V power supply failure
10/100/1000BaseT Ethernet port 0 link up
10/100/1000BaseT Ethernet port 0 activity
DS123 Yellow
DS124 Blue
DS125 Green
DS126 Yellow
DS127 Yellow
DS128 Blue
DS129 Green
DS130 Yellow
10/100/1000BaseT Ethernet port 0 100 Mbps operation
10/100/1000BaseT Ethernet port 0 1000 Mbps operation
10/100/1000BaseT Ethernet port 1 link up
10/100/1000BaseT Ethernet port 1 activity
10/100/1000BaseT Ethernet port 1 100 Mbps operation
10/100/1000BaseT Ethernet port 1 1000 Mbps operation
10/100/1000BaseBX Ethernet port 2 link up
10/100/1000BaseBX Ethernet port 2 activity
DS131 Yellow
DS132 Blue
DS133 Green
DS134 Yellow
DS135 Yellow
DS136 Blue
10/100/1000BaseBX Ethernet port 2 100 Mbps operation
10/100/1000BaseBX Ethernet port 2 1000 Mbps operation
10/100/1000BaseBX Ethernet port 3 link up
10/100/1000BaseBX Ethernet port 3 activity
10/100/1000BaseBX Ethernet port 3 100 Mbps operation
10/100/1000BaseBX Ethernet port 3 1000 Mbps operation
4.8 JTAG
The CPLDs and the Power Manager are connected to the JTAG port to allow these devices to be programmed. There is a backplane strap to enable the GPU to be included in the JTAG chain.
Publication No. IPN250-HRM/3 Functional Description 37
4.9 Front Panel
4.9.1 Air-cooled Versions (Build Levels 1 to 3)
The air‐cooled assembly is available at 1” pitch. This should match the pitch of the backplane being used to allow correct EMC protection of the system.
LEDs at the front edge of the PWB (rear side) should be visible through the small apertures in the front panel.
Figure 4-4 Air-cooled Front Panels
Connector
A 25‐way connector, P82 , provides COM1/COM2 and Ethernet connection.
A breakout cable (IPN250FPCBL‐11) is available for this connector.
4.9.2 Conduction-cooled Versions (Build Levels 4 and 5)
The conduction‐cooled assembly is available at 0.8” pitch. If a VITA48/REDI two‐ level maintenance build is required, consult the factory.
LEDs on the back of the PWB may just be visible. No front I/O is available.
Figure 4-5 Conduction-cooled Front Panel
38 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5 • Connectors
P1
P2
P3
P4
The following table shows the function of the connectors on the IPN250:
Table 5-1 Connector Functions
Connector Function Connector Functions
P0 VPX interface P5 Not used
Data plane
Expansion plane
P6
P82
User I/O
Ethernet control plane
P80S
User I/O
Where fitted, COM1/2 and Ethernet
Debug
Figure 5-1 Connector Positions and Pin Numbering (Top)
Publication No. IPN250-HRM/3 Connectors 39
Figure 5-2 Connector Position and Numbering (Rear)
40 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5.1 Backplane Connector Pin Assignments
The pinout of the backplane VPX connectors is compatible with the requirements of the OpenVPX specification SLT6‐PAY‐4F1Q2U2T‐10.2.1 6U payload slot profile and MOD6‐PAY‐4F1Q2U2T‐12.2.1‐8 6U payload module profile.
The following sections show the pin assignments of the IPN250 VPX backplane connectors (P0 to P6). These are shown in the 7‐row format as used in the VPX specifications.
Also provided are the corresponding pinouts to the J0 to J6 backplane connectors.
These are shown in the 9‐row format.
5.1.1 P0
The pinout of this connector is in accordance with VITA46.0 and VITA65.
Table 5-2 P0 Pin Assignments
A B C D E F
1 P12V P12V P12V None P12V P12V
2 P12V
3 P5V
4 NVMRO
5 SM1
6 GA0~
7 TRST~
8 GND
P12V
P5V
SYSRESET~
SM0
GA1~
TMS
NC
P12V None
P5V None
GND NC
GND P3V3_AUX
GND NC
GND TDI
NC GND
P12V
P5V
GND
GND
GND
TDO
REF_CLKP
P12V
P5V
NC
GA4~
GA2~
GND
REF_CLKN
G
P12V
P12V
P5V
NC
GAP~
GA3~
TCLK
GND
5.1.2 J0 (Backplane)
Table 5-3 J0 Pin Assignments
A B C
1 P12V P12V
2 P12V P12V
P12V
P12V
D E
P12V None
P12V None
3 P5V P5V P5V P5V None
4 GND NVMRO SYSRESET~ GND NC
5 GND SM1
6 GND GA0~
7 TRST~ TMS
8 GND GND
SM0
GA1~
GND
NC
GND TDI
NC GND
F G
P12V P12V
P12V P12V
P5V P5V
GND NC
GND P3V3_AUX GND GA4~
GND NC GND GA2~
H
P12V
P12V
P5V
NC
GAP~
GA3~
I
P12V
P12V
P5V
GND
GND
GND
TDO GND GND TCLK
GND REF_CLKP REF_CLKN GND
Publication No. IPN250-HRM/3 Connectors 41
5.1.3 P1
The pinout of this connector is in accordance with VITA46.0 and VITA65 Slot
Profile SLT6‐PAY‐4F1Q2U2T‐10.2.1. Fat Pipes 3 and 4 are unconnected.
Table 5-4 P1 Pin Assignments
A B C D E F G
1 DP01_R0P DP01_R0N GND DP01_T0P DP01_T0N GND NC
2 GND DP01_R1P DP01_R1N GND
3 DP01_R2P DP01_R2N GND
DP01_T1P DP01_T1N GND
DP01_T2P DP01_T2N GND VBAT
4 GND DP01_R3P DP01_R3N GND
5 DP02_R0P DP02_R0N GND
DP01_T3P DP01_T3N GND
DP02_T0P DP02_T0N GND SYSCON~
6 GND DP02_R1P DP02_R1N GND
7 DP02_R2P DP02_R2N GND
DP02_T1P DP02_T1N GND
DP02_T2P DP02_T2N GND Reserved
8 GND
9 NC
DP02_R3P DP02_R3N GND
NC GND NC
DP02_T3P DP02_T3N GND
NC GND BP_PWR~
10 GND
11 NC
12 GND
13 NC
14 GND
15 NC
16 GND
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
GND
NC
GND
GPU1_NODE_RESET~
GND
GPU1_SEQ_IN
GND
MASKABLERESET~
GND
5.1.4 J1 (Backplane)
8 GND
9 NC
10 GND
11 NC
12 GND
13 NC
14 GND
15 NC
16 GND
Table 5-5 J1 Pin Assignments
A B C
1 DP01_R0P DP01_R0N GND
D
GND
E F G
DP01_T0P DP01_T0N GND
H
GND
I
NC
2 GND GND DP01_R1P DP01_R1N GND
3 DP01_R2P DP01_R2N GND GND
GND DP01_T1P DP01_T1N GND
DP01_T2P DP01_T2N GND GND VBAT
4 GND GND DP01_R3P DP01_R3N GND
5 DP02_R0P DP02_R0N GND GND
GND DP01_T3P DP01_T3N GND
DP02_T0P DP02_T0N GND GND SYSCON~
6 GND GND DP02_R1P DP02_R1N GND
7 DP02_R2P DP02_R2N GND GND
GND DP02_T1P DP02_T1N GND
DP02_T2P DP02_T2N GND GND Reserved
GND
NC
GND
NC
GND
NC
GND
NC
GND
DP02_R3P DP02_R3N GND
GND GND NC
NC
GND
NC
GND
NC
GND
NC
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
GND
NC
GND
NC
GND
NC
GND
NC
GND
DP02_T3P DP02_T3N GND
GND GND BP_PWR~
NC
GND
NC
GND
NC
GND
NC
NC
GND
NC
GND
NC
GND
NC
GND
GPU1_NODE_RESET~
GND
GPU1_SEQ_IN
GND
MASKABLERESET~
GND
42 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5.1.5 P2
The pinout of this connector is in accordance with VITA65 Slot Profile SLT6‐PAY‐
4F1Q2U2T‐10.2.1.
Table 5-6 P2 Pin Assignments
A B C D E F G
1 EP00_RP EP00_RN GND EP00_TP EP00_TN GND GPU1_SEQ_OUT
2 GND EP01_RP EP01_RN GND
3 EP02_RP EP02_RN GND
EP01_TP EP01_TN GND
EP02_TP EP02_TN GND GPU1_POWR_SDA
4 GND EP03_RP EP03_RN GND
5 EP04_RP EP04_RN GND
EP03_TP EP03_TN GND
EP04_TP EP04_TN GND GPU1_POWR_SCL
6 GND EP05_RP EP05_RN GND
7 EP06_RP EP06_RN GND
EP05_TP EP05_TN GND
EP06_TP EP06_TN GND GPU2_NODE_RESET~
8 GND EP07_RP EP07_RN GND
9 EP08_RP EP08_RN GND
EP07_TP EP07_TN GND
EP08_TP EP08_TN GND GPU2_SEQ_IN
10 GND EP09_RP EP09_RN GND
11 EP10_RP EP10_RN GND
EP09_TP EP09_TN GND
EP10_TP EP10_TN GND GPU2_SEQ_OUT
12 GND EP11_RP EP11_RN GND
13 EP12_RP EP12_RN GND
EP11_TP EP11_TN GND
EP12_TP EP12_TN GND GPU2_POWR_SDA
14 GND EP13_RP EP13_RN GND
15 EP14_RP EP14_RN GND
EP13_TP EP13_TN GND
EP14_TP EP14_TN GND GPU2_POWR_SCL
16 GND EP15_RP EP15_RN GND EP15_TP EP15_TN GND
5.1.6 J2 (Backplane)
Table 5-7 J2 Pin Assignments
1
A B C
EP00_RP EP00_RN GND
D
GND
E F G
EP00_TP EP00_TN GND
H
GND
I
GPU1_SEQ_OUT
2 GND GND EP01_RP EP01_RN GND
3 EP02_RP EP02_RN GND GND
GND EP01_TP EP01_TN GND
EP02_TP EP02_TN GND GND GPU1_POWR_SDA
4 GND GND EP03_RP EP03_RN GND
5 EP04_RP EP04_RN GND GND
GND EP03_TP EP03_TN GND
EP04_TP EP04_TN GND GND GPU1_POWR_SCL
6 GND GND EP05_RP EP05_RN GND
7 EP06_RP EP06_RN GND GND
GND EP05_TP EP05_TN GND
EP06_TP EP06_TN GND GND GPU2_NODE_RESET~
8 GND GND EP07_RP EP07_RN GND
9 EP08_RP EP08_RN GND GND
GND EP07_TP EP07_TN GND
EP08_TP EP08_TN GND GND GPU2_SEQ_IN
10 GND GND EP09_RP EP09_RN GND
11 EP10_RP EP10_RN GND GND
GND EP09_TP EP09_TN GND
EP10_TP EP10_TN GND GND GPU2_SEQ_OUT
12 GND GND EP11_RP EP11_RN GND
13 EP12_RP EP12_RN GND GND
GND EP11_TP EP11_TN GND
EP12_TP EP12_TN GND GND GPU2_POWR_SDA
14 GND GND EP13_RP EP13_RN GND
15 EP14_RP EP14_RN GND GND
GND EP13_TP EP13_TN GND
EP14_TP EP14_TN GND GND GPU2_POWR_SCL
16 GND GND EP15_RP EP15_RN GND GND EP15_TP EP15_TN GND
Publication No. IPN250-HRM/3 Connectors 43
5.1.7 P3
This connector is assigned for User Defined signals in VITA65 Payload Slot Profile
SLT6‐PAY‐4F1Q2U2T‐10.2.1.
Table 5-8 P3 Pin Assignments
A B C D E F G
1 PCIE1_RXP PCIE1_RXN GND PCIE1_TXP PCIE1_TXN GND P5V_USB0
2 GND
3 PCIE3_RXP
4 GND
5 SATA1_RXP
6 GND
7 USB2_DP
8 GND
9 NC
10 GND
11 NC
12 GND
13 LINE_OUT_R
14 GND
15 LINE_IN_R
16 GND
PCIE2_RXP
PCIE3_RXN
SATA0_RXP
SATA1_RXN
USB0_DP
USB2_DN
NC
NC
NC
NC
NC
AUDIO_GND
AUDIO_GND
AUDIO_GND
AUDIO_GND
PCIE2_RXN
GND
SATA0_RXN
GND
USB0_DN
GND
NC
GND
NC
GND
NC
GND
LINE_OUT_L
GND
LINE_IN_L
GND
PCIE3_TXP
GND
SATA1_TXP
GND
USB3_DP
GND
NT_UPORT4
GND
NT_ENABLE~
GND
NC
GND
NC
GND
PCIE2_TXP
PCIE3_TXN
SATA0_TXP
SATA1_TXN
USB1_DP
USB3_DN
NT_UPORT1
NT_UPORT2
NC
NC
NC
EP_PCFG1
NC
NC
NC
PCIE2_TXN
GND
SATA0_TXN
GND
USB1_DN
GND
NT_UPORT0
GND
EP_PCFG0~
GND
NC
GND
NC
GND
NC
GND
P5V_USB1
GND
P5V_USB2
GND
P5V_USB3
GND
NC
GND
NC
GND
SEQ_IN
GND
SEQ_OUT
GND
5.1.8 J3 (Backplane)
Table 5-9 J3 Pin Assignments
A B C
1 PCIE1_RXP PCIE1_RXN GND
5 SATA1_RXP SATA1_RXN GND
6 GND GND USB0_DP
7 USB2_DP USB2_DN GND
8 GND
9 NC
10 GND
GND
NC
GND
NC
GND
NC
D
GND
GND
USB0_DN
GND
NC
GND
NC
E
PCIE1_TXP
2 GND GND PCIE2_RXP PCIE2_RXN GND
3 PCIE3_RXP PCIE3_RXN GND GND PCIE3_TXP
4 GND GND SATA0_RXP SATA0_RXN GND
F G
PCIE1_TXN GND
H
GND
I
P5V_USB0
GND PCIE2_TXP PCIE2_TXN GND
PCIE3_TXN GND GND P5V_USB1
GND SATA0_TXP SATA0_TXN GND
SATA1_TXP
GND
USB3_DP
SATA1_TXN GND
GND USB1_DP
USB3_DN GND
GND
USB1_DN
GND
P5V_USB2
GND
P5V_USB3
GND GND NT_UPORT1 NT_UPORT0 GND
NT_UPORT4 NT_UPORT2 GND GND NC
GND GND EP_PCFG1 EP_PCFG0~ GND
11 NC
12 GND
NC
GND
GND
NC
13 LINE_OUT_R AUDIO_GND GND
GND
NC
GND
NT_ENABLE~ NC
GND GND
NC NC
14 GND GND AUDIO_GND LINE_OUT_L GND
15 LINE_IN_R AUDIO_GND GND
16 GND GND
GND
AUDIO_GND LINE_IN_L
NC
GND
GND
NC
GND
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
GND
SEQ_IN
GND
SEQ_OUT
GND
44 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5.1.9 P4
The pinout of this connector is in accordance with VITA65 Slot Profile SLT6‐PAY‐
4F1Q2U2T‐10.2.1.
Table 5-10 P4 Pin Assignments
A B C D E F G
1 GMCH_RED GMCH_RED_RET GND COM1_RTS_TXP COM1_TXD_TXN GND GPIO_0
2 GND NC NC
3 GMCH_GREEN GMCH_GREEN_RET GND
4 GND NC NC
5 GMCH_BLUE GMCH_BLUE_RET GND
6 GND NC
7 GMCH_HSYNC Reserved (GND)
8 GND NC
9 GMCH_VSYNC Reserved (GND)
NC
GND
NC
GND
10 GND DDC_DATA
11 CPUTP02_RP CPUTP02_RN
12 GND CPUTP01_RP
13 CPTP02_DAP CPTP02_DAN
14 GND CPTP02_DCP
15 CPTP01_DAP CPTP01_DAN
16 GND CPTP01_DCP
GND COM1_CTS_RXP COM1_RXD_RXN GND
COM2_RTS_TXP COM2_TXD_TXN GND
GND
DEDI_CLK
GND
SPARE_2
GND
SPARE_4
DDC_CLK
GND
GND
CPUTP02_TP
CPUTP01_RN GND
GND CPTP02_DBP
CPTP02_DCN GND
GND CPTP01_DBP
CPTP01_DCN GND
DEDI_SEL
CPUTP02_TN
CPUTP01_TP
CPTP02_DBN
CPTP02_DDP
CPTP01_DBN
CPTP01_DDP
BOOT_FWH~
GND
CPUTP01_TN
GND
CPTP02_DDN
GND
CPTP01_DDN
GPIO_1
COM2_CTS_RXP COM2_RXD_RXN GND
DEDI_SO
DEDI_CS~
SPARE_1
SPARE_3
GND
DEDI_IO3
GND
COM12_FRONT~ DEDI_SI
GND
GPIO_2
GND
GPIO_3
GND
GPIO_4
GND
GPIO_5
GND
GPIO_6
GND
GPIO_7
GND
5.1.10 J4 (Backplane)
Table 5-11 J4 Pin Assignments
A
1 GMCH_RED
B
GMCH_RED_RET
C
GND
2 GND GND NC
3 GMCH_GREEN GMCH_GREEN_RET GND
4 GND GND NC
5 GMCH_BLUE GMCH_BLUE_RET GND
6 GND GND
7 GMCH_HSYNC Reserved (GND)
NC
GND
8 GND GND
9 GMCH_VSYNC Reserved (GND)
10 GND GND
11 CPUTP02_RP CPUTP02_RN
NC
GND
NC
GND
DDC_DATA DDC_CLK
GND GND
12 GND GND
13 CPTP02_DAP CPTP02_DAN
14 GND GND
15 CPTP01_DAP CPTP01_DAN
16 GND GND
NC
GND
NC
GND
D
GND
NC
GND
E F G
COM1_RTS_TXP COM1_TXD_TXN GND
H
GND
I
GPIO_0
GND GND COM1_CTS_RXP COM1_RXD_RXN GND
COM2_RTS_TXP COM2_TXD_TXN GND GND GPIO_1
GND
DEDI_CLK
GND
SPARE_2
GND
DEDI_SO
GND
SPARE_1
COM2_CTS_RXP COM2_RXD_RXN GND
GND
DEDI_CS~
GND
GND
DEDI_IO3
GND
GPIO_2
GND
GPIO_3
GND
SPARE_4
GND
CPUTP02_TP
CPUTP01_RP CPUTP01_RN GND
GND GND CPTP02_DBP
CPTP02_DCP CPTP02_DCN GND
GND GND CPTP01_DBP
CPTP01_DCP CPTP01_DCN GND
GND
SPARE_3
GND
CPUTP02_TN
GND
CPTP02_DBN
GND
CPTP01_DBN
GND
COM12_FRONT~ DEDI_SI
GND GND
DEDI_SEL
GND
BOOT_FWH~
GND
CPUTP01_TP
GND
CPTP02_DDP
GND
CPTP01_DDP
CPUTP01_TN
GND
CPTP02_DDN
GND
CPTP01_DDN
GND
GPIO_4
GND
GPIO_5
GND
GPIO_6
GND
GPIO_7
GND
Publication No. IPN250-HRM/3 Connectors 45
5.1.11 P5
This connector is assigned for User Defined signals in VITA65 Payload Slot Profile
SLT6‐PAY‐4F1Q2U2T‐10.2.1, but is currently unused.
Table 5-12 P5 Pin Assignments
A B C D E F G
1 NC NC GND NC NC GND NC
NC
NC
NC
GND
GND
NC
NC
NC
NC
GND
GND
NC
4
5
2
3
GND
NC
GND
NC
8
9
6
7
GND
NC
GND
NC
10 GND
11 NC
12 GND
13 NC
14 GND
15
NC
16 GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
5.1.12 J5 (Backplane)
Table 5-13 J5 Pin Assignments
A B C
7
8
5
6
3
4
1
2
9 NC
10 GND
11 NC
12 GND
13 NC
14 GND
15 NC
16 GND
NC
GND
NC
GND
NC
GND
NC
GND
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
GND
NC
GND
NC
GND
NC
GND
NC
D
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
G
GND
NC
GND
NC
GND
NC
GND
NC GND
NC
GND
NC
GND
NC
GND
NC
GND
F
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
E
NC
GND
NC
GND
NC
GND
NC
I
NC
GND
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC
GND
NC GND
NC
GND
NC
GND
NC
GND
NC
H
GND
NC
GND
NC
GND
NC
GND
NC
46 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5.1.13 P6
This connector is assigned for User Defined signals in VITA65 Payload Slot Profile
SLT6‐PAY‐4F1Q2U2T‐10.2.1.
Table 5-14 P6 Pin Assignments
A B C D E F G
1 DVI_DL_TX0P
2 GND
3 DVI_DL_TX4P
4 GND
DVI_DL_TX0N
DVI_DL_TX2P
GND
DVI_DL_TX2N
DVI_DL_CLKP
GND
DVI_DL_TX4N GND DVI_DL_TX3P
HDMI_DVI_TX0P HDMI_DVI_TX0N GND
5 HDMI_DVI_TX2P HDMI_DVI_TX2N GND
6 GND DVI_DL_TX5P DVI_DL_TX5N
7 DDC2_CLOCK
8 GND
DDC1_DATA
DDC2_DATA
GND
DDC1_CLOCK
DVI_DL_CLKN
DVI_DL_TX1P
DVI_DL_TX3N
HDMI_DVI_CLKP
HDMI_DVI_TX1P HDMI_DVI_TX1N
GND
HSYNC1
GND
Reserved
VSYNC1
VSYNC2
9 NC
10 GND
11 GREEN1
12 GND
13 HDMI_SEL~
14 GND
15 GREEN2
16 GND
NC
RED1
GREEN1_RET
BLUE1
JTAG_GPU~
RED2
GREEN2_RET
BLUE2
GND
RED1_RET
GND
BLUE1_RET
GND
RED2_RET
GND
BLUE2_RET
NC
GND
Reserved
GND
CVBS1_Y1
GND
CVBS3_C2
GND
NC
Reserved
Reserved
Reserved
GND
DVI_DL_TX1N
GND
HDMI_DVI_CLKN GND
GND
DDC2_5V
GND
HSYNC2
GND
Reserved
GND
Reserved
CVBS1_Y1_RET GND
CVBS2_C1_Pb_RET CVBS2_C1_Pb
CVBS3_C2_RET GND
CVBS4_Y2_Pr_RET CVBS4_Y2_Pr
HOTPLUG1
GND
DDC1_5V
HOTPLUG2
GND
Reserved
GND
Reserved
GND
Reserved
GND
Reserved
GND
Reserved
GND
Publication No. IPN250-HRM/3 Connectors 47
5.1.14 J6 (Backplane)
B CD
48 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
5.1.15 Signal Descriptions
The direction of fabrics is such that TX is an output from the IPN250 and RX is an input to the IPN250.
Table 5-16 Signal Descriptions
Signal Name Description
BOOT_FWH~
BP_PWR~
COM12_FRONT~ a
Factory test only
An external Power Button may be connected between BP_PWR~ and GND
b
COM port n (n = 1 or 2) RS232/RS422 signals (see
COMn_RXD_RXN,
COMn_TXD_TXN,
COMn_CTS_RXP &
COMn_RTS_TXP
CPTP01_DxP/N &
CPTP02_DxP/N
CPUTP01_TP/N,
CPUTP01_RP/N,
CPUTP02_TP/N &
CPUTP02_RP/N
CVBS1_Y1
CVBS1_Y1_RET,
CVBS2_C1_Pb_RET,
CVBS3_C2_RET,
CVBS4_Y2_Pr_RET
Thin pipes provide two Ethernet Control plane 10/100/1000BaseT ports (x = A to D) in accordance with VITA65 Module Profile MOD6-PAY-4F1Q2U2T-12.2.1-8. See
Ultra thin pipes provide two 1000Base-BX ports in accordance with VITA65 Module Profile
MOD6-PAY-4F1Q2U2T-12.2.1-8. See
Composite Video input 1 /S-Video Luma Channel 1. See
Returns for the composite video signals (connected to GND). See section 4.4.3
CVBS2_C1_Pb
CVBS3_C2
CVBS4_Y2_Pr
DDC_CLOCK
DDC_DATA
DDCn_5V
DDCn_CLOCK
DDCn_DATA
DEDI_IO3, DEDI_SI,
DEDI_SO, DEDI_CS~,
DEDI_CLK & DEDI_SEL
DP0x_RyP/N &
DP0x_TyP/N
Composite Video input 2 /S-Video Chroma Channel 1/Color component Pb. See
Composite Video input 3 /S-Video Chroma Channel 2. See
GMCH Display Data Channel Clock (output). See
GMCH Display Data Channel Data (input/output). See
Display Data Channel n (n = 1 or 2) Clock (output). See section 4.4.3
Composite Video input 4 /S-Video Luma Channel 2/Color component Pr. See
Display Data Channel n (n = 1 or 2) 5V Supply to Monitor. See
Display Data Channel n (n = 1 or 2) Data (input/output). See section 4.4.3
These signals provide an interface for reprogramming the SPI Flash devices, which contain
BIOS and BIT firmware (see
). The IPN250RTM provides a header for the connection of a Dediprog SF100 or similar programmer
Data Plane Ports. Two Fat Pipes provide 10Gbase-KX4 Ethernet ports 1 & 2 (x = 1 or 2, y = 0 to
3) in accordance with VITA65 Module Profile MOD6-PAY-4F1Q2U2T-12.2.1-8. See
DVI_DL_CLKP/N
DVI_DL_TXnP/N
Dual-Link DVI Clock Positive/Negative outputs. See
Dual-Link DVI Positive/Negative Transmitted signal (n = 0 to 5). See section 4.4.3
EP_PCFG1 &
EP_PCFG0~ a
These signals configure the 16 lanes of the PCIe expansion layer on the P2 connector as up to
4 ports of varying widths. See
EPxx_RP/N & EPxx_TP/N Expansion Plane PCIe expansion port xx (xx = 0 to 15) Receive and Transmit Positive/Negative signals. See
for configuration of these ports.
GA0~ to GA4~, GAP~ Geographic address and parity. Connected to the CPLD to enable software to determine the backplane slot into which the board is plugged. See
Publication No. IPN250-HRM/3 Connectors 49
Table 5-16 Signal Descriptions
Signal Name Description
GPIO_0 to GPIO_7
GMCH_RED,
GMCH_GREEN,
GMCH_BLUE,
GMCH_HSYNC &
GMCH_VSYNC
GPIO signals. See section 4.5.2
GMCH debug video channel (see section 4.2.2
GMCH_RED_RET,
GMCH_GREEN_RET,
GMCH_BLUE_RET
GND
Returns for the above signals (connected to GND)
GPUn_NODE_RESET~,
GPUn_SEQ_IN,
GPUn_SEQ_OUT,
GPUn_POWR_SDA &
GPUn_POWR_SCL
HDMI_DVI_CLKP/N
Digital ground
Two GPU control ports are provided for connection of two external GPUs. These ports are intended to interface to an NPN240 (n = 1 or 2). See
HDMI_DVI_TXnP/N
HDMI_SEL~
HDMI Single-Link DVI Positive/Negative Clock signal. See section 4.4.3
HDMI Single-Link DVI Channel n (n = 0 to 2) Positive/Negative Transmit signal. See
Selection of the HDMI port to replace the DVI-SL port. See
Hotplug detection of monitor presence (n = 1 or 2). See section 4.4.3
HOTPLUGn
JTAG_GPU~ a
LINE_IN_L, LINE_IN_R,
LINE_OUT_L,
LINE_OUT_R &
AUDIO_GND
MASKABLERESET~
If asserted, the GPU is included in the JTAG chain
Stereo line-in and line-out signals provided by the Audio CODEC. See
NC
None
Not currently used
Not connected – the connector pin is not tracked to any location
No signal defined at this backplane position (not connected/not tracked)
Reserved for future use. Do not connect NT_ENABLE~ &
NT_UPORT0-4
NVMRO
P12V
P3V3_AUX
Non-Volatile Memory Read Only
+12 V backplane supply (Vs2 and Vs1)
+3.3 V auxiliary supply (3.3V_AUX)
P5V +5 V backplane supply (Vs3)
P5V_USBn & USBn_DP/N USB port n (n = 0 to 3). See
PCIEn_RXP/N &
PCIEn_TXP/N
ICH9M PCIe x1 ports (n = 1 to 3). See
REDn, GREENn, BLUEn GPU analog RGBHV signals channel n (n = 1 or 2). See
REDn_RET, GREENn_RET,
BLUEn_RET
Returns for the above signals (connected to GND). See
REF_CLKP/N Reference clock
Reserved
SATAn_RXP/N &
SATAn_TXP/N
SEQ_IN
Reserved pin - not connected (not tracked)
ICH9M SATA port n (n = 0 or 1). See section 4.3.4
Power Supply Sequence Input
50 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Table 5-16 Signal Descriptions
Signal Name Description
SEQ_OUT
SM0 & SM1
SPARE_1 to SPARE_3 a
SPARE_4
SYSCON~
Power Supply Sequence Output
System Management signals, connected to the BMM
These signals control the powered-up or powered-down state of the on-board GPU and two
external GPUs (on an NPN240). See section 4.4.1
Reserved for future use. Do not connect
SYSRESET~
This enables System Controller functions. See VITA65 and VITA46.0 for more information.
When asserted, the IPN250 drives REF_CLKP/N
System Reset
JTAG signals TCLK, TDO, TDI, TMS,
TRST~
VBAT
VSYNCn/HSYNCn
Battery backup supply
GPU analog Vertical/Horizontal Synchronization signal channel n (n = 1 or 2) a. Strapping signal(s) - see next section.
b. As build level 4 and 5 assemblies do not have P82 fitted, COM12_FRONT~ must be unconnected or high in this case.
5.1.16 Strapping Signals
Strapping signals are backplane pins that are used to configure various aspects of the operation of the IPN250. They use LVTTL signalling and should either be left open (logic 1) or connected to GND (logic 0). They have internal 1 K pullup resistors to 3.3V.
Voltages applied to strapping pins must be within the limits specified in the following table:
Table 5-17 Strapping Pin Voltage Levels
Level Minimum Voltage (V) Maximum Voltage (V)
Logic 0 -0.3
0.8
Logic 1 2.0
3.6
a a. Strapping signals are not 5V tolerant.
Publication No. IPN250-HRM/3 Connectors 51
5.2 Front Panel P82 Connector
Build levels 1 to 3 are fitted with an ITT‐Cannon MDSM‐25PE‐Z10‐VR17 25‐way
Micro‐D connector on the front panel. This connector is not fitted on build levels 4 to 6.
Table 5-18 P82 Connector Pin Assignments
Pin Signal Pin Signal
1 COM1_TXD_TXN 14 GND
2 COM1_RXD_RXN 15 COM2_RXD_RXN
3 GND 16 COM2_TXD_TXN
4 COM1_RTS_TXP 17 GND
5 COM1_CTS_RXP 18 COM2_CTS_RXP
6 GND
7 GND
8 GND
9 ETH_2P
19 COM2_RTS_TXP
20 ETH_3N
21 ETH_3P
22 GND
10 ETH_2N
11 GND
12 ETH_0P
13 ETH_0N
23 ETH_1N
24 ETH_1P
25 GND
A breakout cable (IPN250FPCBL‐11) is available for this connector.
5.3 Port 80 Debug Socket (P80S)
The Port 80 Debug Socket P80S is an 11‐way socket used to connect a P80BPROG board for board bring up and debug.
Table 5-19 P80S Pin Assignments
Pin Signal Pin Signal
1 LPC_AD0 2 P3V3_SUS
3 LPC_AD1 4 GND
5 LPC_AD2 6 FWH_INIT~
7 LPC_AD3 8 LPC_FRAME~
9 GND
11 GND
10 CK_DEV_33
52 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
A • Specifications
A.1 Technical Specification
Table A-1 Technical Details
Feature Details
Processor
Processor RAM
Intel Penryn Core 2 Duo SV 2.26GHz CPU
(SP9300)
4 GBytes DDR3 SODIMM
Comments
Default build is two banks of 2 GBytes.
ECC not supported
Northbridge
Southbridge
GPU
GPU RAM
CPU SPI Flash
NAND Flash
Serial COM Ports
VGA ports
DVI ports
TV input ports
USB
SATA
GPIO
AXIS support
I
2
C
RTC
Audio
PCIe ports
Write protection
Form factor
Cantiga GMCH North Bridge
ICH9M South Bridge
NVIDIA GT215
Two banks of 0.5 GBytes DDR3
2 MBytes
8 GByte SATA Flash Disk
2 x RS232/422 (COM1/2) shared with front
2 x VGA (GPU) + 1 x VGA (GMCH)
1 x DVI-DL & 1 x DVI-SL/HDMI (GPU)
4 composite or 2 S-Video (or 2 composite and 1
S-Video)
4 x ports USB2.0 to rear
2 x ports to rear, 1 to NAND Flash
8 TTL GPIO signals
Timestamp using 25 MHz VPX REF_CLK
BMM, EEPROM
Included in ICH9M
Stereo line-in and line-out
3 PCIe x1 ports to rear
Optional write protection on NAND Flash
Single slot 6U VPX (VITA46) and VPX-REDI
(VITA48) card complying with build levels 1 to 6 using a single PCB for all build levels
Slot pitch
OpenVPX Slot Profile
OpenVPX Module Profile MOD6-PAY-4F1Q2U2T-12.2.1-8
Data Plane (P1) 2 Fat Pipes - 10GBase-KX4 Ethernet
Expansion Plane (P2)
1" (Air-cooled), 0.8" (Conduction-cooled)
SLT6-PAY-4F1Q2U2T-10.2.1
Control Plane (P4)
Two 8-lane PCIe ports (Gen1 2.5Gb/s).
Jumper options to support configurations
2 UTPs - 1000Base-KX/BX Ethernet
2 TPs - 1000BaseT Ethernet
GMCH VGA port for console
For connection of NPN240 TV decoders
Compatible with GBX460
Variants also provided for XAUI & CX4
Network boot supported
Publication No. IPN250-HRM/3 Specifications 53
Table A-1 Technical Details
Feature Details
Front I/O
JTAG
Comments
1 independent 1000BaseT Ethernet port.
Backplane strap option to route COM1/2 to front panel connector or backplane
Front panel connector only fitted on build levels 1 to 3
JTAG devices connected to backplane JTAG port
A.2 Electrical Specification
The IPN250 derives its main on‐board power supplies from the +12V (Vs1/Vs2),
+5V (Vs3) and +3.3V (3.3V_AUX) backplane supplies. It does not use the
±12V_AUX supplies.
When present, the VBAT backplane signal is used to power the RTC when other supplies are removed.
A.2.1 Current Consumption
Table A-2 Current Consumption
Current Consumption
Power Supply
Typical Maximum
+12 V (Vs1/Vs2) 4.0 A 7.0 A
+5 V (Vs3) 7.5 A
+3.3 V (3.3V_AUX) 0.2 A
VBAT
12.0 A
0.5 A
0.15 mA 1.0 mA
A.2.2 Voltage Supply Requirements
Power supply voltages and ripple must be in accordance with the limits specified in VITA46.0.
WARNING
Do not exceed the maximum rated input voltages or apply reversed bias to the assembly. If such conditions occur, toxic fumes may be produced due to the destruction of components
A.2.3 Thermal Design
Cooling solutions should be designed for a maximum IPN250 thermal design power of 120 W.
54 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
A.3 Reliability (MTBF)
The following table shows the predicted values for reliability as Mean Time
Between Failures (MTBF) and failures per million hours (fpmh) for the
IPN250‐01000 (see Product Codes for variant details).
Table A-3 Reliability (MTBF)
Environment Fail Rate (fpmh) MTBF (Hours)
Ground Benign 30C
Ground Fixed 40C
Ground Mobile 45C
Naval Sheltered 40C
4.8985
21.0881
56.6076
29.9554
Naval Unsheltered 45C
Airborne Inhabited Cargo 55C
81.3264
54.0664
Airborne Inhabited Fighter 55C 74.0355
Airborne Uninhabited Cargo 70C 144.2538
Airborne Uninhabited Fighter 70C 183.3639
Airborne Rotary Wing 55C 160.6248
Space Flight 30C 3.6163
204 145
47 420
17 665
33 383
12 296
18 496
13 507
6932
5454
6226
276 523
The predictions are carried out using MIL‐HDBK‐217F Notice 2, Parts Count method. To complement the 217 failure rates, some manufacturersʹ data is included where appropriate; Q values have been modified according to the
ANSI/VITA 51.1 specification.
A.4 Mechanical Specification
The IPN250 occupies a single 6U VPX slot.
Convection‐cooled boards are compliant with the mechanical requirements of
IEEE1101.1 (1ʺ slot pitch).
Conduction‐cooled boards are compliant with the mechanical requirements of
IEEE1101.2 (0.8ʺ slot pitch).
A.4.1 Dimensions
The VITA 46.0 VPX Standard gives full convection‐cooled and conduction‐cooled
6U VPX dimensions. The IPN250 occupies a single 6U VPX slot.
A.4.2 Weight
The approximate weight of the IPN250 is:
Build levels 1 to 3 = 1.200 Kg (2.65 lbs)
Build levels 4 and 5 = 1.330 Kg (2.93 lbs)
Publication No. IPN250-HRM/3 Specifications 55
A.5 Environmental Specification
Build levels 3 and 5 are not currently supported. Consult the factory if required.
A.5.1 Convection-cooled Boards
Table A-4 Convection-cooled Environmental Specifications
Build Style Temperature (°C) Vibration Shock
Standard
(Level 1)
Extended
Temperature
(Level 2)
Operating: 0 to +55 with airflow of
300 feet/minute.
Storage: -50 to +100
Operating: -20 to +65 with airflow of
300 feet/minute
Storage: -50 to +100
Random: 0.002g
2
/Hz from 10 to 2000 Hz
Sine: 2g from 5 to
500 Hz
Random: 0.002g
2
/Hz from 10 to 2000 Hz
Sine: 2g from 5 to
500 Hz
20g peak sawtooth,
11 ms duration
20g peak sawtooth,
11 ms duration
Rugged Aircooled
(Level 3)
Operating: -40 to +75 with airflow of
600 feet/minute
Storage: -50 to +100
Random: 0.04g
2
/Hz from 20 to 2000 Hz, with a flat response to
1000 Hz. 6db/Octave roll-off from 1000 to
2000 Hz
20g peak sawtooth,
11 ms duration
Humidity
Up to 95% RH with varying temperature.
10 cycles,
240 hours
Comments
Up to 95% RH Commercial grade cooled by forced air, for use in benign environments and software development applications.
Optional conformal coating
As Standard but conformally coated and temperature characterized
Up to 95% RH with varying temperature.
10 cycles,
240 hours
Wide temperature rugged, cooled by forced air. Conformally coated for additional protection
A.5.2 Conduction-cooled Boards
Table A-5 Conduction-cooled Environmental Specifications
Build Style
Rugged
Conductioncooled
(Level 4)
Rugged
Conductioncooled
(Level 5)
Temperature (°C)
Operating: -40 to +75 at the thermal interface
Storage: -50 to +100
Operating: -40 to +85 at the thermal interface
Storage: -50 to +100
Vibration
Random: 0.1g
2
/Hz from 15 to 2000 Hz per
MIL-STD-810E
Fig 514.4 - 8 for high performance aircraft.
12g RMS
Random: 0.1g
2
/Hz from 15 to 2000 Hz per
MIL-STD-810E
Fig 514.4 - 8 for high performance aircraft.
12g RMS
Shock
40g peak sawtooth,
11 ms duration
40g peak sawtooth,
11 ms duration
Humidity
Up to 95% RH with varying temperature.
10 cycles,
240 hours
Up to 95% RH with varying temperature.
10 cycles,
240 hours
Comments
Designed for severe environment applications with high levels of shock and vibration, small space envelope and restricted cooling supplies.
Conformally-coated as standard.
Optional ESS
Designed for severe environment applications with high levels of shock and vibration, small space envelope and restricted cooling supplies.
Conformally-coated as standard.
Optional ESS
A.5.3 Spray-cooled Boards
Table A-6 Spray-cooled Environmental Specification
Build Style
Spray-cooled
(level 6)
Temperature (°C)
Operating: -40 to
+90 maximum component case temperature
Storage: -50 to
+100
Vibration Shock
Random: 0.04g
2
/Hz from 20 to 2000 Hz, with a flat response to
1000 Hz. 6db/Octave roll-off from 1000 to
2000 Hz
20g peak sawtooth,
11 ms duration
Humidity
Up to 95% RH with varying temperature.
10 cycles,
240 hours
Comments
Conformally-coated as standard
56 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
A.6 Product Codes
Table A-7 Product Codes
IPN250 - x x x x x x x x x
1 = 0.8” VITA 46
3 = 1” VITA 46
1 = BIOS
0 = None
0 = Reserved
0 = Reserved
0 = XAUI
1 = 10GBase-CX4
2 = 10GBase-KX4 a
1 = 4 GBytes
2 = 8 GBytes (consult the factory)
1 = SP9300 @ 2.26 GHz
1 = Build level 1
2 = Build level 2
3 = Build level 3 (consult the factory)
4 = Build level 4
5 = Build level 5 (consult the factory)
6 = Build level 6 (consult the factory) a.Not currently supported under Windows 7.
NOTE
The standard build variants are as shown below. Consult the factory for any specific requirements othat than these.
IPN250-111100013
IPN250-111200013
IPN250-211100013
IPN250-211200013
IPN250-411100011
IPN250-411200011
Convection-cooled builds are offered as 1” pitch assemblies.
Conduction-cooled assemblies are 0.8” pitch unless otherwise specified.
Publication No. IPN250-HRM/3 Specifications 57
A.7 Software Support
Operating System support includes Windows 7 (32‐ and 64‐bit) and Linux
(CentOS 5.4 [32‐bit] and Red Hawk 5.4 [32‐bit]). Contact GE Intelligent Platforms for availability of support for other operating systems.
The IPN250 is an AXIS software‐enable computer, so the range of AXIS software is also available.
LINK
AXISFlow Programmer's Guide, publication number AXISFLOW-0HU .
LINK
AXISView EventView API Programmer's Guide, publication number AXISVIEW-0HU .
LINK
Radstone Signal Processing Library Manual, publication number RSPL-0HL .
LINK
Vector, Signal and Image Processing Library Manual, publication number VSIPL-0HL .
A.8 I/O Modules
The IPN250 is intended for use in deployed systems where all I/O is routed in the system backplane. However, for use in development chassis (such as the GEIP
SCVPX6U) or if required in a deployed system, Rear Transition Modules (RTMs) are available to convert the condensed P0 to P6 pinouts to industry‐standard formats. 3U breakout panels, offering a variety of industry standard connectors such as Serial I/O, internal cables and a basic set of external cables are also available. These rear transition and breakout modules are intended for use in a benign environment, and so are only available in level 1 or 2 build standards. For more details on the I/O modules, see the VPX I/O Modules manual.
LINK
VPX I/O Modules Manual, publication number VPXIOM-0HH.
The IPN250 uses two Rear Transition Modules:
• IPN250RTM for the ‘payload’ signals on P3 to P6
• FABRTMP1 for the Fabric signals on P0 to P2
To accommodate a large number of connectors, the standard IPN250RTM‐111 is dual height (1.6 inch pitch). If this is not suitable for a deployed system that uses
RTMs, contact GEIP product management to discuss alternatives (e.g. a 1 inch pitch form factor with customer‐designated I/O).
58 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
Glossary
LINK
This glossary only features terms special to this manual. Explanations of more general terms can be found in the Glossary, publication number GLOS1 .
BMM
BIT Management Microcontroller.
CEC
Consumer Electronics Control.
CUDA
Compute Unified Device Architecture.
DVI-DL
Digital Visual Interface ‐ Dual Link.
DVI-SL
Digital Visual Interface ‐ Single Link.
FSB
Front‐side Bus.
GEIP
GE Intelligent Platforms.
GPU
Graphics Processing Unit.
ICH
I/O Controller Hub.
LPC
Low Pin Count (bus).
LVTTL
Low Voltage Transistor Transistor Logic.
OpenVPX
VITA65 Specification.
Pipe
This refers to a physical aggregation of differential pairs used for a common function that is characterized in terms of the total number of differential pairs. A pipe is not characterized by the protocol used on it.
SM
System Management (bus).
TDP
Thermal Design Power.
TPM
Trusted Platform Module
UTP
Ultra‐Thin Pipe ‐ a pipe composed of two differential pairs.
Publication No. IPN250-HRM/3 Glossary 59
Index
A
Airflow ............................................................................ 13
Analog RGB Output ...................................................... 27
Associated Documents ................................................... 4
Audio ............................................................................... 24
B
Block Diagram ................................................................ 21
BMM ................................................................................ 25
Board Identification ...................................................... 16
Board Installation .......................................................... 17
C
Cautions ............................................................ 13, 14, 17
Chassis Ground ............................................................. 17
Configuration ................................................................. 17
Connecting to IPN250 ................................................... 18
Connectors ...................................................................... 39
J6 ............................................................................... 48
P0/J0 .......................................................................... 41
P1/J1 .......................................................................... 42
P2/J2 .......................................................................... 43
P3/J3 .......................................................................... 44
P4/J4 .......................................................................... 45
P5/J5 .......................................................................... 46
P6 .............................................................................. 47
P80S .......................................................................... 52
P82 ............................................................................ 52
Positions and Numbering .............................. 39, 40
Signal Descriptions ................................................ 49
VPX ........................................................................... 41
Cooling ..................................................................... 13, 56
CPLD ............................................................................... 32
Current Consumption ................................................... 54
E
Electrical Specification ................................................. 54
EMI/EMC ....................................................................... 17
Regulatory Compliance ........................................ 13
Environmental Specification ....................................... 56
Equipment Number ..................................................... 16
Ethernet
Control Plane .......................................................... 31
Controller (Front Panel) ........................................ 23
Data Plane ............................................................... 31
F
Features .......................................................................... 12
Flammability ................................................................. 13
Flash
Disk .......................................................................... 24
SPI ............................................................................ 24
Functional Description ................................................. 21
G
Geographical Address ................................................. 33
GMCH ............................................................................ 22
GPIO ............................................................................... 30
GPU ................................................................................. 26
PCIe Connection .................................................... 29
Power Control ........................................................ 27
Resources ................................................................ 27
Graphics
Debug ...................................................................... 22
SDRAM ................................................................... 27
Subsystem ............................................................... 26
D
DDC ................................................................................. 28
Debug .............................................................................. 52
Dimensions ..................................................................... 55
Documentation Conventions ......................................... 3
DVI Output ..................................................................... 28
H
Handling ........................................................................ 14
HDMI Output ................................................................ 28
Heatsink ......................................................................... 14
Humidity ........................................................................ 56
I
I/O Modules ............................................................ 18, 58
I/O Subsystem ............................................................... 30
ICH .................................................................................. 23
Identifying Product ...................................................... 16
Inter‐board Sequencing ................................................ 19
Introduction ................................................................... 12
60 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
J
J0 Connector ................................................................... 41
J1 Connector ................................................................... 42
J2 Connector ................................................................... 43
J3 Connector ................................................................... 44
J4 Connector ................................................................... 45
J5 Connector ................................................................... 46
J6 Connector ................................................................... 48
K
Keying ............................................................................. 17
R
Registers
AXIS Timestamp .................................................... 35
BMM Control/Status ............................................. 35
General Control ..................................................... 34
Revision ................................................................... 32
VPX Status .............................................................. 33
Reliability ....................................................................... 55
Reset Sequence and Timing ........................................ 19
Revision State ................................................................ 16
RTM ......................................................................... 18, 58
L
Label ................................................................................ 16
LEDs ................................................................................ 36
LPC Interface .................................................................. 24
M
Mechanical Specification .............................................. 55
MTBF ............................................................................... 55
O
Operating Environment ............................................... 56
Options ............................................................................ 57
S
Safety Ground ............................................................... 13
Safety Notices ................................................................ 13
SATA .............................................................................. 23
SDRAM .......................................................................... 27
Serial Ports ..................................................................... 24
Shock ............................................................................... 56
Signal Descriptions ....................................................... 49
Size .................................................................................. 55
SM Bus
Interface .................................................................. 25
Switch ...................................................................... 25
Software Support .......................................................... 58
Specifications ................................................................. 53
Electrical .................................................................. 54
Environmental ....................................................... 56
Mechanical .............................................................. 55
Technical ................................................................. 53
Storage Environment ................................................... 56
Strapping Signals .......................................................... 51
Super I/O ........................................................................ 24
System Controller ......................................................... 42
P
P0 Connector .................................................................. 41
P1 Connector .................................................................. 42
P2 Connector .................................................................. 43
P3 Connector .................................................................. 44
P4 Connector .................................................................. 45
P5 Connector .................................................................. 46
P6 Connector .................................................................. 47
P80S Debug Socket ........................................................ 52
P82 Connector ................................................................ 52
PCIe
Expansion Plane ..................................................... 30
Ports .......................................................................... 23
Switch ....................................................................... 30
Photograph ..................................................................... 12
Port 80 Debug Socket .................................................... 25
Power
GPU Control ............................................................ 27
Requirements .......................................................... 18
Up ............................................................................. 19
Problems ........................................................................... 5
Processor ......................................................................... 21
Product Codes ......................................................... 16, 57
Product Identification ................................................... 16
Profile .............................................................................. 55
T
Technical Specification ................................................. 53
Technical Support Contact Information ...................... 5
Thermal Design ............................................................. 54
Thermal Sensor ............................................................. 25
TV Input Video Decoder .............................................. 28
U
Unpacking ...................................................................... 15
USB ................................................................................. 23
V
Vibration ........................................................................ 56
Video BIOS ROM .......................................................... 27
Video Output ................................................................. 27
Voltage Supply Requirements .................................... 54
VPX Connectors ............................................................ 41
Publication No. IPN250-HRM/3 Index 61
W
Warnings ......................................................................... 13
Web Sites ........................................................................... 4
Weight ............................................................................. 55
62 IPN250 6U OpenVPX GPGPU Processor Publication No. IPN250-HRM/3
© 2011 GE Intelligent Platforms Embedded
Systems, Inc. All rights reserved.
All trademarks are the property of their respective owners.
Confidential Information - This document contains Confidential/Proprietary Information of GE Intelligent Platforms, Inc. and/or its suppliers or vendors. Distribution or reproduction prohibited without permission.
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PROVIDED "AS IS", WITH NO REPRESENTATIONS
OR WARRANTIES OF ANY KIND, WHETHER
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ARISING FROM RELIANCE UPON ANY
INFORMATION CONTAINED HEREIN IS
EXPRESSLY DISCLAIMED.
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Systems web site at: www.ge-ip.com
Publication No. IPN250-HRM/3
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