Display Port Adapters

Display Port Adapters
PLIP Level II training in Shenzhen
David Li David.j.li@NXP.com
NXP Semiconductors
June, 2010
COMPANY CONFIDENTIAL
2
Contents
NXP’s DisplayPort-VGA Adapter PTN3392
–
–
–
–
Our Value Propositions
BOM Cost
DPVGA4 and DPVGA4M Reference Dongle Designs
Summary Test Results
NXP’s DisplayPort Roadmap
– Next: PTN3372 is the same as PTN3392, and includes 5V regulator
to achieve even lower system BOM
– Low-Power DisplayPort-VGA Adapter PTN3352
NXP’s DisplayPort-DVI and DisplayPort-HDMI solutions
Appendices for PTN3392
–
–
Firmware Update via Host: Flash over AUX
Compliance, Interop, EMI, ESD Tests Results
COMPANY CONFIDENTIAL
3
NXP DisplayPort Adapter Products
Part Number
Status
PTN3360A, PTN3360B
Production
Enhanced DisplayPort-DVI/HDMI Level Shifters (Follow-up versions of PTN3300A, PTN3300B)
PTN3361B
Production
Enhanced DisplayPort-DVI/HDMI Level Shifters w/ DDC buffer, feature optimized for dongle application
PTN3380B
Production
Enhanced DisplayPort-DVI/HDMI Level Shifters w/ 5V voltage regulator, cost and feature optimized for
dongle application
PTN3381B
Enhanced DisplayPort-DVI/HDMI Level Shifters w/ DDC buffer and 5V voltage regulator, cost and feature
optimized for dongle application
PTN3360D
Sampling
Now
Production
Enhanced DisplayPort-HDMI Level Shifter with Deep Color Support for HDMI on Motherboard
PTN3392
Production
2-lane DisplayPort-to-VGA Adaptor IC, cost and feature optimized for VGA dongle
PTN3372
2-lane DisplayPort-to-VGA Adaptor IC, w/ 5V voltage regulator, cost and feature optimized for VGA dongle
Sampling
Now
COMPANY CONFIDENTIAL
4
PTN3392 - DisplayPort to VGA Bridge
DisplayPort receiver v1.1a
– 1-lane / 2-lane 2.7Gb/s / 1.62Gb/s
– AUX channel, HPD support
Output
– Analog RGB, HSYNC, VSYNC
– Up to 240MHz, 8bits color
– DDC
Resolutions
Protocol
ML0
– WUXGA: 1920 x 1200, 60Hz, 193MHz clock
Engine
– UXGA: 1600 x 1200, 60Hz, 162MHz clock
ML1
– SXGA (CRT): 1280 x 1024, 80Hz, 135MHz clock
DisplayPort
AUX
– SXGA: 1280 x 1024, 60Hz, 108MHz clock
Flash
Rx
– XGA: 1024 x 768, 60Hz, 65MHz clock
– VGA: 640 x 480, 60Hz, 25MHz clock
HPD
R
DAC
G
DAC
B
DDC
VGA-IF
MCU
AUX channel to I2C DDC channel bridge
DAC
HSYNC
VSYNC
Supports Flash over AUX field upgradability
Use only power from DP connector 3.3V
< 610mW Active @ 1920 x 1200; 150mW Standby;
500mW Init
No support for HDCP and audio
HVQFN48, 7x7mm, 0.5mm pitch
DP
configuration
RBR: 1.62
Gbps
HBR: 2.70
Gbps
1 Lane
XGA, SDTV
SXGA, 1080i
2 Lanes
SXGA, 1080i
WUXGA
ESD 7kV HBM
In Production
COMPANY CONFIDENTIAL
PTN3392 Block Diagram
COMPANY CONFIDENTIAL
6
NXP’s DisplayPort-VGA Dongle
PTN3392 has Embedded Flash
–
–
–
–
PTN3392 DisplayPort-VGA Adapter
27 MHz crystal
3.3V-to-5V regulator
No Need For
•
•
•
External flash
3.3V-to-1.2V LDO
External ESD protection
– PTN3372 integrates 3.3V-to-5V regulator
Pros
–
–
–
–
–
–
–
–
–
–
–
–
Industry’s lowest component count and BOM
Enable small-size dongle with smallest package and low BOM
Monitor detect by load sensing allows DP source; Support power saving upon monitor detachment
Flash programming over AUX CH, enabling future firmware driver download from the host
Interoperability
MacBook Pro/ NVIDIA 9400M / 9600GT
Windows / Dell Latitude E5400 / Intel GMA4500
Windows / Dell Latitude E6500 / NVIDIA Quadro NVS160M
Windows / Dell Studio 1440 / NVIDIA GeForce 9400M
Windows / Lenovo THINKPAD W700 / NVIDIA Quadro FX2700
Windows / NVIDIA Zotac GeForce 9400GT GPU Card
Windows / ATI Radeon HD5750 GPU Card
Windows / HP ProBook 5310m / Intel GMA 4500
Good interoperability
COMPANY CONFIDENTIAL
Interface Products / Ho Wai Wong-Lam
7
7
June 22, 2010
PTN3392 Bill of Materials
Industry’s Lowest
System BOM
– PTN3392
– 27 MHz
crystal
– 3.3V-to-5V
regulator
– Filter for VGA
No Need For
– External flash
– 3.3V-to-1.2V
LDO
CONFIDENTIAL
8
NXP PL-Interface Products, 2009
PTN3392 Firmware Update Via the Host AUX CH
Interoperability issues due to …
–
–
–
–
“Holes” in DP specification and interoperability guidelines document
Differences in spec interpretation between DP TX and RX vendors
Workaround solutions
Insufficient regression testing of DP source driver updates
Value Proposition of Flash Programming over AUX CH
– Uses host computer to download firmware fix or upgrade to dongle
– Without additional hardware
– NXP will host a web site for dongle end users to download various dongle firmware versions
Implementation depends on availability of SDK from GPU vendors allowing the feature
– NVIDIA / Windows
– AMD / Windows
– Intel / Windows
NXP’s implementation ready
NXP’s implementation ready
NXP’s implementation ready
Flash programming
over AUX CH
ML1
AUX+
AUXHOST
HPD
DisplayPort Protocol
Rx
Engine
8051
MCU
DAC
R
DAC
G
DAC
B
Analog Out
ML0
HSYNC
VSYNC
CONFIDENTIAL
9
NXP PL-Interface Products, 2009
DPVGA4
NXP DP-VGA reference design dongle with PTN3392 and PTN3372
Availability: NOW
Reference Dongle Design
– Uses PTN3392 or PTN3372 (stuff option)
– Form factor close to a real dongle (but with still
some debug capabilities)
– Reflects best practices in schematics & layout
– Reflects best-in-class BOM cost
– Optimized for EMI
– Optimized for VSIS performance
– Purity of signals, reference planes
– Final PTN3392 reference design schematic
and BOM
– Minimized size
– Optimized component cost / quality
– No external ESD protection needed for
passing IEC ESD tests
Contents
–
–
–
Full schematic and layout
Bill of Materials
Design and layout guidelines for optimal
performance and EMC
Purposes
1. Customer reference design
2. PTN3392 interop testing
3. Trade show demos
COMPANY CONFIDENTIAL 10
Interface Products / Ho Wai Wong-Lam
June 22, 2010
DPVGA4M
NXP DP-VGA reference design dongle with PTN3392 and PTN3372
Complete with plastic encasing
Contents
Availability: NOW
Reference Dongle Design
–
–
–
Full schematic and layout
Bill of Materials
Design and layout guidelines for optimal
performance and EMC
–
–
–
–
–
–
–
–
Uses PTN3392 or PTN3372 (stuff option)
Production-ready form factor
Reflects best practices in schematics & layout
Reflects best-in-class BOM cost
Optimized for EMI
Optimized for VSIS performance
Purity of signals, reference planes
Final PTN3392 reference design schematic
and BOM
– Minimized size
– Optimized component cost / quality
– No external ESD protection needed for
passing IEC ESD tests
COMPANY CONFIDENTIAL 11
Interface Products / Ho Wai Wong-Lam
June 22, 2010
PTN3392 Test Status Summary
VSIS 1.2 Compliance Tests
DisplayPort v1.1a PHY-Layer Compliance Tests
– Spec: VESA DisplayPort PHY CTS 1.1 or latest
governing specification
– Setup: Tektronix AWG Compliance Test Suite
– Conditions: RBR & HBR, across supply voltage
and temperature
– Status: ALL PASS
DisplayPort v1.1a Link-Layer Compliance Tests
– Spec: VESA DisplayPort LLC CTS 1.1a or latest
governing specification
– Setup: Quantum Data DisplayPort Link-Layer
Analyzer
– Status: ALL PASS
DisplayPort AUX CH Compliance Tests
(Preliminary Results at Yokohama VESA
Plugtest Dec 2009)
– Status: PASS
Inrush Current Tests
Status: PASS
– Spec: VESA VSIS v1.r2
– Setup: Tektronix VM6000 VSIS Compliance Test
Suite
– Conditions: 800 x 600, 60Hz, DMT, 40MHz ; 800 x 600, 85Hz,
DMT, 56MHz; 1024 x 768, 75Hz, DMT, 81MHz ; 1600 x 1200,
65Hz, DMT, 175MHz
– Status: PASS
– DPVGA4 board - Final BOM optimization is in
progress
EMI Tests
– Spec: CISPR22B
– Setup: EMI chamber test
– Status: PASS without metal shielding, but
without the needed 3-6dB margin
– Recommend use of metal tape around VGA
connector or use of metal can to pass EMI tests
with sufficient margin
ESD Tests
–
–
–
Spec: IEC61000-4-2 8 kV contact discharge, 15
kV air discharge
Setup: Only applicable on over-molded version
of dongle
Status: PASS without external ESD protection
COMPANY CONFIDENTIAL 12
June 22, 2010
PTN3392 Order Entry Options
PTN3392BS
BS = HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; 7x7x0.85
mm SOT619-1
“Trust NXP” option – automatic firmware upgrades
Backward compatible firmware
Customer automatically gets latest firmware version
PTN3392BS/Fx
BS = HVQFN48 plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; 7x7x0.85
•
mm SOT619-1
Fx = Firmware identification option (Fx= 1,2,3, etc and indicates latest firmware version)
Firmware version reflected on shipping box and reel but not on part symbol
Firmware options will be identified by periodic Application Sheet updates, not by PCN
Fx option must be selected at order entry
Gives customer option of controlling firmware version
COMPANY CONFIDENTIAL 13
Interface Products / Ho Wai Wong-Lam
June 22, 2010
DisplayPort-VGA Adapter Roadmap
COMPANY CONFIDENTIAL 14
June 22, 2010
DisplayPort Adapter Roadmap Bridging to DVI/HDMI/VGA
PTN3361B DP to
PTN3360A/B DP to
DVI/HDMI level shifter,
DVI/HDMI level shifter ,
DDC level shift
In Production DDC Buffer
PTN3380B DP to
DVI/HDMI level shifter,
DDC level shifter, 5V
In Production
regulator
CONCEPT
PRODUCT
In Production
First Delivery
CQS/GCF/Pre FTA
Mass production
Samplling
PTN3381B DP to DVI/HDMI level
shifter, DDC Buffer, 5V regulator
In production
Development
Samplling
Considered
PTN3360D DP to HDMI level shifter
(deep color), DDC Level Shift
Change
PTN3381D DP to HDMI level shifter (deep
color), DDC Buffer
In Development
PTN3392 DP to VGA
adapter, 2-lane DP, 8bit DAC, 240MHz,
8kV HBM ESD
In Production
VGA
In Development
PTN3352 Low-Power 2-lane DP to VGA adapter
Sampling
PTN3372 2-lane DP to VGA
adapter with 5V regulator
PTN3355 Low-Power 2-lane DP to VGA adapter, with VGA
multiplexer for notebook with docking
PTN3375 Low-Power 2-lane DP to VGA adapter, w /5V regulator
PTN3354 Low-Power 4-lane DP to VGA adapter
PTNxxxx HDMIv1.3a or 1.4 to VGA adapter
2009
2010
2011
2012
…
15
COMPANY CONFIDENTIAL
PTN3372 – DisplayPort to VGA Bridge with 5V Regulator
DisplayPort receiver v1.1a
– 1-lane / 2-lane 2.7Gb/s / 1.62Gb/s
– AUX channel, HPD support
5V Reg.
Output
– Analog RGB, HSYNC, VSYNC
– Up to 240MHz, 8bits color
– DDC
Protocol
Engine
ML0
Resolutions
– WUXGA: 1920 x 1200, 60Hz, 193MHz clock
– UXGA: 1600 x 1200, 60Hz, 162MHz clock
– SXGA (CRT): 1280 x 1024, 80Hz, 135MHz clock
– SXGA: 1280 x 1024, 60Hz, 108MHz clock
– XGA: 1024 x 768, 60Hz, 65MHz clock
– VGA: 640 x 480, 60Hz, 25MHz clock
ML1
AUX
DisplayPort
Flash
Rx
5V
DAC
R
DAC
G
DAC
B
HPD
DDC
8051 MCU
VGA-IF
HSYNC
VSYNC
Aux channel to I2C DDC channel bridge
Supports Flash over AUX field upgradability
3.3V supply; 0 … 85 °C
<700mW active; 150mW standby
DP
configuration
RBR: 1.62
Gbps
HBR: 2.70
Gbps
1 Lane
XGA, SDTV
SXGA, 1080i
2 Lanes
SXGA, 1080i
WUXGA
No support for HDCP or audio
HVQFN48, 7x7mm, 0.5mm pitch
ESD HBM 7kV
PTN3372 = PTN3392 + Integrated 3.3V to 5V Voltage Regulator
– Integrated solution for Low-cost DP-VGA Dongle
– Lowest system BOM
– 3.3V to 5V voltage regulator supports 75mA load
Sampling NOW
Production TBD
CONFIDENTIAL
16
NXP PL-Interface Products, 2009
PTN3352 – Low-Power DisplayPort to VGA Bridge
DisplayPort receiver v1.1a
– 1-lane / 2-lane 2.7Gb/s / 1.62Gb/s
– AUX channel, HPD support
Output
– Analog RGB, HSYNC, VSYNC
– Up to 240MHz, 8bits color
– DDC
ML0
ML1
AUX
Resolutions
–
–
–
–
–
–
Protocol
Engine
WUXGA: 1920 x 1200, 60Hz, 193MHz clock
UXGA: 1600 x 1200, 60Hz, 162MHz clock
SXGA (CRT): 1280 x 1024, 80Hz, 135MHz clock
SXGA: 1280 x 1024, 60Hz, 108MHz clock
XGA: 1024 x 768, 60Hz, 65MHz clock
VGA: 640 x 480, 60Hz, 25MHz clock
DisplayPort
ROM
Rx
DAC
R
DAC
G
DAC
B
DDC
HPD
MCU
VGA-IF
HSYNC
VSYNC
Aux channel to I2C DDC channel bridge
Does not support Flash over
AUX field upgradability
1.5V and 3.3V supply; 0 … 85 °C
Target 400mW active @ 1920 x 1200; 10mW standby
No support for HDCP or audio
Support fast link training
eDP Content Protection mechanisms
–
–
Support Alternate Framing
Support Alternate Scrambler Reset
HVQFN40, 6x6mm, 0.5mm pitch
ESD HBM 8kV
DP
configuration
RBR: 1.62
Gbps
HBR: 2.70
Gbps
1 Lane
XGA, SDTV
SXGA, 1080i
2 Lanes
SXGA, 1080i
WUXGA
3.3V HSYNC / VSYNC outputs (min. 3.0V)
Clock Reference Options
–
Crystal, ceramic resonator, external clock input
In Development
CONFIDENTIAL
17
NXP PL-Interface Products, 2009
NXP’s DisplayPort Adapter Solutions
COMPANY CONFIDENTIAL 18
PTN33xx for DisplayPort-DVI and HDMI dongles
Feature
TMDS level
shifters
PTN3360A
PTN3360B
PTN3361B
PTN3380B
2.5Gb/s
2.5Gb/s
1.65Gb/s
1.65Gb/s
PTN3360D
PTN3381B
PTN3381D
2.5Gb/s
1.65Gb/s
2.5Gb/s
(Deep
Color)
(Deep Color
HDMI)
3.3V to 5V voltage
regulator
DDC level shifter
Pass-gate
Pass-gate
Buffer
Pass-gate
Buffer
Buffer
Buffer
HPD level shifter
1.1V inverting
3.3V noninverting
3.3V noninverting
3.3V noninverting
3.3V noninverting
3.3V noninverting
3.3V noninverting
Respond to I2C
HDMI dongle detect
-
-
-
-
Option
Option
pin
pin
Option pin
Programmable
Equalization
ESD HBM
8kV
8kV
7kV
8kV
6kV
7kV
6kV
Application
DVI / HDMI
on MBD
DVI / HDMI
on MBD
HDMI
dongle
DVI dongle
DVI / HDMI
on MBD
HDMI
dongle
HDMI
dongle
/DVI dongle
In Production
/DVI dongle
Products in
Development
NOTE: I2C HDMI dongle detect is a mandatory feature for DisplayPort-HDMI dongle
19
COMPANY CONFIDENTIAL
PTN3360B AC-Coupled to DVI/HDMI Level Shifter
Inputs
– 4 pairs of low-swing AC-coupled differential for TX
from display source to sink with integrated 50-ohm
termination resistors and bias voltage
– 1 HPD from display HPD_Sink to GMCH HPD_Source
– 1 pair for DDC (I2C SCL and SDA)
Outputs
– 4 pairs of TMDS outputs - up to 2.5Gb/s per lane
– 1 pair for DDC level shifter
Non-inverting level-shifting HPD inverter
3.3V ± 10% power supply
Active 35mA typical
-40 to +85 oC
ESD 8kV HBM
HVQFN 48-pin package, 7x7 mm
In Production
COMPANY CONFIDENTIAL 20
PTN3360D AC-Coupled to DVI/HDMI Level Shifter
Inputs
– 4 pairs of low-swing AC-coupled differential for TX
from display source to sink with integrated 50-ohm
termination resistors and bias voltage
– 1 HPD from display HPD_Sink to GMCH HPD_Source
– 1 pair for DDC (I2C SCL and SDA)
Outputs
– 4 pairs of TMDS outputs - up to 2.5Gb/s per lane
– Supports HDMI Deep Color at 10bits/color
– 1 pair for DDC level shifter / buffer
Programmable equalizer
Non-inverting level-shifting HPD inverter
3.3V ± 10% power supply
Active 35mA typical
-40 to +85 oC
ESD 6kV HBM
HVQFN 48-pin package, 7x7 mm
In Production
COMPANY CONFIDENTIAL 21
PTN3361B AC-Coupled to DVI/HDMI Level Shifter
Inputs
– 4 pairs of low-swing AC-coupled differential for TX from
display source to sink with integrated 50-ohm termination
resistors and bias voltage
– 1 HPD from display HPD_Sink to north bridge HPD_Source
– 1 pair for DDC (I2C SCL and SDA)
Outputs
– 4 pairs of TMDS outputs - Up to 1.65Gb/s per lane
– 1 pair for DDC buffer and level shifter
– Optional I2C-based HDMI dongle detect
Respond to HDMI dongle detect via I2C (option pin)
– Mandatory feature for DisplayPort-HDMI dongle
3.3V ± 10% power supply
Active current consumption t.b.d.
-40 to +85 oC
ESD 8kV HBM (target)
PTN3361BBS: HVQFN-48, 7x7 mm
Suitable for DisplayPort-HDMI Dongle
In Production
COMPANY CONFIDENTIAL 22
PTN3361B - HDMI Dongle Detect via I2C
When connected to a DVI dongle or HDMI dongle, how
does a multi-standard source determine what display
interface to transmit?
Pin 13 = HIGH means a dongle is attached
Multi-mode
Display
Source
outputs
DVI?
HDMI?
Source reads at I2C address 81h
– If DVI dongle, no response from dongle
– If HDMI dongle, dongle returns a
predetermined character sequence
PTN3361B supports HDMI dongle detect via I2C
– Option pin DDET tied LOW for DVI dongle
– Option pin DDET tied HIGH for HDMI dongle
COMPANY CONFIDENTIAL
PTN3380B AC-Coupled to DVI/HDMI Level Shifter & 3.3V/5V Regulator
Inputs
– 4 pairs of low-swing AC-coupled differential for TX
from display source to sink with integrated 50-ohm
termination resistors and bias voltage
– 1 HPD from display HPD_Sink to GMCH
HPD_Source
– 1 pair for DDC (I2C SCL and SDA)
Outputs
– 4 pairs of TMDS outputs - up to 1.65Gb/s per lane
– 1 pair for DDC level shifter
Non-inverting level-shifting HPD inverter
3.3V ± 10% power supply
Active Current TBD
-40 to +85 oC
ESD 8 kV HBM (target)
HWQFN 48-pin package, 7x7 mm
PTN3380B = PTN3360B + Integrated 3.3V to 5V
Voltage Regulator
– Integrated solution for Low-cost DP-DVI
Dongle; Lowest system BOM
– 3.3V to 5V voltage regulator supports 55mA load
In Production
COMPANY CONFIDENTIAL 24
PTN3381B
HDMI Level Shifter w/ DDC Buffer & 3.3V/5V Regulator
Inputs
– 4 pairs of low-swing AC-coupled differential for TX from
display source to sink with integrated 50-ohm termination
resistors and bias voltage
– 1 HPD from display HPD_Sink to GMCH HPD_Source
– 1 pair for DDC (I2C SCL and SDA)
Outputs
– 4 pairs of TMDS outputs - Up to 1.65Gb/s per lane
– 1 pair for DDC level shifter
– Optional I2C-based HDMI dongle detect
Respond to HDMI dongle detect via I2C (option pin)
– Mandatory feature for DisplayPort-HDMI dongle
3.3V ± 10% power supply
0 to +70 oC
ESD 8kV HBM (target)
PTN3381BBS: HVQFN-48, 7x7 mm
PTN3381B = PTN3361B + Integrated 3.3V to 5V Voltage
Regulator
– Integrated solution for Low-cost DP-HDMI Dongle
– 3.3V to 5V voltage regulator (55mA)
Sampling NOW
COMPANY CONFIDENTIAL 25
DPDVI Reference Design
NXP DP-DVI dongle with PTN3360B or PTN3360D or PTN3361B or PTN3380B
Availability: NOW
Hardware:
–
–
–
–
–
Hardware ready for both PTN3360B/60D/61B and PTN3380B (stuff option)
Form factor optimized as a production-ready dongle
Reflects best practices in schematics and layout
Reflects best-in-class BOM cost
Constitutes a reference design of PTN3360B/D, PTN3361B, PTN3380B
Contents
– Full schematic and layout
– Bill of Materials
– Design and layout guidelines for
optimal performance and EMC
Purposes
1. Customer reference design
2. PTN3360/3361/3380 interop testing
3. Trade show demos
COMPANY CONFIDENTIAL 26
DPHDMI Reference Design
NXP DP-HDMI dongle with PTN3361B or PTN3361D or PTN3381D
Availability: Soon
Hardware:
– Hardware ready for both PTN3361B, PTN3361D, and PTN3381B (stuff
option)
– Form factor optimized as a production-ready dongle
– Reflects best practices in schematics and layout
– Reflects best-in-class BOM cost
– Constitutes a reference design of PTN3361B, PTN3361D and PTN3381D
Contents
– Full schematic and layout
– Bill of Materials
– Design and layout guidelines for
optimal performance and EMC
Purposes
1. Customer reference design
2. PTN3361/3381 interop testing
3. Trade show demos
COMPANY CONFIDENTIAL 27
PTN3360/1, PTN3380/1 Schedule
PTN3360BBS
PTN3360BBS Production
DONE
DP-DVI Reference Design (PTN3360)
AVAILABLE
DP-DVI Reference Design Interoperability Tests (PTN3360)
AVAILABLE
PTN3361BBS
PTN3361BBS Production
DONE
DP-DVI Reference Design (PTN3361)
AVAILABLE
DP-DVI Reference Design Interoperability Tests (PTN3361)
AVAILABLE
DP-HDMI Reference Design (PTN3361)
2H, 2010
DP-HDMI Interoperability Tests (PTN3361)
2H, 2010
PTN3360DBS
PTN3360DBS Production
DONE
PTN3380BBS
PTN3380BBS Production
DONE
DP-DVI Reference Design (PTN3380)
AVAILABLE
DP-DVI Reference Design Interoperability Tests (PTN3380)
AVAILABLE
PTN3381BBS
PTN3381BBS Sampling
AVAILABLE
PTN3381BBS Production
2H, 2010
CONFIDENTIAL
28
NXP PL-Interface Products, 2009
APPENDIX: Firmware Update via Host
Flash-over-AUX Feature
COMPANY CONFIDENTIAL 29
Firmware updater Tested on these PCs
Computer
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CONFIDENTIAL
30
NXP PL-Interface Products, 2009
APPENDIX: Compliance and EMI Test Results
COMPANY CONFIDENTIAL 31
PTN3392 DisplayPort PHY Compliance Test
Jitter and height measurement with RBR & HBR (Gain 0
to 7) @ -5 C, 25 C, 85 C
AWG7122B
Tektronix Awg7102
Pw2=3V3
Pw3=5V
HP6626A
HP81130
@ 2MHz
Fosc 27Mhz Vhigh 1.5V Vlow0.5V
-10dB Attenuators
J1
0
@ 10MHz
J9
Jtag
FS2 Probe
J8
@ 20MHz
Plug
J7
J6
J5
@ 100MHz
I²c
Input measurement HBR @ 100MHz
Lane 0
Tektronix AWG Compliance Test Suite
Lane 1
Speed
-5 C
25 C
85 C
-5 C
25 C
85 C
RBR 2 MHz
PASS
PASS
PASS
PASS
PASS
PASS
RBR 10 MHz
PASS
PASS
PASS
PASS
PASS
PASS
RBR 20 MHz
PASS
PASS
PASS
PASS
PASS
PASS
HBR 2 MHz
PASS
PASS
PASS
PASS
PASS
PASS
HBR 10 MHz
PASS
PASS
PASS
PASS
PASS
PASS
HBR 20 MHz
PASS
PASS
PASS
PASS
PASS
PASS
HBR 100 MHz
PASS
PASS
PASS
PASS
PASS
PASS
AWG pattern
Amplitude AWG 700mV + attenuator 10dB
COMPANY CONFIDENTIAL 32
PTN3392 DP Link Layer Compliance Tests
COMPANY CONFIDENTIAL 33
PTN3392 VSIS v1.2 VGA Compliance Tests
Resolutions tested
* video filter optimization TBD
•VGA 640x480@60Hz, 8 bits per color, 25.175MHz clock
•SVGA 800x600@60Hz, 8 bits per color, 40MHz clock
•XGA 1024x768@60Hz, 8 bits per color, 65MHz clock
•SXGA 1280x1024@60Hz, 8 bits per color, 108MHz clock
•SXGA 1280x1024@85Hz, 8 bits per color, 135MHz clock
•UXGA 1600x1200@60Hz, 8 bits per color, 162MHz clock
•WUXGA 1920x1200@60Hz, 8 bits per color, Reduced Blanking,
154 MHz clock
•WUXGA 1920x1200@60Hz, 6 bits per color, 193 MHz clock
Setup:
•Tektronix VM6000
•DPVGA4 dongle
COMPANY CONFIDENTIAL 34
PTN3392 VGA DAC INL Measurement Update
Set up: Tektronix VM6000
DAC INL previously failing at some resolutions
–
Determined that VM6000 has linearity anomalies for given
sensitivity and offset settings that impact results
–
Sensitivity changed from 96mV/div to 80 mV /div
_
Measurement averages set to “3”, waveform averages
set to 500 to compensate for oscilloscope noise effects
Measurements retaken with results below. Previously
failing resolutions highlighted in dark orange
DPVGA4 dongle
Status: Previously failing
resolutions NOW PASS
Datasheet updated to reflect
INL of <+/-1 LSB
' 6 -7
5
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COMPANY CONFIDENTIAL 35
Interface Products / Ho Wai Wong-Lam
June 22, 2010
DPVGA4 EMI Test Results and Findings
EMI Chamber Tests
Test Setup
30MHz to 1GHz
Resolution: 800 x 600
30MHz to 1GHz
Resolution: 1600 x 1200
30MHz to 1GHz
Resolution: 1280 x 1024
1GHz to 6GHz
DPVGA4 Prototype Dongle with PTN3392
Dell Latitude E6500 with power supply and mouse
Scrolling “H” pattern
Philips Brilliance 200P LCD monitor
Resolutions Tested
800 x 600; 1600 x 1200, 1280 x 1024
EMI Test Findings
PASS CISPR22B without metal shielding
(however, without the desired 3-6dB margin)
PI-filter is indeed not necessary for EMI
reasons
1GHz to 6GHz
However, RGB filtering needed to pass VSIS
1GHz to 6GHz
Semi-Anechoic Chamber
Recommend metal tape around VGA connector
or metal cage
CONFIDENTIAL
36
NXP PL-Interface Products, 2009
DPVGA4 IEC61000-4-2 ESD Tests
Test Performed
ESD –
Enclosure
Test date
Level
Criteria/Result
Comment
2010/02/19
4
B / Pass
Notes Deviations
Pass
Pass without external
ESD Protection Devices!
CONFIDENTIAL
Interface Products / Ho
37
NXP PL-Interface
Products,
2009
Wai Wong-Lam
June
22, 2010
DPVGA4 IEC61000-4-2 ESD Tests
Indirect Discharges
(to Coupling
Planes)
Positive Polarity
Negative Polarity
(kV)
(kV)
Contact Mode
Level 1
2
4
6
8
2
4
6
8
VCP located 10cm
from the front, rear,
left, and right sides of
the EUT
X
X
X
X
X
X
X
X
HCP located 10cm
from the front, rear,
left, and right sides of
the EUT
X
X
X
X
X
X
X
X
Direct Discharges
(to the EUT)
Contact Mode
Level 2
Level 3
Level 4
Level 1
Positive Polarity
Level 2
Level 3
Level 4
Negative Polarity
(kV)
(kV)
Level 1
Level 2
Level 3
Level 4
Level 1
Level 2
Level 3
Level 4
2
4
6
8
2
4
6
8
VGA shell
X
X
X
X
X
X
X
X
Display Port shell
X
X
X
X
X
X
X
X
Air Discharge
Mode
Contact Mode
Level 1
Positive Polarity
Negative Polarity
(kV)
(kV)
Level 2
Level 3
Level 4
Level 1
Level 2
Level 3
Level 4
2
4
8
15
2
4
8
15
VGA shell
X
X
X
X
X
X
X
Note 3
Display Port shell
X
X
X
X
X
X
X
Note 3
Note 1: An “X” indicates that the EUT continued to operate as intended
Note 2: ND: No discharges was possible due to lack of discharge path to ground from test point.
HCP: Horizontal Coupling Plane,
VCP: Vertical Coupling Plane.
Note 3: Image disappeared but returned to normal by itself. Criterion B.
Note 4: 10 positive and 10 negative discharges applied to each side of EUT
CONFIDENTIAL
Interface Products / Ho
38
NXP PL-Interface
Products,
2009
Wai Wong-Lam
June
22, 2010
APPENDIX: Interoperability Test Suites
COMPANY CONFIDENTIAL 39
DisplayPort Sources
#
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Sinks (Monitors used w/ VGA)
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VGA Cables Used
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8
8
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COMPANY CONFIDENTIAL 40
Interface Products / Ho Wai Wong-Lam
June 22, 2010
Interoperability Test Matrix
COMPANY CONFIDENTIAL 41
Interface Products / Ho Wai Wong-Lam
June 22, 2010
Resolution Figure of Merit
Definition: Resolution Figure of Merit =
Average score of all resolution tests
•
•
Each source-to-sink combination may
have a unique # and list of
resolutions
Each test score has equal weight
– Each test gets a score on a scale of 1
to 10.
•
•
•
–
1 = failed test, not user fixable
– E.g. Permanent Blinking, blanking,
flashing
5 = fixable or occasional flaw
– E.g. by changing resolution image may
be restored
10 = pass
– Perfect image
Interpretation Guide
• 10 = Perfect (our goal)
• Score 9.9 acceptable
• 1 = Total Failure
COMPANY CONFIDENTIAL 42
Interface Products / Ho Wai Wong-Lam
June 22, 2010
Overall Figure of Merit
Definition: Overall Figure of Merit =
Average score of all interop tests
•
•
•
Each source-to-sink combination may
have a unique # and list of all tests
Each test score has equal weight
Tests include Hotplug, EDID, Clone,
Primary, etc.. AND all resolution tests
– Each test gets a score on a scale of 1
to 10.
•
1 = permanently failed test, not user
fixable
–
•
2 = largely failed test
–
•
E.g. @ the native resolution the test fails,
multiple Hot-plugs fixes error
8 = fixable or occasional flaw, minor
–
•
E.g. 7 out of 8 Hot-plugs fail
5 = fixable or occasional flaw
–
•
E.g. Permanent Hot-plug fail, simple
primary no image
E.g. @ mid-range resolution the test
fails, occasional random test fail
10 = pass
–
Perfect image
COMPANY CONFIDENTIAL 43
Interface Products / Ho Wai Wong-Lam
June 22, 2010
Interop Status
Interoperability
Good interoperability
Windows (Dell) / NVIDIA GeForce 9400GT
Good Interoperability
Windows (Dell)/NVIDIA Quadro NVS 160M
Good Interoperability
Mac OS X (Apple) / NVIDIA GeForce 9400M
Good Interoperability
Windows (Dell) / Intel GMA4500 chipset
Good Interoperability
Windows (Lenovo) / ATI Radeon HD5750
Good Interoperability
Windows (Lenovo) / NVIDIA Quadro FX 2700M
Good Interoperability
Windows (Dell) / NVIDIA GeForce 9400M
Good Interoperability
Windows (HP) / Intel GMA4500 chipset
Good Interoperability
Windows (Intel Customer Reference Board) / Intel HD Graphics
Good Interoperability
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COMPANY CONFIDENTIAL 44
Interface Products / Ho Wai Wong-Lam
June 22, 2010
Thank you !
COMPANY CONFIDENTIAL 45
Interface Products / Ho Wai Wong-Lam
June 22, 2010