DFI Lanparty UT/LT X48-T3R BIOS Setting Guideline

DFI Lanparty UT/LT X48-T3R
BIOS Setting Guideline
(BIOS version: 2008/8/29) V001
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Pressing DEL at DFI UT/LT X38 LOG screen to login BIOS setup screen
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BIOS setup screen
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Genie BIOS settings: This setup thread is combined all needed settings for over clocking
(CPU speed setting, CPU features, DRAM timings, Voltage settings and PCI speed etc.)
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Genie BIOS : Main setup screen
Exist Setup Shutdown: Mode1/Mode2
Somehow it’s a “characteristic” of Intel chipset when overclocking… it will shutdown after tweaking. For that, DFI
has 2 different modes to chose:
Mode 1) when the system was boot-up, it will run a little “diagnose”.
If the CPU frequency doesn’t change too much, it will skip the “shutdown” function and rewrite the clock generator
directly.
Mode 2) no matter how little the CPU clock or DRAM’s ratio has been changed,
The system still “shutdown” and reboot by itself
Shutdown after AC Loss: Enable / Disable
System Power recovers item. (Enabled for power on system automatically if AC power failure)
OC Fail Retry Counter: 0~3 times
OC fail retry looping setting. For example, set it on 1, it will retry boot again if fail, then auto back CPU default
value to boot system.
CPU Clock ratio:
CPU multiplier setting, 6~11 for locked processors, 6~50 times for unlocked processors
CPU N/2 Ratio: Disable / Enable
CPU 0.5 multiplier supporting, it depends on CPU type and auto pop put item when detected a 0.5
multiplier supported CPU.
CPU Clock range:
Boot-up clock: Auto/ 100MHz ~410MHz
This function can help you out for setting a lower boot up clock. As a buffer, when your FSB is tweaked
too high in the beginning. The process will to be: system boot up with “Boot-up clock” first, after that it
will change to your highest FSB.
CPU Clock Amplitude :
Clock output strength, to add it for increasing grow weaker signal to terminal devices, default value is
700mV, max out put is 1000mv.
CPU Clock Skew0 :
The skew of clock signal for CPU; To achieve higher FSB, please add more ps for increasing CPU OC
ability. Default value is 0mV, max out put is 1500mv.
*** Recommend to add 100ps~200ps when if the FSB is higher to 500~600MHz or DRAM speed at
1800~2000MHz
CPU Clock Skew1 :
The skew of clock signal for North-Bridge; To achieve higher FSB, please add more ps for increasing
CPU OC ability. Default value is 0mV, max out put is 1500mv.
DRAM Speed:
PCIE Clock:
PCIE Slot Config:
PCIE 2 and PCIE 4 transferring status:
1X 1X : PCIE 2 / 4 are running with 1X model
4X NC: PCIE4 is running 4X mode, PCIE 2 will be disable and on board LAN2 will be disable as well.
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CPU Feature:
(For gaining a maximum CPU utilization, we will always disable all CPU key features except “Core
multi-Processing”)
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DRAM Timing:
Enhance Data Transmitting: Auto / Normal / First / Turbo
DFI specifically designed a “fine-tune mode” for DATA transmitting performance, Normal for lowest
performance, Fast for highest performance, Default AUTO will automatically adjust performance based
on current system Front Side BIOS.
Enhance Addressing: Auto / Normal / First
DFI specifically designed a “fine-tune mode” for DATA addressing, “Normal” for lowest performance,
“Fast” for highest performance, Default AUTO will automatically adjust performance based on current
system Front Side BIOS.
T2 Dispatch: Auto/ Enabled / Disabled
DRAM performance parameters patch, enabling for getting optimized and disabling to relax DRAM
timing for running higher working frequency on modules.
Performance level:
It is tRD of DRAM parameter
Read delay phase adjust:
It is the fine-tune feature for tRD
MCH ODT Latency:
DRAM ODT read/Write latency,
(Basically ODT is On Die Termination, it likes a variable resistor termination to protect DATA signal
integrity from high frequency interference)
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CLK setting fine delay:
DRAM CLK Driving Strength: Level 1~8
DRAM Data Driving Strength: Level 1~8
CH1 DLL Default Skew Model: Model 0~7
CH1 DLL Default Skew Model: Model 0~7
***DRAM DLL table is a base for calculating clock delays; they are very important parameters for
control singles delivering between CPU, NB and DRAM. Genie BIOS has provided 7 models to make
more suitable parameters for running higher DDR3 speed.
*** Recommend fine delay settings for PC3 12800 and 14400 ***
Micro D9 chips:
Fine delay setting: 3/8/3/3, 3/8/4/4 and 4/7/4/4
Samsung chips:
Fine delay setting: 3/8/5/5, 3/8/6/6 and 4/6/7/7
Fine Delay Step Degree:
Scale gap from 5ps ~80ps, each scale can be able to adjust 31 degree steps.
How to use it?
For example: if you would like to manual set 310ps for DIMM1 Clock fine delay
Fine Delay Step Degree=10ps
DIMM 1 Clock Fine Delay=31 DEG
Ch1 / Ch2 Clock Crossing Setting :
Auto / More aggressive /aggressive / Nominal / Relaxed / More Relaxed
Giving an easy explanation, after the CPU, PCIE, DRAM locked the clock phase by “PLL phase locked
loop”, we can utilize the DRAM DLL to adjust DRAM operating phase by tuning DRAM DATA output
phase forward or backward to create a better match with current DATA operating phase.
The BIOS will automatically calculate a parameter after system boot up.
The BIOS will show the current value of this parameter.
The best tuning range for finding the best DATA operating phase will be 3 ranks before or after this
current value.
Ch1Ch2 CommonClock Setting:
Auto / More aggressive /aggressive / Nominal / Relaxed / More Relaxed
As above, it is PLL fine-tune for Common clock signals of DRAM modules.
Ch1/Ch2 RDCAS GNT-Chip Delay: Auto /1~7 CLK
Read command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N disable mode
Ch1/Ch2 WRCAS GNT-Chip Delay: Auto /1~7 CLK
Write command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N disable mode
Ch1/Ch2 Command to CS Delay: Auto /1~7 CLK
DRAM module bank selecting command rate, 1Clock is Intel Command rate 1N mode, 2~7Clock are 1N
disable
mode
Common CMD to CS Timing”
DRAM command rate mode 1N and 2N (1N disable) selection.
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Voltage Settings:
CPU VID Control range: 0.90V ~ 1.60V
CPU VID Special Add Limit: Enable / Disable
CPU special add rage, Enable to 114% maximum, Disable for 130% maximum
CPU VID Special Add:100% ~114% (130% when above item is disabled)
DRAM Voltage range: 1.208V~2.450V (default 1.521V
SB Core / CPU PLL voltage: (1.51V~2.38V)
These two voltages are controlling by same adjustable circuit, increasing CPU PLL voltage higher is
better for gaining a stable OC situation.
NB Core Voltage: (1.265V~2.040V)
CPU VTT Voltage:
Vcore drop control: Enable / Disabled
Enabling to control Vout level by PWM, disabling to get a maximum output.
Clockgen voltage control: (3.45V~3.85V)
Clock working voltage, increase it to achieve higher and more stable in extreme FSB environment
GTL+ buffer Strength: Strong / Weak
It is adjustment option for North-Bridge reference voltage strength.
Host Slew Rate: Strong / Weak
It is adjustment option for North-Bridge voltage driving strength.
GTL REF Voltage control: Enable / Disabled
CPU VTT reference voltage for determining host bus high / low level.
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Manual MCH parameter Table:
To change default MCH parameter registers for reaching highest FSB. Some of CPU can broken FSB wall after
modified following values.
*** Recommend settings ***
MCH RON Offset Value: 00
MCH RTT Offset Value: 00
MCH Skew Rate Offset Value: 00
MCH VREF 1 Value: 00 /23 /24 /26
MCH VREF 2 Value: 00 /23 /24 /26
MCH VREF 3 Value: 80 /8A
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Manual GTL Voltage Table:
VTT BIOS Setting
CPU GTL 1/2 REF. BIOS
CPU GTL 0/3 REF. BIOS
(Real)
Setting (Real)
Setting (Real)
1.100V (1.060V)
95 (0.711V)
90 (0.713V)
75 (0.716V)
1.250V (1.213V)
110 (0.812V)
105 (0.816V)
85 (0.812V)
1.35V (1.310V)
120 (0.878V)
110 (0.875V)
90 (0.873V)
1.453V (1.411V )
130 (0.947V)
120 (0.945V)
100 (0.945V)
1.553V(1.508V)
140 (1.014V)
130 (1.014V)
110 (1.015V)
1.603V (1.550V)
140 (1.038V)
130 (1.037V)
110 (1.041V)
NB GTL REF.BIOS Setting (Real)
GTL REF voltage Difinition= 0.67% VTT, Please choose a correct value for VTT when "GTL REF Voltage" item was selected on
Manual.
For details, please link to: http://dfics.dfi.com.tw/dfi_cs/LTX48/X38X48_vtt.xls
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BIOS Reloaded function: DFI Lan Party series are providing 1last fine status + 4 user’s profile
space for doing BIOS setting saving and recovery.
Auto Save bootable setting: Enable / Disable
For saving last fine/ bootable parameters by BIOS itself every time
Load last bootable:
For loading last BIOS parameters.
Save setting to bank with: Current settings or last saved CMOS settings.
To define the resource of parameters for bank saving.
User define setting bank #1 ~ #4:
1. Bank Description: There are 4 rows for writing a short description. Double click on row when this
row is empty, it will erase pervious data.
2. Save to this bank: Press “Y” to save data to this bank
3. Load from this bank: Press “Y” to load data of this bank to be current BIOS setup settings.
4. Hotkey =>: define the “hotkey” for a quick change BIOS settings to boot. Please press Hotkey after
power on system immediately.
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EZ Clear CMOS methods:
a. To
press POWER + Reset bottoms for 5sec when 5Vsb existed, by doing that current CMOS data will be
clear
b. To hold Home key to power on system, BIOS will recover FSB to default, remains setting will be keeping
the last time fine status.
c. To hold Insert key to power on system, BIOS will load all setting back to default as like doing a CCMOS
by manually.
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