740 Family Software Manual

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User’s Manual
8
740 Family
Software Manual
RENESAS MCU
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Rev.2.00 2006.11
Notes regarding these materials
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740 Family Software Manual
REVISION HISTORY
Rev.
Date
Description
Page
Summary
1.00 Aug 29, 1997
–
First edition issued
2.00 Nov 14, 2006
–
Changed to the RENESAS style.
“Preface” is changed to “Using This Manual”.
4
2.5 Processor Status Register: Description added.
26
3.2 Instruction Set : Description revised.
31
ADC : Note 2 is revised.
53
CMP : Function revised.
60
DIV : Note 3 is added.
65
JMP : Note is added.
72, 133, 134 XX instruction cannot be used for any products → XX instruction cannot be used
for some products.
72
MUL : Note 3 is added.
74
ORA : N is when bit 7..... → N is “1” when bit 7.....
78
PLP : Note is added.
82
RTI : Status flag is revised.
83
RTS : Operation is revised.
84
SBC : Note 2 is revised.
101
WIT : Function is revised.
102 to 104 3.4 Instructions Related to Interrupt Processing and Subroutine Processing added.
105
NOTES ON USE : “4.1 Notes on input and output ports” is added.
107
Fig. 4.3.1 is revised.
4.3.2 : Description revised.
108
4.3.3 Distinction of interrupt request bit : Description revised.
Fig. 4.3.2 is revised.
110
Fig. 4.4.4 is revised.
111
“4.4.5 Multiplication and division instruction”, “4.4.6 Ports” and
“4.4.7 Instruction execution time” are added.
112
Valid signal for each product : Table is revised and note is added.
178
Part of instruction table is revised.
184
Part of instruction code is revised.
Table of products which unuse these instructions is eliminated.
A-1
Using This Manual
This software manual is written for the 740 Family. It applies to all microcomputers integrating the 740
Family CPU core.
The reader of this manual is assumed to have a basic knowledge of electrical circuits, logic circuits, and
microcomputers.
740 Family Documents
The following documents were prepared for the 740 family.
Document
Data Sheet
Software Manual
Application Note
Contents
Hardware overview and electrical characteristics
Hardware specifications (pin assignments, memory maps, peripheral
specifications, electrical characteristics, timing charts).
Detailed description of assembly instructions and microcomputer
performance of each instruction
• Usage and application examples of peripheral functions
• Sample programs
Table of contents
Table of contents
CHAPTER 1. OVERVIEW ............................................................................................ 1
CHAPTER 2. CENTRAL PROCESSING UNIT (CPU) ............................................. 2
2.1
2.2
2.3
2.4
2.5
Accumulator (A) ........................................................................................................................ 2
Index Register X (X), Index Register Y (Y) ........................................................................ 2
Stack Pointer (S) ...................................................................................................................... 3
Program Counter (PC) ............................................................................................................. 4
Processor Status Register (PS) ............................................................................................ 4
CHAPTER 3. INSTRUCTIONS .................................................................................... 6
3.1 Addressing Mode ...................................................................................................................... 6
3.2 Instruction Set ......................................................................................................................... 26
3.2.1 Data transfer instructions ............................................................................................... 26
3.2.2 Operating instruction ....................................................................................................... 27
3.2.3 Bit managing instructions ............................................................................................... 28
3.2.4 Flag setting instructions ................................................................................................. 28
3.2.5 Jump, Branch and Return instructions ......................................................................... 28
3.2.6 Interrupt instruction (Break instruction) ........................................................................ 29
3.2.7 Special instructions ......................................................................................................... 29
3.2.8 Other instruction .............................................................................................................. 29
3.3 Description of instructions .................................................................................................. 30
3.4 Instructions Related to Interrupt Handling and Subroutine Processing ................... 31
3.4.1 Instructions Related to Interrupt Handling ................................................................... 31
3.4.2 Instructions Related to Interrupt Control ...................................................................... 31
3.4.3 Instructions Related to Subroutine Processing ........................................................... 32
CHAPTER 4. NOTES ON USE ............................................................................... 105
4.1 Notes on input and output ports ..................................................................................... 105
4.1.1 Notes in standby state ................................................................................................. 105
4.1.2 Modifying output data with bit managing instruction ................................................ 105
4.2 Termination of unused pins ............................................................................................... 106
4.2.1 Appropriate termination of unused pins ..................................................................... 106
4.2.2 Termination remarks ..................................................................................................... 106
4.3 Notes on interrupts .............................................................................................................. 107
4.3.1 Setting for interrupt request bit and interrupt enable bit ......................................... 107
4.3.2 Switching of detection edge ........................................................................................ 107
4.3.3 Distinction of interrupt request bit .............................................................................. 108
4.4 Notes on programming ....................................................................................................... 109
4.4.1 Processor Status Register ........................................................................................... 109
4.4.2 BRK instruction .............................................................................................................. 110
4.4.3 Decimal calculations ..................................................................................................... 110
4.4.4 JMP instruction .............................................................................................................. 111
4.4.5 Multiplication and division instructions ....................................................................... 111
4.4.6 Ports ................................................................................................................................ 111
4.4.7 Instruction execution time ............................................................................................ 111
A-1
Table of contents
APPENDIX 1. Instruction Cycles in each Addressing Mode ........................ 112
APPENDIX 2. 740 Family Machine Language Instruction Table .................. 178
APPENDIX 3. 740 Family list of Instruction Codes ........................................ 184
<Addressing Mode>
Immediate .................................. 7
Accumulator .............................. 8
Zero Page ................................. 9
Zero Page X ........................... 10
Zero Page Y ........................... 11
Absolute .................................. 12
Absolute X .............................. 13
Absolute Y .............................. 14
Implied ..................................... 15
Relative ................................... 16
Indirect X ................................ 17
Indirect Y ................................ 18
Indirect Absolute .................... 19
Zero Page Indirect ................. 20
Special Page .......................... 21
Zero Page Bit ......................... 22
Accumulator Bit ...................... 23
Accumulator Bit Relatibe ...... 24
Zero Page Bit Relative ......... 25
<Instructions>
ADC .......................... 34
AND .......................... 35
ASL ........................... 36
BBC ........................... 37
BBS ........................... 38
BCC .......................... 39
BCS ........................... 40
BEQ .......................... 41
BIT ............................ 42
BMI ........................... 43
BNE ........................... 44
BPL ........................... 45
BRA ........................... 46
BRK ........................... 47
BVC ........................... 48
BVS ........................... 49
CLB ........................... 50
CLC ........................... 51
CLD ........................... 52
CLI ............................ 53
CLT ........................... 54
CLV ........................... 55
CMP .......................... 56
COM.......................... 57
CPX........................... 58
CPY........................... 59
DEC .......................... 60
DEX........................... 61
DEY........................... 62
DIV ............................ 63
EOR .......................... 64
INC ............................ 65
INX ............................ 66
INY ............................ 67
JMP ........................... 68
JSR ........................... 69
LDA ........................... 70
LDM .......................... 71
LDX ........................... 72
LDY ........................... 73
LSR ........................... 74
MUL .......................... 75
NOP .......................... 76
ORA .......................... 77
PHA ........................... 78
PHP ........................... 79
PLA ........................... 80
PLP ........................... 81
ROL ........................... 82
ROR .......................... 83
RRF ........................... 84
RTI ............................ 85
RTS ........................... 86
SBC ........................... 87
SEB ........................... 88
SEC ........................... 89
SED ........................... 90
A-2
SEI ............................ 91
SET ........................... 92
STA ........................... 93
STP ........................... 94
STX ........................... 95
STY ........................... 96
TAX ........................... 97
TAY ........................... 98
TST ........................... 99
TSX ......................... 100
TXA ......................... 101
TXS ......................... 102
TYA ......................... 103
WIT ......................... 104
OVERVIEW
1. OVERVIEW
The distinctive features of the CMOS 8-bit microcomputers 740 Family’s software are described
below:
1) An efficient instruction set and many addressing modes allow the effective use of ROM.
2) The same bit management, test, and branch instructions can be performed on the Accumulator, memory, or I/O area.
3) Multiple interrupts with separate interrupt vectors allow servicing of different non-periodic
events.
4) Byte processing and table referencing can be easily performed using the index addressing
mode.
5) Decimal mode needs no software correction for proper decimal operation.
6) The Accumulator does not need to be used in operations using memory and/or I/O.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 1 of 185
CENTRAL PROCESSING UNIT
Accumulator (A)
Index Register X (X), Index Register Y (Y)
2. CENTRAL PROCESSING UNIT (CPU)
Six main registers are built into the CPU of the 740 Family.
The Program Counter (PC) is a sixteen-bit register; however, the Accumulator (A), Index
Register X (X), Index Register Y (Y), Stack Pointer (S) and Processor Status Register (PS)
are eight-bit registers.
☞ Except for the I flag, the contents of these registers are indeterminate after a hardware
reset; therefore, initialization is required with some programs (immediately after reset the I
flag is set to “1”).
7
0
Accumulator(A)
A
7
0
Index Register X(X)
X
7
0
Index Register Y(Y)
Y
7
0
S
7
0 7
PC H
Stack Pointer(S)
0
PC L
7
0
N V T B D I Z C
Program Counter(PC)
Processor
Status Register(PS)
Carry Flag
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag (BRK)
X Modified Operation Mode Flag
Overflow Flag
Negative Flag
Fig.2.1.1 Register Configuration
2.1 Accumulator (A)
The Accumulator, an eight-bit register, is the main register of the microcomputer.
This general-purpose register is used most frequently for arithmetic operations, data transfer,
temporary memory, conditional judgments, etc.
2.2 Index Register X (X), Index Register Y (Y)
The 740 Family has an Index Register X and an Index Register Y, both of which are eightbit registers.
When using addressing modes which use these index registers, the address, which is added
the contents of Index Register to the address specified with operand, is accessed. These
modes are extremely effective for referencing subroutine and memory tables.
The index registers also have increment, decrement, compare, and data transfer functions;
therefore, these registers can be used as simple accumulators.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 2 of 185
CENTRAL PROCESSING UNIT
Stack Pointer (S)
2.3 Stack Pointer (S)
The Stack Pointer is an eight-bit register used for generating interrupts and calling subroutines.
When an interrupt is received, the following procedure is performed automatically in the
indicated sequence:
(1) The contents of the high-order eight bits of the Program Counter (PCH) are saved to
an address using the Stack Pointer contents for the low-order eight bits of the address.
(2) The Stack Pointer contents are decremented by 1.
(3) The contents of the low-order eight bits of the Program Counter (PCL) are saved to an
address using the Stack Pointer Contents for the low-order eight bits of the address.
(4) The Stack Pointer contents are decremented by 1.
(5) The contents of the Processor Status Register (PS) are saved to an address using the
Stack Pointer contents for the low-order eight bits of the address.
(6) The Stack Pointer contents are decremented by 1.
The Processor Status Register is not saved when calling subroutines (items (5) and (6) above
are not executed). The Processor Status Register is saved by executing the PHP instruction
in software.
To prevent data loss when generating interrupts and calling subroutines, it is necessary to
save other registers as well. This is done by executing the proper instruction in software while
in the interrupt service routine or subroutine.
The high-order eight bits of the address are determined by the Stack Page Selection Bit.
For example, the PHA instruction is executed to save the contents of the Accumulator.
Executing the PHA instruction saves the Accumulator contents to an address using the Stack
Pointer contents as the low-order eight bits of the address.
The RTI instruction is executed to return from an interrupt routine.
When the RTI instruction is executed, the following procedure is performed automatically in
sequence.
(1) The Stack Pointer contents are incremented by 1.
(2) The contents of an address using the Stack Pointer contents as the low-order eight bits
of the address is returned to the Processor Status Register (PS).
(3) The Stack Pointer contents are incremented by 1.
(4) The contents of an address using the Stack Pointer as the low-order eight bits of the
address is returned to the low-order eight bits of the Program Counter (PCL).
(5) The Stack Pointer contents are incremented by 1.
(6) The contents of an address using the Stack Pointer as the low-order eight bits of the
address is returned to the high-order eight bits of the Program Counter (PCH).
Steps (1) and (2) are not performed when returning from a subroutine using the RTS
instruction. The Processor Status Register should be restored before returning from a
subroutine by using the PLP instruction. The Accumulator should be restored before returning
from a subroutine or an interrupt servicing routine by using the PLA instruction.
The PLA and PLP instructions increment the Stack Pointer by 1 and return the contents of an
address stored in the Stack Pointer to the Accumulator or Processor Status Register, respectively.
☞ Saving data in the stack area gradually fills the RAM area with saved data; therefore,
caution must exercised concerning the depth of interrupt levels and subroutine nesting.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 3 of 185
CENTRAL PROCESSING UNIT
Program Counter (PC)
Processor Status Register (PS)
2.4 Program Counter (PC)
The Program Counter is a sixteen-bit counter consisting of PCH and PCL, which are each
eight-bit registers. The contetnts of the Program Counter indicates the address which an
instruction to be executed next is stored.
The 740 Family uses a stored program system; to start a new operation it is necessary to
transfer the instruction and relevant data from memory to the CPU.
Normally the Program Counter is used to indicate the next memory address. After each
instruction is executed, the next instruction required is read. This cycle is repeated until the
program is finished.
☞ The control of the Program Counter of the 740 Family is almost fully automatic. However,
caution must be exercised to avoid differences between program flow and Program
Counter contents when using the Stack Pointer or directly altering the contents of the
Program Counter.
2.5 Processor Status Register (PS)
The Processor Status Register is an eight-bit register consisting of 5 flags which indicate the
status of arithmetic operations and 3 flags which determine operation. Immediately after a
reset, only the interrupt disable flag is set to “1,” and the other flags are undefined. Therefore,
initialize the flags that effect program execution. Especially, initialize the T and D flags because
of their effect on operation.
Each of these flags is described below. Table 2.5.1 lists the instructions to set/clear each flag.
Refer to the section “Appendix 2 MACHINE LANGUAGE INSTRUCTION TABLE” or “3.3
INSTRUCTIONS” for details on when these flags are altered.
[ Carry flag C ] ------------------------------------------------------ Bit 0
This flag stores any carry or borrow from the Arithmetic Logic Unit (ALU) after an arithmetic
operation and is also changed by the Shift or Rotate instruction.
This flag is set by the SEC instruction and is cleared by the CLC instruction.
[ Zero flag Z ] ------------------------------------------------------- Bit 1
This flag is set when the result of an arithmetic operation or data transfer is “0” and is
cleared by any other result.
[ Interrupt disable flag I ] ---------------------------------------- Bit 2
This flag disables interrupts when it is set to “1.” This flag immediately becomes “1” when
an interrupt is received.
This flag is set by the SEI instruction and is cleared by the CLI instruction.
[ Decimal mode flag D ] ----------------------------------------- Bit 3
This flag determines whether addition and subtraction are performed in binary or decimal
notation. Addition and subtraction are performed in binary notation when this flag is set to
“0” and as a 2-digit, 1-word decimal numeral when set to “1.” Decimal notation correction
is performed automatically at this time.
This flag is set by the SED instruction and is cleared by the CLD instruction.
Only the ADC and SBC instructions are used for decimal arithmetic operations.
Note that the flags N, V and Z are invalid when decimal arithmetic operations are performed by these instructions.
[ Break flag B ] ----------------------------------------------------- Bit 4
This flag determines whether an interrupt was generated with the BRK instruction. When a
BRK instruction interrupt occurs, the flag B is set to “1” and saved to the stack; for all other
interrupts the flag is set to “0” and saved to the stack.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 4 of 185
CENTRAL PROCESSING UNIT
Processor Status Register (PS)
[ X modified operation mode flag T ] ----------------------- Bit 5
This flag determines whether arithmetic operations are performed via the Accumulator or
directly on a memory location. When the flag is set to “0”, arithmetic operations are
performed between the Accumulator and memory. When “1”, arithmetic operations are
performed directly on a memory location.
This flag is set by the SET instruction and is cleared by the CLT instruction.
(1) When the T flag = 0
A ← A * M2
* : indicates an arithmetic operation
A: accumulator contents
M2: contents of a memory location specified by the addressing mode of the
arithmetic operation
(2) When the T flag = 1
M1 ← M1 * M2
* : indicates arithmetic operation
M1: contents of a memory location, designated by the contents of Index
Register X.
M2: contents of a memory location specified by the addressing mode of
arithmetic operation.
[ Overflow flag V ] ------------------------------------------------- Bit 6
This flag is set to “1” when an overflow occurs as a result of a signed arithmetic operation.
An overflow occurs when the result of an addition or subtraction exceeds +127 (7F16) or
–128 (8016) respectively.
The CLV instruction clears the Overflow Flag. There is no set instruction.
The overflow flag is also set during the BIT instruction when bit 6 of the value being tested
is “1.”
☞ Overflows do not occur when the result of an addition or subtraction is equal to or
smaller than the above numerical values, or for additions involving values with different
signs.
[ Negative flag N ] ------------------------------------------------- Bit 7
This flag is set to match the sign bit (bit 7) of the result of a data or arithmetic operation.
This flag can be used to determine whether the results of arithmetic operations are positive
or negative, and also to perform a simple bit test.
Table 2.5.1 Instructions to set/clear each flag of processor status register
Flag D Flag B
Flag Z
Flag V
Flag C
Flag I
Flag T
SED
Set instruction
SEC
SEI
SET
CLD
CLV
Clear instruction
CLC
CLI
CLT
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Flag N
INSTRUCTIONS
Addressing mode
3. INSTRUCTIONS
3.1 Addressing Mode
The 740 Family has 19 addressing modes and a powerful memory access capability. When
extracting data required for arithmetic and logic operations from memory or when storing the
results of such operations in memory, a memory address must be specified. The specification
of the memory address is called addressing. The data required for addressing and the
registers involved are described below. The 740 Family instructions can be classified into three
kinds, by the number of bytes required in program memory for the instruction: 1-byte, 2-byte
and 3-byte instructions. In each case, the first byte is known as the “Op-Code (operation
code)” which forms the basis of the instruction. The second or third byte is called the “operand” which affects the addressing. The contents of index registers X and Y can also effect the
addressing.
1-byte instruction
2-byte instruction
3-byte instruction
AAAAA AAAAAAAAAA
AAAAA AAAAAAAAAA
Op-Code
Op-Code
Op-Code
Operand I
Operand I
Index Register
X
Y
Y
Operand II
Fig.3.1.1 Byte Structure of Instructions
Although there are many addressing modes, there is always a particular memory location
specified. What differs is whether the operand, or the index register contents, or a combination
of both should be used to specify the memory or jump destination. Based on these 3 types
of instructions, the range of variation is increased and operation is enhanced by combinations
of the bit operation instructions, jump instruction, and arithmetic instructions.
As for 1-byte instruction, an accumulator or a register is specified, so that the instruction does
not have “operand,” which specify memory.
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INSTRUCTIONS
Immediate
Addressing mode
Addressing mode : Immediate
Function : Specifies the Operand as the data for the instruction.
Instructions : ADC, AND, CMP, CPX, CPY, EOR, LDA, LDX, LDY,
ORA, SBC
Example : Mnemonic
∆ ADC∆
∆ #$A5
Machine code
6916 A516
This symbol(#) indicates the Immediate addressing mode.
Memory
Op-code (6916)
(A) ← (A) + (C) + A516
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Operand (A516)
INSTRUCTIONS
Accumulator
Addressing mode
Addressing mode : Accumulator
Function : Specifies the contents of the Accumulator as the data
for the instruction.
Instructions : ASL, DEC, INC, LSR, ROL, ROR
Example : Mnemonic
∆ ROL∆
∆A
C
bit
7
Carry flag
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Machine code
2A16
bit
0
Accumulator
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INSTRUCTIONS
Zero Page
Addressing mode
Addressing mode : Zero Page
Function : Specifies the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
using Operand as the low-order byte of the address
and 0016 as the high-order byte.
Instructions : ADC, AND, ASL, BIT, CMP, COM, CPX, CPY, DEC,
EOR, INC, LDA, LDM, LDX, LDY, LSR, ORA, ROL, ROR,
RRF, SBC, STA, STX, STY, TST
Example : Mnemonic
∆ADC∆
∆$40
Machine code
6516 4016
Memory
0016
Zero page
(A) ← (A) + (C) + XX16
Data(XX16)
4016
FF16
Zero page
designation
Op-code(6516)
Operand (4016)
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INSTRUCTIONS
Zero Page X
Addressing mode
Addressing mode : Zero Page X
Function : Specified the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
the following:
(a) Operand and the Index Register X are added. (If as
a result of this addition a carry occurs, it is
ignored.)
(b) The result of the addition is used as the low-order
byte of the address and 00 16 as the high-order
byte.
Instructions : ADC, AND, ASL, CMP, DEC, DIV, EOR, INC, LDA, LDY,
LSR, MUL, ORA, ROL, ROR, SBC, STA, STY
Example : Mnemonic
∆ADC∆
∆$5E,X
Machine code
7516 5E16
Memory
0016
Zero page
(A) ← (A) + (C) + XX16
Data(XX16)
4416
FF16
Zero page X
designation
Op-code (7516)
Operand (5E16)
+ E616 = 1 4416
Ignored
Contents of Index Register X
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INSTRUCTIONS
Zero Page Y
Addressing mode
Addressing mode : Zero Page Y
Function : Specifies the contents in a Zero Page memory
location as the data for the instruction. The address
in the Zero Page memory location is determined by
the following:
(a) Operand and the Index Register Y are added (if as
a result of this addition a carry occurs, it is ignored).
(b) The result of the addition is used as the low-order
byte of the address and 00 16 as the high-order
byte.
Instructions : LDX, STX
Example : Mnemonic
∆LDX∆
∆$62,Y
Machine code
B616 6216
Memory
0016
Zero page
(X) ← XX16
Data(XX16)
6816
FF16
Zero page Y
designation
Op-code (B616)
Operand (6216)
+ 0616 = 6816
Contents of Index Register Y
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INSTRUCTIONS
Absolute
Addressing mode
Addressing mode : Absolute
Function : Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by using Operand I as the loworder byte of the address and Operand II as the highorder byte.
Instructions : ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC,
JMP, JSR, LDA, LDX, LDY, LSR, ORA, ROL, ROR, SBC,
STA, STX, STY
Example : Mnemonic
∆ADC∆
∆$AD12
Machine code
6D16 1216 AD16
Memory
AAAAA
AAAAA
Op-code (6D16)
Operand I (1216)
Operand II (AD16)
Absolute
designation
(A) ← (A) + (C) + XX16
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Data (XX16)
AD1216
INSTRUCTIONS
Absolute X
Addressing mode
Addressing mode : Absolute X
Function : Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) Operand I is used as the low-order byte of an
address, Operand II as the high-order byte.
(b) Index Register X is added to the address above.
The result is the address in the memory location.
Instructions : ADC, AND, ASL, CMP, DEC, EOR, INC, LDA, LDY, LSR,
ORA, ROL, ROR, SBC, STA
Example : Mnemonic
∆ADC∆
∆$AD12, X
Machine code
7D16 1216 AD16
Memory
Contetns of Index
Register X
Op-code (7D16)
Operand I (1216)
+ EE16 = AE0016
Operand II (AD16)
Absolute X
designation
(A) ← (A) + (C) + XX16
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Data(XX16)
AE0016
INSTRUCTIONS
Absolute Y
Addressing mode
Addressing mode : Absolute Y
Function : Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) Operand I is used as the low-order byte of an
address, Operand II as the high-order byte.
(b) Index Register Y is added to the address above.
The result is the address in the memory location.
Instructions : ADC, AND, CMP, EOR, LDA, LDX, ORA, SBC, STA
Example : Mnemonics
∆ADC∆
∆$AD12, Y
Machine code
7916 1216 AD16
Memory
AAAAAA
AAAAAA
Contents of Index Register Y
Op-code (7916)
Operand I (1216)
+ EE16 = AE0016
Operand II (AD16)
Absolute Y
designation
(A) ← (A) + (C) + XX16
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Data(XX16)
AE0016
INSTRUCTIONS
Implied
Addressing mode
Addressing mode : Implied
Function : Operates on a given register or the Accumulator, but
the address is always inherent in the instruction.
Instructions : BRK, CLC, CLD, CLI, CLT, CLV, DEX, DEY, INX, INY,
NOP, PHA, PHP, PLA, PLP, RTI, RTS, SEC, SED, SEI,
SET, STP, TAX, TAY, TSX, TXA, TXS, TYA, WIT
Example : Mnemonic
∆CLC
Machine code
1816
Processor status register
bit 7
bit 0
?
Carry flag
Carry flag is cleared to “0.”
0
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INSTRUCTIONS
Relative
Addressing mode
Addressing mode : Relative
Function : Specifies the address in a memory location where the
next Op-Code is located.
When the branch condition is satisfied, Operand and
the Program Counter are added. The result of this
addition is the address in the memory location.
When the branch condition is not satisfied, the next
instruction is executed.
Instructions : BCC, BCS, BEQ, BMI, BNE, BPL, BRA, BVC, BVS
Example : Mnemonic
∆BCC∆∗
∆∗
∆∗–12
Machine code
9016 F216
Decimal
When the carry flag is cleared,
jumps to address *–12.
Memory
Memory
Address to be
executed next
When the carry flag is set,
goes to address *+2.
* –12
Jump
Op-code (9016)
*
*
Operand (F216)
Operand (F216)
* +2
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Op-code (9016)
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Address to be
executed next
* +2
INSTRUCTIONS
Indirect X
Addressing mode
Addressing mode : Indirect X
Function : Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) A Zero Page memory location is determined by the
adding the Operand and Index Register X (if as a
result of this addition a carry occurs, it is ignored).
(b) The result of the addition is used as the low-order
byte of an address in the Zero Page memory
location and 0016 as the high-order byte.
(c) The contents of the address in the Zero Page
memory location is used as the low-order byte of
the address in the memory location.
(d) The next Zero Page memory location is used as
the high-order byte of the address in the memory
location.
Instructions : ADC, AND, CMP, EOR, LDA, ORA, SBC, STA
Example : Mnemonic
∆ADC∆
∆($1E,X)
Machine code
6116 1E16
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Memory
Zero page
0016
Data I (0016)
0416
Data II (1416)
0516
FF16
Absolute
designation
Zero page X
designation
Op-code (6116)
Operand (1E16)
+ E616 = 1 0416
Ignored
(A)← (A) + (C) + XX16
Data(XX16)
140016
Contents of Index
Register X
Assuming that “0016” for Data I, and “1416” for Data ll are stored in advance.
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INSTRUCTIONS
Indirect Y
Addressing mode
Addressing mode : Indirect Y
Function : Specifies the contents in a memory location as the
data for the instruction. The address in the memory
location is determined by the following:
(a) The Operand is used the low-order byte of an
address in the Zero Page memory location and
0016 of the high-order byte.
(b) The contents of the address in the Zero Page
memory location is used as the low-order byte of
an address. The next Zero Page memory location
is used as the high-order byte.
(c) The Index Register Y is added to the address in
Step b. The result of this addition is the address
in the memory location.
Instructions : ADC, AND, CMP, EOR, LDA, ORA, SBC, STA
Example : Mnemonic
∆ADC∆
∆($1E),Y
Machine code
7116 1E16
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
Memory
Zero page
0016
Data I (0116)
1E16
Data II (1216)
1F16
Zero page
indirect
designation
Contents of Index Register Y
120116 + E616 = 12E716
FF16
Op-code (7116)
Absolute Y
designation
Operand (1E16)
(A) ← (A) + (C) + XX16
Data (XX16)
12E716
Assuming that “0116” for Data I, and “1216” for Data ll are stored in advance.
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INSTRUCTIONS
Indirect Absolute
Addressing mode
Addressing mode : Indirect Absolute
Function : Specifies the address in a memory location as the
jump destination address.
The address in the memory location is determined by
the following:
(a) Operand I is used as the low-order byte of an
address and Operand II as the high-order byte.
(b) The contents of the address above is used as the
low-order byte and the contents of the next
address as the high-order byte.
(c) The high-order and low-order bytes in step b
together form the address in the memory location.
Instructions : JMP
Example : Mnemonic
∆JMP∆
∆($1400)
Machine code
6C16 0016 1416
Memory
Op-code (6C16)
Operand I (0016)
Operand II (1416)
✽
Indirect
designation
Data I (FF16)
140016
Jump
Data II (1E16)
Absolute
designation
Address to be
executed next
1EFF16
Assuming that “FF16” for Data I, and “1E16” for Data ll are stored in advance.
Note: The page’s last address (address XXFF16) cannot be specified for the
indirect designation address; in other words, JMP ($XXFF) cannot be
executed.
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INSTRUCTIONS
Zero Page Indirect
Addressing mode
Addressing mode : Zero Page Indirect Absolute
Function : Specifies the address in a memory location as the
jump destination address. The address in the memory
location is determined by the following:
(a) Operand is used as the low-order byte of an
address in the Zero Page memory location and
0016 as the high-order byte.
(b) The contents of the address in the Zero Page
memory location is used as the low-order byte
and the contents of the next Zero Page memory
location as high-order byte.
(c) The high-order and low-order bytes in step b
together form the address of the memory location.
Instructions : JMP, JSR
Example : Mnemonic
∆JMP∆
∆($45)
Machine code
B216 4516
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAAAAA
AAA
A
AA
A
AAA
Memory
Zero page
Zero page
indirect
designation
0016
Data I (FF16)
4516
Data II (1E16)
4616
FF16
Absolute
designation
Op-code (B216)
Operand (4516)
∗
Jump
Address to be
executed next
1EFF16
Assuming that “FF16” for Data I, and “1E16” for Data ll are stored in advance.
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INSTRUCTIONS
Special Page
Addressing mode
Addressing mode : Special Page
Function : Specifies the address in a Special Page memory
location as the jump destination address. The address
in the Special Page memory location is determined by
using Operand as the low-order byte of the address
and FF16 as the high-order byte.
Instructions : JSR
Example : Mnemonic
∆ JSR∆
∆ \$FFC0
Machine code
2216 C016
This symbol indicates the Special page mode.
Memory
AAAAA
AAAAA
AAAAAAAA
AAA
A
AAAAA
A
AAAAA
A
AAAAA AA
A
AAAAA
AAAAA
AAAAA
AAAAA
Op-code (2216)
Operand (C016)
*
FF0016
Special page
designation
Jump
Address to be
executed next
FFC016
Special page
FFFF16
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INSTRUCTIONS
Zero Page Bit
Addressing mode
Addressing mode : Zero Page Bit
Function : Specifies one bit of the contents in a Zero Page
memory location as the data for the instruction.
Operand is used as the low-order byte of the address
in the Zero Page memory location and 00 16 as the
high-order byte. The bit position is designated by the
high-order three bits of the Op-code.
Instructions : CLB, SEB
Example : Mnemonic
∆CLB∆
∆5,$44
Machine code
BF16 4416
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Memory
0016
Zero page
bit 5
4416
?
FF16
Zero page
designation
Bit designation
Op-code(BF16)
1 0 1 1 1 1 1 1
Operand (4416)
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
AAA
Zero page
bit 5
0
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4416
INSTRUCTIONS
Accumulator Bit
Addressing mode
Addressing mode : Accumulator Bit
Function : Specifies one bit of the Accumulator as the data for
the instruction. The bit position is designated by the
high-order three bits of the Op-Code.
I n s t r u c t i o n : CLB, SEB
Example : Mnemonic
∆CLB∆
∆5,A
Machine code
BB16
Accumulator
bit 5
?
Memory
Bit designation
AAAAA
AAAAA
Op-code(BB16)
1 0 1 1 1 0 1 1
Accumulator
bit 5
0
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INSTRUCTIONS
Accumulator Bit Relative
Addressing mode
Addressing mode : Accumulator Bit Relative
Function : Specifies the address in a memory location where the
next Op-Code is located. The bit position is
designated by the high-order three bits of the Op-Code.
If the branch condition is satisfied, Operand and the
Program Counter are added. The result of this
addition is the address in the memory location.
When the branch condition is not satisfied, the next
instruction is executed.
Instructions : BBC, BBS
Example : Mnemonic
∆BBC∆
∆5,A,∗
∗–12
Machine code
B316 F216
Decimal
When the bit 5 of the
Accumulator is cleared
When the bit 5 of the
Accumulator is set
Accumulator
Accumulator
bit 5
bit 5
0
1
Memory
Memory
AA
AA
A
A
AAAAAA A
AAAAAAAA
A
AA
Address to be
executed next
* –12
Bit designation
Op-code(B316)
Jump
1 0 1 1 0 0 1 1 *
Operand (F216)
* +2
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Bit designation
AAAAA
AAAAA
Op-code(B316)
1 0 1 1 0 0 1 1 *
Operand (F216)
Address to be
executed next
* +2
INSTRUCTIONS
Zero Page Bit Relative
Addressing mode
Addressing mode : Zero Page Bit Relative
Function : Specifies the address of a memory location where the
next Op-Code is located.
The bit position is designated by the high-order three
bits of the Op-Code. The address in the Zero Page
memory location is determined by using Operand I as
low-order byte of the address and 0016 as the highorder byte. If the branch condition is satisfied, Operand Il and the Program Counter are added. The result
of this addition is the address in the memory location.
When the branch condition is not satisfied, the next
instruction is executed.
Instructions : BBC, BBS
Example : Mnemonic
∆BBC∆
∆5,$04,∗
∗–12
Machine language
B716 0416 F116
Decimal
When the bit 5 at address 0416
is cleared, jumps to address *–12.
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
0016
Zero page
bit 5
0
Zero page
designation
FF16
FF16
*–12
Op-code(B716)
Jump
1 0 1 1 0 1 1 1 *
Operand I (0416)
Operand II (F116)
*+3
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0416
1
Bit designation
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0016
bit 5
0416
AA
AA
AAAA
AAAAA
A
AAAAA AAAA
AA
Address to be
executed next
AAAAA
AAAAA
AAAAA
AAAAA
AAAAA
Memory
Memory
Zero page
When the bit 5 at address 0416
is set, goes to address *+3.
Zero page
designation
Bit designation
AAAAA
AAAAA
Op-code(B716)
1 0 1 1 0 1 1 1 *
Operand I (0416)
Operand II (F116)
Address to be
executed next
*+3
INSTRUCTIONS
Instruction Set
3.2 Instruction Set
The 740 Family has 71 types of instructions. The detailed explanation of the instructions is
presented in §3.3. Note that some instructions cannot be used for some products.
3.2.1 Data transfer instructions
These instructions transfer the data between registers, register and memory, and memories.
The following are data transfer instructions.
Instruction
LDA
Load
Store
Transfer
Stack
Operation
LDM
LDX
LDY
STA
STX
STY
TAX
TXA
TAY
TYA
TSX
TXS
PHA
PHP
PLA
PLP
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Function
Load memory value into Accumulator, or memory
where is indicated by Index Register X
Load immediate value into memory
Load memory contents into Index Register X
Load memory contents into Index Register Y
Store Accumulator into memory
Store Index Register X into memory
Store Index Register Y into memory
Transfer Accumulator to the Index Register X
Transfer Index Register X into the Accumulator
Transfer Accumulator into the Index Register Y
Transfer Index Register Y into the Accumulator
Transfer Stack Pointer into the Index Register X
Transfer Index Register X into the Stack Pointer
Push Accumulator onto the Stack
Push Processor Status onto the Stack
Pull Accumulator from the Stack
Pull Processor Status from the Stack
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INSTRUCTIONS
Instruction Set
3.2.2 Operating instruction
The operating instructions include the operations of addition and subtraction, logic,
comparison, rotation, and shift.
The operating instructions are as follows:
Contents
Add memory contents and C flag to Accumulator or memory
ADC
where is indicated by Index Register X
Subtracts memory contents and C flag’s complement from
SBC
Accumulator or memory where is indicated by Index
Addition
Register X
&
Increment Accumulator or memory contents by 1
INC
Subtraction
Decrement Accumulator or memory contents by 1
DEC
Increment Index Register X by 1
INX
Decrement Index Register X by 1
DEX
Increment Index Register Y by 1
INY
Decrement Index Register Y by 1
DEY
MUL(Note) Multiply Accumulator with memory specified by Zero Page
Multiplication
X addressing mode and store high-order byte of result on
&
Stack and low-order byte in Accumulator
Division
DIV(Note) Quotient is stored in Accumulator and one’s complement of
remainder is pushed onto stack
“AND” memory with Accumulator or memory where is
AND
indicated by Index Register X
“OR” memory with Accumulator or memory where is
ORA
indicated by Index Register X
Logical
“Exclusive-OR” memory with Accumulator or memory where
EOR
Operation
is indicated by Index Register X
Store one’s complement of memory contents to memory
COM
“AND” memory with Accumulator (The result is not stored
BIT
into anywhere.)
Test whether memory content is “0” or not
TST
Compare
memory contents and Accumulator or memory
CMP
where is indicated by Index Register X
Comparison
Compare memory contents and Index Register X
CPX
Compare memory contents and Index Register Y
CPY
Shift left one bit (memory contents or Accumulator)
ASL
Shift right one bit (memory contents or Accumulator)
LSR
Shift
Rotate one bit left with carry (memory contents or
ROL
&
Accumulator)
Rotate
Rotate one bit right with carry (memory contents or
ROR
Accumulator)
Rotate four bits right witout carry (memory)
RRF
Note: For some products, multiplication and division instructions cannot be used.
Instructions
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INSTRUCTIONS
Instruction Set
3.2.3 Bit managing instructions
The bit managing instructions clear “0” or set “1” designated bits of the Accumulator or
memory.
Instructions
Bit
Managing
CLB
SEB
Contents
Clear designated bit in the Accumulator or memory
Set designated bit in the Accumulator or memory
3.2.4 Flag setting instructions
The flag setting instructions clear “0” or set “1” C, D, I, T and V flags.
Contents
Instructions
Flag
Setting
CLC
SEC
CLD
SED
CLI
SEI
CLT
SET
CLV
Clear C flag
Set C flag
Clear D flag
Set D flag
Clear I flag
Set I flag
Clear T flag
Set T flag
Clear V flag
C flag : Carry Flag
D flag : Decimal Mode Flag
I flag : Interrupt Disable Flag
T flag : X Modified Operation Mode Flag
V flag : Overflow Flag
3.2.5 Jump, Branch and Return instructions
The jump, branch and return instructions as following are used to change program flow.
Jump
Instructions
JMP
BRA
JSR
BBC
BBS
Branch
Return
BCC
BCS
BNE
BEQ
BPL
BMI
BVC
BVS
RTI
RTS
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Contents
Jump to new location
Jump to new location
Jump to new location saving the current address
Branch when the designated bit in the Accumulator or
memory is “0”
Branch when the designated bit in the Accumulator or
memory is “1”
Branch when the C Flag is “0”
C flag : Carry Flag
Branch when the C Flag is “1”
Branch when the Z Flag is “0”
Z flag : Zero Flag
Branch when the Z Flag is “1”
Branch when the N Flag is “0”
N flag : Negative Flag
Branch when the N Flag is “1”
Branch when the V Flag is “0”
V flag : Overflow Flag
Branch when the V Flag is “1”
Return from interrupt
Return from subroutine
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INSTRUCTIONS
Instruction Set
3.2.6 Interrupt instruction (Break instruction)
This instruction causes a software interrupt.
Instruction
Interrupt
BRK
Contents
Executes a software interrupt.
3.2.7 Special instructions
These special instructions control the oscillation and the internal clock.
Instructions
Special
WIT
STP
Contents
Stops the internal clock.
Stops the oscillation of oscillator.
3.2.8 Other instruction
Instruction
Other
NOP
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Contents
Only advances the program counter.
page 29 of 185
INSTRUCTIONS
Description of instructions
3.3 Description of instructions
This section presents in detail the 740 Family instructions by arranging mnemonics of instructions alphabetically and dividing each instruction essentially into one page.
The heading of each page is a mnemonic. Operation, explanation and changes of status flags
are indicated for each instruction. In addition, assembler coding format, machine code, byte
number, and list of cycle numbers for each addressing mode are indicated.
The following are symbols used in this manual:
Symbol
A
Ai
PC
PCL
Description
Symbol
Description
Accumulator
hh
Address high-order byte data
Bit i of Accumulator
in 0 to 255
Program Counter
ll
Address low-order byte data
Low-order byte of Program
in 0 to 255
Counter
zz
Zero page address data in 0
PCH High-order byte of Program
to 255
Counter
nn
Data in 0 to 255
PS
Processor Status Register
i
Data in 0 to 7
S
Stack Pointer
✽
Contents of the Program
X
Index Register X
Counter
Y
Index Register Y
∆
Tab or space
M
Memory
#
Immediate mode
Mi
Bit i of memory
\
Special page mode
C
Carry Flag
$
Hexadecimal symbol
Z
Zero Flag
+
Addition
I
Interrupt Disable Flag
–
Subtraction
D
Decimal Operation Mode Flag
✕
Multiplication
B
Break Flag
/
Division
T
X Modified Operations Mode
∧
Logical AND
Flag
∨
Logical OR
V
Overflow Flag
∀
Logical exclusive OR
N
Negative Flag
()
Contents of register, memory,
REL Relative address
etc.
BADRS Break address
←
Direction of data transfer
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ADC
ADC
ADD WITH CARRY
Operation : When (T) = 0, (A) ← (A) + (M) + (C)
(T) = 1, (M(X)) ← (M(X)) + (M) + (C)
Function : When T = 0, this instruction adds the contents M, C, and A;
and stores the results in A and C.
When T = 1, this instruction adds the contents of M(X), M and
C; and stores the results in M(X) and C. When T=1, the
contents of A remain unchanged, but the contents of status
flags are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise it is
0.
V : V is 1 when the operation result exceeds +127 or –128;
otherwise it is 0.
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise it is 0.
C : C is 1 when the result of a binary addition exceeds 255 or
when the result of a decimal addition exceeds 99;
otherwise it is 0.
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆ADC∆#$nn
∆ADC∆$zz
∆ADC∆$zz,X
∆ADC∆$hhll
∆ADC∆$hhll,X
∆ADC∆$hhll,Y
∆ADC∆($zz,X)
∆ADC∆($zz),Y
Machine codes
Byte number
Cycle number
6916, nn16
6516, zz16
7516, zz16
6D16, ll16, hh16
7D16, ll16, hh16
7916, ll16, hh16
6116, zz16
7116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Notes 1: When T=1, add 3 to the cycle number.
2: When ADC instruction is executed in decimal operation mode (D = 1),
execute at least one instruction after the ADC instruction before
executing a SEC, CLC, or CLD instruction.
In decimal operation mode, the N, V, Z flags are invalid.
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AND
AND
LOGICAL AND
Operation : When (T) = 0, (A) ← (A) ∧ (M)
(T) = 1, (M(X)) ← (M(X)) ∧ (M)
Function : When T = 0, this instruction transfers the contents of A and M
to the ALU which performs a bit-wise AND operation and stores
the result back in A.
When T = 1, this instruction transfers the contents M(X) and M
to the ALU which performs a bit-wise AND operation and stores
the results back in M(X). When T = 1 the contents of A remain
unchanged, but status flags are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise it is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise it is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆AND∆#$nn
∆AND∆$zz
∆AND∆$zz,X
∆AND∆$hhll
∆AND∆$hhll,X
∆AND∆$hhll,Y
∆AND∆($zz,X)
∆AND∆($zz),Y
Machine codes
Byte number
Cycle number
2916, nn16
2516, zz16
3516, zz16
2D16, ll16, hh16
3D16, ll16, hh16
3916, ll16, hh16
2116, zz16
3116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Note: When T = 1, add 3 to a cycle number.
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ASL
Operation :
ASL
ARITHMETIC SHIFT LEFT
C
←
b7
b0
←
0
Function : This instruction shifts the content of A or M by one bit to the
left, with bit 0 always being set to 0 and bit 7 of A or M always
being contained in C.
Status flag: N : N is 1 when bit 7 of A or M is 1 after the operation;
otherwise it is 0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise it is 0.
C : C is 1 when bit 7 of A or M is 1, before this operation;
otherwise it is 0.
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
Statement
∆ASL∆A
∆ASL∆$zz
∆ASL∆$zz,X
∆ASL∆$hhll
∆ASL∆$hhll,X
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Machine codes
Byte number
Cycle number
0A16
0616, zz16
1616, zz16
0E16, ll16, hh16
1E16, ll16, hh16
1
2
2
3
3
2
5
6
6
7
BBC
BBC
BRANCH ON BIT CLEAR
Operation : When (Mi) or (Ai) = 0, (PC) ← (PC) + n + REL
(Mi) or (Ai) = 1, (PC) ← (PC) + n
n: If addressing mode is Zero Page Bit Relative, n=3. And if
addressing mode is Accumulator Bit Relative, n=2.
Function : This instruction tests the designated bit i of M or A and takes
a branch if the bit is 0. The branch address is specified by a
relative address. If the bit is 1, next instruction is executed.
Status flag : No change
Addressing mode
Statement
Accumulator bit
∆BBC∆i,A,$hhll
Relative
Zero page bit
∆BBC∆i,$zz,$hhll
Relative
Machine codes
Byte number
Cycle number
(20i+13)16, rr16
2
4
(20i+17)16,
zz16, rr16
3
5
Notes 1: rr16=$hhll–(✽+n). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
3: When executing the BBC instruction after the contents of the interrupt
request bit is changed, one instruction or more must be passed
before the BBC instruction is executed.
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BBS
BBS
BRANCH ON BIT SET
Operation : When (Mi) or (Ai) = 1, (PC) ← (PC) + n + REL
(Mi) or (Ai) = 0, (PC) ← (PC) + n
n : If addressing mode is Zero Page Bit Relative, n=3. And if
addressing mode is Accumulator Bit Relative, n=2.
Function : This instruction tests the designated bit i of the M or A and
takes a branch if the bit is 1. The branch address is specified
by a relative address. If the bit is 0, next instruction is executed.
Status flag : No change
Addressing mode
Statement
Accumulator bit
∆BBS∆i,A,$hhll
Relative
Zero page bit
∆BBS∆i,$zz,$hhll
Relative
Machine codes
Byte number
Cycle number
(20i+3)16, rr16
2
4
(20i+7)16,
zz16, rr16
3
5
Notes 1: rr16=$hhll–(✽+n). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
3: When executing the BBS instruction after the contents of the interrupt
request bit is changed, one instruction or more must be passed
before the BBS instruction is executed.
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BCC
BCC
BRANCH ON CARRY CLEAR
Operation : When (C) = 0, (PC) ← (PC) + 2 + REL
(C) = 1, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address if C is
0. The branch address is specified by a relative address. If C
is 1, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BCC∆$hhll
Machine codes
9016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BCS
BCS
BRANCH ON CARRY SET
Operation : When (C) = 1, (PC) ← (PC) + 2 + REL
(C) = 0, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address if C is
1. The branch address is specified by a relative address. If C
is 0, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BCS∆$hhll
Machine codes
B016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BEQ
BEQ
BRANCH ON EQUAL
Operation : When (Z) = 1, (PC) ← (PC) + 2 + REL
(Z) = 0, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address when
Z is 1. The branch address is specified by a relative address.
If Z is 0, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BEQ∆$hhll
Machine codes
F016,rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BIT
TEST BIT IN MEMORY WITH ACCUMULATOR
BIT
Operation : (A) ∧ (M)
Function : This instruction takes a bit-wise logical AND of A and M
contents; however, the contents of A and M are not modified.
The contents of N, V, Z are changed, but the contents of A, M
remain unchanged.
Status flag: N :
V:
T:
B:
I:
D:
Z:
N is 1 when bit 7 of M is 1; otherwise it is 0.
V is 1 when bit 6 of M is 1; otherwise it is 0.
No change
No change
No change
No change
Z is 1 when the result of the operation is 0; otherwise Z is
0.
C : No change
Addressing mode
Zero page
Absolute
Statement
∆BIT∆$zz
∆BIT∆$hhll
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Machine codes
Byte number
Cycle number
2416, zz16
2C16, ll16, hh16
2
3
3
4
BMI
BMI
BRANCH ON RESULT MINUS
Operation : When (N) = 1, (PC) ← (PC) + 2 + REL
(N) = 0, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address when
N is 1. The branch address is specified by a relative address.
If N is 0, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BMI∆$hhll
Machine codes
3016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BNE
BNE
BRANCH ON NOT EQUAL
Operation : When (Z) = 0, (PC) ← (PC) + 2 + REL
(Z) = 1, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address if Z is
0. The branch address is specified by a relative address. If Z
is 1, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BNE∆$hhll
Machine codes
D016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BPL
BPL
BRANCH ON RESULT PLUS
Operation : When (N) = 0, (PC) ← (PC) + 2 + REL
(N) = 1, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address if N is
0. The branch address is specified by a relative address. If N
is 1, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BPL∆$hhll
Machine codes
1016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BRA
BRA
BRANCH ALWAYS
Operation : (PC) ← (PC) + 2 + REL
Function : This instruction branches to the appointed address. The branch
address is specified by a relative address.
Status flag : No change
Addressing mode
Relative
Statement
∆BRA∆$hhll
Machine codes
8016, rr16
Byte number
Cycle number
2
4
Note: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
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BRK
BRK
FORCE BREAK
Operation : (B) ← 1
(PC) ← (PC) + 2
(M(S)) ← (PCH)
(S) ← (S) – 1
(M(S)) ← (PCL)
(S) ← (S) – 1
(M(S)) ← (PS)
(S) ← (S) – 1
(I) ← 1
(PC) ← BADRS (Note 1)
Function : When the BRK instruction is executed, the CPU pushes the
current PC contents onto the stack. The BADRS designated in
the interrupt vector table is stored into the PC.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
1
1
No
No
No
Addressing mode
Implied
change
change
change
change
change
change
Statement
∆BRK∆
Machine codes
0016
Byte number
Cycle number
1
7
Notes 1: “BADRS” means a break address.
2: The value of the PC pushed onto the stack by the execution of the
BRK instruction is the BRK instruction address plus two. Therefore,
the byte following the BRK will not be executed when the value of
the PC is returned from the BRK routine.
3: Both after the BRK instruction is executed and after INT is input, the
program is branched to the address where is specified by the interrupt vector table. By testing the value of the B Flag in the PS
(pushed on the Stack) in the interrupt service routine, the user can
determine if the interrupt was caused by the BRK instruction.
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BVC
BVC
BRANCH ON OVERFLOW CLEAR
Operation : When (V) = 0, (PC) ← (PC) + 2 + REL
(V) = 1, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address if V is
0. The branch address is specified by a relative address. If V
is 1, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BVC∆$hhll
Machine codes
5016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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BVS
BVS
BRANCH ON OVERFLOW SET
Operation : When (V) = 1, (PC) ← (PC) + 2 + REL
(V) = 0, (PC) ← (PC) + 2
Function : This instruction takes a branch to the appointed address when
V is 1. The branch address is specified by a relative address.
When V is 0, the next instruction is executed.
Status flag : No change
Addressing mode
Relative
Statement
∆BVS∆$hhll
Machine codes
7016, rr16
Byte number
Cycle number
2
2
Notes 1: rr16=$hhll–(✽+2). The rr16 is a value in a range of –128 to +127.
2: When a branch is executed, add 2 to the cycle number.
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CLB
CLB
CLEAR BIT
Operation : (Ai) ← 0, or
(Mi) ← 0
Function : This instruction clears the designated bit i of A or M.
Status flag : No change
Addressing mode
Statement
Accumulator bit ∆CLB∆i,A
Zero page bit ∆CLB∆i,$zz
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Machine codes
Byte number
Cycle number
(20i+1B)16
1
2
( 2 0 i + 1 F ) 16,
ZZ16
2
5
CLC
CLC
CLEAR CARRY FLAG
Operation : (C) ← 0
Function : This instruction clears C.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
No
No
No
No
0
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆CLC
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Machine codes
1816
Byte number
Cycle number
1
2
CLD
CLD
CLEAR DECIMAL MODE
Operation : (D) ← 0
Function : This instruction clears D.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
Addressing mode
Implied
No
No
No
No
No
0
No
No
change
change
change
change
change
change
change
Statement
∆CLD
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Machine codes
D816
Byte number
Cycle number
1
2
CLI
CLEAR INTERRUPT DISABLE STATUS
CLI
Operation : (I) ← 0
Function : This instruction clears I.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
No
0
No
No
No
change
change
change
change
change
change
change
Addressing mode
Implied
Statement
∆CLI
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Machine codes
5816
Byte number
Cycle number
1
2
CLT
CLT
CLEAR TRANSFER FLAG
Operation : (T) ← 0
Function : This instruction clears T.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
0
No
No
No
No
No
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆CLT
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Machine codes
1216
Byte number
Cycle number
1
2
CLV
CLV
CLEAR OVERFLOW FLAG
Operation : (V) ← 0
Function : This instruction clears V.
Status flag N :
V:
T:
B:
I:
D:
Z:
C:
No
0
No
No
No
No
No
No
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆CLV
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Machine codes
B816
Byte number
Cycle number
1
2
CMP
CMP
COMPARE
Operation : When (T) = 0, (A) – (M)
(T) = 1, (M(X)) – (M)
Function : When T = 0, this instruction subtracts the contents of M from
the contents of A. The result is not stored and the contents of
A or M are not modified.
When T = 1, the CMP subtracts the contents of M from the
contents of M(X). The result is not stored and the contents of
M(X), M, and A are not modified.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 of the operation result is 1 after the
operation; otherwise N is 0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : C is 1 when the subtracted result is equal to or greater
than 0; otherwise C is 0.
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆CMP∆#$nn
∆CMP∆$zz
∆CMP∆$zz,X
∆CMP∆$hhll
∆CMP∆$hhll,X
∆CMP∆$hhll,Y
∆CMP∆($zz,X)
∆CMP∆($zz),Y
Note: When T=1, add 1 to the cycle number.
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Machine codes
Byte number
Cycle number
C916, nn16
C516, zz16
D516, zz16
CD16, ll16, hh16
DD16, ll16, hh16
D916, ll16, hh16
C116, zz16
D116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
COM
COM
COMPLEMENT
Operation : (M) ← (M)
Function : This instruction takes the one’s complement of the contents of
M and stores the result in M.
Status flag: N : N is 1 when bit 7 of the M is 1 after the operation;
otherwise N is 0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Zero page
Statement
∆COM∆$zz
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Machine codes
4416, zz16
Byte number
Cycle number
2
5
CPX
CPX
COMPARE MEMORY AND INDEX REGISTER X
Operation : (X) – (M)
Function : This instruction subtracts the contents of M from the contents of
X. The result is not stored and the contents of X and M are not
modified.
Status flag: N : N is 1 when bit 7 of the operation result is 1 after the
operation; otherwise N is 0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : C is 1 when the subtracted result is equal to or greater
than 0; otherwise C is 0.
Addressing mode
Immediate
Zero page
Absolute
Statement
∆CPX∆#$nn
∆CPX∆$zz
∆CPX∆$hhll
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Machine codes
Byte number
Cycle number
E016, nn16
E416, zz16
EC16, ll16, hh16
2
2
3
2
3
4
CPY
COMPARE MEMORY AND INDEX REGISTER Y
CPY
Operation : (Y) – (M)
Function : This instruction subtracts the contents of M from the contents of
Y. The result is not stored and the contents of Y and M are not
modified.
Status flag: N : N is 1 when bit 7 of the operation result is 1 after the
operation; otherwise N is 0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : C is 1 when the subtracted result is equal to or greater
than 0; otherwise C is 0.
Addressing mode
Immediate
Zero page
Absolute
Statement
∆CPY∆#$nn
∆CPY∆$zz
∆CPY∆$hhll
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Machine codes
Byte number
Cycle number
C016, nn16
C416, zz16
CC16, ll16, hh16
2
2
3
2
3
4
DEC
DEC
DECREMENT BY ONE
Operation : (A) ← (A) – 1, or
(M) ← (M) – 1
Function : This instruction subtracts 1 from the contents of A or M.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
N is 1 when bit 7 is 1 after the addition; otherwise N is 0.
No change
No change
No change
No change
No change
Z is 1 when the operation result is 0; otherwise Z is 0.
No change
Statement
∆DEC∆A
∆DEC∆$zz
∆DEC∆$zz,X
∆DEC∆$hhll
∆DEC∆$hhll,X
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Machine codes
Byte number
Cycle number
1A16
C616, zz16
D616, zz16
CE16, ll16, hh16
DE16, ll16, hh16
1
2
2
3
3
2
5
6
6
7
DEX
DECREMENT INDEX REGISTER X BY ONE
DEX
Operation : (X) ← (X) – 1
Function : This instruction subtracts one from the current contents of X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆DEX
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Machine codes
CA16
Byte number
Cycle number
1
2
DEY
DECREMENT INDEX REGISTER Y BY ONE
DEY
Operation : (Y) ← (Y) – 1
Function : This instruction subtracts one from the current contents of Y.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆DEY
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Machine codes
8816
Byte number
Cycle number
1
2
DIV
DIV
DIVIDE MEMORY BY ACCUMULATOR
Operation : (A) ← (M(zz+(X)+1),M(zz+(X)) / (A)
M(S) ← one’s complement of Remainder
(S) ← (S) – 1
Function : Divides the 16-bit data in M(zz+(X)) (low-order byte) and
M(zz+(X)+1) (high-order byte) by the contents of A. The
quotient is stored in A and the one’s complement of the
remainder is pushed onto the stack.
dividend low-order
M (zz+(X))
dividend high-order
M (zz+(X)+1)
(A)
divisior
(A)
quotient
Zero page
one's complement of
Remainder
M (S)
Status flag : No change
Addressing mode
Zero page X
Statement
∆DIV∆$zz,X
Machine codes
E216, zz16
Byte number
Cycle number
2
16
Notes 1: The quotient’s overflow and zero division can not be detected. Check the
quotient’s overflow and zero division by software before DIV instruction is
executed. This instruction changes the Stack Pointer and the contents of the
Accumulator.
2: The DIV instruction can not be used for some products.
3: The DIV instruction is not affected by T and D flags.
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EOR
EOR
EXCLUSIVE OR MEMORY WITH ACCUMULATOR
Operation : When (T) = 0, (A) ← (A) ∀ (M)
(T) = 1, (M(X)) ← (M(X)) ∀ (M)
Function : When T = 0, this instruction transfers the contents of the M
and A to the ALU which performs a bit-wise Exclusive OR, and
stores the result in A.
When T = 1, the contents of M(X) and M are transferred to the
ALU, which performs a bit-wise Exclusive OR and stores the
results in M(X). The contents of A remain unchanged, but status flags are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆EOR∆#$nn
∆EOR∆$zz
∆EOR∆$zz,X
∆EOR∆$hhll
∆EOR∆$hhll,X
∆EOR∆$hhll,Y
∆EOR∆($zz,X)
∆EOR∆($zz),Y
Machine codes
Byte number
Cycle number
4916, nn16
4516, zz16
5516, zz16
4D16, ll16, hh16
5D16, ll16, hh16
5916, ll16, hh16
4116, zz16
5116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Note: When T=1, add 3 to the cycle number.
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INC
INC
INCREMENT BY ONE
Operation : (A) ← (A) + 1, or
(M) ← (M) + 1
Function : This instruction adds one to the contents of A or M.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
Statement
∆INC∆A
∆INC∆$zz
∆INC∆$zz,X
∆INC∆$hhll
∆INC∆$hhll,X
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Machine codes
3A16
E616, zz16
F616, zz16
EE16, ll16, hh16
FE16, ll16, hh16
Byte number
Cycle number
1
2
2
3
3
2
5
6
6
7
INX
INCREMENT INDEX REGISTER X BY ONE
INX
Operation : (X) ← (X) + 1
Function : This instruction adds one to the contents of X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆INX
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Machine codes
E816
Byte number
Cycle number
1
2
INY
INCREMENT INDEX REGISTER Y BY ONE
INY
Operation : (Y) ← (Y) + 1
Function : This instruction adds one to the contents of Y.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆INY
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Machine codes
C816
Byte number
Cycle number
1
2
JMP
JMP
JUMP
Operation : When addressing mode is
(a) Absolute, then
(PC) ← hhll
(b) Indirect Absolute, then
(PCL) ← (hhll)
(PCH) ← (hhll+1)
(c) Zero page Indirect Absolute, then
(PCL) ← (zz)
(PCH) ← (zz+1)
Function : This instruction jumps to the address designated by the
following three addressing modes:
Absolute
Indirect Absolute
Zero Page Indirect Absolute
Status flag: No change
Addressing mode
Statement
Absolute
∆JMP∆$hhll
Indirect Absolute ∆JMP∆($hhll)
Zero Page Indirect ∆JMP∆($zz)
Machine codes
4C16,ll16,hh16
6C16,ll16,hh16
B216,zz16
Byte number
Cycle number
3
3
2
3
5
4
Note: The page’s last address (address XXFF16) cannot be specified for the
indirect designation address; in other words, JMP ($XXFF) cannot be
executed.
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JSR
JSR
JUMP TO SUBROUTINE
Operation : (M(S)) ← (PCH)
(S) ← (S) – 1
(M(S)) ← (PCL)
(S) ← (S) – 1
After the above operations, if the addressing mode is
(a) Absolute, then
(PC) ← hhll
(b) Special page, then
(PC L) ← ll
(PCH) ← FF16
(c) Zero page Indirect, then
(PCL) ← (zz)
(PCH) ← (zz+1)
Function : This instruction stores the contents of the PC in the stack, then
jumps to the address designated by the following addressing
modes:
Absolute
Special Page
Zero Page Indirect Absolute
Status flag: No change
Addressing mode
Statement
Absolute
∆JSR∆$hhll
Special page
∆JSR∆\$hhll (Note)
Zero page Indirect ∆JSR∆($zz)
Machine codes
2016, ll16, hh16
2216, ll16
0216, zz16
Byte number Cycle number
3
2
2
6
5
7
(Note) “\” (5C16 of the ASCII code) denotes special page. hh16 must be FF16
in the special page addressing mode.
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LDA
LOAD ACCUMULATOR WITH MEMORY
LDA
Operation : When (T) = 0, (A) ← (M)
(T) = 1, (M(X)) ← (M)
Function : When T = 0, this instruction transfers the contents of M to A.
When T = 1, this instruction transfers the contents of M to
(M(X)). The contents of A remain unchanged, but status flags
are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆LDA∆#$nn
∆LDA∆$zz
∆LDA∆$zz,X
∆LDA∆$hhll
∆LDA∆$hhll,X
∆LDA∆$hhll,Y
∆LDA∆($zz,X)
∆LDA∆($zz),Y
Machine codes
Byte number
Cycle number
A916, nn16
A516, zz16
B516, zz16
AD16, ll16, hh16
BD16, ll16, hh16
B916, ll16, hh16
A116, zz16
B116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Note: When T = 1, add 2 to the cycle number.
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LDM
LOAD IMMEDIATE DATA TO MEMORY
LDM
Operation : (M) ← nn
Function : This instruction loads the immediate value in M.
Status flag : No change
Addressing mode
Zero page
Statement
∆LDM∆#$nn,$zz
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Machine codes
Byte number
Cycle number
3C16, nn16, zz16
3
4
LDX
LOAD INDEX REGISTER X FROM MEMORY
LDX
Operation : (X) ← (M)
Function : This instruction loads the contents of M in X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page Y
Absolute
Absolute Y
Statement
∆LDX∆#$nn
∆LDX∆$zz
∆LDX∆$zz,Y
∆LDX∆$hhll
∆LDX∆$hhll,Y
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Machine codes
Byte number
Cycle number
A216, nn16
A616, zz16
B616, zz16
AE16, ll16, hh16
BE16, ll16, hh16
2
2
2
3
3
2
3
4
4
5
LDY
LOAD INDEX REGISTER Y FROM MEMORY
LDY
Operation : (Y) ← (M)
Function : This instruction loads the contents of M in Y.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Statement
∆LDY∆#$nn
∆LDY∆$zz
∆LDY∆$zz,X
∆LDY∆$hhll
∆LDY∆$hhll,X
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Machine codes
Byte number
Cycle number
A016, nn16
A416, zz16
B416, zz16
AC16, ll16, hh16
BC16, ll16, hh16
2
2
2
3
3
2
3
4
4
5
LSR
Operation :
LSR
LOGICAL SHIFT RIGHT
0
→
b7
b0
→
C
Function : This instruction shifts either A or M one bit to the right such
that bit 7 of the result always is set to 0, and the bit 0 is
stored in C.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
0
No change
No change
No change
No change
No change
Z is 1 when the operation result is 0; otherwise Z is 0.
C is 1 when the bit 0 of either the A or the M before the
operation is 1; otherwise C is 0.
Statement
∆LSR∆A
∆LSR∆$zz
∆LSR∆$zz,X
∆LSR∆$hhll
∆LSR∆$hhll,X
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Machine codes
Byte number
Cycle number
4A16
4616, zz16
5616, zz16
4E16, ll16, hh16
5E16, ll16, hh16
1
2
2
3
3
2
5
6
6
7
MUL
MULTIPLY ACCUMULATOR AND MEMORY
MUL
Operation : M(S) • (A) ← (A) ✕ M(zz+(X))
(S) ← (S) – 1
Function : Multiplies Accumulator with the memory specified by the Zero
Page X addressing mode and stores the high-order byte of the
result on the Stack and the low-order byte in A.
multiplicant
product
Zero page
M(zz+(X))
(A)
multiplier
M(S)
(A)
high-order
low-order
Status flag : No change
Statement
Addressing mode
Zero page X
∆MUL∆$zz,X
Machine codes
6216, zz16
Byte number
Cycle number
2
15
Notes 1: This instruction changes the contents of S and A.
2: The MUL instruction cannot be used for some products.
3: The MUL instruction is not affected by T and D flags.
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NOP
NOP
NO OPERATION
Operation : (PC) ← (PC) + 1
Function : This instruction adds one to the PC but does no other
operation.
Status flag : No change
Addressing mode
Implied
Statement
∆NOP
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Machine codes
EA16
Byte number
Cycle Number
1
2
ORA
ORA
OR MEMORY WITH ACCUMULATOR
Operation : When (T) = 0, (A) ← (A) ∨ (M)
(T) = 1, (M(X)) ← (M(X)) ∨ (M)
Function : When T = 0, this instruction transfers the contents of A and M
to the ALU which performs a bit-wise “OR”, and stores the
result in A.
When T = 1, this instruction transfers the contents of M(X) and
the M to the ALU which performs a bit-wise OR, and stores the
result in M(X). The contents of A remain unchanged, but status
flags are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is “1” when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the execution result is 0; otherwise Z is 0.
C : No change
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆ORA∆#$nn
∆ORA∆$zz
∆ORA∆$zz,X
∆ORA∆$hhll
∆ORA∆$hhll,X
∆ORA∆$hhll,Y
∆ORA∆($zz,X)
∆ORA∆($zz),Y
Machine codes
Byte number
Cycle number
0916, nn16
0516, zz16
1516, zz16
0D16, ll16, hh16
1D16, ll16, hh16
1916, ll16, hh16
0116, zz16
1116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Note: When T=1, add 3 to the cycle number.
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PHA
PHA
PUSH ACCUMULATOR ON STACK
Operation : (M(S)) ← (A)
(S) ← (S) – 1
Function : This instruction pushes the contents of A to the memory
location designated by S, and decrements the contents of S by
one.
Status flag : No change
Addressing mode
Implied
Statement
∆PHA
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Machine codes
4816
Byte number
Cycle number
1
3
PHP
PUSH PROCESSOR STATUS ON STACK
PHP
Operation : (M(S)) ← (PS)
(S) ← (S) – 1
Function : This instruction pushes the contents of PS to the memory location designated by S and decrements the contents of S by one.
Status flag: No change
Addressing mode
Implied
Statement
∆PHP
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Machine codes
0816
Byte number Cycle number
1
3
PLA
PULL ACCUMULATOR FROM STACK
PLA
Operation : (S) ← (S) + 1
(A) ← (M(S))
Function : This instruction increments S by one and stores the contents of
the memory designated by S in A.
Status flag: N : N is 1 when bit 7 is 1 after the operation ; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆PLA
Machine codes
6816
Byte number
Cycle number
1
4
Note: A NOP instruction should be executed after every PLP instruction.
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PLP
PULL PROCESSOR STATUS FROM STACK
PLP
Operation : (S) ← (S) + 1
(PS) ← (M(S))
Function : This instruction increments S by one and stores the contents of
the memory location designated by S in PS.
Status flag : Value returns to the original one that was pushed in the stack.
Addressing mode
Implied
Statement
∆PLP
Machine codes
2816
Byte number
Cycle number
1
4
Note: A NOP instruction should be executed after every PLP instruction.
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ROL
ROL
ROTATE ONE BIT LEFT
Operation :
b7
b0
C
Function : This instruction shifts either A or M one bit left through C. C is
stored in bit 0 and bit 7 is stored in C.
Status flag: N : N is 1 when bit 6 is 1 before the operation; otherwise N is
0.
V: No change
T: No change
B: No change
I: No change
D: No change
Z: Z is 1 when the operation result is 0; otherwise Z is 0.
C: C is 1 when bit 7 is 1 before the operation; otherwise C is
0.
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
Statement
∆ROL∆A
∆ROL∆$zz
∆ROL∆$zz,X
∆ROL∆$hhll
∆ROL∆$hhll,X
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Machine codes
Byte number
Cycle number
2A16
2616, zz16
3616, zz16
2E16, ll16, hh16
3E16, ll16, hh16
1
2
2
3
3
2
5
6
6
7
ROR
ROR
ROTATE ONE BIT RIGHT
Operation :
C
b7
b0
Function : This instruction shifts either A or M one bit right through C. C
is stored in bit 7 and bit 0 is stored in C.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
Addressing mode
Accumulator
Zero page
Zero page X
Absolute
Absolute X
N is 1 when C is 1 before the operation; otherwise N is 0.
No change
No change
No change
No change
No change
Z is 1 when the operation result is 0; otherwise Z is 0.
C is 1 when bit 0 is 1 before the operation; otherwise C is
0.
Statement
∆ROR∆A
∆ROR∆$zz
∆ROR∆$zz,X
∆ROR∆$hhll
∆ROR∆$hhll,X
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Machine codes
Byte number
Cycle number
6A16
6616, zz16
7616, zz16
6E16, ll16, hh16
7E16, ll16, hh16
1
2
2
3
3
2
5
6
6
7
RRF
RRF
ROTATE RIGHT OF FOUR BITS
Operation :
b7
b4
b3
b0
Function : This instruction rotates 4 bits of the M content to the right.
Status flag : No change
Addressing mode
Zero page
Statement
∆RRF∆$zz
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Machine codes
8216, zz16
Byte number
Cycle number
2
8
RTI
RTI
RETURN FROM INTERRUPT
Operation : (S) ← (S) + 1
(PS) ← (M(S))
(S) ← (S) + 1
(PCL) ← (M(S))
(S) ← (S) + 1
(PCH) ← (M(S))
Function : This instruction increments S by one, and stores the contents
of the memory location designated by S in PS. S is again
incremented by one and stores the contents of the memory
location designated by S in PCL. S is again incremented by
one and stores the contents of memory location designated by
S in PC H.
Status flag : Value returns to the original one that was pushed in the stack.
Addressing mode
Implied
Statement
∆RTI
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Machine codes
4016
Byte number Cycle number
1
6
RT S
RT S
RETURN FROM SUBROUTINE
Operation : (S) ← (S) + 1
(PCL) ← (M(S))
(S) ← (S) + 1
(PCH) ← (M(S))
(PC) ← (PC) + 1
Function : This instruction increments S by one and stores the contents of
the memory location designated by S in PC L . S is again
incremented by one and the contents of the memory location is
stored in PCH. PC is incremented by 1.
Status flag: No change
Addressing mode
Implied
Statement
∆RTS
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Machine codes
6016
Byte number
Cycle number
1
6
SBC
SBC
SUBTRACT WITH CARRY
Operation : When (T) = 0, (A) ← (A) – (M) – (C)
(T) = 1, (M(X)) ← (M(X)) – (M) – (C)
Function : When T = 0, this instruction subtracts the value of M and the
complement of C from A, and stores the results in A and C.
When T = 1, the instruction subtracts the contents of M and
the complement of C from the contents of M(X), and stores the
results in M(X) and C.
A remain unchanged, but status flag are changed.
M(X) represents the contents of memory where is indicated by
X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : V is 1 when the operation result exceeds +127 or –128;
otherwise V is 0.
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : C is 1 when the subtracted result is equal to or greater
than 0; otherwise C is 0.
Addressing mode
Immediate
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X)
(Indirect Y)
Statement
∆SBC∆#$nn
∆SBC∆$zz
∆SBC∆$zz,X
∆SBC∆$hhll
∆SBC∆$hhll,X
∆SBC∆$hhll,Y
∆SBC∆($zz,X)
∆SBC∆($zz),Y
Machine codes
Byte number
Cycle number
E916, nn16
E516, zz16
F516, zz16
ED16, ll16, hh16
FD16, ll16, hh16
F916, ll16, hh16
E116, zz16
F116, zz16
2
2
2
3
3
3
2
2
2
3
4
4
5
5
6
6
Notes 1: When T=1, add 3 to the cycle number.
2: When SBC instruction is executed in decimal operation mode
(D = 1), execute at least one instruction after the SBC instruction
before executing a SEC, CLC, or CLD instruction.
In decimal operation mode, the N, V, Z flags are invalid.
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SEB
SEB
SET BIT
Operation : (Ai) ← 1, or
(Mi) ← 1
Function : This instruction sets the designated bit i of A or M.
Status flag: No change
Addressing mode
Statement
Accumulator bit ∆SEB∆i,A
Zero page bit ∆SEB∆i,$zz
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Machine codes
Byte number
Cycle number
(20i+B)16
(20i+F)16, zz16
1
2
2
5
SEC
SEC
SET CARRY FLAG
Operation : (C) ← 1
Function : This instruction sets C.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
No
No
No
No
1
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆SEC
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Machine code
3816
Byte number
Cycle number
1
2
SED
SED
SET DECIMAL MODE
Operation : (D) ← 1
Function : This instruction set D.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
No
No
1
No
No
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆SED
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Machine codes
F816
Byte number
Cycle number
1
2
SEI
SEI
SET INTERRUPT DISABLE FLAG
Operation : (I) ← 1
Function : This instruction sets I.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
No
No
1
No
No
No
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆SEI
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Machine codes
7816
Byte number
Cycle number
1
2
SET
SET
SET TRANSFER FLAG
Operation : (T) ← 1
Function : This instruction sets T.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
No
No
1
No
No
No
No
No
Addressing mode
Implied
change
change
change
change
change
change
change
Statement
∆SET
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Machine codes
3216
Byte number
Cycle number
1
2
STA
STORE ACCUMULATOR IN MEMORY
STA
Operation : (M) ← (A)
Function : This instruction stores the contents of A in M.
The contents of A does not change.
Status flag: No change
Addressing mode
Zero page
Zero page X
Absolute
Absolute X
Absolute Y
(Indirect X )
(Indirect Y)
Statement
∆STA∆$zz
∆STA∆$zz,X
∆STA∆$hhll
∆STA∆$hhll,X
∆STA∆$hhll,Y
∆STA∆($zz,X)
∆STA∆($zz),Y
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Machine codes
Byte number
Cycle number
8516, zz16
9516, zz16
8D16, ll16, hh16
9D16, ll16, hh16
9916, ll16, hh16
8116, zz16
9116, zz16
2
2
3
3
3
2
2
4
5
5
6
6
7
7
STP
STP
STOP
Operation : CPU ← Stand-by state (Oscillation stopped)
Function : This instruction resets the oscillation control F/F and the oscillation stops. Reset or interrupt input is needed to wake up from
this mode.
Status flag: No change
Addressing mode
Implied
Statement
∆STP
Machine codes
4216
Byte number
Cycle number
1
2
Note: If the STP instruction is disabled the cycle number will be 2 (same in
operation as NOP). However, disabling this instruction is an optional
feature; therefore, consult the specifications for the particular chip in
question.
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STX
STORE INDEX REGISTER X IN MEMORY
STX
Operation : (M) ← (X)
Function : This instruction stores the contents of X in M. The contents of
X does not change.
Status flag: No change
Statement
Addressing mode
Zero page
Zero page Y
Absolute
∆STX∆$zz
∆STX∆$zz,Y
∆STX∆$hhll
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Machine codes
Byte number
Cycle number
8616, zz16
9616, zz16
8E16, ll16, hh16
2
2
3
4
5
5
STY
STORE INDEX REGISTER Y IN MEMORY
STY
Operation : (M) ← (Y)
Function : This instruction stores the contents of Y in M.
The contents of Y does not change.
Status flag: No change
Addressing mode
Zero page
Zero page X
Absolute
Statement
∆STY∆$zz
∆STY∆$zz,X
∆STY∆$hhll
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Machine codes
Byte number
Cycle number
8416, zz16
9416, zz16
8C16, ll16, hh16
2
2
3
4
5
5
TAX
TAX
TRANSFER ACCUMULATOR TO INDEX REGISTER X
Operation : (X) ← (A)
Function : This instruction stores the contents of A in X. The contents of
A does not change.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆TAX
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Machine codes
AA16
Byte number
Cycle number
1
2
TAY
TAY
TRANSFER ACCUMULATOR TO INDEX REGISTER Y
Operation : (Y) ← (A)
Function : This instruction stores the contents of A in Y. The contents of
A does not change.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆TAY
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Machine codes
A816
Byte number Cycle number
1
2
TST
TST
TEST FOR NEGATIVE OR ZERO
Operation : (M) = 0 ?
Function : This instruction tests whether the contents of M are “0” or not
and modifies the N and Z.
Status flag: N :
V:
T:
B:
I:
D:
Z:
C:
Statement
Addressing mode
Zero page
N is 1 when bit 7 of M is 1; otherwise N is 0.
No change
No change
No change
No change
No change
Z is 1 when the M content is 0; otherwise Z is 0.
No change
∆TST∆$zz
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Machine codes
6416, zz16
Byte number
Cycle number
2
3
TSX
TSX
TRANSFER STACK POINTER TO INDEX REGISTER X
Operation : (X) ← (S)
Function : This instruction transfers the contents of S in X.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V : No change
T : No change
B : No change
I : No change
D : No change
Z : Z is 1 when the operation result is 0; otherwise Z is 0.
C : No change
Addressing mode
Implied
Statement
∆TSX
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Machine codes
BA16
Byte number
Cycle number
1
2
TXA
TXA
TRANSFER INDEX REGISTER X TO ACCUMULATOR
Operation : (A) ← (X)
Function : This instruction stores the contents of X in A.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N is
0.
V: No change
T: No change
B: No change
I: No change
D: No change
Z: Z is 1 when the operation result is 0; otherwise Z is 0.
C: No change
Addressing mode
Implied
Statement
∆TXA
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Machine codes
8A16
Byte number
Cycle number
1
2
TXS
TXS
TRANSFER INDEX REGISTER X TO STACK POINTER
Operation : (S) ← (X)
Function : This instruction stores the contents of X in S.
Status flag No change
Addressing mode
Implied
Statement
∆TXS
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Machine codes
9A16
Byte number
Cycle number
1
2
TYA
TYA
TRANSFER INDEX REGISTER Y TO ACCUMULATOR
Operation : (A) ← (Y)
Function : This instruction stores the contents of Y in A.
Status flag: N : N is 1 when bit 7 is 1 after the operation; otherwise N
is 0.
V: No change
T: No change
B: No change
I: No change
D: No change
Z: Z is 1 when the operation result is 0; otherwise Z is 0.
C: No change
Addressing mode
Implied
Statement
∆TYA
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Machine codes
9816
Byte number
Cycle number
1
2
WIT
WIT
WAIT
Operation : CPU ← Wait state
Function : The WIT instruction stops the internal clock but the
oscillation of the oscillation circuit is not stopped. Reset or
interrupt input is needed to wake up from this mode.
Status flag : No change
Statement
Addressing mode
Implied
∆WIT
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Machine codes
C216
Byte number
Cycle number
1
2
INSTRUCTIONS
Instructions Related to Interrupt Processing and Subroutine Processing
3.4 Instructions Related to Interrupt Handling and Subroutine Processing
3.4.1 Instructions Related to Interrupt Handling
When an interrupt is accepted, the contents of the processor status register are pushed onto
the memory location indicated by the stack pointer. There is therefore no need to execute the
PHP instruction.
If it is necessary to save the contents of the accumulator, the PHA instruction should be
executed within an interrupt routine (before any instruction that manipulates the accumulator).
Whenever a stack operation instruction such as PHA is executed within an interrupt routine,
make sure that instructions such as PLA that affect the stack operation instruction are also
executed within the same interrupt routine.
Execute the RTI instruction to return from the interrupt routine.
3.4.2 Instructions Related to Interrupt Control
The factors that control an interrupt are the interrupt disable flag (I) as well as the interrupt
enable bit and request bit corresponding to the interrupt source. (This does not apply to
software interrupts triggered by the BRK instruction.)
(1) Disabling Interrupts
An interrupt may be disabled by setting the interrupt disable flag (I) to “1” using the SEI
instruction or by using an instruction such as LDM or CLB (a variety of other instructions
can be used as well) to clear the interrupt enable bit to “0”.
(2) Enabling Interrupts
An interrupt may be enabled by setting the interrupt enable bit to “1” using an instruction
such as LDM or SEB, and by using the CLI instruction to clear the interrupt disable flag
(I) to “0”.
(3) Clearing Interrupt Requests
When an interrupt is generated, the interrupt request bit corresponding to the interrupt
source is set to “1” automatically. The interrupt request bit is cleared to “0” when the
interrupt is accepted. Therefore, there is no need to clear the interrupt request bit (within
an interrupt routine) by means of a user program.
If interrupt generation occurs while an interrupt is disabled, the interrupt request bit is set
to “1”. If, under this condition, the interrupt is subsequently enabled (the interrupt disable
flag (I) is cleared to “0” and the interrupt enable bit is set to “1”), the interrupt is
accepted. To prevent an interrupt from being accepted in such a case, use an instruction
such as LDM or CLB to clear the interrupt request bit to “0” before enabling the interrupt.
In such cases, the following point should be considered.
●While the interrupt disable flag (I) is “0”, if the interrupt request bit is cleared to “0” and
the interrupt enable bit is cleared to “0” at the same time using an instruction such as
LDM, the interrupt will actually be enabled before the request bit is cleared to “0”, causing
the interrupt to be accepted.
To prevent this, use an instruction such as CLB to clear the request bit to “0” first, then
enable the interrupt.
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INSTRUCTIONS
Instructions Related to Interrupt Processing and Subroutine Processing
(4) Interrupt Control within Interrupt Routines
After an interrupt is accepted and execution of the interrupt routine begins, the interrupt
disable flag (I) is set to “1” automatically to prevent multiple interrupts. To enable multiple
interrupts, use the CLI instruction within the interrupt routine to clear the interrupt disable
flag (I) to “0”.
3.4.3 Instructions Related to Subroutine Processing
Normally, the JSR instruction is used to jump to a subroutine. When this instruction is
executed, the current program counter values, first PCH then PCL, are pushed onto the stack
automatically and the stack pointer is moved accordingly. However, in contrast to interrupt
handling, the contents of the processor status register are not saved automatically when a
subroutine is called. If it is necessary to save the contents of the processor status register,
execute the PHP instruction. Executing the JSR instruction does not alter the content of the
processor status register. Therefore, saving the contents of the processor status register using
the PHP instruction may be performed either immediately before the JSR instruction or
immediately after it (at the beginning of the subroutine). However, if such a stack operation
instruction is executed within a subroutine, do not fail to perform the opposite operation
before returning from (that is, within) the subroutine.
Execute the RTS instruction to return from a subroutine. When this instruction is executed,
the return address saved by the JSR instruction is returned to the program counter
automatically. Likewise in contrast to interrupt handling, the contents of the processor status
register are not restored. If the PHP or PHA instruction is used within a subroutine to store
the contents of the processor status register or accumulator, do not fail to perform the
opposite stack operation, using the PLP or PLA instruction, before returning from (that is,
within) the subroutine.
Figure 3.4.1 shows pushing and pulling values onto and from the stack during interrupt
handling and subroutine processing. Table 3.4.1 shows instructions for storing and retrieving
values in the accumulator and processor status register.
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INSTRUCTIONS
Instructions Related to Interrupt Processing and Subroutine Processing
Currently running routine
Interrupt request →
(Note)
M(S) ← (PC H)
Push return address
onto stack
(S) ← (S) – 1
Execute JSR instruction
M(S) ← (PC L)
Push return address
onto stack
M(S) ← (PC H)
(S) ← (S) – 1
(S) ← (S) – 1
M(S) ← (PS)
M(S) ← (PC L)
(S) ← (S) – 1
(S) ← (S) – 1
Interrupt S. R.
.... .
.... .
I flag “0” → “1”
Fetch interrupt jump
destination address
Subroutine
Execute RTI instruction
Execute RTS instruction
Pull return address
from stack
Push contents of
processor status register
onto location indicated by
stack pointer
(S) ← (S) + 1
(PC L) ← M(S)
(S) ← (S) + 1
(PC H) ← M(S)
(S) ← (S) + 1
(PS) ← M(S)
Pull contents of processor
status register from location
indicated by stack pointer
(S) ← (S) + 1
(PC L) ← M(S)
Pull return address
from stack
(S) ← (S) + 1
(PC H) ← M(S)
Note: Conditions under which interrupt is accepted at this point: Interrupt enable flag set to “1”
Interrupt disable flag set to “0”
Fig.3.4.1 Pushing and pulling values onto and from the stack
Table 3.4.1 Instructions for storing and retrieving values in the accumulator or processor status register
Instruction to push onto Stack
Instruction to pull from Stack
Accumulator
PHA
PLA
Processor status register
PHP
PLP
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NOTES ON USE
4. NOTES ON USE
The information below applies to the entire 740 Family. Please refer to it in conjunction with
the usage notes of each specific product model.
4.1 Notes on input and output ports
4.1.1 Notes in standby state
In standby state✽1, do not make pin levels “undefined” when I/O ports are set to input mode.
In addition, the same note is necessary even when N-channel open-drain I/O ports are set
to output mode.
Pull-up (connect the port to VCC) or pull-down (connect the port to VSS) these ports through
a resistor.
When determining a resistance value, note the following points:
• External circuit
• Variation of output levels during the ordinary operation
●Reason
An transistor becomes an OFF state when an I/O port is set as input mode by the direction
register, so that the port enter a high-impedance state. At this time, the potential which
is input to the input buffer in a microcomputer is unstable in the state that input levels are
“undefined”. This may cause power source current. Even when an I/O port of N-channel
open-drain is set as output mode by the direction register, if the contents of the port latch
is “1”, the same phenomenon as that of an input port will occur.
✽1 standby state: Stop mode by executing STP instruction
Wait mode by executing WIT instruction
4.1.2 Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing instruction ✽2, the value
of the unspecified bit may be changed.
●Reason
I/O ports are set to input or output mode in bit units. Reading from a port register or writing
to it involves the following operations.
• Port in input mode
Read: Read the pin level.
Write: Write to the port latch.
• Port in output mode
Read: Read the port latch or read the output from the peripheral function (specifications
differ depending on the port).
Write: Write to the port latch. (The port latch value is output from the pin.)
Since bit managing instructions✽1 are read-modify-write instructions, ✽2 using such an instruction
on a port register causes a read and write to be performed simultaneously on the bits
other than the one specified by the instruction.
When an unspecified bit is in input mode, its pin level is read and that value is written to
the port latch. If the previous value of the port latch differs from the pin level, the port latch
value is changed.
If an unspecified bit is in output mode, the port latch is generally read. However, for some
ports the peripheral function output is read, and the value is written to the port latch. In
this case, if the previous value of the port latch differs from the peripheral function output,
the port latch value is changed.
✽1. Bit managing instructions: SEB and CLB instructions
✽2. Read-modify-write instructions: Instructions that read memory in byte units, modify the
value, and then write the result to the same location in memory in byte units
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NOTES ON USE
4.2 Termination of unused pins
At the termination of unused pins, perform wiring at the shortest possible distance (20 mm
or less) from microcomputer pins. With regard to an effects on the system, thoroughly perform
system evaluation on the user side.
4.2.1 Appropriate termination of unused pins
➀ Output-only pins:
Open.
➁ Input-only pins:
Connect each pin via a 1 kΩ to 10 kΩ resistor (reference value) to V CC or VSS. If the port
allows selection of an on-chip pull-up or pull-down resistor, the on-chip pull-up or pulldown resistor may be used.
In addition, pins (CNV SS and INT pins, etc.) for which the operating mode is affected by
the voltage level, select V CC or V SS after checking the mode.
➂ I/O ports:
Set the I/O ports for the input mode and connect them to V CC or VSS through each resistor
of 1 kΩ to 10 kΩ (reference value).
Ports that permit the selecting of a built-in pull-up/pull-down resistor can also use this
resistor. Set the I/O ports for the output mode and open them at “L” or “H”.
• When opening them in the output mode, the input mode of the initial status remains until
the mode of the ports is switched over to the output mode by the program after reset.
Thus, the potential at these pins is undefined and the power source current may increase
in the input mode. With regard to an effects on the system, thoroughly perform system
evaluation on the user side.
• Since the direction register setup may be changed because of a program runaway or
noise, set direction registers by program periodically to increase the reliability of program.
➃ The AVss pin when not using the A/D converter:
When not using the A/D converter, handle a power source pin for the A/D converter, AV SS
and AV CC pins as follows:
• AV SS: Connect to the V SS pin.
• AV CC: Connect to the V CC pin.
4.2.2 Termination remarks
➀ I/O ports:
Do not open in the input mode.
●Reason
• The power source current may increase depending on the first-stage circuit.
• An effect due to noise may be easily produced as compared with proper termination ➀
and shown on the above.
➁ I/O ports:
When setting for the input mode, do not connect to V CC or V SS directly.
●Reason
If the direction register setup changes for the output mode because of a program runaway
or noise, a short circuit may occur between a port and V CC (or V SS).
➂ I/O ports:
When setting for the input mode, do not connect multiple ports in a lump to V CC or V SS
through a resistor.
●Reason
If the direction register setup changes for the output mode because of a program runaway
or noise, a short circuit may occur between ports.
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NOTES ON USE
4.3 Notes on interrupts
4.3.1 Setting for interrupt request bit and interrupt enable bit
To set an interrupt request bit and an interrupt enable bit for interrupts, execute as the
following sequence:
➀ Clear an interrupt request bit to “0” (no interrupt request issued).
➁ Set an interrupt enable bit to “1” (interrupts enabled).
●Reason
If the above setting are performed simultaneously with one instruction, an unnecessary
interrupt processing routine is executed. Because an interrupt enable bit is set to “1”
(interrupts enabled) before an interrupt request bit is cleared to “0.”
4.3.2 Switching of detection edge
If it is not necessary to generate interrupts synchronized with certain settings, such as
setting the active edge for external interrupts or switching the interrupt source for a vector
in cases where multiple interrupt sources are assigned to the same interrupt vector, use
the following procedure to make the settings.
Clear an interrupt enable bit to “0” (interrupt disabled)
Set the interrupt edge selection bit (active edge switch
bit) or the interrupt (source) selection bit
NOP instruction (one or more instructions)
Clear an interrupt request bit to “0” (no interrupt request
issued)
Set the interrupt enable bit to “1” (interrupt enabled)
Fig. 4.3.1 Switching sequence of detection edge
●Reason
The interrupt request bit may be set to “1” in the following cases:
• When switching the active edge for external interrupts.
• When switching the interrupt source for a vector in cases where multiple interrupt sources
are assigned to the same interrupt vector.
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NOTES ON USE
4.3.3 Distinction of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request (request distinguish) bit
of an interrupt request register (interrupt request distinguish register) immediately after this
bit is set to “0”, execute one or more instructions before executing the BBC or BBS instruction.
Clear an interrupt request (request distinguish) bit to “0”
(no interrupt request issued)
NOP instruction (one or more instructions)
Execute the BBC or BBS instruction
Fig. 4.3.2 Distinction sequence of interrupt request bit
●Reason
If the BBC or BBS instruction is executed immediately after an interrupt request (request
distinguish) bit of an interrupt request register (interrupt request distinguish register) is
cleared to “0,” the value of the interrupt request (request distinguish) bit before being cleared
to “0” is read.
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page 108 of 185
NOTES ON USE
4.4 Notes on programming
4.4.1 Processor Status Register
(1) Initialization of Processor Status Register
Flags which affect program execution must be initialized after a reset. In particular, it is essential
to initialize the T and D flags because they have an important effect on calculations.
●Reason
After a reset, the contents of processor status register (PS) are undefined except for the I flag
which is “1.”
Reset
Flags initializing
Main program
Fig. 4.4.1 Initialization of flags in Processor Status Register
(2) How to reference Processor Status Register
To reference the contents of the processor status register (PS), execute the PHP instruction
once then read the contents of (S + 1). If necessary, execute the PLP instruction to
return the PS to its original status.
A NOP instruction should be executed after every PLP instruction.
PLP instruction
(S)
NOP instruction
(S) + 1
Saved PS
Fig. 4.4.2 PLP instruction execution sequence
Fig. 4.4.3 Stack memory contents after PHP
instruction execution
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REJ09B0322-0200
page 109 of 185
NOTES ON USE
4.4.2 BRK instruction
(1) Method detecting interrupt source
It can be detected that the BRK instruction interrupt event or the least priority interrupt
event by referring the stored B flag state. Refer the stored B flag state in the interrupt
routine, in this case.
(S)
7
(S) + 1
4
1
0
= B flag
(S) + 2
PCL (program counter low-order)
(S) + 3
PCH (program counter high-order)
PS
Fig. 4.4.4 Contents of stack memory in interrupt processing routine
(2) Interrupt priority level
At the following status,
➀ the interrupt request bit has set to “1.”
➁ the interrupt enable bit has set to “1.”
➂ the interrupt disable flag (I) has set to “1.”
If the BRK instruction is executed, the interrupt disable state is cancelled and it becomes
in the interrupt enable state. So that the requested interrupts (the interrupts that corresponding
to their request bits have set to “1”) are accepted.
4.4.3 Decimal calculations
(1) Execution of Decimal calculations
The ADC and SBC are the only instructions which will yield proper decimal results in
decimal mode. To calculate in decimal notation, set the decimal mode flag (D) to “1” with
the SED instruction. After executing the ADC or SBC instruction, execute another instruction
before executing the SEC, CLC, or CLD instruction.
Rev.2.00 Nov 14, 2006
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page 110 of 185
NOTES ON USE
(2) Status flags in decimal mode
When decimal mode is selected (D = 1), the values of three of the flags in the status
register (the flags N, V, and Z) are invalid after a ADC or SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the calculation, or
is cleared to “0” if a borrow is generated. To determine whether a calculation has
generated a carry, the C flag must be initialized to “0” before each calculation. To check
for a borrow, the C flag must be initialized to “1” before each calculation.
Set D flag to “1”
ADC or SBC instruction
NOP instruction
SEC, CLC, or CLD instruction
Fig. 4.4.5 Status flags in decimal mode
4.4.4 JMP instruction
When using the JMP instruction in indirect addressing mode, do not specify the last address
on a page as an indirect address.
4.4.5 Multiplication and division instructions
The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
The execution of these instructions does not change the contents of the processor status
register.
4.4.6 Ports
The contents of the port direction registers cannot be read.
The following cannot be used:
• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction register as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register
Use instructions such as LDM and STA, etc., to set the port direction registers.
4.4.7 Instruction execution time
The instruction execution time is obtained by multiplying the frequency of the internal clock
φ by the number of cycles needed to execute an instruction.
The number of cycles required to execute an instruction is shown in the list of machine
instructions.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 111 of 185
APPENDIX 1
Instruction Cycles in each Addressing Mode
APPENDIX 1. Instruction Cycles in each Addressing Mode
Clock φ controls the system timing of 740 Family. The SYNC signal and the value of PC
(Program Counter) are output in every instruction fetch cycle. The Op-Code is fetched during
the next half-period of φ . The instruction decoder of CPU decodes this Op-Code and
determines the following how to execute the instruction. The instruction timings of all addressing modes are described on the following pages.
The φ, SYNC, R/W (RD, WR), ADDR (ADDRL, ADDRH), and DATA signals in these figures
indicate the status of the internal bus. These signals cannot be seen directly in single-chip
mode, but they can be checked on products that support use of microprocessor mode.
The combination of these signals differs according to the microcomputer’s type. The following
table lists the valid signal for each product.
Valid signal for each product
φ
Type
SYNC
M507XX
M509XX
M374XX
(Except M37451)
M38XXX
M375XX
M372XX
M371XX
M37451
R/W
M50734
Note: Only 80-pin version.
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REJ09B0322-0200
page 112 of 185
RD
WR
(Note)
(Note)
ADDR DATA ADDRH ADDRL/DATA
IMPLIED
Byte length
Cycle number
: ∆CLC
∆CLD
∆CLI
∆CLT
∆CLV
∆DEX
∆DEY
∆INX
∆INY
∆NOP
:1
:2
Timing
:
Instructions
∆SEC
∆SED
∆SEI
∆SET
∆TAX
∆TAY
∆TSX
∆TXA
∆TXS
∆TYA
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
Op -code
PC H
PC L
Opcode
Invalid
PC H
PC L+1
page 113 of 185
Invalid
PC L+1
IMPLIED
Instruction
Byte length
Cycle number
: ∆BRK
:1
:7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
Op code
DATA
ADDRH
ADDRL
/DATA
PC H
PC L
S,00
(Note 1)
PC +1
Invalid
PC H
Opcode
PC L+1
Invalid
S
PC H
S-1
Notes 1 : Some p roducts are “01” or content of SPS flag.
2 : Some p roducts differ the address.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC L
01
PC H
page 114 of 185
FFF4
(Note 2)
S-2,00
(Note 1)
S-1,00
(Note 1)
PC L
S-2
AA
AA
AA
AA
PS
PS
F4
ADL
ADH
FFF5
(Note 2)
ADL
FF
ADL
ADH
PC H
F5
ADH ADL
IMPLIED
Byte length
: ∆STP
∆WIT
:1
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
PC +1
Invalid
Op -code
PC H
PC H
PC L
Opcode
PC L+1
Invalid
PC L +1
Return from standb y
state is excuted b y external interrup t.
Return from wait state is
excuted b y internal or
external interrup t.
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REJ09B0322-0200
page 115 of 185
IMPLIED
Instruction
Byte length
Cycle number
: ∆RTI
:1
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Invalid
Op-code
PCH
PCL
S,00
(Note)
PC+1
Opcode
S+1,00
(Note)
Invalid
Invalid
S
Note: Some products are “01” or content of SPS flag.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 116 of 185
PCL
(Stack)
PCH
(Stack)
00 (Note)
PCH
PCL+1
PS
(Stack)
PCL
PCH
S+3,00
(Note)
S+2,00
(Note)
S+1
PS
S+2
PCH
PCL
S+3
PCH
PCL
IMPLIED
Instruction
Byte length
Cycle number
: ∆RTS
:1
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Invalid
Op-code
PCH
PCL
S,00
(Note)
PC+1
Opcode
Invalid
Invalid
S
Note: Some products are “01” or content of SPS flag.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 117 of 185
PCL
(Stack)
PCH
(Stack)
00 (Note)
PCH
PCL+1
PCL
PCH
S+2,00
(Note)
S+1,00
(Note)
S+1
PCL
Invalid
PCH
S+2
PCH
PCL+1
P CH
PCL
PCH
PCL+1
IMPLIED
Byte length
Cycle number
: ∆PHA
∆PHP
:1
:3
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
ADDRH
ADDRL
/DATA
Invalid
Op -code
DATA
PC H
PC L
S,00
(Note)
PC +1
PC
Opcode
PC H
PC L+1
Invalid
A or PS
00 (Note)
S
Aor
PS
Note: Some p roducts are “01” or content of SPS flag.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 118 of 185
IMPLIED
Byte length
Cycle number
: ∆PLA
∆PLP
:1
:4
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Invalid
Op-code
PCH
PCL
(PC+1)L,00
PC+1
PC
Opcode
PCH
PCL+1
Invalid
Invalid
00
(PC+1) L
Note: Some products are “01” or content of SPS flag.
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REJ09B0322-0200
page 119 of 185
S+1,00
(Note)
DATA
00 (Note)
S+1
DATA
[T=0]
IMMEDIATE
Byte length
Cycle number
: ∆ADC∆#$nn
∆AND∆#$nn
∆CMP∆#$nn
∆CPX∆#$nn
∆CPY∆#$nn
∆EOR∆#$nn
∆LDA∆#$nn
∆LDX∆#$nn
∆LDY∆#$nn
∆ORA∆#$nn
∆SBC∆#$nn
:2
:2
Timing
:
Instructions
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
PC
PC+1
Op-code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PCH
PCL
Opcode
DATA
PCH
PCL+1
page 120 of 185
DATA
ACCUMULATOR
Byte length
Cycle number
: ∆ASL
∆DEC
∆INC
∆LSR
∆ROL
∆ROR
:1
:2
Timing
:
Instructions
∆A
∆A
∆A
∆A
∆A
∆A
φ
SYNC
R/W
RD
WR
ADDR
Op -code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
PC
PC H
PC L
Opcode
page 121 of 185
Invalid
PC H
PC L+1
Invalid
PC H
PC L+1
ACCUMULATOR BIT RELATIVE
Instructions
Byte length
: ∆BBC∆i,A,$hhll
∆BBS∆i,A,$hhll
:2
(1) With no branch
Cycle number
:4
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC +1
PC
DATA
ADDRH
ADDRL
/DATA
Invalid
Op -code
PC H
PC L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
PC H
PC L+1
Invalid
page 122 of 185
PC L+1
Invalid
PC L+1
Invalid
ACCUMULATOR BIT RELATIVE
: ∆BBC∆i,A,$hhll
∆BBS∆i,A,$hhll
:2
Instructions
Byte length
(2) With branch
Cycle number
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
Op-code
DATA
ADDRH
ADDRL
/DATA
Opcode
PCH
PCL+1
Invalid
RR : Offset address
*1 : (PC+1)L
*2 : ((PC+2) +
− RR)L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
+
− RR
Invalid
PCH
PCL
(PC+2)L
(PC+1)H
PC+1
PC
page 123 of 185
PCL+1
Invalid
PCL+1
+ RR
−
((PC+2) +
− RR)L
(PC+2) H
Invalid
Inva
(PC+2)H
(PC+2)H
*1
*2
ACCUMULATOR BIT
Byte length
Cycle number
: ∆CLB∆i,A
∆SEB∆i,A
:1
:2
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC+1
PC
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Invalid
Op-code
PCH
PCL
page 124 of 185
Opcode
PCH
PCL+1
Invalid
BIT RELATIVE
Instructions
Byte length
: ∆BBC∆i,$zz,$hhll
∆BBS∆i,$zz,$hhll
:3
(1) With no branch
Cycle number
:5
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL
Op -code
DATA
PC H
PC L
ADL,00
PC +1
Opcode
PC H
PC L+1
page 125 of 185
ADL
PC +2
Invalid
DATA
00
ADL DATA
PC H
PC L+2
Invalid
PC L+2
Invalid
BIT RELATIVE
Byte length
: ∆BBC∆i,$zz,$hhll
∆BBS∆i,$zz,$hhll
:3
(2) With branch
Cycle number
:7
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
PC+1
ADL
Op-code
PCH
PCL
Opcode
ADL,00
PCL+1
ADL
ADL DATA
RR : Offset address
*1 : (PC+3)L
*2 : ((PC+3) +
− RR)L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
DATA
00
PCH
page 126 of 185
(PC+3)L
(PC+2)H
PC+2
Invalid
+
− RR
PCH
PCL+2
Invalid
PCL+2
+
− RR
((PC+3) +
− RR)L
(PC+3) H
Invalid
(PC+3)
+
− RR
Invalid
(PC+2)H
(PC+3)H
*1
*2
((PC+3) +
− RR) H
*2
ZERO PAGE BIT
Byte length
Cycle number
: ∆CLB∆i,$zz
∆SEB∆i,$zz
:2
:5
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC
PC +1
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Op -code
PC H
PC L
Opcode
ADL,00
ADL
PC H
PC L+1
page 127 of 185
ADL
Invalid
DATA
NEW
DATA
00
ADL
DATA
ADL
ADL
NEW
DA TA
[T=0]
ZERO PAGE
Byte length
Cycle number
: ∆ADC
∆AND
∆BIT
∆CMP
∆CPX
∆CPY
∆EOR
∆LDA
∆LDX
∆LDY
∆ORA
∆SBC
∆TST
:2
:3
Timing
:
Instructions
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
∆$zz
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
Op -code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
PC
PC H
PC L
Opcode
ADL,00
ADL
00
PC H
PC L+1
page 128 of 185
ADL
DATA
ADL
DATA
ZERO PAGE
Byte length
Cycle number
: ∆ASL ∆$zz
∆COM ∆$zz
∆DEC ∆$zz
∆INC ∆$zz
∆LSR ∆$zz
∆ROL ∆$zz
∆ROR ∆$zz
:2
:5
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC +1
PC
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL
Op -code
DATA
PC H
PC L
Opcode
ADL,00
DATA
PC H
PC L+1
page 129 of 185
ADL
Invalid
NEW
DATA
00
ADL
DATA
ADL
ADL
NEW
DA TA
ZERO PAGE
Instruction
Byte length
Cycle number
: ∆RRF∆$zz
:2
:8
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
Op -code
DATA
ADDRH
PC +1
PC
PC H
ADDRL PC L
/DATA
Opcode
ADL,00
ADL
DATA
PC H
PC L+1
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL
NEW
DATA
Invalid
00
ADL
DATA
page 130 of 185
ADL
ADL
ADL
ADL
ADL
NEW
DA TA
ZERO PAGE
Instruction
Byte length
Cycle number
: ∆LDM∆#$nn,$zz
:3
:4
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
PC +1
Op -code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC H
PC L
Opcode
PC L+1 DATA
DATA
ADL
DATA
PC H
page 131 of 185
ADL,00
PC +2
PC H
PC L+2
ADL
00
ADL
DATA
ZERO PAGE
Byte length
Cycle number
: ∆STA∆$zz
∆STX∆$zz
∆STY∆$zz
:2
:4
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
PC
ADL
Op -code
PC H
PC L
Opcode
page 132 of 185
ADL,00
ADL
DATA
00
PC H
PC L+1
Invalid
ADL
ADL
DATA
Zero Page X
Instruction
Byte length
Cycle number
: ∆MUL∆$zz,X
:2
: 15
Timing
:
(Note)
φ
SYNC
R/W
RD
WR
ADDR
DATA
PC
Opcode
PC+1
ADL
S,SPS
ADL+X,00
Invalid
DATA
Invalid
SPS: A selected page by stack page selection bit of the CPU mode register.
Note: This instruction cannot be used for some products.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 133 of 185
NEW
DATA
Invalid
Zero Page X
Instruction
Byte length
Cycle number
: ∆DIV∆$zz,X (Note)
:2
: 16
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC+1
PC
ADL
+X,00
Low-order DATA
DATA
Opcode
ADL
ADL+X+1,00
Invalid
Invalid
SPS: A selected page by stack page selection bit of the CPU mode register.
Note: This instruction cannot be used for some products.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
S,SPS
High-order DATA
page 134 of 185
NEW
DATA
Invalid
Zero Page X
Byte length
Cycle number
: ∆ASL ∆$zz,X
∆DEC ∆$zz,X
∆INC ∆$zz,X
∆LSR ∆$zz,X
∆ROL ∆$zz,X
∆ROR∆$zz,X
:2
:6
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Op -code
Opcode
ADL
ADL +X,00
Invalid
DATA
PC H
PC H
PC L
(PC+1)L
,00
PC +1
PC
PC L+1
page 135 of 185
ADL
Invalid
NEW
DATA
00
(PC+1) L
A DL+X DATA
A DL+X
A DL+X
NEW
DA TA
[T=0]
ZERO PAGE X, ZERO PAGE Y
Byte length
Cycle number
: ∆ADC ∆$zz,X
∆AND ∆$zz,X
∆CMP∆$zz,X
∆EOR ∆$zz,X
∆LDA ∆$zz,X
∆LDX ∆$zz,Y
∆LDY ∆$zz,X
∆ORA∆$zz,X
∆SBC ∆$zz,X
:2
:4
Timing
:
Instructions
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PCH
PCL
Opcode
page 136 of 185
Invalid
ADL
Op-code
PCH
PCL+1
ADL+X (orY)
,00
(PC+1) L
,00
PC+1
PC
ADL
DATA
00
(PC
+1)L
ADL+X
(or Y)
DATA
ZERO PAGE X, ZERO PAGE Y
Byte length
Cycle number
: ∆STA∆$zz,X
∆STX∆$zz,Y
∆STY∆$zz,X
:2
:5
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
Op-code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PCH
PCL
(PC+1) L
,00
PC+1
PC
Opcode
page 137 of 185
ADL
ADL+X(or Y)
,00
Invalid
PCH
PCL+1
ADL
Invalid
DATA
00
(PC
+1) L
ADL+X
(or Y)
ADL+X
(or Y)
DATA
[T=0]
ABSOLUTE
Byte length
Cycle number
: ∆ADC
∆AND
∆BIT
∆CMP
∆CPX
∆CPY
∆EOR
∆LDA
∆LDX
∆LDY
∆ORA
∆SBC
:3
:4
Timing
:
Instructions
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
DATA
Op-code
ADDRH
ADDRL
/DATA
PCH
PCL
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
ADL
PCH
PCL+1
ADL
ADH
PC+2
PC+1
PC
ADL
page 138 of 185
ADH
PCH
PCL+2
ADH
DATA
ADH
ADL
DATA
ABSOLUTE
Byte length
Cycle number
: ∆ASL ∆$hhll
∆DEC ∆$hhll
∆INC ∆$hhll
∆LSR ∆$hhll
∆ROL ∆$hhll
∆ROR∆$hhll
:3
:6
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
PC
PC +1
Op -code
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC H
PC L
Opcode
PC +2
ADL
PC H
PC L+1
page 139 of 185
ADL
ADL ,ADH
ADH
PC H
PC L+2
ADH
DATA
Invalid
NEW
DATA
ADH
ADL DATA ADL
ADL
NEW
DA TA
ABSOLUTE
Instruction
Byte length
Cycle number
: ∆JMP∆$hhll
:3
:3
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
PC +1
Op -code
DATA
ADDRH
PC H
ADDRL
/DATA
OpPC L code
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 140 of 185
PC H
PC L
PC H
PC L+1
PC L,PC H
PC +2
PC L
PC H
PC L+2
PC H
PC H
PC L
ABSOLUTE
Instruction
Byte length
Cycle number
: ∆JSR∆$hhll
:3
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
Opcode
Invalid
ADL
Op-code
PCH
PCL+1
ADL
page 141 of 185
(PC+2)H
S
S
(PC
+2)H
ADL
ADH
PC+2
(PC+2)L
00 (Note)
Note: Some products are “01” or content of SPS flag.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
S-1,00
(Note)
S,00 (Note)
PC+1
ADH
PCH
S-1
(PC
+2)L
PCL+2
ADH
ADH
ADL
ABSOLUTE
Byte length
Cycle number
: ∆STA∆$hhll
∆STX∆$hhll
∆STY∆$hhll
:3
:5
Timing
:
Instructions
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Op-code
PCH
PCL
Opcode
page 142 of 185
ADL
PCH
PCL+1
ADL
ADH
PC+2
PC+1
PC
ADL
ADH
ADH
DATA
ADH
PCH
PCL+2
Invalid
ADL
ADL
DATA
[T=0]
ABSOLUTE X, ABSOLUTE Y
Byte length
Cycle number
: ∆ADC
∆AND
∆CMP
∆EOR
∆LDA
∆LDX
∆LDY
∆ORA
∆SBC
:3
:5
Timing
:
Instructions
∆$hhll,X or Y
∆$hhll,X or Y
∆$hhll,X or Y
∆$hhll,X or Y
∆$hhll,X or Y
∆$hhll,Y
∆$hhll,X
∆$hhll,X or Y
∆$hhll,X or Y
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
Op-code
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
Opcode
PCH
C : Carry of ADL+X or Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL
PCL+1
page 143 of 185
AD L+X(or Y)
AD H
PC+2
PC+1
PC
ADL
Invalid
ADH
PCH
PCL+2
ADH
AD L+X(or Y)
AD H+C
ADH
ADL+X
(or Y)
DATA
ADH +C
ADL+X
(or Y)
DATA
ABSOLUTE X
Byte length
Cycle number
: ∆ASL
∆DEC
∆INC
∆LSR
∆ROL
∆ROR
:3
:7
Timing
:
Instructions
∆$hhll,X
∆$hhll,X
∆$hhll,X
∆$hhll,X
∆$hhll,X
∆$hhll,X
φ
SYNC
R/W
RD
WR
ADDR
PC
Op -code
DATA
ADDRH
ADDRL
/DATA
PC H
PC L
Opcode
PC H
ADL
PC L+2
C : C arry of ADL +X
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 144 of 185
ADH
ADL+X
ADH+C
Invalid
ADH
ADL
PC H
PC L+1
ADL+X
ADH
PC +2
PC +1
ADH
A D L+X
DATA
Invalid
NEW
DATA
ADH +C
A D L+X DATA A D L+X
A D L+X NEW
DA TA
ABSOLUTE X, ABSOLUTE Y
Instruction
Byte length
Cycle number
: ∆STA∆$hhll,X or Y
:3
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
Op -code
DATA
ADDRH
ADDRL
/DATA
PC H
PC H
PC L
ADL
Opcode
PC L+1
ADL
C : C arry of ADL +X or Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 145 of 185
Invalid
ADH
PC H
PC L+2
A D L+X(or Y )
A D H+C
A D L+X(or Y )
AD H
PC +2
PC +1
ADH
ADH
ADL+X
(or Y)
Invalid
DATA
ADH +C
ADL+X
(or Y)
ADL+X
(or Y)
DATA
INDIRECT
Instruction
Byte length
Cycle number
: ∆JMP∆($hhll)
:3
:5
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
Op-code
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
Opcode
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL
PCH
PCL+1
page 146 of 185
BAL
BAH
PC+2
PC+1
BAL
BAH
PCH
PCL+2
BAH
BAL+1
B AH
ADL
BAH
BAL
ADL
ADL
ADH
ADH
BAH
BAL+1
ADH
ADH
ADL
ZERO PAGE INDIRECT
Instruction
Byte length
Cycle number
: ∆JMP∆($zz)
: 2
: 4
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
Op-code
DATA
ADDRH
ADDRL
/DATA
PC+1
PCH
PCL
Opcode
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 147 of 185
BAL
ADL
PCH
PCL+1
BAL
ADH
ADH
00
BAL
ADL
ADH
BAL+1,00
BAL,00
ADL
BAL+1
ADH
ADL
ZERO PAGE INDIRECT
Instruction
Byte length
Cycle number
: ∆JSR∆($zz)
:2
:7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
PC+1
DATA
ADDRH
ADDRL
/DATA
Op-code
PCH
PCL
Opcode
Invalid
BAL
PCH
PCL+1
BAL
(PC+1)H
(PC+1)L
S
S
Note: Some kind types are “01” or content of SPS flag.
page 148 of 185
ADL
ADH
BAL+1
,00
BAL,00
ADL
01
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
S-1,00
(Note)
S,00 (Note)
ADH
ADH
00
(PC
+1)H
S-1
(PC
+1)L
BAL
ADL
BAL+1
ADH
ADL
[T=0]
INDIRECT X
Byte length
Cycle number
: ∆ADC
∆AND
∆CMP
∆EOR
∆LDA
∆ORA
∆SBC
:2
:6
Timing
:
Instructions
∆($zz,X)
∆($zz,X)
∆($zz,X)
∆($zz,X)
∆($zz,X)
∆($zz,X)
∆($zz,X)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
BAL
Op-code
PCH
PCL
(PC+1) L,00
PC+1
Opcode
PCH
PCL+1
BAL
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Invalid
page 149 of 185
ADL
ADH
BAL+X+1
,00
BAL+X,00
ADL
ADH
00
(PC
+1)L
BAL+X
ADL
DATA
ADH
BAL
+X+1
ADH
ADL
DATA
INDIRECT X
Instruction
Byte length
Cycle number
: ∆STA∆($zz,X)
: 2
: 7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op-code
PCH
PCL
(PC +1) L
,00
PC+1
Opcode
BAL
PCH
PCL+1
BAL
ADL
ADH
(PC
+1)L
page 150 of 185
BAL+X
ADL
Invalid
DATA
ADH
00
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Invalid
ADL
ADH
BAL+X+1
,00
BAL+X
,00
BAL
+X+1
ADH
ADL
ADL
DATA
[T=0]
INDIRECT Y
Byte length
Cycle number
: ∆ADC ∆($zz),Y
∆AND ∆($zz),Y
∆CMP∆($zz),Y
∆EOR ∆($zz),Y
∆LDA ∆($zz),Y
∆ORA∆($zz),Y
∆SBC ∆($zz),Y
:2
:6
Timing
:
Instructions
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
(T=0)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op -code
PC H
PC L
BA L
ADL
PC H
Opcode
PC L+1
BA L
BA : Basic address
C : C arry of ADL +Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL+1
,00
BA L ,00
PC +1
page 151 of 185
ADL+Y
ADH
BA L
ADL
BA L+1
Invalid
ADH
ADH
00
ADH
ADL+Y
ADH+C
A DL+Y
DATA
ADH +C
A DL+Y
DATA
INDIRECT Y
Instruction
Byte length
Cycle number
: ∆STA∆($zz),Y
:2
:7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
PC +1
Op -code
PC H
PC L
Opcode
BA L
PC H
PC L+1
BA L
ADL
BA L ADL
C : C arry of ADL +Y
page 152 of 185
BA L+1
ADL+Y
ADH+C
ADL+Y
ADH
Invalid
ADH
ADH
00
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL+1
,00
BA L ,00
ADH
A D L+Y
Invalid
DATA
ADH +C
A D L+Y
A D L+Y DATA
RELATIVE
Instructions
Byte length
: ∆BCC
∆BCS
∆BEQ
∆BMI
∆BNE
∆BPL
∆BVC
∆BVS
: 2
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
(1)With no branch
Cycle number
: 2
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
PC
Invalid
Op -code
PC H
PC L
Opcode
page 153 of 185
PC H
PC L+1
Invalid
RELATIVE
Byte length
: ∆BCC
∆BCS
∆BEQ
∆BMI
∆BNE
∆BPL
∆BVC
∆BVS
:2
(2)With branch
Cycle number
:4
Timing
:
Instructions
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
∆$hhll
φ
SYNC
R/W
RD
WR
PC
ADDR
ADDRH
ADDRL
/DATA
PCH
PCH
Opcode
RR : Offset value
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
+ RR
−
Op-code
DATA
(PC+2)L
(PC+1)H
PC+1
page 154 of 185
PCH
PCL+1
+ RR
−
+ RR)L
((PC+2) −
(PC+2) H
Invalid
(PC+1)H
(PC+2)L
Invalid
(PC+2)H
((PC+2)
RR)L
(PC+2) +
− RR
((PC+2) +
− RR ) H
((PC+2)
+
−RR)L
RELATIVE
Instruction
Byte length
Cycle number
: ∆BRA∆$hhll
:2
:4
Timing
:
φ
SYNC
R/W
RD
WR
PCH
ADDRH
ADDRL
/DATA
+
− RR
Op-code
DATA
PCL
Opcode
PCH
PCL+1
RR : Offset value
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
(PC+2) L
(PC+1) H
PC+1
PC
ADDR
page 155 of 185
+
− RR
Invalid
(PC+1)H
(PC
+2)L
+ RR ) L
((PC+2) −
(PC+2)H
Invalid
(PC+2)H
((PC+2)
+ RR)L
−
+ RR
(PC+2 ) −
+ RR)H
((PC+2) −
((PC+2)
+ RR)L
−
SPECIAL PAGE
Instruction
Byte length
Cycle number
: ∆JSR∆\$hhll
: 2
: 5
Timing
:
φ
SYNC
R/W
RD
WR
PC
ADDR
DATA
Op -code
PC H
ADDRH
ADDRL
/DATA
PC +1
PC L
Opcode
Invalid
BA L
PC H
PC L+1
BA L
S
Note : Some p roducts are “01” or content of SPS flag.
page 156 of 185
(PC +1)H
S
(PC
+1)H
BA L ,FF
(PC +1)L
00 (Note)
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
S-1,00
(Note)
S,00 (Note)
FF
S-1
(PC
+1)L
BA L
[T=1]
IMMEDIATE
Byte length
Cycle number
: ∆ADC∆#$nn
∆AND∆#$nn
∆EOR∆#$nn
∆ORA∆#$nn
∆SBC∆#$nn
:2
:5
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC +1
PC
DATA
ADDRL
/DATA
DATA
1
Op -code
ADDRH
PC H
PC L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
X,00
DATA
2
Invalid
PC H
PC L+1
page 157 of 185
DA TA
1
NEW
DATA
00
X
DA TA
2
X
X
NEW
DA TA
[T=1]
IMMEDIATE
Instruction
Byte length
Cycle number
: ∆CMP∆#$nn
:2
:3
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
PC
Op -code
PC H
PC L
X,00
PC H
OpPC L+1 DA TA
code
1
page 158 of 185
DATA
2
DATA
1
00
X
DA TA
2
[T=1]
IMMEDIATE
Instruction
Byte length
Cycle number
: ∆LDA∆#$nn
:2
:4
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PC +1
Op -code
PC H
PC L
Opcode
page 159 of 185
X,00
DATA
PC H
PC L+1 DATA
Invalid
DATA
00
X
X
DATA
[T=1]
ZERO PAGE
Byte length
Cycle number
: ∆ADC∆$zz
∆AND∆$zz
∆EOR∆$zz
∆ORA∆$zz
∆SBC∆$zz
:2
:6
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
PC
ADDR
DATA
ADDRH
ADDRL
/DATA
ADL
Op -code
PC H
PC L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
X,00
ADL ,00
PC +1
DATA
1
DA TA
2
PC H
PC L+1
ADL
page 160 of 185
Invalid
NEW
DATA
00
ADL
DA TA
1
X
DA TA
2
X
X
NEW
DA TA
[T=1]
ZERO PAGE
Instruction
Byte length
Cycle number
: ∆CMP∆$zz
:2
:4
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADL
Op -code
ADDRH
PC H
ADDRL
/DATA
PC L code
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL ,00
PC +1
PC
Op-
PC H
PC L+1
page 161 of 185
ADL
X,00
DATA
2
DATA
1
00
ADL
DA TA
1
X
DA TA
2
[T=1]
ZERO PAGE
Instruction
Byte length
Cycle number
: ∆LDA∆$zz
:2
:5
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
PC +1
PC
Op -code
PC H
PC L
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
ADL ,00
ADL
X,00
PC H
PC L+1
ADL
page 162 of 185
Invalid
DATA
DATA
00
ADL DATA
X
X
DATA
[T=1]
ZERO PAGE X
Byte length
Cycle number
: ∆ADC∆$zz,X
∆AND∆$zz,X
∆EOR∆$zz,X
∆ORA∆$zz,X
∆SBC∆$zz,X
:2
:7
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op-code
PCH
PCL
ADL
ADL+X
,00
Invalid
X,00
DATA
2
DATA
1
PCH
Opcode
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
(PC+1) L
,00
PC+1
PCL+1
ADL
Invalid
NEW
DATA
00
(PC
+1)L
page 163 of 185
ADL
+X
DATA
1
X
DATA
2
X
X
NEW
DATA
[T=1]
ZERO PAGE X
Instruction
Byte length
Cycle number
: ∆CMP∆$zz,X
:2
:5
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
ADL
Op-code
PCH
PCL
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
(PC+1) L
,00
PC+1
PC
ADL+X
,00
Opcode
PCL+1
ADL
page 164 of 185
DATA
2
DATA
1
Invalid
PCH
X,00
00
(PC
+1) L
AD L+X
DATA
1
X
DATA
2
[T=1]
ZERO PAGE X
Instruction
Byte length
Cycle number
: ∆LDA∆$zz,X
:2
:6
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
ADL
Op-code
PCH
PCL
(PC+1) L
,00
PC+1
PC
Invalid
PCH
Opcode
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL+X
,00
PCL+1
ADL
X,00
DATA
Invalid
DATA
00
(PC
+1) L
page 165 of 185
ADL
+X
DATA
X
X
DATA
[T=1]
ABSOLUTE
Byte length
Cycle number
: ∆ADC∆$hhll
∆AND∆$hhll
∆EOR∆$hhll
∆ORA∆$hhll
∆SBC∆$hhll
:3
:7
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
ADL
Op-code
PCH
PCL
Opcode
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
PCH
PCL+1
ADL
ADH
PC+2
PC+1
ADL
PCL+2
page 166 of 185
ADH
DATA
2
DATA
1
ADH
PCH
X,00
Invalid
ADH
ADL
DATA
1
NEW
DATA
00
X
DATA
2
X
X
NEW
DATA
[T=1]
ABSOLUTE
Instruction
Byte length
Cycle number
: ∆CMP∆$hhll
:3
:5
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
ADL
Op-code
PCH
PCL
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
PCH
PCL+1
ADL
ADH
PC+2
PC+1
ADL
page 167 of 185
DATA
1
ADH
PCH
PCL+2
ADH
X,00
DATA
2
ADH
ADL
DATA
1
00
X
DATA
2
[T=1]
ABSOLUTE
Instruction
Byte length
Cycle number
: ∆LDA∆$hhll
:3
:6
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
ADL
Op-code
PCH
PCL
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
Opcode
PCH
PCL+1
ADL
page 168 of 185
ADL
ADH
PC+2
PC+1
ADH
PCH
PCL+2
ADH
X,00
DATA
ADH
ADL
DATA
Invalid
DATA
00
X
X
DATA
[T=1]
ABSOLUTE X, ABSOLUTE Y
Byte length
Cycle number
: ∆ADC∆$hhll,X or Y
∆AND∆$hhll,X or Y
∆EOR∆$hhll,X or Y
∆ORA∆$hhll,X or Y
∆SBC∆$hhll,X or Y
:3
:8
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
DATA
ADDRH
ADDRL
/DATA
PC +1
PC
PC H
PC L
Opcode
PC H
PC L+1
ADL
PC H
PC L+2
ADH
C : C arry of ADL +X or Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 169 of 185
A D L+X(or Y )
A D H+C
Invalid
ADH
ADL
Op -code
A D L+X(or Y )
AD H
PC +2
ADH
ADL+X
(or Y)
X,00
DATA
2
DATA
1
Invalid
ADH +C
ADL+X
(or Y)
DA TA
1
NEW
DATA
00
X
DA TA
2
X
X
NEW
DA TA
[T=1]
ABSOLUTE X, ABSOLUTE Y
Instruction
Byte length
Cycle number
: ∆CMP∆$hhll,X or Y (T=1)
:3
:6
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
ADL
Op -code
PC H
PC L
PC L+1
ADL
PC L+2
C : C arry of ADL +X or Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 170 of 185
ADH
A DL+X(or Y )
A DH+C
Invalid
ADH
PC H
PC H
Opcode
A DL+X(or Y )
A DH
PC +2
PC +1
ADH
ADL+X
(or Y)
X,00
DATA
2
DATA
1
ADH +C
ADL+X
(or Y)
DA TA
1
00
X
DA TA
2
[T=1]
ABSOLUTE X, ABSOLUTE Y
Instruction
Byte length
Cycle number
: ∆LDA∆$hhll,X or Y (T=1)
:3
:7
Timing
:
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op -code
PC L
ADL
Opcode
PC L+1
ADL
PC L+2
C : C arry of ADL +X or Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 171 of 185
ADH
A DL+X(or Y )
A DH+C
Invalid
ADH
PC H
PC H
PC H
A DL+X(or Y )
A DH
PC +2
PC +1
ADH
A DL+
X(orY )
X,00
DATA
ADH +C
A DL+
X(orY ) DATA
Invalid
DATA
00
X
X
DATA
[T=1]
INDIRECT X
Byte length
Cycle number
: ∆ADC∆($zz,X)
∆AND∆($zz,X)
∆EOR∆($zz,X)
∆ORA∆($zz,X)
∆SBC∆($zz,X)
:2
:9
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
Opcode
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
(PC+1) L
,00
PC+1
BAL
Invalid
PCH
Op- PCL
code +1
BAL
(PC
+1)L
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADL
00
page 172 of 185
BAL
+X
ADL
ADH
BAL+X
+1,00
BAL+X
,00
X,00
DATA
1
ADH
DATA
2
ADH
AD L BAL+ AD H AD L DATA
X+1
1
NEW
DATA
Invalid
00
X
DATA
2
X
X
NEW
DATA
[T=1]
INDIRECT X
Instruction
Byte length
Cycle number
: ∆CMP∆($zz,X)
:2
:7
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op-code
PCH
PCL
(PC+1) L
,00
PC+1
Opcode
Invalid
BAL
PCH
PCL
+1
B AL
A DL
A DH
BAL+X+1
,00
ADL
(PC
+1)L
page 173 of 185
BAL
+X
X,00
DATA
2
DATA
1
ADH
ADH
00
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL+X
,00
ADL
BAL+
X+1
A DH
ADL
DATA
1
00
X
DATA
2
[T=1]
INDIRECT X
Instruction
Byte length
Cycle number
: ∆LDA∆($zz,X)
:2
:8
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
Opcode
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
(PC+1) L
,00
PC+1
BAL
Invalid
PCH
Op- PCL BAL
code +1
(PC
+1)L
page 174 of 185
BAL
+X
BAL+X +1
,00
ADL
00
BA : Basic address
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL+X
,00
ADH
ADL
ADH
X,00
DATA
ADH
AD L BAL+ AD H AD L DATA
X+1
Invalid
DATA
00
X
X
DATA
[T=1]
INDIRECT Y
Byte length
Cycle number
: ∆ADC∆($zz),Y
∆AND∆($zz),Y
∆EOR∆($zz),Y
∆ORA∆($zz),Y
∆SBC∆($zz),Y
:2
:9
Timing
:
Instructions
(T=1)
(T=1)
(T=1)
(T=1)
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
Op-code
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
BAL
,00
PC+1
BAL
PCH
Op- PCL
code +1
BAL
BAL+1
,00
ADL
AD L
BA : Basic address
C : Carry of ADL+Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 175 of 185
BA L
+1
ADL+Y
ADH+C
Invalid
ADH
ADH
00
BAL
ADL+Y
A DH
AD H AD L
+Y
X,00
DATA
1
DATA
2
ADH+C
AD L DATA
1
+Y
NEW
DATA
Invalid
00
X
DATA
2
X
X
NEW
DATA
[T=1]
INDIRECT Y
Instruction
Byte length
Cycle number
: ∆CMP∆($zz),Y
:2
:7
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
DATA
ADDRH
ADDRL
/DATA
Op-code
PCH
PCL
BAL
,00
PC+1
Opcode
BAL
BAL
BAL
BA : Basic address
C : Carry of ADL+Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
ADH
00
page 176 of 185
AD L
BAL
+1
AD H
ADL+Y
ADH+C
AD L
+Y
X,00
DATA
1
Invalid
ADH
ADL
PCH
PCL
+1
ADL+Y
ADH
BAL+1
,00
DATA
2
ADH+C
AD L
+Y
DATA
1
00
X
DATA
2
[T=1]
INDIRECT Y
Instruction
Byte length
Cycle number
: ∆LDA∆($zz),Y
: 2
: 8
Timing
:
(T=1)
φ
SYNC
R/W
RD
WR
ADDR
PC
Opcode
DATA
ADDRH
ADDRL
/DATA
PCH
PCL
BAL
,00
PC+1
Opcode
ADL
BAL
PCH
PCL
BAL
+1
00
BAL
AD L
BA : Basic address
C : Carry of ADL+Y
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
BAL+1
,00
page 177 of 185
BA L
+1
ADL+Y
ADH
ADL+Y
ADH+C
Invalid
ADH
ADH
AD H AD L
+Y
X,00
DATA
ADH+C
AD L DATA
+Y
Invalid
DATA
00
X
X
DATA
APPENDIX 2
740 Family Machine Language Instruction Table
APPENDIX 2. 740 Family Machine Language Instruction Table
Parameter
Stack
Operation
Transfer
Store
Data Transfer
Load
Classification
SYMBOL
FUNCTION
INSTRUCTION CODE
FLAG
N V T B DI Z C
LDA # $ nn
(A)←nn
✕✕✕✕✕
✕
LDA $ zz
(A)←(M)
where
M=(zz)
✕✕✕✕✕
✕
LDA $ zz, X
(A)←(M)
where
M=(zz+(X))
✕✕✕✕✕
✕
LDA $ hhII
(A)←(M)
where
M=(hhII)
✕✕✕✕✕
✕
LDA $ hhII, X
(A)←(M)
where
M=(hhII+(X))
✕✕✕✕✕
✕
LDA $ hhII, Y
(A)←(M)
where
M=(hhII+(Y))
✕✕✕✕✕
✕
LDA
($ zz, X)
(A)←(M)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕
✕
LDA
($ zz), Y
(A)←(M)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕
✕
✕✕✕✕✕
✕
LDX # $ nn
(X)←nn
LDX $ zz
(X)←(M)
where
M=(zz)
✕✕✕✕✕
✕
LDX $ zz, Y
(X)←(M)
where
M=(zz+(Y))
✕✕✕✕✕
✕
LDX $ hhII
(X)←(M)
where
M=(hhII)
✕✕✕✕✕
✕
LDX $ hhII, Y
(X)←(M)
where
M=(hhII+(Y))
✕✕✕✕✕
✕
LDY # $ nn
(Y)←nn
✕✕✕✕✕
✕
LDY $ zz
(Y)←(M)
where
M=(zz)
✕✕✕✕✕
✕
LDY $ zz, X
(Y)←(M)
where
M=(zz+(X))
✕✕✕✕✕
✕
LDY $ hhII
(Y)←(M)
where
M=(hhII)
✕✕✕✕✕
✕
LDY $ hhII, X
(Y)←(M)
where
M=(hhII+(X))
✕✕✕✕✕
✕
LDM # $ nn, $ zz
(M)←nn
where
M=(zz)
✕✕✕✕✕✕✕✕
STA $ zz
(M)←(A)
where
M=(zz)
✕✕✕✕✕✕✕✕
STA $ zz, X
(M)←(A)
where
M=(zz+(X))
✕✕✕✕✕✕✕✕
STA $ hhII
(M)←(A)
where
M=(hhll)
✕✕✕✕✕✕✕✕
STA $ hhII, X
(M)←(A)
where
M=(hhII+(X))
✕✕✕✕✕✕✕✕
STA $ hhII, Y
(M)←(A)
where
M=(hhII+(Y))
✕✕✕✕✕✕✕✕
STA
($ zz, X)
(M)←(A)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕✕✕✕
STA
($ zz), Y
D7D6D5D4
D3D2D1D0
HEX
BYTE
CYCLE
NUMBER NUMBER
1 0 1 0
1
<B2>
1 0 1 0
0
<B2>
1 0 1 1
0
<B2>
1 0 1 0
1
<B2>
<B3>
1 0 1 1
1
<B2>
<B3>
1 0 1 1
1
<B2>
<B3>
1 0 1 0
0
<B2>
1 0 1 1
0
<B2>
0 0 1
A9
2
2
2
1 0 1
A5
2
3
2
1 0 1
B5
2
4
2
1 0 1
AD
3
4
2
1 0 1
BD
3
5
2
0 0 1
B9
3
5
2
0 0 1
A1
2
6
2
0 0 1
B1
2
6
2
1 0 1 0
0
<B2>
1 0 1 0
0
<B2>
1 0 1 1
0
<B2>
1 0 1 0
1
<B2>
<B3>
1 0 1 1
1
<B2>
<B3>
1 0 1 0
0
<B2>
1 0 1 0
0
<B2>
1 0 1 1
0
<B2>
1 0 1 0
1
<B2>
<B3>
1 0 1 1
1
<B2>
<B3>
0 1 0
A2
2
2
1 1 0
A6
2
3
1 1 0
B6
2
4
1 1 0
AE
3
4
1 1 0
BE
3
5
0 0 0
A0
2
2
1 0 0
A4
2
3
1 0 0
B4
2
4
1 0 0
AC
3
4
1 0 0
BC
3
5
0 0 1 1
1
<B2>
<B3>
1 0 0 0
0
<B2>
1 0 0 1
0
<B2>
1 0 0 0
1
<B2>
<B3>
1 0 0 1
1
<B2>
<B3>
1 0 0 1
1
<B2>
<B3>
1 0 0 0
0
<B2>
1 0 0 1
0
<B2>
1 0 0
3C
3
4
1 0 1
85
2
4
1 0 1
95
2
5
1 0 1
8D
3
5
1 0 1
9D
3
6
0 0 1
99
3
6
0 0 1
81
2
7
0 0 1
91
2
7
1 0 0 0
0 1 1 0
<B2>
1 0 0 1
0 1 1 0
<B2>
1 0 0 0
1 1 1 0
<B2>
<B3>
86
2
4
96
2
5
8E
3
5
1 0 0
84
2
4
1 0 0
94
2
5
1 0 0
8C
3
6
0 1 0
0 1 0
AA
8A
1
1
2
2
(M)←(A)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕✕✕✕
STX $ zz
(M)←(X)
where
M=(zz)
✕✕✕✕✕✕✕✕
STX $ zz, Y
(M)←(X)
where
M=(zz+(Y))
✕✕✕✕✕✕✕✕
STX $ hhII
(M)←(X)
where
M=(hhII)
✕✕✕✕✕✕✕✕
STY $ zz
(M)←(Y)
where
M=(zz)
✕✕✕✕✕✕✕✕
STY $ zz, X
(M)←(Y)
where
M=(zz+(X))
✕✕✕✕✕✕✕✕
STY $ hhII
(M)←(Y)
where
M=(hhII)
✕✕✕✕✕✕✕✕
TAX
TXA
(X)←(A)
(A)←(X)
✕✕✕✕✕
✕✕✕✕✕
✕
✕
1 0 0 0
0
<B2>
1 0 0 1
0
<B2>
1 0 0 0
1
<B2>
<B3>
1 0 1 0
1
1 0 0 0
1
TAY
TYA
(Y)←(A)
(A)←(Y)
✕✕✕✕✕
✕✕✕✕✕
✕
✕
1 0 1 0
1 0 0 1
1 0 0 0
1 0 0 0
A8
98
1
1
2
2
TSX
TXS
(X)←(S)
(S)←(X)
✕✕✕✕✕ ✕
✕✕✕✕✕✕✕✕
1 0 1 1
1 0 0 1
1 0 1 0
1 0 1 0
BA
9A
1
1
2
2
PHA
PHP
(M(S))←(A), (S)←(S)—1
(M(S))←(PS), (S)←(S)—1
✕✕✕✕✕✕✕✕
✕✕✕✕✕✕✕✕
0 1 0 0
0 0 0 0
1 0 0 0
1 0 0 0
48
08
1
1
3
3
PLA
PLP
(S)←(S)+1, (A)←(M(S))
(S)←(S)+1, (PS)←(M(S))
✕✕✕✕✕ ✕
Previous status in stack
0 1 1 0
0 0 1 0
1 0 0 0
1 0 0 0
68
28
1
1
4
4
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 178 of 185
NOTE
740 Family Machine Language Instruction Table
Parameter
Add and Sabstruct
Multiply
/ Divide
Operation
Classification
SYMBOL
FUNCTION
INSTRUCTION CODE
FLAG
N V T B D I Z C
✕✕✕✕
ADC # $ nn
(A)←(A)+nn+(C)
ADC $ zz
(A)←(A)+(M)+(C)
where
M=(zz)
✕✕✕✕
ADC $ zz, X
(A)←(A)+(M)+(C)
where
M=(zz+(X))
✕✕✕✕
ADC $ hhII
(A)←(A)+(M)+(C)
where
M=(hhII)
✕✕✕✕
ADC $ hhII, X
(A)←(A)+(M)+(C)
where
M=(hhII+(X))
✕✕✕✕
ADC $ hhII, Y
(A)←(A)+(M)+(C)
where
M=(hhII+(Y))
✕✕✕✕
ADC ($ zz, X)
(A)←(A)+(M)+(C)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕
ADC ($ zz), Y
(A)←(A)+(M)+(C)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕
SBC # $ nn
(A)←(A)–nn–(C)
SBC $ zz
(A)←(A)–(M)–(C)
where
M=(zz)
✕✕✕✕
SBC $ zz, X
(A)←(A)–(M)–(C)
where
M=(zz+(X))
✕✕✕✕
SBC $ hhII
(A)←(A)–(M)–(C)
where
M=(hhII)
✕✕✕✕
SBC $ hhII, X
(A)←(A)–(M)–(C)
where
M=(hhII+(X))
✕✕✕✕
SBC $ hhII, Y
(A)←(A)–(M)–(C)
where
M=(hhII+(Y))
✕✕✕✕
SBC
($ zz, X)
(A)←(A)–(M)–(C)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕
SBC
($ zz), Y
(A)←(A)–(M)–(C)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕
INC
A
(A)←(A)+1
INC
$ zz
(M)←(M)+1
where
M=(zz)
✕✕✕✕✕
✕
INC
$ zz, X
(M)←(M)+1
where
M=(zz+(X))
✕✕✕✕✕
✕
INC
$ hhII
(M)←(M)+1
where
M=(hhll)
✕✕✕✕✕
✕
INC
$ hhII, X
(M)←(M)+1
where
M=(hhII+(X))
✕✕✕✕✕
✕
✕✕✕✕
✕✕✕✕✕
✕
D7D6D5D4
D3D2D1D0
HEX
BYTE
CYCLE
NUMBER NUMBER
0 1 1 0
1
<B2>
0 1 1 0
0
<B2>
0 1 1 1
0
<B2>
0 1 1 0
1
<B2>
<B3>
0 1 1 1
1
<B2>
<B3>
0 1 1 1
1
<B2>
<B3>
0 1 1 0
0
<B2>
0 1 1 1
0
<B2>
0 0 1
69
2
2
1
1 0 1
65
2
3
1
1 0 1
75
2
4
1
1 0 1
6D
3
4
1
1 0 1
7D
3
5
1
0 0 1
79
3
5
1
0 0 1
61
2
6
1
0 0 1
71
2
6
1
1 1 1 0
1
<B2>
1 1 1 0
0
<B2>
1 1 1 1
0
<B2>
1 1 1 0
1
<B2>
<B3>
1 1 1 1
1
<B2>
<B3>
1 1 1 1
1
<B2>
<B3>
1 1 1 0
0
<B2>
1 1 1 1
0
<B2>
0 0 1
E9
2
2
1
1 0 1
E5
2
3
1
1 0 1
F5
2
4
1
1 0 1
ED
3
4
1
1 0 1
FD
3
5
1
0 0 1
F9
3
5
1
0 0 1
E1
2
6
1
0 0 1
F1
2
6
1
1 0 1 0
3A
1
2
E6
2
5
1 1 0
F6
2
6
1 1 0
EE
3
6
1 1 0
FE
3
7
0 1 0
1A
1
2
1 1 0
C6
2
5
1 1 0
D6
2
6
1 1 0
CE
3
6
1 1 0
DE
3
7
0 0 1 1
1 1 1 0
0
<B2>
1 1 1 1
0
<B2>
1 1 1 0
1
<B2>
<B3>
1 1 1 1
1
<B2>
<B3>
0 0 0 1
1
1 1 0
DEC A
(A)←(A)–1
✕✕✕✕✕
✕
DEC $ zz
(M)←(M)–1
where
M=(zz)
✕✕✕✕✕
✕
DEC $ zz, X
(M)←(M)–1
where
M=(zz+(X))
✕✕✕✕✕
✕
DEC $ hhII
(M)←(M)–1
where
M=(hhII)
✕✕✕✕✕
✕
DEC $ hhII, X
(M)←(M)–1
where
M=(hhII+(X))
✕✕✕✕✕
✕
INX
(X)←(X)+1
✕✕✕✕✕
✕
1 1 1 0
1 0 0 0
E8
1
2
DEX
(X)←(X)–1
✕✕✕✕✕
✕
1 1 0 0
1 0 1 0
CA
1
2
INY
(Y)←(Y)+1
✕✕✕✕✕
✕
1 1 0 0
1 0 0 0
C8
1
2
DEY
(Y)←(Y)–1
✕✕✕✕✕
✕
1 0 0 0
1 0 0 0
88
1
2
MUL $ zz, X
M(S), (A)←(A)✕M(zz+(X))
(S)←(S)–1
✕✕✕✕✕✕✕✕
0 1 1 0
0 0 1 0
62
2
15
DIV
(A)←(M(zz+(X)+1), M(zz+(X))÷(A)
M(S)←One’s complement of remainder
(S)←(S)–1
✕✕✕✕✕✕✕✕
1 1 1 0
0 0 1 0
E2
2
16
$ zz, X
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 179 of 185
NOTE
1 1 0 0
0
<B2>
1 1 0 1
0
<B2>
1 1 0 0
1
<B2>
<B3>
1 1 0 1
1
<B2>
<B3>
740 Family Machine Language Instruction Table
Parameter
SYMBOL
FUNCTION
∨
✕✕✕✕✕
✕
where
M=(zz)
✕✕✕✕✕
✕
∨
where
M=(zz+(X))
✕✕✕✕✕
✕
∨
where
M=(hhII)
✕✕✕✕✕
✕
∨
where
M=(hhII+(X))
✕✕✕✕✕
✕
∨
where
M=(hhII+(Y))
✕✕✕✕✕
✕
∨
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕
✕
∨
Operation
INSTRUCTION CODE
FLAG
N V T B D I Z C
∨
Logic Operation
Classification
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕
✕
✕✕✕✕✕
✕
(A)←(A)∨(M)
where
M=(zz)
✕✕✕✕✕
✕
ORA $ zz, X
(A)←(A)∨(M)
where
M=(zz+(X))
✕✕✕✕✕
✕
ORA $ hhII
(A)←(A)∨(M)
where
M=(hhII)
✕✕✕✕✕
✕
ORA $ hhII, X
(A)←(A)∨(M)
where
M=(hhII+(X))
✕✕✕✕✕
✕
ORA $ hhII, Y
(A)←(A)∨(M)
where
M=(hhII+(Y))
✕✕✕✕✕
✕
ORA ($ zz, X)
(A)←(A)∨(M)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕
✕
ORA ($ zz), Y
(A)←(A)∨(M)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕
✕
AND # $ nn
(A)←(A) nn
AND $ zz
(A)←(A) (M)
AND $ zz, X
(A)←(A) (M)
AND $ hhII
(A)←(A) (M)
AND $ hhII, X
(A)←(A) (M)
AND $ hhII, Y
(A)←(A) (M)
AND ($ zz, X)
(A)←(A) (M)
AND ($ zz), Y
(A)←(A) (M)
ORA # $ nn
(A)←(A)∨nn
ORA $ zz
EOR # $ nn
(A)←(A)∀nn
✕✕✕✕✕
✕
EOR $ zz
(A)←(A)∀(M)
where
M=(zz)
✕✕✕✕✕
✕
EOR $ zz, X
(A)←(A)∀(M)
where
M=(zz+(X))
✕✕✕✕✕
✕
D7D6D5D4
D3D2D1D0
0 0 1 0
1
<B2>
0 0 1 0
0
<B2>
0 0 1 1
0
<B2>
0 0 1 0
1
<B2>
<B3>
0 0 1 1
1
<B2>
<B3>
0 0 1 1
1
<B2>
<B3>
0 0 1 0
0
<B2>
0 0 1 1
0
<B2>
HEX
BYTE
CYCLE
NOTE
NUMBER NUMBER
0 0 1
29
2
2
1
1 0 1
25
2
3
1
1 0 1
35
2
4
1
1 0 1
2D
3
4
1
1 0 1
3D
3
5
1
0 0 1
39
3
5
1
0 0 1
21
2
6
1
0 0 1
31
2
6
1
0 1
09
2
2
1
0 1
05
2
3
1
0 1
15
2
4
1
0 1
0D
3
4
1
0 1
1D
3
5
1
0 1
19
3
5
1
0 1
01
2
6
1
0 1
11
2
6
1
0 1 0 0
1 0 0 1
<B2>
0 1 0 0
0 1 0 1
<B2>
0 1 0 1
0 1 0 1
<B2>
0 1 0 0 1 1 0 1
<B2>
<B3>
0 1 0 1 1 1 0 1
<B2>
<B3>
0 1 0 1 1 0 0 1
<B2>
<B3>
0 1 0 0 0 0 0 1
<B2>
0 1 0 1 0 0 0 1
<B2>
49
2
2
1
45
2
3
1
55
2
4
1
4D
3
4
1
5D
3
5
1
59
3
5
1
41
2
6
1
51
2
6
1
44
2
5
0 0 0 0 1 0
<B2>
0 0 0 0 0 1
<B<B2>2>
0 0 0 1 0 1
<B2>
0 0 0 0 1 1
<B2>
<B3>
0 0 0 1 1 1
<B2>
<B3>
0 0 0 1 1 0
<B2>
<B3>
0 0 0 0 0 0
<B2>
0 0 0 1 0 0
<B2>
EOR $ hhII
(A)←(A)∀(M)
where
M=(hhII)
✕✕✕✕✕
✕
EOR $ hhII, X
(A)←(A)∀(M)
where
M=(hhII+(X))
✕✕✕✕✕
✕
EOR $ hhII, Y
(A)←(A)∀(M)
where
M=(hhII+(Y))
✕✕✕✕✕
✕
EOR ($ zz, X)
(A)←(A)∀(M)
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕
✕
EOR ($ zz), Y
(A)←(A)∀(M)
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕
✕
where
M=(zz)
✕✕✕✕✕
✕
0 1 0 0 0 1 0 0
<B2>
_____
COM $ zz
(M)←(M)
BIT
$ zz
(A)
BIT
$ hhll
(A)
where
M=(zz)
M7M6✕ ✕ ✕ ✕
✕
∨
(M)
where
M=(hhII)
M7M6✕ ✕ ✕ ✕
✕
0 0 1 0 0 1 0 0
<B2>
0 0 1 0 1 1 0 0
<B2>
<B3>
where
M=(zz)
✕✕✕✕✕
✕
(M)=0?
CMP $ zz
(A)–(M)
CMP $ zz, X
(A)–(M)
CMP $ hhII
(A)–(M)
CMP $ hhII, X
(A)–(M)
CMP $ hhII, Y
(A)–(M)
CMP ($ zz, X)
(A)–(M)
CMP ($ zz), Y
(A)–(M)
CPX # $ nn
(X)–nn
CPX $ zz
(X)–(M)
CPX $ hhII
(X)–(M)
CPY # $ nn
(Y)–nn
CPY $ zz
(Y)–(M)
CPY $ hhII
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
(Y)–(M)















✕✕✕✕✕
Comparison in size
(A)–nn










where
M=(zz)
✕✕✕✕✕
where
M=(zz+(X))
✕✕✕✕✕
where
M=(hhII)
✕✕✕✕✕
where
M=(hhII+(X))
✕✕✕✕✕
where
M=(hhII+(Y))
✕✕✕✕✕
where
M=((zz+(X)+1)(zz+(X)))
✕✕✕✕✕
where
M=((zz+1)(zz)+(Y))
✕✕✕✕✕
Comparison
in size
CMP # $ nn
where
M=(zz)
✕✕✕✕✕
where
M=(hhII)
✕✕✕✕✕
Comparison
in size
Comparison
∨
TST $ zz
(M)
where
M=(zz)
✕✕✕✕✕
M=(hhII)
✕✕✕✕✕
✕✕✕✕✕
✕✕✕✕✕
where
page 180 of 185
24
2
3
2C
3
4
0 1 1 0 0 1 0 0
<B2>
64
2
3
1 1 0 0 1
<B2>
1 1 0 0 0
<B2>
1 1 0 1 0
<B2>
1 1 0 0 1
<B2>
<B3>
1 1 0 1 1
<B2>
<B3>
1 1 0 1 1
<B2>
<B3>
1 1 0 0 0
<B2>
1 1 0 1 0
<B2>
0 0 1
C9
2
2
3
1 0 1
C5
2
3
3
1 0 1
D5
2
4
3
1 0 1
CD
3
4
3
1 0 1
DD
3
5
3
0 0 1
D9
3
5
3
0 0 1
C1
2
6
3
0 0 1
D1
2
6
3
1 1 1 0 0 0 0 0
<B2>
1 1 1 0 0 1 0 0
<B2>
1 1 1 0 1 1 0 0
<B2>
<B3>
E0
2
2
E4
2
3
EC
3
4
C0
2
2
C4
2
3
CC
3
4
1 1 0 0 0 0 0 0
<B2>
1 1 0 0 0 1 0 0
<B2>
1 1 0 0 1 1 0 0
<B2>
<B3>
740 Family Machine Language Instruction Table
Parameter
Classification
SYMBOL
ASL A
ASL $ zz
ASL $ zz, X
ASL $ hhII
ASL $ hhII, X
LSR A
LSR $ zz
LSR $ zz, X
LSR $ hhII
Operation
Rotate and Shift
LSR $ hhII, X
ROL
A
ROL $ zz
ROL $ zz, X
ROL $ hhII
ROL $ hhII, X
ROR
A
ROR $ zz
ROR $ zz, X
ROR $ hhII
ROR $ hhII, X
FLAG
FUNCTION
N V T B D I Z C








Left Shift C ←A7A6
A 1A0 ← 0
where
M=(zz)








Right Shift 0 → A7A6
A 1A0 → C
where
M=(zz)
where
M=(zz+(X))
Right Shift 0 → M7M6
M 1 M0 → C
where
M=(hhII)








Left Shift ← A7A6








Right Shift → C → A7 A6
where
Left Shift
C ← M7 M 6
✕✕✕✕✕
✕✕✕✕✕
M=(zz+(X))
M1 M0 ← 0 where M=(hhII)
where
M=(hhII+(X))
where
M=(hhII+(X))
A 1A0 ← C ←
0 0 0 0
0 0 0 0
1 0 1 0
0 1 1 0
0A
06
1
2
2
5
0 1 1 0
16
2
6
1 1 1 0
0E
3
6
0 0 0 1
<B2>
✕✕✕✕✕
CYCLE
HEX
<B2>
✕✕✕✕✕
BYTE
NUMBER NUMBER
D 3D 2D 1 D 0
0 0 0 0
<B2>
<B3>
0 0 0 1
1 1 0
1E
3
7
0✕✕✕✕✕
0✕✕✕✕✕
0 1 0
0 1 0
0 1 0
1 1 0
4A
46
1
2
2
5
0✕✕✕✕✕
0 1 0
1 1 0
56
2
6
0✕✕✕✕✕
0 1 0
1 1 0
4E
3
6
0✕✕✕✕✕
0 1 0
1 1 0
5E
3
7
✕✕✕✕✕
0 0 1
✕✕✕✕✕
0 0 1 0
✕✕✕✕✕
0 0 1 1
✕✕✕✕✕
0 0 1 0
✕✕✕✕✕
0 0 1 1
✕✕✕✕✕
1
<B2>
<B3>
0
1
0
0
<B2>
1
0
<B2>
0
1
<B2>
<B3>
1
1
<B2>
<B2>
0
1
0 1 0
2A
1
2
0 1 1 0
26
2
5
0 1 1 0
36
2
6
1 1 1 0
2E
3
6
3E
3
7
✕✕✕✕✕
1 1 1 0
<B2>
<B3>
0 1 1 0
1 0 1 0
6A
1
2
✕✕✕✕✕
0 1 1 0
0 1 1 0
66
2
5
M=(zz+(X))
M 1M 0 →
✕✕✕✕✕
0 1 1 1
0 1 1 0
76
2
6
M=(hhII)
✕✕✕✕✕
0 1 1 0
1 1 1 0
6E
3
6
✕✕✕✕✕
0 1 1 1
1 1 1 0
7E
3
7
0 0 1 0
82
2
8
1 0 1 1
(1+2i)✕10
+B
(1+2i)✕10
+F
1
2
2
5
2i✕10
+B
2i✕10
+F
1
2
2
5
18
1
2
where
M=(zz)
where
M(zz+(X))
Left Shift ← M7M6
M 1 M0 ← C ←
where
M(hhII)
where
M(hhII+(X))
A1 A 0 →
where
where
Right Shift → C → M7M6
INSTRUCTION CODE
D 7 D 6D 5 D 4
M=(zz)
where
where
M=(hhll+(X))
<B2>
<B2>
<B2>
<B3>
<B2>
<B2>
<B2>
<B3>
<B2>
<B2>
↑
M7
Flag setting
Bit
Management
RRF $ zz
M4 M3
M0
↑
where
M=(zz)
✕✕✕✕✕✕✕✕
1 0 0 0
<B2>
CLB
i, A
(Ai) ← 0
where
i=0—7
✕✕✕✕✕✕✕✕
i i i 1
CLB
i, $ zz
(Mi) ← 0
where
i=0—7, M=(zz)
✕✕✕✕✕✕✕✕
i i i 1
1 1 1 1
<B2>
i i i 0
1 0 1 1
i i i 0
SEB
i, A
(Ai) ←1
where
i=0—7
✕✕✕✕✕✕✕✕
SEB
i, $ zz
(Mi) ← 1
where
i=0—7, M=(zz)
✕✕✕✕✕✕✕✕
1 1 1 1
<B2>
CLC
(C) ← 0
✕✕✕✕✕✕✕0
0 0 0 1
1 0 0 0
SEC
(C) ← 1
✕✕✕✕✕✕✕1
0 0 1 1
1 0 0 0
38
1
2
CLD
(D) ← 0
✕✕✕✕0✕✕✕
1 1 0 1
1 0 0 0
D8
1
2
SED
(D) ← 1
✕✕✕✕1✕✕✕
1 1 1 1
1 0 0 0
F8
1
2
CLI
(I) ← 0
✕✕✕✕✕0✕✕
0 1 0 1
1 0 0 0
58
1
2
SEI
(I) ← 1
✕✕✕✕✕1✕✕
0 1 1 1
1 0 0 0
78
1
2
CLT
(T) ← 0
✕✕0✕✕✕✕✕
0 0 0 1
0 0 1 0
12
1
2
SET
(T) ← 1
✕✕1✕✕✕✕✕
0 0 1 1
0 0 1 0
32
1
2
CLV
(V) ← 0
✕0✕✕✕✕✕✕
1 0 1 1
1 0 0 0
B8
1
2
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 181 of 185
NOTE
740 Family Machine Language Instruction Table
Parameter
Jump
Classification
SYMBOL
FLAG
FUNCTION
INSTRUCTION CODE
N V T B D I Z C
D 7 D 6D 5D 4
1 0 0 0
0
<B2>
0 1 0 0
1
<B2>
<B3>
0 1 1 0
1
<B2>
<B3>
1 0 1 1
0
<B2>
0 0 1 0
0
<B2>
<B3>
0 0 0 0
0
<B2>
BRA $ hhII
(PC) ← (PC)+2+Rel
✕✕✕✕✕✕✕✕
JMP $ hhII
(PC) ← hhII
✕✕✕✕✕✕✕✕
JMP
($ hhII)
(PCL ) ← (hhII), (PCH) ← (hhII+1)
✕✕✕✕✕✕✕✕
JMP
($ zz)
D3D2D1D0
HEX
BYTE
CYCLE
NUMBER NUMBER
NOTE
0 0 0
80
2
4
1 0 0
4C
3
3
4
1 0 0
6C
3
5
0 1 0
B2
2
4
0 0 0
20
3
6
0 1 0
02
2
7
0 0 1 0
0 0 1 0
<B2>
22
2
5
0 0 1 1
<B2>
(1+2i)x10
+3
2
4
4
0 1 1 1
<B2>
<B3>
i i i 0
0 0 1 1
<B2>
(1+2i)x10
+7
3
5
4
2ix10
+3
2
4
4
2ix10
+7
3
5
4
✕✕✕✕✕✕✕✕
(M(S))←(PC H), (S)←(S) –1, (M(S)) ← (PC L),
(S)←(S) –1, and (PC)←hhII
✕✕✕✕✕✕✕✕
JSR
(M(S))←(PC H), (S)←(S) –1, (M(S))←(PC L),
(S)←(S) –1, (PCL)←(zz), and (PCH)←(zz+1)
✕✕✕✕✕✕✕✕
JSR \ $ hhII
(M(S))←(PCH ), (S)←(S) –1, (M(S))←(PC L ),
(S)←(S)–1, (PCL)←II, and (PCH )←FF
✕✕✕✕✕✕✕✕
BBC
i, A, $ hhII
When (Ai)=0
When (Ai)=1
(PC) ←(PC)+2+Rel
(PC) ← (PC)+2
Where
i=0—7
✕✕✕✕✕✕✕✕
i i i 1
BBC
i, $ zz, $ hhII
When (Mi)=0
When (Mi)=1
(PC) ← (PC)+3+Rel
(PC) ← (PC)+3
Where
i=0—7
✕✕✕✕✕✕✕✕
i i i 1
BBS
i, A, $ hhII
When (Ai)=1
When (Ai)=0
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
Where
i=0—7
✕✕✕✕✕✕✕✕
BBS
i, $ zz, $ hhII
When (Mi)=1
When (Mi)=0
(PC) ← (PC)+3+Rel
(PC) ← (PC)+3
Where
i=0—7
✕✕✕✕✕✕✕✕
BCC $ hhII
When (C)=0
When (C)=1
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
1 0 0 1
0 0 0 0
<B2>
90
2
2
4
BCS $ hhII
When (C)=1
When (C)=0
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
1 0 1 1
0 0 0 0
<B2>
B0
2
2
4
BNE $ hhII
When (Z)=0
When (Z)=1
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
1 1 0 1
0 0 0 0
<B2>
D0
2
2
4
BEQ $ hhII
When (Z)=1
When (Z)=0
(PC) ←(PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
1 1 1 1
0 0 0 0
<B2>
F0
2
2
4
BPL $ hhII
When (N)=0
When (N)=1
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
0 0 0 1
0 0 0 0
<B2>
10
2
2
4
BMI
$ hhII
When (N)=1
When (N)=0
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
0 0 1 1
0 0 0 0
<B2>
30
2
2
4
BVC $ hhII
When (V)=0
When (V)=1
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
0 1 0 1
0 0 0 0
<B2>
50
2
2
4
BVS $ hhII
When (V)=1
When (V)=0
(PC) ← (PC)+2+Rel
(PC) ← (PC)+2
✕✕✕✕✕✕✕✕
0 1 1 1
0 0 0 0
<B2>
70
2
2
4
RTI
(S)←(S)+1, (PS)←(M(S)), (S)←(S)+1, (PCL)←(M(S)),
(S)←(S)+1, and (PCH )←(M(S))
Previous status in
stack
0 1 0 0
0 0 0 0
40
1
6
RTS
(S)←(S)+1, (PCL)←(M(S)), (S)←(S)+1, (PCH)←(M(S)),
and (PC)←(PC)+1
✕✕✕✕✕✕✕✕
0 1 1 0
0 0 0 0
60
1
6
Interrupt
BRK
(B)←1, (PC)←(PC)+2, (M(S))←(PCH), (S)←(S)–1, (M(S))←(PCL),
(S)←(S)–1, (M(S))←(PS), (S)←(S)–1, (I)←1, (PC)←BADRS
✕✕✕1✕1✕✕
0 0 0 0
0 0 0 0
00
1
7
Other
NOP
(PC) ← (PC)+1
✕✕✕✕✕✕✕✕
1 1 1 0
1 0 1 0
EA
1
2
Special
WIT
Internal clock source is stopped.
✕✕✕✕✕✕✕✕
1 1 0 0
0 0 1 0
C2
1
2
STP
Oscillation is stopped.
✕✕✕✕✕✕✕✕
0 1 0 0
0 0 1 0
42
1
2
Return
Branch
Branch and Return
(PCL ) ←(zz), (PCH ) ← (zz+1)
JSR $ hhII
($ zz)
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 182 of 185
i i i 0
0 1 1 1
<B2>
<B3>
5
740 Family Machine Language Instruction Table
A
Ai
X
Y
M
Mi
PS
S
PC
PCL
PCH
N
V
T
B
D
I
Z
C
#
$
Means
Accumulator
Bit i of accumulator
Index register X
Index register Y
Memory
Bit i of memory
Processor status register
Stack Pointer
Program counter
Low-order byte of program counter
High-order byte of program counter
Negative flag
Overflow flag
X modified operation mode flag
Break flag
Decimal mode flag
Interrupt disable flag
Zero flag
Carry flag
Immediate mode
Hexadecimal
Special page mode
Symbol
hh
II
zz
nn
i
iii
<B2>
<B3>
Rel
BADRS
←
( )
+
*
÷
∨
∨
Symbol
∀
✕
Notes 1: Listed function is when (T) = 0.
When (T) = 1, (M(X)) is entered instead of (A) and the cycle number is increased by 3.
2: Ditto. The cycle number is increased by 2.
3: Ditto. The cycle number is increased by 1.
4: The cycle number is increased by 2 when a branch is occurred.
5: If the STP instruction is disabled the cycle number will be 2 (same in operation as two NOPs).
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 183 of 185
Means
High-order byte of address (0—255)
Low-order byte of address (0—255)
Zero page address (0—255)
Date at (0—255)
Data at (0—7)
Data at (0—7)
Second byte of instruction
Third byte of instruction
Relative address
Break address
Direction of data transfer
Contents of register of memory
Add
Subtract
Multiplication
Division
Logical OR
Logical AND
Logical Exclusive OR
Negative
Stable flag after execution
Variable flag after execution
APPENDIX 3
740 Family Iist of Instruction Codes
APPENDIX 3. 740 Family Iist of Instruction Codes
D7 – D4
D3 – D0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Hexadecimal
notation
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
ORA
ABS
ASL
ABS
SEB
0, ZP
0000
0
BRK
ORA
JSR
IND, X ZP, IND
BBS
0, A
—
ORA
ZP
ASL
ZP
BBS
0, ZP
PHP
ORA
IMM
ASL
A
SEB
0, A
—
0001
1
BPL
ORA
IND, Y
CLT
BBC
0, A
—
ORA
ZP, X
ASL
ZP, X
BBC
0, ZP
CLC
ORA
ABS, Y
DEC
A
CLB
0, A
—
0010
2
JSR
ABS
AND
IND, X
JSR
SP
BBS
1, A
BIT
ZP
AND
ZP
ROL
ZP
BBS
1, ZP
PLP
AND
IMM
ROL
A
SEB
1, A
BIT
ABS
0011
3
BMI
AND
IND, Y
SET
BBC
1, A
—
AND
ZP, X
ROL
ZP, X
BBC
1, ZP
SEC
AND
ABS, Y
INC
A
CLB
1, A
LDM
ZP
0100
4
RTI
STP
EOR
IND, X (Note)
BBS
2, A
COM
ZP
EOR
ZP
LSR
ZP
BBS
2, ZP
PHA
EOR
IMM
LSR
A
SEB
2, A
JMP
ABS
0101
5
BVC
EOR
IND, Y
—
BBC
2, A
—
EOR
ZP, X
LSR
ZP, X
BBC
2, ZP
CLI
EOR
ABS, Y
—
CLB
2, A
—
0110
6
RTS
ADC
IND, X
MUL
ZP, X
(Note)
BBS
3, A
TST
ZP
ADC
ZP
ROR
ZP
BBS
3, ZP
PLA
ADC
IMM
ROR
A
SEB
3, A
JMP
IND
0111
7
BVS
ADC
IND, Y
—
BBC
3, A
—
ADC
ZP, X
ROR
ZP, X
BBC
3, ZP
SEI
ADC
ABS, Y
—
CLB
3, A
—
1000
8
BRA
STA
IND, X
RRF
ZP
BBS
4, A
STY
ZP
STA
ZP
STX
ZP
BBS
4, ZP
DEY
—
TXA
SEB
4, A
STY
ABS
STA
ABS
STX
ABS
SEB
4, ZP
1001
9
BCC
STA
IND, Y
—
BBC
4, A
STY
ZP, X
STA
ZP, X
STX
ZP, Y
BBC
4, ZP
TYA
STA
ABS, Y
TXS
CLB
4, A
—
STA
ABS, X
—
CLB
4, ZP
1010
A
LDY
IMM
LDA
IND, X
LDX
IMM
BBS
5, A
LDY
ZP
LDA
ZP
LDX
ZP
BBS
5, ZP
TAY
LDA
IMM
TAX
SEB
5, A
LDY
ABS
LDA
ABS
LDX
ABS
SEB
5, ZP
1011
B
BCS
JMP
LDA
IND, Y ZP, IND
BBC
5, A
LDY
ZP, X
LDA
ZP, X
LDX
ZP, Y
BBC
5, ZP
CLV
LDA
ABS, Y
TSX
CLB
5, A
1100
C
CPY
IMM
CMP
IND, X
WIT
BBS
6, A
CPY
ZP
CMP
ZP
DEC
ZP
BBS
6, ZP
INY
CMP
IMM
DEX
SEB
6, A
CPY
ABS
1101
D
BNE
CMP
IND, Y
—
BBC
6, A
—
CMP
ZP, X
DEC
ZP, X
BBC
6, ZP
CLD
CMP
ABS, Y
—
CLB
6, A
—
1110
E
CPX
IMM
SBC
IND, X
DIV
ZP, X
(Note)
BBS
7, A
CPX
ZP
SBC
ZP
INC
ZP
BBS
7, ZP
INX
SBC
IMM
NOP
SEB
7, A
CPX
ABS
1111
F
BEQ
SBC
IND, Y
—
BBC
7, A
—
SBC
ZP, X
INC
ZP, X
BBC
7, ZP
SED
SBC
ABS, Y
—
CLB
7, A
—
CLB
ASL
ORA
ABS, X ABS, X 0, ZP
AND
ABS
ROL
ABS
SEB
1, ZP
CLB
ROL
AND
ABS, X ABS, X 1, ZP
EOR
ABS
LSR
ABS
SEB
2, ZP
CLB
LSR
EOR
ABS, X ABS, X 2, ZP
ADC
ABS
ROR
ABS
SEB
3, ZP
CLB
ROR
ADC
ABS, X ABS, X 3, ZP
CLB
LDX
LDY
LDA
ABS, X ABS, X ABS, Y 5, ZP
CMP
ABS
DEC
ABS
SEB
6, ZP
CLB
DEC
CMP
ABS, X ABS, X 6, ZP
SBC
ABS
INC
ABS
SEB
7, ZP
CLB
INC
SBC
ABS, X ABS, X 7, ZP
Note: Some products unuse these instructions.
3-byte instruction
2-byte instruction
1-byte instruction
Refer to the related section
because the clock control instruction and
multiplication and division instruction
depend on products.
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 184 of 185
740 Family Iist of Instruction Codes
MEMORANDUM
Rev.2.00 Nov 14, 2006
REJ09B0322-0200
page 185 of 185
740 Family Software Manual
Publication Data :
Rev.1.00 Aug 29, 1997
Rev.2.00 Nov 14, 2006
Published by : Sales Strategic Planning Div.
Renesas Technology Corp.
© 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
740 Family
Software Manual
1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan
REJ09B0322-0200