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FM482 user manual V1.3 FM482 User Manual 4DSP Inc. 955 S Virginia Street, Suite 214, Reno, NV 89502, USA Email: [email protected] This document is the property of 4DSP Inc. and may not be copied nor communicated to a third party without the written permission of 4DSP Inc. © 4DSP Inc. 2007 FM482 user manual V1.3 Revision History Date Revision Version 02-01-07 First release 1.0 02-23-07 Updated Pn4 pin allocation table 1.1 03-14-07 Updated clock tree diagram 1.2 04-26-07 Corrected typos 1.3 April 2007 FM482 User manual www.4dsp.com -2- FM482 user manual V1.3 Table of Contents 1 2 3 4 5 6 7 8 9 Acronyms and related documents ............................................................................. 4 1.1 Acronyms............................................................................................................... 4 1.2 Related Documents ............................................................................................... 4 1.3 General description................................................................................................ 5 Installation ................................................................................................................... 6 2.1 Requirements and handling instructions ................................................................ 6 2.2 Firmware and software........................................................................................... 6 Design .......................................................................................................................... 6 3.1 FPGA devices ........................................................................................................ 6 3.1.1 Virtex-4 device A ............................................................................................ 6 3.1.2 Virtex-4 device B ............................................................................................ 9 3.2 FPGA devices configuration..................................................................................10 3.2.1 Flash storage ................................................................................................10 3.2.2 CPLD device .................................................................................................10 3.2.3 JTAG.............................................................................................................12 3.3 Clock tree..............................................................................................................13 3.4 Memory resources ................................................................................................13 3.4.1 QDR2 SRAM.................................................................................................13 3.4.2 DDR2 SDRAM ..............................................................................................13 3.5 Front Panel IO daughter card................................................................................14 3.5.1 Virtex-4 device B to I/O front Panel daughter card.........................................14 3.5.2 Power connection to the front panel I/O daughter card..................................16 3.6 Front Panel optical transceivers ............................................................................17 Power requirements ...................................................................................................18 4.1 External power connector for stand alone mode ...................................................19 Environment................................................................................................................20 5.1 Temperature .........................................................................................................20 5.2 Convection cooling................................................................................................20 5.3 Conduction cooling ...............................................................................................20 Safety...........................................................................................................................20 EMC .............................................................................................................................20 Warranty......................................................................................................................20 FM482 picture .............................................................................................................21 April 2007 FM482 User manual www.4dsp.com -3- FM482 user manual V1.3 1 Acronyms and related documents 1.1 Acronyms ADC DAC DCI DDR DSP EPROM FBGA FPDP FPGA JTAG LED LVTTL LVDS LSB LVDS MGT MSB PCB PCI PCI-e PLL PMC QDR SDRAM SRAM Analog to Digital Converter Digital to Analog Converter Digitally Controlled Impedance Double Data Rate Digital Signal Processing Erasable Programmable Read-Only Memory Fineline Ball Grid Array Front Panel Data Port Field Programmable Gate Array Join Test Action Group Light Emitting Diode Low Voltage Transistor Logic level Low Differential Data Signaling Least Significant Bit(s) Low Voltage Differential Signaling Multi-Gigabit Transceiver Most Significant Bit(s) Printed Circuit Board Peripheral Component Interconnect PCI Express Phase Locked Loop PCI Mezzanine Card Quadruple Data rate Synchronous Dynamic Random Access memory Synchronous Random Access memory Table 1: Glossary 1.2 Related Documents IEEE Std 1386.1-2001 : IEEE Standard Physical and Environmental Layers for PCI Mezzanine Cards (PMC). ANSI/VITA 39-2003 : PCI-X for PMC and Processor PMC. ANSI/VITA 20-2001 : Conduction Cooled PMC. ANSI/VITA 42.0-2005 : XMC Switched Mezzanine Card Auxiliary Standard. IEEE Std 1386-2001 : IEEE Standard for a Common Mezzanine Card (CMC) Family. Xilinx Virtex-4 user guide Xilinx PCI-X core datasheet Xilinx Virtex-4 Rocket I/O guide April 2007 FM482 User manual www.4dsp.com -4- FM482 user manual 1.3 V1.3 General description The FM482 is a high performance PMC/XMC dedicated to digital signal processing applications with high bandwidth and complex algorithms requirements. The FM482 can interface to a PCI-e, PCI-X and/or PCI bus. It offers various interfaces, fast on-board memory resources and one Virtex-4 FPGA. It can be utilized, for example, to accelerate frequencydomain algorithms with off-the-shelf Intellectual Property cores for applications that require the highest level of performances. The FM482 is mechanically and electrically compliant to the standard and specifications listed in section 1.2 of this document. Figure 1: FM482 block diagram April 2007 FM482 User manual www.4dsp.com -5- FM482 user manual V1.3 2 Installation 2.1 Requirements and handling instructions The FM482 must be installed on a motherboard compliant to the IEEE Std 1386-2001 standard for 3.3V PMC or on a motherboard compliant to the XMC Switched Mezzanine Card Auxiliary Standard Do not flex the board Observe SSD precautions when handling the board to prevent electrostatic discharges. Do not install the FM482 while the motherboard is powered up. 2.2 Firmware and software Drivers, API libraries and a program example working in combination with a pre-programmed firmware for both FPGAs are provided. The FM482 is delivered with an interface to the Xilinx PCI core in the Virtex-4 device A and an example VHDL design in the Virtex-4 device B so users can start performing high bandwidth data transfers over the PCI bus right out of the box. For more information about software installation and FPGA firmware, please refer the FM482 Get Started Guide. 3 Design 3.1 FPGA devices The Virtex-4 FPGA devices interface to the various resources on the FM482 as shown on Figure 1. They also interconnect to each other via 86 general purpose pins and 2 clock pins. 3.1.1 3.1.1.1 Virtex-4 device A Virtex-4 device A family and package The Virtex-4 device A is from the Virtex-4 FX family. It can be either an XC4VFX20 or XC4VFX60 in a Fineline Ball Grid array with 672 balls (FF672). 3.1.1.2 Power PC embedded processor Up to two IBM PowerPC RISC processor cores are available in the Virtex-4 device A. This core can be used to execute C based algorithms and control the logic resources implemented in the FPGA. 3.1.1.3 Virtex-4 device A external memory interfaces The Virtex-4 device A is connected to a 128Mbytes SDRAM bank with a 32-bit data bus width. This memory resource can be used by the PowerPC core or can serve as data buffer. April 2007 FM482 User manual www.4dsp.com -6- FM482 user manual 3.1.1.4 V1.3 PCI interface The Virtex-4 device A interfaces directly to the PCI bus via the PMC Pn1, Pn2 and Pn3 connectors or to the PCI-e bus via the Pn5. An embedded PCI core from Xilinx is used to communicate over the PCI bus with the host system on the motherboard. PCI-e 4 lanes, PCIX 64-bit 66MHz/133MHz, PCI 64-bit 66MHz and PCI 32-bit 33MHz are supported on the FM482. The bus type must be communicated at the time of the order so the right Virtex-4 device A firmware can be loaded into the flash prior to delivery. The following performances have been recorded with the FM482 transferring data on the bus: PCI-X 64-bit 133MHz: 750Mbytes/s sustained PCI-X 64-bit 66MHz: 450Mbytes/s sustained PCI 32-bit 33MHz: 120Mbytes/s sustained The PCI-express is using the MGT I/Os on the Virtex-4 device A. Power filtering, low jitter clock and special routing are used to achieve the performances required by this standard. Please refer to the Front Panel Optical transceivers section of this document for more details (3.6). 3.1.1.5 LED Four LEDs are connected to the Virtex-4 device A. In the default FPGA firmware, the LEDs are driven by the Virtex-4 device B via the Virtex-4 device A/ Virtex-4 device B interface. The LEDs are located on side 2 of the PCB in the front panel area. Figure 2: FPGA LED locations April 2007 FM482 User manual www.4dsp.com -7- FM482 user manual 3.1.1.6 V1.3 Pn4 user I/O connector The Pn4 connector is wired to the Virtex-4 device A. The 32 lower bits are available only if an XC4VFX60 device is mounted on board. The 32 higher bits are available only if PCI 32-bit is used and only if specified at the time of order. All signals are user-defined 3.3V LVTLL./LVCMOS. Connector pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 Signal name Pn4_IO0 Pn4_IO2 Pn4_IO4 Pn4_IO6 Pn4_IO8 Pn4_IO10 Pn4_IO12 Pn4_IO14 Pn4_IO16 Pn4_IO18 Pn4_IO20 Pn4_IO22 Pn4_IO24 Pn4_IO26 Pn4_IO28 Pn4_IO30 Pn4_IO32 Pn4_IO34 Pn4_IO36 Pn4_IO38 Pn4_IO40 Pn4_IO42 Pn4_IO44 Pn4_IO46 Pn4_IO48 Pn4_IO50 Pn4_IO52 Pn4_IO54 Pn4_IO56 Pn4_IO58 Pn4_IO60 Pn4_IO62 FPGA pin M9 N11 N7 N6 P10 P9 R8 R6 N21 M20 P19 N18 P16 R18 P21 R17 L9 L5 AD10 L3 AC11 N4 T8 R5 AB10 R3 Y10 P3 U5 T3 V6 V4 FPGA pin M10 M11 N8 P6 P11 N9 P8 R7 M21 M19 N19 N17 N16 P18 P20 R16 M5 AD11 L4 AB11 M4 T9 P5 AA10 P4 W10 N3 U6 T4 U7 U4 U9 Signal name Pn4_IO1 Pn4_IO3 Pn4_IO5 Pn4_IO7 Pn4_IO9 Pn4_IO11 Pn4_IO13 Pn4_IO15 Pn4_IO17 Pn4_IO19 Pn4_IO21 Pn4_IO23 Pn4_IO25 Pn4_IO27 Pn4_IO29 Pn4_IO31 Pn4_IO33 Pn4_IO35 Pn4_IO37 Pn4_IO39 Pn4_IO41 Pn4_IO43 Pn4_IO45 Pn4_IO47 Pn4_IO49 Pn4_IO51 Pn4_IO53 Pn4_IO55 Pn4_IO57 Pn4_IO59 Pn4_IO61 Pn4_IO63 Connector pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 Table 2 : Pn4 pin assignment April 2007 FM482 User manual www.4dsp.com -8- FM482 user manual 3.1.2 3.1.2.1 V1.3 Virtex-4 device B Virtex-4 device B family and package The Virtex-4 device B is dedicated to Digital Signal Processing applications and can be chosen from the SX or LX family devices. Its package is based on Fineline Ball Grid array with 1148 balls. In terms of logic and dedicated DSP resources, the FPGA B can be chosen from the following types: SX55, LX40, LX60, LX80, LX100 and LX160. 3.1.2.2 Virtex-4 device B external memory interfaces The Virtex-4 device B interfaces to four 8Mbytes QDR2 SRAM devices with 32-bit data bus, Please note that the four QDR2 SRAM devices are only available with the LX80, LX100 and LX160 devices. For smaller Virtex-4 FPGAs (LX40, LX60 and SX55) only three QDR2 SRAM devices are connected to the FPGA. 3.1.2.3 Virtex-4 device B interface to Front Panel daughter card The Virtex-4 device B interfaces to the front panel daughter card on the FM482 via a high speed connector. 114 I/Os are available from the FPGA to/from the daughter card. Refer to the Front Panel I/O section of this document for more details about the daughter card connector electrical characteristics. April 2007 FM482 User manual www.4dsp.com -9- FM482 user manual 3.2 V1.3 FPGA devices configuration 3.2.1 Flash storage The FPGA firmware is stored on board in a flash device. The 128Mbit device is partly used to store the configuration for both FPGAs. In the default CPLD firmware configuration, the Virtex-4 devices A and B are directly configured from flash if a valid bitstream is stored in the flash for each FPGA. The flash is pre-programmed in factory with the default firmware example for both FPGAs. Figure 3 : Configuration circuit 3.2.2 CPLD device As shown on Figure 2, a CPLD is present on board to interface between the flash device and the FPGA devices. It is of type CoolRunner-II. The CPLD is used to program and read the flash. The data stored in the flash are transferred from the host motherboard via the PCI bus to the Virtex-4 device A and then to the CPLD that writes the required bit stream to the storage device. A 31.25 MHz clock connects to the CPLD and is used to generate the configuration clock sent to the FPGA devices. At power up, if the CPLD detects that an FPGA configuration bitstream is stored in the flash for both FPGA devices, it will start reading programming the devices in SelecMap mode. Do NOT reprogram the CPLD without 4DSP approval The CPLD configuration is achieved by loading with a Xilinx download cable a bitstream from a host computer via the JTAG connector. The FPGA devices configuration can also be performed using the JTAG. April 2007 FM482 User manual www.4dsp.com - 10 - FM482 user manual 3.2.2.1 V1.3 DIP Switch A switch (J1) is located next to the JTAG programming connector (J6) see Figure 4. The switch positions are defined as follows: Figure 4: switch (J1) location Sw1 OFF Default setting. The Virtex-4 device A configuration is loaded from the flash at power up. ON Virtex-4 device A safety configuration loaded from the flash at power up. To be used only if the Virtex-4 device A cannot be configured or does not perform properly with the switch in the OFF position. Sw2 Reserved Sw3 Reserved Sw4 Reserved Table 3: Switch description 3.2.2.2 LED and board status Four LEDs connect to the CPLD and give information about the board status. LED 0 LED 1 LED 2 LED 3 April 2007 Flashing FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA A not configured OFF FPGA A configured Flashing FPGA A or B bitstream or user_ROM_register is currently being written to the flash ON FPGA B not configured OFF FPGA B configured Flashing The Virtex-4 device A has been configured with the safety configuration bitstream programmed in the flash at factory. Please write a valid Virtex-4 device A bitstream to the flash. ON Flash is busy writing or erasing OFF Flash device is not busy ON CRC error. Presumably a wrong or corrupted FPGA bitstream FM482 User manual www.4dsp.com - 11 - FM482 user manual LED 3 V1.3 has been written to the flash. Once on this LED remains on OFF No CRC error detected Table 4: LED board status Figure 5: CPLD LED locations 3.2.3 JTAG A JTAG connector is available on the FM482 for configuration purposes. The JTAG can also be used to debug the FPGA design with the Xilinx Chipscope. The JTAG connector is located on side 1 of the PCB (see Figure 6). YFF WPV JQG WGL WFN WGR -7$*FRQQHFWRU Figure 6: JTAG connector (J6) location The JTAG connector pinout is as follows: Pin # 1 2 3 Signal 1.8V GND TCK Signal TMS TDI TDO Pin # 4 5 6 Table 5 : JTAG pin assignment April 2007 FM482 User manual www.4dsp.com - 12 - FM482 user manual 3.3 V1.3 Clock tree The FM482 clock architecture offers an efficient distribution of low jitter clocks. In addition to the PCI Express bus, the MGT reference clocks of 106.25MHz and 125MHz (Epson EG2121CA) make it possible to implement several standards over the MGT I/Os connected to the optical transceivers. Both FPGAs receive a low jitter 125MHz clock. A low jitter programmable clock able to generate frequencies from 62.5MHz to 255.5MHz in steps of 0.5MHz is also available. This clock management approach ensures maximum flexibility to efficiently implement multi-clock domains algorithms and use the memory devices at different frequencies. Both clock buffer devices (CDM1804) and the frequency synthesizer (ICS8430-61) are controlled by the Virtex-4 device A. Figure 7 : Clock tree 3.4 Memory resources 3.4.1 QDR2 SRAM Four independent QDR2 SRAM devices are connected to the Virtex-4 device B. The QDR2 SRAM devices available on the FM482 are 2M words deep (8Mbytes per memory device). Please note that only three QDR SRAM devices are available to the user if the XC4VLX40, XC4VLX60 or XC4VSX55 FPGA device is mounted on board. 3.4.2 DDR2 SDRAM Two 16-bit DDR2 SDRAM devices of 128MBytes each are connected to Virtex-4 device A. The two memories share the same address and control bus and have their own data bus. This memory resource can be accessed by the PowerPC processor in the Virtex-4 device A or can be used as a data buffer for custom user logic. April 2007 FM482 User manual www.4dsp.com - 13 - FM482 user manual 3.5 3.5.1 V1.3 Front Panel IO daughter card Virtex-4 device B to I/O front Panel daughter card (only available with daughter card purchase) The Virtex-4 device B interfaces to a 120-pin connector placed in the Front panel I/O area (on both side 1 and side 2 of the PCB). It serves as a base for a daughter card and offers I/O diversity to the FM482 PMC. On side 2 of the PCB, the connectors and mounting holes placement complies with the SLB standard except for the 1.5V mounting hole that is not present on this module. The FPGA I/O banks are powered either by 1.8V, 2.5V or 3.3V via a large 0 ohms resistor (3.3V is the default if not specified otherwise at the time of order). Using the Xilinx DCI termination options to match the signals impedance allows many electrical standards to be supported by this interface. All signals are routed as 100-ohm LVDS pairs. The VRP and VRN pins on the I/O banks connected to the daughter card connector are respectively pulled up and pulled down with 50-ohm resistors in order to ensure optimal performances when using the Xilinx DCI options. The VREF pins are connected to 0.9V for DDR2 DCI terminations. Please, contact 4DSP Inc. for more information about the daughter card types available. The 120-pin Samtec connector pin assignment is as follows. All signals are shown as LVDS pairs in the table but they can be used for any standard that does not breach the electrical rules of the Xilinx I/O pad. Connector pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 Signal Name FP_P0 FP_N0 (2) FP_P2 FP_N2(2) FP_P4 FP_N4 FP_P6 FP_N6 FP_P8 FP_N8 FP_P10(2) FP_N10(2) FP_P12 FP_N12 FP_P14 FP_N14 FPGA pin W24 Y24 AA25 AA26 AB30 AA30 AB22 AB23 AC29 AC30 AD34 AC34 AE29 AD29 AE33 AE34 FPGA pin AA23 AA24 AA28 AA29 AC28 AB28 AD27 AC27 AC32 AC33 AE32 AD32 AF31 AE31 AF33 AF34 (2) AF29 AH19 FP_P16 Signal name FP_P1 FP_N1 FP_P3 FP_N3 FP_P5 FP_N5 FP_P7 FP_N7 FP_P9 FP_N9 FP_P11 FP_N11 FP_P13 FP_N13 FP_P15 FP_N15 FP_P17 Connector pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 (1) 34 (1) 36 (2) AF30 AH18 (1) AG18 AG30 FP_P19 38 (1) AG17 AG31 FP_N19 40 FP_N16 FP_P18 FP_N18 FP_N17 Table 6 : Front Panel IO daughter card pin assignment Bank A (1) (2) Connected to a global clock pin on the FPGA. LVDS output not supported. Connected to a regional clock pin on the FPGA. LVDS output not supported. April 2007 FM482 User manual www.4dsp.com - 14 - FM482 user manual Connector pin 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 Differential FP_P20 FP_N20 FP_P22 FP_N22 FP_P24(2) FP_N24(2) FP_P26 FP_N26 FP_P28 FP_N28 FP_P30 FP_N30 FP_P32 FP_N32 FP_P34 FP_N34 (2) FP_P36 3.3V/2.5V/1.8V 3.3V/2.5V/1.8V 3.3V/2.5V/1.8V FP_P37 FP_N37 FP_P39 FP_N39 FP_P41 FP_N41 FP_P43 FP_N43 (1) FP_P45 (1) FP_N45 FP_P47 FP_N47 FP_P49 FP_N49 FP_P51 FP_N51 (2) FP_P53 (2) FP_N53 FP_P55(1) FP_N55(1) V1.3 FPGA pin AG32 AG33 AH32 AH33 AK31 AK32 AL33 AL34 AM32 AM33 AM30 AL30 AK29 AJ29 AP29 AN29 AG27 FPGA pin AJ34 AH34 AJ30 AH30 AK33 AK34 AM31 AL31 AP30 AN30 AH28 AH29 AL28 AL29 AN28 AM28 AG28 AF28 AE27 AM26 AM27 AP25 AP26 AG25 AG26 AJ17 AH17 AP24 AN24 AG23 AF24 AL23 AM23 AL24 AL25 AE17 AE16 AJ27 AH27 AP27 AN27 AL26 AK26 AF26 AE26 AN25 AM25 AK24 AJ24 AK22 AK23 AN22 AN23 AP21 AP22 AK21 AL21 Differential FP_P21 FP_N21 FP_P23 FP_N23 FP_P25 FP_N25 FP_P27 FP_N27 FP_P29 FP_N29 FP_P31 FP_N31 FP_P33 FP_N33 FP_P35(2) (2) FP_N35 (2) FP_N36 (3) Vbatt 0.9V 3.3V/2.5V/1.8V FP_P38 FP_N38 FP_P40 FP_N40 FP_P42 FP_N42 FP_P44 FP_N44 FP_P46 FP_N46 FP_P48 FP_N48 FP_P50 FP_N50 FP_P52 FP_N52 FP_P54 FP_N54 FP_P56 FP_N56 Connector pin 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 Table 7 : Front Panel IO daughter card pin assignment Bank B and C (1) (2) (3) Connected to a global clock pin on the FPGA. LVDS output not supported. Connected to a regional clock pin on the FPGA. LVDS output not supported. Vbatt is connected to both Virtex-4 devices Vbatt pin. April 2007 FM482 User manual www.4dsp.com - 15 - FM482 user manual V1.3 3.5.2 Power connection to the front panel I/O daughter card The Front Panel I/O daughter card on side 1 of the PCB is powered via a 7-pin connector of type BKS (Samtec). Each pin can carry up to 1.5A. The power connector’s pin assignment is as follows. Pin # 1 3 5 7 Signal +3.3V +5V +12V -12V Signal +3.3V GND GND Pin # 2 4 6 Table 8: Daughter card power connector pin assignment on PMC side 1 On side 2 of the PCB, the daughter card is powered via a 33-pin connector of type BKS (Samtec). Each pin can carry up to 1.5A. The power connector’s pin assignment is as follows. Pin # 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 Signal +3.3V +3.3V +3.3V +3.3V +5V +5V +5V +5V +12V +12V -12V -12V GND reserved reserved reserved GND Signal GND GND GND GND GND GND GND GND GND GND GND GND reserved reserved reserved reserved Pin # 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 Table 9: Daughter card power connector pin assignment on PMC side 2 April 2007 FM482 User manual www.4dsp.com - 16 - FM482 user manual 3.6 V1.3 Front Panel optical transceivers Four 2.5Gb/s optical transceivers (LTP-ST11M) are available on the FM482 in the front panel area. They are connected to the MGT I/Os of the Virtex-4 device A. Infiniband protocols as well as Gigabit Ethernet and Fibre channel (sFPDP) can be implemented over the transceivers. Lower rate optical transceivers (2.125Gb/s and 1.0625Gb/s) are available in the same form factor. Two low jitter clocks (106.25MHz and 125MHz) are directly connected to the MGT clock inputs so multi-rate applications can be implemented on the FM482. The MGT banks have power supplies independent from the digital supply provided to the FPGAs in order to insure low noise and data integrity. The LT1963 device will be used to generate the 1.2V, 1.5V and 2.5V necessary for the MGT to operate. The power filtering network includes a 220nF decoupling capacitor and ferrite bead (MP21608S221A) per power pin. The signal differential pairs are routed on a specific inner layer with one reference GND plane on each side of the layer stack up. Please note that the optical transceivers are not available if the FM482 is Conduction Cooled. Figure 8: Optical transceivers April 2007 FM482 User manual www.4dsp.com - 17 - FM482 user manual V1.3 4 Power requirements The Power is supplied to the FM482 via the PMC and/or XMC connectors. Several DC-DC converters generate the appropriate voltage rails for the different devices and interfaces present on board. The FM482 power consumption depends mainly on the FPGA devices work load. By using high efficiency power converters, all care has been taken to ensure that power consumption will remain as low as possible for any given algorithm. After power up the FM482 typically consumes 2W of power. For precise power measurements it is recommended to use the Xilinx power estimation tools for both FPGA A and B. The maximum current rating given in the table below is the maximum current that can be drawn from each voltage rail in the case resources are used to their maximum level. Device/Interface Voltage Maximum current rating 0.9V 5A Virtex-4 device A & B core 1.2V 12A QDR2, DDR2 SDRAM core and I/O banks, Virtex-4 devices I/O banks 1.8V 10A Virtex-4 device B I/O bank connected to the front panel daughter card 1.8V/2.5/3.3V 1.5A Virtex-4 device A I/O bank connected to the PCI bus, Flash, CPLD, front Panel I/O daughter card 3.3V 2A Front Panel IO daughter card 5V 1A Front Panel IO daughter card 12V 0.5A Front Panel IO daughter card -12V 0.5A 1.2V, 1.5V, 2.5V 1.7A, 0.5A, 0.01A respectively DCI and voltage memory MGT power supply reference Table 10 : Power supply Optionally, the FM482 can be used as a stand alone module and is powered via the external power connector. April 2007 FM482 User manual www.4dsp.com - 18 - FM482 user manual V1.3 Figure 9 : Power supply An ADT7411 device is used to monitor the power on the different voltage rails as well as the temperature. The ADT7411 data are constantly passed to the Virtex-4 device A. Measurements can be accessed from the host computer via the PCI bus. A software utility delivered with the board allows the monitoring of the voltage on the 2.5V, 1.8V, 1.2V and 0.9V rails. It also displays the Virtex-4 device B junction temperature. 4.1 External power connector for stand alone mode An external power connector (J2) is available on side 2 of the PMC, next to the PMC connectors. It is used to power the board when it is in stand alone mode. This is a right angled connector and it will be mounted on board only if the card is ordered in its stand alone version (FM482-SA). The height and placement of this connector on the PCB breaches the PMC specifications and the module should not be used in an enclosed chassis compliant to PMC specifications if the external power connector is present on board. Do not connect an external power source to J2 if the board is powered via the PMC connectors. Doing so will result in damaging the board. The external power connector is of type Molex 43045-1021. Each circuit can carry a maximum current of 5A. The connector pin assignment is as follows: Pin # 1 3 5 7 9 Signal 3.3V 5V GND GND -12V Signal 3.3V 5V GND GND 12V Pin # 2 4 6 8 10 Table 11 : External power connector pin assignment April 2007 FM482 User manual www.4dsp.com - 19 - FM482 user manual V1.3 5 Environment 5.1 Temperature Operating temperature 0°C to +60°C (Commercial) -40°C to +85°C (Industrial) Storage temperature: -40°C to +120°C 5.2 Convection cooling 600LFM minimum 5.3 Conduction cooling The FM482 can optionally be delivered as conduction cooled PMC. The FM482 is compliant to ANSI/VITA 20-2001 standard for conduction cooled PMC. 6 Safety This module presents no hazard to the user. 7 EMC This module is designed to operate from within an enclosed host system, which is build to provide EMC shielding. Operation within the EU EMC guidelines is not guaranteed unless it is installed within an adequate host system. This module is protected from damage by fast voltage transients originating from outside the host system which may be introduced through the system. 8 Warranty Hardware Software/Firmware Basic Warranty (included) 1 Year from Date of Shipment 90 Days from Date of Shipment Extended Warranty (optional) 2 Years from Date of Shipment 1 Year from Date of Shipment April 2007 FM482 User manual www.4dsp.com - 20 - FM482 user manual V1.3 9 FM482 picture Figure 10: FM482 April 2007 FM482 User manual www.4dsp.com - 21 -
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