Chassis Applications - Renesas Electronics

Microcontrollers and MOSFETs for
Chassis Applications
2 62
6
2
O
IS
ASIL D
www.renesas.eu
2014.11
Highest functional safety requirements
The P Series was developed
by Renesas for applications
requiring the highest
functional safety levels
(up to ASIL D). This is realized
by the highly efficient on-chip
diagnostic features such as
redundant CPU subsystem with compare unit, built-in
self-tests for logic and memories, and ECC protection
for on-chip memories.
Compliance with the functional safety standard
ISO 26262 was inherent during development and
analyzed throughout the course of safety assessments
to ensure ASIL D conformity.
Functional safety
Intrinsic safety vs. software-based safety
MCU design considerations
While conventional Microcontrollers (MCUs) require
additional monitoring software to supervise their correct
function, development with intrinsically safe MCUs, like
RH850/P1M and RH850/P1x-C, completely reduces this
design effort.
This has many advantages for the ECU maker:
A detailed FMEA during the MCU design phase was used
to identify relevant failure modes and to implement the
appropriate diagnostics features in the hardware. This
included fault scenarios that would not normally be covered
by a conventional MCU or, if needed, only through high
costs at the system level. The effectiveness of these
diagnostic measures to meet ASIL D has been proven in
special fault injection validations conducted during MCU
development.
Smaller code
ASIL D compliance requires a high diagnostic coverage to
detect random faults. Conventional MCUs require very
complex diagnostic software to achieve this level of cover.
The integral safety architecture of Renesas’ P Series MCUs
provides such diagnostic functions in hardware. This means
a significant simplification and reduction of the code size,
resulting in smaller memory sizes and shorter TATs.
Performance
V850E2/Px4
RH850/P1M
RH850/P1x-C
Number of
Processor
Elements (CPUs)
2
(In lock-step)
2
(In lock-step)
Up to 4
(2 x 2 in lock-step)
Code Flash
512 KB – 1 MB
512 KB – 2 MB
2 MB – 8 MB
Data Flash
32 KB
Up to 64 KB
Up to 224 KB
FlexRayTM
2 ch.
Up to 2 ch.
Up to 4 ch.
By migrating diagnostic functions from software to highly
efficient integrated hardware peripherals, with improved
test coverage, the CPU can focus on its main purpose:
running the application system. The 32-bit RH850 core
delivers up to 2.8 DMIPS/MHz which corresponds to up
to 1344 DMIPS for a dual core device like RH850/P1x-C
running at 240 MHz!
SENT
–
6 ch.
Up to 8 ch.
PSI5
–
2 ch.
–
Cryptographic
Unit
–
ICU-S
(optional)
ICU-M (with 4 and
8 MB version)
ADC Channels
ADC 0: 22 ch.
Temperature
Sensor
–
•
•
Shorter development cycles
Max.
Performance
Up to 410 DMIPS
448 DMIPS
Up to 1344 DMIPS
3.0 – 3.6 V or
4.5 – 5.5 V
3.0 – 5.5 V
3.0 – 3.6 V
For the ECU manufacturer, the implementation and
assessment of the system level functional safety architecture
is an extremely complex and time-consuming task. The MCU
analysis is an especially challenging task as it is one of the
most complex components of the system. For an ECU
manufacturer, the MCUs internal structure and failure modes
makes this even more complicated, simply down to the
limited MCU knowledge. In effect, Renesas has taken care
of the safety assessment of the P Series devices. This
significantly reduces the ECU engineering workload and
helps to shorten development time.
2
I/O Voltage
Packages
LQFP144
ADC 0: up to 12 ch. ADC 0: up to 20 ch.
ADC 1: up to 12 ch. ADC 1: up to 20 ch.
LQFP100, LQFP144 LQFP144, BGA292
Feature comparison of microcontrollers
for ASIL D applications
www.renesas.eu
The next generation: RH850/P1M and RH850/P1x-C
RH850/P1M and RH850/P1x-C are the latest additions to
Renesas’ successful line of microcontrollers, targeting
applications with functional safety requirements up to
ASIL D. These devices are based on the proven V850E2/Px4
but feature a long list of improvements: significantly lower
power consumption, more advanced on-chip peripherals,
and more CPU performance just to name a few.
LQFP100
R7F701322/23
R7F701310/11
R7F701314/15
LQFP144
0.8
0.8
0.4
0.4
0.5
0.4
R7F701318/19
0.5
R7F701304/05
R7F701366/67
0.4
R7F701312/13
R7F701362/63
0.5
0.5
0.5
R7F701320/21
0.5
R7F701364/65
R7F701331/30
R7F701326
(Dual Voltage only)
0.8
RH850/P1x-C
RH850/P1M with ICU-S
RH850/P1M without ICU-S
0.5
512 KB
1 MB
2 MB
4 MB 8 MB
Flash Size
controller etc.) an identical Checker Processor Element.
This executes in lock-step operation with two clock cycles
delay exactly the same code as the Processor Element. If the
integrated comparator detects any difference between the
outputs of the Main Processor Element and the Checker
Processor Element, it automatically triggers the Error Control
Module to initiate appropriate actions before the failure puts
the functional safety of the ECU at risk.
The redundancy of the Processor Elements is completely
transparent to software and does not need to be taken
into account in the implementation of the application code.
R7F701327
(Dual Voltage only)
Built-in self-test (BIST)
R7F701329/28
Safety can be achieved only if all integrated functions work
properly. All P Series devices therefore feature a built-in
self-test that checks all relevant digital on-chip units in a
matter of milliseconds during start-up. This self-test
includes all internal volatile memories as well as many
logic functions. Moreover, soft-error-robust flip-flops and
ECC/EDC on all internal memories mitigate the occurrence
of transient faults.
Pin Pitch
(mm)
Single Voltage
Dual Voltage
BGA292
Dual core performance (RH850/P1H-C only)
The more functions ECUs have to fulfil, the more performance
is needed. RH850/P1x-C devices with 4 and 8 MB code
flash incorporate two Processor Elements (PEs) and two
Redundant CPU
Checker Processor Elements. The two Processor Elements
Redundancy of their most critical parts is key for systems with
deliver up to 672 DMIPS each or 1344 DMIPS in total.
strong functional safety requirements. All RH850/P1x and
Both Processor Elements are identical and can access all
RH850/P1x-C microcontrollers therefore incorporate for each
peripherals. This means the ECU designer can achieve
Main Processor Element (with CPU, FPU, MPU, interrupt
maximum flexibility regarding the partitioning of his
software. For example, it is possible
to run AUTOSAR non-time critical
Code Flash
Global RAM
tasks on one Processor Element,
while simultaneously executing time
critical tasks on the second Processor
Element (in a real-time operating
system).
Local RAM
Local RAM
Processor
Processor
MEV
The inter-processor communication
Element
Element
IPIR
and semaphore handling between
1
2
Cache
Cache
the two Processor Elements is
supported by 34 dedicated 32-bit
registers (MEV, IPIR) which are
accessible by both Processor
Elements.
...
Ethernet
CAN
Timers
Data Flash
RH850/P1M and RH850/P1x-C product portfolio
for ASIL D applications
Simplified block diagram of dual core RH850/P1H-C microcontroller
(ICU-M not shown)
3
Data flash
All RH850/P1M and RH850/P1x-C devices
feature dedicated data flash for storing nonvolatile information (E²PROM emulation). Each
4-byte unit can be written more than 250,000
times. For security reasons, devices featuring
an Intelligent Cryptographic Unit (ICU) offer an
extra area of up to 32 KB for storing confidential
information. The access to this area is limited
to the ICU.
As code flash and data flash are separate blocks,
the execution of application code does not
interfere with write/ erase operations on data
flash (dual operation).
Code Flash
RAM
ICU-M
Area
Data Flash
AES
Engine
TRNG
WDG
Timer
ICU-M
Area
Other
System
Resources
Intelligent Cryptographic Unit M (ICU-M) for advanced
cryptographic requirements like public key cryptography
Data-CRC peripheral
Functional safety on system level strongly depends on
error-free transmission of information between the
components of the system. The protection of data stream
integrity by CRC checksums is therefore standard in such
kind of systems.
In RH850/P1M and RH850/P1x-C, the calculation and
verification of CRC checksums on data streams of arbitrary
length is supported by up to eight dedicated hardware
CRC units. The CRC polynomial can be selected for 32-bit
Ethernet, 16-bit CCITT, 8-bit SAE J1850 or 8-bit 0x2F.
As calculation is implemented in hardware, it has no impact
on the CPU load.
Error control module
The ECM module collects error signals from various sources
and monitoring systems. It also defines the action to be
carried out upon the detection of a failure: signaling it at the
ERROROUT pin, triggering an interrupt, or initiating a reset.
A dedicated Error Delay Timer optionally allows the execution
of program code before a failure is signaled to external
components via the ERROROUT pin. This allows the MCU to
be prepared for system shut-downs by external components.
Intelligent Cryptographic Unit ICU-M
(RH850/P1x-C only)
The ICU-M security module incorporates everything
necessary to implement user-defined security services,
from secure boot to autonomous memory check during
run-time, from fast encryption/decryption to RSA signature
verification. The ICU-M operates on a fully featured 80 MHz
RH850 CPU that processes the programmed services,
and has access to all resources within the device (global
RAM, flash, peripherals). Program code and data for ICU-M
are stored within secured and exclusive flash areas.
4
Crypto Core
(RH850)
RAM
The ICU-M includes a powerful AES engine, which supports
several complex block ciphers, including Galois/Counter
mode (GCM) and XTS mode, with multiple execution
contexts that can run in parallel. It also includes a true source
of randomness. The Debugger Authentication Logic blocks
malicious connection attempts from the outside and optionally
disables any communication via CAN and FlexRayTM once
an attack is detected.
Intelligent Cryptographic Unit ICU-S
(RH850/P1M only)
The optional SHE-compliant ICU-S security module provides
an effective way to prevent software tampering and to
secure CAN communications. It incorporates a state machine,
protected RAM, an AES engine and a hardware random
number generator (TRNG) that process the services as
described in the SHE specification (encryption in ECB and
CBC mode and CMAC generation and verification).
The ICU-S secret keys are stored in a protected data flash
area, which is accessible only to the ICU-S and cannot be
read or written by the main CPU.
RH850/P1M devices can be provided on request with a
fixed, worldwide unique device ID. This can be used for
example to control software updates or to unlock features
only for individual ECUs.
RAM
State
Machine
Data Flash
AES
Engine
TRNG
ICU-S
Area
Intelligent Cryptographic Unit S (ICU-S)
for standard AES-128 encryption
www.renesas.eu
Ethernet controller
(RH850/P1x-C only)
RS-CAN
(RH850/P1M only)
RH850/P1x-C devices provide for 10/100 Mbps Ethernet
connections an on-chip IEEE 802.3 conformant Media
Access Controller (MAC) with up to two MII/RMII
interfaces. To reduce CPU load, the controller supports
automatic address filtering (except in promiscuous mode),
CRC calculations and data transfer via DMA directly to RAM.
The integrated magic package detection optionally triggers
a Wake-on-LAN (WOL) interrupt which can be used for
example to start the device.
In contrast to previous device generations, the RS-CAN as
implemented in RH850/P1x supports shared memory
among multiple channels, flexible sizes of the used memory
areas, and consequent assignment of FIFO structures.
Thanks to this, a channel that needs more data and filter
resources can take advantage of another channel needing
less of these resources. The RS-CAN allows for diagnostic
purposes to mirror all CAN messages to one CAN port.
The CAN transfer layer fulfills all requirements defined in
ISO 11898, SAE J1939 and CAN 2.0B standard.
System
Memory
DMA & DTS
16 ch. & 128 ch.
Code Flash
8 MB
RAM
1088 KB
Data Flash
192 KB + 32 KB secure
ICU-M
Main Oscillator
16 – 24 MHz
On-Chip Oscillator
8 MHz
Timers
External
Memory Controller
Generic
Timer Module
(GTM)
POC/LVI
On-Chip Debug
8 CMU ch.
2 TBU ch.
16 TIM ch.
21 ATOM ch.
12 DTM ch.
15 MCS ch
Functional Safety
Hardware Built-In
Self Test (BIST)
Error Control Module
(ECM)
Error-Out Pin
8 Data CRC Modules
Temperature Sensor
2 Window
Watchdog Timers
2 System Timers
2 Redundant
32-bit CPUs
2 x RH850G3M in
Lock-Step Operation
1344 DMIPS @ 240 MHz
Dual Pipelines
7 Stages
Instruction Cache
16 KB, 4-way
FPU
Single & Double
Precision
Communication
2 Ethernet
10/100 Mbps
FlexRayTM
The optional FlexRayTM interface supports two communication
channels up to 10 Mbps and is conformance tested to
FlexRayTM protocol specification V2.1.
Key features
• 8 KB RAM, configurable from 30 message buffers with
254-byte data field each up to 128 message buffers with
48-byte data field each
• Fast CPU access to message buffers via I/O buffer
• Filtering by frame ID, channel ID or cycle number
4 CAN (FD)
• High clock accuracy
4 FlexRay
• Network management support
TM
4 CSIs
up to 20 Mbps
8 SENT
V850E2/Px4 RH850/P1M RH850/P1x-C
Feature
Extended Safety Analysis
on Peripherals
–
•
•
Checker Core delayed
by two Clock Cycles
•
•
•
Optional Delay for ERROROUT Pin
–
•
•
Bus Protection
–
Parity
ECC
M-CAN
(RH850/P1x-C only)
ECC on RAM and Code Flash
•
•
•
ECC on Data Flash
–
•
•
The M-CAN peripheral supports not only standard CAN as
specified in ISO 11898-1 but also the CAN FD specification
with a payload size of up to 64 bytes (instead of 8 bytes)
and a maximum transmission rate of 8 Mbps (instead of
1 Mbps). This increases the CAN bandwidth significantly
while compatibility is maintained.
The M-CAN of RH850/P1x-C also supports the TTCAN
(time-triggered CAN) level 2 protocol according ISO 11898-4
in hardware.
CRC Modules
2
4
up to 8
Error Injection Points
–
•
•
On-chip Temperature Sensor
–
•
•
Core Voltage Monitor (CVM)
–
•
•
WDT with changing Restart Code
–
•
•
4 High-Speed USRTs
up to 160 Mbps
Analog
4 UARTs/LIN
2 12-bit ADCs
2 x 20 ch.
136 digital I/Os
Block diagram of dual core RH850/P1x
Functional safety feature overview
5
A/D converters
Motor control & encoder timers (RH850/P1M only)
The integrated ADCs allow conversion with 12-bit resolution
and a minimum conversion time of 1 µs. The assignment
of analogue inputs to up to 72 Virtual ADC Channels in
10 Scan Groups allows to define complex conversion
sequences with arbitrary priorities. These conversion
sequences are processed autonomously by the ADC which
stores the converted values into the Virtual Channel’s
result register.
In RH850/P1M, additional track-and-hold stages enable
simultaneous snapshots of up to 10 analog signals that can
then be converted successively. The correct function of the
ADC is checked by an integrated self-test that performs
manifold systematic tests of the complete signal path from
the analog input pin via the external sample capacitors and
the channel multiplexers to the actual A/D conversion unit.
Each motor control timer can generate autonomously six
center- or edge-aligned 16-bit PWM signals for the control
of asynchronous and synchronous AC motors. Brushless DC
(BLDC) motors can be controlled by 120° excitation mode
that takes into account the inputs of three Hall sensors.
Interconnections with other peripherals support enhanced
functions like automatic calculation of the rotor position
from Hall sensor signals, speed detection or A/D conversion
triggering. For safety reasons, emergency shut-off is
controlled by hardware and independent from any software.
In addition to this, all RH850/P1M devices incorporate two
dedicated encoder timers for the autonomous calculation
of rotor positions of AC and BLDC motors based on rotary
encoder signals (for BLDC in combination with the motor
control timers and Hall sensors).
Virtual
Channel
Physical
Channel
Scan
Group
0
1
2
3
4
5
6
7
8
9
10
11
...
7
9
9
1
2
14
15
4
15
10
9
13
...
0
0
0
0
0
1
1
1
1
2
2
2
...
Scan Group 0
7
9
9
1
2
15
4
15
10
9
13
10
9
13
INT
14
Scan Group 1
INT
Scan Group 2
Converted
Physical
Channel
7
9
14
15
4
15
9
1
2
Example for the usage of virtual ADC channels and scan groups.
The conversion results are stored for each virtual channel in a dedicated result register.
Generic Timer Module (RH850/P1x-C only)
Temperature sensor
The GTM is a very powerful and complex timer module
which is capable to fulfill even the most sophisticated
timer requirements.
It integrates a whole bunch of functional sub-modules,
like Multi-Channel Sequencers (MCSs), Clock Management
Units (CMUs), Time Base Units (TBUs), Timer Input Modules
(TIMs), and Timer Output Modules (ATOMs). All these units
are connected via the central Advanced Routing Unit (ARU).
Each of the up to fifteen Multi-Channel Sequencers (MCSs)
operates as a freely programmable, Turing complete CPU
system for the processing of timer inputs and controlling
of timer outputs. Dedicated Dead Time Modules (DTMs)
support the generation of inverse signals, like it is necessary
for the control of half bridges, in hardware.
All devices feature a temperature sensor to measure the
junction temperature in single-shot or continuous mode. It
can be configured to send an automatic notification to the
Error Control Module (ECM) if an upper or lower limit is
exceeded. In addition to this, the temperature sensor in
RH850/P1x-C can optionally trigger an interrupt when the
temperature rises or falls into one of two definable
temperature ranges (high temperature range and standard
operation temperature range).
6
www.renesas.eu
On-chip debugging
Extremely low power consumption
All RH850/P1M and RH850/P1x-C devices provide on-chip
debugging via Nexus JTAG and Low Pin Debug (LPD)
interface. In both cases, the debugger unit can be connected
to the device without interrupting its operation (hot plugging)
and can be used also to program the device’s internal code
and data flash.
For RH850/P1x-C, a special version of the microcontroller with
even more debugging features is offered: RH850/PH1-CE.
This device incorporates in addition to the debugging options
of RH850/P1x-H a high-speed Nexus Aurora interface for
collecting trace information in real-time. Like RH850/P1x,
it also provides an AUD (Advanced User Debugger) monitor
to access RAM, registers, code and data flash during runtime.
All RH850/P1M and RH850/P1H-CE devices feature up to
2 MB dedicated Emulation RAM. This Emulation RAM can be
mapped into the memory space of the code flash, virtually
replacing its content. The content of the Emulation RAM can be
modified via debug interface or by the microcontroller itself.
Thanks to the 40-nm process, the power consumption of
RH850/P1M and RH850/P1x-C devices could be reduced
significantly from previous generations and hence sets new
standards for microcontrollers for ASIL D applications.
This opens the door for costs savings in several parts of
the ECU, like in the power supply circuitry. The much lower
power dissipation of this new generation of functional safety
microcontrollers also invites to evaluate new, previously
impossible heat sink solutions.
Comparable
Microcontroller
570 mA
(55 nm, @ 180 MHz)
RH850/P1M 150 mA*
(40 nm, @ 160 MHz)
- 73%
Power Consumption**
*: Target value
**: Typical, excl. I/Os
RH850/P1M consumes only about ¼ of the current
other, comparable microcontrollers need.
Tools
RH850/P1x-C starter kit
Y-ASK-RH850P1X-C
This starter kit comes with everything necessary for a fast
and smooth start with RH850/P1x-C. The board itself is
fully equipped with
• RH850/P1x-C microcontroller with 4 MB on-board flash
• 2.7” colour TFT (320 x 240) with touch panel
• 2 Ethernet interfaces (RJ45 & Broadcom BroadR-Reach®)
• 3 CAN/CAN FD, 2 RS232, 3 LIN, 2 FlexRayTM, CSI,
I/O interfaces
• Rotary encoder with push-button, buzzer
Board dimensions: 330 mm x 187 mm
• ICs for power consumption measurement (1.25 V and 3.3 V)
• Connector for E1 on-chip debugger
The package includes besides the board the E1 on-chip
debugger, a power supply, a 90-day evaluation version of
Green Hills’ Multi IDE, and a CD-ROM with documentation
and sample code.
7
RH850 evaluation platform main board
Y-RH850-X1X-MB-T1-V1
This generic board for RH850 software development hosts
device-specific Adapter Boards and provides a large set of
peripherals:
• Various interfaces/connectors:
– 2 CAN, 2 LIN
– FlexRayTM (2 channels)
– Ethernet
– 2 UART/RS232, 2 SENT, 2 PSI5
Board dimensions: 260 mm x 174 mm
• 4 signal LEDs (active high), 3 push buttons,
3 analogue inputs
The package includes a CD-ROM with user’s manual and
schematic.
• LCD module, breadboard area
Functional safety microcontroller portfolio with RH850/P1M and RH850/P1x-C
Group
Part Number
Main
CPU(s)
Clock
Frequency
R7F701304
Code
Flash
Data
Flash
512 KB
R7F701305
RAM
Emulation
RAM
CAN
8 KB
2 ch.
(CAN)
Ethernet
FlexRayTM
64 KB
R7F701312
R7F701313
32 KB
R7F701310
1 MB
R7F701311
–
R7F701314
R7F701315
R7F701320
RH850/P1M
R7F701364
R7F701321
RH850
160 MHz
–
128 KB
R7F701365
R7F701318
R7F701362
R7F701319
2 MB
64 KB
2 MB
96 KB
32 KB
3 ch.
(CAN)
2 ch.
R7F701363
R7F701322
R7F701366
R7F701323
R7F701367
R7F701331
RH850/P1M-C
R7F701330
R7F701329
RH850
240 MHz
448 KB
R7F701328
RH850/P1H-C
RH850/P1H-CE
8
R7F701327
R7F701326
R7F701325
2 x RH850
2x
240 MHz
4 MB
8 MB
10 MB
160 KB
192 KB
1 ch.
2 ch.
–
3 ch.
(CAN FD)
2 ch.
4 ch.
2 MB
4 ch.
(CAN FD)
1088 KB
1536 KB
www.renesas.eu
RH850 evaluation platform adapter boards
Y-RH850-P1X-100PIN-PB-T1-V1 (LQFP100, 0.5 mm p. p.)
Y-RH850-P1X-144PIN-PB-T1-V1 (LQFP144, 0.4 mm p. p.)
Y-RH850-P1X-C-144PIN-PB-T1-V1 (LQFP144, 0.4 mm p. p.)
Y-RH850-P1X-C-292PIN-PB-T1-V1 (BGA292)
Y-RH850-P1X-C-404PIN-PB-T1-V1 (BGA404)
Adapter Boards can be operated plugged into the RH850/x1x
Evaluation Platform Main Board or stand-alone. They are
equipped with an E1 connector and a test socket to hold
RH850/P1M devices (not included).
ADC 0
ADC 1
CSIs/
USRTs
SENT
Crypto
Unit
CRC
Units
Approximate
Performance
Board dimensions: 160 mm x 100 mm
Supply
Voltage
Supply Voltage
(Core, I/Os)
Pin
Count
Package Type
100
LQFP, 0.5 mm p. p.
n/a
9 x 12-bit
10 x 12-bit
1.15 - 1.35 V
5 ch.
n/a
1.15 - 1.35 V
–
12 x 12-bit 12 x 12-bit
n/a
1.15 - 1.35 V
6 ch.
n/a
LQFP, 0.4 mm p. p.
144
1.15 - 1.35 V
–
9 x 12-bit
10 x 12-bit
8
5 ch.
ICU-S
–
n/a
4
448 DMIPS
3.0 – 5.5 V
–
n/a
ICU-S
LQFP, 0.4 mm p. p.
–
6 ch.
1.15 - 1.35 V
ICU-S
144
–
n/a
ICU-S
LQFP, 0.5 mm p. p.
–
1.15 - 1.35 V
ICU-S
12 x 12-bit
n/a
8 x 12-bit
6
6 ch.
12 x 12-bit 12 x 12-bit
4
8
8 ch.
10 ch.
1.15 - 1.35 V
672 DMIPS
ICU-M
16 x 12-bit 16 x 12-bit
20 x 12-bit 20 x 12-bit
100
1.15 - 1.35 V
ICU-S
12 x 12-bit 12 x 12-bit
LQFP, 0.5 mm p. p.
1344 DMIPS
LQFP, 0.4 mm p. p.
n/a
3.0 – 3.6 V
8
144
292
1.15 - 1.35 V
BGA, 0.8 mm b. p.
404
9
16-bit Microcontroller RL78/F1x
• 16-Bit device technology shrunk to 130 nm
512 KB
• Huge scalability with more than 120 derivatives
384 KB
• Many new energy saving features integrated
256 KB
• Ultra low power consumption
–– Reduced to 50% compared to previous generation
–– RUN mode: typ. 0.2 mA/MHz and max. 0.4 m A/MHz
• Strong performance CPU with 1.6 DMIPS/MHz
192 KB
128 KB
96 KB
64 KB
• Increased ambient temperature of up to 150 °C
48 KB
• Improved Data Flash memory with minimum 100,000
write/erase cycles
32 KB
24 KB
• High integration enabling system cost reduction
–– High precision on chip oscillator (+/- 2% at -40 to
105 °C) fully suitable for LIN
–– 64 MHz on-chip high-speed clock for dedicated
peripherals
16 KB
8 KB
20
30
SSOP
32
48
48
64
QFN
80
100
144
OFP
Number of MCUs
1–2
3–4
Device concept
Basis of the concept is the compatibility. That supports
the flexibility during the design of the application to move
to amore suitable derivative in case of significant changes.
The portfolio of the RL78/F1x is the largest among all 16-bit
MCU suppliers.
RL78/F15
48 to 144 pins
128 to 512 KB
RL78/F14
30 to 100 pins
48 to 256 KB
ROM/RAM/Package Expansion
Data Flash Expansion
2 channel Full-H/W LIN
DAC
Comparator
Event Link Controller (ELC)
RL78/F13
20 to 80 pins
16 to 128 KB
RL78/F12
20 to 64 pins
8 to 64 KB
ROM/Package Expansion
64MHz OCO (for Timer RD)
Independent OCO for WDT PLL
Full H/W LIN (Master & Slave)
Advanced CAN
Timer RD (3 phase Motor)
DTC (Advanced DMA)
Hot Plug-in Debugging
Functional Safety: RAM ECC
DIV/MUL instruction
Advanced POR and LVD
Advanced Standby Mode
Snooze Mode
Functional safety
Support IPs
Timer Array Unit (TAU)
Serial Array Unit (SAU)
Full HW LIN (Slave)
Built in functional safety features
10
ROM/RAM/Package Expansion
Data Flash Expansion
Peripheral Expansion
Supports compatibility
Developed according
to ISO 26262 standard
www.renesas.eu
Block diagram RL78/F15 – 144-pin QFP
System
16-bit CPU
Interfaces
2 x CAN
DTC (24 channel)
RL78 Core
3 x HW LIN UART
(with MUL/DIV/MAC)
up to 3 x UART
Internal 15 kHz OSC
32 MHz @ -40 to +105° C
24 MHz @ -40 to +125° C
up to 6 x CSI
Internal 32 kHz OSC
2.7 – 5.5 V (single voltage)
Event Link Controller
PLL
Ext. OSC 20 MHz
31 x 10-bit ADC
BLDC Motor Control
IEBus
16 x Ext INT
Memory
POR/LVD
Analog
I2C Multimaster
On-Chip debug (Hot plug in, Live debug)
Ext. Sub-OSC 32 MHz
Clock Monitor
up to 4 x I2C
8 x KeyReturn
512 KB Flash *
32 KB RAM
384 KB Flash *
26 KB RAM
256 KB Flash **
20 KB RAM
192 KB Flash **
16 KB RAM
128 KB Flash **
10 KB RAM
Comparator 4 x MUX
16 KB Data Flash*
8-bit DAC
8 KB Data Flash**
136 I/O Ports
Timers
3P Motor Timer 16-bit
24 x 16-bit Timer
24 x OS-Timer
RTC
Window WDT (15 kHz)
RL78/F1x feature line-up
16 - b it
RL78/
Basics
F12
F13
F14
F15
Flash
8 – 64 KB
16 – 128 KB
4 8 – 256 KB
128 – 512 KB
RAM
0.5 – 4 KB
1 – 8 KB
4 – 20 KB
10 – 32 KB
Data flash
4 KB
4 KB
4 – 8 KB
8 – 16 KB
20 – 64
20 – 80
30 – 100
4 8 – 14 4
Ethernet
–
–
–
–
FlexRay
–
–
–
–
Security (cryptographic)
–
–
–
–
CAN
–
0–1
1
2
CAN FD TM
–
–
–
–
2–3
Package pins/balls
LIN
Peripherals
1
1
1–2
UART
2–4
1–2
2
2–3
CSI
2–7
2–4
3–4
4–6
I 2C
1–7
2–5
3–5
5
ADC 10-bit
4 – 12
4 – 20
10 – 31
18 – 31
ADC 12-bit
PWM
16-bit timer
32-bit timer
Max. CPU clock
Supply
Temperature
Support
–
–
–
–
4–7
7 – 16
11 – 20
15 – 27
9
17 – 21
21 – 25
25 – 3 3
–
–
–
–
32 MHz
32 MHz
32 MHz
32 MHz
Min. voltage
1.8 V
2.7 V
2.7 V
2.7 V
Max. voltage
5.5 V
5.5 V
5.5 V
5.5 V
Min. temperature
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
Max. temperature
+125 °C
+150 °C
+150 °C
+125 °C
AUTOSAR MCAL
–
–
–
–
Functional safety
–
3
3
3
- FMEDA
–
3
3
3
- Design
–
–
–
3
- ASIL
–
–
–
B
11
32-Bit Microcontroller RH850/F1x
• 32-bit device technology shrunk to 40 nm
6 MB
• Huge scalability with more than 80 derivatives
4 MB
• Many new energy saving features integrated
3 MB
• Super low power
–– RUN mode: typ. 0.3 mA/MHz and max. 0.75 mA/MHz
2 MB
1.5 MB
• High performance CPU with up to 3.04 DMIPS/MHz
• Ambient temperature up to 125 °C supported
1 MB
• Improved Data Flash memory with minimum 125,000
write/erase cycles
• Full coverage of body networking interfaces supported
–– CAN, CAN FD, LIN
–– FlexRayTM, Ethernet AVB
788 KB
512 KB
384 KB
256 KB
48
64
80
100
144
QFP
176
233
272
BGA
Number of MCUs
1–2
3–4
>4
Device concept
The RH850 Family represents the next generation 32-bit
RISC microcontroller to endorse future automotive
applications. The F Series products, designed for body
applications, provide high scalability, extreme low power
consumption and a broad range of networking IPs.
nectivity
ry and con
ce, memo
an
in p e rform
S ca la b le
+FlexRay
plete series
within com
hernet AV
+Core + Et
+ FPU
B
CAN, LIN
Extra Data Flash
CAN FD
48 – 176 LQFP
Developed according to ISO 26262 standard
12
2 x 120 MHz
3 MB – 6 MB Flash
320 KB – 576 KB RAM
64 KB Data Flash
CAN, LIN
ICUM
FlexRay
Ethernet AVB
ECO
PREMIUM
144 – 233 LQFP/BGA
F1H
AD VANCED
120 MHz
3 MB – 4 MB Flash
256 KB – 320 KB RAM
64 KB Data Flash
CAN, LIN
ECO
PREMIUM
F1M
AD VANCED
80 MHz
256 KB – 2 MB Flash
32 KB – 192 KB RAM
32 KB Data Flash
CAN, LIN
AD VANCED
F1L
ECO
CAN FD
176 – 272 LQFP/BGA
SECURITY
SUPPORT
www.renesas.eu
Block Diagram RH850/F1H – 233-pin BGA
System
32-bit CPU
Interfaces
6 x CAN FD™/1 x CAN
32 x DMA
(560 Msg)
2 x RH850 Core
Interrupt Controller
Ethernet AVB
2 x 120 MHz
FlexRay
Ext. Memory Int.
3.0 – 5.5 V (single voltage)
-40 to + 125° C
SPF: 2 x MPU, SRP
4 x CSI
On-Chip debug
4 x QCSI
Main OSC
6 x UART/LIN
FPU
12 x LIN (Master)
2 x IntOSC
Sub OSC
Power on Clear
Clock Monitor
Memory
6144 kB Flash
64 kB
Data
Flash
4096 kB Flash
1 x I2C
576 kB RAM
178 x GPIO
384 kB RAM
Analog
320 kB RAM
3072 kB Flash
21ch A/D
+ ext. MUX
CRC
Timer
ICUM
80 x 12-bit PWM
1 x Motor Control
32ch A/D
incl. Diag & Delay
1 x Encoder
2 x OS Timer
1 x 16ch 16-bit Timer
8 x Tmg. Supervision
2 x 4ch 32-bit Timer
3 x WDT
2 x 16ch 16-bit Timer
RTC
RH850/F1x feature line-up
32 - b it
RH850 /
F 1L
Basics
PREMIUM
ECO
ADVANCED
PREMIUM
ECO
Flash
256 – 2 MB
768 – 2 MB
1.5 – 2 MB
3 – 4 MB
3 – 4 MB
3 – 4 MB
3 – 6 MB
3 – 4 MB
RAM
32 KB
32 KB
6 4 KB
256 – 320 KB
256 – 320 KB
256 – 320 KB
320 – 736 KB
256 – 320 KB
Data flash
32 KB
32 KB
4 6 KB
6 4 KB
6 4 KB
6 4 KB
6 4 KB
6 4 KB
6 4 – 176
14 4 – 176
14 4 – 2 3 3
14 4 – 2 3 3
14 4 – 2 3 3
176 – 272
14 4 – 2 3 3
Ethernet
–
–
–
–
–
–
3
3
FlexRay
–
–
–
3
3
3
3
3
Security (cryptographic)
–
3
3
3
3
3
3
3
1–6
1–6
1–6
6
6
6
7–8
7
–
–
–
–
–
6
–
6
LIN
3 – 16
3 – 16
3 – 16
12 – 16
12 – 16
12 – 16
12 – 18
12 – 18
UART
1–6
1–6
1–6
6
6
6
2–6
6
CSI
2–6
2–6
2–6
6
6
6
6–8
8
I 2C
1
1
1
1
1
1
1
1
4 – 28
4 – 28
4 – 28
22 – 3 4
22 – 3 4
22 – 3 4
26 – 38
26 – 38
CAN FD TM
ADC 10-bit
ADC 12-bit
8 – 32
8 – 32
8 – 32
24
24
24
32
32
PWM
13 – 72
13 – 72
13 – 72
6 4 – 80
6 4 – 80
6 4 – 80
4 0 – 96
72 – 80
16-bit timer
16 – 4 8
16 – 4 8
16 – 4 8
21 – 4 8
21 – 4 8
32 – 4 8
32 – 4 8
48
32-bit timer
5–9
5–9
5–9
13
13
13
18
18
80 MHz
96 MHz
96 MHz
120 MHz
120 MHz
120 MHz
2 x 120 MHz
2 x 120 MHz
Min. voltage
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
3.0 V
Max. voltage
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
Min. temperature
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
-4 0 °C
Max. temperature
+125°C
+125 °C
+120 °C
+125 °C
+125 °C
+125 °C
+125 °C
+125 °C
AUTOSAR MCAL
3
3
3
3
3
3
3
3
Functional safety
3
3
3
3
3
3
3
3
- FMEDA
3
3
3
3
3
3
3
3
- Design
3
3
3
3
3
3
3
3
- ASIL
B
B
B
B
B
B
B
B
Max. CPU clock
Temperature
Support
ADVANCED
4 8 – 176
CAN
Supply
F1H
ADVANCED
Package pins/balls
Peripherals
F 1M
ECO
13
AUTOSAR
Complete MCAL packages
License models
Since the early days of AUTOSAR, Renesas provides
AUTOSAR Release 3 Microcontroller Abstraction Layer
(MCAL) for Renesas 32-bit microcontrollers. Meanwhile,
Renesas has expanded its roadmap to incorporate
AUTOSAR Release 4 compliant drivers, which support
automotive Ethernet and safety relevant solutions.
Renesas offers MCALs in three different license models
to meet different requirements:
Support
Single-project
This license type entitles the licensee to use an MCAL for
one specified project.
Development
This license type is for MCAL evaluation, development and
prototyping purposes for a period of 12 months.
Together with the actual MCAL software licenses,
Renesas offers a whole set of MCAL related services
including: support & maintenance, engineering services,
customizations and, last but not least, customer training.
All these AUTOSAR activities are coordinated in Europe
by the AUTOSAR Software Competence Centre, located
in Düsseldorf, Germany.
Multi-project
This is the preferred license type if an MCAL is required
for several projects.
Application Layer
Runtime Environment (RTE)
PORT Driver
DIO Driver
ADC Driver
PWM Driver
I/O Drivers
Complex Drivers
I/O Hardware Abstraction
ICU Driver
Ethernet Driver*
FlexRayTM
Driver
CAN Driver
LIN Driver
Communication Drivers
SPI Handler
Driver
Memory Drivers
Internal Flash
Driver
Microcontroller Drivers
RAM Test*
Communication Hardware
Abstraction
Flash Test*
Memory Hardware
Abstraction
Core Test*
Onboard Device
Abstraction
MCU Driver
Communication Services
Wtachdog
Driver
Memory Services
GPT Driver
AUTOSAR OS
AUTOSAR Libraries
System Services
Modules from Renesas Electronics
ECU Hardware
*Only in AUTOSAR Release 4
AUTOSAR basic software modules including Microcontroller Abstraction Layer (MCAL)
14
www.renesas.eu
PowerMOSFETs
Chassis applications need the whole portfolio of lowvoltage PowerMOSFETs, from power devices in small
packages for ABS/ESP systems to high-power packages
as well as bare dies for EPS. Renesas offers advanced
silicon technologies, reliable packages and known good
dies (KGDs) to meet any or all of these requirements.
Advanced silicon technologies are
the key success factor for offering
superior PowerMOSFETs. Renesas’
ANL2 N-channel technology
significantly reduces RDS(ON) and
gate charge QG compared with the
latest well known UMOS-4 trench
technology. Accordingly switching
losses and on-losses are drastically
reduced – ideal for high power
switching applications. With its
outstanding FOM performance
(RDS(ON) x QG ), this technology will
considerably increase the efficiency
of modern chassis applications.
ANL2 PowerMOSFETs and its
broad line-up cover the performance
requirements of a wide range of
chassis applications.
Normalized RDS(ON)
Technology
Process Name:
ANL1
Serial No.
Low Voltage
Polarity (N/P)
For Automotive
P-Channel
1.5
Gen8
UMOS4
NEW
-30 to -60V
APL1
Under Development
-40 to -60V
N-Channel
1.0
Super-Junction
Gen8
UMOS4
SJ1 ANL1
30 to 60 V
40 to 60 V
Reduced Qg
ANL2
NEW
40 to 60 V
Reduced RDS(on)
ANL3
Under Development
0.5
30 to 60V
2011
2009
2013
2015
RDS(ON) reduction by optimized trench structures
Packages
Mounting Area
PowerMOSFETs come in highly
reliable standard packages like DPAK
TO-263ZK
and D2PAK, but Renesas also offers
new packages with improved
electrical and thermal characteristics
for automotive applications. D2PAKTO-252
7-pin increases current capability up
to 180 A and reduces the package
resistance – it’s the obvious choice
90 A
for high-performance applications.
To support further mounting area
reduction requirements, advanced
SOP-8 Dual
versions of the DPAK and D2PAK7-pin packages with reduced
footprint are being developed by
introducing shorter head and leads
(SHL). In the field of small packages
the HSON-8 combines the small
size of SOP-8 footprint with performance and reliability
comparable to that of DPAK and standard packages – the
best solution for all space-constrained applications.
TO-263ZP
TO-263-7p
TO-263-7p-SHL**
160 mm2
119 mm2
NEW
180 A
TO-252-5p SHL*
HSON-8
57 mm2
150 A
SOP-8
250 A
30 mm2
HSON-8
HSON-8
Dual**
75 A
30 A
*Planned
30 mm2
NEW
**Under development
Current Capability
PowerMOSFET package roadmap
All automotive PowerMOSFETs are qualified to AEC-Q101;
175 °C rated and comply with RoHS and ELV directives.
15
Microcontrollers and MOSFETs for Chassis Applications
Download this brochure at
www.renesas.eu/chassis_brochure
Before purchasing or using any Renesas Electronics products listed herein, please refer to the latest product manual and/or data sheet in advance.
www.renesas.eu
© 2014 Renesas Electronics Europe.
All rights reserved. Printed in Germany.
Document No. R01CA0002ED0300