Specifications: PCI

Specifications
PCI-DAS1602/16
Document Revision 3.2, June, 2006
© Copyright 2006, Measurement Computing Corporation
Specifications
Typical for 25 °C unless otherwise specified.
Specifications in italic text are guaranteed by design.
Analog input
Table 1. Analog input specifications
A/D converter type
Resolution
Number of channels
Input ranges, software
selectable
Polarity
A/D pacing
(software programmable)
Burst mode
A/D trigger sources
A/D triggering modes
Data transfer
A/D conversion time
Throughput
Calibration
Common mode range
CMRR @ 60 Hz
Input leakage current
Input impedance
Absolute maximum input
voltage
AD976ABN
16 bits
16 single-ended / 8 differential, software selectable
±10 V, ±5 V, ±2.5 V, ±1.25 V
0 to 10 V, 0 to 5 V, 0 to 2.5 V, 0 to 1.25 V
Unipolar/bipolar, software selectable
Internal counter - 82C54.
External source (A/D EXTERNAL PACER)
Software polled
Software selectable option, rate = 5 µs
External digital (A/D EXTERNAL TRIGGER)
External analog (ANALOG TRIGGER IN)
External digital: Software configurable for:
! Edge (triggered)
! Level-activated (gated)
! Programmable polarity (rising/falling edge trigger, high/low gate)
External analog: software-configurable for:
! Positive or negative slope.
! Above or below reference
! Positive or negative hysteresis
! In or out of window
Trigger levels set by DAC0 and/or DAC1, 4.88 mV resolution.
Unlimited pre- and post-trigger samples. Total # of samples must be > 256. Compatible
with both Digital and Analog trigger options.
From 512 sample FIFO via interrupt w/ REPINSW
Interrupt
Software polled
5 µs max
200 kHz
Auto-calibration, calibration factors for each range stored on board in non-volatile RAM.
±10 V min
-70 dB
±200 nA max
10 MΩ min
±15 V
1
PCI-DAS1602/16
Specifications
Accuracy
Table 2. Analog input accuracy specifications
Typical accuracy
Absolute accuracy
±2.3 LSB
±5.0 LSB
Accuracy Components
Gain error
Offset error
PGA linearity error
Integral linearity error
Differential linearity error
Trimmable by potentiometer to 0
Trimmable by potentiometer to 0
±1.3 LSB typ , ±10.0 LSB max
±0.5 LSB typ , ±3.0 LSB max
±0.5 LSB typ, ±2.0 LSB max
Each PCI-DAS1602/16 is tested at the factory to assure the board’s overall error does not exceed ±5 LSB.
Total board error is a combination of gain, offset, differential linearity and integral linearity error. The
theoretical absolute accuracy of the board may be calculated by summing these component errors. Worst case
error is realized only in the unlikely event that each of the component errors is at their maximum level, and
causing error in the same direction.
Analog input drift
Table 3. Analog input drift specifications
Range
Analog input full-scale
gain drift
Analog input zero drift
Overall analog input drift
± 10.00 V
± 5.000 V
± 2.500 V
± 1.250 V
0 - 10.00 V
0 - 5.000 V
0 - 2.500 V
0 - 1.250 V
2.2 LSB/°C max
2.2 LSB/°C max
2.2 LSB/°C max
2.2 LSB/°C max
4.1 LSB/°C max
4.1 LSB/°C max
4.1 LSB/°C max
4.1 LSB/°C max
1.8 LSB/°C max
1.9 LSB/°C max
2.0 LSB/°C max
2.3 LSB/°C max
1.9 LSB/°C max
2.1 LSB/°C max
2.4 LSB/°C max
3.0 LSB/°C max
4.0 LSB/°C max
4.1 LSB/°C max
4.2 LSB/°C max
4.5 LSB/°C max
6.0 LSB/°C max
6.2 LSB/°C max
6.5 LSB/°C max
7.1 LSB/°C max
Absolute error change per °C temperature change is a combination of the Gain and Offset drift of many
components. The theoretical worst case error of the board may be calculated by summing these component
errors. Worst case error is realized only in the unlikely event that each of the component errors is at their
maximum level, and causing error in the same direction.
2
PCI-DAS1602/16
Specifications
Noise performance
The following table summarizes the worst case noise performance for the PCI-DAS1602/16. Noise distribution
is determined by gathering 50000 samples with inputs tied to ground at the PCI-DAS1602/16 main connector.
Data is for both single-ended and differential modes of operation.
Table 4. Noise specifications
Range
±2 counts
±1 count
Max Counts
LSBrms*
± 10.00 V
± 5.000 V
± 2.500 V
± 1.250 V
0 - 10.00 V
0 - 5.000 V
0 - 2.500 V
0 - 1.250 V
97%
97%
96%
96%
88%
88%
83%
83%
80%
80%
79%
79%
65%
65%
61%
61%
11
11
11
11
15
15
15
16
1.7
1.7
1.7
1.7
2.3
2.3
2.3
2.4
* Input noise is assumed to be Gaussian. An RMS noise value from a Gaussian distribution is calculated by
dividing the peak-to-peak bin spread by 6.6.
Crosstalk
Crosstalk is defined here as the influence of one channel upon another when scanning two channels at the
specified per channel rate for a total of 50000 samples. A full scale 100 Hz triangle wave is input on channel 1.
Channel 0 is tied to analog ground at the 100-pin user connector. Table 5 summarizes the influence of channel 1
on channel 0 and does not include the effects of noise.
Table 5. Crosstalk specifications
Range
1 kHz Crosstalk
(LSB pk-pk)
10 kHz Crosstalk
(LSB pk-pk)
50 kHz Crosstalk
(LSB pk-pk)
±10.000 V
±5.000 V
±2.500 V
±1.250 V
0V to +10.000 V
0V to +5.000 V
0V to +2.500 V
0V to +1.250 V
4
2
2
3
4
2
2
3
13
7
5
4
8
5
4
3
24
18
16
14
23
16
16
16
3
PCI-DAS1602/16
Specifications
Analog output
Table 6. Analog output specifications
D/A converter type
Resolution
Number of channels
Channel type
Output range (each channel independently
software selectable)
Data transfer
Throughput
Monotonicity
Slew rate
Settling time
Current drive
Output short-circuit duration
Output coupling
Output impedance
Output stability
Coding
Output voltage on power up and reset
AD669BR
16 bits
2
Single-ended voltage output
±10 V, ±5 V, 0 to 10 V, or 0 to 5 V
From 512 sample FIFO via REPOUTSW or programmed I/O. Data
interleaved for dual analog output mode.
100 kHz, 2 channels simultaneous
16 bits at 25 °C
10 V ranges: 6 V/µs
5 V ranges: 3 V/µs
13 µS max 20 V step to 0.0008%
6 µS typ 10V step to 0.0008%
±5 mA min
Indefinite @ 25 mA
DC
0.1 ohms max
Any passive load
Offset binary
0 V ± 10 mV
Accuracy
Table 7. Analog output accuracy specifications
Typical accuracy
Absolute accuracy
±1 LSB
±2 LSB
Accuracy Components
Gain error
Offset error
Integral linearity error
Differential linearity error
Trimmable by potentiometer to 0
Trimmable by potentiometer to 0
±0.5 LSB typ, ±1 LSB max
±0.5 LSB typ, ±1 LSB max
Total board error is a combination of gain, offset, differential linearity and integral linearity error. The
theoretical absolute accuracy of the board may be calculated by summing these component errors. Worst case
error is realized only in the unlikely event that each of the component errors is at their maximum level, and
causing error in the same direction.
Analog output drift
Table 8. Analog output drift specifications
Analog output full-scale gain drift
Analog output zero drift
Overall analog output drift
±0.22 LSB/°C max
±0.22 LSB/°C max
±0.44 LSB/°C max
Absolute error change per °C temperature change is a combination of the gain and offset drift of many
components. The theoretical worst case error of the board may be calculated by summing these component
errors. Worst case error is realized only in the unlikely event that each of the component errors is at their
maximum level, and causing error in the same direction.
4
PCI-DAS1602/16
Specifications
Digital input / output
Table 9. Digital input/output specifications
Digital type
Number of I/O
Configuration
Input high
Input low
Output high
Output low
Power-up / reset state
Pull-up/pull-down resistors
Simultaneous sample and hold trigger
82C55 emulation
Input 74LS244
Output 74LS373
24
2 banks of 8 and 2 banks of 4, or
3 banks of 8, or
2 banks of 8 with handshake
2.0 volts min, 7 volts absolute max
0.8 volts max, -0.5 volts absolute min
2.4 volts min @ -15 mA
0.5 volts max @ 64 mA
Input mode (high impedance)
Provisions have been made on the board for user installed pull-up/pulldown resistor networks
TTL output (SSH OUT).
Logic 0 = Hold
Logic 1 = Sample compatible with CIO-SSH16
Interrupts
Table 10. Interrupt specifications
Interrupt
Interrupt enable
Interrupt polarity
Interrupt sources
(software programmable)
INTA# - mapped to IRQn via PCI BIOS at boot-time
Programmable through PLX9052
Active high level or active low level, programmable through PLX9052
External (rising TTL edge event)
Residual counter
A/D End-of-conversion
A/D End-of-channel-scan
A/D FIFO-not-empty
A/D FIFO-half-full
D/A FIFO-not-empty
D/A FIFO-half-full
5
PCI-DAS1602/16
Specifications
Counter
*Note: Pins 21, 24, and 25 are pulled to logic high via 10K resistors.
Table 11. Counter specifications
Counter type
Configuration
82C54
Two 82C54 chips containing three 16-bit down counters each
82C54A:
Counter 0 — ADC residual sample
counter.
Counter 1 — ADC pacer lower
divider
Counter 2 — ADC pacer upper
divider
Source:
Gate:
Output:
Source:
Gate:
Output:
Source:
Gate:
Output:
ADC Clock.
Programmable source.
End-of-Acquisition interrupt.
10 MHz oscillator
Tied to Counter 2 gate, programmable source.
Chained to Counter 2 Clock.
Counter 1 Output.
Tied to Counter 1 gate, programmable source.
ADC Pacer clock (if software selected), available at user
connector.
Source:
Gate:
Output:
Source:
ADC Clock.
External trigger
End-of-Acquisition interrupt.
User input at 100pin connector or internal 10MHz (software
selectable)
User input at 100pin connector.
Available at 100pin connector.
10 MHz oscillator
Tied to Counter 2 gate, programmable source.
Chained to Counter 2 Clock.
Counter 1 Output.
Tied to Counter 1 gate, programmable source.
DAC Pacer clock, available at user connector.
82C54B:
Counter 0 — pretrigger mode
Counter 0 — non-pretrigger mode:
user counter 4
Counter 1 — DAC pacer lower
divider
Counter 2 — DAC pacer upper
divider
Clock input frequency
High pulse width (clock input)
Low pulse width (clock input)
Gate width high
Gate width low
Input high
Input low
Output high
Output low
Crystal oscillator frequency
Frequency accuracy
Gate:
Output:
Source:
Gate:
Output:
Source:
Gate:
Output:
10 MHz max
30 ns min
50 ns min
50 ns min
50 ns min
2.0 volts min, 5.5 volts absolute max
0.8 volts max, -0.5 volts absolute min
3.0 volts min @ -2.5 mA
0.4 volts max @ 2.5 mA
10 MHz
50 ppm
6
PCI-DAS1602/16
Specifications
Power consumption
Table 12. Power consumption specifications
+5 V operating (A/D converting to FIFO)
2 A typical, 2.1 A max
Environmental
Table 13. Environmental specifications
Operating temperature range
Storage temperature range
Humidity
0 to 70 °C
-40 to 100 °C
0 to 95% non-condensing
Mechanical
Table 14. Mechanical specifications
Card dimensions
PCI custom type card: 107 mm (H) x 18.5 mm (W) x 292 mm (L)
Main connector and pin out
Table 15. Main connector specifications
Connector type
Compatible cables
Compatible accessory products
(with C100FF-x cable)
100-pin high-density, Robinson-Nugent
C100FF-x
ISO-RACK16/P
ISO-DA02/P
BNC-16SE
BNC-16DI
CIO-MINI50
CIO-TERM100
SCB-50
SSR-RACK24 (DADP-5037 adaptor required)
SSR-RACK08 (DADP-5037 adaptor required)
CIO-ERB24 (DADP-5037 adaptor required)
CIO-ERB08 (DADP-5037 adaptor required)
7
PCI-DAS1602/16
Specifications
Table 16. 8-channel differential mode
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal Name
LLGND
CH0 HI
CH0 LO
CH1 HI
CH1 LO
CH2 HI
CH2 LO
CH3 HI
CH3 LO
CH4 HI
CH4 LO
CH5 HI
CH5 LO
CH6 HI
CH6 LO
CH7 HI
CH7 LO
LLGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR4 CLK
CTR4 GATE
CTR4 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
D/A EXTERNAL PACER IN
A/D EXTERNAL TRIGGER IN
N/C
N/C
PC +5V
SSH OUT
GND
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
8
Signal Name
FIRSTPORTA Bit 0
FIRSTPORTA Bit 1
FIRSTPORTA Bit 2
FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5
FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2
FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6
FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
+12V
GND
-12V
N/C
N/C
A/D INTERNAL PACER OUTPUT
D/A INTERNAL PACER OUTPUT
EXTERNAL D/A PACER GATE
N/C
EXTERNAL INTERRUPT
GND
PCI-DAS1602/16
Specifications
Table 17. 16-channel single-ended mode
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Signal Name
LLGND
CH0 HI
CH8 HI
CH1 HI
CH9 HI
CH2 HI
CH10 HI
CH3 HI
CH11 HI
CH4 HI
CH12 HI
CH5 HI
CH13 HI
CH6 HI
CH14 HI
CH7 HI
CH15 HI
LLGND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
D/A GND 0
D/A OUT 0
D/A GND 1
D/A OUT 1
CTR4 CLK
CTR4 GATE
CTR4 OUT
A/D EXTERNAL PACER
ANALOG TRIGGER IN
D/A EXTERNAL PACER IN
A/D EXTERNAL TRIGGER IN
N/C
N/C
PC +5V
SSH OUT
GND
Pin
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
9
Signal Name
FIRSTPORTA Bit 0
FIRSTPORTA Bit 1
FIRSTPORTA Bit 2
FIRSTPORTA Bit 3
FIRSTPORTA Bit 4
FIRSTPORTA Bit 5
FIRSTPORTA Bit 6
FIRSTPORTA Bit 7
FIRSTPORTB Bit 0
FIRSTPORTB Bit 1
FIRSTPORTB Bit 2
FIRSTPORTB Bit 3
FIRSTPORTB Bit 4
FIRSTPORTB Bit 5
FIRSTPORTB Bit 6
FIRSTPORTB Bit 7
FIRSTPORTC Bit 0
FIRSTPORTC Bit 1
FIRSTPORTC Bit 2
FIRSTPORTC Bit 3
FIRSTPORTC Bit 4
FIRSTPORTC Bit 5
FIRSTPORTC Bit 6
FIRSTPORTC Bit 7
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
+12V
GND
-12V
N/C
N/C
A/D INTERNAL PACER OUTPUT
D/A INTERNAL PACER OUTPUT
EXTERNAL D/A PACER GATE
N/C
EXTERNAL INTERRUPT
GND
Measurement Computing Corporation
10 Commerce Way
Suite 1008
Norton, Massachusetts 02766
(508) 946-5100
Fax: (508) 946-9500
E-mail: info@mccdaq.com
www.mccdaq.com
PCI-DAS1602_16 SPEC.doc