US006311264B1
(12) United States Patent
(10) Patent N0.:
Boutaud et al.
(54)
US 6,311,264 B1
(45) Date of Patent:
DIGITAL SIGNAL PROCESSOR WITH WAIT
4,074,351
STATE REGISTER
*Oct. 30, 2001
2/1978 Boone et al. ...................... .. 364/200
.
.
(List continued on next page.)
(75) Inventors: Frederic Boutaud, Roquefort les Pins
OTHER PUBLICATIONS
(FR); Peter N. Ehlig, Houston, TX
(Us)
Second Generation TMS320 User’s Guide ; p. 3—6,
5—2—5—7, 3—34.*
Lin et al. The TMS320 Family of Digital Signal Processors
pp. 1143—1159.*
(73) Assignee: Texas Instruments Incorporated,
Dallas, TX (US)
(*)
Notice:
First—Generation TMS320 User’s Guide, Texas Instruments,
pp. 3—9, A—1—20, 6—2—5, Apr. 1988.
“DSP56000 Digital Signal Processor’s User’s Manual”,
Subject to any disclaimer, the term of this
patent is extended or adjusted under 35
U.S.C. 154(b) by 0 days.
Motorola, 1986, pp. 2—12—18, 3—2, 7—1—3.
“DSP96001”, Motorola, 1988, pp. 1, 2, 6, 9, 10.
This patent is subject to a terminal disclaimer.
Second—Generation TMS320 User’s Guide, Texas Instru
ments, pp. 6—10—26,Dec. 1987.
_
Primary Examiner—Larry D. Donaghue
(21) Appl' NO" 09/431’504
(22) Filed:
Nov. 1, 1999
(74) Attorney, Agent, or Firm—LaWrence J. Bassuk;
Frederick J- Telecky
Related US. Application Data
_ _ _
_
(57)
_
(62) Dlvlslon 9f a_PPh°aF19n_ NO- 09/390388: ?led on JUL 23:
having addressees and differing communication response
1999, which is a division of application No. 08/906,863,
- d
Th
d t
d
-
-
1 d
division of application No_ 08/293,259’ ?led on Aug 19’
1994, now Pat. No. 5,907,714, and a continuation of appliCanon N°-_07/_967:942:_?1ed_ on Oct- 28: 1992: now aban'
cessor adapted for selecting different ones of the peripheral
devices by asserting addresses of each selected peripheral
device. Addressable programmable registers hold Wait state
-
967 ?led on May 4 1989 now abandoned
IIlt- Cl-
7
’
’
a a procesmg ,evlce me ‘1 65 a
d- -t 1
Pen‘) 5'
’
e
-
?led on Aug. 6, 1997, now Pat. No. 5,946,483, which is a
doned, which is a continuation of application No. 07/347,
(52)
(58)
ABSTRACT
A data processing device is used With peripheral devices
-
-
lgl?‘ Pro‘
-
values representative of distinct numbers of Wait states
'
corresponding to different address ranges. Circuitry respon
.................................................... ..
siVe [0 an asserted address to the peripheral devices asserted
US. Cl. ................ ..
712/38; 710/16; 713/401
Field of Search ................................... .. 713/501, 502,
by the digital processor generates the number of Wait states
represented by the value held in one of the addressable
713/600, 401; 712/38, 43; 710/130, 16
programmable registers corresponding to the one of the
References Cited
accommodating the differing communication response peri
address ranges in Which the asserted address occurs, thereby
(56)
U'S' PATENT DOCUMENTS
3,757,306
ods of the peripheral devices.
9/1973 Boone ............................. .. 340/1725
R—DY
8 Claims, 18 Drawing Sheets
\
DATA ADDRESS
<:V>
SEL
A
"
3
M58
111A
9/71
DECODER l
4-BIT COUNTER
M
0/
\—>
PERIPHERAL
ADDR BUS
PWSRO
’
;> PWSRl
\-—-> DWSRO
>
Dwsm
g>
\
lWSRO
\——>
lWSRl
V
;> lWSRZ
IWSRI’)
i
/
D‘ 1110 '
9 7:5 DATA ’ g
C
973
TIT
GENERATOR
T
977 ,9
959/
978
WAIT STATE
974
US 6,311,264 B1
Page 2
US. PATENT DOCUMENTS
4,713,748
4,772,888
4,224,667
4,268,904
4,393,446
9/1980 Lewis et a1~ ----------------------- ~- 395/275
5/1981 Suzuki et a1. ..
.. 395/275
7/1983 Gurr et a1.
.. 395/550
4,400,773
8/1983
4,435,763
3/1984 Bellay er a1- --
Brown er a1-
--
4,482,983 * 11/1984 Slechta, Jr.
4,520,458 * 5/1985 Ha?ori er a1
4,528,625
7/1985 McDonough et a1.
--
4,785,416
478317514
478357681
12/1987 Magar et a1. ...................... .. 364/200
9/1988
Kimura ........................... .. 340/8255
11/1988 Stringer .............................. .. 364/200
5/1989 Turlakov et a1_
_ 364/2OO
5/1989 Culley ___ ~~
_ 364/200
395/275
4,847,757
-- 364/200
4,967,398
10/1990 Jamoua e161. ..
7/1989
.. 713/502
479927960
2/1991 Yamaoka et a1_
-- 711/167
5,065,313
Lunsford ....... ..
.395/275
_ 710/260
71O/1O1
11/1991
Smith
.......
4,577,282
3/1986 Caudel et a1.
.. 364/200
.. 364/200
570707473 * 12/1991 Takano et aL
571517986 * 9/1992 Langan et a1' __
4,631,659
12/1986 Hayn, 11 er a1
- 364/200
5,155,812 * 10/1992
4,638,452
4,675,807
1/1987 Schultz et a1.
.. 395/550
6/1987 Gourneau et a1. ................. .. 395/275
* cited by examiner
. . . .. 395/325
365/23005
364/521
Ehlig et a1. .......................... .. 710/59
U.S. Patent
0111. 30, 2001
FI G.
Sheet 1 of 18
7a
US 6,311,264 B1
W11
PROG ADDRESS
//
PROG DATA
1
1
1 1 1
BMAR
/ ‘
MUX
WT
95
1
INT
231\
160
‘
CONTROL
93/
l
“
\101A
/13
STACK‘(816)
91/
X
V
PROGRAM
V
1110
MEMORY
61
DATA
/
81% 11
TREGZ
11
112501
11
49\ TRECO
195
53\
11 11 11
1
MULTIPLIER
27/’
11
[15 185
1
\ MUX A197
V
1
\ MUX A211
1
-/_1HD
‘ V
\
‘1
1
'
PC (16)
/
PREG (32)
‘ ~ BPR (32)
/
1
73A MUX / COUNT \199
51
3
0
"MUX
E
191
‘
<
P
65/
"
P_SCALER
\
1
51f
=
_
101D/
PRESCALER
g
S
ACCB (32)
~
169
1 MUX
‘7 V
77 ,/
CALL RET
1
225/
1A0 [ACK
1
1
1
PIPELINE
I’—.>
CONTROLLER
:*
_
ACC (32)
23
1
Y
POST—SCALER \181
ALU,MULT---PLU,ARAU---,MUXES
2211 1 1 1
DECODER PLA E‘
v
‘
VJ
TO P10. 111
U.S. Patent
0111. 30, 2001
Sheet 2 of 18
US 6,311,264 B1
FROM [10. 10
,N
N‘
= DBMR f223
101D\.
_/111D
‘
241
/
BlM
R
=
k
‘
V
DATA
153
144
\1 11
MUX
1
CBER
lNDX
1
ARCR
\
MUX
V
CBSR \ MUX A126
\
157
159
115
/
W
5
2
11
£— g
DP|(9) DMA(|7)
11 /
_ AUXREGS
7 (8x16)
11
= =
‘
145
IR
\1 1 v 1
ARP
s
E
x13
1
/
\
\
125
127
ARB
/
148
121/
CORE REGISTER
ADR DEcoDER
I:
y
\
DATA ADDRESS
\
1
MEMORY—MAPPED REGISTERS
>
5T0
ST1
PMST
1MR
IFR
GREG
RPTC
DBMR
CBCR
BRCR
PASR
PAER
\85
FIG.
‘
\
~ DATA MEMORY
25
7b
U.S. Patent
0111. 30, 2001
Sheet 3 of 18
US 6,311,264 B1
305
\.
301
A
5-’
'
DSP
CPU
~5- :
T -
I_1
F '
_
41
11
3
RELAYS
500
INDUSTRIAL
PROCESS AND
_
PROTECTIVE
i——/—’C&
\
9
'
O f
MOTOR
i
PLU = =3 -
303
CONTROL
313
H
SOLENOID
V
VALVE
507
\315
FIG. 2
321
\‘
325\
f“
/
/4 _I\\/
E
\\
\
© \11
323
375w,
1 \@
327
329
\ I}
I}
BRAKES
ENGINE
ANTI-SKID
CONTROL
\
\
373
381
I}
583\
331
SUSPENSION f335
—ACTIVE—
€M571
I
IAIBICIDIEIFICIHIIIJIKILIMINI
31;
BIT MANIPULATION
4I
/
V
ISSIDi’ PLU +36ID
PARALLEL COMPUTATION
FIG. 3
_
U.S. Patent
0a. 30, 2001
REFERENCE r(IT)
Sheet 4 0f 18
401
403
405
406
\
/
/
/
DIGITAL
INPUT
US 6,311,264 B1
u(n)_ ZOH HIT)~ (DC SERVO) y(il)_ DISK‘
CONTROLLER
(D/A)
(MOTOR)
DRIVE
A
/"
W
400
SAMPLER
(A/D)
*
SENSOR
FIG.
REFERENCE
INPUT
\
407
4
421
423
\
/
STATE
“(0)
_
T
_’ CONTROLLER
MOTOR
‘ “ L TORQUE, X 4
_I
CURRENT, x 3
SPEED, x 2
POSITION, X 1
FIG. 5
441
451
\ D/A
U(n)
/
A/D
ZERO
‘
435
ORDER
f433
~
MOTOR
=
HOLD
40/0
SAMPLER
\
STATE
REFERENCE
INPUT
‘ CONTROLLER
459
_ VELOCITY
WT
‘ POSITION
ESTIMATOR
_ CURRENT
4L7
FIG. 6
‘
_ VELOCITY
U.S. Patent
Oct. 30, 2001
Sheet 8 0f 18
6%‘
US 6,311,264 B1
ROM
H
‘
/
619
607.1
G
21
ALU
'
-
MULT f53 ‘ A
I
I
‘
VIDEO
'
DISPLAY
CONVERTER
g}
INTV
6O7.n
;£__I
6/15
ADR
123’
4 : [/0
I
CONTROL
V
\
621
A
V
RAM
A2
FI G.
74
5‘
\605
A3‘
531
HOST
11
11
a
I
t
I
PIXEL
A555
PROCESSING
/
559\
NUMERIC
PROCESSING
V
ggg?‘gg
r
f655
637“ CRT CONTROL
V
V
FRAME BUFFER
DISPLAY
I
543/’
/
SHIFT
_
SHIFT
_
COLOR
REGISTER
'
REGISTER
'
PALETTE
TMS3407O
TMS4161
\649
FIG.
15
\647
U.S. Patent
0111. 30, 2001
Sheet 9 0f 18
653
655
\
/
DSP
CONTROL
GSP
HOST _ >
,up
ADDRESS
Mp
DATA
‘
_’ INTERFACE
f
_
COLOR
*
651
_+
A
V
661
i
MEMORY
11
V
1
V
‘ '
PROM (TBP38L165)
EPRoM
(TMS27C256)
SRAM (2K x a)
J
659
6/57
DISPLAY
6?]
1_]_
US 6,311,264 B1
PALETTE
\647
TMS3407O
M
I '
DRAM J
VRAM ‘LX665
TMS4256
TMS4461
FIG.
76
711
7/17
“
719
\ _ SPEECH
I
SYNTHESIZER
713\
RoM
~ >
_
DOCUMENT
>
721
723
701
S/H -» A/D W
W W
7
703
RECOCNITION—>
~
DSP
/
/
/
705
707
709
+@WU
751
MOTgRS
_ ~ COf/TFROL _> VALVES,’
743
‘
ETC.
\
l/
I
E
_
729
INPUT
PATTERN
TOP-DOWN
SYSTEM
RECOG'N
PROCESSOR
‘
~
D A
_
/\
737
LEXICAL
745
‘
FIG.
77
v
ACCESS
\739
U.S. Patent
0111. 30, 2001
Sheet 10 of 18
US 6,311,264 B1
771
779\
MODEM
#C
E """""""" ""1
l A/D D/A SERIAL
1
TCM29C13
I
I
DATA
~
|
L082
1
LM386
:
II
11
i
_
osp
1
7
IIC
I
:
I
1
DSP
1
I
III;
I
\
1
783
I
781
I
:l
\
"
I
775
DAA
l
111393 \787
l SERIAL
|
1
ANALOG
LINE
l
ENCRYPT
l
1
T
1
/
l:
I
T
|
\785
%
VOCODER
T --
V
|
TLO82
\
1
LM386
777
I
____ ____|
i
I
l
L.
_
_
_
_
_ _
_ _
_
_ _
_ _
_ ___l
775 $
FIG
78
TELEPHONE
LINE
FlG.19axxxxxx
Fla
79b
7
x
x
x
x
x :>T011E11
F[G_79CX11X1XSET
FfG79dxooxoxc1EAR
FIG.
792
X
7
7
x
7
x
DSP "C
DATA_ TCM29C13
—TOGCLE
FIG. 79f
T————co1/1PARE—>Tc
FIG. 79g
'—-— TEST BIT —>
\
U.S. Patent
0a. 30, 2001
Sheet 12 of 18
US 6,311,264 B1
CPU READ
IACK
INPUT
MAIN
. REGISTER
A
CPU WRITE’? “
RETE
‘
~
1/
= Q
855/ OE
—I
D
l/
COUNTERPART
REGISTER
867
INPUT
MUX
SEL
ISR
CPU WRITE
U
FIG. 23
OUTPUT
U.S. Patent
R—DY
0a. 30, 2001
Sheet 14 of 18
>
US 6,311,264 B1
'
DATA ADDRESS
9/71
\
’
978
SEL
A
‘
3
M88
/+—’
1,
973
‘HA
wA|T sTATE
GENERATOR
4-BlT COUNTER
DECODER
/
v
k
977 A,
959/
974
o,
\—>
PWSRO
> ’
L—-—->
PWSR1
>
PERIPHERAL
\--~>
DWSRO
>
ADDR BUS
\____>
DWSR1
:
;>
\-—>
IWSRO
|WSR1
=
>
;> lWSR2
=
/
lWSR3
FIG-
=
A
V
TN
V
975 DATA D” H/m
<
>
981% START )
983
‘F
CRGT,
CRLT?
N0
vYES
985\
STORE ALU To ACCUM
987 \
SELECT ACCB
$
A
COACTIVELY OP ALU TO
989/
COMPARE ACC TO ACCB
A
991 / SUPPLY GTR/LSR TO ACCB
NO
FIG. 28
993
995/
YES
STORE MAX/MIN
L_—______
27
U.S. Patent
0a. 30, 2001
Sheet 15 of 18
US 6,311,264 B1
PIPELINE
CYCLE
I
2
3
4
5
6
7
‘I | FETCH |DEc0DE| READ |ExECLITE|
2
INSTRUCTIONS 3
| FETCH |DECODE| READ IEXECUTE
| FETCH |DECODE| READ |ExECuTE|
4
5
| FETCH |DECODE| READ lExEcuTEl
| FETCH |DEC0DE| READ |
FI G. 29
CONDITIONAL INSTRUCTION
PIPELINE\
A
B
C
D
_D
USES
Nop I CYCLE
C0NDITI0NAL INSTRUCTION
/ (PIPELINE HIT)
A
B
C
D
LOSES
4 CYCLE
SAVINGS: 3 CYCLES
F1G. 30
I005 I085
EH A/D
IR
I
2]
:sOCESSOR
\ MULT
1001
I02I
A _ $0M
CDND
"
INSTR
22\5
CONTROL
ACC \23 ‘
‘I
vIDE0
CI<T
ll
1007/ 001 @1009
‘
I023
STATUS’
BITS
MASK’
BITS
I
\
DECEIDER
\
I026
FIG 37
221
U.S. Patent
061. 30, 2001
Sheet 16 0f 18
Bcnd INSTRUCTION
ACC=O AGG<0 OVERFLOW CARRY
STATUS
BITS
MASK
MANY SHORT ‘NSTRUCHONS
1
O
O
1 fmz]
2
L
v
c
1
1
1
1
1
1
0
1
BITS
1 | | | l
1
—
1 |
/
\
‘
LARGER DECODER
\1023
1
US 6,311,264 B1
FIG
33
1
(z AAEv CARRY)
FI G. 32
ONE LoNGER INSTRUCTION
\. Bcnd
53m
51\
STATUS 1921 MASK 1923
lllil-W 1J1 I | l l'—lR
MEM
SMALLER
A
DECODER
225/ CONT’L < BRANCH
ACC
=
Op CKT \_
1025
CLK
A
1
5
I
v
17/
1027
MUX
(ARR)
FIG.
34
PROGRAM COUNTER \93
(ACC=O)
103“
1033.1
(ACC<O)
'2
1033.2
STATUSZgmj
STATUSLEMAQ
MASKL-———————
/
OVERFLOW
10313
1033.3
LOG'C QBRANCH
swusvlkj
Log
MASKV——1—_
CARRY
0314
1033.4
s1A1usc::\:1g_l_o~6_
MAsKG—--——_
FIG.
35
U.S. Patent
0a. 30, 2001
Sheet 18 of 18
TART
63 Q
\
:>
US 6,311,264 B1
IO5I
I:
LOAD CKT.BDS.
SUPPLY
A
1077
I
21>
LOAD KEYLESS
DEVICES
I
1065/
1067
/
REORIENT
AOL/ICES
/
I
OPERATE MACHINE
I
1069/
SOCKET DEVICES
I
1071/ ENERGIZE ASSEMBLIES
FIG.
39
DISABLED? YES
I073
\
NO
1075 X PASS ON E>ASSEMBLIES
_
J.-
L
VccVcc
0—FF
‘
I
?>QO0CEOOOCP
T
I
]
UL?
F1047
g
g
OOOOO
I
I
F1043