DS33Z41DK Ethernet Transport Design Kit

DS33Z41DK
Ethernet Transport Design Kit
www.maxim-ic.com
GENERAL DESCRIPTION
FEATURES
The DS33Z41 design kit is an easy-to-use evaluation
board for the DS33Z41 Ethernet transport-over-serial
link device. The DS33Z41DK is intended to be used
with a resource card for the serial link. The serial link
resource cards are complete with transceivers,
transformers, and network connections. Dallas’
ChipView software is provided with the design kit,
giving point-and-click access to configuration and
status registers from a Windows®-based PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
Demonstrates Key Functions of DS33Z41
Ethernet Transport Chipset
Includes Resource Card for DS21458 T1/E1
quad Transceiver with Transformers, RJ48
Network Connectors, and Termination
Provides Support for Hardware and Software
Modes
On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
the DS33Z41 Register Set
All DS33Z41 Interface Pins are Easily
Accessible for External Data Source/Sink
LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status
Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
Windows is a registered trademark of Microsoft Corp.
ORDERING INFORMATION
PART
DESCRIPTION
DS33Z41DK
DS33Z41 demo card, T1/E1 transceiver
resource card included
DESIGN KIT CONTENTS
•
•
•
1 of 44
DS33Z41DK Main Board
Quad-Port Serial Card with DS21458 T1/E1
CD_ROM
o ChipView Software and Manual
o DS33Z41DK Data Sheet
o Configuration Files
REV: 110106
DS33Z41DK
TABLE OF CONTENTS
GENERAL DESCRIPTION ..........................................................................................................1
ORDERING INFORMATION .......................................................................................................1
DESIGN KIT CONTENTS............................................................................................................1
COMPONENT LIST .....................................................................................................................3
PC BOARD ERRATA ..................................................................................................................9
FILE LOCATIONS .......................................................................................................................9
BASIC OPERATION..................................................................................................................10
POWERING UP THE DESIGN KIT ...............................................................................................................10
General ............................................................................................................................................................... 10
BASIC DS33Z41 INITIALIZATION (USED FOR ALL QUICK SETUPS) .............................................................10
Quick Setup #1 (Device Driver + DS21458 T1/E1) ............................................................................................ 11
Quick Setup #2 (DS21458 T1/E1, Register Based) ........................................................................................... 11
Configuration Note: Using a Single System ....................................................................................................... 11
Configuration Note: A Mixing Device Driver and Register-Based Modes .......................................................... 11
CONFIGURATION SWITCHES AND JUMPERS......................................................................12
ADDRESS MAP (ALL CARDS) ................................................................................................14
QUAD T1/E1 RESOURCE CARD FPGA REGISTER MAP ............................................................................14
ID REGISTERS..........................................................................................................................14
CONTROL REGISTERS ....................................................................................................................... 15
DS33Z41 INFORMATION..........................................................................................................16
DS33Z41DK INFORMATION ....................................................................................................16
TECHNICAL SUPPORT ............................................................................................................16
DOCUMENT REVISION HISTORY ...........................................................................................16
SCHEMATICS ...........................................................................................................................17
LIST OF FIGURES
Figure 1. System Floorplan.......................................................................................................................................... 8
Figure 2. DS21458 Resource Card Floorplan ............................................................................................................. 8
Figure 3. Schematic Hierarchy and Floorplan ........................................................................................................... 17
LIST OF TABLES
Table 1. Component List (Decoupling Caps Not Shown)............................................................................................ 3
Table 2. Main Board PC Board Configuration ........................................................................................................... 12
Table 3. Overview of Daughter Card Address Map................................................................................................... 14
Table 4. Quad T1/E1 Processor Card FPGA Register Map...................................................................................... 14
2 of 44
DS33Z41DK
COMPONENT LIST
Table 1 shows the component list for the DS33Z44 and DS33Z11/DS33Z41 design kits and resource cards. This
BOM contains the part listing for five boards. These boards are the DS33Z41DK, DS33Z44DK, DS21458RC,
DS3174RC, and DS2155-DS21348-DS3170RC. Each reference designator is only used once. For example, U18
only appears on the DS33Z41DK and is not used on any of the other boards. See Table 2.
Table 1. Component List (Decoupling Caps Not Shown)
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
U18
1
ELITE 10/100 ETHERNET TRANSPORT OVER
SERIAL LINK 14X14 CSBGA 169 PIN
Dallas Semiconductor
DS33Z41
U20
1
3.3V T1.E1.J1 QUAD TRANSCEIVER 0-70C 256P
BGA
Dallas Semiconductor
DS21458
U22
1
QUAD 10/100 ETHERNET EXTENSION TO WAN
17X17 PBGA 256 PIN
Dallas Semiconductor
DS33Z44
U23
1
DS3/E3 SCT, 11X11 CSBGA, 100 PIN
Dallas Semiconductor
DS3170
U24
1
T1/E1/J1 XCVR 100P QFP 0-70C
Dallas Semiconductor
DS2156L
U25
1
3.3V LIU
Dallas Semiconductor
DS21348
UB08
1
QUAD TRIPLE DUAL SINGLE ATM PACKET PHYS
FOR DS3 E3 STS1 0-70C 400P BGA
Dallas Semiconductor
DS3184
U01, U09
2
SOIC 8PIN STEP-UP DC-DC CONVERTER 0.5A
LIMIT
Maxim
MAX1675EUA
U07, U11
2
8-Pin μMAX/SOIC 1.8V or Adj
Maxim
MAX1792EUA18
U13, UB01
2
MICROPROCESSOR VOLTAGE MONITOR, 2.93V
RESET, 4PIN SOT143
Maxim
MAX811SEUS-T
U21, UB07
2
Dual RS-232 transceivers with 3.3V/5V internal
capacitors
MAXIM
NA
U31, UB06, UB11
3
8-Pin μMAX/SOIC 2.5V or Adj
Maxim
MAX1792EUA25
C11, C13, C16, C25, C27,
C31–C35, C37, C41, C47,
CB10, CB63, CB114, CB128,
CB164, CB496
19
1206 CERAM 10uF 10V 20%
Panasonic
ECJ-3YB1A106M
CB390, CB391, CB395, CB396
4
1206 CERAM 0.1uF 25V 10%
Panasonic
ECJ-3VB1E104K
D01–D03, D05, DB03–DB05
DS01, DS07, DS10–DS12,
DS17, DS20
DS02, DS03, DS09, DS14,
DS15
7
SCHOTTKY DIODE, 1 AMP 40 VOLT
International Rectifier
10BQ040
7
LED, AMBER, SMD
Panasonic
LN1451C
5
L_LED, GREEN, SMD
Panasonic
LN1351C
13
LED, RED, SMD
Panasonic
LN1251C
2
LED, GREEN, SMD
Panasonic
LN1351C
19
L_LED, RED, SMD
Panasonic
LN1251C
76
STANDARD GROUND CLIP
KEYSTONE
4954
8
KIT, 4-40 HARDWARE, .50 NYLON STANDOFF AND
NYLON HEX-NUT
NA
Lab Stock
DS04–DS06, DS08, DS13,
DS16, DS18, DS27, DS28,
DS35, DS37, DS38, DS40
DS19, DS43
DS21–DS26, DS30, DS32–
DS34, DS36, DS39, DS41,
DS42, DS44–DS48
GND_TP01–GND_TP07,
GND_TP09-–GND_TP44,
GND_TP46–GND_TP68,
GND_TPB01–GND_TPB10
H1–H8, H17–H19
3 of 44
DS33Z41DK
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
H9–H16
16
KIT, 4-40 HARDWARE, 1.12 NYLON STANDOFF
AND NYLON HEX-NUT (1.12 STANDOFF PN =
4807K-ND)
NA
Lab Stock
J01–J05
5
CONNECTOR, FASTJACK SINGLE, 8 PIN
Halo Electronics
HFJ11-2450E
J06, J41
2
100 MIL 2*7 POS JUMPER
NA
Lab Stock
J07–J12
6
RECEPTACLE, SMD, 140 PIN, .8MM, 2 ROW
VERTICAL
AMP
5-179010-6
J13–J22
10
L_TERMINAL STRIP, 10 PIN, DUAL ROW, VERT DO
NOT POPLUATE
NA
Lab Stock
J23, J29, J32, J38, J39, J43,
J44, J47, JB07
9
L_TERMINAL STRIP, SHROUDED, 10 PIN, DUAL
ROW, VERT
3M Electronics
2510-6002UB
J24, J30, J31, J33
4
100 MIL 2 POS JUMPER
NA
Lab Stock
J25, J26, J45, J46
4
TERMINAL STRIP, 10 PIN, DUAL ROW, VERT
NA
Lab Stock
J27, J42
2
CONN 50 PIN, 2 ROW, POSTS VERT,
MOTHERBOARD FOOTPRINT
SAMTEC
TSW-125-07-T-D
J28, J36
2
L_CONN, DB9 RA, LONG CASE
AMP
747459-1
J48, J54, JB01
3
SOCKET, BANANA PLUG, HORIZONTAL, BLACK
Mouser Electronics
164-6218
J49–J52
4
CONNECTOR BNC 75 OHM VERTICAL 5PIN
Cambridge
CP-BNCPC-004
J53, JB02, JB08
3
SOCKET, BANANA PLUG, HORIZONTAL, RED
Mouser Electronics
164-6219
J55, JB11
2
L_RJ48 8 PIN SINGLE PORT CONNECTOR
MOLEX
15-43-8588
J56–J59, J61, J63
6
CONNECTOR BNC 75 OHM RA 5PIN
Trompetor
UCBJR220
J60, J62, J64, J65
4
CONNECTOR BNC RA 5PIN
Trompetor
UCBJR220
JB05, JB06, JB09, JB10, JB13,
JB14
6
PLUG, SMD, 140 PIN, .8MM, 2 ROW VERTICAL
AMP
179031-6
JB12
1
RA RJ45 8PIN 4PORT JACK
MOL
43223-8140
JP01–JP19
19
100 MIL 3 POS JUMPER
NA
NA
L01, L03–L08, LB01, LB02
9
FERRITE 3A 100 OHM AT 100 MHZ 1206 SMD
Steward
HI1206N101R-00
L02, L09
2
INDUCTOR 22.0uH 2PIN SMT 20%
Coiltronics
UP1B-220
L10
1
XFMR 1-2CT XMIT, 1-1CT RCV, 40P WIDE SOIC
Pulse
T1068
10
RES 0603 54.9 Ohm 1/16W 1%
Panasonic
ERJ-3EKF54R9V
10
RES 0603 49.9 Ohm 1/16W 1%
Panasonic
ERJ-3EKF49R9V
R05, R06, R08, R09, R11
5
RES 0603 10.0K Ohm 1/16W 1% - Must be 1%
tolerance
Panasonic
ERJ-3EKF1002V
R07, R12, R16, R79, R160,
R244, R248, R250, R251,
R254, R255, RB126, RB143,
RB147, RB150, RB157
16
RES 0603 1.0K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ102V
R10, R107
2
RES 1206 5.6 Ohm 1/8W 5%
Panasonic
ERJ8GEYJ5R6V
R132, R137, R142, R144,
R156, RB194, RB208, RB227
8
L_RES 0603 0 Ohm 1/16W 1%
AVX
CJ10-000F
R01, R02, RB10, RB11, RB18,
RB19, RB22, RB23, RB26,
RB27
R03, R04, RB12, RB13, RB20,
RB21, RB24, RB25, RB28,
RB29
4 of 44
DS33Z41DK
DESIGNATION
QTY
R13–R15, R18–R20, R22, R23,
R29, R30, RB01, RB03, RB07,
RB09, RB15–RB17, RB30–
RB32, RB34–RB38, RB41,
RB44, RB47, RB48, RB50–
RB52, B55, RB60, RB62, RB72,
RB73, RB75, RB80, RB82
40
RES 0603 5.1K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ512V
104
RES 0603 30 Ohm 1/16W
Panasonic
ERJ-3GEYJ300V
8
L_RES 0805 0.0 Ohm 1/10W 5%
Panasonic
ERJ6GEY0R00V
10
RES 0603 332 Ohm 1/16W 1%
Panasonic
ERJ-3EKF3320V
16
RES 1206 0 Ohm 1/8W 5%
Panasonic
2
RES 0805 51.1 Ohm 1/10W 1%
Panasonic
ERJ8GEYJ0R00V
ERJ-6ENF51R1V
R24, R114, R197, RB14, RB33,
RB40, RB42, RB43, RB49,
RB53, RB54, RB57–RB59,
RB71, RB77, RB78, RB152–
RB156, RB221, RB234, RB251,
RB284, RB304, RB331, RB332,
RB342, RB344, RB350, RB354,
RB360
34
L_RES 0603 330 Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ331V
R242, R243, RB144, RB166,
RB355–RB358, RB368–RB371
12
RES 0603 51 Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ510V
13
RES 0603 330 Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ331V
152
RES 0402 30 Ohm 1/16W 5%
Panasonic
ERJ-2GEJ300X
2
RES 0603 1.0M Ohm 1/16W 5%
Panasonic
R77, RB159
2
L_RES 1206 0 Ohm 1/8W 5%
Panasonic
ERJ-3GEYJ105V
ERJ8GEYJ0R00V
R80, R81, R84, R87, R89, R91–
R93, R95, R108, R110, R118,
R127, R152, R153, R196,
R209, R214, R229–R236,
RB200, RB237, RB238, RB263,
RB264, RB286, RB287, RB300,
RB301, RB333, RB364
37
RES 0603 10K Ohm 1/16W 5%
Panasonic
R17, R21, R25–R28, R31, R55,
R57–R59, R71, R74–R76, R83,
R96–R102, R105, R106, R109,
R111, R112, R115–R117,
R120, R122–R126, R128,
R133, R134, R140, R141,
RB61, RB96, RB97, RB99,
RB100, RB102–RB110, RB112,
RB114–RB119, RB121,
RB123–RB125, RB127, RB128,
RB130, RB131, RB133,
RB135–RB138, RB145, RB148,
RB149, RB160, RB161, RB164,
RB165, RB167–RB171,
RB173–RB181, RB184, RB187,
RB311, RB320, RB335, RB339,
RB359
R171, R172, R174, R175,
R190, R191, R240, R241
R198–R200, R210–R213,
RB306, RB325, RB326
R201–R208, RB321–RB324,
RB327–RB330
R239, RB349
R32, R70, R78, R161, R176,
R194, R195, R237, R238,
RB129, RB134, RB146, RB193
R33–R54, R60–R69, R72, R73,
R131, R136, R143, R147,
R150, R154, R158, R163,
R166, R169, R173, R178–
R189, R215–R228, RB89–
RB95, RB101, RB188–RB191,
RB196–RB199, RB202–RB205,
RB210–RB213, RB216–RB219,
RB223–RB226, RB230–RB233,
RB239–RB242, RB244–RB249,
RB252–RB260, RB265–RB268,
RB270-RB282, RB289–RB297
R56, R90
DESCRIPTION
5 of 44
SUPPLIER
PART
ERJ-3GEYJ103V
DS33Z41DK
DESIGNATION
QTY
DESCRIPTION
SUPPLIER
PART
R85, R88, R94, R104, R113,
RB02, RB04–RB06, RB08,
RB39, RB45, RB46, RB56,
RB63–RB70, RB76, RB83,
RB98, RB183, RB185, RB192,
RB209, RB228, RB302, RB303,
RB305, RB338, RB340, RB341,
RB346–RB348, RB351–RB353,
RB361–RB363, RB365–RB367
48
RES 0603 2.0K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ202V
R86, R103, R119, R121, R129,
R130, R135, R138, R139,
R145, R146, R149, R151,
R157, R162, R164, R167,
R168, R170, R177, R192,
R193, R245-R247, R249, R252,
R253, R256, R257, RB74,
RB79, RB132, RB139-RB141,
RB151, RB162, RB163, RB172,
RB182, RB186, RB206, RB207,
RB214, RB215, RB220, RB222,
RB229, RB235, RB236, RB243,
RB250, RB261, RB262, RB269,
RB308–RB310, RB343, RB345
61
L_RES 0603 10K Ohm 1/16W 5%
Panasonic
ERJ-3GEYJ103V
RB201, RB285
2
RES 0805 330 Ohm 1/10W 5%
Panasonic
ERJ-6GEYJ331V
RB283
1
RES 0603 10K Ohm 1/10W 5% - SEE SPECIAL
INSTRUCTIONS
Panasonic
603_ERJ3GEYJ103V
RB298, RB299, RB312–RB319,
RB336, RB337
12
RES 0805 61.9 Ohm 1/10W 1%
Panasonic
ERJ-6ENF61R9V
RB81, RB84–RB88, RB111,
RB113, RB120, RB122
10
RES 0603 DO NOT POPULATE
NA
NA
SW01–SW05, SW08–SW21,
SW24–SW26, SW29–SW31,
SW33–SW44
37
L_SWITCH, SP3T SLIDE, 4PIN TH
Tyco
3-1437575-3
SW06, SW22
2
L_SWITH 8POS 16PIN DIP LOW PROFILE
AMP
435668-7
SW07, SW23
2
SWITCH MOM 4PIN SINGLE POLE
Panasonic
EVQPAE04M
SW27, SW28, SW32
3
L_DIPSWITCH, 10 POS
AMP
435668-9
T01, T03
2
XFMR 16P SMT
Pulse
TX1099
T02, TB01
2
XFMR, OCTAL T3/E3, 1 TO 2, SMT 32 PIN
Pulse
T3049
TP01–TP78, TPB01, TPB02
80
TESTPOINT, 1 PLATED HOLE, DO NOT STUFF
NA
NA
U02–U06
5
IC, DsPHYTER11-SINGLE 10/100 ETHERNET
TRANSCEIVER, 65 PIN LLP
National
Semiconductor
DP83847ALQA5
6A
U08, U12, U29
3
1MBit Flash based config mem
Avnet
XCF01SV020C
U10
1
XILINX SPARTAN xc200 2.5V FPGA,256 PIN BGA
Xilinx
XC2S2005FG256C
U14, U26, U30, UB05
4
CYPRESS SRAM, LAB STOCK
NA
NA
U15, U19
2
mmc2107 processor
Motorola
MMC2107
U16, U27
2
XILINX SPARTAN 2.5V FPGA,256 PIN BGA
Xilinx
XC2S505FG256C
U17, U28, U32
3
10 pin res pack, 10K ohm
NA
NA
UB02, UB03, UB04
3
100 PIN CPLD
XILINX
XC95144XL10TQ100C
UB09, UB10
2
SYNCHRONOUS DRAM, 1MEGX32X4 BANKS,
TSOP 86 PIN
Micron
MT48LC4M32B2
TG-7
6 of 44
DS33Z41DK
DESIGNATION
QTY
DESCRIPTION
UX01–UX12, UXB02–UXB04,
UXB06–UXB08
18
HIGH SPEED BUFFER
Fairchild
NC7SZ86
UXB01, UXB05
2
HIGH SPEED INVERTER
Fairchild
NC7SZ86
X01, X02
2
XTAL LOW PROFILE 8.0MHZ
ECL
EC1-8.000M
Y01, Y09
2
OSCILLATOR, CRYSTAL CLOCK, 3.3V - 25.000
MHZ, Low Jitter required for PHY
SaRonix
NTH089AA325.000
Y02, Y13
2
SPI SERIAL EEPROM 16K 8 PIN DIP 2.7V NEEDS
SOCKET
Atmel
AT25160A-10PI2.7
Y03
1
OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048 MHZ
SaRonix
NTH039A32.0480
Y05, Y06
2
OSCILLATOR, CRYSTAL CLOCK, 3.3V - 100.000
MHZ
SaRonix
NTH089A3100.0000
Y07
1
OSCILLATOR, CRYSTAL CLOCK, 3.3V - 44.736 MHZ
SaRonix
NTH089AA344.736
Y08
1
OSCILLATOR, CRYSTAL CLOCK, 5.0V - 44.736 MHZ
SaRonix
NTH089AA44.736
YB02
1
L_OSCILLATOR, CRYSTAL CLOCK, 3.3V - 2.048
MHZ
SaRonix
NTH039A32.0480
7 of 44
SUPPLIER
PART
DS33Z41DK
Figure 1. System Floorplan
DS33Z41 MAINBOARD
LEDS AND TESTPOINTS
DS21458 RESOURCE CARD
(DETAIL PROVIDED BELOW)
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
SDRAM
ETHERNET PHY,
MAGNETIC,
LEDS, AND
JUMPERS
DS33Z41
HARDWARE
MODE SWITCHES
FOR DS33Z41
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
Figure 2 shows the DS21458 quad T1/E1 PC board floorplan. The current configuration is to populate oscillators
for MCLK1 with a 8.192MHz oscillator. Testpoints for port 3 and port 4 are provided on the WAN card, and
testpoints for ports 1 and 2 are provided on the motherboard.
PORT 2
OSC
MCLK1, 2
FPGA
DS21458
QUAD-PORT
T1/E1
TRANSCEIVER
INT LED
QUAD
TRANSFORMER
PORT 4
RLOS LEDS
8 of 44
PORT 1
PORT 3
QUAD-PORT RJ45
TEST POINTS
JTAG
140 PIN CONNECTORS
Figure 2. DS21458 Resource Card Floorplan
DS33Z41DK
PC BOARD ERRATA
•
Silkscreen for JTAG connector signal descriptions is incorrect on the quad T1/E1 card. This should be
corrected with an adhesive label.
FILE LOCATIONS
This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file
from the Maxim website at www.maxim-ic.com/DS33Z41DK.
All locations are given relative to the top directory of the CD/zip file.
•
DS33Z41 register definition files and configuration files:
o .\cfg_demo_gui\DS33Z41_cfg_demo_gui\DS33Z41.def
o .\DS33Z41_cfg_demo_gui\SU_LI_PORT1.def
o .\DS33Z41_cfg_demo_gui\z41_basic.mfg
•
DS21458 register definition files and configuration files:
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\DS21458RC_FPGA.def
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\DS21458RC.def
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\T1_IBO_ LoopTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\T1_IBO_ SourceTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\E1_CRC_HDB3_IBO_ SourceTime.ini
o .\DS33Z41_cfg_demo_gui\Qt1e1_DS21458\E1_CRC_HDB3_IBO_ LoopTime.ini
9 of 44
DS33Z41DK
BASIC OPERATION
Powering Up the Design Kit
•
•
•
Attach DS21458 resource card to main board.
Connect PCB 3.3V and GND banana plugs to power supply. At power-up the system should draw
approximately 1A.
Set switches for software mode as described in Table 2 (short description follows).
• Top left bank: All low, except for MODEC0, which is high.
• Top right bank: A2, A1, A0 in mid position, SCANTRI low
• Bottom Bank: All high (AFCS, FULLDS, H1OS)
General
•
Upon power-up, the processor FPGA Status LEDs (DS43 green) will be lit. Interrupt LEDs (DS44 red) will not
be lit. DS33Z11 Queue overflow LEDs (DS39 red) will not be lit. PHY LINK LED (DS06 green) should be lit if
the Ethernet is connected.
Following are several basic system initializations. These initializations assume that there are two boards present
(DS33Z41 and / or DS33R41). A note is provided below to assist with using a system that only contains one board.
Basic DS33Z41 Initialization (Used for All Quick Setups)
This section covers four basic methods for configuring the DS33Z41. Any one of these initializations can be used
with the following Quick Setup examples:
1. Upon power-up, the on-board device driver provides a basic configuration for the DS33Z41 and attached
serial cards. This enables traffic to pass from the Ethernet port to the serial port. Consult the device driver
documentation for further details. Device driver behavior is dependant upon jumper settings, which are
detailed in Table 2.
2. Launch ChipView.exe and select Register View. When prompted for a definition file, pick the file named
DS33Z41.def. Following this load the definition file named DS21458RC_FPGA.def
3. Hardware Mode is not available with this DK
4. EEPROM mode is not available with this DK.
5. Ethernet Traffic generation and analysis:
a. Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment.
This should cause the link LED to turn on.
b. Although ping is mentioned it is *not* recommended. The ping command goes through the
computers TCPIP stack, and will sometimes will not be sent out the PCs network connector (i.e. if
the PCs ARP cache is out of date). Additionally ping requires two PCs, as a PC can not ping itself
(a local ping gets sent to ‘localhost’ instead of out the connector). With that said – ping is still a
valuable test once the prototyping stage is complete.
c. Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A timelimited demo is available at the website www.tamos.com/products/commview.
d. Ethereal is an excellent (and free) packet capture utility. Download is available at
www.ethereal.com.
e. Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used.
This allows for end-to-end testing using a single PC. When using two adapters the PC will have a
different IP address for each adapter. Test equipment will allow selection of either adapter.
Operating system based network traffic will be sent out the default adapter, usually this is the
adapter that has recently had connection to a real network.
10 of 44
DS33Z41DK
Quick Setup #1 (Device Driver + DS21458 T1/E1)
•
•
•
•
•
Select TCLK source for the DS21458 resource card. If this is the only DS33Z41 in the system (i.e. used in
loopback) then select TCLK=MCLK. From Table 2, this requires that the J45.3+J45.4 jumper is not installed. If
this is the second DS33Z41 in the system select TCLK=RCLK, which requires that J45.3+J45.4 jumper is
installed. Note: The TCLK source settings can be changed using the driver interface, which is described
below.
Complete the hardware configuration and one of the basic DS33Z41 configurations as described in the
previous section.
At this point any packets sent to the DS33Z41 are sent out the T1/E1 ports. Incoming Ethernet packets should
cause the RX LED to blink, transmitted packets cause the TX LED should also blink.
Launch ChipView.exe, select Register View
To interact with the device driver go to ChipView and select from the drop down menu:
• Tools→Plugins→Load Plugins. When asked if DLLs have already registered select yes
• Select Tools→Plugins→DS33Z41/11/41 Device Driver Demo
• A new form called ‘Zchip Configuration’ appears
• Preload basic configuration for the GUI by selecting File→Load Settings (in the ‘Zchip Configuration’ form).
Select the file named ‘basic_Config.eset’
Quick Setup #2 (DS21458 T1/E1, Register Based)
1. Disable device drivers and callbacks – remove all jumpers from J45 header. Press the reset button, or cycle
power on the board to restore the system to its power-on state.
2. Configure the DS33Z41. After the definition files load, go to the File menu and select File→Memory Config
File→Load .MFG file. When prompted, select the file named z41_basic.mfg.
3. Set the DS2148 serial card for IBO mode. Using the menu marked ‘Def File Selection’ switch to the
DS21458RC_FPGA def file. Set the register MO+CLK to 0x47.
4. Configure the DS21458. Go to the File menu and select File→Register INI File→Load .INI file. When
prompted, select either the file named T1_IBO_ SourceTime.ini (TCLK=MCLK) or T1_IBO_ LoopTime.ini
(TCLK=RCLK). Set one board to be the source of network timing (TCLK=MCLK), and one board to follow the
timing source (TCLK=RCLK). The RLOS LEDs should go out when this step is complete for both boards.
5. Additional setup (for both boards):
• Switch to the DS33Z41 def file and set the following:
• Set the GL.IMUXCN register to 0x0F (both systems)
• Set GL.IMUXC register to 0x00 then to 0x82 (both systems)
• Check GL.IMUXSS register. They should be 0xFF on both systems
• Return to GL.IMUXCN and set the bits RXE and SENDE
• The system should now be configured to pass Ethernet traffic into one system and out of the other.
Configuration Note: Using a Single System
The DS33Z41 is intended for use in a system with a DS33Z41 at each end. However, the system may be tested
with only a single DS33Z41 system. This configuration requires that the DS21458 serial link is in loopback, either
internal loopback or hardware loopback may be used. In this configuration any packets sent to the Ethernet side
will be echoed back. In this configuration the setting for DS21458 TCLK=MCLK should be used (see Table 2) and
steps intended for the “second” system may be ignored.
Configuration Note: A Mixing Device Driver and Register-Based Modes
Quick setup #1 discuses device driver based operation. Quick setup #2 discusses register based operation. To
some extent both modes may be used simultaneously to gain insight to device configuration. For example:
• In register view click “Read All” this causes all registers to be read, changed registers turn green.
• Switch to the device driver GUI, select one of the forms, make changes, and click “send configuration”
• Switch back to register view and click “Read All”. Newly changed registers will turn green, showing which
registers changed as a result of settings selected in the device driver GUI
A second type of device driver/register-based configuration is to power the board with the device drivers enabled,
and then remove the jumpers that enable the device drivers. This allows for a fast initial configuration.
11 of 44
DS33Z41DK
CONFIGURATION SWITCHES AND JUMPERS
The DS33Z41DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).
Table 2. Main Board PC Board Configuration
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SW MODE
DESCRIPTION
HW MODE
This jumper is not for use with
the DS33Z41 design kit. Pin
J25.10 has been removed to
prevent accidental installation
When installed the device driver
will configure the DS33Z41 and
the Transceiver during power-up.
When installed the driver will
respond to interrupts
When installed the driver will
configure DS21458 TCLK to be
sourced from DS21458 RCLK.
When not installed DS21458
scaled MCLK is used. This
setting is only applied at reset. If
only one board is used select
TCLK = MCLK.
System Ground. Always
connected to power supply.
System VDD. Always connected
to power supply.
Debug connector for processor
J45.9 + J45.10
Reserved
Not installed
—
J45.7 + J45.8
Enable device driver
User decision
—
J45.5 + J45.6
Enable callbacks
User decision
—
J45.3 + J45.4
Select TCLK source
User decision
—
Power supply ground
—
—
Power supply VDD
—
—
BDM
DS33Z41 mode pin;
DTE/DCE selection
—
—
LOW
LOW
Low for DTE
DS33Z41 mode pin
LOW
LOW
High for RMII, low for MII
DS33Z41 mode pin
LOW
LOW
SPI EEPROM hardware mode
configuration switch
DS33Z41 mode pin
HIGH
LOW
Software mode selected
DS33Z41 mode pin
LOW
LOW
Software mode selected
DS33Z41 mode pin
LOW
LOW
Hardware/software mode
(software mode selected)
DS33Z41 mode pin
LOW
LOW
Set low for normal operation
DS33Z41 mode pin
LOW
LOW
Set low for normal operation
….testpoints….
DS33Z41 testpoints
—
—
Z-RESET (button)
DS33Z41 reset
—
—
A2, A1, A0
(3pos switches)
DS33Z41/SPI pins
Mid position
Mid position
SDRAM CLOCK
DS33Z41 SDRAM
clock
Installed
Installed
MII CLOCK
PHY MII clock
Installed
Installed
GROUND
(banana plug)
VDD 3.3V
(banana plug)
OnCe
DCEDTES
(3pos switch)
RMIIMII
(3pos switch)
CKPHA
(3pos switch)
MODEC0
(3pos switch)
MODEC1
(3pos switch)
HWMODE
(3pos switch)
SCANMO
(3pos switch)
SCANTRI
(3pos switch)
12 of 44
Processor bus, JTAG and LAN
side testpoints for Zchip
System reset
Address pin/EEPROM config
switch. Set to mid position to
allow connection to processor.
100MHz oscillator to drive
SDRAM clock
25MHz oscillator to drive SDRAM
clock
DS33Z41DK
SILKSCREEN
REFERENCE
FUNCTION
BASIC SETTING
SW MODE
HW MODE
DESCRIPTION
spi_cs, spi_ck,
spi_miso,
spi_mosi
….testpoints…..
AFCS
(1 per port)
—
—
—
DS33Z41 testpoints
—
—
DS33Z41 mode pin
HW mode only
HIGH
FULLDS
(1 per port)
DS33Z41 mode pin
HW mode only
HIGH
Set high to enable full duplex.
H10S
(1 per port)
DS33Z41 mode pin
HW mode only
HIGH
Set high to confg for 100Mb.
GROUND/VDD
(banana plug)
Power supply
ground/3.3V
—
—
VDD 3.3V
(banana plug)
Power supply VDD
—
—
13 of 44
SPI signals (for EEPROM
memory)
DS33Z41 serial port testpoints
Set high to enable auto flow
control.
Redundant connection to system
power. Use plugs at either top or
bottom of board.
Redundant connection to system
power. Use plugs at either top or
bottom of board.
DS33Z41DK
ADDRESS MAP (ALL CARDS)
Motorola resource card address space begins at 0x81000000. All offsets given below are relative to the beginning
of the daughter card address space (shown previously).
Table 3. Overview of Daughter Card Address Map
OFFSET
DEVICE
0X0000 to
0X0087
FPGA
0X1000 to
0X1FFF
DS33Z41
DS33Z41. Uses CS_X1.
0X2000 to
0X2FFF
DS21458
T1/E1 DS21458 resource card. Uses CS_X2.
0X4000 to
0X4010
FPGA
DESCRIPTION
Processor board identification
FPGA on DS21458 resource card. Used to facilitate IBO mode.
Default configuration of FPGA is compatible with non-IBO mode
functionality. The FPGA settings will require modification for use
with the DS33Z41 when device drivers are disabled.
Registers in the DS33Z41 and DS21458 can be easily modified using the ChipView host-based user-interface
software with the definition files previously mentioned.
Quad T1/E1 Resource Card FPGA Register Map
Table 4. Quad T1/E1 Processor Card FPGA Register Map
OFFSET
REGISTER
NAME
TYPE
0X4000
0X4001
0X4002
0X4003
0X4004
0X4005
0X4006
0X4007
Rev
delay_line1
delay_line2
delay_line3
delay_line4
MO+CLK
UNUSED
UNUSED
Read only
Control
Control
Control
Control
Control
Control
Control
DESCRIPTION
FPGA Rev
Line 1 number of frame delay
Line 2 number of frame delay
Line 3 number of frame delay
Line 4 number of frame delay
Mode and clock ctrl
Unused / test
Unused / test
ID REGISTERS
REV: FPGA REV (Offset=0X4000)
FPGA Rev is read only, showing the current FPGA revision
14 of 44
DS33Z41DK
CONTROL REGISTERS
Register Name: delay_line1, delay_line2, delay_line3, delay_line4
Register Description: DS33Z41 frame delay
Register Offset: 0X4001, 0X4002, 0X4003, 0X4004
Bit #
Name
Default
7
—
—
6
—
—
5
B5
—
4
B4
—
3
B3
0
2
B2
0
1
B1
0
0
B0
0
Bits 5 to 0: B5 to B0. Number of frame delay for a given line.
Register Name: MO+CLK
Register Description: DS33ZXY Mode and Clock Settings
Register Offset: 0X4005
Bit #
Name
Default
7
LB
0
6
MC
—
5
IR
—
4
tgapclk
1
3
rgapclk
1
2
comm_tclk
0
1
common_rclk
0
0
z41_mode
0
Bit 7: LB
0 = Normal operation, traffic goes from the Z chip through the FPGA and to the DS21458.
1 = Loopback, Z chip rser is driven by Z chip tser. Clocks, and frame sync for Z41, are still driven by DS21458.
Bit 6: INVERT_RCLKh
0 = Do not invert RCLK.
1 = Invert RCLK.
Bit 5: MclkHiBpclkLow
0 = Use BPCLK for clock signals below.
1 = Use MCLK for clock signals below.
This signal drives the following clocks: TCLK (when bit for common_tclk is set); RCLK (when bit for common_rclk is
set); TSYSCLK and RSYSCLK (when bit for Z41_mode is set).
Bit 4: TGAPCLK
0 = Drive internal TGAPCLKx signal with TCLKx.
1 = Drive internal TGAPCLKx signal with TGAPCLK pin.
Bit 3: RGAPCLK
0 = Drive internal RGAPCLKx signal with RCLKx.
1 = Drive internal RGAPCLKx signal with RGAPCLK pin.
Bit 2: Common TCLK
0 = Drive TCLKx with internal TGAPCLKx signal (see bit 4)
1 = Drive Z chip TCLKx with BPCLK
Bit 1: Common RCLK
0 = Drive RCLKx with internal RGAPCLKx signal (see bit 3).
1 = Drive Z chip RCLKx with BPCLK.
Bit 0: Z41 Mode
0 = Not in Z41 mode.
1 = In Z41 mode.
15 of 44
DS33Z41DK
DS33Z41 INFORMATION
For more information about the DS33Z41, consult the DS33Z41 data sheet available on our website at
www.maxim-ic.com/DS33Z41.
DS33Z41DK INFORMATION
For more information about the DS33Z41DK, including software downloads, consult the DS33Z41DK data sheet
available on the our website at www.maxim-ic.com/DS33Z41DK.
TECHNICAL SUPPORT
For additional technical support, go to www.maxim-ic.com/support.
DOCUMENT REVISION HISTORY
REVISION
DATE
051505
DESCRIPTION
Initial DS33Z41DK data sheet release.
080706
Updated Table 2.
110106
Updated schematics.
16 of 44
DS33Z41DK
SCHEMATICS
The DS33Z41DK schematics are featured in the following pages. As this is a hierarchal schematic some
explanation is in order. The main board is composed of six hierarchal blocks: the processor block, the DS33Z41
block, and four Ethernet blocks inside the DS33Z41 block, which is a nested hierarchy block. The DS21458
consists of a single hierarchy block, which connects to a 140-pin AV bus that snaps into the mainboard.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here, blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
This system contained other hierarchy blocks that are not shown (primarily a single-port serial card, T3E3 serial
card and the DS33Z44 mainboard). Due to this, page numbers will not be continuous and some gaps in numbering
will be seen when referring to the total page count. However, page numbers inside any given hierarchy block will
be continuous.
Figure 3. Schematic Hierarchy and Floorplan
ETHERNET PHY
PAGE 8 SYMBOL
DS33Z11 BLOCK
PAGE 3. SYMBOL
SCHEMATIC
PAGES 11-12
SCHEMATIC
PAGES 5-10
SERIAL INTERFACE
2 X 140 PIN CONNECTORS
DS33Z11 MAINBOARD TOP LEVEL SCHEMATIC
DS21458 RESOURCE CARD
SCHEMATIC
PAGES 46-55
µP BLOCK
PAGE 4 SYMBOL
SCHEMATIC
PAGES 13-19
17 of 44
Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.
No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2006 Maxim Integrated Products
The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.
3B5<>
3C8<>
3D8>
4D8>
GND
GND
GND
GND
GND
GND
4D8 3D8
3A8<> 3A5<> V3_3
3C5<> 3B8<>
GND
GND
GND
3C8<>
3A8<>
3B8<>
4D8 3D8 4D8>
8
3C5<>
3A5<> V3_3
3B5<> OSC2_NU
3D8> OSC4_NU
11
7
9
4
GND
GND
4B4> TDI_NU
3D8> 4B4> TMS_NU
3C5<>
3D8 3B5<> 3A8<> 3A5<> V3_3
3B8<>
4D8 3C8<>
0
4D8>
2
GND
3B5<>
3C8<>
GND
GND
GND
V3_3
GND
GND
4D8
3A8<> 3A5<> V3_3
3C5<> 3B8<>
Z44_RCLK<2>
Z44_RDEN<2>
3B8<>
71
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JB13
VDD
3C5<>
7
3C8<> 4D8>
3D8 4D8
6
5
4
7
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Z44_TSER<1>
3A1>
10
3C5<>
3C5<>
3C8<>
3C5<>
3C5<>
3B8<>
3B8<>
3C5<>
3B8<>
3B8<>
3B5<>
3A8<>
3A8<>
3A8<>
4D3>
3A5<>
4C3>
4C3>
6
2
4
BLOCK NAME: _z11top_dn.
6
GND
GND
CS_X2
V3_3
CS_X3
WR_X
OSC1_NU
GND
71
72
73
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JB09
PARENT BLOCK: \_ztopdn_\
5
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
3A5<> V3_3
Z44_RCLK<4>
Z44_RDEN<4>
Z44_RSER<4>
Z44_RCLK<3>
3A8<>
GND
GND
GND
3A5<> V3_3
Z44_RDEN<3>
3B5<>
GND
GND
3A5<> V3_3
Z44_RSER<3>
3B5<>
3B5<>
XD<7..0>
3C5<>
3B5<> 3A8<> 3A5<>
4D8 3D8 4D8>
3B5<> 3A8<> 3A5<>
4D8 3D8 4D8>
3C8<>
3C8<>
3C8<>
3A4 4B2>
3D8>
3B8<>
3B8<>
3C7<>
3D8>
3B7<>
3D8>
4C3> CS_X5
MOTHERBOARD CONNECTORS FOR WAN R.C.
4D8 3D8 4D8>
3D8>
4D8 3D8 4D8>
3C8<>
XA<15..0>
OSC3_NU
GND
GND
3A8 4B2>
6
8
3
5
1
TDO_NU 4B4>
TCK_NU 4B4>
3D8>
3C8<>
3A3<>
4D8 3D8 4D8>
Z44_TCLK<2>
3D8>
5C5v
6A6v
6A6v
3C2>
3D3<
3D3<
Z44_TDEN<2>
Z44_TSER<2>
SIG_RETURN
Z41RSYNC
Z41TSYNC
Z44_TCLK<1>
5D5v
3A1> 3A3<>
3C1> 5C4v
3C1>
Z44_TDEN<1>
SIG_RETURN
4D8 3D8 4D8>
INT2 3C8<> 3D1> 4D5< 5A6v
RESET_B 4C3> 3D3< 5A5v
INT3 4D5<
INT4 4C5<
PLUG
4
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
P1 CONNECTOR (PLUG)
RW_X
5
7
1
3
0
4C3>
XD<7..0>
Z44_TCLK<4>
SIG_RETURN
Z44_TDEN<4>
Z44_TSER<4>
Z44_TCLK<3>
Z44_TDEN<3>
Z44_TSER<3>
ALE
CS_X4 4C3>
3
Z41RSYNC Z41RSYNC
Z41TSYNC
Z41TSYNC
RESET_B
GND
3
ENGINEER:
STEVE SCULLY
2
INT
4B5<
5A5v
BIS0_DUT 4C5<
5A5v
BIS1_DUT 4B5<
5A5v
3C8<> 4D5<
BTS_DUT
3C7<>
5A6v
1
3B7<>
3C7<>
1
09/16/2004
PAGE: 1/2(BLOCK)
3/71(TOTAL)
DATE:
3A3<>
3C6<> 5C4v 3C8<>
5C5v
INT2
3C6<>
5D5v
SIG_RETURN
3C6<>
5C5v
HWMODE
MODEC0
MODEC1
CS
_z11andlan_dn
RD
PAGES 5-10
WR
RESET_B
DAT<7..0>
ADDR<9..0>
HIERARCHICAL BLOCK
2
TITLE: DS33Z11/41/44DK01A0
3C7<>
3C6<>
6A6v
3B7<>
3C6<>
3C7<>
6A6v
5A5v 4C3>
3A1>
CS_X1
5A5v 4C5< RD_DUT
WR_DUT
5A5v 4C5<
5A6v 4D3>
5B4v 4C6<
D_DUT<7..0>
5C4v 5B1v 5A1v 4C6< A_DUT<9..0>
DS33Z11/Z41 TOP LEVEL
3B5<>
PLUG
3A8<>
P2 CONNECTOR (PLUG)
3A5<>
4D8 3D8
3A8<> 3A5<> V3_3
3C5<> 3B8<>
Z44_RSER<2>
3B5<>
3C8<>
Z44_RCLK<1>
Z44_RDEN<1>
Z44_RSER<1>
3D8>
4D8>
3D8>
4D8>
3C2>
5C5v
3C1>
5C5v
3C1>
5C5v
GND
V3_3
4C5< INT5
3D1> 3C7<> INT2
5A6v 4D5<
XA<15..0>
A
B
3D8
C
D
V3_3
8
CR-3 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1
RCLKI
TCLKI
RSER
TSER
RDEN
TDEN
Z44_RCLK<1>
Z44_TCLK<1>
Z44_RSER<1>
Z44_TSER<1>
Z44_RDEN<1>
Z44_TDEN<1>
A
B
C
D
A
B
C
8
GND
V3_3
3A5<>
3A8<>
3B5<>
7
3B8<>
7
3C5<>
3C8<>
3D8>
3D8 4D8
6
17A6v 17A5v
3D3<
5
BTS_DUT
BTS_DUT
3D1>
17C3v
BIS1_DUT
3C1>
BIS1_DUT
A_DUT<11..0>
BIS0_DUT
17C3v
13-19
4
4
3A8<>
3C7<>
3C5<>
RW_X
RESET_B
CS_X5
19A7v 3A8<>
XD<7..0>
19A7v 3A7<>
17B3v
17B3v
3A5<>
XD<7..0>
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 2/2(BLOCK)
4/71(TOTAL)
1
DATE:
3A4 3A6 17B3v
3A7 3A8 17C7v
2
TITLE: DS33Z11/41/44DK01A0
19A7v
13A5v
17A4v
17A4v
17A4v
17B3v
17B3v
3A4<>
3D3<
XA<15..0>
RW_X
WR_X
RESET_B
3C4<>
CS_X5
3A5<>
3A5<>
CS_X4
3D3<
CS_X4
CS_X3
CS_X1
CS_X2
3
CS_X1
CS_X2
CS_X3
I47
WR
XA<15..0>
_motprocrescard_dn
PAGES
D_DUT<7..0>
WR_DUT
INT5
INT5
WR_DUT
INT4
INT4
RD_DUT
INT3
INT3
RD_DUT
INT2
INT2
D_DUT<7..0>
3D3<
3C8<>
14D4v
17C3v
3C7<>
13B7v
3D3<
3C7<>
13B7v
17C3v
3C7<>
3C8<>
5
A_DUT<11..0>
17C3v 3C1> BIS0_DUT
3D3<
3D1>
17D5v
13B7v
6
TMS_NU
TMS_NU
D
V3_3
8
TDI_NU
TDI_NU
CR-4 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE2
TCK_NU
TDO_NU
TCK_NU
TDO_NU
A
B
C
D
A
V3_3
8
RB342
330
MDC
MDIO
DS44
8B4>
8B4>
TX_EN<1>
RED
1
2
8C5<
30
NC7SZ86_U
R74
BUFFER
30
7
1
30
INT
VALUE=30
COL_DET<1>
UXB08
4
RB173
8C3>
RB176
5A6>
C13
C12
B13
6
3D1^
MDIO
MDC
COL_DET
TX_EN
TXD<3>
E9
E10
TXD<2>
D9
RXDV
D10
TXD<1>
RXD<3>
A11
C9
RXD<2>
D11
TXD<0>
RXD<1>
C11
B9
RXD<0>
B11
TX_CLK
RX_CLK
A10
A8
RX_ERR
5A6<>
3D1^
B12
RX_CRS/CRS_DV
1
LINE IO
U18
DS33Z11_U3
JTAG
1
1
1
MICRO PORT/SPI MASTER PORT
CS*
3D2^ IN
C8
5C2<
B
30
SPI_CS*
REF_CLKO
RD*/DS*
C
WR*/RW*
1
8
9
0
3
4
5
6
7
A4
B4
A5
A6
A7
B5
B6
B7
C5
C6
A<8>
A<9>
5C2<
D<0>/MOSI
5C2>
D<1>/MISO
5C2<
D<2>/SPICK
D<3>
D<4>
D<5>
D<6>
D<7>
5
4
JTRST
JTDI
5D5<
5D5<
7
JTDO
5D5<>
9
5
5D5<
JTCLK 1
JTMS 3
7
C3
A<7>
5D5<
6
B3
A<6>
10
8
6
4
2
RED
5A5>
5B4<>
5B4<>
5B4<>
10
8
V3_3
5C3<
5C3<
5C3<
3
ENGINEER:
STEVE SCULLY
2
1
6
2
5
GND
HOLD*
WP*
VCC
ZADDR2
ZADDR1
SP3T
SW26
SP3T
SW25
SP3T
4
4
4
4
7
3
8
1
RB345
V3_3
IN
2
1
0
V3_3
1
09/16/2004
PAGE: 1/6(BLOCK)
5/71(TOTAL)
DATE:
SW24
AT25160A_U
CS*
SCK
SO
SI
2.7V
Y13
ZADDR0
TITLE: DS33Z11/41/44DK01A0
TDO_NU
TDI_NU
TMS_NU
4
6
TCK_NU
2
2
ZMOSI
ZMISO
ZSPISCK
ZSPICS
3D2^
3D2^ 5B1<
DAT<7..0>
IO
IN
ADDR<9..0>
CONN_10P
9
7
5
3
1
J29
2
1
5
A3
A<5>
ZMOSI
ZMISO
ZSPISCK
4
C2
A<4>
5A2<>
5B2<>
5B2<>
DS39
1
2
3
ZADDR0
B1 ZADDR1
A2 ZADDR2
A1
R197
330
B2
A<2>
A<1>
A<0>
TP53
UXB06
4
NC7SZ86_U
BUFFER
3
A<3>
LED+TP
4
HW MODE PINS ARE OUTPUTS FROM Z MODULE TO PROC
PROC (FPGA) AUTOMATICALY IMPLEMENTS BUS MODE
3D2^ IN
3D2^ IN
REF_CLK
RST*
3D2^
8B4<
E13
MODEC<0>
REF_CLKO
TP35
RX_CRS<1>
8C3>
8C3> RX_ERR<1>
8C3> RX_CLK<1>
8D3> RXD0<1>
8C3> RXD1<1>
8C3> RXD2<1>
8C3> RXD3<1>
8C3> RXDV<1>
8C5< TX_CLK<1>
RB177
TXD0<1>
8D5<
30
RB178
8C5< TXD1<1>
30
R55
8C5< TXD2<1>
VALUE=30
RB175
8C5< TXD3<1>
5A3<>
HWMODE
9D4< 3D1^
OUT
9D2< 3C1^
TP36 D13
RB174
DCEDTES
REF_CLK
MODEC<1>
OUT
OUT
OUT
9D4< 3C1^
WR
RD
ZSPICS
CS
INT
9D2<
RESET_B
9C4<
8A1<
RCLKI
5A3<>
JTMS
1
RMIIMIIS
(INPUT)
TCLKI
5A3<>
JTDI
IN 3C2^
IN 3C2^
RSER
5A3<>
JTDO
IN 3C2^
1
FULLDS
9C2<
D
9C4<
DS33Z11/Z41
H10S
(OUTPUT)
INT*
5
AFCS
9C2<
6
SCAN/EN
9B4<
7
MII/RMII PORTS
TSER
5A3<>
JTCLK
OUT 3C2^
IN 3C2^
RDEN/RBSYNC
F7 JTMS
E4 JTDI
E5 JTDO
D4 JTCLK
E6 JTRST
JTRST
3C2^
IO
RCLKI
TCLKI
RSER
RB359TSER
30
RDEN
TDEN
TP72
TP71
TP78
TP77
TP75
TP74
G2
F1
H1
F2
H2
F5
TDEN/TBSYNC
C7
QOVF
SCAN/MODE
9B2<
10K
RB343
3D2^ 5B2<
8
10K
CR-5 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE1
ADDR<9..0>
JMP_3
CKPHA
9B4<
F3
C1
B8
E1
E2
D8
D5
D6
D7
A13
C4
A9
B10
C10
E7
E8
F6
CKPHA
SCANMOD
SCANEN
AFCS
H10S
FULLDS
RMIIMIIS
DCEDTES
MODEC1
MODEC0
HWMODE
A
B
C
D
A
B
C
7C4<
7C4<
7C4<
9D5<
7C3<
7C4<
7C4<
7C4<
7C4<
7C4<
SD_CS
SD_CLKO
SD_CLKI
SD_RAS
SD_CAS
SD_WE
SD_DQM0
SD_DQM1
SD_DQM2
SD_DQM3
SD_A<11..0>
8
11
10
9
8
7
6
5
3D2^ IN
3D2^ IN
SD_CLKO MAY BE DELAYED
BY REMOVING 0 OHM RESISTOR
AND CONNECTING
JUMPERS WITH 75 OHM COAX
7A3>
4
3
2
7
M7
M8
N8
N6
R222
R188
RB253
RB255
M4
RB278
TP46
TP70
TP69
Z41RSYNC
Z41TSYNC
NC_PINF9
H4
RB295
SWE*
SCAS*
SRAS*
SYSCLKI
G13
SDCS*
SDMASK<3>
SDMASK<2>
SDMASK<1>
SDCLKO
K6
0VDD3.3
SDMASK<0>
SDA<11>
SDA<10>
SDA<9>
SDA<8>
SDA<7>
SDA<6>
SDA<5>
SDA<4>
SDA<3>
SDA<2>
SDA<1>
N5
RB293
RB256
L6
M5
R221
R189
L5
R220
M9
L9
RB275
R219
L8
RB276
G4
L7
RB294
M10
K11
RB272
RB274
L11
RB270
RB296
N10
2VDD3.3
2
6
VSS1
RB252
1VDD3.3
2
VSS0
V3_3
U18
DS33Z11_U3
I228
NA
DS33Z11
10A4<
6D4<
10B4<>
V1_8ZCHIP
SDRAM CONTROLLER SYSTEM
PWR/GND
2
1
5VDD3.3
2
VSS4
SDA<0>
6VDD3.3
VSS5
N9
2
VSS6
R187
7VDD3.3
2
2
VSS7
0
8VDD3.3
2
SBA<1>
2
VSS8
3VDD3.3
2
VSS2
2
VSS9
SBA<0>
4VDD3.3
VSS3
2
2
VSS10
N7
0VDD1.8
2
2
VSS11
M6
1VDD1.8
2
2
VSS12
RB254
2
VSS13
CB252
10UF
CB182
10UF
CB426
10UF
CB183
10UF
CB432
2
VSS14
SD_BA0
SD_BA1
9VDD3.3
4
V1_8ZCHIP
3VDD1.8
2
VSS15
7B4<
10VDD3.3
10B4<>
2
VSS16
7B4<
11VDD3.3
6B5<
2VDD1.8
10A4<
4VDD1.8
V3_3
5VDD1.8
5
6VDD1.8
2
VSS17
RB277
NC1
7VDD1.8
5
UNMARKED RESISTORS ARE 30 OHMS
4
2
6
SDATA<31>
R218
NC2
8VDD1.8
2
D
7
SDATA<30>
RB292
8
1 1 1
CR-6 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE2
SDATA<29>
RB291
VSS18
D1
K3
K10
F8
J5
K5
J6
J11
J7
K7
J8
K8
J9
K9
J10
K12
F12
F13
A12
2
10UF
CB433
10UF
CB413 1
0.1UF
CB452 1
0.1UF
CB425 1
0.1UF
CB451 1
0.1UF
CB244 1
0.1UF
CB281 1
0.1UF
CB437 1
0.1UF
CB213 1
0.1UF
CB434 1
0.1UF
CB214 1
0.1UF
CB226 1
0.1UF
CB303 1
0.1UF
CB428 1
470UF
RB289
NC3
9VDD1.8
CB351 1
470UF
CB235 1
0.1UF
CB249 1
0.1UF
CB173 1
0.1UF
CB159 1
0.1UF
CB129 1
0.1UF
CB153 1
0.1UF
CB430 1
0.1UF
CB136 1
0.1UF
CB170 1
0.1UF
CB186 1
0.1UF
CB141 1
0.1UF
CB175
10UF
CB354
10UF
CB224
10UF
CB418
10UF
CB419
10UF
CB382
10UF
10VDD1.8
G5
G6
G7
G8
G9
G10
H5
H6
H7
H8
H9
H10
F9
G1
G3
11VDD1.8
SDATA<28>
D3
D2
E3
F4
J4
K4
L3
F10
E11
E12
D12
M13
L12
12VDD1.8
SDATA<27>
L10
G11
F11
G12
H12
RB290
31
30
29
28
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
RB259
R184
R183
RB258
RB257
RB245
R182
R223
R224
R225
R226
RB297
R227
RB260
R228
R181
R186
RB273
R180
R179
RB271
RB244
R178
R215
R216
R217
L2
N1
M2
N2
N4
N3
L4
J3
M3
H3
J1
J2
K1
K2
L1
M12
H11
M11
N13
N11
L13
N12
K13
J13
J12
H13
SDATA<1>
SDATA<2>
SDATA<3>
SDATA<4>
SDATA<5>
SDATA<6>
SDATA<7>
SDATA<8>
SDATA<9>
SDATA<10>
SDATA<11>
SDATA<12>
SDATA<13>
SDATA<14>
SDATA<15>
SDATA<16>
SDATA<17>
SDATA<18>
SDATA<19>
SDATA<20>
SDATA<21>
SDATA<22>
SDATA<23>
SDATA<24>
SDATA<25>
SDATA<26>
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 2/6(BLOCK)
6/71(TOTAL)
1
DATE:
SD_DQ<31..0>
2
TITLE: DS33Z11/41/44DK01A0
7D7
0
R185
M1
SDATA<0>
3
A
B
C
D
A
B
8
7
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
DQ<29>
DQ<28>
DQ<27>
DQ<26>
DQ<25>
DQ<24>
DQ<23>
DQ<22>
DQ<21>
DQ<20>
DQ<19>
DQ<18>
DQ<17>
DQ<16>
DQ<15>
DQ<14>
DQ<13>
DQ<12>
DQ<11>
DQ<10>
DQ<9>
DQ<8>
DQ<7>
DQ<6>
1
0
MT48LC4M32B2_TSOP_U
UB10
6
5
A<11>
A<10>
A<9>
A<8>
A<7>
A<6>
A<5>
A<4>
A<3>
A<2>
A<1>
A<0>
BA<1>
BA<0>
DQM<3>
DQM<2>
DQM<1>
DQM<0>
RAS*
CAS*
WE*
CS*
CKE
CLK
V3_3
SYNCHRONOUS
DRAM
MT48LC4M32B2 - 1 MEG X 32 X 4 BANKS
DQ<1>
DQ<30>
DQ<5>
VDD4
VSS4
5
VSS2
DQ<4>
VDD3
VSS3
DQ<3>
VDDQ8
VSSQ8
3
VDDQ7
VSSQ7
DQ<2>
VDDQ6
VSSQ6
4
5
7
8
10
11
13
74
76
77
79
80
82
83
85
31
33
34
36
37
39
40
42
45
47
48
50
51
53
VSSQ5
2
VSSQ4
SD_DQ<31..0>
VSSQ3
C
6A2
VDD2
5
VDDQ5
6
VDDQ4
4
2
DQ<0>
DQ<31>
54
56
30
31
VSSQ2
D
7
VDD1
VSS1
86
72
58
44
8
VDDQ3
43
29
15
1
CR-7 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE3
VDDQ2
81
75
55
49
41
35
9
3
VDDQ1
VSSQ1
84
78
52
46
38
32
12
6
4
4
25 0
26 1
27 2
60 3
61 4
62 5
63 6
64 7
65 8
66 9
24 10
21 11
6C7<
6D7<
6B8<
6B8<
6B8<
6B8<
SD_A<11..0>
22 SD_BA0
23 SD_BA1
SD_DQM0
SD_DQM1
SD_DQM2
SD_DQM3
16
71
28
59
6B8<
SD_CS 6B8<
SD_WE 6A8<
SD_CAS 6B8<
SD_RAS 6B8<
68
67
20
17
18
19
SD_CLKO
6C8
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 3/6(BLOCK)
7/71(TOTAL)
1
DATE:
2
TITLE: DS33Z11/41/44DK01A0
V3_3
FROM Z11 SYSCLKO
3
A
B
C
D
A
B
DS11
1
2
1
RB44
5.1K
RB48
5.1K
7
RB47
5.1K
DS06 RB54
2
330
RB60
5.1K
RB57
330
RB72
5.1K
DS15 RB78
2
330
LED_TX_A3<1>
1
LED_RX_A4<1>
11C5v 8B6<
11C5v 8C6<
11C5v 8B6<
8
LED_COL_A1<1>
LED_GDLINK_A2<1>
11C5v 8C6<
LED_DPLX_A0<1>
11C5v 8C6<
RED
AMBER
GREEN
V3_3
6
11C5v 8A8<>
V3_3
LED_RX_A4<1>
11C5v 8A8<>
L04
1
1
I70
5
CHASSIS GND FOR PHY
LB01
100O100MZH
2
2
I69
LED_RX_ADD4
LED_TX_ADD3
LED_GDLINK_ADD2
100O100MZH
LED_TX_A3<1>
11C5v 8A8<>
LED_COL_ADD1
LED_COL_A1<1>
11C5v 8B8<
CHASSIS
4
PAGES 11-12
LED_DPLX_ADD0
1
LED_GDLINK_A2<1>
4
HIERARCHICAL BLOCK
_mii_wan_dn
LED_DPLX_A0<1>
TX_EN
TX_CLK
TXD3
TXD2
TXD1
TXD0
11C5v 8B8<
11A5v 5B8<
TX_CLK<1>
TX_EN<1>
TXD0<1>
TXD1<1>
TXD2<1>
TXD3<1>
0.1UF
C
11A5v 5B7<>
11A5v 5B7<
11A5v 5B7<
11A5v 5B7<
11A5v 5B7<
5
IN
6
MDIO
MDC
D
7
CB05
10UF
CB04
10UF
RESET_B
2 C10
8
CR-8 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE4
RXDV
RX_ERR
RX_CRS
RX_CLK
RXD3
RXD2
RXD1
RXD0
COL_DET
MII_CLK
RESET_B
3D2^
MDC
MDIO
11C7v 5A5<
11C5v
5B7< 5B7< 8A1<
11C5v
MII_CLK
11A7v
11A7v
5B7<
11A7v
11A7v
5B7<
5C7<
5C7<
11C7v
GND
1
OSC
OUT
VCC
3
ENGINEER:
STEVE SCULLY
2
TITLE: DS33Z11/41/44DK01A0
4
1
2
5
8
R133
R140
25.000MHZ_3.3V
Y09
V3_3
RX_CLK<1> 5C7<> 11A7v
RX_CRS<1> 5C7< 11A7v
RX_ERR<1> 5C7< 11A7v
RXDV<1> 5B7< 11A7v
COL_DET<1> 5B7< 11A7v
RXD0<1>
RXD1<1>
RXD2<1>
RXD3<1>
3
30
30
11C7v
09/16/2004
5C7<>
8B3>
1
PAGE: 4/6(BLOCK)
8/71(TOTAL)
DATE:
REF_CLK
MII_CLK
1
A
B
C
D
A
B
C
D
8
8
4
1
GND
1
OSC
Y06
7
OUT
VCC
5
8
30
OSC100MHZ
R128
V3_3
100.000MHZ_3.3V
7
1
6
UXB04
4
NC7SZ86_U
6
R120
30
SD_CLKI
5
5
6B8<
CR-9 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE5
5A5<
LOW
MODEC1 1
LOW
5A4<
5A4<
5A4<
4
LOW
CKPHA 1
LOW
2
1
2
SP3T
SW15
SP3T
1
3 CKPHATRI
4
5A4<
1
RB64 2
2.0K
2
SP3T
SIGNAME_TRI DOES NOT
CONNECT ANYWHERE
(HELPS PCB NETLIST)
LOW
SCANMOD
SW11
SW10
1
3 SCANENTRI
4
SP3T
LOW
RB3672
2.0K
SP3T
5A4<
AFCS
SW44
SW42
1
3 H10STRI
4
SP3T
HIGH
FULLDS 1
RB3662
2.0K
2
SW17
SP3T
SP3T
5A5<
LOW
RB70 2
2.0K
2
SW43
1
3 RMIIMIISTRI
4
1
DCEDTES 1
HIGH
RB67 2
2.0K
SW16
5A5<
3C1^ 5A5>
MODEC0
SW14
SP3T
1
3 MODEC1TRI
4
1
3 HWMODETRI
4
V3_3
2
SP3T
SW13
SP3T
SW12
3
1
3 SCANMODTRI
4
1
3 AFCSTRI
4
1
3 FULLDSTRI
4
1
3 DCEDTESTRI
4
2
1
ENGINEER:
3
09/16/2004
PAGE: 5/6(BLOCK)
9/71(TOTAL)
STEVE SCULLY
DATE:
TITLE: DS33Z11/41/44DK01A0
CONFIG SWITCHES FOR Z11
V3_3
1
3 MODEC0TRI
4
1
MODE (SHOWN BELOW SIGNAL) RESULTS IN:
MOTOROLA NON-MUX, MII, FULL DUPLEX, 100 MBIT, AUTO-FLOW CONTROL
2
2
2
2
2
2
RB68 2
2.0K
RB63 2
2.0K
SCANEN 1
HIGH
RB3652
2.0K
1
RB69 2
2.0K
RB66 2
2.0K
RB65 2
2.0K
1
H10S
LOW
RMIIMIIS
3C1^ 5A5>
3D1^ 5A5>
HWMODE 1
4
A
B
C
D
A
2
C70
1
1
8
1UF
C45
JB01
B
A
BLACK
1
2
B
CONN_BANANA_2P
B
A
7
CONN_BANANA_2P
1
2
JB08
1
2
J54
JB02
A
B
A
CONN_BANANA_2P
I39
1
2
RED
V3_3
I38
SHDN
RST
BLACK
4
RED
CONN_BANANA_2P
2
1
1UF
C38
2
1
1UF
CB102
2
B
GND
SET
5
2
7
2
6
10UF
6
2
OUT
2
IN
2
3
1UF
2
2
2
8
V3_3
2
OUT
2
1UF
2
CB110
1
2
C46
1
2
CB139
1
2
1UF
CB131
1
CB355 1
0.1UF
CB344 1
0.1UF
CB225 1
0.1UF
CB345 1
0.1UF
CB192 1
0.1UF
CB217 1
0.1UF
CB456 1
0.1UF
CB234 1
0.1UF
CB253 1
0.1UF
IN
1UF
5
6D4< 6B5<
10B4<>
V1_8ZCHIP
2 CB450 1
1
0.1UF
2 CB455 1
V3_3
0.1UF
2 CB435 1
U07
MAX1792
6B5< 6D4<
4
V1_8ZCHIP
0.1UF
2 CB280 1
C
0.1UF
2 CB304 1
D
0.1UF
5
0.1UF
2 CB453 1
6
4
10A4<
0.1UF
2 CB436 1
7
2 CB454 1
8
0.1UF
CR-10 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I5@\_ZTOP_LIB\.\_Z11TOP_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_Z11ANDLAN_DN\(SCH_1):PAGE6
0.1UF
2 CB181 1
3
3
2
1
PAGE: 6/6(BLOCK)
10/71(TOTAL)
STEVE SCULLY
ENGINEER:
09/16/2004
DATE:
1
TITLE: DS33Z11/41/44DK01A0
2
A
B
C
D
A
B
C
12B8<
0.1UF
8C3^
12B8<
8
8C3^
12B8<
RESERVED3
RXD2
RXD3
9
7
5
3
10
8
6
4
10
8
6
4
2
CONN_10P
9
7
5
3
1
2
RESERVED11
47
1
RESERVED10
44
RXD0
RXD1
X2
48
J14
RESET*
46
RESET_B
X1
RBIAS
49
3
MII_CLK
RBIAS
RESERVED5
RESERVED14
RESERVED4
RESERVED13
RX_CLK
RXDV
RX_CRS
COL_DET
RX_ERR
OUT
OUT
12C6<> 8C3^
12C8<
8C5^ IN
OUT 8C3^ 12B5<
OUT 8C3^ 12C5<
OUT
12C4<
8C5^ OUT
CONTROL
U04
DP83847_U1
17
16
15
AN_EN
AN_1
AN_0
TX_EN
TX_CLK
9
7
5
3
10
8
6
4
10
8
6
4
2
CONN_10P
9
7
5
3
1
2
18
LED_SPEED
1
19
LED_RX/PHYAD4
J13
20
LED_TX/PHYAD3
TXD1
TXD0
TXD3
TXD2
RB55
5.1K
RB52
5.1K
RB07
5.1K
TP03
AN0
6
5
2
JP09
AN_EN
V3_3
2
JP15
IN 8D5^ 12C8<
4
8C5^ 12C8<
IN 8C5^ 12C8<
IN
4
3
JP14
V3_3
LEDS NEED TO BE ATTACHED
OUTSIDE OF MODULE DUE TO
STRAP ADAPTING OPTION OF DP83847
IN 8C5^ 12C8<
2
IO
AN1
ON Z44 CARD ALL 4 PORTS MUST BE PLACED WITH EQUAL SPACING AND A COMMON CENTER LINE
7
IO
IO
IO
LED_TX_ADD3 IO
LED_RX_ADD4
21 LED_GDLINK_ADD2
LED_COL_ADD1
22
LED_COL/PHYAD1
LED_GDLNK/PHYAD2
LED_DPLX_ADD0
23
8B4^
LED_DPLX/PHYAD0
MDC IN
MDIO
IO
30
24
25 R109
MDIO
MDC
PLACEMENT NOTE:
TESTPOINTS (SHOWN ABOVE) MUST BE PLACED THE SAME FOR EACH PORT TO
ALLOW USE OF A DIFFERENT PHY CARD IF DESIRED. PLACEMENT SHOULD ALLOW
0.2 BETWEEN CONNECTORS.
OUT
OUT
OUT
OUT
IN
8B4^
8D3^
IN
V3_3
12B8<
8C3^
1
2 C30
8B4^
R08
10.0K
C1
RESERVED6
RESERVED15
42
RESERVED7
RESERVED16
C32
1
10UF
2
VDD/IO_VDD1
4
5
8
9
12
13
34
RESERVED12
VDD/IO_VDD2
28
56
14
AN_V3_3
GND2
COMPONETS FOR
C1 AND RBIAS MUST
BE PLACED CLOSE TO PIN
2
RESERVED2
C1PIN
1
RESERVED1
GND3
RESERVED8
RESERVED17
VDD1
57
59
63
VDD2
GND4
VDD/ANA_VDD
GND1
V3_3
1
D
3
1
RESERVED9
RESERVED18
50
51
52
53
54
55
61
3
1
VDD3
GND5
58
60
62
64
65
3
1
5
V3_3
2
2 CB63 1
3
ENGINEER:
STEVE SCULLY
2
TITLE: DS33Z11/41/44DK01A0
2
6
2
L03
1
100O100MZH
10UF
7
2
1
8
2
1
AN_V3_3
1
CR-11 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page1
C207 1
0.1UF
CB239 1
0.1UF
CB93 1
0.1UF
CB194 1
0.1UF
2 CB238 1
0.1UF
2 C198 1
0.1UF
CB96
10UF
CB497
10UF
2
1
1
11/71(TOTAL)
09/16/2004
PAGE: 1/2(BLOCK)
DATE:
C16
2
10UF
2 CB41
0.1UF
CB39
2
0.1UF
A
B
C
D
A
B
C
D
8
RD_P
RD_N
RXD0
RXD1
RXD2
RXD3
8
30
TXD<3>
41
30
R141 30
R76 30
R75
RD+
RD-
6
7
RXD<3>
26
7
RXD<2>
RXD<1>
27
29
RXD<0>
TXD<2>
40
30
TXD<1>
39
R134
TXD<0>
38
TXD0
TXD1
TXD2
TXD3
TX_EN
37
TX_ER
TX_EN
35
TD-
TD+
COL
CRS/LED_CFG*
TX_CLK
RX_CLK
RX_DV
RX_ER/PAUSE_EN*
PORT
DP83847_U1
U04
7
11
10
43
45
36
32
31
33
6
30
30
TD_P
TD_N
R71
R31
RXDV
RX_ERR
6
RX_CRS
COL_DET
R129 2
10K
5
5
UX034
1
UX044
NC7SZ86_U
BUFFER
RB88
RB87 DNP
DNP
1
NC7SZ86_U
BUFFER
RB109
RB110
30
30
4
RX_CLK
TX_CLK
4
CR-12 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page1_i1@\_ztop_lib\.\_z11andlan_dn\(sch_1):page4_i32@\_ztop_lib\.\_mii_wan_dn\(sch_1):Page2
P5
P6
5
6
TD_N
CHASSIS
8
SH2
J7,8
J4,5
J6
J3
J2
J1
SH1
1
CONN_HFJ11_2450_U
P8
P3
3
TD_P
P2
4
P1
RD_N 2
1
P4
RD_P
J04
SYM_1
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 2/2(BLOCK)
12/71(TOTAL)
CHASSIS
10
CHASSIS
9
DATE:
RESISTORS FOR TD+-/RD+SHOULD BE PLACED CLOSE TO PHY
CAPS FOR XFRM CENTER TAP
SHOULD BE PLACED CLOSE TO XFRM
R04
49.9
R03
49.9
R02
54.9
R01
54.9
.1UF
C06
2
TITLE: DS33Z11/41/44DK01A0
V3_3
.1UF
C08
3
C138
.1UF
A
B
C
D
A
B
61
58
57
56
55
54
8
EB1*
INT3*
EB2*
INT4
EB3*
INT5*
INT6*
INT7*
RXD1
TXD1
RXD2
TXD2
TEST
ICOC10
ICOC11
ICOC12
ICOC13
ICOC20
ICOC21
ICOC22
PQA3
XTAL
MMC2107
CONTROL
EB0*
INT2*
53
PQB3
INT1*
ICOC23
PQB2
INT0*
52
I68
GND
TEST 63
SCI2_OUT 66
68
SCI2_IN
SCI1_OUT 69
70
SCI1_IN
ICOC23
ICOC22
ICOC21
ICOC20
ICOC13
ICOC12
ICOC11
ICOC10
PQB1
YC0
C
PQA1
EXTAL
7
TC2
TC1
CS3
67
78
94
143
1
3
GND
MR*
5
2
4
RESET_B
V3_3
4
17
20
21
20
19
18
25
27
30
31
34
35
16
15
14
13
12
11
22
16
21
17
15
12
10
7
5
4
3
2
22
23
24
25
26
27
28
29
1
30
PARENT BLOCK: \_z11top_dn\
RESET*
VCC
U13
MAX811_U
SOT143
2.93V
MAX811SEUS-T
I70
ONCE_DE_B
SS
CS0
118
RESET_B
128 CPUCLK_OUT
120 PROC_RESET_OUT
SCK
93
86
85
83
81
CS2
CS1
CSE1
CSE0
62
60
BLOCK NAME: _motprocrescard_dn.
3
2
6
4
1
SW23
I64
SS*
DE*
SCK
RSTOUT*
CLKOUT
RESET*
CS0*
CS1*
CS2*
CS3*
TC1
TC2
CSE0
CSE1
144
31
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
VRL
MMC2107
PORT
VDD6
VSS7
VDD7
VSS8
VRH
VRH
D3
VSTBY
D4
TA
TEA
TEA*
D5
TA*
D6
RW
OE
RCON
SHS*
D7
OE*
D8
D9
RW
D10
U15
1
2
R77
VDDSYN
2
VSS6
I51
TQFP
NA
MMC2107
3
FLASH_VPP
VPP
D2
PQB0
MOSI
VDDA
D1
U15
4
VSSA
PQA4
MISO
VDDH
VDDSYN
VSSF
I69
PQA0
TCLK
1
VDD5
TQFP
NA
MMC2107
TDI
TRST*
0.0
C67 2
.1UF
VDD4
VSS5
D
5
VDD3
VSS4
88 TIM_16H_8L
96
EB3
EB2
98
100
EB1
101
EB0
104
PQB3
105
PQB2
PQB1
106
107
PQB0
PQA4
108
109
PQA3
110
PQA1
111
PQA0
133 ONCE_TDI
135 2107_TDO
TDO
TMS
VDDF
D0
PD<31..0>
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
V3_3
10
9
8
7
6
5
4
11
13
14
23
24
26
28
0
11
6
1
12
139
50
13
137
49
14
136
3
15
134
2
16
132
47
17
131
29
19
18
20
119
122
21
117
121
22
116
2
1
ENGINEER:
3
09/16/2004
PAGE: 1/7(BLOCK)
13/71(TOTAL)
STEVE SCULLY
DATE:
1
TITLE: DS33Z11/41/44DK01A0
MMC2107
PROCESSOR RESOURCE CARD
10
9
8
7
6
5
4
3
2
1
0
89
84
82
79
75
72
71
80
90
91
124
125
130
142
138
USER_LED1
USER_LED2
INT3
INT4
RUN_KIT_USR
TIM_STATUS
INT2
YCO
MOSI
MISO
XTAL
OSC_MCU
ONCE_TCLK
ONCE_TRST_B
ONCE_TMS
VDD8
VSSSYN
6
VSS3
7
VDD2
59
95
97
99
102
92
113
112
87
115
74
103
123
141
129
77
65
45
33
19
9
VDD1
VSS2
8
VSS1
36
37
38
39
40
41
42
43
46
48
51
114
73
126
140
127
76
64
44
32
18
8
CR-13 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page1
PA<22..0>
A
B
C
D
A
B
C
D
2
25
3
26
4
31
27
28
15
14
13
12
11
10
9
A8
A9
A10
A11
A12
A13
A14
A15
A16
8
PA<17..1>
5
16
I54
U30
CY62128V
CY62128V
NA
V3_3
BOOT
INTERN/EXTERN
INTERNAL
FLASH ENABLE
XTAL W/ PLL
FULL DRIVE
MASTER MODE
17
8
PD<18>
PD<19>
PD<28>
PD<22>
PD<23>
PD<21>
PD<16>
PD<17>
PD<26>
7
CY62128V
VCC
A7
7
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
1
1
31
30
29
28
27
26
25
24
21
18
15
17
14
20
13
2
19
10K
10K
R229
2
10K
10K
R234
R231
10K
10K
R232
10K
R233
R235
10K
R236
10K
R230
R196
1
1
1
1
1
2
1
5
2
2
2
2
2
1
2
6
PD<31..24>
V3_3
2
10K
1
5
9
9
31
27
28
10
26
11
25
12
4
V3_3
I18
V3_3
A8
A9
A10
A11
A12
A13
A14
A15
A16
U26
CY62128V
CY62128V
NA
PA<17..1>
10
11
12
13
14
15
16
17
WHEN SET FOR
BOOT INTERNAL
D18 HAS A 10K LOAD TO GND
BOOT EXT
D18 HAS A 10.5K LOAD TO V3V
RCON
R152
RESET CONFIGURATION
6
CY62128V
1.0K
4
IO0
IO1
IO2
IO3
IO4
IO5
IO6
IO7
BTS_OBSXI
BIS1OBSXI
BIS0OBSXI
V5_0
19
18
17
16
15
20
17
13
RESET AND CHIP CONFIGURATION
PD<23..16>
30
1
2
3
STEVE SCULLY
2
1
A
B
C
D
AMBER V3_3
ENGINEER:
20
R83
I65
DS20
09/16/2004
PAGE: 2/7(BLOCK)
14/71(TOTAL)
21
14
21
FLASH_VPP
1
DATE:
22
18
10
9
7
8
11
6
14
V3_3
0L_SMT0805_10PCT
13
ECJ-2VB1C104K
15
12
SWITCH
8 POS
16
5
4
3
2
1
SW06
I69
2
TITLE: DS33Z11/41/44DK01A0
23
19
INT3
INT4
USERFPGA2
INT5
3
1.0K
CR-14 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page2
N_C
A6
2
R255
1.0K
1
VCC
A7
EB0
OE
WE*
A5
N_C
A6
OE*
A4
2
2
R79
1
R248
1.0K
1
1 R160 2
1.0K
2
2
R254
1
WE*
A5
CE2
A3
1
A4
CS0
A2
R161.0K
2
EB1
OE
OE*
A3
CE1*
A1
1.0KR12
CE2
A2
32
1
29
24
30
22
16
GND
A0
6
7
8
9
10
11
12
23
8
7
6
5
4
3
2
1
A1
2
C12
1
1
R07
2
1
1.0K
CS0
CE1*
32
1
29
24
30
22
16
GND
A0
8
7
6
5
4
3
2
23
8
7
6
5
4
3
2
1
.1UF
A
B
8
PRT1_IN
PRT1_OUT
SCI1_IN
PRT1_OUT
PRT1_IN
10
9
8
7
6
5
4
E
D
C
B
A
I35
J
H
G
F
J28
V3_3
9
8
7
6
FORCEOFF*
VCC
R1IN
T1OUT
R1OUT
FORCEON
T1IN
T2IN
INVALID*
R2OUT
7
V+1
V+2
C1+
C1-
C2+
C2-
V-
GND
T2OUT
R2IN
11
12
13
14
15
16
17
18
19
20
6
C44
1
2
10K
1
CONN_DB9P
5
4
3
2
1
10K
SCI1_OUT
3
2
1
ONCETDI
PIN
1UF
2
U21
MAX3233E
10K
MAX3233E
MAX3233E
V3_3 NA
I31
2
2
1
1
C33
5
1UF
10UF
CB113
TDI
ONCETDO
PIN
1UF
C07
4
...FPGA+FLASH...
JTAG CONFIGURATION
MMC2107
2
2
10UF
C27
1
V5_0
C02
2
1
2
RB134
1
2
1
C
R87
330
1UF
XTAL
C21
PLACE PADS FOR CAP
BUT DO NOT POPULATE
68UF
I13
1
2
1
1UF
8.0MHZ
2
1
1
2 C52
L02
2
22.0UH
5
6
7
8
C14
OSC_MCU
U01
V3_3
RESET_B
ONCE_TDI
2107_TDO
ONCE_TCLK
REF
LBO*
LBI
4
3
2
1
I11
R10
5.6
SMT1206_5PCT
ERJ-8GEYJ5R6V
SHDN
GND
LX
FB
MAX1675
OUT
C40
I47
2
1
3
13
11
10
3
ENGINEER:
STEVE SCULLY
2
VDDSYN
1
1
2
1
09/16/2004
PAGE: 3/7(BLOCK)
15/71(TOTAL)
DATE:
ALIGN KEY
ONCE_TMS
12 ONCE_DE_B
14 ONCE_TRST_B
8
7
6
9
4
2
3
V3_3
CON14P
I1
J06
CON14P
CON14P
NA
5
1
V3_3
2
TITLE: DS33Z11/41/44DK01A0
1UF
X01
1UF
2
1
1
2
4
CB28
R209
1
C03
2
1UF
1
.1UF
CB490
5
1UF
2
2
1
10K
2
1
6
CB488
R81 10K
1
7
1UF
D
1
R110
2
1
R95
2
1
R56
1
2
1
8
C56
R80 10K
2
1.0M
CR-15 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page3
1UF
68UF
2
C26
A
B
C
D
A
B
C
9
7
10
8
6
10
8
8
IO1_0
IO3_0
IO4_0
IO5_0
IO6_0
IO7_0\VREF
L12
B7
K12
J14
M13
B6
B4
4
3
2
1
IO9_0
IO10_0
IO11_0
IO12_0
IO13_0
IO14_0
IO15_0
IO16_0
IO17_0
IO18_0
IO19_0
IO20_0
A9
D12
B10
E13
A3
G15
B11
A5
A4
A6
B3
30
29
28
27
26
25
24
23
22
21
20
PD<31..16>
7
X_INIT
IO8_0
E14
31
IO2_0\VREF
GCK3
B8
5
SPARE_B<5..0>
G13
1
2
3
4
6
4
CONN_10P
9
7
5
4
3
19
18
3
IO3_1
IO4_3\VREF
5
17
16
5
IO5_1
IO6_3
2
IO6_1
IO7_3\D6
2
IO7_1
IO8_3\D5
1
IO8_1
IO9_3
1
BANK 3
XC2S50_BGA
U27
BANK 1
IO16_1
IO17_3
J45
IO17_1
IO18_3
D
6
IO18_1
IO19_3
7
5
IO19_1
IO20_3
8
6
5
R16
F15
E16
P16
IO5_2
IO6_2\D2
IO7_2\D1
IO8_2
15
14
13
12
11
10
9
8
7
6
C15
A10
A11
C12
F16
E15
A13
C16
D16
B12
C8
D9
IO13_2\(DOUT,BUSY)
IO14_2
IO15_2
IO16_2
IO17_2
IO18_2
IO19_2
IO20_2
IO21_2
IO22_2
IO23_2
IO24_2
4
16
D14
D7
PA<16..0>
3
GREEN
2
1
1
2
1
RED
RED
2
DS18
2
DS38
RED
2
1
DS16
1
RED
RED
RED
3
STEVE SCULLY
2
1
ENGINEER:
330
R70
330
R32
1
09/16/2004
PAGE: 4/7(BLOCK)
16/71(TOTAL)
1
330
R176
1
DATE:
V3_3
2
2
2
TITLE: DS33Z11/41/44DK01A0
USER_LED2
USER_LED1
TIM_INTERUPT_IND
CFG_DIN
PROC_RESET_OUT
TIM_INTERUPT
4
IO12_2\(DIN,D0)
IO11_2
IO10_2\VREF
H13
IO4_2
L13
G16
IO3_2\D3
F13
H15
IO2_2\VREF
IO9_2
H16
IO2_1\IRDY
CR-16 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page4
IO9_1\VREF
IO10_3\VREF
GCK2
IO1_3\INIT*
IO10_1
IO11_3\D4
IO1_1\CS*
IO2_3\D7
IO11_1
IO12_3
IO2_1\WRITE*
IO3_3
IO12_1
IO13_3\TRDY
IO4_1\VREF
IO5_3
IO13_1
IO14_3
IO20_1
BANK 2
IO21_3
IO14_1
IO15_3
IO21_1
IO22_3
IO15_1
IO16_3
IO22_1
IO23_3
N15
N14
C6
L14
C7
C10
N16
M16
K14
K16
J16
K15
J15
T15
G12
M14
M15
E11
A12
B16
D11
G14
D10
0
1
2
3
4
5
1
R237
2
DS43
330
C9 OE
B13 RW
C13 CS0
D6 CS1
C11 CS2
A14 EB0
F14 EB1
A7 TA
B5 TEA
B9
D8
A8
E7
H14
J13
E6
F12 SCI2_IN
E10 SCI2_OUT
D5
L16
C5
K13
L15
BANK 0
A
B
C
D
A
B
C
8
5
7
9
6
10
8
6
10
8
6
3
1
2
7
XA<11..0>
CONN_10P
9
7
5
IO6_4
IO7_4
IO8_4
T7
R5
M2
T12
9
8
7
IO10_4
IO11_4
IO12_4
IO13_4
IO14_4
IO15_4
IO16_4
IO17_4
IO18_4
IO19_4
IO20_4
IO21_4
IO22_4
T6
M1
T5
N2
P1
T3
T2
R10
T13
N12
B1
N10
L2
6
5
4
3
2
1
0
IO9_4\VREF
IO5_4
R6
IO3_4\VREF
P9
10
IO2_4
R9
11
IO1_4
H4
IO4_4
GCK0
N8
T10
10
GCK1
IO3_7\VREF
7
IO1_5
IO4_7
8
IO2_5\VREF
IO5_7
4
IO3_5
IO6_7
4
IO4_5
IO7_7
3
IO5_5
IO8_7
5
I46
U27
BANK 5
BANK 7
XC2S50_BGA
IO6_5
IO9_7\VREF
4
IO7_5
IO10_7
2
IO8_5\VREF
IO11_7
2
IO9_5
IO12_7\IRDY
1
IO10_5
IO13_7
3
IO11_5
IO14_7
1
IO12_5
IO15_7
10
IO13_5
IO16_7
9
D_DUT<7..0>
IO14_5
IO17_7
D
SPARE_A<10..1>
IO15_5
IO18_7
I34
CONN_THRU-HOLE
NA
NA
J46
5
IO16_5
IO19_7
6
IO17_5
IO20_7
7
IO1_7
9
8
7
6
5
4
3
2
1
6
USERFPGA2
INT5
A_DUT<11..0>
5
11
10
9
8
7
6
5
4
3
2
1
0
8
IO2_7
4
7
6
5
4
3
2
1
0
IO19_5
R8
E4
T4
T11
P12
T14
F2
P13
P8
N11
R13CPUCLK_OUT
N5
M6
P11
F1
N9
C2
L3
R7
M4
IO18_5
IO21_7
BANK 6
IO22_7
RW_X
CS_X1
WR
CS_X2
H1
J1
J3
P6
M11
K1
M3
P5
N1
R1
L1
N6
IO2_6
IO3_6
IO4_6\VREF
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO10_6\VREF
IO11_6
IO12_6
IO13_6
4
5
4
3
2
1
0
G4
H2
K3
P7
T8
IO18_6
IO19_6
IO20_6
IO21_6
IO22_6
IO23_6
XD<7..0>
BUS MODE
DETECTION (DUT AT CS_X2)
2
2
1
ENGINEER:
3
09/16/2004
PAGE: 5/7(BLOCK)
17/71(TOTAL)
STEVE SCULLY
DATE:
1
TITLE: DS33Z11/41/44DK01A0
WE ALSO FUNCTIONS AS ALT_WR_RW
RW ALSO FUNCTIONS AS ALT_RD_DS
6
F5
IO16_6
G5
F4
IO15_6
IO17_6
7
L4
G2
IO14_6
BIS0_DUT
BIS1_DUT
RD_DUT
BTS_DUT
WR_DUT
J2
ALE_DUT
3
IO1_6\TRDY
T9
P10
C1
R11
D1
E1
K4
G3
H3
M10
K2
G1
A2
E3
D2
F3
E2
J4
R12
K5
L5
M7
N7
IO23_7
CR-17 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page5
BANK 4
CS_X3
CS_X4
CS_X5
CS_X6
ALE
A
B
C
D
A
B
C
D
8
8
RESET_B
V3_3
A_DUT<11..0>
SCK
MISO
MOSI
SS
13
15
17
19
21
23
2
3
4
5
6
7
7
11
1
49
47
45
43
41
39
37
35
33
31
29
27
25
9
7
5
3
1
0
7
5V2
5V1
USER17
ALE
RD
WR
AD0
AD1
3.3V1
3.3V2
AD2
AD3
AD4
AD5
AD6
AD7
CS2
CS3
CS4
CS5
CS6
CS1
INT2
INT3
INT4
INT5
A8
USER16
USER15
USER14
USER13
USER12
USER11
USER10
USER9
USER8
USER7
USER6
USER5
USER4
USER3
USER2
USER1
GND4
A9
A10
GND2
GND3
A11
GND1
1
50
48
46
WR_DUT
ALE_DUT
6
INT4
INT3
INT2
INT5
D_DUT<7..0>
CS_X1
CS_X6
CS_X5
CS_X4
CS_X3
CS_X2
A_DUT<11..0>
RD_DUT
0
42
44
2
3
38
40
4
36
5
6
32
34
7
8
30
28
26
24
22
20
18
16
14
12
10
8
9
10
4
6
11
2
J42
CONN_50P_T1E1
MBVER
6
5
5
V3_3
4
4
10K
10K
CR-18 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page6
2
R257
1
2
R256
1
2
10K
R253
1
2
10K
R252
1
3
WR_DUT
RD_DUT
CS_X1
CS_X2
CS_X3
WR
RW_X
XA<15..0>
15C3<> 4C3^ 18A7<
3
STEVE SCULLY
2
1
ENGINEER:
19B1<
09/16/2004
PAGE: 6/7(BLOCK)
18/71(TOTAL)
OUT 17A4<> 18B6<> 4C3^
OUT 17A4<> 18B6<> 4C3^
OUT 17B3<> 18B6<> 4D3^
OUT 17B3<> 18B6<> 4D3^
OUT 17A4<> 18B6<> 4C3^
OUT 17B3<> 4C3^
OUT 17B3<> 4C3^
OUT 17C3<> 18A6<> 4C3^
OUT 17C3<> 18A6<> 4C5^
OUT 4C5^ 17A6 18B7 18C6
OUT
IO
IO
19A6<> 4B4^
19A6<> 4B4^
19A6<> 4B4^
19A6<> 4B4^
OUT
13B5<>
4C5^
4C5^
4D5^
DATE:
XD<7..0>
D_DUT<7..0>
13A4>
17A6<> 18C6<>
14C3<> 18C6<>
14D3<> 18C6<>
18C6<> 4D5^
17C3<> 4B5^
17C3<> 4C5^
17C3<> 4B5^
OUT
14C3<>
13A7<>
13A7<>
13A7<>
1
TITLE: DS33Z11/41/44DK01A0
17B7 4B3^
TDO_NU
TCK_NU
TDI_NU
TMS_NU
CS_X4
CS_X5
INT5
INT4
INT3
INT2
RESET_B
BTS_DUT
BIS0_DUT
BIS1_DUT
A_DUT<11..0>
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
A
B
C
D
A
B
8
DONE
10K
10
9
8
7
6
5
4
3
2
GND
DNC6
CEO*
DNC5
DNC4
DNC3
TDO
VCCINT
VCCO
VCCJ
JTD_FLASH_TDO
9
7
6
5
10
TDI_NU
6
10
7
TDO_NU
TMS_NU
8
TCK_NU
4
6
V3_3
JTD_FLASH_TDO
2
11
12
13
14
15
16
17
18
19
CONN_10P
9
8
4
3
7
2
1
J44
V3_3
XILINX_XCF01S
CE*
DNC2
OE/RST*
CF*
TCK
TMS
TDI
CLK
DNC1
ONCE_TCLK 1
XI_TMS
3
JTD_SPART_TDI
5
CCLK
JTD_SPART2FLASH
XI_TMS
ONCE_TCLK
XRST
RB333
V2_5XI 1
2X_INIT
D0
10K
20
VCCO5
VCCO6
VCCO7
VCCO8
VCCO9
VCCO10
VCCO11
VCCO12
VCCO13
VCCO14
VCCO15
VCCO16
H11
H12
J11
J12
L9
M9
L8
M8
J5
J6
H5
H6
VCCO3
E9
VCCO4
VCCO2
F8
F9
VCCO1
E8
GND2
1
GND1
2
CB271
1
GND3
1UF
CB467
GND4
2
CB49
1
GND6
CFG_DIN
2
GND7
C
V3_3
GND8
V3_3
1
GND9
2
1
GND5
2
1UF
CB69
1
1
1UF
CB485
2
1
GND10
4
3
2
IN
IN
SHDN
RST
GND14
1UF
CB412
VCCINT2
1
1UF
CB1221
.1UF
CB80 2
.1UF
CB320
2
.1UF
GND11
VCCINT3
5
6
7
8
VCCINT10
VCCINT9
CONTROL
V3_3
XC2S50_BGA
U27
GND
SET
OUT
OUT
MAX1792
GND16
1
1
1
VCCINT5
GND17
2
GND12
VCCINT6
2
GND18
VCCINT1
.1UF
2 CB1211
GND13
VCCINT7
GND19
1UF
VCCINT4
U31
1
GND20
C212 2
.1UF
CB2652
.1UF
C211
1
.1UF
GND15
VCCINT8
C210 2
.1UF
GND21
V3_3
GND24
1
C153
2
GND22
VCCINT12
C3
C14
D4
D13
E5
E12
M5
M12
N4
N13
P3
P14
3
V2_5XI
2
GND34
4
GND25
VCCINT11
GND23
5
GND27
1
10UF
C181
2
GND26
U29
6
1UF
GND29
1
1UF
C143
2
GND28
7
GND30
1
CB383
2
GND31
D
1
R214
2
1UF
GND32
8
GND35
GND33
CR-19 : @\_ztop_lib\.\_ztopdn_\(sch_1):page1_i5@\_ztop_lib\.\_z11top_dn\(sch_1):page2_i47@\_ztop_lib\.\_motprocrescard_dn\(sch_1):Page7
A15
C4
B14
P15
D15
R14
TDI
TCK
TDO
PROGRAM*
CCLK
DONE
5
4
1
P4
NC1
3
STEVE SCULLY
2
1
ENGINEER:
R4
NC2
V3_3
09/16/2004
PAGE: 7/7(BLOCK)
19/71(TOTAL)
R3
M2
CCLK
DONE
RESET_B
2
DATE:
P2
M1
330
R161
TITLE: DS33Z11/41/44DK01A0
N3
M0
XI_TMS
1
JTD_SPART_TDI
ONCE_TCLK
JTD_SPART2FLASH
XRST
D3
TMS
GND36
A1
A16
B2
B15
F6
F7
F10
F11
G6
G7
G8
G9
G10
G11
H7
H8
H9
H10
J7
J8
J9
J10
K6
K7
K8
K9
K10
K11
L6
L7
L10
L11
R2
R15
T1
T16
A
B
C
D
A
B
OUT
5
8
1/10(BLOCK)
GND
M8
A10
C9
CS
RD
WR
54C7<> IN
55A3<>
7
54C7<> IN
55A4< IN
V3_3
RESET_AH
1
DVSS23
DVSS22
DVSS21
DVSS13
DVSS12
DVSS11
WR*
RD*
CS*
TSTRST
TEST2
TEST1
RPOSI
RNEGI
RCLKI
MCLK2
MCLK1
LIUC
6
V3_3
V3_3
V3_3
R114 2
330
1
RED
2
DS25
I38
BLOCK NAME: _quadte1wan_dn.
N4
N5
N6
D11
D12
D13
D9
H4
J12
H9
H10
G8
J14
J13
K15
MCLK
55A2<>
46A1<> IN
46D7<
51D7<
LIUC
INT*
WAN_INTH5
55D5> 46A4<> OUT
JTDI
JTCLK
JTMS
JTDO
JTRST
K14
XI_TMS
J15
52C1< 52C8<> 52A7<>
ONCE_TCLK
K16
52C1< 52C8<> 52A7<>
JTD_FLASH_TDO
C10
52C6<>
K13
52A7<> JTDO458
53B6<>
2
DVSS31
MCLK2FPGA
DVSS32
46C7<
2
MCLK
DVDD11
2
DVSS33
30
RB184
30
DVDD12
DVSS41
RB160
DVDD21
2
DVSS43
C
4
DVDD13
2
DVSS42
D
DVDD22
C42
10UF
C48
10UF
CB236
10UF
CB126
10UF
CB154
10UF
C103
1
RVSS11
V3_3
2
RVSS12
8
DVDD23
RVSS13
VCC
DVDD31
2
1
OSC
DVDD32
RVSS21
CONTROL
DS21458_U
U20
RVDD1
1
3
BUFFER
4UX11
1
WAN_INT
4
46C7> 55D5>
PARENT BLOCK: \_wan4z44_dn\
5
I37
NC7SZ86_U
NA
NC7SZ86
V3_3
ESIBS<1>
ESIBS<0>
ESIBRD
MUX
BTS
AD<7>
AD<6>
AD<5>
AD<4>
AD<3>
AD<2>
AD<1>
AD<0>
A<9>
A<8>
A<7>/ALE_AS
A<6>
A<5>
A<4>
A<3>
A<2>
A<1>
A<0>
DS21458 WAN INTERFACE BLOCK
DVDD33
1
CB179 1
0.1UF
CB144 1
0.1UF
CB161 1
0.1UF
CB160 1
0.1UF
CB156 1
0.1UF
CB120 2
0.1UF
CB204 1
0.1UF
CB138 1
0.1UF
CB205 2
0.1UF
RVSS22
RVDD2
YB02
4
RVDD4
RVSS43
I73
5
TVDD11
2.048MHZ_3.3V
6
TVDD12
TVSS11
7
NC1
8
CR-46 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE1
DVDD41
10UF
CB151
10UF
CB340
10UF
CB112
10UF
RVSS23
TVDD21
TVSS21
DVDD42
RVSS31
TVDD22
TVSS22
DVDD43
RVSS32
TVDD31
TVSS31
H1
J16
A9
T8
RVSS33
TVDD32
TVSS32
P4
P5
P6
C11
C12
C13
D3
E3
F3
L14
M14
N14
D4
E4
F4
L13
M13
N13
TVSS41
RVDD3
RVSS41
RVSS42
TVDD41
R6
T6
A11
B11
F1
F2
L15
L16
TVSS12
N1
J1
M1
E16
H16
D16
A5
A8
A4
T12
T13
T9
NC2
TVDD42
1 CB155 2
0.1UF
1 CB127 2
0.1UF
2 CB200 1
0.1UF
2 CB220 1
0.1UF
TVSS42
R5
T5
A12
B12
E1
E2
M15
M16
NC3
B10
R8
H8
J8
J9
P8
D10
N8
P7
M7
R7
G1
G3
H2
E10
H3
G4
N7
B9
T7
G2
H6
J11
52B1< 55D6<>
RESET_B 1
3
ENGINEER:
STEVE SCULLY
2
I41
4
54C3 55A2 55A4
46B7<
1
INVERTER
09/16/2004
1
46/71(TOTAL)
PAGE:
DATE:
NA
NC7SZ86
NC7SZ86_U
UXB05
RESET_AH
IO
IN 54C7 55A5 55A7
DAT<7..0>
BTS 51C7<
MUX 51B7<
ESIBRD 51C7<
ESIBR0 51C7<
ESIBR1 51C7<
7
6
5
4
3
2
1
0
9
8
7
6
5
4
3
2
1
0
ADDR<9..0>
2
TITLE: DS33Z11/41/44DK01A0
K9
P3
E9
A
B
C
D
A
B
C
D
51A6<>
53D7<
53D5<>
53B7<> IN
RPOSO
J6
TLCLK
TSYNC
TSSYNC
TSYSCLK
RLCLK
RSYNC
RMSYNC
RSYSCLK
7
RLOS/LOTC
RFSYNC
BPCLK
TCHCLK
RCHCLK
RSIGF
TCHBLK
TSIG
RSIG
RCHBLK
TSER
RSER
TPOSI
TPOSO
TNEGI
TNEGO
RNEGO
J4
K2
K3
RGAPCLK1
L2
M2
RSYNC1
K6
M3
RSYSCLK1 J3
L3
K4
RLOS1
K5
RSER1
TCLKO
RCLKO
TCLKI
TCLK
TTIPB
TTIPA
TRINGB
TRINGA
RCLK
PORT
TLINK
K8
R1
RCLK1
RTIP
RRING
RLINK
K1
RTIP1
49C8<
6
49D8<
5
49A5<
RRING2
F16
PORT2_RRING = PIN F16
3
53D4<>
53A2<>
TSSYNC1 53D5<>
TSYSCLK1 53D7<
BPCLK1 53C6<>
TSYNC1
IO
IN 53B2<>
IN 53B2<>
49D8<
TGAPCLK1
TSER1
TCLK1
TTIP1
4
51A6<>
53D7<
RTIP2
H12
C15
H11
F10
C14
G16
H14
G15
G10
RGAPCLK2G11
F15
RSYNC2 E14
G13
RSYSCLK2H15
F14
G14
RLOS2
E15
RSER2
RCLK2
53D5<>
53B7<> IN
53C2< 53A7<> OUT
53B7<> OUT
49A5<
TSSYNC
TSYSCLK
RMSYNC
RSYSCLK
53D4<>
IO
53A2<>
IN 53B2<>
IN 53A2<>
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 2/10(BLOCK)
47/71(TOTAL)
TSSYNC2 53D4<>
TSYSCLK2 53D7<
TSYNC2
TGAPCLK2
TSER2
49B5<
49C5<
TCLK2
TTIP2
TRING2
1
DATE:
A13
B13
A14
B14
G12
A15
F12
F11
B15
E12
A16
F13
G9
E11
E13
D15
C16
B16
D14
J10
H13
2
TITLE: DS33Z11/41/44DK01A0
RLOS/LOTC
RFSYNC
BPCLK
TSYNC
RSYNC
RSIGF
TLCLK
TCHCLK
RCHCLK
RLCLK
TCHBLK
TSIG
RSIG
RCHBLK
TSER
RSER
TPOSI
TPOSO
TNEGI
TNEGO
RNEGO
RPOSO
TLINK
RLINK
TCLKI
TCLKO
RCLKO
TTIPB
TTIPA
TRINGB
TRINGA
TCLK
PORT
RCLK
RTIP
RRING
DS21458_U
4
DS21458_U
TRING1
5
U20
R4
T4
R3
T3
L5
T2
L6
K7
T1
M5
R2
L4
M6
L7
N2
J7
P1
N3
M4
H7
J5
6
U20
P2
J2
L1
RRING1
49C8<
53C2< 53A7<> OUT
8
7
PORT1_RRING = PIN L1
53B7<> OUT
8
CR-47 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE2
A
B
C
D
A
B
C
D
8
7
51A6<>
53D7<
53D4<>
53B7<> IN
TCLKO
RCLKO
TNEGO
RNEGO
RPOSO
F9
TLCLK
TSYNC
TSSYNC
TSYSCLK
RLCLK
RSYNC
RMSYNC
RSYSCLK
RLOS/LOTC
RFSYNC
6
BPCLK
TCHCLK
RCHCLK
RSIGF
TCHBLK
TSIG
RSIG
RCHBLK
TSER
RSER
TPOSI
TPOSO
TNEGI
TLINK
TCLKI
TCLK
TTIPB
TTIPA
TRINGB
RCLK
PORT
TRINGA
RLINK
7
RRING
RTIP
TRING3
50D8<
53D4<>
53A2<>
TSSYNC3 53D4<>
TSYSCLK3 53C7<
TSYNC3
53A2<>
IN 53B2<>
IN
50D8<
TGAPCLK3 IO
TSER3
TCLK3
TTIP3
5
4
53B7<>
RSER4
RCLK4
RTIP4
N10
T15
P10
K12
P14
T10
P9
R10
R11
RGAPCLK4 M9
IN
R12
53D4<> RSYNC4 N12
M10
RSYSCLK4
R9
53D7<
N11
P11
P12
51A6<> RLOS4
53C2< 53A7<> OUT
53B7<> OUT
50A5<
50A5<
RRING4 T11
TSSYNC4 53D4<>
TSYSCLK4 53C7<
53A2<>
IN 53B2<>
IN 53A2<>
IO
53D4<>
TGAPCLK4
TSER4
TSYNC4
50B5<
50C5<
TCLK4
TTIP4
TRING4
3
STEVE SCULLY
2
1
ENGINEER:
N15
N16
P15
P16
L9
R16
L11
L12
T16
M12
R15
L10
K10
K11
R13
P13
T14
R14
M11
L8
N9
09/16/2004
PAGE: 3/10(BLOCK)
48/71(TOTAL)
BPCLK
TSYSCLK
TSSYNC
TSYNC
TLCLK
TCHCLK
TCHBLK
TSIG
TSER
TPOSI
TPOSO
TNEGI
TNEGO
TLINK
TCLKI
TCLKO
TCLK
TTIPB
TTIPA
TRINGB
TRINGA
1
DATE:
PORT
2
TITLE: DS33Z11/41/44DK01A0
RLOS/LOTC
RFSYNC
RSIGF
RSYSCLK
RMSYNC
RSYNC
RLCLK
RCHCLK
RCHBLK
RSIG
RSER
RPOSO
RNEGO
RLINK
RCLKO
RCLK
RTIP
RRING
PORT4_RRING = PIN T11
3
DS21458_U
D1
D2
C1
C2
F6
B2
F7
G7
A1
E5
B1
D5
G6
F5
C5
B4
C4
B3
A3
D8
E8
4
DS21458_U
C3
F8
C8
B7
C7
RGAPCLK3D7
B6
RSYNC3
B5
E6
RSYSCLK3 B8
E7
C6
RLOS3
D6
RSER3
RCLK3
50C8<
53B7<> OUT
A7
RTIP3
50C8<
G5
A2
A6
RRING3
5
U20
6
U20
PORT3_RRING = PIN A6
53C2< 53A7<> OUT
8
CR-48 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE3
A
B
C
D
A
B
C
2
32
31
RB3272
0
1
L10
RCV
35
34
33
8
9
10
I14
L10
XMIT
7
I11
6
RB3282
0
1
1
1UF
C176
7
C2
C4
C6
C8
1
3
5
7
RJ45
2
4
6
8
C1
C3
C5
C7
JB12
I13
RJ45_4PORT
6
8
7
6
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
RRING1
RTIP1
TRING1 1
R207 2
0
R208 2
0
1
2
1
CB395
2
D
1
1
2
0.1UF
TTIP1
8
5
5
47C4<
47C4<
47C2>
47C2>
RRING2
RTIP2
TRING2 1
TTIP2
1
R203 2
0
R204 2
0
4
2
4
22
21
RB3212
0
1
L10
RCV
25
24
23
18
19
20
I26
L10
XMIT
17I2
16
RB3222
0
1
1
1UF
C173
1
2
1
CB390
2
CR-49 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE4
1
2
RB317
61.9
RB313
61.9
0.1UF
RB316
61.9
RB312
61.9
3
1
3
5
7
RJ45
2
4
6
8
A1
A3
A5
A7
JB12
3
ENGINEER:
STEVE SCULLY
2
TITLE: DS33Z11/41/44DK01A0
A2
A4
A6
A8
I25
RJ45_4PORT
2
1
09/16/2004
PAGE: 4/10(BLOCK)
49/71(TOTAL)
DATE:
1
A
B
C
D
A
B
C
D
2
37
36
RB3292
0
1
L10
RCV
40
39
38
3
4
5
I25
L10
XMIT
2
I24
1
RB3302
0
1
1
1UF
C175
7
D2
D4
D6
D8
1
3
5
7
RJ45
2
4
6
8
D1
D3
D5
D7
JB12
I19
RJ45_4PORT
6
8
7
6
THE PCB LAYOUT INCORRECTLY USES PINS 38-40, 33-35, 28-30 AND 23-25
AS THE TX PRIMARY. THIS HAS BEEN CORRECTED IN THE SCHEMATIC,
THE PCB / ASSEMBLY HAS BEEN MODIFIED TO ACCOMMODATE THIS.
RRING3
RTIP3
R201 2
0
R202 2
0
1
2
1
CB396
2
TRING3 1
1
1
2
0.1UF
TTIP3
8
5
5
RTIP4
RRING4
48C4<
TRING4 1
TTIP4
48C4<
48C1>
48C1>
1
R205 2
0
R206 2
0
4
2
4
27
26
RB3232
0
1
L10
RCV
30
29
28
13
14
I915
L10
XMIT
12I7
11
RB3242
0
1
1
1UF
C174
1
2
1
CB391
2
CR-50 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE5
1
2
RB319
61.9
RB315
61.9
0.1UF
RB318
61.9
RB314
61.9
3
1
3
5
7
RJ45
2
4
6
8
B1
B3
B5
B7
JB12
3
ENGINEER:
STEVE SCULLY
2
TITLE: DS33Z11/41/44DK01A0
B2
B4
B6
B8
I8
RJ45_4PORT
2
1
09/16/2004
PAGE: 5/10(BLOCK)
50/71(TOTAL)
DATE:
1
A
B
C
D
A
B
C
D
8
8
7
46A2<
46A2<
46A2<>
46A2<>
46A2<>
46C7<
RB2512
330
RB2842
330
1
RB2342
330
1
1
RB2212
330
1
MUX
1
2
2
DS34
2
DS33
2
1
1
1
1
DS30
RB3032
2.0K
RB2282
2.0K
RB1832
2.0K
RB1922
2.0K
RB2092
2.0K
RB1852
2.0K
DS32
1
BTS
1
ESIBR0
1
1
ESIBRD
ESIBR1
1
LIUC
ALL UNMARKED BIAS RESISTORS ARE 10K
7
NOTMUX
MOT
V3_3
6
RLOS4
RLOS3
RLOS2
RLOS1
6
48A4>
48A8>
47A4>
47A8>
5
5
CR-51 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE6
4
4
3
2
1
ENGINEER:
3
09/16/2004
PAGE: 6/10(BLOCK)
51/71(TOTAL)
STEVE SCULLY
DATE:
1
TITLE: DS33Z11/41/44DK01A0
2
A
B
C
D
A
B
C
0.1UF
2 C135 1
0.1UF
0.1UF
2 C85 1
7
9
TDI_NU
TCK_NU
TMS_NU
8
3
5
TDO_NU
1
10
8
6
4
2
VCCO
VCCINT
TDO
DNC3
DNC4
DNC5
CEO*
DNC6
GND
DNC1
CLK
TDI
TMS
TCK
CF*
OE/RST*
DNC2
CE*
JTDO458
V3_3
XILINX_XCF01S
VCCJ
D0
46C7>
20
19
18
17
16
15
14
13
12
11
6
7
JTD_SPART_TDI 52C1<
8 ONCE_TCLK 52C8<> 46C7<
10 XI_TMS
52C8<> 46C7<
4
2
CONN_10P
9
7
5
3
1
JB07
1
2
CCLK
3
52B1<>
JTD_SPART2FLASH 4
5
46C7< 52A7<> XI_TMS
52C1<
ONCE_TCLK
6
46C7< 52A7<>
52C1<
7
52B1< XRST
R84
V2_5XI 2
1X_INIT 8
10K
9
10
52B1<> DONE
CFG_DIN
2 CB245 1
53B2<>
52C1<
52C1<
JTD_FLASH_TDO
6
46C7<
VCCO5
VCCO6
VCCO7
VCCO8
VCCO9
VCCO10
VCCO11
VCCO12
VCCO13
VCCO14
VCCO15
VCCO16
H11
H12
J11
J12
L9
M9
L8
M8
J5
J6
H5
H6
VCCO3
E9
VCCO4
VCCO2
F8
F9
VCCO1
E8
GND1
2
C77
1
GND2
2 CB257 1
GND4
V3_3
GND6
1UF
C188
GND3
C22
0.1UF
2
GND7
V3_3
GND8
0.1UF
2 CB190 1
2
0.1UF
2 CB150 1
1
2 CB168 1
2
1UF
C23
1
0.1UF
2 CB134 1
1
GND9
U08
GND10
2
1
GND5
1
1UF
CB65
2
0.1UF
2 C108 1
1
SHDN
RST
VCCINT2
GND14
0.1UF
1UF
CB66
IN
U10
GND
SET
OUT
OUT
8
7
6
5
VCCINT9
CONTROL
V3_3
XC2S50_BGA
GND16
1UF
CB2751
.1UF
CB1352
.1UF
CB216
2
.1UF
GND11
IN
1
2
VCCINT4
MAX1792
GND17
1
VCCINT6
2
GND18
VCCINT1
.1UF
GND13
VCCINT7
GND19
1
2
3
4
1
VCCINT3
1
VCCINT8
GND20
1UF
VCCINT5
UB06
2
GND22
CB2782
.1UF
CB3382
.1UF
CB269
1
.1UF
GND15
VCCINT10
C114
1
GND23
V3_3
2
GND24
D
2
GND25
V3_3
2
GND26
C192 2
.1UF
GND21
2
VCCINT11
2
1
10UF
C86
VCCINT12
C3
C14
D4
D13
E5
E12
M5
M12
N4
N13
P3
P14
2 CB3371
GND12
3
V2_5XI
2
GND28
4
1UF
GND29
52B8<
1
5
GND30
1
1UF
CB230
CB62 1
0.1UF
C123 1
0.1UF
C142 1
0.1UF
C125 1
0.1UF
GND27
6
1UF
GND32
CB274
2
GND31
7
2
GND34
8
GND35
GND33
CR-52 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE7
C4
B14
P15
TCK
TDO
PROGRAM*
5
4
1
P4
NC1
3
STEVE SCULLY
2
1
ENGINEER:
R4
NC2
V3_3
52B8<>
52C8<>
09/16/2004
PAGE: 7/10(BLOCK)
52/71(TOTAL)
R3
M2
CCLK
DONE
DATE:
P2
M1
330
RESET_B
2
RB129
TITLE: DS33Z11/41/44DK01A0
N3
R14
DONE
M0
D15
CCLK
XI_TMS
1
JTD_SPART_TDI
ONCE_TCLK
JTD_SPART2FLASH
XRST
A15
TDI
52B8<>
D3
TMS
GND36
A1
A16
B2
B15
F6
F7
F10
F11
G6
G7
G8
G9
G10
G11
H7
H8
H9
H10
J7
J8
J9
J10
K6
K7
K8
K9
K10
K11
L6
L7
L10
L11
R2
R15
T1
T16
A
B
C
D
A
B
C
8
48B1<
7
53C2< 48B4>
53C2< 48B8>
53C2< 47B4>
53C2< 47B8>
48C4>
48C8>
47C4>
47C8>
48B4<
48B8<
47B4<
47B8<
TSYSCLK4
TSYSCLK3
MCLK2FPGA
BPCLK1
RGAPCLK1
RGAPCLK2
RGAPCLK3
RGAPCLK4
RCLK1
RCLK2
RCLK3
RCLK4
RSER1
RSER2
RSER3
RSER4
46D7<
47B6>
TSYSCLK
6
IO11_0
IO12_0
IO13_0
IO14_0
IO15_0
IO16_0
IO17_0
IO18_0
IO19_0
IO20_0
C8
D7
E7
B5
D6
A4
E6
D5
C5
IO7_0\VREF
B4
A6
IO6_0
C6
IO10_0
IO5_0
A5
D8
IO4_0
B6
IO9_0
IO3_0
C7
IO8_0
IO2_0\VREF
B7
B3
IO1_0
A7
A3
GCK3
B8
IO3_1
IO4_3\VREF
48B5<
IO4_1\VREF
IO5_3
TSYSCLK2
IO5_1
IO6_3
47B2<
47B8<>
IO6_1
IO7_3\D6
TSYSCLK1
47B6<
IO7_1
IO8_3\D5
47B6<
IO8_1
IO9_3
RSYSCLK4
IO1_1\CS*
IO2_3\D7
GCK2
IO1_3\INIT*
IO2_1\WRITE*
IO3_3
48B5<
48B8<>
U10
BANK 1
BANK 3
XC2S50_BGA
IO9_1\VREF
IO10_3\VREF
48B4<
47B4<>
IO10_1
IO11_3\D4
48B8<
47B2<
IO11_1
IO12_3
RSYSCLK
48B4<>
IO14_1
IO15_3
RSYSCLK3
IO16_1
IO17_3
RSYSCLK2
47B6<>
IO17_1
IO18_3
47B4<
47B2<>
IO18_1
IO19_3
RSYSCLK1
48B5<>
IO19_1
IO20_3
47B8<
48B1<
IO15_1
IO16_3
X_INIT
5
4
H13
G13
F15
E16 SPARE_TP1 TP32
IO4_2
IO5_2
IO6_2\D2
IO7_2\D1
48B5<
48B1<
47C5<
47C1<
48C5<
48C1<
47B5<>
47B1<>
48B5<>
48B1<>
J13TSER3
G14TSER4
G15 TCLK1
G12 TCLK2
F16 TCLK3
F12 TCLK4
E15 TGAPCLK1
E14 TGAPCLK2
C16 TGAPCLK3
B16 TGAPCLK4
IO15_2
IO16_2
IO17_2
IO18_2
IO19_2
IO20_2
IO21_2
IO22_2
IO23_2
IO24_2
3
ENGINEER:
STEVE SCULLY
2
1
RSER2
RSER3
RSER4
RSER1
TSER PULLDNS USED IN IBO MODE
(IMPLEMENTS IMUX)
TITLE: DS33Z11/41/44DK01A0
47B1<
52C8<>
H14TSER2
C15
IO13_2\(DOUT,BUSY)
CFG_DIN
47B5<
IO14_2
D14
IO12_2\(DIN,D0)
53A7<> 48B4>
53A7<> 48B8>
SPARE_TP2 TP30
E13TSER1
F13
IO10_2\VREF
IO11_2
D16
IO9_2
F14
G16
IO3_2\D3
53A7<> 47B4>
H15
IO2_2\VREF
IO8_2
2
53A7<> 47B8>
H16
IO2_1\IRDY
3
2.0K
4
R88
5
2.0K
6
R113
7
1
09/16/2004
PAGE: 8/10(BLOCK)
53/71(TOTAL)
DATE:
2.0K
D
8
R104
CR-53 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE8
2.0K
48B1<>
IO20_1
BANK 2
IO21_3
IO12_1
IO13_3\TRDY
IO21_1
IO22_3
1
1
IO13_1
IO14_3
IO22_1
IO23_3
N15
N14
M13
L14
P16
L13
N16
M16
K14
K16
J16
K15
J15
T15
R16
M14
M15
L12
L16
K13
L15
K12
J14
52B8<>
R94
C9
B13
C13
A14
C11
E11
B11 RSYNC1
A11 TSSYNC1
C10
B9
D9 RSYNC2
A8 TSSYNC2
C12 RSYNC3
D12 TSSYNC3
B12 RSYNC4
A13 TSSYNC4
D11
A12 TSYNC1
B10 TSYNC2
D10 TSYNC3
A10 TSYNC4
E10
A9
BANK 0
A
B
C
D
A
B
T3ENH_T1ENLPRT4
T3ENH_T1ENLPRT3
T3ENH_T1ENLPRT2
T3ENH_T1ENLPRT1
Z44_TDEN<2>
Z44_RDEN<2>
Z44_TCLK<2>
Z44_RCLK<2>
Z44_TSER<2>
Z44_RSER<2>
Z44_TDEN<1>
Z44_RDEN<1>
Z44_TCLK<1>
Z44_RCLK<1>
Z44_TSER<1>
Z44_RSER<1>
46B7< 55A2<>
IO3_4\VREF
P9
WR
RD
R48
R47
IO7_4
IO8_4
IO9_4\VREF
IO10_4
IO11_4
IO12_4
IO13_4
IO14_4
IO15_4
IO16_4
IO17_4
IO18_4
IO19_4
IO20_4
IO21_4
IO22_4
N11
T12
R13
P13
T9
M10
R10
P10
R12
P11
T13
N12
P12
N10
T14
IO6_4
IO5_4
N2
M11
R11
IO4_4
IO2_4
R9
CS_X4 K5
IO1_4
IO5_5
IO8_7
IO4_5
IO7_7
GCK1
IO3_7\VREF
8
7
6
U10
BANK 5
BANK 7
XC2S50_BGA
5
PORTS ARE ENABLED BY DEFAULT ON T1 BRD, AND ARE DISABLED USING JUMPERS ON T3 BRD
55B2<> 54A5<>
55C2<> 54A5<>
55C6<> 54A5<>
55D6<> 54A6<>
55C8<>
55C6<>
55C8<>
55C6<>
55C8<>
55C6<>
55D8<>
55D6<>
55C8<>
55C6<>
55C8<>
55C6<>
Z41RSYNC
55C6<>
46B7< 55A3<>
Z41TSYNC
55C6<>
55D2<>
0
1
GCK0
IO6_5
IO9_7\VREF
N9
IO7_5
IO10_7
C
2.0K
IO8_5\VREF
IO11_7
ADDR<9..0>
RB04
IO9_5
IO12_7\IRDY
55A7 55A5 46C2<
RB05
IO10_5
IO13_7
N8
IO1_5
IO4_7
54A8<
2.0K
IO11_5
IO14_7
2
IO1_7
5
4
IO16_5
IO19_7
IO15_5
IO18_7
IO14_5
IO17_7
D
IO2_7
IO12_5
IO15_7
6
IO17_5
IO20_7
7
IO18_5
IO21_7
8
CR-54 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE9
IO2_5\VREF
IO5_7
54A8<
30
30
30
30
30
30
30
30
30
30
2.0K
IO3_5
IO6_7
54A8<
2.0K
BANK 6
IO22_7
IO13_5
IO16_7
IO19_5
R8
L5
T4
N6
R5
P6
R6
M7
P8
M4
N5
M3
J4
M6
K2
N7
T6
P7
R7
K3
54A8<
R73
R46
R52
R72
R45
R54
R53
R49
R51
R50
RB45
4
3
2
1
0
J3
L1
L2
K4
L3
L4
IO4_6\VREF
IO5_6
IO6_6
IO7_6
IO8_6
IO9_6
IO23_6
IO22_6
IO21_6
IO20_6
IO19_6
IO18_6
IO17_6
IO16_6
IO15_6
IO14_6
IO13_6
IO12_6
IO11_6
T2
T3
M1
P1
M2
P5
K1
T8
T10
T5
T7
R1
T11
Z44_TSER<3>
RB101 30
OBS_RDEN<3>
R44 30
R42
OBS_RCLK<3>
OBS_TCLK<3>
RB94 30
30
30
R39
OBS_RCLK<4>
30
RB93
OBS_TCLK<4>
30
RB92
OBS_RDEN<4>
30
R40
OBS_TDEN<4>
30
Z44_TSER<4>
Z44_RCLK<4>
Z44_TCLK<4>
Z44_RDEN<4>
Z44_TDEN<4>
Z44_RSER<4>
Z44_RCLK<3>
Z44_TCLK<3>
Z44_RDEN<3>
Z44_TDEN<3>
Z44_RSER<3>
2
3
ENGINEER:
STEVE SCULLY
2
TITLE: DS33Z11/41/44DK01A0
TP13
TP25
TP12
TP24
TP14
R41
TP26 OBS_RSER<4>
30
TP28 OBS_TDEN<3>
TP16
TP15
TP27
TP17
DAT<7..0>
R43
OBS_RSER<3>
4
J1
IO3_6
TP29
5
H1
IO2_6
N1
7
55A4 55A2
46B1<>
6
J2
3
IO1_6\TRDY
IO10_6\VREF
IO23_7
C2
B1
C1
T3ENH_T1ENLPRT1E4
55D6<>
T3ENH_T1ENLPRT2D1
55C6<>
T3ENH_T1ENLPRT3E1
55C2<>
T3ENH_T1ENLPRT4F2
55B2<>
G3
H3
G4
G5
G1
A2
E3
D2
F3
E2
F1
F4
F5
G2
H2
H4
1
1
1
1
1
1
1
1
1
1
1
1
30
30
RB46
BANK 4
55B1<>
55B4<>
55B1<>
55B4<>
1
09/16/2004
PAGE: 9/10(BLOCK)
54/71(TOTAL)
DATE:
55B1<>
55B4<>
55C1<>
55C4<>
55B1<>
55B4<>
55C1<>
55C4<>
1
A
B
C
D
A
B
C
D
V3_3
GND
V3_3
Z44_RCLK<2>
54B8<
8
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
7
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
J12
46A4<> 46C7>
54B8<
GND
GND
GND
GND
GND
GND
GND
ADDR<9..0>
55A2 54C3 46B1<>
6
5
WAN R.C. CONNECTOR TO MOTHERBOARD
OSC3_NU
GND
GND
6
8
3
5
1
4
CS_X5
CS
6
GND
GND
GND
V3_3
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
GND
GND
GND
RD
5
7
1
3
0
55A4
3
2
1
ENGINEER:
STEVE SCULLY
09/16/2004
PAGE: 10/10(BLOCK)
55/71(TOTAL)
SIG_RETURN
DATE:
I27
1
TITLE: DS33Z11/41/44DK01A0
54C7<> 46B7<
GND
55A1> 55C6<>
54B1<
54A1<
DAT<7..0>
Z44_TCLK<4>
SIG_RETURN
Z44_TDEN<4>
Z44_TSER<4>
54B1<
54A5<> 54A8<
54B1<>
Z44_TCLK<3>
54B1<
54A5<> 54A8<
54B1<>
Z44_TDEN<3>
Z44_TSER<3>
T3ENH_T1ENLPRT3
ALE
CS_X4 54C7<>
T3ENH_T1ENLPRT4
54C3 46B1<>
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
2
NOTE 3184 IS ON CS3 WHILE 21455 IS ON CS2/CS4
CS_X2
V3_3
CS_X3
WR
I29
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
GND
V3_3
GND
GND
J09
RECEPTACLE
GND
OSC1_NU
Z44_RCLK<4>
Z44_RDEN<4>
Z44_RSER<4>
Z44_RCLK<3>
Z44_RDEN<3>
2
4
3
P1 CONNECTOR (RECEPTICAL)
Z44_RSER<3>
46B7< 54C7<>
46B7<
DAT<7..0>
54B1<
54B1<
54B1<
54B1<
54B1<
GND
46C2< 54C7 55A7
4
54B1<
54B8<
54B8<
55A1> 55B2<> 55C6<>
54B8<>
54A5<> 54A8<
Z44_TCLK<2>
TDO_NU 52A8<>
TCK_NU 52A8<>
5
55A1> 55B2<> 55C6<>
54B8<
54C7<
54C7<
Z44_TDEN<2>
Z44_TSER<2>
SIG_RETURN
T3ENH_T1ENLPRT2
Z41RSYNC
Z41TSYNC
Z44_TCLK<1>
Z44_TDEN<1>
SIG_RETURN
Z44_TSER<1>
54A6<> 54A8<
54B8<>
INT2 55D7<>
RESET_B 46A2<> 52B1<
WAN_INT
T3ENH_T1ENLPRT1
INT3
I28
6
GND
GND
GND
GND
GND
GND
GND
GND
P2 CONNECTOR (RECEPTICAL)
RECEPTACLE
7
GND
46C2< 54C7
55A5
V3_3
OSC2_NU
OSC4_NU
7
9
4
0
2
52A8<> TDI_NU
52A8<> TMS_NU
Z44_RDEN<2>
54B8<
Z44_RCLK<1>
54B8<
Z44_RSER<2>
Z44_RDEN<1>
54B8<
54A8<
Z44_RSER<1>
INT5
55D6<> INT2
54B8<
ADDR<9..0>
8
CR-55 : @\_ZTOP_LIB\.\_ZTOPDN_\(SCH_1):PAGE1_I11@\_ZTOP_LIB\.\_WAN4Z44_DN\(SCH_1):PAGE1_I1@\_ZTOP_LIB\.\_QUADTE1WAN_DN\(SCH_1):PAGE10
A
B
C
D