VS133-D512
60027054-01
DATA SHEET
Memory Module Part Number
VS133-D512
BUFFALO INC.
(1/7)
VS133-D512
60027054-01
1. Description
168pin Unbuffered DIMM
PC133/CL=3
2. Module Specification
Item
Capacity
Physical Bank(s)
Module Organization
Module Type
Speed Grade
Interface
Power Supply Voltage
Burst Lengths
DRAM Organization
PCB Part No.
PCB Layer
Contact Tab
Serial PD
Specification
512MByte
2
64M x 64bit
Unbuffered NonECC
PC133/CL=3
PC100/CL=2
LVTTL
3.3V±0.3V
1,2,4,8,Full
32M x 16bit SDR SDRAM
ZSZGVNF-A
6 Layers
168pin GOLD Flash Plating
Ni : min 2.00µm / Au : min 0.05µm
Support
3. Mechanical Design and Module Pinout
Item
Mechanical Design
and Pinout
Reference standard
Mechanical Design and Pinout SDR 168Pin DIMM
(PDRB-28998-X059-xx)
Y(PCB Height)
Z1
Z2
: 33.5 mm
: Undefined
: 4.52mm MAX(Double Sided)
4. Block Diagram
Item
Block Diagram
Reference standard
Block Diagram
PC133/PC100 Unbuffered DIMM(x16bitDRAM 2Bank)
(PDRB-28998-X067-xx)
BUFFALO INC.
(2/7)
VS133-D512
60027054-01
5. Electrical Specifications
5.1 Absolute Maximum Ratings
Parameter
Symbol
Voltage Any Pin Relative to Vss
Supply Voltage Relative to Vss
Power Dissipation
Short Circuit Output Current
VT
VCC
PD
IO
Value
-0.5~Vcc+0.5 (max 4.6)
-0.5~4.6
16
50
Unit
V
V
W
mA
5.2 Recommended Operating Conditions
Parameter
Symbol
MIN
MAX
Unit
VCC
VIH
VIL
TA
3.0
2.0
-0.3
0
3.6
Vcc+0.3
0.8
70
V
V
V
°C
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Operating Ambient Temperature
5.3 Pin Capacitance
CK2
CK3
CICK4
Maximum Pin
Capacitance
33
33
33
33
S0
S1
S2
S3
CIS1
CIS2
CIS3
CIS4
20
20
20
20
pF
pF
pF
pF
CKE Input Pin Capacitance
CKE0
CKE1
CICKE1
CICKE2
40
40
pF
pF
DQM Input Pin Capacitance
DQMB0,2,3,4,6,7
DQMB1
DQMB5
CIDQM1
CIDQM2
CIDQM3
20
20
20
pF
pF
pF
DQ0-DQ63
CB0-7
COUT1
COUT2
16
——
pF
pF
A,BA,/RAS,/CAS,/WE
CIN
80
pF
Parameter
CK Input Pin Capacitance
/S Input Pin Capacitance
DQ Input / Output Pin Capacitance
Other Input Pin Capacitance
Symbol
CK0
CK1
CICK1
CICK2
CICK3
Unit
pF
pF
pF
pF
BUFFALO INC.
(3/7)
VS133-D512
60027054-01
5.4 D.C. Characters
Parameter
Symbol
Operating current
Value
Unit
ICC1
MAX 1400 * mA
ICC2P
MAX
48
* mA
ICC2PS
MAX
40
* mA
ICC2N
MAX
640 * mA
ICC2NS
MAX
160 * mA
ICC3P
MAX
96
* mA
ICC3PS
MAX
96
* mA
ICC3N
MAX
480 * mA
ICC3NS
MAX
400 * mA
Precharge Standby current in power down mode
Precharge Standby current in non power down mode
Active standby current in power down mode
Active standby current in non power down mode
Operating current (Burst mode)
ICC4
MAX 1400 * mA
Auto refresh current
Self refresh current
ICC5
ICC6
Input leakage current
IIL
MAX 3520 * mA
MAX 80 * mA
MIN -80 * µA
Output High Voltage
Output Low Voltage
VOH
VOL
MAX
80
*
µA
MIN
MAX
2.4
0.4
*
*
V
V
Test Condition
Burst length=1,
tRC ≥ tRC (min),
IO=0mA,
One bank active
CKE ≤ VIL(max),
tCK = 12ns
CKE ≤ VIL(max),
tCK = ∞
CKE, /S ≥ VIH(min),
tCK = 12ns
CKE ≥ VIH (min),
tCK = ∞
CKE ≤ VIL(max),
tCK = 12ns
CKE ≤ VIL(max),
tCK = ∞
CKE, /S ≥ VIH(min),
tCK = 12ns
CKE ≥ VIH (min),
tCK = ∞
tCK ≥ tCK (min)
Io=0mA,
One bank active
tRC ≥ tRC (min)
CKE ≤ 0.2V
All other pins are
not under test=0V
0V ≤ VIN ≤ VCC
IOH = -2mA
IOL = 2mA
* : No guarantee against this value.
5.5 A.C. Timing Characters
Parameter
Symbol
MIN
MAX
10
7.5
2.5
2.5
1.5
0.8
1000
1000
——
——
——
——
——
——
2.7
20
45
20
15
67
——
15
6
5.4
——
——
100,000
——
——
——
7.8
——
Unit
Clock Period
/CAS Latency = 2
/CAS Latency = 3
Clock High Pulse Width
Clock Low Pulse Width
Input Setup Time
Input Hold Time
Output Valid From Clock
tCH
tCL
tSI
tHI
/CAS Latency = 2
/CAS Latency = 3
Output Hold From Clock
/RAS to /CAS Delay
/RAS Active Time
/RAS Precharge Time
Act to Act Command Period
Row Cycle Time
Average Periodic Refresh Interval
Mode Register cycle time
tCLK
tAC
tOH
tRCD
tRAS
tRP
tRRD
tRC
tREF
tMRC
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
BUFFALO INC.
(4/7)
VS133-D512
60027054-01
6. Serial Presence Detect (SPD) Data Structure
Byte
No.
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Hex
Value
Function
Function Supported
80
08
04
0D
0A
02
40
00
01
75
54
00
82
10
00
LVTTL
7.5ns (CL=3)
5.4ns (CL =3)
NonECC
7.8µs
x16bit
Non Use
01
1CLK
16
17
18
19
20
21
Defines # of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type (FPM, EDO, SDRAM..)
# of row addresses on this assembly
# Column Addresses on this assembly
# Module Banks on this assembly
Data Width of this assembly
... Data Width continuation
Voltage interface standard of this assembly
SDRAM Cycle time (highest CAS latency)
SDRAM Access from Clock (highest CAS latency)
DIMM Configuration type (non-parity, ECC)
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM width
Minimum Clock Delay
Back to Back Random Column Address
Burst Lengths Supported
# of Banks on Each SDRAM Device
CAS# Latency
CS# Latency
Write Latency
SDRAM Module Attributes
8F
04
06
01
01
00
22
SDRAM Device Attributes: General
0E
SDRAM Cycle time (2nd highest CAS latency)
SDRAM Access from Clock (2nd highest CAS latency)
SDRAM Cycle time (3rd highest CAS latency)
SDRAM Access from Clock (3rd highest CAS latency)
Minimum Row Precharge Time
Row Activate to Row Activate Min.
RAS to CAS Delay Min
Minimum RAS Pulse Width
Density of each bank on module
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Data signal input hold time
Superset Information (may be used in future)
SPD Data Revision Code
Checksum for bytes 0-62
A0
60
00
00
14
0F
14
2D
40
15
08
15
08
00
12
DB
7F
83
00
01
20
00
Burst Lengths (1,2,4,8,FULL)
4Banks
CAS Latency =2,3
CS Latency =0
WE Latency =0
UnBuffered
Supports Write1/Read Burst
Supports Precharge All
Supports Auto-Precharge
10ns (CL=2)
6ns (CL=2)
Non Support
Non Support
20ns
15ns
20ns
45ns
256MB
1.5ns
0.8ns
1.5ns
0.8ns
Undefined
Rev 1.2
Checksum
15
23
24
25
26
27
28
29
30
31
32
33
34
35
36-61
62
63
64-66
67
68-71
72
73-90
91-92
93-94
95-98
99-125
126
127
Manufacturer’s JEDEC ID code per JEP-106
Manufacturing Location
Manufacturer’s Part Number
Revision Code
Manufacturing Date
Assembly Serial Number
Manufacturer Specific Data
Intel specification frequency
——
——
——
64
Intel Specification CAS# Latency support
F7
——
128+ Unused storage locations
128Bytes
256Bytes
SDR SDRAM
13
0A
2Banks
64bits
BUFFALO
Blank
Undefined
Undefined
Undefined
Undefined
100MHz Compatible
Clock=0,1,2,3
CL =2,3
Undefined
BUFFALO INC.
(5/7)
VS133-D512
60027054-01
7. Packing/Label Specification
Item
Packing/Label Specification
Reference standard
Packing/Label Specification –for 5.25inchWidth DIMM
(PDRB-28998-X062-xx)
BUFFALO INC.
(6/7)
VS133-D512
60027054-01
8. Revision History
Rev.
Date
Changes
Issued
01
Sep.04.2008
―――
M.Goto(A07)
BUFFALO INC.
(7/7)
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