CFP-40G-LR4 (40G Base-LR4 CFP) Datasheet
Features

Transmission data rate up to 11.2Gbps per channel

CFP MSA compliant

Compliant to IEEE 802.3ba specification for 40GBASE-LR4 links

OTU3 compatible

1310nm Un-cooled CWDM DFB-DML,Transmitter and optical MUX

High Sensitivity PIN-TIA and optical DEMUX

1271, 1291, 1311, 1331nm CWDM grid in ITU-T G.694.2 up to 10km over a SMF

MDIO digital diagnostic and control capabilities.

compliant to CFP MSA Management Interface Specification, Draft 1.4

TX input and RX output CDR retiming

Hot pluggable electrical interface

Power class 1 (<8W max)

Operating case temperature 0°C to +70°C

3.3V power supply

RoHS 6 compliant (lead free)
Applications

40GE Enterprise switches and routers

Carrier Grade 40GE Core-routers

CWDM Point to Point and Ring Application

Other high speed data connections
Description
The CFP optical transceiver module are a high performance, low power consumption, long reach (10 km)
interconnect solution supporting 40G Ethernet. It is compliant with the CFP MSA and IEEE P802.3ba 40GBASELR4. Compatiblesfp.com CFP 40G LR4 modules offer 4 CWDM transmit and 4 CWDM receive asynchronous
channels operating at up to 11.2Gbps per channel.
As shown in the application block diagram, the transmitter side of the module consists of an array of VCSELs
(Vertical Cavity Surface Emitting Lasers) and associated circuitry, which converts 4 parallel electrical data inputs
to 4 parallel optical data output signals and also converts 4 parallel optical signals into 4 parallel electrical
signals through an array of PIN photodiodes and associated circuitry.
Page 1 of 12
Application Block Diagram
Absolute Maximum Ratings
Parameter
Symbol
Min
Max
Unit
Supply Voltage
Vcc
-0.3
3.6
V
Input Voltage
Vin
-0.3
Vcc+0.3
V
Storage Temperature
Tst
-40
85
ºC
Case Operating Temperature
Top
0
70
ºC
Humidity(non-condensing)
Rh
95
%
Recommended Operating Conditions
Parameter
Symbol
Min
Typical
Max
Unit
Supply Voltage
Vcc
3.13
3.3
3.47
V
Operating Case temperature
Tca
0
70
ºC
Data Rate Per Lane
fd
-
11.2
Gbps
Humidity
Rh
85
%
Power Dissipation
Pm
8
W
Page 2 of 12
Electrical Characteristics
Parameter
Symbol
Min
Typical
Max
Unit
Differential input impedance
Zin
90
100
110
ohm
Differential Output impedance
Zout
90
100
110
ohm
Differential input voltage amplitude
ΔVin
120
820
mVp-p
Differential output voltage amplitude
ΔVout
300
820
mVp-p
Input Logic Level High
VIH
2.0
VCC
V
Input Logic Level Low
VIL
0
0.8
V
Output Logic Level High
VOH
VCC-0.5
VCC
V
Output Logic Level Low
VOL
0
0.4
V
Note:
1.
Differential input voltage amplitude is measured between TxnP and TxnN.
2.
Differential output voltage amplitude is measured between RxnP and RxnN.
XLAUI Input Interface
XLAUI Receiver Parameters
Symbol
Min
Signal Rate Per Lane
Typical
Max
10.3125
Signal Rate tolerance
-100
Units
Note
Gb/s
100
ppm
20
mV
AC Common Mode Voltage Tolerance, RMS
CMVLTac
Minimum Differential Input Return Loss
Rldiff
Total Input Jitter Tolerance
Tjin
0.62
UI
Deterministic Input Jitter Tolerance
Tdin
0.42
UI
IEEE802.3ba Equation 83B-5
dB
Transmitter Input Eye Mask (X1, X2)
(0.31, 0.5)
UI
1
Transmitter Input Eye Mask (Y1, Y2)
(42.5, 425)
mV
1
XLAUI Output Interface
XLAUI Driver Parameters
Signal Rate Per Lane
Signal Rate tolerance
Single-end Output Voltage
Output AC Common Mode Voltage, RMS
Output Rise and Fall Time (20%-80%)
Minimum Differential Output Return Loss
Total Output Jitter
Deterministic Output Jitter
Receiver Output Eye Mask (X1, X2)
Receiver Output Eye Mask (Y1, Y2)
Symbol
Min
Typical
Max
10.3125
Vosingle
Vocomac
Trftl
Rldiff
Tjo
Tdo
-100
-0.4
100
4
15
24
IEEE802.3ba Equation 83B-6
0.4
0.25
(0.2, 0.5)
(136, 380)
Units
Note
Gb/s
ppm
V
mV
ps
dB
UI
UI
UI
mV
2
2
Page 3 of 12
3.3V CMOS DC Parameters
(MOD_RSTn, MOD_LOPWR, TX_DIS, PRG_CNTL, MOD_ABS, RX_LOS, GLB_ALRMn, PRG_ALRM)
Parameter
symbol
Min
Output High Voltage (IOH=-100uA)
Output Low Voltage (IOL=100uA)
Intput High Voltage
Input Low Voltage
Input Leakage Current
Minimun Pulse Width of Control Pin Signal
Voh
Vol
Vih
Vil
IIN
t_CNTL
Vcc-0.2
-0.3
2
-0.3
-10
100
Typical
Max
Units
Vcc+0.3
0.2
Vcc+0.3
0.8
10
V
V
V
V
μA
μS
Note
1.2V CMOS DC Parameters (MDIO, MDC, PRTADR4:0)
Parameter
Symbol
Intput High Voltage
Input Low Voltage
Input Leakage Current
Output High Voltage
Output Low Voltage
Output high current (Vi =1.0V)
Output low current (Vi = 0.2V)
Input Capacitance
Vih
Vil
IIN
Voh
Vol
Iioh
Iol
Ci
Min
Typical
0.84
-0.3
-100
1.0
-0.3
Max
1.5
0.36
100
1.5
0.2
-4
4
10
Units
Note
V
V
μA
V
V
mA
mA
pF
MDIO and MDC AC parameters
Parameter
Symbol
MDC clock Frequency
MDC clock period
MDIO data hold time
MDIO data setup time
fMDC
tprd
Thold
Tsetup
MDC high and low time
twidth
Delay from MDC rising edge to MDIO data
change
MDIO/MDC termination in CFP
Min
0.1
250
10
10
40
160
Tdelay
Zt
Typical
Max
4
10000
60
175
100
Units
Note
MHz
ns
ns
ns
%
ns
ns
kOhm
Page 4 of 12
Optical Characteristics
Transmitter Optical Specifications (T = 25°C, VCC =3.3V +/- 5%)
Parameter
Symbol
Min
Average Optical Power(per channel)
Pout
-7
Average Optical Power(per channel) - Disabled
Poff
Typical
Optical Return Loss Tolerance
Max
Unit
2.3
dBm
-30
dBm
-12
dB
Extinction Ratio
ER
3
Lane0 Wavelength
λc
1264.5
1271
1277.5
nm
Lane1 Wavelength
λc
1284.5
1291
1297.5
nm
Lane2 Wavelength
λc
1304.5
1311
1317.5
nm
Lane3 Wavelength
λc
1324.5
1331
1337.5
nm
Side-mode suppression ratio (SMSR)
SMSR
Total average launch power
Transmitter eye mask definition {X1, X2, X3,
Y2, Y3}
dB
30
dB
Ptotal
Y1,
8.3
dBm
Max
Unit
-11.5
dBm
2.3
dBm
{0.25, 0.4, 0.45, 0.25, 0.28, 0.4}
Note:
1. Average optical power is measured at the output of the modules optical interface.
Receiver Optical Specifications (T = 25°C, VCC =3.3V +/- 5%)
Parameter
Symbol
Min
Typical
Optical Power Sensitivity(per channel,OMA)
Average receive power, each lane
Pin max
Average receive power, each lane
Pin min
-13.7
dBm
Stressed Receiver Sensitivity(OMA)
PS
-9.6
dBm
Receiver reflectance
λc
-26
dB
Difference in receive power between any two lanes
(OMA)
Rl
7.5
dB
Note:
1. Optical power sensitivity is measured with BER@10-12 at 10.3125Gbps per channel.
Page 5 of 12
CFP 40G LR4 module functional block diagram
Pin Descriptions
Part A: Bottom Row Pin Function Definition
Pin
Symbol
Type
1
3.3V_GND
GND
2
3.3V_GND
GND
3
3.3V_GND
GND
4
3.3V_GND
GND
5
3.3V_GND
GND
6
3.3V
VCC
7
3.3V
VCC
8
3.3V
VCC
9
3.3V
VCC
10
3.3V
VCC
11
3.3V
VCC
12
3.3V
VCC
I/O
Description
3.3V Module Supply Voltage Return Ground, can be separate or
tied together with Signal Ground
3.3V Module Supply
Page 6 of 12
13
3.3V
VCC
14
3.3V
VCC
15
3.3V
VCC
16
3.3V_GND
GND
17
3.3V_GND
GND
18
3.3V_GND
GND
19
3.3V_GND
GND
20
3.3V_GND
GND
21
NC
I/O
internal, do not connect
22
NC
I/O
internal, do not connect
23
GND
GND
24
(TX_MCLKn)
CML
O
CML For optical waveform testing. Not used.
25
(TX_MCLKp)
CML
O
CML For optical waveform testing. Not used.
26
GND
GND
27
NC
I/O
internal, do not connect
28
NC
I/O
internal, do not connect
29
NC
I/O
30
PRG_CNTL1
LVCMOS
w/PU
31
PRG_CNTL2
LVCMOS
w/PU
32
PRG_CNTL3
LVCMOS
w/PU
33
PRG_ALRM1
LVCMOS
O
34
PRG_ALRM2
LVCMOS
O
35
PRG_ALRM3
LVCMOS
O
36
TX_DIS
37
MOD_LOPWR
38
MOD_ABS
GND
O
39
MOD_RSTn
LVCMOS
w/PD
I
40
RX_LOS
LVCMOS
O
internal, do not connect
Programmable Control 1 set via MDIO, MSA default:
TRXIC_RSTn – TX & RX IC reset. “0” = reset, “1” or NC =
enabled or not used
Programmable Control 2 set via MDIO, MSA default: Hardware
power Interlock LSB, “00” = <8W, “01” = <16W, “10” < 24W, “11”
or NC = >24W or not used
Programmable Control 3 set via MDIO, MSA default: Hardware
power Interlock MSB, “00” = <8W, “01” = <16W, “10” < 24W, “11”
or NC = >24W or not used
Programmable Alarm 1 set via MDIO, Reflex default: HIPWR_ON,
Module power on indicator. “1” = Module high power up
completed, “0” = Module not high powered up
Programmable Alarm 2 set via MDIO, Reflex default:
MOD_READY, module initialization complete, “1” = complete, “0”
= not complete
Programmable Alarm 3 set via MDIO, Reflex default:
MOD_FAULT, module fault detected, “1” = fault, “0” = no fault
Transmitter Disable for all channels, “1” or NC = transmitter
disabled, “0” = transmitter enabled
Module low power mode. “1” or NC = module in low power (safe)
mode, “0” = power-on enabled
Module Absent. “1” or NC = Module absent, “0” = module present.
Pull-up resistor on Host
Module Reset. “0” = reset the module, “1” or NC = module
enabled, Pull Down resistor in module
Receiver loss of optical signal on any channel, “1” = loss of signal,
“0” = normal condition
LVCMOS
w/PU
LVCMOS
w/PU
I
I
I
I
I
Page 7 of 12
LVCMOS
O
PRTADR4
1.2V CMOS
I
Global Alarm. “0” = alarm condition in any MDIO alarm register,
“1” = no alarm
MDIO port address bit 4
43
PRTADR3
1.2V CMOS
I
MDIO port address bit 3
44
PRTADR2
1.2V CMOS
I
MDIO port address bit 2
45
PRTADR1
1.2V CMOS
I
MDIO port address bit 1
46
PRTADR0
1.2V CMOS
I
MDIO port address bit 0
47
MDIO
1.2V CMOS
I/O
48
MDC
1.2V CMOS
I
49
GND
GND
50
NC
I/O
internal, do not connect
51
NC
I/O
internal, do not connect
52
GND
53
NC
I/O
internal, do not connect
54
NC
I/O
55
3.3V_GND
GND
internal, do not connect
3.3V Module Supply Voltage Return Ground, can be separate or
tied together with Signal Ground
56
3.3V_GND
GND
57
3.3V_GND
GND
58
3.3V_GND
GND
59
3.3V_GND
GND
60
3.3V
VCC
61
3.3V
VCC
62
3.3V
VCC
63
3.3V
VCC
64
3.3V
VCC
65
3.3V
VCC
66
3.3V
VCC
67
3.3V
VCC
68
3.3V
VCC
69
3.3V
VCC
70
3.3V_GND
GND
71
3.3V_GND
GND
72
3.3V_GND
GND
73
3.3V_GND
GND
74
3.3V_GND
GND
41
GLB_ALRMn
42
Management Data I/O bi-directional data (electrical specs as per
802.3ae)
Management data clock (electrical specs as per 802.3ae)
GND
3.3V Module Supply
Page 8 of 12
Part B: Top Row Pin Function Definition
Pin
Symbol
Pin
Symbol
148
147
GND
Not used
111
110
GND
Not used
146
145
144
Not used
GND
Not used
109
108
107
Not used
GND
RX9n
143
142
141
Not used
GND
TX9n
106
105
104
RX9p
GND
RX8n
140
139
138
TX9p
GND
TX8n
103
102
101
RX8p
GND
RX7n
137
136
135
TX8p
GND
TX7n
100
99
98
RX7p
GND
RX6n
134
TX7p
97
RX6p
133
GND
96
GND
132
TX6n
95
RX5n
131
130
129
TX6p
GND
TX5n
94
93
92
RX5p
GND
RX4n
128
TX5p
91
RX4p
127
GND
90
GND
126
TX4n
89
RX3n
125
124
123
TX4p
GND
TX3n
88
87
86
RX3p
GND
RX2n
122
TX3p
85
RX2p
121
GND
84
GND
120
TX2n
83
RX1n
119
TX2p
82
RX1p
118
GND
81
GND
117
TX1n
80
RX0n
116
TX1p
79
RX0p
115
GND
78
GND
114
TX0n
77
Not used
113
TX0p
76
Not used
112
GND
75
GND
Page 9 of 12
Pad Layout of the CFP module
Lane Assignment
Fibre
Symbol
1
Unused
2
RX0
3
Corresponding
Electrical pins
Fibre
Symbol
Corresponding
Electrical pins
13
Unused
79,80
14
TX0
113,114
RX1
82,83
15
TX1
116,117
4
RX2
85,86
16
TX2
119,120
5
RX3
88,89
17
TX3
122,123
6
RX4
91,92
18
TX4
125,126
7
RX5
94,95
19
TX5
128,129
8
RX6
97,98
20
TX6
131,132
9
RX7
100,101
21
TX7
134,135
10
RX8
103,104
22
TX8
137,138
11
RX9
106,107
23
TX9
140,141
12
Unused
24
Unused
Page 10 of 12
Mechanical Dimensions
Page 11 of 12
References
1. 40G Ethernet
2. 40G OTU3
Important Notice
Performance figures, data and any illustrative material provided in this datasheet are typical and must be
specifically confirmed in writing by Compatible SFP before they become applicable to any particular order or
contract. In accordance with the Compatible SFP policy of continuous improvement specifications may change
without notice. The publication of information in this datasheet does not imply freedom from patent or other
protective rights of Compatible SFP or others. Further details are available by emailing info@compatiblesfp.com
Page 12 of 12
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