DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
Identification
DTM63332 256Mx72
Performance range
Clock / Module Speed / CL-tRCD -tRP
333 MHz / DDR2-667 / 5-5-5
267 MHz / DDR2-533 / 4-4-4
Features
Description
240-pin JEDEC-compliant DIMM
DTM63332 is a Registered 256Mx72 memory
module which conforms to JEDEC's DDR2,
PC2-5300 standard. The assembly is comprised
of two Ranks of eighteen DDR2 DRAMs, four
Registers with command/address parity, one
Phase-Locked Loop (PLL), and one 2K-bit
EEPROM used for Serial Presence Detect.
Both output driver strength and input termination
impedance are programmable to maintain signal
integrity on the I/O signals. Error Checking and
Correction bits are provided to ensure data
integrity. The module will support advanced ECC
features; Chipkill and Intel SDDC.
The eighteen Data Strobe signals may be used
either as nine differential pairs, or as eighteen
single-ended strobes for use in systems with a
mix of x4 and x8 DRAMs.
Operating Voltage: 1.8 V ±0.1
I/O Type: SSTL_18
Data Transfer Rate: 667 MHz
Data Bursts: 4 or 8 bits, Sequential or Interleaved ordering
Error Checking and Correction (ECC) bits
Programmable I/O driver strength (OCD)
Programmable On-Die Termination (ODT)
Differential/Single-Ended Data Strobe signals
Dual Rank
SDRAM Addressing (Row/Col/Bank): 14/11/2
Fully RoHS Compliant
Pin Configuration
Front Side
Pin Description
Back Side
1 VREF
31 DQ19
61 A4
91
GND
2 GND
32 GND
62 VDD
92
3 DQ0
4 DQ1
5 GND
33 DQ24
34 DQ25
35 GND
63 A2
64 VDD
65 GND
93
94
95
121 GND
Name
181 VDD
211 DQS14
/CAS
Column Address Strobe
/DQS5 122 DQ4
152 DQ28
182 A3
212 /DQS14
/Err_Out
Parity Error Found
DQS5
GND
DQ42
123 DQ5
124 GND
125 DQS9
153 DQ29
183 A1
154 GND
184 VDD
155 DQS12 185 CK0
213 GND
214 DQ46
215 DQ47
/RAS
/RESET
/S[1:0]
Row Address Strobe
Register and PLL Reset
Chip Selects
/WE
A[15:0]
BA[2:0]
Write Enable
Address Inputs
Bank Addresses
CB[7:0]
CK0, /CK0
CKE[1:0]
Data Check Bits
Differential Clock Inputs
Clock Enables
DQ[63:0]
DQS[17:0], /DQS[17:0]
GND
NC
ODT[1:0]
Data Bits
Differential Data Strobes
Ground
No Connection
On Die Termination Inputs
Par_In
SA[2:0]
SCL
Parity Bit, Address & Control
SPD Address
SPD Clock Input
SDA
VDD
VDDSPD
VREF
SPD Data Input/Output
Power
SPD EEPROM Power
Reference Voltage
6 /DQS0
36 /DQS3
66 GND
96
DQ43
126 /DQS9
156 /DQS12 186 /CK0
216 GND
7 DQS0
8 GND
37 DQS3
38 GND
67 VDD
97
68 Par_In 98
GND
DQ48
127 GND
128 DQ6
157 GND
158 DQ30
187 VDD
188 A0
217 DQ52
218 DQ53
DQ49
9 DQ2
39 DQ26
69 VDD
99
129 DQ7
159 DQ31
189 VDD
219 GND
10 DQ3
11 GND
40 DQ27
41 GND
70 A10
71 BA0
100 GND
101 SA2
130 GND
131 DQ12
160 GND
161 CB4
190 BA1
191 VDD
220 NC
221 NC
12 DQ8
42 CB0
72 VDD
102 NC
132 DQ13
162 CB5
192 /RAS
222 GND
13
14
15
16
43
44
45
46
73
74
75
76
103
104
105
106
133
134
135
136
163
164
165
166
193
194
195
196
223
224
225
226
DQ9
GND
/DQS1
DQS1
17 GND
CB1
GND
/DQS8
DQS8
47 GND
18 /RESET 48 CB2
19 NC
49 CB3
/WE
/CAS
VDD
/S1
GND
/DQS6
DQS6
GND
GND
DQS10
/DQS10
GND
GND
DQS17
/DQS17
GND
/S0
VDD
ODT0
A13
DQS15
/DQS15
GND
DQ54
77 ODT1 107 DQ50
137 NC
167 CB6
197 VDD
227 DQ55
78 VDD
79 GND
138 NC
139 GND
168 CB7
169 GND
198 GND
199 DQ36
228 GND
229 DQ60
108 DQ51
109 GND
20 GND
50 GND
80 DQ32
110 DQ56
140 DQ14
170 VDD
200 DQ37
230 DQ61
21
22
23
24
25
26
51
52
53
54
55
56
81
82
83
84
85
86
111
112
113
114
115
116
141
142
143
144
145
146
171
172
173
174
175
176
201
202
203
204
205
206
231
232
233
234
235
236
DQ10
DQ11
GND
DQ16
DQ17
GND
VDD
CKE0
VDD
BA2
/Err_Out
VDD
DQ33
GND
/DQS4
DQS4
GND
DQ34
Function
151 GND
DQ57
GND
/DQS7
DQS7
GND
DQ58
DQ15
GND
DQ20
DQ21
GND
DQS11
CKE1
VDD
A15
A14
VDD
A12
GND
DQS13
/DQS13
GND
DQ38
DQ39
GND
DQS16
/DQS16
GND
DQ62
DQ63
27 /DQS2
28 DQS2
29 GND
57 A11
58 A7
59 VDD
87 DQ35
88 GND
89 DQ40
117 DQ59
118 GND
119 SDA
147 /DQS11 177 A9
148 GND
178 VDD
149 DQ22
179 A8
207 GND
208 DQ44
209 DQ45
237 GND
238 VDDSPD
239 SA0
30 DQ18
60 A5
90 DQ41
120 SCL
150 DQ23
210 GND
240 SA1
180 A6
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 1
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
Front view
133.35
[5.250]
30.00
[1.181]
10.00
[0.394]
4.00
[0.157]
17.78
[0.700]
5.00
[0.197]
5.18
[0.204]
63.00
[2.480
55.00
[2.165]
2.54 Min
[0.100 Min]
123.00
[4.843]
Back view
Side view
3.94Max
[0.155]Max
4.06 Min
[0.160] Min
1.27 ±.10
[0.0500 ±0.0040]
Notes
Tolerances on all dimensions except where otherwise
indicated are ±.13 (.005).
All dimensions are expressed: millimeters [inches]
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 2
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
VSS
/RS0
/RS1
DQS0
/DQS0
DQS9
/DQS9
/DQS
DQR[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
CS
/CS DM
DQS1
/DQS1
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
CS
/CS DM
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
CS
DQS
CS
/DQS
/CS DM
I/O[3:0]
DQS
CS
/CS DM
/DQS
DQS
CS
/CS DM
/DQS
I/O[3:0]
/DQS
DQR[31:28]
I/O[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
CS
/CS DM
DQS
CS
/CS DM
DQS
CS
/CS DM
DQS
CS
/CS DM
DQS
CS
/CS DM
DQS
/CS DM
DQS
/CS DM
DQS
CS
/CS DM
DQS
CS
/CS DM
I/O[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
/DQS
DQR[39:36]
I/O[3:0]
DQS5
/DQS5
I/O[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
I/O[3:0]
DQS14
/DQS14
/DQS
DQS
CS
/DQS
/CS DM
I/O[3:0]
DQS
/CS DM
/DQS
DQR[47:44]
I/O[3:0]
DQS6
/DQS6
DQS
/CS DM
/DQS
I/O[3:0]
I/O[3:0]
DQS15
/DQS15
/DQS
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
/CS DM
/DQS
DQR[55:52]
I/O[3:0]
DQS7
/DQS7
DQS
/CS DM
/DQS
I/O[3:0]
I/O[3:0]
DQS16
/DQS16
/DQS
DQS
CS
/DQS
/CS DM
I/O[3:0]
DQS
CS
/CS DM
/DQS
DQR[63:60]
I/O[3:0]
DQS8
/DQS8
DQS
CS
/CS DM
/DQS
I/O[3:0]
I/O[3:0]
DQS17
/DQS17
/DQS
CBR[3:0]
/CS DM
DQS13
/DQS13
/DQS
DQR[59:56]
/CS DM
I/O[3:0]
/DQS
DQR[23:20]
I/O[3:0]
DQS4
/DQS4
DQR[51:48]
DQS
CS
DQS12
/DQS12
/DQS
DQR[43:40]
DQS
CS
I/O[3:0]
/CS DM
DQS3
/DQS3
DQR[35:32]
/DQS
DQS11
/DQS11
/DQS
DQR[27:24]
/CS DM
I/O[3:0]
/DQS
DQR[15:12]
I/O[3:0]
DQS2
/DQS2
DQR[19:16]
DQS
CS
I/O[3:0]
DQS10
/DQS10
/DQS
DQR[11:8]
/DQS
DQR[7:4]
I/O[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
DQS
CS
/CS DM
/DQS
CBR[7:4]
I/O[3:0]
DQS
CS
/CS DM
/DQS
I/O[3:0]
I/O[3:0]
REGISTERS
/S0
/S1
BA0-BA2
/RS0
18 SDRAMs
18 SDRAMs
/RS1
RBA0-RBA1 All SDRAMs
A0-A15
RA0-RA13
All SDRAMs
/RAS
/RRAS
All SDRAMs
/CAS
CKE0
CKE1
/RCAS
RCKE0
All SDRAMs
18 SDRAMs
DQS[17:00]
DQSR[17:00]
RCKE1
18 SDRAMs
/DQS[17:00]
/DQSR[17:00]
/WE
ODT0
ODT1
/RWE
RODT0
All SDRAMs
RODT1
18 SDRAMs
/RESET
DECOUPLING
Notes:
1. Unless otherwise noted, resistor values are 22 Ohms ±5%
DQ[63:00]
CB[7:0]
V DDSPD
VDD
V REF
V SS
DQR[63:00]
CBR[7:0]
SCL
18 SDRAMs
Serial PD
All SDRAMs
All SDRAMs
All SDRAMs
SERIAL PD
WP
SDA
/RST
SA0
SA1 SA2
PCK7
/PCK7
CK0
Signals for Address and Command Parity Function
VSS
VDD
PAR_In
C0
Register A
C1
PAR_IN
PPO
/QERR
VDD
VDD
/CK0
C0
Register B
C1
PAR_IN
PPO
/QERR
/Err_Out
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
/RESET
P
L
L
OE
PCK0-PCK6,PCK8,PCK9 to SDRAMS
/PCK0-/PCK6,/PCK8,/PCK9 to SDRAMS
PCK7
/PCK7
to Registers
to Registers
Page 3
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
Absolute Maximum Ratings
(Note: Operation at or above Absolute Maximum Ratings can adversely affect module reliability.)
PARAMETER
Symbol
Minimum
Maximum
Unit
Temperature, non-Operating
TSTORAGE
-55
100
C
TCASE
0
95*
C
VDD
-0.1
2.3
V
VIN,VOUT
-0.5
2.3
V
DRAM Case Temperature, Operating
Voltage on VDD relative to VSS
Voltage on Any Pin relative to VSS
*With refresh rate increased to 3.9us. Maximum temperature is 85C, with refresh rate at 7.8us.
Recommended DC Operating Conditions (Voltages referenced to Vss = 0 V)
PARAMETER
Power Supply Voltage
Symbol
VDD
Minimum
1.7
Typical
1.8
Maximum
1.9
Unit
V
Note
I/O Reference Voltage
VREF
0.49 VDD
0.50 VDD
0.51 VDD
V
1
Bus Termination Voltage
VTT
VREF - 0.04
VREF
VREF + 0.04
V
Notes:
1. The value of VREF is expected to equal one-half VDD and to track variations in the VDD DC level. Peak-to-peak noise on VREF may
not exceed ±1% of its DC value.
DC Input Logic Levels, Single-Ended (Voltages referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(DC)
Minimum
VREF + 0.125
Maximum
VDD + 0.300
Unit
V
Logical Low (Logic 0)
VIL(DC)
-0.300
VREF - 0.125
V
AC Input Logic Levels, Single-Ended (Voltages referenced to Vss = 0 V)
PARAMETER
Logical High (Logic 1)
Symbol
VIH(AC)
Minimum
VREF + 0.200
Maximum
-
Unit
V
Logical Low (Logic 0)
VIL(AC)
-
VREF - 0.200
V
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 4
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
Differential Input Logic Levels (Voltages referenced to Vss = 0 V)
PARAMETER
DC Input Signal Voltage
Symbol
VIN(DC)
Minimum
-0.300
Maximum
VDD + 0.300
Unit
V
Note
1
DC Differential Input Voltage
VID(DC)
-0.250
VDD + 0.600
V
2
AC Differential Input Voltage
VID(AC)
-0.500
VDD + 0.600
V
3
AC Differential Cross-Point Voltage
VIX(AC)
0.50 VDD - 0.175
0.50 VDD + 0.175
V
4
Notes:
1. VIN(DC) specifies the allowable DC excursion of each input of a differential pair.
2. VID(DC) specifies the input differential voltage, i.e. the absolute value of the difference between the two voltages of a differential
pair.
3. VID(AC) specifies the input differential voltage required for switching.
4. The typical value of VIX(AC) is expected to be 0.5 VDD and is expected to track variations in VDD.
Capacitance (0 C < TCASE < 55 C, f = 100 MHz, VOUT(DC) = VDD/2, VOUT(ac) = 0.1V(p-p))
PARAMETER
Symbol
Minimum
Maximum
Unit
Input Capacitance, Clock
CK0, /CK0
Pin
CIN1
2
3
pF
Input Capacitance, Address
and Control
BA[2:0], A[15:0], /S[1:0], /RAS, /CAS,
/WE, CKE[1:0], ODT[1:0]
CIN2
5
7
pF
Input/Output Capacitance
DQ[63:0], CB[7:0], DQS[17:0],
/DQS[17:0]
CIO
5
7
pF
DC Characteristics (Voltages referenced to Vss = 0 V)
PARAMETER
Symbol
Minimum
Maximum
Unit
Note
Input Leakage Current
ILI
-5
5
µA
1
Output Leakage Current
IOZ
-5
5
µA
2
Output Minimum Source DC Current
IOH
-13.4
-
mA
3
Output Minimum Sink DC Current
IOL
+13.4
-
mA
4
Notes:
1.
2.
3.
4.
These values are guaranteed by design and are tested on a sample basis only
DQx and ODT are disabled, and 0 V ≤ VOUT ≤ VDD.
VDD = 1.7 V, VOUT = 1420 mV. (VOUT - VDD)/IOH must be less than 21 Ohms for values of VOUT between VDD and (VDD - 280
mV).
VDD = 1.7 V, VOUT = 280 mV. VOUT/IOL must be less than 21 Ohms for values of VOUT between 0 V and 280 mV.
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 5
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
IDD Specifications and Conditions (Voltages referenced to Vss = 0 V)
PARAMETER
Operating One
Bank ActivePrecharge
Current
Operating One
Bank ActiveRead-Precharge
Current
Precharge
Power-Down
Current
Symbol
Test Condition
Max
Value
Unit
Note
IDD0
CKE is HIGH, /CS is HIGH between valid commands;
Address bus inputs are switching; Data bus inputs are
switching.
2870
mA
1
IDD1
IOUT = 0 mA; BL = 4, CL = 5 ns, AL = 0; CKE is HIGH, /CS is
HIGH between valid commands; Address bus inputs are
switching.
3330
mA
1
IDD2P
All banks idle; CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating.
710
mA
2
1890
mA
2
1790
mA
2
3250
mA
2
4500
mA
1
4680
mA
1
6480
mA
2
570
mA
2
6290
mA
1
Precharge
Standby Current
IDD2N
Active PowerDown Current
IDD3P
Active Standby
Current
IDD3N
Operating Burst
Write Current
IDD4W
Operating Burst
Read Current
IDD4R
Burst Refresh
Current
IDD5
Self Refresh
Current
IDD6
Operating Bank
Interleave Read
Current
IDD7
All banks idle; CKE is HIGH, /CS is HIGH; Other control and
address bus inputs are switching; Data bus inputs are
switching.
All banks open; CKE is LOW; Other control and address bus
inputs are stable; Data bus inputs are floating. Fast Powerdown exit (Mode Register bit 12 = 0)
All banks open; tRAS = 70 ms; CKE is HIGH, /CS is HIGH
between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching.
All banks open, Continuous burst writes; BL = 4, CL = 3 tCK,
AL = 0; tRAS = 70 ms, CKE is HIGH, /CS is HIGH between
valid commands; Address bus inputs are switching; Data
bus inputs are switching.
All banks open, Continuous burst reads, IOUT = 0 mA; BL = 4,
CL = 4 tCK, AL = 0; xx, tRAS = 70 ms; CKE is HIGH, /CS is
HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching.
Refresh command at every 75 ns; CKE is HIGH, /CS is
HIGH between valid commands; Other control and address
bus inputs are switching; Data bus inputs are switching.
CK and /CK at 0 V; CKE ≤ 0.2 V; Other control and address
bus inputs are floating; Data bus inputs are floating.
All bank interleaving reads, IOUT= 0 mA; BL = 4, CL = 4 tCK;
AL = 70 ns; tRRD = 7.5 ns; CKE is HIGH, /CS is HIGH
between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching.
Notes: 1) IDD values calculated as one module rank in operating condition. Second rank is IDD2P.
2) IDD values calculated reflects both ranks in operating condition.
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 6
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
AC Operating Conditions
PARAMETER
Symbol
Min
Max
Unit
DQ Output Access Time from Clock
tAC
0.45
-
ns
CAS-to-CAS Command Delay
tCCD
2
-
tCK
Clock High Level Width
tCH
0.45
0.55
tCK
Clock Cycle Time
tCK
3000
8000
ps
Clock Low Level Width
tCL
0.45
0.55
tCK
tDH
0.175
-
ns
tDIPW
0.35
-
tCK
DQS Output Access Time from Clock
tDQSCK
-400
+400
ps
Write DQS High Level Width
tDQSH
0.35
-
tCK
Write DQS Low Level Width
tDQSL
0.35
-
tCK
DQS-Out Edge to Data-Out Edge Skew
tDQSQ
240
-
ps
Data Input Setup Time Before DQS Strobe
tDS
0.10
-
ns
DQS Falling Edge from Clock, Hold Time
tDSH
0.2
-
tCK
DQS Falling Edge to Clock, Setup Time
tDSS
0.2
-
tCK
Clock Half Period
tHP
minimum of tCH or tCL
-
ns
Address and Command Hold Time after Clock
tIH
0.275
-
ns
Address and Command Setup Time before Clock
tIS
0.200
-
ns
Load Mode Command Cycle Time
tMRD
2
-
tCK
DQ-to-DQS Hold
tQH
tHP - tQHS
-
-
Data Hold Skew Factor
tQHS
340
-
ps
Active-to-Precharge Time
tRAS
45
120K
ns
Active-to-Active / Auto Refresh Time
tRC
60
-
ns
RAS-to-CAS Delay
tRCD
15
-
ns
Average Periodic Refresh Interval
tREFI
-
7.8
µs
Auto Refresh Row Cycle Time
tRFC
105
-
ns
Row Precharge Time
tRP
15
-
ns
Read DQS Preamble Time
tRPRE
0.9
1.1
tCK
Read DQS Postamble Time
tRPST
0.4
0.6
tCK
Row Active to Row Active Delay
tRRD
7.5
-
ns
Data Input Hold Time after DQS Strobe
DQ Input Pulse Width
tRTP
7.5
-
ns
Write DQS Preamble Setup Time
tWPRES
.35
-
tCK
Write DQS Postamble Time
tWPST
0.4
0.6
tCK
tWR
15
-
ns
Internal Read to Precharge Command Delay
Write Recovery Time
Internal Write to Read Command Delay
tWTR
7.5
-
ns
Exit Self Refresh to Non-Read Command
tXSNR
tRFC(min) + 10
-
ns
Exit Self Refresh to Read Command
tXSRD
200
-
tCK
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 7
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
Serial Presence Detect Contents
Byte#
0
1
2
3
4
5
6
7
8
9
10
11
Function
Number of Serial PD Bytes written during module production
Total number of Bytes in Serial Presence Detect device
Fundamental Memory Type
Number of Row Addresses
Number of Column Addresses
Module Attributes - Number of Ranks, Package and Height
bits 0 through 2 - number of Ranks
bit 3 - Card on Card
bit 4 - DRAM Package
bits 5 through 7 - Module Height
Module Data Width
Reserved
Voltage Interface Level of this assembly
SDRAM Cycle time at highest CAS Latency
SDRAM Access from Clock time at highest CAS Latency (tAC)
DIMM configuration type
12
Refresh Rate/Type
13
14
15
16
Primary SDRAM Width
Error Checking SDRAM Width
Reserved
SDRAM Device Attributes - Burst Lengths Supported
bits 0 and 1 - [undefined]
bit 2 - Burst Length = 4
bit 3 - Burst Length = 8
bits 4 through 7 - [undefined]
SDRAM Device Attributes - Number of Banks on SDRAM Device
SDRAM Device Attributes - CAS Latency
bits 0 and 1 - [undefined]
bit 2 - Latency = 2
bit 3 - Latency = 3
bit 4 - Latency = 4
bit 5 - Latency = 5
bits 6 and 7 - [undefined]
DIMM Mechanical Characteristics. Max. module thickness. (mm)
DIMM type information
bit 0 - Regular RDIMM (133.35mm)
bit 1 - Regular UDIMM (133.35mm)
bit 2 - SODIMM (67.6mm)
bit 3 - Micro-DIMM (45.5mm)
bit 4 - Mini RDIMM (82.0mm)
bit 5 - Mini UDIMM (82.0mm)
bits 6 and 7 - [undefined]
SDRAM Module Attributes (Refer to Byte20 for DIMM type information).
Number of active registers on the DIMM (N/A for UDIMM) Number of PLL on the DIMM (N/A for UDIMM) FET Switch External Enable bit 5 - TBD
bit 6 - Analysis probe installed
bit 7 - [undefined]
SDRAM Device Attributes - General
bit 0 - Supports Weak Driver
bit 1 - Supports 50 ohm ODT Minimum Clock Cycle Time at Reduced CAS Latency, CL = X-1
17
18
19
20
21
22
23
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Value
128 bytes
256 bytes
DDR2
14
11
2
No
Planar
30mm
72
UNUSED
SSTL/1.8V
3 ns
0.45 ns
ECC
7.8 µs
Self Refresh
4
4
UNUSED
Hex
80
08
08
0E
0B
61
48
00
05
30
45
06
82
04
04
00
0C
yes
yes
4
04
30
yes
yes
x </= 4.10
01
01
yes
no
no
no
no
no
no
07
4
no
no
03
yes
yes
3.75 ns
3D
Page 8
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
24
Maximum Data Access Time (tAC) from Clock at CL = X-1
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Minimum Clock Cycle Time at Reduced CAS Latency CL = X-2
Maximum Data Access Time (tAC) from Clock at CL = X-2
Minimum Row Precharge Time (tRP)
Minimum Row Active to Row Active Delay (tRRD)
Minimum RAS to CAS Delay (tRCD)
Minimum Active to Precharge Time (tRAS)
Module Rank Density
Address and Command Setup Time before Clock (tIS)
Address and Command Hold Time after Clock (tIH)
Data Input Setup Time before Strobe (tDS)
Data Input Hold Time after Strobe (tDH)
Write Recovery Time (tWR)
Internal Write-to-Read Command Delay (tWTR)
Internal Read-to-Precharge Command Delay (tRTP)
Memory Analysis Probe Characteristics.
Extension of Byte 41(tRC) and Byte 42 (tRFC)
Add this value to byte 41
Add this value to byte 42
Minimum Active-to-Active / Auto Refresh Time (tRC)
Minimum Auto-Refresh to Active/Auto-Refresh Command Period (tRFC)
Maximum Cycle Time (tCK max)
DQS-DQ Skew for DQS & associated DQ Signals (tDQSQ)
Read Data Hold Skew Factor (tQHS)
PLL Relock Time
Reserved
SPD Revision
Checksum for Bytes 0-62
Module Manufacturer’s JEDEC ID Code
Module Manufacturer’s JEDEC ID Code
Module Manufacturer’s JEDEC ID Code
Module Manufacturing Location
Module Part Number
Module Revision Code
Module Manufacturing Date
Module Serial Number
Manufacturer’s Specific Data
41
42
43
44
45
46
47-61
62
63
64
65
66-71
72
73-90
91-92
93-94
95-98
99-127
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
0.45 ns
45
0
0
15 ns
7.5 ns
15 ns
45 ns
1 GB
0.2 ns
0.28 ns
0.1 ns
0.18 ns
15 ns
7.5 ns
7.5 ns
UNUSED
00
00
3C
1E
3C
2D
01
20
28
10
18
3C
1E
1E
00
00
0 ns
0 ns
60 ns
105 ns
8 ns
0.24 ns
0.34 ns
6 µs
UNUSED
Revision 1.2
checksum
Dataram ID
Dataram ID
UNUSED
UNUSED
Space
UNUSED
UNUSED
[serial number]
UNUSED
3C
69
80
18
22
06
00
12
4D
7F
91
00
00
20
00
00
00
Page 9
DTM63332
2GB - 256Mx72, 240-Pin Registered DDR2 DIMM with CMD/ADD Parity
DATARAM CORPORATION, USA Corporate Headquarters, P.O.Box 7528, Princeton, NJ 08543-7528;
Voice: 609-799-0071, Fax: 609-799-6734; www.dataram.com
DATARAM, Europe-EMEA Headquarters, Frichsparken, Soeren Frichs Vej 42R, 8230 Aabyhoej, Denmark;
Voice: +45 70 212 212, Fax: +45 70 212 216; www.dataram.com
All rights reserved.
The information contained in this document has been carefully checked and is believed to be reliable. However,
Dataram assumes no responsibility for inaccuracies.
The information contained in this document does not convey any license under the copyrights, patent rights or
trademarks claimed and owned by Dataram.
No part of this publication may be copied or reproduced in any form or by any means, or transferred to any third party
without prior written consent of Dataram.
Document 06880, Revision A, 18-May-06, Dataram Corporation © 2006
Page 10
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