- Industrial & lab equipment
- Electrical equipment & supplies
- Circuit protection
- Voltage regulators
- User manual
advertisement
ICE5xRxxxxAG
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-
12 Package
Product highlights
Integrated 700 V/ 800 V avalanche rugged CoolMOS™
Enhanced Active Burst Mode with selectable entry and exit standby power to reach the lowest standby power <100 mW
Digital frequency reduction for better overall system efficiency
Fast startup achieved with cascode configuration
Frequency jitter and soft gate driving for low EMI
Integrated error amplifier
Comprehensive protection with input line over voltage protection
Pb-free lead plating, halogen-free mold compound, RoHS compliant
PG-DSO-12
Features
Integrated 700 V/ 800 V avalanche rugged
CoolMOS™
Enhanced Active Burst Mode with selectable entry and exit standby power
Digital frequency reduction for better overall system efficiency
Fast startup achieved with cascode configuration
DCM and CCM operation with slope compensation
Frequency jitter and soft gate driving for low EMI
Built-in digital soft start
Integrated error amplifier to support direct feedback in non-isolated flyback
Comprehensive protection with input line over voltage protection, V
CC
over voltage, V
CC
under voltage, overload/open loop, over temperature and Current Sense (CS) short to GND
All protections are in auto restart mode
Limited charging current for V
CC
short to GND
Applications
Auxiliary power supply for home appliances/white goods, TV, PC & server
Blu-ray player, set-top box & LCD/LED monitor
Product validation
Qualified for industrial applications according to the relevant tests of JEDEC47/20/22
Description
The ICE5xRxxxxAG is the 5 th
generation of fixed frequency integrated power IC (CoolSET™) optimized for off-line switch mode power supply in cascode configuration. The CoolSET™ package has 2 separate chips inside; one is controller chip and the other is a
700 V/ 800 V CoolMOS™ chip. The cascode configuration helps achieve fast startup. The frequency reduction with soft gate driving and frequency jitter operation offers lower EMI and better efficiency between light load and 50% load. The selectable entry and exit standby power ABM enables flexibility and ultra-low power consumption at standby mode with small and controllable output voltage ripple. The product has a wide operating range (10.0 ~ 25.5 V) of IC power supply and lower power consumption. The numerous protection functions with adjustable line over voltage protection support the power supply system in failure situations.
All these make the 5 th generation CoolSET™ series an outstanding integrated power stage fixed frequency flyback converter in the market.
Datasheet www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 1 of 42
V 2.0
2017-11-21
ICE5xRxxxxAG
85 ~ 300 VAC
D r1
~D r4
R
I1
VIN
R
I2
GND
# Optional
R
Sel
(Burst mode detect)
R ovs3
(V
02
feedback)
C bus
R
START UP
R
VCC
Snubber
D
VCC
W p
W s1
D
O1
C
O1
L f1
C f1
C
VCC
W a
W s2
D
O2
VCC GATE
DRAIN
CoolMOS
TM
C
PS
Power Management
PWM controller
Current Mode Control
Cycle-by-Cycle current limitation
Digital Control
Error Amplifier
Active Burst Mode
Protections
D
Control Unit
Gate
Driver
ICE5xRxxxxAG CoolSET
TM
C
2
CS
R
CS
VERR
FB
Optocoupler
R b1
C
O2
L f2
TL431
R b2
R c1
C f2
R ovs1
C c1
C c2
R ovs2
V
O1
V
O2
# R ovs3
Figure 1 Typical application in isolated flyback using TL431 and optocoupler
85 ~ 300 VAC
D r1
~D r4
R
I1
VIN
R
I2
GND
# Optional
R
Sel
(Burst mode detect)
W p
C bus
R
START UP
R
VCC
Snubber
D
VCC
C
VCC
VCC GATE
DRAIN
CoolMOS
TM
Power Management
V
P1
C fP1
PWM controller
Current Mode Control
Cycle-by-Cycle current limitation
Digital Control
Error Amplifier
Active Burst Mode
Protections
D
Gate
Driver
CS
R
CS
Control Unit
ICE5xRxxxxAG CoolSET
TM
VERR
FB
C
2
R
1
C
1
R
F2
R
F1
L fP1
D
P1
W a
C
P1
W
P1
C
PS
W s1
D
O1
C
O1
L f1
C f1
V
O1
Figure 2 Typical application in non-isolated flyback utilizing integrated error amplifier
Output power of 5
th
generation Fixed-Frequency CoolSET™
Table 1 Output power of 5 th
generation Fixed-Frequency CoolSET™
Type Package
ICE5AR4770AG PG-DSO-12
ICE5GR4780AG PG-DSO-12
Marking
5AR4770AG
5GR4780AG
V
DS
Fsw
700 V 100 kHz
800 V 125 kHz
R
DSon
1
4.73 Ω
4.13 Ω
220 V AC ±20% 2 at DCM
27 W
27.5 W
85-300 V AC 2 at DCM
15 W
15 W
85-300 V AC at CCM
2
16 W
16 W
ICE5GR2280AG PG-DSO-12
ICE5GR1680AG PG-DSO-12
ICE5AR0680AG PG-DSO-12
5GR2280AG
5GR1680AG
5AR0680AG
800 V 125 kHz
800 V 125 kHz
800 V 100 kHz
2.13 Ω
1.53 Ω
0.71 Ω
41 W
48 W
68 W
23 W
27 W
40 W
24 W
28 W
42 W
1 Typ. at T
J
=25 °C (inclusive of low side MOSFET)
2
Calculated maximum output power rating in an open frame design at T a
=50 °C, T
J
=125 °C (integrated high voltage MOSFET) and using minimum drain pin copper area in a 2 oz copper single sided PCB. The output power figure is for selection purpose only. The actual power can vary depending on particular designs. Please contact to a technical expert from Infineon for more information.
Datasheet www.infineon.com
Please read the Important Notice and Warnings at the end of this document
page 2 of 42
V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Pin configuration and functionality
Table of contents
voltage during start-up ....................................................................... 8
Datasheet 3 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Pin configuration and functionality
Datasheet 4 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Pin configuration and functionality
1 Pin configuration and functionality
The pin configuration is shown in Figure 3 and the functions are described in Table 2.
VIN
1
PG-DSO-12
12 GND
VERR 2 11 VCC
FB 3
CS
4
10 GATE
9
NC
DRAIN 5 8 DRAIN
DRAIN
6 7
DRAIN
Figure 3 Pin configuration
Table 2
Pin
1
2
3
4
Pin definitions and functions
Symbol Function
VIN
VERR
FB
CS
Input Line Over Voltage Protection (LOVP)
VIN pin is connected to the bus via resistor divider (see Figure 1) to sense the line voltage.
Internally, it is connected to the line over voltage comparator which will stop the switching when LOVP condition occurs. To disable LOVP, connect this pin to GND.
Error amplifier
VERR pin is internally connected to the transconductance error amplifier for non-isolated flyback application. Connect this pin to GND for isolated flyback application.
Feedback and ABM entry/exit control
FB pin combines the functions of feedback control, selectable burst entry/exit control and overload/open loop protection.
Current sense
The CS pin is connected to the shunt resistor for the primary current sensing externally and to the PWM signal generator block for switch-off determination (together with the feedback voltage) internally. Moreover, CS short to ground protection is sensed via this pin.
Datasheet 5 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Pin configuration and functionality
Pin
5, 6, 7,
8
9
10
11
12
Symbol Function
DRAIN DRAIN(Drain of integrated CoolMOS™)
The DRAIN pin is connected to the drain of the integrated CoolMOS™.
NC
GATE
No connection
Gate driver output
The GATE pin is connected to the Gate of the internal CoolMOS™ and additionally, a pull up resistor is connected from bus voltage to turn on the internal CoolMOS™ for charging up the V
CC
capacitor during startup.
VCC
GND
VCC(Positive voltage supply)
The VCC pin is the positive voltage supply to the IC. The operating range is between
V
VCC_OFF
and V
VCC_OVP
.
Ground
The GND pin is the common ground of the controller.
Datasheet 6 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Representative block diagram
2
VIN
Representative block diagram
VCC
Line Overvoltage Protection
V
VIN_LOVP
C7a
250 µs
Blanking time
100 ns
Blanking time
S Q
R
Input
OVP
Mode
Autorestart
Protect
Power Management
Undervoltage Lockout
16.0V
10.0V
Voltage
Reference
Internal
Bias
V
VCC_OVP
C20 t
VCC_OVP_B
GATE DRAIN
Thermal Protection
T j
> T jcon_OT P
50 µs
Blanking time
S
Q
OTP
Mode
R
T j
< T jcon_OTP
-T jHYS_OTP
Autorestart
Protect
Error Amplifier
Non-
Isolated
Detector
VERR
V
FB_OLP
/
V
FB_LB
C12
ERR
V
ERR_REF
V
REF
R
FB
Overload Protection
Burst
Mode detect t
FB_OLP_B
FB
Active Burst Block
Burst Mode
Level Select
V
FB_EBHP
V
FB_EBLP
No bur st
C9 t
FB_BEB
2pF
V
FB_BOn
C10
V
FB_BOff
C11
Figure 4
Active
Burst Mode
Representative block diagram f
OSC_2
OSC with
Jitter and
Frequency
Reduction f
OSC
OSC
Protection and PWM Digital Control
V
1
C
PWM
PWM
Comparator
V
PWM
PWM OP
G
PWM
Current Mode
D1
Gate Driver
Gate
Drive
Gate
Drive
V
CS_BLP
V
CS_BHP
C13
Peak current limit
V
CS_Nx
C15
V
REF
Leading
Edge
Blanking t
CS_LEB
1pF
D2
Slope
Comp
10kΩ
C15a
Soft-start
Delay t
CS_STG
C19
V
CS_STG
Slope Compensation/Current Limiting
GND
CS
Note: Junction temperature of the controller chip is sensed for over temperature protection. The
CoolMOS
TM
is a separate chip from the controller chip in the same package. Please refer to the design guide and/or consult a technical expert for the proper thermal design.
Datasheet 7 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3 Functional description
3.1 V
CC
pre-charging and typical V
CC
voltage during start-up
BUS.
The pull up resistor R
STARTUP
provides a current to charge the C iss
(input capacitance) of CoolMOS™ and gradually generate one voltage level. If the voltage over C iss
is high enough, CoolMOS™ on and V charged through primary inductance of transformer L
P,
CC
CoolMOS™ and internal diode D
capacitor will be
1
with two steps constant current source I
VCC_ Charge1
1
and I
VCC_ Charge3
1
.
A very small constant current source (I
VCC_Charge1
) is charged to the V
CC capacitor till V
CC
reach V
CC_SCP
to protect the controller from V
(I
VCC_Charge3
CC
pin short to ground during the start up. After this, the second step constant current source
) is provided to charge the V
CC
capacitor further, until the V
CC
voltage exceeds the turned-on threshold
V
VCC_ON
. As shown in the time phase I in Figure 5, the V
CC
voltage increase almost linearly with two steps.
V
VCC
V
VCC_ON
V
VCC_OFF t
A
V
VCC_SCP
I
VCC
I t
B
II III t
I
VCC_Normal
0
I
VCC_Charge1 t
Figure 5
I
VCC_Charge2/3
-I
VCC
V
CC
voltage and current at startup t1 t2
The time taking for the V
CC
pre-charging can then be approximately calculated as: 𝑡
1
= 𝑡
A
+ 𝑡
B
=
𝑉
𝑉𝐶𝐶_𝑆𝐶𝑃
∙ 𝐶
𝑉𝐶𝐶
𝐼
𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒1
+
(𝑉
𝑉𝐶𝐶_𝑂𝑁
− 𝑉
𝑉𝐶𝐶_𝑆𝐶𝑃
𝐼
𝑉𝐶𝐶_𝐶ℎ𝑎𝑟𝑔𝑒3
) ∙ 𝐶
𝑉𝐶𝐶
(1)
When the V
CC
voltage exceeds the V
CC
turn on threshold V
VCC_ON at time t
1
, the IC begins to operate with soft-start.
Due to power consumption of the IC and the fact that there is still no energy from the auxiliary winding to charge the V
CC
capacitor before the output voltage is built up, the V
CC
voltage drops (Phase II). Once the output voltage rises close to regulation, the auxiliary winding starts to charge the V
CC and delivering the I
VCC_ Normal
2 to the CoolSET™. The V
CC
capacitor from the time t
2 onward
then will reach a constant value depending on output load.
1 I
VCC_ Charge1/2/3
is charging current from the controller to VCC capacitor during start up
2 I
VCC_ Normal is supply current from VCC capacitor or auxiliary winding to the CoolSET™ during normal operation
Datasheet 8 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.2 Soft-start
As shown in Figure 6, the IC begins to operate with a soft-start at time t
on
. The switching stresses on the power
MOSFET, diode and transformer are minimized during soft-start. The soft-start implemented in ICE5xRxxxxAG is a digital time-based function. The preset soft-start time is t
SS
(12 ms) with 4 steps. If not limited by other functions, the peak voltage on CS pin will increase step by step from 0.3 V to V
CS_N
(0.8 V) finally. The normal feedback loop will take over the control when the output voltage reaches its regulated value.
Figure 6 Maximum current sense voltage during soft start
3.3 Normal operation
The PWM controller during normal operation consists of a digital signal processing circuit including regulation control and an analog circuit including a current measurement unit and a comparator. Details about the full operation of the CoolSET™ in normal operation are illustrated in the following paragraphs.
3.3.1 PWM operation and peak current mode control
3.3.1.1 Switch-on determination
The power MOSFET turn-on is synchronized with the internal oscillator with a switching frequency f
SW
that corresponds to the voltage level V
FB
3.3.1.2 Switch-off determination
In peak current mode control, the PWM comparator monitors voltage V
1
representation of the instantaneous current of the power MOSFET. When V
1
exceeds V
FB
, the PWM comparator sends a signal to switch off the GATE of the power MOSFET. Therefore, the peak current of the power MOSFET is controlled by the feedback voltage V
FB
At switch on transient of the power MOSFET, a voltage spike across R
CS
To avoid a false switch off, the IC has a blanking time t
CS_LEB
can cause V
1
to increase and exceed V
before detecting the voltage across R
FB
.
CS
to mask the voltage spike. Therefore, the minimum turn on time of the power MOSFET is t
CS_LEB
.
For some reason that the voltage level at V
1
takes long time to exceed V
FB duty cycle control to force the power MOSFET to switch off when D
MAX
, the IC has implemented a maximum
= 0.75 is reached.
Datasheet 9 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
Figure 7 Pulse width modulation
3.3.2 Current sense
The power MOSFET current generates a voltage V
CS
across the current sense resistor R
CS
connected between the
CS pin and the GND pin. V
CS
is amplified with gain G described below in below equation 3.
PWM
, then, added with an offset V
PWM
to become V
1
as
(2) 𝑉
CS
= 𝐼
D
× 𝑅
CS
𝑉
1
= 𝑉
CS
∗ 𝐺
PWM
+ 𝑉
PWM where, V
CS
I
D
R
CS
V
1
G
PWM
V
PWM
: CS pin voltage
: power MOSFET current
: resistance of the current sense resistor
: voltage level compared to V
FB
as described in section 3.3.1.2
: PWM-OP gain
: offset for voltage ramp
(3)
Datasheet 10 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.3.3 Frequency reduction
Frequency reduction is implemented in ICE5xRxxxxAG to achieve a better efficiency during the light load. At light load, the reduced switching frequency F
SW
improves efficiency by reducing the switching loses.
When load decreases, V
FB
decreases as well. F
SW
is dependent on the V
FB decreases as the load decreases.
as shown in Figure 8. Therefore, F
SW
Typically, F
SW
at high load is 100 kHz/ 125 kHz and starts to decrease at V
FB
= 1.7V. There is no further frequency reduction once it reached the f
OSCx_MIN
even the load is further reduced.
f
SW
(V
FB
) V
CS
(V
FB
)
Vcs
V
CS_N
0.80 V
f
OSC2
/ f
OSC4
125 kHz / 100 kHz
Fsw f
OSC2_ABM
/ f
OSC4_ABM
103 kHz / 83 kHz
BM f
OSC2_MIN
/ f
OSC4_MIN
53 kHz / 43 kHz
No B M
BM
V
CS_BHP /
V
CS_BLP
0.27 V /0.22 V
No B M
0.5 V
V
FB_EBxP
0.93 / 1.03 V
Frequency reduction curve
1.35 V 1.7 V
V
FB_OL P
2.73 V
V
FB
Figure 8
3.3.4 Slope compensation
ICE5xRxxxxAG can operate at Continuous Conduction Mode (CCM). At CCM operation, duty cycle greater than
50% may generate a sub-harmonic oscillation. To avoid the sub-harmonic oscillation, slope compensation is added to V
CS
pin when the gate of the power MOSFET is turned on for more than 40% of the switching cycle period. The relationship between V
FB
and the V
CS
for CCM operation is described in below equation 4:
𝑉
FB
= 𝑉
CS
∗ 𝐺
PWM
+ 𝑉
PWM
+ 𝑀
COMP
∗ (𝑇
ON
− 40% ∗ 𝑇
PERIOD
) (4) where, T
ON
: gate turn on time of the power MOSFET
M
COMP
: slope compensation rate
T
PERIOD
: switching cycle period
Slope compensation circuit is disabled and no slope compensation is added into the V
CS mode to save the power consumption.
pin during active burst
Datasheet 11 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.3.5 Oscillator and frequency jittering
The oscillator generates a frequency of 100 kHz/ 125 kHz with frequency jittering of ±4% at a jittering period of
T
JITTER
(4 ms). The frequency jittering helps to reduce conducted EMI.
A capacitor, a current source and current sink which determine the frequency are integrated. The charging and discharging current of the implemented oscillator capacitor are internally trimmed in order to achieve a highly accurate switching frequency.
Once the soft-start period is over and when the IC goes into normal operating mode, the frequency jittering is enabled. There is also frequency jittering during frequency reduction.
3.3.6 Modulated gate drive
The drive-stage is optimized for EMI consideration. The switch on speed is slowed down before it reaches the
Thus the leading switch spike during turn on is minimized.
Figure 9 Gate rising waveform
3.4 Peak current limitation
There is a cycle by cycle peak current limitation realized by the current limit comparator to provide primary over-current protection. The primary current generates a voltage V connected between the CS pin and the GND pin. If the voltage V
CS
CS
across the current sense resistor R
exceeds an internal voltage limit V
CS_N
CS
, the comparator immediately turns off the gate drive.
The primary peak current I
PEAK_PRI
can be calculated as below:
𝐼
PEAK_PRI
= 𝑉
CS_N
⁄ 𝑅
CS
To avoid mistriggering caused by MOSFET switch on transient voltage spikes, a leading edge blanking time
(t
CS_LEB
) is integrated in the current sensing path.
(5)
3.4.1 Propagation delay compensation
In case of overcurrent detection, there is always a propagation delay from sensing the V
CS
to switching the power MOSFET off. An overshoot on the peak current I peak
the primary current (see Figure 10).
caused by the delay depends on the ratio of dI/dt of
Datasheet 12 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
Figure 10 Current limiting
The overshoot of Signal2 is larger than Signal1 due to the steeper rising waveform. This change in the slope is depending on the AC input voltage. Propagation delay compensation is integrated to reduce the overshoot due to dI/dt of the rising primary current. Thus the propagation delay time between exceeding the current sense threshold V
CS_N
and the switching off of the power MOSFET is compensated over wide bus voltage range.
Current limiting becomes more accurate which will result in a minimum difference of overload protection triggering power between low and high AC line input voltage.
Under CCM operation, the same V
CS
do not result in the same power. In order to achieve a close overload
the curve is used for T
ON
greater than 0.40 duty cycle and the other is for lower than 0.40 duty cycle.
Figure 11 Dynamic voltage threshold V
CS_N
Similarly, the same concept of propagation delay compensation is also implemented in ABM with reduced level. With this implementation, the entry and exit burst mode power can be close between low and high AC line input voltage.
Datasheet 13 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.5 Active Burst Mode (ABM) with selectable power level
At light load condition, the IC enters ABM operation to minimize the power consumption. Details about ABM operation are explained in the following paragraphs.
3.5.1 Entering ABM operation
The sytem will enter into ABM operation when two conditions below are met:
the FB voltage is lower than the threshold of V
FB_EBLP
/V
FB_EBHP depending on burst configuration option setup and a certain blanking time t
FB_BEB
Once all of these conditions are fulfilled, the ABM flip-flop is set and the controller enters ABM operation. This multi-condition determination for entering ABM operation prevents mis-triggering of entering ABM operation, so that the controller enters ABM operation only when the output power is really low.
3.5.2 During ABM operation
After entering ABM, the PWM section will be inactive making the V
OUT
start todecrease. As the V
OUT
decreases, V
FB rises. Once V
FB switching.
exceeded V
FB_BOn
, the internal circuit is again activated by the internal bias to start with the
If the PWM is still operating and the output load is still low, V
When V
FB
reaches the low threshold V
OUT
increases and V
FB
signal starts to decrease.
FB_BOff
, the internal bias is reset again and the PWM section is disabled with no switching until V
FB
increases back to exceed V
FB_BOn threshold.
In ABM, V
FB
is like a sawtooth waveform swinging between V
FB_BOff
and V
FB_BOn
During ABM, the switching frequency f
OSCx_ABM
is 83 kHz for 100 kHz version and 103 kHz for 125 kHz version IC.
The peak current I
PEAK_ABM of the power MOSFET is defined by:
𝐼
PEAK_ABM
= 𝑉
CS_BxP
⁄
𝑅
CS where V
CS_BxP
is the peak current limitation in ABM
(6)
3.5.3 Leaving ABM operation
The FB voltage immediately increases if there is a sudden increase in the output load. When V
FB will leave ABM and the peak current limitation trhreshold voltage will return back to V
CS_N
exceeds V
FB_LB,
immediately. it
Datasheet 14 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
V
FB
V
FB_LB
V
FB_BOn
V
FB_BOff
V
FB_EBHP
/V
FB_EBLP
Entering Active Burst Mode
Leaving Active Burst Mode
Blanking Window (t
FB_BEB
)
V
CS
V
CS_N
V
CS_BHP
/V
CS_BLP
V
VCC
Current limit level during Active Burst Mode
V
VCC_off
V
O
Max. Ripple < 1% t t t t
Figure 12 Signals in Active Burst Mode
Burst Mode Operation
Datasheet 15 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.5.4 ABM configuration
The burst mode entry level can be selected by changing the different resistance R
Sel
at FB pin. There are 3 configuration options depending on R
Sel
which corresponds to the options of no ABM (Option 1), low range of
ABM power (Option 2) and high range of ABM power (Option 3). The table below shows the control logic for the entry and exit level with the FB voltage.
Table 3 ABM configuration option setup
Option R
Sel
1
2
<470 kΩ
720 kΩ ~ 790 kΩ
3(Default) >1210 kΩ
V
FB
V
FB
< V
FB_P_BIAS1
V
FB_P_BIAS1
<V
FB
<V
FB_P_BIAS2
V
FB
> V
FB_P_BIAS2
V
-
CS_BxP
0.22V
0.27V
Entry level
V
FB_EBxP
No ABM
0.93 V
1.03 V
Exit level
V
FB_LB
No ABM
2.73 V
2.73 V
During IC first startup, the controller preset the ABM selection to Option 3, the FB resistor (R
internal switch S2 (see Figure 13)and a current source I
sel
is turned on instead.From V
CC
FB
) is turned off by
= 4.44 V to V
CC
on threshold, the FB pin will start to charge resistor R
Sel
with current I
Sel
to a certain voltage level. When V
CC
reaches
V
CC
on threshold, the FB voltage is sensed. The burst mode option is then chosen according to the FB voltage level. After finishing the selection, any change on the FB level will not change the burst mode option and the current source (I sel
) is turned off while the FB resistor (R
FB
) is connected back to the circuit (Figure 13).
Figure 13 ABM detect and adjust
3.6 Non-isolated/isolated configuration
ICE5xRxxxxAG has a VERR Pin, which is connected to the input of an integrated error amplifier to support non-
isolated flyback application (see Figure 2). When V
CC
is charging and before reaching the V
CC
on threshold, a current source I
ERR_P_BIAS
from VERR pin together with R
F1 is more than V
ERR_P_BIAS
and R
F2
will generate a voltage across it. If VERR voltage
(0.2 V), non-isolated configuration is selected, otherwise, isolated configuration is selected. In isolated configuration, the error amplifier output is disconnected from the FB pin.
In case of non-isolated configuration, the voltage divider R
F1
and R
F2
is used to sense the output voltage and compared with the internal reference voltage V
ERR_REF
. The difference between the sensed voltage and the reference voltage is converted as an output current by the error amplifier. The output current will charge/discharge the resistor and capacitor network connected at the FB pin for the loop compensation.
Datasheet 16 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.7 Protection functions
The ICE5xRxxxxAG provides numerous protection functions which considerably improve the power supply system robustness, safety and reliability. The following table summarizes these protection functions and the corresponding protection mode whether as a non switch auto restart, auto restart or odd skip auto restart
mode. Refer to Figure 14, Figure 15 and Figure 16 for the waveform illustration of protection modes.
Table 4 Protection functions
Protection Functions Normal Mode Protection Mode
Line over voltage
V
CC
over voltage
V
CC
under voltage
Overload/ open loop
Over temperature
CS short to GND
V
CC
short to GND
√
√
√
√
√
√
√
Burst Mode
Burst ON Burst OFF
√ √
√
√
NA
√
1
NA
1
√
√
NA
1
√
NA
1
√ √
Non switch auto restart
Odd skip auto restart
Auto restart
Odd skip auto restart
Non switch auto restart
Odd skip auto restart
No startup
3.7.1 Line over voltage
The AC Line Over Voltage Protection (LOVP) is detected by sensing bus capacitor voltage through VIN pin via
voltage divider resistors, Rl1 and Rl2 (Figure 1). Once V
(V
VIN_LOVP
VIN
voltage is higher than the line over voltage threshold
), the controller enters into protection mode until V
VIN
is lower than V
VIN_LOVP
. This protection can be disabled by connecting VIN pin to GND.
3.7.2 V
CC
over/under voltage
During operation, the V
CC
voltage is continuously monitored. If V
CC
is either below V
VCC_OFF
for 50 µs (t
VCC_OFF_B
) or above V
VCC_OVP
for 55 µs (t
VCC_OVP_B
), the power MOSFET is kept switch off. After the V
CC
voltage falls below the threshold V
VCCoff
, the new start up sequence is activated. The V
CC exceeds the threshold V
VCC_ON
capacitor is then charged up. Once the voltage
, the IC begins to operate with a new soft-start.
3.7.3 Overload/ open loop
In case of open control loop or output overload, the FB voltage will be pulled up. When V
FB a blanking time of t
FB_OLP_B
exceeds V
FB_OLP
after
, the IC enters odd skip auto restart mode. The blanking time enables the converter to provide a peak power in case the increase in V
FB
is due to a sudden load increase.
3.7.4 Over temperature
If the junction temperature of controller exceeds T jcon_OTP
, the IC enters into Over Temperature Protection (OTP) auto restart mode. The IC has also implemented with a 40
°
C hysteresis. That means the IC can only be recovered from OTP when the controller junction temperature is dropped 40 point.
° C lower than the over temperature trigger
1 Not Applicable
Datasheet 17 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
3.7.5 CS short to GND
If the voltage at the current sense pin is lower than the preset threshold V
CS_STG
with certain blanking time t
CS_STG_B
for three consecutive pulses during on-time of the power switch, the IC enters CS short to GND protection.
3.7.6 V
CC
short to GND
To limit the power dissipation of the startup circuit at V
CC limited to a minimum level of I
VCC_ Charge1
short to GND condition, the V
CC
charging current is
. With such low current, the power loss of the IC is limited to prevent overheating.
3.7.7 Protection modes
All the protections are in auto restart mode with a new soft start sequence. The three auto restart modes are illustrated in the following figures.
Fault detected
Fault released
Start up and detect at every charging cycle
Switching start at the
V
VCC
V
CC_ON
V
CC_OFF
V
CS
No switching t t
Figure 14 Non switch auto restart mode
Datasheet 18 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Functional description
Fault detected
Fault released
Start up and detect at every charging cycle
Switching start at the
V
VCC
V
CC_ON
V
CC_OFF
V
CS t t
Figure 15 Auto restart mode
V
VCC
V
CC_ON
V
CC_OFF
V
CS
Fault detected
Fault released
Start up and detect at every even charging cycle
No detect No detect
Switching start at the cycle t t
Figure 16 Odd skip auto restart
Datasheet 19 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
4 Electrical characteristics
Attention: All voltages are measured with respect to ground (Pin 12). The voltage levels are valid if other ratings are not violated.
4.1 Absolute maximum ratings
Attention:
Table 5
Parameter
Drain Voltage
ICE5xRxx70AG
ICE5xRxx80AG
Pulse drain current
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
Avalanche energy, repetitive, t
AR
limited by max. T
J
=150 °C and T
J,Start
= 25 °C
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
Avalanche current, repetitive,t
AR
limited by max. T
J
=150 °C and T
J,Start
= 25 °C
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
VCC Supply Voltage
GATE Voltage
1 Pulse width t
P
limited by T j,max
2 Pulse width t
P
= 20 µs and limited by T j,max
Datasheet
Stresses above the maximum values listed here may cause permanent damage to the device.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit. For the same reason, make sure that any capacitor that will be connected to pin 11 (VCC) is discharged before assembling the application circuit.
T a
=25 °C unless otherwise specified.
Absolute maximum ratings
Symbol Limit Values Unit Note / Test Condition
Min. Max.
V
DRAIN
V T j
= 25 °C
I
D,Pulse
-
-
-
-
-
-
-
700
800
2.2
1
2.6
1
5.8
2
5.8
2
5.8
2
A
V
E
AR
V
I
AR
CC
GATE
-
-
-
-
-
-
-
-
-
-
-0.3
-0.3
0.02
0.02
0.05
0.07
0.22
0.14
0.20
0.40
0.60
1.80
27.0
27.0 mJ
I
D
=0.14 A, V
DD
=50 V
I
D
=0.20 A, V
DD
=50 V
I
D
=0.40 A, V
DD
=50 V
I
D
=0.60 A, V
DD
=50 V
I
D
=1.80 A, V
DD
=50 V
A
V
V
20 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
FB Voltage
VERR Voltage
CS Voltage
VIN Voltage
Maximum DC current on any pin
ESD robustness HBM
ESD robustness CDM
Junction temperature range
Storage Temperature
Thermal Resistance (Junction- Ambient)
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
V
FB
V
ERR
V
CS
V
CS
V
ESD_HBM
V
ESD_CDM
T
J
T
STORE
R
thJA
-0.3
-0.3
-0.3
-0.3
-10.0 10.0
- 2000
-
-40
500
150
-55
-
-
-
-
-
150
104
105
98
95
94
3.6
3.6
3.6
3.6
V
V
V
V mA Except DRAIN and CS pin
V According to EIA/JESD22
V
°C Controller & CoolMOS
°C
K/W Setup according to the JEDEC standard JESD51 and using minimum drain pin copper area in a 2 oz copper single sided PCB
4.2 Operating range
Note:
Table 6
Parameter
Within the operating range, the IC operates as described in the functional description.
Operating range
Symbol
VCC Supply Voltage
Junction Temperature of controller
T
V
VCC jCon_op
Junction Temperature of CoolMOS
T jCoolMOS_op
4.3 Operating conditions
Limit Values
Min. Max.
Unit Remark
V
VCC_OFF
V
VCC_OVP
-40
T jCon_OTP
˚C Max value limited due to OTP of controller chip
-40 150 ˚C
Note: The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range T
J
from – 40
°
C to 125
°
C. Typical values represent the median values, which are related to 25 °C. If not otherwise stated, a supply voltage of V
CC
= 18 V is assumed.
Table 7 Operating conditions
Parameter
VCC Charge Current
Current Consumption, Startup Current I
Symbol Limit Values
Min. Typ. Max.
Unit Note / Test Condition
I
VCC_Charge1
-0.35 -0.20 -0.09 mA
V
VCC
V
DRAIN
=0 V, R
StartUp
=90 V
=50 MΩ and
I
VCC_Charge2
- -3.2 - mA V
VCC
=3 V, R
V
DRAIN
=90 V
StartUp
=50 MΩ and
I
VCC_Charge3
-5 -3 -1
VCC_Startup
- 0.25 - mA V
VCC
=15 V, R
StartUp
=50 MΩ and V
DRAIN
=90 V mA V
VCC
=15 V
Datasheet 21 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
Current Consumption, Normal
Current Consumption, Auto Restart
Current Consumption, Burst Mode –
Isolated
Current Consumption, Burst Mode –
Non-Isolated
VCC Turn-on Threshold Voltage
VCC Turn-off Threshold Voltage
VCC Short Circuit Protection
VCC Turn-off blanking
I
VCC_Normal
-
I
VCC_AR
-
-
I
VCC_Burst
Mode_ISO
I
VCC_Burst
Mode_NISO
-
0.9
410
0.54
0.61 -
t
V
VCC_ON
15.3 16.0 16.5
V
VCC_OFF
9.4 10.0 10.4
V
VCC_SCP
VCC_OFF_B
-
-
1.1 1.9
50 -
-
-
- mA I
FB
=0 A (No gate switching)
µA mA mA
V
V
V
µs
4.4
Table 8
Parameter
Internal voltage reference
Internal voltage reference
Symbol Limit Values
Min. Typ. Max.
3.20 3.30 3.39
Unit Note / Test Condition
V Measured at pin FB I
FB
=0 A Internal Reference Voltage
4.5 PWM section
Table 9
Parameter
PWM section
V
REF
Symbol
f
OSC1 f
OSC2 f
OSC3 f
OSC4 f
OSC2_ABM
Min.
117
119
92
94
91
Limit Values
Typ.
125
125
100
100
103
Max.
133
131
108
106
114
Unit Note / Test
Condition k H z k H z T j
= 25 °C k H z k H z T j
= 25 °C k H z T j
= 25 °C
Fixed Oscillator Frequency –
125 kHz
Fixed Oscillator Frequency –
100 kHz
Fixed Oscillator Frequency –
125 kHz (Active Burst Mode)
Fixed Oscillator Frequency –
100 kHz (Active Burst Mode)
Fixed Oscillator Frequency –
125 kHz (Minimum Fsw)
Fixed Oscillator Frequency –
100 kHz (Minimum Fsw)
Frequency Jittering Range
Frequency Jittering period
Maximum Duty Cycle
Feedback Pull-Up Resistor
PWM-OP Gain
Offset for Voltage Ramp
Slope Compensation rate –
125 kHz
f
OSC4_ABM f
OSC2_MIN f
OSC4_MIN
F
JITTER
T
JITTER
D
MAX
R
FB
G
PWM
V
PWM
M
COMP
71
46
36
-
-
70
11
1.91
0.42
52.5
83
53
43
+/- 4
4
75
15
2.03
0.50
61.0
94
61
51 k H z T j
= 25 °C k H z T j
= 25 °C k H z T j
= 25 °C
-
-
80
20
2.16
0.58
% T j
= 25 °C m s T j
= 25 °C
% k Ω
V
68.0 m V / μ s V
CS
=0 V
Datasheet 22 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
Slope Compensation rate -
100 kHz
M
COMP
41 50 58
4.6
Table 10
Parameter
Error amplifier
Error amplifier
Symbol
Transconductance
G
ERR_M
Transconductance – Burst Mode
G
ERR_BM
I
ERR_SOURCE
Error Amplifier Source Current
Error Amplifier Sink Current
Error Amplifier Reference Voltage
I
V
ERR_SINK
ERR_REF
Error Amplifier Output Dynamic
Range of Transconductance
Error Amplifier Mode Bias Current
Error Amplifier Mode Threshold
I
V
ERR_DYN
ERR_P_BIAS
V
ERR_P_BIAS
Values Unit Note / Test Condition
Min. Typ. Max.
2.14 2.80 3.44 m A / V
6.9
85
9.2
150
11.6
223 m A / V
μ A
85
1.76
0.05
150
1.80
-
223
1.84
3.15
μ A
V
V
9.5
0.16
14.0
0.20
18.5
0.24 m V / μ s V cs
=0 V
μ A
V
4.7
Table 11
Parameter
Current sense
Current sense
Symbol
Min.
0.72
Limit Values
Typ.
0.80
Max.
0.88
Unit Note / Test Condition
V dv sense
/dt = 0.41V/ μ s Peak current limitation in normal operation
Peak current limitation in normal operation, 15% of T
ON
Leading Edge Blanking time
Peak Current Limitation in Active
Burst Mode - High Power
Peak Current Limitation in Active
Burst Mode - Low Power
V
CS_N
V
CS_N15
t
CS_LEB
V
CS_BHP
V
CS_BLP
0.74
70
0.23
0.18
0.79
220
0.27
0.22
0.84 V
365 ns
0.31 V
0.26
4.8 Soft start
Table 12
Parameter
Soft-Start time
Soft start
Soft-start time step
Symbol
t
SS
t
SS_S
1
Limit Values
Min. Typ. Max.
7.3
-
12.0
3
-
-
CS peak voltage at first step of soft start
V
SS1
1 - 0.30
1 The parameter is not subjected to production test - verified by design/characterization
-
Datasheet 23 of 42
V
Unit Note / Test Condition ms ms
V CS peak voltage
V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
- 0.15 - Step increment of CS peak voltage in soft start
4.9 Active Burst Mode
V
SS_S
1
Table 13
Parameter
Active Burst Mode
Symbol
Min.
2.5
Limit Values
Typ.
3.0
Max.
3.5
Charging current to select burst mode
Burst mode selection reference voltage Threshold
Burst mode selection reference voltage Threshold
Feedback voltage for entering
ABM for high power
Feedback voltage for entering
ABM for low power
Blanking time for entering
Active Burst Mode
Feedback voltage for leaving
Active Burst Mode
Feedback voltage for burst-on
– Isolated Case
Feedback voltage for burst-off
– Isolated Case
V
V
V
V
V
V
I sel
FB_P_BIAS1
FB_P_BIAS2 t
FB_EBHP
V
FB_EBLP
FB_BEB
FB_LB
FB_Bon_ISO
FB_BOff_ISO
Feedback voltage for burst-on
– Non-Isolated Case
Feedback voltage for burst-off
– Non-Isolated Case
V
FB_Bon_NISO
V
FB_BOff_NISO
1.65
2.76
0.98
0.88
-
2.63
2.26
1.88
1.88
1.50
1.73
2.89
1.03
0.93
36
2.73
2.35
2.00
1.95
1.55
1.80
3.01
1.08
0.98
-
2.83
2.45
2.05
2.05
1.64
V CS peak voltage
Unit Note / Test Condition
µA
V
V
V
V ms
V
V
V
V
V
4.10
Table 14
Parameter
Line over voltage protection
Line OVP
Symbol
Line Over Voltage threshold
Line Over Voltage Blanking
V
VIN_LOVP
t
VIN_LOVP_B
Limit Values
Min. Typ. Max.
2.75
-
2.85
250
2.95
-
Unit Note / Test Condition
V
µs
1 The parameter is not subjected to production test - verified by design/characterization
Datasheet 24 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
4.11 V
CC
over voltage protection
Table 15 V
CC
over voltage protection
Parameter
VCC Over Voltage threshold
VCC Over Voltage blanking
Symbol
V
VCC_OVP
t
VCC_OVP_B
Limit Values
Min. Typ. Max.
24.0
-
25.5
55
27.0
-
Unit Note / Test Condition
V
µs
4.12
Table 16
Parameter
Overload protection
Overload protection
Symbol Limit Values
Min. Typ. Max.
2.63 2.73 2.83
Unit Note / Test Condition
Over Load Detection threshold for
OLP protection at FB pin
Over Load Protection Blanking
Time
4.13
Table 17
Parameter
V
FB_OLP
t
FB_OLP_B
Thermal protection
Thermal protection
Symbol
30 54 -
V ms
Over temperature protection
Over temperature Hysteresis
Over temperature Blanking Time
T
jcon_OTP
1
T
jHYS_OTP
T
jcon_OTP_B
Limit Values
Min. Typ. Max.
129 140 150
-
-
40
50
-
-
Unit Note / Test Condition
°C Junction temperature of
°C
µs the controller chip (not the
CoolMOS™ chip)
4.14
Table 18
Parameter
CS short to GND protection
CS short to GND protection
Symbol
CS Short to Gnd Protection
CS Short to Gnd Consecutive
Trigger
CS Short to Gnd Sample period
V
CS_STG
P
CS_STG
Limit Values
Min. Typ. Max.
0.06 0.10 0.15
- 3 -
Unit Note / Test Condition
V cycle
t
CS_STG_SAM
t
PERIOD
*
0.36
t
PERIOD
0.4
*
t
PERIOD
0.44
*
µs
1 The parameter is not subjected to production test - verified by design/characterization
Datasheet 25 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Electrical characteristics
4.15 CoolMOS™ section
Table 19
Parameter
ICE5xRxxxxAG
Drain Source Breakdown Voltage
ICE5xRxx70AG
ICE5xRxx80AG
Drain Source On-Resistance (inclusive of low side MOSFET)
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
Effective output capacitance, energy related
1
ICE5AR4770AG
ICE5GR4780AG
ICE5GR2280AG
ICE5GR1680AG
ICE5AR0680AG
Rise Time
Fall Time
Symbol
V
(BR)DSS
R
DSon
C
o(er)
t
rise
t
fall
2
2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Limit Values
Min. Typ. Max.
700
800
-
-
-
-
3.4
3
7
8
24
4.73
8.73
1
4.13
8.69
1
2.13
4.31
1
1.53
3.01
1
0.71
1.27
1
-
-
-
-
-
5.18
-
4.85
-
2.35
-
1.75
-
0.80
-
- 30 -
- 30 -
Unit Note / Test Condition
V T
Ω pF ns ns j
= 25°C
Tj = 25°C
Tj=125°C at I
D
=0.4A
Tj = 25°C
Tj=125°C at I
D
=0.4A
Tj = 25°C
Tj=125°C at I
D
=1A
Tj = 25°C
Tj=125°C at I
D
=1.4A
Tj = 25°C
Tj=125°C at I
D
=2A
V
GS
=0V, V
DS
=0~480V
V
GS
=0V, V
DS
=0~500V
V
GS
=0V, V
DS
=0~500V
V
GS
=0V, V
DS
=0~500V
V
GS
=0V, V
DS
=0~500V
1 The parameter is not subjected to production test - verified by design/characterization
2 Measured in a typical flyback converter application
Datasheet 26 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
5 CoolMOS™ performance characteristics
Figure 17 Safe Operating Area (SOA) curve for ICE5AR4770AG
Figure 18 Safe Operating Area (SOA) curve for ICE5GR4780AG
Datasheet 27 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 19 Safe Operating Area (SOA) curve for ICE5GR2280AG
Figure 20 Safe Operating Area (SOA) curve for ICE5GR1680AG
Datasheet 28 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 21 Safe Operating Area (SOA) curve for ICE5AR0680AG
Figure 22 Power dissipation of ICE5AR4770AG; P tot
=f(T a
), (Maximum ratings as given in section 4.1 must not be exceeded)
Datasheet 29 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 23 Power dissipation of ICE5GR4780AG; P tot
=f(T a
), (Maximum ratings as given in section 4.1 must not be exceeded)
Figure 24 Power dissipation of ICE5GR2280AG; P tot
=f(T a
), (Maximum ratings as given in section 4.1 must not be exceeded)
Datasheet 30 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 25 Power dissipation of ICE5GR1680AG; P tot
=f(T a
), (Maximum ratings as given in section 4.1 must not be exceeded)
Figure 26 Power dissipation of ICE5AR0680AG; P tot
=f(T a
), (Maximum ratings as given in section 4.1 must not be exceeded)
Datasheet 31 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 27 Drain-source breakdown voltage ICE5xRxx70AG; V
BR(DSS)
=f(T
J
), I
D
=1 mA
Figure 28 Drain-source breakdown voltage ICE5xRxx80AG; V
BR(DSS)
=f(T
J
), I
D
=1 mA
Datasheet 32 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 29 Typical CoolMOS™ capacitances of ICE5AR4770AG (C=f(V
DS
);V
GS
=0 V; f=1 MHz)
Figure 30 Typical CoolMOS™ capacitances of ICE5GR4780AG (C=f(V
DS
);V
GS
=0 V; f=250 kHz)
Datasheet 33 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 31 Typical CoolMOS™ capacitances of ICE5GR2280AG (C=f(V
DS
);V
GS
=0 V; f=250 kHz)
Figure 32 Typical CoolMOS™ capacitances of ICE5GR1680AG (C=f(V
DS
);V
GS
=0 V; f=250 kHz)
Datasheet 34 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
CoolMOS™ performance characteristics
Figure 33 Typical CoolMOS™ capacitances of ICE5AR0680AG (C=f(V
DS
);V
GS
=0 V; f=250 kHz)
Datasheet 35 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Output power curve
6 Output power curve
The calculated output power curves versus ambient temperature are shown below. The curves are derived based on a typical DCM/CCM flyback in an open frame design setting the maximum T
J
of the integrated
CoolMOS™ at 125 °C, using minimum drain pin copper area in a 2 oz copper single sided PCB and steady state operation only (no design margins for abnormal operation modes are included).
The output power figure is for selection purpose only. The actual power can vary depending on a particular design. In a power supply system, appropriate thermal design margins must be considered to make sure that the operation of the device is within the maximum ratings given in section 4.1.
Figure 34 Output power curve of ICE5AR4770AG
Datasheet 36 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Output power curve
Figure 35 Output power curve of ICE5GR4780AG
Figure 36
Datasheet
Output power curve of ICE5GR2280AG
37 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Output power curve
Figure 37 Output power curve of ICE5GR1680AG
Figure 38
Datasheet
Output power curve of ICE5AR0680AG
38 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Outline dimension
7 Outline dimension
Figure 39 PG-DSO-12
Datasheet 39 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Marking
8 Marking
Figure 40 Marking of PG-DSO-12
Datasheet 40 of 42 V 2.0
2017-11-21
Fixed Frequency 700 V/800 V CoolSET™ - in DSO-12 Package
Revision history
Revision history
Document version
V 2.0
Date of release
21 Nov 2017
Description of changes
First release
Datasheet 41 of 42 V 2.0
2017-11-21
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2017-11-21
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2017 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this document?
Email: [email protected]
Document reference
ICE5xRxxxxAG
IMPORTANT NOTICE
The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. Before implementation of the product, the recipient of this application note must verify any function and other technical information given herein in the real application. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all information given in this application note.
The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application.
For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office
( www.infineon.com
).
WARNINGS
Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest
Infineon Technologies office.
Except as otherwise explicitly approved by Infineon
Technologies in a written document signed by authorized representatives of Infineon
Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.
advertisement
* Your assessment is very important for improving the workof artificial intelligence, which forms the content of this project