U4301 PCIe Gen3 Analyzer User Guide

U4301A PCIe Gen3
Analyzer
User Guide

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U4301-97001
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Edition
July 2013
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U4301A PCIe Gen3 Analyzer—At a Glance
The U4301A PCIe Gen3 analyzer lets you capture and decode PCI Express
3.0 (PCIe 3.0) data and view it in a Protocol Viewer window. The protocol
analyzer supports all PCIe 3.0 speeds, including 2.5 GT/s (Gen1) and
5.0 GT/s (Gen2) through PCIe 8 GT/s (Gen3), and it supports link widths
from x1 to x16.
The U4301A PCIe Gen3 analyzer is a module installed in an Agilent Digital
Test Console chassis (for example, the U4002A portable 2- slot chassis) or
Agilent AXIe chassis (for example, the M9502A 2 slot chassis).
When a controller PC is connected to an Agilent Digital Test
chassis via an external PCIe interface and cable, the Agilent
Analyzer application (running on the controller PC) lets you
the chassis, set up U4301A PCIe Gen3 analyzer data captures,
analysis.
Console
Logic
connect to
and perform
The U4301A PCIe Gen3 analyzer provides:
Effective presentation of protocol interactions from physical layer to
transaction layer:
• Industry standard spreadsheet format protocol viewer with:
• Highlighting by packet type or direction.
• Easy flow columns to better understand the stimulus and response
nature of the protocols.
• Context sensitive columns to show only the relevant information,
minimizing the need to scroll horizontally.
• Flexible GUI configuration to meet debug needs, with pre- defined GUI
layouts for Link Training debug, Config accesses, and general I/O.
Simple and powerful state- based triggering:
• New simple trigger mode makes it easy to setup single event triggers.
• Powerful state- based triggering including:
• Four states supported in trigger sequencer.
• Triggering on patterns (ordered set patterns or packet types).
• Internal counters and timers.
• Triggering on an ordered set on a specific lane.
• External trigger in/out.
Powerful hardware features ensure capture of important transition events:
• Dual phase lock loops (PLLs) per direction ensuring that the analyzer
will lock on speed change events quickly and not miss any critical data.
• Large 4 GB of capture buffer per module (up to 8 GB of capture for
x16 analyzer), for long recording sessions.
U4301A PCIe Gen3 Analyzer User Guide
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• PCIe Gen1 x4 link to the host PC, provides up to 10 Gbps of data
download.
• LEDs to show lane status and speed for fast understanding of current
link status.
See
4
• "Using the PCIe Gen3 Analyzer" on page 5
U4301A PCIe Gen3 Analyzer User Guide
Using the PCIe Gen3 Analyzer
For an overview and list of features, see: "U4301A PCIe Gen3 Analyzer—At
a Glance" on page 3
• Chapter 1, “Hardware and Software Installation,” starting on page 11
• Chapter 2, “Probing Options for PCIe Gen3,” starting on page 13
• Chapter 3, “Specifying the Connection Setup,” starting on page 15
• Chapter 4, “Setting the Capture Options,” starting on page 29
• Chapter 5, “Tuning the Analyzer for a Specific DUT,” starting on page
33
• Chapter 7, “Setting Up Triggers,” starting on page 53
• Chapter 8, “Running/Stopping Captures,” starting on page 63
• Chapter 9, “Viewing PCIe Gen3 Packets,” starting on page 65
• Chapter 10, “Viewing LTSSM States and State Transitions,” starting on
page 75
• Chapter 11, “Viewing Decoded Transactions,” starting on page 85
• Chapter 12, “Viewing Offline Performance Summary,” starting on page
111
See Also
• U4305 PCIe Gen3 exerciser documentation.
U4301A PCIe Gen3 Analyzer User Guide
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U4301A PCIe Gen3 Analyzer User Guide
Contents
U4301A PCIe Gen3 Analyzer—At a Glance
Using the PCIe Gen3 Analyzer
3
5
1 Hardware and Software Installation
2 Probing Options for PCIe Gen3
3 Specifying the Connection Setup
4 Setting the Capture Options
5 Tuning the Analyzer for a Specific DUT
PCIe Gen3 Tuning Overview 34
What is Tuning 34
How Tuning Works 34
When to Perform Tuning 34
Default and User Defined .ptu Files
Tuning - Broad steps 35
Tuning Method 36
35
Preparing the U4301A Module and DUT for Tuning
37
Creating a Physical Layer Tuning File 38
To create a physical layer tuning file 38
LEDs display during BER Based Tuning 42
Loading a Tuning File in the Logic and Protocol Analyzer GUI
Tuning a Bidirectional Setup
44
46
Fine Tuning a .ptu File 47
Fine Tuning Flow 47
To fine tune a .ptu file 47
6 Manually Adjusting the Equalizing Snoop Probe (ESP) Settings
7 Setting Up Triggers
Setting Up Simple Triggers
Setting Up Advanced Triggers
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57
7
Setting General Trigger Options 60
To select which links the trigger is for
To set the trigger position 60
To save/recall favorite triggers 61
To clear the current trigger 61
60
8 Running/Stopping Captures
9 Viewing PCIe Gen3 Packets
Viewing the Captured PCIe Traffic Statistics 67
Navigating through the captured PCIe packets
Viewing Errored Packets Statistics 70
Viewing LTSSM State Transitions
71
Viewing Offline Performance Summary
Viewing Decoded Transactions
68
72
73
Exporting Captured PCIe Data to a .csv File
74
10 Viewing LTSSM States and State Transitions
LTSSM Overview
Prerequisites
76
78
Configuring and Computing LTSSM States
79
Viewing LTSSM States/Transitions 80
Navigating Through the LTSSM States/Transitions Occurrences
Interpreting LTSSM Overview Results
81
83
11 Viewing Decoded Transactions
Transaction Decoding - Overview
Types of Protocols Supported
Transaction Decode Tab 86
86
86
Configuring and Computing Decoded Transactions 87
Before you Start 87
Defining / Verifying the Device Setup 87
Saving the Device Setup Details 91
Computing Transactions from the Captured Data 92
Saving the Computed Transaction Data 93
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U4301A PCIe Gen3 Analyzer User Guide
Interpreting and Navigating Through the Transaction Decode Results 95
Transaction Details Pane 95
Transaction Overview Pane 96
Navigating Through Transactions 97
Navigating Between Transactions and their Associated Packets 99
Viewing NVMe Transactions 101
Viewing Transactions for NVMe Controller Initialization 101
Viewing Admin Command Transactions 102
Viewing NVMe I/O Command Transactions 103
Viewing a Complete Set of Transactions for a Command Submission and
Completion 104
Viewing Decoded Payload for Commands 105
Viewing Decoded PRPs for Commands 106
Viewing Decoded MSI-X Table 108
12 Viewing Offline Performance Summary
Offline Performance Summary - Overview 112
PCIe Performance Overview Tab 112
Configuring and Computing Offline Performance Summary 114
Before you Start 114
Computing Offline Performance Summary 114
Saving the Computed Performance Summary Data 115
Interpreting the Performance Summary Results 117
Categories and Performance Statistics panes 117
Charts pane 118
Navigating Through the Performance Summary Results 120
Navigating Through a Chart 120
Navigating Between Performance Statistics and Associated PCIe Data
120
Customizing Charts 125
Changing the Sampling Rate 125
Changing the Size of Charts 125
Changing the Chart Display 126
Zooming In/Out Charts 127
Reordering Charts 129
13 Glossary
Index
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U4301A PCIe Gen3 Analyzer
User Guide
1
Hardware and Software Installation
The U4301A PCIe Gen3 analyzer is a module installed in an Agilent Digital
Test Console chassis (for example, the U4002A portable 2- slot chassis) or
Agilent AXIe chassis (for example, the M9502A 2- slot chassis).
The Agilent chassis is connected to a controller PC via a PCI Express
interface and cable.
The controller PC runs the Agilent Logic Analyzer application software
which lets you set up the U4301A PCIe Gen3 analyzer, specify triggers and
other data capture options, capture data, and analyze the captured data
using Packet Viewer/Protocol Viewer windows.
See the
"Agilent Digital Test Console Installation Guide" for
information on:
• Installing the U4301A PCIe Gen3 analyzer blade into a Digital Test
Console chassis.
• Connecting the Digital Test Console chassis to a controller PC via the
PCI Express Gen1 x4 interface.
• Installing the Agilent Logic Analyzer software on the controller PC.
See the
“Agilent AXIe based Logic Analysis and Protocol Test Modules
Installation Guide” for information on:
• Installing the U4301A PCIe Gen3 analyzer module into an Agilent AXIe
chassis.
• Connecting the AXIe chassis to a controller PC via the PCI Express
interface.
• Installing the Agilent Logic Analyzer software on the controller PC.
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Hardware and Software Installation
U4301A PCIe Gen3 Analyzer User Guide
U4301A PCIe Gen3 Analyzer
User Guide
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Probing Options for PCIe Gen3
The currently available options for probing a PCIe Gen3 device under test
(DUT) are:
• U4321A solid slot interposer
• U4322A midbus 3.0 probe
• U4324A PCIe Gen3 Flying Lead probe
Details about these two probing options (and other PCIe Gen3 tools) can
be found in the
"PCI Express Gen3 Hardware and Probing Guide".
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14
Probing Options for PCIe Gen3
U4301A PCIe Gen3 Analyzer User Guide
U4301A PCIe Gen3 Analyzer
User Guide
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Specifying the Connection Setup
Once you have connected the U4301A module, probing hardware, and DUT
in the required configuration based on your probing requirements, the
next step is to configure the connection setup for the U4301A module in
the Agilent Logic Analyzer application. You use the Connection Setup tab
of the analyzer's Setup dialog to configure the connection setup.
The connection setup details that you specify in this tab tells the Logic
Analyzer software how the U4301A module is connected to the DUT in
terms such as the probing option used, the direction of data capture
(upstream, downstream, or bidirectional), and the link width needed. For
instance, if you have connected the U4301A module hardware to the DUT
using the U4321A Solid Slot Interposer card in a x8 bidirectional setup,
then you need to select the U4321 Slot Interposer Both Dir x8 as the
Footprint option, 1 Bidirectional upto x8 as the Link type, and x8 as the
Link Width in the Connection Setup tab to reflect the hardware setup that
you have configured.
NOTE
• For details on how to set up the hardware and probing connections between
the U4301A module and DUT, refer to PCI Express Gen3 Hardware and Probing
Guide.
• For details on how to set up the chassis, U4301A module, and host PC, refer to
the AXIe based Logic Analysis and Protocol Test Modules Installation Guide.
These guides are installed with the Logic Analyzer software and can also
be downloaded from www.agilent.com.
Probing options
While specifying the connection setup, one of the key requirements is to
select the probing option that you have used with the U4301A module to
probe the DUT and the data capture direction in which you have
configured the hardware setup.
Broadly, there are the following four probing options available with the
U4301A module:
• U4321A Solid Slot Interposer card
• U4322A Soft Touch Midbus 3.0 probe
• U4324A PCIe Gen3 Flying Lead probe
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3
Specifying the Connection Setup
• PCIe Gen2 probes with the U4317A adapter. This adapter is used for
conversion between the PCIe Gen2 probes and U4301A PCIe Gen3
Analyzer module. The PCIe Gen2 probes supported are:
• N5315A Solid Slot Interposer for PCIe Gen2
• N4241A straight, N4242A swizzled, and N4243A split cable Soft
Touch Midbus 2.0 probe for PCIe Gen2
• N5328A Half Size Midbus probe
• N4241F/Z Flying Lead probe for PCIe Gen2
For each of the above four probing types, different options are available in
the Connection Setup tab reflecting the data direction (upstream,
downstream, or bidirectional). Upstream is the data direction towards the
root complex. Downstream is the data direction away from the root
complex. Based on your probing setup and the data capture direction in
which you have configured the hardware setup, you need to select an
appropriate probing option in the Connection Setup tab.
U4321A Solid Slot Interposer Card
When used with a U4321A solid slot interposer card, one U4301A module
can probe in the upstream (x1- x16), downstream (x1- x16), or bidirectional
(x1- x8) way.
If you need to probe in both upstream as well downstream directions with
a x16 link width, you need two U4301A Analyzer modules and a U4321A
SSI card. To reflect such a hardware setup in the Connection Setup tab of
the Logic Analyzer application, you need to select U4321A Slot Interposer
Upstream as the probing option for one of the U4301A modules and
U4321A Slot Interposer Downstream as the probing option for the other
U4301A module.
if you have connected the U4301A module hardware to the DUT using the
U4321A Solid Slot Interposer card in a x8 bidirectional setup, then you
need to select the U4321 Slot Interposer Both Dir x8 as the probing
option.
U4322A Soft Touch Midbus 3.0 probe
The U4322A midbus 3.0 probes require footprints to be designed into the
device under test. Each probe requires its own footprint, and there are
basically two variations:
• Bidirectional — where half the footprint pins are for the upstream data
and the other half are for the downstream data.
• Unidirectional — where all the pins on the footprint are for the data
going in the same direction.
Reversed refers to optional lane reversal which is supported for upstream
ports.
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Specifying the Connection Setup
3
Based on how you have designed the footprint for the probe, you need to
select an appropriate probing option in the Connection Setup tab. For
instance, if you have configured a x4 bidirectional setup using a U4322A
midbus probe, then you need to select U4322A Bidirectional Full as the
Footprint, 1 Bidirectional upto x8 as the Link type, and x4 as the Link
Width in the Connection Setup tab.
U4324A PCIe Gen 3 Flying Lead probe
When used with a U4324A Flying Lead probe, one U4301A module can
probe in the upstream (x1- x16), downstream (x1- x16), or bidirectional
(x1- x8) way. For x1- x8 bidirectional link type, you can use the U4324A
Flying Lead probes in a straight or a swizzled configuration.
If you need to probe in both upstream as well downstream directions with
a x16 link width, you need two U4301A Analyzer modules and eight
U4324A Flying Lead probes. To reflect such a hardware setup in the
Connection Setup tab of the Logic Analyzer application, you need to select
the U4324A Flying Lead Probe as the probing option and Unidirectional as
the link type for both the U4301A modules.
If you have connected the U4324A Flying Lead probes in a x1 to x8
bidirectional straight setup, then you need to select the U4324A Flying
Lead Probe as the probing option and Bidirectional as the link type.
If you have set up a swizzled x1 to x8 bidirectional configuration using the
U4324A Flying Lead probes, then you need to select the U4324A Flying
Lead Probe Bi Swizzled as the probing option and Bidirectional as the link
type.
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3
Specifying the Connection Setup
To specify the connection setup
1 In the Agilent Logic Analyzer application's Overview window, from the
PCIe analyzer module's drop- down menu, select Setup>Setup....
2 From the Footprint listbox, select the type of probing that you have set
up between the U4301A Analyzer module and DUT. For each of the
supported four probing types, different probing options are available in
the Footprints listbox based on the data direction (upstream,
downstream, or bidirectional). Based on your probing setup and the link
type needed, select an appropriate probing option from the Footprint
listbox. Refer to the "Probing options" on page 15 to know more about
these options.
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Specifying the Connection Setup
3
For more information on probing setups, click Connection diagram... or
refer to the
"PCI Express Gen3 Hardware and Probing Guide".
If you have installed multiple U4301A modules in the chassis, all these
modules are listed in the Module section of the tab. You need to select
the probing option individually for these modules.
3 Specify the link type.
U4301A PCIe Gen3 Analyzer User Guide
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Specifying the Connection Setup
The Link Type refers to the type of link that you want to create
between the U4301A module and DUT. You can select the 1
Unidirectional up to x16 link type if you want the U4301A module to
probe and capture data in only one direction (upstream or
downstream). In the Unidirectional link type, the U4301A module can
support a unidirectional link with upto 16 channels in the same
direction. You can select the 1 Bidirectional up to x8 link type if you
want the same U4301A module to probe and capture data in both
directions (upstream as well as downstream). In the bidirectional link
type, the U4301A module can support one bidirectional link with upto
eight channels for each direction. When you select the bidirectional link
type, two sub- links are created for the two directions. You can set the
link attributes such as clock source, master lane, and lane ordering
separately for these two sub- links. These attributes are available in the
Link Naming and Lane Setup section.
The following screen displays the sub- links of a x8 bidirectional link.
These sub- links have been renamed on the basis of the direction these
represent.
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U4301A PCIe Gen3 Analyzer User Guide
Specifying the Connection Setup
3
If you have installed multiple U4301A modules in the chassis, all these
modules are listed in the Module section of the tab. You need to select
the link type individually for these modules.
4 Select the link width.
Select the link width that matches the negotiated link width of
transmitter and receiver.
If you select the Link Type as 1 Bidirectional upto x8, then you can
select the Link Width from x1 to x8. The x16 option is disabled in this
case because a U4301A Analyzer module can probe and capture data in
both directions with upto eight channels in each direction.
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Specifying the Connection Setup
5 Verify the connection:
a Click Connection diagram....
b Use the Connection Diagram dialog to verify that your connection
setup specification matches the actual device under test connection.
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Specifying the Connection Setup
3
c Close the Connection Diagram dialog.
6 Select the clock source:
U4301A PCIe Gen3 Analyzer User Guide
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Specifying the Connection Setup
• Internal — selects an internal clock source. You should select Internal
if the data rate is in the range of 2.5 Gbps or 5 Gbps +/- 50 ppm.
Note that there is no input clock in this mode.
• External 1/2/3/4 — selects an external clock source. You should select
External if the device under test uses SSC or the data rate is in the
range of 2.5 Gbps +/- 300 ppm (+0% / - 0.5% if using SSC). The clock
rate for external mode should be between 100 MHz +/- 300 ppm (+0%
/ - 0.5% if using SSC).
Some important points about external reference clock selection
If you plan to use an external clock source, then you must ensure
that the reference clock from the DUT is available when you:
• select External as the Clock Source in the Setup dialog and
apply the selection by clicking Apply or OK.
• or load a configuration file that specifies the use of the external
clock source.
If the reference clock from the DUT is not available to Analyzer
when you apply the external clock source selection, the Analyzer’s
internal PLL may not be able to attain the initial lock with the
DUT’s reference clock resulting in an erratic behavior. Just making
the DUT’s reference clock available at this point does not establish
the lock with the reference clock. In such a situation, you can
re- establish the lock with the DUT’s reference clock by performing
the following steps:
i
Ensure that the reference clock of the DUT is available.
ii Then select Internal as the Clock Source in the Setup dialog and
click Apply.
iii Finally, select External as the Clock Source in the Setup dialog
and click Apply.
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Specifying the Connection Setup
Once the initial lock is established, it is maintained. You need not
re- establish the lock with the reference clock on subsequent
availability/unavailability of the reference clock in the event of DUT
power off/on or on any further changes to the Setup dialog except
for Clock Source or Link Type.
7 Select the master lane. You can select any lane as the master lane from
the lanes displayed in the Master Lane listbox. The lanes are displayed
as per the selected link width. The lane that you select as the master
lane is considered the lane for capturing the ordered sets.
8 Specify whether lane reversal is on or off.
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Specifying the Connection Setup
9 Specify any lane polarity inversion:
a Click Auto or Manual to toggle between the types of polarity inversion
specification.
When Auto is selected, the polarity of the lanes is set automatically
during the initial link training.
b When manual selection is chosen, select the lanes that are inverted.
10 The Lane Ordering option lets you perform the ordering of the physical
lanes of the link with the logical lanes. You can either retain the
Default lane ordering which means Lane 0 of the link maps to logical
Lane 0 and so on. If you want to map Lane 0 of the link to some other
Lane, then select Custom option from Lane Ordering and click Specify
to display the Custom Lane Ordering dialog box. In this dialog box,
select the lane with which you want to map Lane 0. The number of
lanes displayed for lane ordering depend on the selected link width. For
example, if the link width is selected as x4, then the Lane 0, 1, 2, and
3 are available for lane ordering.
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Specifying the Connection Setup
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U4301A PCIe Gen3 Analyzer
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Setting the Capture Options
The Capture Setup tab in the PCIe Gen3 analyzer's Setup dialog lets you
set basic capture options.
1 In the Agilent Logic Analyzer application's Overview window, from the
PCIe Gen3 analyzer module's drop- down menu, select Setup>Setup....
2 Click the Capture Setup tab.
3 In the Capture Setup tab, select the appropriate options.
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Setting the Capture Options
Capture
Memory Depth
Lets you select the trace memory depth. Deeper traces capture more activity
but take longer to save and process.
Capture Link
Speed
Lets you specify the link speed of the data to be captured:
• Gen 1 — select this when capturing data on 2.5 Gbps links.
• Gen 2 — select this when capturing data on 5 Gbps links.
• Gen 3 — select this when capturing data on 8 Gbps links.
• Auto – select this option when testing link speed switching scenarios.
On selecting this option, analyzer automatically detects the link speed
change and accordingly starts capturing data based on the changed link
speed. The Auto option also has a drop-down listbox displayed with it.
From this listbox, you can select either Gen1 or Gen2. If you select Gen1
from this listbox, then analyzer prioritizes and captures the Gen 1
ordered sets while switching speed from Gen 3. If you select Gen2 from
this listbox, then analyzer prioritizes and captures the Gen 2 ordered
sets while switching speed from Gen 3.
Based on the selected link speed, the speed LED of the Analyzer pod on
which the logical Lane 0 is present will glow. The following color coding is
used to interpret the status of the speed LED.
• Off - This means that the system is not configured.
• Red - This means that the link speed is not detected or not configured.
• Yellow - This means that the link speed is 2.5 Gb/s.
• Green - This means that the link speed is 5 Gb/s.
• Blue - This means that the link speed is 8 Gb/s.
If you selected a fixed speed (Gen1, Gen2, or Gen3), then the speed LED will
glow according to the selected speed. If you selected the Auto speed option,
then the speed LED will glow according to the detected speed.
U4301A PCIe Gen3 Analyzer User Guide
Setting the Capture Options
Descrambler
(Gen1 / Gen2)
Tells the analyzer whether the descrambler algorithm is necessary:
• Enabled — activates the descrambler algorithm. This algorithm
generates the descrambled packet stream from an incoming scrambled
packet stream.
• Disabled — deactivates the descrambler algorithm. Select this option
when the DUT is transmitting the non-scrambled data.
Garbage data is displayed if this is set incorrectly.
Capture Mode
Lets you choose between two capture modes:
• Normal — captures data only when all the configured lanes are out of
the Loss of Sync (LOS) condition, that is, each lane has valid data. In this
mode, channel bonding occurs when the analyzer encounters the first
SKIP ordered set after exiting from the L0s/L1/L2/recover.speed
condition.
• Raw — captures data by each lane. This means, if only one lane is out
of the LOS condition, its data is captured in the trace. In this mode,
channel bonding may not exist at all. The Raw mode gives you data
visibility even when there are significant PHY layer issues.
L0s Testing
Lets you select whether or not the U4301A module will capture packets in the
L0s state.
• Enabled - When you enable the L0s Testing option, the U4301A module
captures packets in the L0s state and the power management testing
capabilities are enabled and enhanced in terms of :
• improvement in locking time
• faster data capture while coming out of the electrical idle
• Disabled - When you disable the L0s Testing option, the power
management testing capabilities are available but not enhanced.
NOTE
4
When testing L0s/L1, ensure that you:
- set manual lane polarity.
- select a fixed capture link speed instead of the Auto speed.
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Setting the Capture Options
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Tuning the Analyzer for a Specific DUT
PCIe Gen3 Tuning Overview 34
Preparing the U4301A Module and DUT for Tuning 37
Creating a Physical Layer Tuning File 38
Loading a Tuning File in the Logic and Protocol Analyzer GUI 44
Tuning a Bidirectional Setup 46
Fine Tuning a .ptu File 47
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PCIe Gen3 Tuning Overview
What is Tuning
Tuning is the process of adjusting Agilent's probing system to remove the
effects of different driving silicon, termination silicon (or other
termination schemes), imperfect transmission paths, and the fact that the
probes may not be in the "ideal" location for receiving a high- speed signal
(that is, at the end of the transmission path).
Furthermore, a PCIe Gen3 system will negotiate its own TX Linear
Equalization, and you would like to have the largest eye possible. Tuning
does not affect either the transmitter or the receiver; it is used only to
increase the eye as seen by the U4301 Analyzer module. This process
involves getting the system/device- under- test to a stable PCIe Gen3
transmission state which the analyzer then optimizes its own equalizations
settings for.
How Tuning Works
For tuning, you:
• either use a predefined physical layer tuning (.ptu) file with default
tuning values appropriate for your probing and connection setup.
• or create a physical layer tuning (.ptu) file..
The .ptu file contains the information necessary to adjust the probing
system for a specific device- under- test (DUT). At the 8 Gbps speed, you
then need to load this .ptu file into the U4301 Analyzer module’s software
to have the best possible eye at the Analyzer.
It is recommended that you first use a predefined .ptu file with default
tuning values. If the default tuning values do not provide robust and clean
tracing results, you should consider creating your own .ptu file.
From this release of the Agilent PCIe Gen3 software, you can create or
fine tune a .ptu file using the Agilent Logic and Protocol Analyzer GUI.
When to Perform Tuning
You should only perform tuning when all of the following conditions are
met:
• Poor trace quality which may include red packets, triggers on “Loss of
Sync” or “Channel Bonding”.
• No Recovery cycles (that is, cannot Trigger on “Any TS”) on the target.
• When no existing .ptu files are able to provide robust tracing.
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Default and User Defined .ptu Files
A set of default tuning (.ptu) files are provided with the Agilent Logic and
Protocol Analyzer software. These tuning files contain the probe defaults
to compensate for the signal impairments associated with the probe. These
files are named on the basis of the probe type for which these are created.
Based on the probe type you are using, one of these files is used and if
the trace quality is clean, you do not need to tune further by creating your
own .ptu file. These default .ptu files work fine and support robust tracing
in situations where the targets have margin. The following screen displays
the location of these default ptu files.
However, if the default .ptu file does not serve the purpose and you find
the trace quality to be poor, you can create your own .ptu file with your
specific parameters and use it in the Logic and Protocol Analyzer GUI to
perform tuning. You can create a .ptu file using the Logic and Protocol
Analyzer GUI.
Tuning - Broad steps
The following picture illustrates the broad steps involved in the tuning
flow.
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All these steps are described in detail in the topics that follow.
Tuning Method
While creating a .ptu file using the Logic and Protocol Analyzer GUI, the
AnalogTune tuning method is used. This method minimizes the deviations
of the observed Vertical Eye characteristics versus the desired Vertical Eye
characteristics. From the DUT participation perspective, this method only
requires that the DUT must not have transitions to or from Electrical Idle
at 8Gbps.
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Preparing the U4301A Module and DUT for Tuning
Perform these steps to prepare the setup for tuning:
1 Connect the U4301A Analyzer module to the DUT. Refer to the PCI
Express Gen3 Hardware and Probing Guide to know how to connect
Analyzer to the DUT based on your specific probing situation.
The following Agilent probing options are supported for use with the
Analyzer module.
• U4321A solid slot interposer.
Note that there are four connections on this interposer; the upper
two are for the "To Upstream" path (assuming that the card plugged
into the top connector of the interposer is the downstream side). The
lower two connectors are for the "to Downstream" direction.
• U4322A soft touch midbus 3.0 probe.
Note that there are several supported footprints that define what
lanes are at specific physical connections.
• U4324A PCIe Gen3 flying lead probe.
Each of these probes provides support for probing one to four
channels of a PCIe link making it a total of 16 channels probing
support for a set of four probes.
2 If the Resource Bus connector is connecting two Analyzer modules
together (the connector at the left of the modules), remove the Resource
Bus Connector and do the tuning of one module at a time.
After you have tuned, you can reconnect the Resource Bus Connector
without affecting the tuning.
3 Your DUT must enter L0 at Gen3 speed (8 Gbps).
4 The DUT must not transition to or from Electrical Idle at 8Gbps and its
TXEQ should have stabilized before tuning. If the DUT is experiencing
Recovery cycles, it is likely that it will change its TXEQ to achieve
stability.
5 Ensure that the connection settings such as the number of lanes in use
and the lanes inverted by the transmitter are correctly set up in the
Connection Setup tab of the U4301A module’s Setup dialog box before
starting the tuning. These settings are used in the tuning process and
incorrect settings can result in incorrect tuning.
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Creating a Physical Layer Tuning File
After you have prepared your system for tuning and configured the
connection setup for the U4301A module, you can create a physical layer
tuning (.ptu) file. This file stores the information about the test setup
(lane inversions, number of lanes, etc) and the tuning parameters that
were discovered during tuning. You use this file in the PCIe Analyzer
setup in the Logic and Protocol Analyzer GUI to tune the system.
To create a physical layer tuning file
Perform these steps on the host PC that is physically connected to the
U4301 Analyzer module.
1 Exit the Agilent Logic and Protocol Analyzer application if it is
currently active.
2 Start the Agilent Logic and Protocol Analyzer application.
This is done to ensure that all the default settings in the analyzer
software are used.
3 In the Logic and Protocol Analyzer GUI’s Overview window, select
Setup>Setup.... from the PCIe analyzer module's drop- down menu to
access its Setup dialog box.
4 Click the Phy Tuning tab of the Setup dialog box.
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5 The left pane of the Phy Tuning tab displays a list of the currently
available PCIe Analyzer modules. From this list, select the module
which you want to tune.
6 Select the Use Specified Tuning File option from the Tuning File
Selection section.
7 Click the New Tune... button to open the Tuning File Creation dialog
box.
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8 Select one of the following two options from the Tuning Mode listbox.
• Standard Tune - This option performs an Analog Tune followed by a
fine tune. In this option, the number of iterations for a tuning test
completion are more than the number of iterations in the Quick
Tune option. Standard Tune, therefore takes more time than Quick
Tune.
• Quick Tune - This option also performs an Analog Tune followed by
a fine tune. However, the number of iterations for a test are lesser
making this option suitable for performing tuning quickly.
NOTE
The third option - Fine Tune Previous Results in the Tuning Mode listbox is
meant for fine tuning a previously created .ptu file.
icon displayed with the Output PTU File field to browse
and specify the name and location for the .ptu file.
9 Click the
10 Click Perform Tune.
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The tuning process starts. The Tuning Log section displays the results
of the tuning process run operation. If the tuning process completes
successfully, the specified .ptu file gets created. A tuning log file is also
created with the same name and location as the tuning file.
11 Click OK to close the Tuning File Creation dialog box.
The newly created tuning file is now loaded for use in the Phy Tuning tab.
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LEDs display during BER Based Tuning
The U4301 Analyzer module has 16 channel LEDs and four speed LEDs.
The following table lists the interpretation of these LEDs display during
BER- based tuning.
Channel LEDs
Green
Indicates no bit errors on that lane.
Yellow
Indicates loss of sync or “OK”/”ERROR” is toggling quickly. You get
“shades of yellow”, usually, when there are frequent bit errors.
Red
Indicates bit error on that lane.
Blinking Red / Off
Indicates input FIFO overflow.
Speed LEDs
Off
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Indicates an Idle state.
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Channel LEDs
Blue
Indicates that the data is being taken.
For a general description of the channel and speed LEDs, refer to the PCI
Express Gen3 Hardware and Probing guide. You can download this guide
from www.agilent.com.
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Loading a Tuning File in the Logic and Protocol Analyzer GUI
The Phy Tuning tab lets you load a user- created physical tuning (.ptu) file
or the default tuning values from a predefined tuning file.
To load a specified tuning file or default tuning values
1 In the Agilent Logic and Protocol Analyzer application's Overview
window, select Setup>Setup... from the PCIe Gen3 analyzer module's
drop- down menu.
2 Click the Phy Tuning tab.
3 The left pane of the Phy Tuning tab displays a list of the currently
available PCIe Analyzer modules. From this list, select the module for
which you want to select a tuning file.
4 To load default tuning values:
a Select the Use Default Tuning Values option from the Tuning File Selection
section. On selecting this option, the software automatically uses the
default tuning values from the predefined .ptu file applicable for
your probing and connection setup. This is the default and
recommended option for an initial run. If the default tuning values
do not produce robust and clean tracing results, you should load a
user- specified PTU file for tuning (described in the next step).
5 To load a user- specified tuning file:
a Select the Use Specified Tuning File option to load a user- specified
tuning file.
icon displayed with the Select PCI Express PHY Tuning
File (.ptu) to use section to browse and navigate to the tuning file that
you want to load.
b Click the
c Select the tuning file and click Open in the Open dialog box.
The tuning file is now loaded for use.
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6 Click Apply or OK.
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Tuning a Bidirectional Setup
A single U4301A module can support a x1 to x8 bidirectional
configuration. To tune a U4301A module in a x1 to x8 bidirectional
configuration, you just need to tune once. A single tuning file is used to
perform tuning for both directions.
However, for a x16 bidirectional configuration, you need two U4301A
modules. Therefore, for such a configuration, you need two separate tuning
files, one for each module. Each module is tuned separately using its
tuning file.
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Fine Tuning a .ptu File
If the .ptu file that you created does not produce robust and clean tracing,
then you can fine tune the .ptu file to get the desired results from tuning.
Fine Tuning Flow
The following picture illustrates the fine tuning flow.
To fine tune a .ptu file
1 In the Setup dialog box of the U4301A Analyzer module, click the Phy
Tuning tab.
2 Ensure that the Use Specified Tuning File option is selected and the .ptu
file that you want to fine tune is selected in the Select PCI Express Phy
Tuning File (.ptu) to use section. If no .ptu file is selected, then the default
predefined .ptu file applicable for your probe and connection setup is
used for fine tuning.
3 Click New Tune....
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4 Select Fine Tune Previous Results from the Tuning Method listbox in the
Tuning File Creation dialog box.
icon displayed with the Output PTU File field to browse
and specify the path and location of the tuning file that will be
generated after the fine tuning process.
5 Click the
6 Click Perform Tune.
The fine tuning process starts and the fine tuning progress is displayed
with a progress bar.
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7 When fine tuning completes, click OK to close the Tuning File Creation
dialog box.
On successful completion, the fine- tuned PTU file is created at the
specified location along with a tuning log with the same name as the
fine- tuned PTU file.
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Manually Adjusting the Equalizing
Snoop Probe (ESP) Settings
The Probe Setup tab in the PCIe Gen3 analyzer's Setup dialog lets you
manually adjust the equalizing snoop probe (ESP) settings.
NOTE
To enable the Probe Setup tab in the PCIe Gen3 analyzer's Setup dialog, you must check the
Enable Advanced Probe Settings (ASP) option in the Options dialog. See "Options Dialog"
(in the online help).
1 In the Agilent Logic Analyzer application's Overview window, from the
PCIe Gen3 analyzer module's drop- down menu, select Setup>Setup....
2 Click the Probe Setup tab.
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Manually Adjusting the Equalizing Snoop Probe (ESP) Settings
3 In the Probe Setup tab, select the appropriate options.
For each lane in the links, you can adjust the boost and bandwith
settings. Click Reset -> to restore the original settings.
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Setting Up Triggers
Setting Up Simple Triggers 54
Setting Up Advanced Triggers 57
Setting General Trigger Options 60
The U4301A PCIe Gen3 analyzer lets you set up triggers (events that
specify when to capture a trace) with simple or advanced dialogs.
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Setting Up Triggers
Setting Up Simple Triggers
1 In the Agilent Logic Analyzer application's Overview window, from the
PCIe analyzer module's drop- down menu, select Setup>Trigger....
2 In the Trigger dialog:
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a Select the Simple Trigger option.
b Select the Trigger on Packets or Ordered Sets Trigger Mode option.
(The Trigger when Stop button is pressed Trigger Mode option can be
useful, for example, to see the events that lead up to a stop, halt,
etc.)
c From the Global Filter listbox, select the following two options:
i
Select whether you want to enable or disable the storage of all
types of ordered sets and packets including the logical idles in the
capture memory.
ii If you disable the storage of everything including the logical idles,
then this drop- down list is activated. From this list, you can select
the types of ordered sets and TLP/DLLP packets that you want to
filter out from getting stored in analyzer memory. The options
selected from this list act as the storage qualifiers. The selected
types of ordered sets and packets are acquired but are not
qualified to be stored in the analyzer's memory. If you select the
Filter Everything option from this list, then none of the acquired
samples will qualify to be stored in the analyzer memory. As a
result, analyzer will keep running and you need to stop it
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Setting Up Triggers
manually because analyzer keeps acquiring data until the memory
depth is full. If you do not select any option from the list, then
the filtering is considered Off and all the acquired data is stored
in memory when the trigger condition is met.
c Drag events you would like to trigger on from the left- side pane to
the Trigger on any of these events box.
The left- side pane contains an event hierarchy that can be expanded
or collapsed.
To edit events in the trigger box, click the underlined event name.
To remove events from the trigger box, click the "X" to the left of the
event name.
d Drag events you'd like to exclude from the trigger to the While ignoring
any of these events box.
e Click Apply or OK.
See Also
• "To select which links the trigger is for" on page 60
• "To set the trigger position" on page 60
• "To save/recall favorite triggers" on page 61
• "To clear the current trigger" on page 61
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Setting Up Advanced Triggers
1 In the Agilent Logic Analyzer application's Overview window, from the
PCIe analyzer module's drop- down menu, select Setup>Trigger....
2 In the Trigger dialog:
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a Select the Advanced Trigger option.
b From the Global Filter listbox, select the following two options:
i
Select whether you want to enable or disable the storage of all
types of ordered sets and packets including the logical idles in the
capture memory.
ii If you disable the storage of everything including the logical idles,
then this drop- down list is activated. From this list, you can select
the types of ordered sets and TLP/DLLP packets that you want to
filter out from getting stored in analyzer memory. The options
selected from this list act as the storage qualifiers. The selected
types of ordered sets and packets are acquired but are not
qualified to be stored in the analyzer's memory. If you select the
Filter Everything option from this list, then none of the acquired
samples will qualify to be stored in the analyzer memory. As a
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result, analyzer will keep running and you need to stop it
manually because analyzer keeps acquiring data until the memory
depth is full. If you do not select any option from the list, then
the filtering is considered Off and all the acquired data is stored
in memory when the trigger condition is met.
c Drag events you'd like to trigger on from the left- side pane to
sequence steps in the Select the Trigger(s) to use box.
The left- side pane contains an event hierarchy that can be expanded
or collapsed. (This is the same event hierarchy displayed in the
simple trigger dialog.)
To edit events in the trigger box, click the event button.
To remove events from the trigger box, click the sequence step
buttons.
d In the Select the Trigger(s) to use box, click buttons, make drop- down
selections, and enter values in fields to edit the steps in the trigger
sequence:
• The Step buttons let you insert or delete steps.
• The If/Else if buttons let you insert or delete "if" clauses.
• The event chevron buttons let you insert, delete, or logically group
(or negate) events.
• The direction drop- down listbox is displayed if you configured the
U4301A module's connection setup as a bidirectional setup. It lets
you select the direction (upstream or downstream) applicable for
the trigger sequence. For a unidirectional data capture setup, this
listbox is not displayed.
• The action chevron buttons let you insert or delete actions.
• Use the Comment fields to document your advanced triggers.
e Click Apply or OK.
See Also
• "To select which links the trigger is for" on page 60
• "To set the trigger position" on page 60
• "To save/recall favorite triggers" on page 61
• "To clear the current trigger" on page 61
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Setting General Trigger Options
The top part of the Trigger dialog contains general options that apply to
both simple and advanced triggers.
• "To select which links the trigger is for" on page 60
• "To set the trigger position" on page 60
• "To save/recall favorite triggers" on page 61
• "To clear the current trigger" on page 61
To select which links the trigger is for
The top of the Trigger dialog has tabs that let you set up separate triggers
for different links. You can add tabs for separate triggers and apply them
to the links that are set up in the Connection Setup dialog (see Chapter 3,
“Specifying the Connection Setup,” starting on page 15).
To set the trigger position
The top of the Trigger dialog has a slider for setting the trigger position
within the capture memory.
Note that the pre- trigger portion of the capture memory is filled before
searching for the trigger.
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To save/recall favorite triggers
The top of the Trigger dialog has a Favorite Triggers drop- down menu for
saving trigger setups and recalling previously saved trigger setups.
Do not confuse these "favorite" triggers with the favorites that appear in
the left- side pane (which are added using the Event Editor dialog).
To clear the current trigger
The top of the Trigger dialog has a Clear button for erasing the current
trigger setup and restoring the default trigger setup.
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Running/Stopping Captures
Running and stopping the U4301A PCIe Gen3 analyzer is just like running
and stopping any other analyzer. See "Running/Stopping Measurements" (in
the online help).
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Viewing PCIe Gen3 Packets
You can view the data captured by the U4301A PCIe Gen3 analyzer using
the Protocol Viewer window. See “Analyzing Packet Data” (in the Agilent
Logic and Protocol Analyzer online help). A Protocol Viewer is
automatically added for a U4301A PCIe Gen3 analyzer module in the Logic
Analyzer GUI.
The Protocol Viewer window displays the summarized and detailed packet
information at the same time within two panes. The upper pane lists the
packets. On selecting a packet, the details of that packet are displayed in
the lower pane.
The following screen displays a sample view of the captured PCIe data in
the Protocol Viewer window. In this screen, the Lanes tab of the Protocol
Viewer window is displayed. The Lanes viewer displays not just the
selected packet data across lanes but also the post packet data
represented by colors matching the selected packet color in the upper
pane.
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Viewing the Captured PCIe Traffic Statistics
You can use the Traffic Overview tab in the lower pane of Protocol
Viewer to get an overview of the PCIe traffic that is displayed in the
upper pane of Protocol Viewer. This tab provides a count of various PCIe
packet types captured and displayed in the upper pane. The count of
packets is categorized on the basis of packet types.
For each packet type, the count of packets is further segregated based on
the direction (upstream or downstream). The following screen displays the
traffic statistics in the lower pane. Notice that for each packet type, the
count of packets is displayed for upstream as well as downstream
direction along with a sum of packets in both directions.
You can specify the data range based on which the traffic statistics get
computed in the Traffic Overview tab. For instance, you might want to
view the traffic statistics only for the PCIe packets between the markers
M1 and M2. In such a situation, you can select M1 as the start point and
M2 as the end point in the Data Range group box and then click
Compute. Then Protocol Viewer displays the traffic statistics of only the
packets that fall in the specified data range and not for all the PCIe
packets displayed in the upper pane. The following screen displays the
traffic statistics for the data range starting from M1 and ending at M2
markers.
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The Compute button is disabled when U4301A PCIe Analyzer module is
capturing data. It becomes enabled when the capture has stopped.
Navigating through the captured PCIe packets
From the displayed traffic overview statistics, you can select a particular
packet type and then navigate through the packets displayed in the upper
pane for that packet type. For instance, there are total 1782 packets of the
type Ack and you want to view the details of the 45th Ack packet out of
these 1782 Ack packets. To go directly to the 45th Ack packet out of the
total Ack packets, you can select this packet type in the Traffic Overview
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results and then type 45 in the Navigation text box and click Go. This
takes you directly to the 45th Ack packet in the upper pane of Protocol
Viewer.
You can also navigate through the PCIe packets of a particular direction
(upstream or downstream). To do this, select a particular packet type in
the displayed traffic statistics and then select the count column for the
required direction. Then specify the packet number in the Navigation text
box to reach directly to that packet.
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You can also select multiple packet types in the Traffic Overview tab by
clicking a packet type and then dragging the mouse over to the other
packet types that you want to select. When you select multiple packet
types, the Navigation section displays the total packet count for all the
selected packet types.
Viewing Errored Packets Statistics
If you want to include the count of errored packets in the traffic overview,
then select the Include Errors check box. You can then click the Errors
option in the left panel of Traffic Overview tab. This displays the count of
errored packets categorized based on different error types and direction.
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Viewing LTSSM State Transitions
You can use the LTSSM Overview tab in the lower pane of Protocol
Viewer to get an overview of the LTSSM state transitions that occurred in
the PCIe data captured by U4301A module in a trace. This pane provides
an overview of the link training process by displaying a sequential list of
the LTSSM states and their transitions and the packets exchanged during
each state. You can use this information to verify the link training process
and find out reasons for any failure in this process.
To get detailed information on how to use Protocol Viewer’s LTSSM
Overview pane, refer to the chapter "Viewing LTSSM States and State
Transitions" on page 75.
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Viewing Offline Performance Summary
You can use the PCIe Performance Overview tab in the lower pane of
Protocol Viewer to perform post processing on the captured PCIe traffic
and generate an offline performance summary of bus utilization.
To get detailed information on how to use Protocol Viewer’s PCIe
Performance Overview pane, refer to the chapter "Viewing Offline
Performance Summary" on page 111.
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Viewing Decoded Transactions
You can use the Transaction Decode tab in the lower pane of Protocol
Viewer to compute and view transactions decoded from the captured PCIe
traffic.
To get detailed information on how to use Protocol Viewer’s Transaction
Decode pane, refer to the chapter "Viewing Decoded Transactions" on
page 85.
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Exporting Captured PCIe Data to a .csv File
You can export the captured PCIe packet information from the Protocol
Viewer window to a specified .csv file and use it later in other analysis
tools. You do this by clicking the
toolbar button in the Protocol Viewer
window. On clicking this toolbar button, the Protocol Export dialog box is
displayed in which you can specify the details of export such as the range
of packet data that you want to export and the delimiter that you want to
use to delimit the exported data in the specified .csv file.
For details on how to export data to a .csv file, click the Help button in
the Protocol Export dialog box.
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Viewing LTSSM States and State
Transitions
LTSSM Overview 76
Configuring and Computing LTSSM States 79
Viewing LTSSM States/Transitions 80
Interpreting LTSSM Overview Results 83
The U4301A PCIe Gen3 analyzer lets you view LTSSM states and their
transitions as detected in the data captured in a trace to help you test or
debug the DUT’s LTSSM functions. This chapter describes how you can
view these LTSSM states.
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LTSSM Overview
Link Training and Status State Machine (LTSSM) drives and controls the
link initialization and training process for a PCIe device to enable the
normal data exchange between the two PCIe devices over the link. LTSSM
operates at the physical layer level and transits through various states and
substates during link initialization, training, and management. During each
of these states, appropriate physical layer packets (training sequences) are
exchanged between the link partners to initialize, train, and manage the
link.
To begin communication with a PCIe device, the link training process must
complete successfully. This makes link training one of the most crucial
process in testing and validating a DUT. With so many states/substates
and training sequences exchange involved in link training, it can be a
challenging task to verify and debug this process.
The LTSSM Overview pane in the Protocol Viewer window of the Logic
Analyzer GUI helps you in verifying the link training process and finding
out reasons for any failure in this process. This pane provides an overview
of the link training process by displaying a sequential list of the LTSSM
states and their transitions and the packets exchanged during each state.
To display these states and transitions, it analyzes a user- specified data
range or the entire data captured in a trace and presents the list of
states/transitions from that trace.
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The LTSSM Overview pane can display LTSSM states and transitions for
both upstream as well as downstream link directions. However, this display
depends on how you configured the direction of data capture (upstream,
downstream, or bidirectional) in the Connection Setup tab of the Setup
dialog box of the U4301A module. For instance, if you configured a
bidirectional data capture using U4301A, then LTSSM states are displayed
for both directions.
Using the LTSSM Overview pane, you can view the LTSSM states and their
transitions during events such as:
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• Link initialization and configuration to bring the link to an operational
state.
• Link recovery or retraining in situations such as speed changes, power
management, or recovering from a link error.
• Downgrading or upgrading the link speed in response to a link speed
change request.
• Performing the Equalization procedure before reaching the Gen3 (8.0
GT/s) speed during the link training or retraining.
Prerequisites
Before you can view LTSSM states and transitions, you need to ensure
that:
• You have the appropriate node/server software license available and
installed for the LTSSM Overview feature.
• You have set up the U4301A analyzer module and captured the PCIe
data for the required direction(s).
• You have configured the LTSSM setup to get the data display in the
LTSSM overview pane according to your requirements. (Described in the
next section)
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Configuring and Computing LTSSM States
To view LTSSM states in the LTSSM Overview pane, you need to configure
the pane settings and initiate computation of the LTSSM states display
based on these settings.
1 Access the captured data along with the U4301A setup details in the
Logic Analyzer GUI.
2 Click the Protocol Viewer node connected to the U4301A module in the
Overview window of the Logic Analyzer GUI.
3 Click the LTSSM Overview tab in the lower pane of the Protocol
Viewer window.
4 Configure the LTSSM setup to get a display of LTSSM states as per your
requirements.
a To configure how the states are displayed in the LTSSM Overview’s
navigation pane, click Setup and then select the appropriate LTSSM
navigation mode - By Transitions or By States from the LTSSM
Setup dialog box. ‘By Transitions’ displays the LTSSM states
transitions in the results for navigating through the occurrences of
the state transition events in the analyzed data. ‘By States’ displays
the LTSSM states in the results for navigating through the
occurrences of the state entry events in the analyzed data.
b In the Data Range groupbox, specify the start and end range for the
captured data in the trace for which you want to display the LTSSM
states and transitions. Only the specified range of data is analyzed to
detect the LTSSM states. The default selections in the Data Range
group box ensure that the LTSSM states are displayed for the entire
trace. However, you can set markers in the packets listing in the
upper pane and then specify the data range using these markers so
that LTSSM states are displayed only for that specific range of
packets.
5 Click the Compute button displayed with the Data Range fields.
The LTSSM states are computed and displayed for the specified data
range and configured link direction.
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Viewing LTSSM States/Transitions
The screen below displays the results of a compute operation for LTSSM
states followed by a description of these results.
The LTSSM states results are displayed in the following two sections of the
pane as highlighted in the above screen.
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LTSSM States List Display
section
This section displays a list of the LTSSM states in the sequence in which these occurred in
the trace or the specified part of the trace. The states are grouped and listed for a link
direction. In the above screen, LTSSM states are displayed for both upstream and
downstream directions.
For each state in this list, the applicable link speed during the state is also displayed.
Clicking a speed in this list highlights the packet representing the transition to that speed in
the upper pane of the Protocol Viewer.
When you click a state in the list, the packet that is exchanged as the first packet for that
state occurrence is highlighted in the upper pane of the Protocol Viewer. This provides you a
quick start point for viewing and navigating through the packets exchanged during a
particular state.
Moving the mouse pointer to a state presents a tool tip with useful information about the
state such as the time tag for the state and the packet exchanged at the state change.
LTSSM States/Transitions
Navigation section
This section displays a list of the applicable LTSSM states or state transition names. The
display of states or transitions in this section depends on whether you selected By
Transitions or By States navigation mode in the LTSSM Setup dialog box. In the above
screen, the display in the navigation section is as per the By transitions mode.
For each of these states/transitions, the section displays the number of events representing
the number of occurrences of these states or transitions in the analyzed data. For instance,
in the above screen, the transition from Rcvr.Idle to L0 state occurred 8 times in each
upstream and downstream direction making the total occurrences of this transition 16.
Using this section, you can easily navigate through these occurrences of LTSSM states or
transitions and the packets exchanged during these occurrences.
NOTE
You need to recompute the LTSSM states display results if you want to change:
- the data range for which results are to be displayed.
- the LTSSM navigation mode for the navigation pane.
- the link direction for which results are to be displayed.
You can hide or display the LTSSM Overview pane using the
upper pane of the Protocol Viewer window.
toolbar button in the
Navigating Through the LTSSM States/Transitions Occurrences
You use the Navigation groupbox in the LTSSM Overview pane to navigate
through LTSSM states / transitions occurrences.
1 To navigate through the occurrences of a state for both the directions,
select the particular state / transition name in the navigation section.
To navigate through the occurrences of a state for a specific direction,
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select the number of events displayed for that direction in front of the
state / transition name in the navigation section.
2 Either type the number of occurrence to which you want to navigate in
the Navigation groupbox and click Go or click the + or - buttons in the
groupbox to sequentially move to next or previous occurrence of the
state/transition.
The specified occurrence of the selected state/transition is highlighted
in the state list display and the packet representing the state transition
is highlighted in the upper pane of the Protocol Viewer window. For
instance, in the following screen, the third occurrence of the transition
from L0 to Rcvr.RcvrLock is highlighted in the states list along with the
TS1 packet representing the beginning of the third occurrence of
Rcvr.RcvrLock state.
3 Click
toolbar button to navigate to the first packet of the first
occurrence of the selected state/transition.
4 Click
toolbar button to navigate to the packet representing the
transition to the last occurrence of the selected state/transition.
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Interpreting LTSSM Overview Results
Following are some important points about interpreting the states and
transitions displayed in the LTSSM Overview pane:
• Errored LTSSM states - If an LTSSM state is listed in red colored text,
it indicates an erroneous state transition. Following is an example of an
erroneous state transition from Detect to Config.LW.Accept. There
should have been a transition to the Polling state after Detect.
• The following background color coding is used to represent the three
speed in the speed column of the states listing.
• Yellow - Gen1 (2.5 Gbps)
• Green - Gen2 (5 Gbps)
• Blue - Gen3 (8 Gbps)
• The pane displays LTSSM states as detected from the trace. If some
events are not represented in the captured data in the trace, then these
events will not be part of the LTSSM state transitions list in the LTSSM
Overview pane.
• Except for the Configuration and Recovery states, the substates are not
displayed for any other state. For instance, the substates of Polling such
as Polling.Active, Polling.Compliance and Polling.Configuration are not
displayed. Only the Polling state is listed in the pane.
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Viewing Decoded Transactions
Transaction Decoding - Overview 86
Configuring and Computing Decoded Transactions 87
Interpreting and Navigating Through the Transaction Decode Results 95
Viewing NVMe Transactions 101
The U4301A Analyzer module can decode storage protocols over PCI
Express such as NVMe to display decoded transactions from the captured
PCIe data. This chapter describes how you can compute and view these
decoded transactions.

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Transaction Decoding - Overview
The Transaction Decode tab in the Protocol Viewer window allows you to
compute and view transactions decoded from the captured PCIe traffic.
The decoding and display of transactions is done as per the relevant
storage protocol specifications to help you easily correlate the decoded
data to the protocol specifications and evaluate DUT’s compliance to these
specifications.
Types of Protocols Supported
In this release, decoding of NVMe transactions is supported. More
protocols such as PCIe would be supported in the future releases of the
Logic and Protocol Analyzer software.
Transaction Decode Tab
You use the Transaction Decode tab displayed in the lower pane of the
Protocol Viewer to compute and view decoded transactions.
This tab consist of two panes. The left pane displays a list of transactions.
The right pane displays the number of occurrences of these transactions.
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Configuring and Computing Decoded Transactions
Before you Start
• You should have purchased and installed the appropriate U4301
Transaction Decoder license for computing decoded transactions.
On purchasing the license, you receive an entitlement certificate. Follow
the instructions in this certificate to install the license.
• Ensure that the data in the required direction(s) is already captured
and available in the Logic and Protocol Analyzer GUI for transaction
decoding. You may save the captured data in a Logic Analyzer
configuration (.ala) file and access this data offline for transaction
decoding.
Defining / Verifying the Device Setup
For decoding transactions, the Logic and Protocol Analyzer software
automatically discovers the required device details such as device ID, type,
and base address from the captured data. You can view this device related
data in the Transaction Decode Setup dialog box.
NOTE
In certain situations, you may need to or you may want to add/modify these device
details. For instance, at times, the required device details are not available in the
captured data and therefore cannot be autodiscovered from the captured data. It then
becomes mandatory for you to specify these details before starting the transaction
decode computation. There may also be situations when you want to rectify the
autodiscovered device details or add details of multiple devices or queues.
It is recommended that you verify and modify device details (if needed) before
transaction decode computation.
You use the Transaction Decode Setup dialog box to define/modify/verify
the information about devices such as:
• device ID, type, and base address
• ID, size, and base address for submission and completion queue(s) of a
device
• ID and size of namespace(s) of a device
To verify/modify device details
1 Click Setup in the Transaction Decode tab of the Protocol Viewer.
The Transaction Decode Setup dialog box is displayed with the
autodiscovered device details from the captured PCIe data.
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2 Modify device details, if needed.
3 You can also add new device details or delete the details of an existing
device by clicking Add Device and Remove Device.
To edit queues and namespaces details of a device
All device details such as its submission and completion queues and
namespaces are autodiscovered from the captured data. If needed, you can
add, remove, or edit these details of a device.
1 In the Transaction Decode Setup dialog box, double- click the device row for
which you want to edit details. Alternatively, select the device row and
click Edit Details...
The Device Setup dialog box is displayed.
2 The Memory Page Size field indicates the size of the physical memory
page configured by the host software. The Memory Page Size value is a
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part of the controller configurations that the host can set and modify.
This value is used to set the size of PRP entries.
3 The Doorbell Stride field indicates the number of bytes to be used in
memory space to separate doorbell registers. This value is a part of the
controller capabilities.
4 Click the Completion Queue tab. The details of Admin and I/O completion
queue(s) autodiscovered by the software from the captured data are
displayed. If these are not autodiscovered, you can add a new queue by
clicking Add Queue and specifying its ID, size, base address, and the
unique MSI- X vector that the controller allocated to this queue to
respond back.
5 Click the Submission Queue tab. The details of Admin and I/O submission
queue(s) autodiscovered by the software from the captured data are
displayed. The completion queue associated with a submission queue is
also displayed. A queue ID is used to display this association. If a
queue’s details are not autodiscovered, you can add a new queue by
clicking Add Queue and specifying its ID, size, and base PRP address(es).
6 If a queue is physically non- contiguous, multiple PRP addresses are
displayed for the queue representing multiple memory chunks. For a
non- contiguous queue, you can add multiple PRP addresses by selecting
a PRP address entry of the queue and clicking Add Address.
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7 Click the Namespaces tab. The details of the controller’s namespace(s)
autodiscovered by the software from the captured data are displayed. If
these are not autodiscovered, you can add a new namespace by clicking
Add Namespace and specifying the following details.
• LBA Size - The Logical Block Address (LBA) data size (in bytes) that
the namespace supports.
• Metadata Size - The number of metadata bytes provided per LBA.
• Metadata Transfer Mode - The metadata may be transferred either as
part of the LBA by creating an extended LBA or as a separate
contiguous buffer of data. When this field is set to End of data LBA, it
indicates that the metadata is transferred at the end of the data
LBA. When this field is set to Separate Buffer, it indicates that all the
metadata for a command is transferred as a separate contiguous
buffer of data.
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8 Click OK to confirm and apply these settings.
Saving the Device Setup Details
You can save the device, its queues, and namespace details (specified using
the Transaction Decode Setup dialog box) in a Transaction decode
(.tdprop) file. Once saved, you can open this file later in the Transaction
Decode Setup dialog box to quickly access and set up the device details
for a transaction decode computation.
To save device details
1 Click Setup in the Transaction Decode tab of the Protocol Viewer.
The Transaction Decode Setup dialog box is displayed. Modify the device
details as needed.
2 Click File > Save As...
3 Specify a name for the Transaction Decode setup file and click Save.
To open a previously saved setup file for transaction computation
1 Click Setup in the Transaction Decode tab.
The Transaction Decode Setup dialog box is displayed.
2 Click File > Open.
3 In the Open dialog box, select the Transaction decode (.tdprop) file that
contains the device setup details.
4 Click Open.
You can edit a saved .tdprop file by opening it in an XML Editor or the
Transaction Decode Setup dialog box.
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Computing Transactions from the Captured Data
1 Click the Transaction Decode tab in the Protocol Viewer window.
2 In the Data Range groupbox, specify the start and end points of the
captured PCIe data for which you want to compute decoded
transactions. Only the specified range of data is analyzed to compute
transactions. Following options are available for setting the data range.
• Beginning and End of data - This data range selection ensures that
transactions are computed for the entire trace.
• Beginning and End of paired data - This data range selection ensures that
transactions are computed only for paired data.
• Trigger - Selecting Trigger in the data range ensures that transactions
are computed from the point where the U4301 module’s trigger
condition was met.
• Markers - Selecting markers in the data range ensures that
transactions are computed for the specific portion of PCIe traffic
defined by markers. Refer to "Defining Markers for Setting the
Computation Range" on page 93 to know more.
3 Click the Compute button displayed with the Data Range fields.
Transactions are computed and displayed for the specified data range.
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You need to recompute the decoded transaction results if you want to change:
- the data range for which transactions are to be displayed.
- the storage protocol for which transactions are to be displayed.
- the device setup such as base address, size, or the number of queues.
Defining Markers for Setting the Computation Range
If the captured PCie traffic is too large and you want to view decoded
transactions from a specific portion of this traffic, then you can limit the
computation range by defining start and end markers in the PCIe traffic.
To define markers
1 From the upper pane of the Protocol Viewer, right- click the row in the
captured PCIe traffic that should act as the starting point for
transaction decode.
2 Select Place Marker from the displayed context menu and then select an
existing marker or click New Marker to define a new marker at this
point.
Once markers are defined, these are available for selection in the Data
Range group box of the Transaction Decode tab.
Saving the Computed Transaction Data
Once you computed the transaction data, you can save it in a logic
analyzer .ala configuration file. The transaction data is saved along with
the captured PCIe traffic, device setup details, and any other
configurations that you made in the Protocol Viewer window.
NOTE
You do not need the Transaction Decoder software license to view the saved
transaction data. However, if you want to recompute transactions from the saved PCIe
trace, then you need the Transaction Decoder software license.
To save the computed transaction data
1 Click File > Save as.
2 In the Save As dialog box, specify the name of the file.
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3 Ensure that the Standard Configuration (*.ala) option is selected as the file
type and All Data and Setup is selected in the File Options group box.
4 Click Save.
To access and view previously saved transaction data
1 Click File > Open.
2 In the Open dialog box, navigate to the Standard Configuration (*.ala) file in
which you saved the transaction data.
3 Click Open.
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Interpreting and Navigating Through the Transaction Decode Results
Transactions are decoded and computed from a set of captured PCIe
packets that contain the storage protocol information associated with that
transaction.
Decoded transactions are displayed in the Transaction Decode tab in an
order based on the timestamp of the first packet associated with a
transaction. One or many PCIe packets may be associated with a
transaction.
Transaction Details Pane
In the left pane of the Transaction Decode tab, transactions with their
details are displayed. In this pane, a transaction is uniquely identified by
a Transaction ID.
The details displayed for transactions vary based on their type and the
applicable storage protocol. Moving the mouse pointer to a field of a
transaction presents a tool tip with information about that field.
A color coding scheme is used to clearly indicate transactions of different
types. Errored transactions are displayed in red.
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NOTE
If you are displaying data captured from multiple U4301A modules in a single Protocol
Viewer instance, then transactions from these multiple modules will be interleaved
based on the timestamp of the first packet in the transaction.
To display transactions for each module separately, you can add a Protocol Viewer
instance to each module in the Overview pane of the Logic and Protocol Analyzer GUI.
Refer to the topic "Viewing NVMe Transactions" on page 101 to get an
understanding of how NVMe transactions are displayed.
Transaction Overview Pane
The right pane of the Transaction Decode tab displays statistics for the
computed transactions. This pane lists the transaction types applicable for
the computed transaction data and the number of events/occurrences for
each transaction type in the computed data.
In this pane, you can organize the number of transaction
occurrences/events on the basis of:
• Link direction - Transaction occurrences are organized on the basis of
the Uplink and Downlink directions in the captured data. Ensure that
you select By Directions in the Organize by field to organize occurrences by
direction. If the captured data is unidirectional, then this view displays
occurrences for one direction only.
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• Queues - Transaction occurrences are organized on the basis of the
submission/completion queues applicable for transactions. Ensure that
you select By Queues in the Organize by field to organize occurrences by
queues. The field next to Organize by listbox displays the device ID for
which the displayed queues are applicable. If multiple devices are
involved, then this field provides you multiple options representing
device IDs of multiple devices. The following screen displays
organization by five queues (0 to 4) of the device with device ID
(001:00:0).
Navigating Through Transactions
You can easily navigate through the occurrences of a particular type of
transaction in the computed transaction data.
1 From the Transaction Overview pane on the lower- right, select a
transaction type whose occurrences you want to navigate and view.
The navigation bar in the Transaction Decode tab now displays the total
number of occurrences found for the selected transaction type.
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2 To view the first occurrence of that transaction type in the computed
data, click
button in the navigation bar. Click
last occurrence of the selected transaction type.
to go to the
3 To sequentially move through the occurrences of a transaction type, use
the
buttons in the navigation bar.
4 To go to a specific occurrence of a transaction type, specify the
event/occurrence number in the text box displayed in the navigation bar
and click Go.
You can also double- click a particular occurrence number in the right
pane to navigate to the first transaction mapped to that occurrence
number. For instance, in the following screen, the first occurrence of an
NVMe Read transaction for Queue 4 is highlighted on double- clicking its
occurrence number in the right pane.
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Navigating Between Transactions and their Associated Packets
From a transaction listed in the Transaction Decode tab, you can quickly
navigate to the PCIe packet(s) exchanged for that particular transaction.
To accomplish this, you need to double- click a transaction in the
Transaction Decode tab. Doing so, highlights the packet exchanged as the
first packet for that transaction in the upper pane of the Protocol Viewer.
In the following screen, double- clicking the transaction for modifying
controller settings highlights the memory write packet for this
modification.
Navigating to a specific packet of a transaction
A transaction may have multiple packets associated with it. For such
transactions, you can directly navigate to any packet of the transaction. To
do this,
1 Right- click a transaction.
2 Select Go To.
A list of packets applicable for that transaction are displayed in a
sequential order.
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3 Select a packet from this list. The packet that you selected gets
highlighted in the upper pane of the Protocol Viewer.
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Viewing NVMe Transactions
Previous help topics described how you can configure and compute
transactions in the Transaction Decode tab. This topic is specific to NVMe
transactions and provides examples of how you can interpret NVMe
transactions that are computed and displayed in the Transaction Decode
tab.
The decoded NVMe transactions provide you a sequential view of the
communication cycle between the host software and NVMe controller for
various requests placed by the host software in queues. You can check
how the NVMe controller responds to and completes these requests. At the
administrative management level, you can verify how the NVMe controller
handles admin requests such as queue management requests.
For NVMe, the Transaction Decode tab displays transactions for:
• NVMe controller initialization such as Admin queue configuration
• NVMe Admin and I/O commands submission and their responses
(completions).
• MSI- X interrupts initiations by controller
• NVMe I/O submission and completion queues management
Viewing Transactions for NVMe Controller Initialization
The following screen displays a set of transactions for NVMe controller
initialization. The AQA, ASQ, and ACQ registers are modified to define the
Admin Submission Queue and its corresponding Admin Completion Queue.
The transactions display the Admin queue attributes in terms of size (128
entries) and the base address (64- bit physical address) to be used for
Admin submission queue and completion queue.
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Viewing Admin Command Transactions
The following screen displays transactions related to the Identify command
submission and completion to return capabilities and status of a specific
namespace.
You can further view the namespace capabilities returned by the Identify
command by right- clicking the NVMe Identify transaction and selecting
Decode Payload.
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You can also visualize how the data returned by the Identify command is
stored in specific PRP entries by right- clicking the transaction and
selecting Visualize PRPs (see page 106).
Viewing NVMe I/O Command Transactions
The following screen displays an NVMe Read transaction to read data from
the starting LBA specified in the Read command.
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For this transaction, the controller:
• first performs a Memory Read to read the request entry from the base
address of submission queue 1.
• then fetches the requested data from system memory
• then performs multiple Memory Writes to write this data to the
applicable PRP entries for data transfer to host.
In the transaction following the NVMe Read transaction, the controller
updates the completion queue 1 with the status of the Read command
completion.
Viewing a Complete Set of Transactions for a Command Submission and
Completion
The following screen displays a complete set of NVMe transactions between
the host and controller. This set of five transactions represents the steps
involved in the NVMe Write command submission and completion process.
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The following list describes the set of five transactions displayed above.
1 The first transaction indicates to the controller that a command is
submitted for processing.
2 The second transaction represents the NVMe Write command that the
host created in the submission queue. The controller reads this
command from the submission queue for execution and executes the
command.
3 The third transaction represents the command completion entry that
the controller writes to the completion queue.
4 The fourth transaction represents the MSI- X interrupt generated by the
controller to indicate that a completion entry has been added to the
completion queue.
5 The fifth transaction indicates to the controller that the host has
processed the completion entry that the controller added to the
completion queue.
Viewing Decoded Payload for Commands
For NVMe commands that retrieve information from NVMe registers in a
specific data structure format, you can view the returned data structure in
the same format as defined in the NVMe protocol specifications. For
instance, the Identify command or the Get Features command returns
information in a specific data structure format defined in NVMe
specifications. The Transaction Decode tab displays the decoded payload
for such commands to present the data structure for such commands as
per the defined format.
To view the decoded payload of an NVMe command
1 Right- click the transaction displayed for the command in the
Transaction Decode tab.
2 Select Decode Payload...
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The Visualize Payload dialog box is displayed with the payload fields
matching the fields specified in NVMe specifications.
The following screen displays the payload details of the NVMe Get
Features command. The feature for which the information is retrieved is
LBA Range Type. The displayed payload is as per the data structure
format defined for LBA Range Type in NVMe specifications.
Viewing Decoded PRPs for Commands
Physical Region Page (PRP) entries are used in read/write transactions to
indicate the physical memory locations in system memory. These memory
locations are used by controller for data transfers to and from system
memory. For a Read request, the PRP entry indicates the memory location
where the controller should transfer the data read from system memory.
For a Write request, the PRP entry indicates the memory location from
where the controller has to gather the data to be written to the system
memory.
These addresses can be directly a memory location or a pointer to a
location that provides a set of addresses of contiguous memory to perform
large read/write operations.
In the Transaction Decode tab, you can view the PRP entries associated
with a command that utilizes PRP entries such as an NVMe Read or Write
command.
To view the decoded PRPs of an NVMe command
1 Right- click the transaction displayed for the command in the
Transaction Decode tab.
2 Select Visualize PRP...
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Viewing Decoded Transactions
The Visualize PRPs dialog box is displayed with PRPs and related
information associated with the command. This dialog box displays:
Component displayed
PRPs applicable for the NVMe
command
Description
The displayed PRPs include:
• a PRP entry representing an actual physical memory page.
• a PRP representing a pointer to a page that defines a PRP List. For such a PRP, a
set of PRP entries in a single page of contiguous memory are also displayed
underneath.
• multiple PRP lists for commands that require multiple PRP Lists for larger
read/writes. The last PRP entry in the first list points to the next PRP list used.
Packets associated with each PRP
entry
Clicking a PRP entry displays a list of its associated PCIe packets in the right pane
of the dialog box. You can click a packet from this list to navigate directly to that
specific packet in the upper pane of Protocol Viewer. This can help you view the
complete address range associated with a PRP entry.
Raw payload for each PRP entry
Clicking a PRP entry displays the raw payload for that PRP entry in the lower pane
of the dialog box.
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11 Viewing Decoded Transactions
Viewing Decoded MSI-X Table
From the decoded MSI-X Table transaction, you can view the index entries
of the MSI- X table in a decoded readable format.
To view index entries of the MSI- X table
1 In the Transaction Decode tab, navigate to the MSI- X Table transaction
by double- clicking the MSI-X Table transaction type from the right pane.
2 Right- click the highlighted MSI-X Table transaction in the left pane of the
Transaction Decode tab and then select Decode MSI-X Table.
The decoded MSI- X Table is displayed.
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11
An MSI- X index entry is associated to a completion queue at the time of
creation of the queue. You can view details about the MSI- X index entry
associated to a completion queue in the Completion Queues tab of the Setup
dialog box.
Each MSI- X index entry in the MSI- X table has a base address associated
to it. This is the address at which the controller writes the MSI- X
interrupt for the associated completion queue.
The following screen displays one such MSI- X Interrupt transaction for the
completion queue 1.
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11 Viewing Decoded Transactions
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U4301A PCIe Gen3 Analyzer
User Guide
12
Viewing Offline Performance Summary
Offline Performance Summary - Overview 112
Configuring and Computing Offline Performance Summary 114
Interpreting the Performance Summary Results 117
Navigating Through the Performance Summary Results 120
Customizing Charts 125
In the Protocol Viewer window, you can generate and view the
performance summary from a PCIe trace that you captured using the
U4301A Analyzer module. This chapter describes how you can compute
and view offline performance summary from the captured PCIe data.
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12 Viewing Offline Performance Summary
Offline Performance Summary - Overview
The PCIe Performance Overview tab in the Protocol Viewer window
allows you to perform post processing on the captured PCIe traffic to
generate an offline performance summary of bus utilization. This tab
presents statistics for various performance parameters in tabular as well
as charts form.
In this tab, you define the range of captured data for which performance
summary is to be generated. The software decodes transactions from this
specified range of data and then computes performance statistics and
charts from the decoded transactions. The specified range of trace data is
sampled and statistics is computed from these samples to generate charts
for each performance parameter.
Performance statistics are displayed separately for upstream and
downstream link directions.
NOTE
You do not need connectivity to the U4301 hardware module to generate
performance summary from a captured PCIe trace.
PCIe Performance Overview Tab
You use the PCIe Performance Overview tab displayed in the lower pane
of the Protocol Viewer to compute and view performance summary.
This tab displays the performance data in the following three panes.
Pane
Description
Categories pane
This is the leftmost pane. It displays a list of categories for which statistics will be generated
and displayed.
Performance Statistics
pane
This is the middle pane and displays a list of performance parameters for the category that
you select in the Categories pane. For each of these parameters, statistics are displayed
based on the link directions (upstream as well as downstream).
Performance Charts pane
This is the rightmost pane. It displays a performance chart for each performance parameter
included in the category selected in the Categories pane
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Viewing Offline Performance Summary
NOTE
If the PCIe Performance Overview tab is not visible, click the
the top of the Protocol Viewer window.
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12
button displayed at
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12 Viewing Offline Performance Summary
Configuring and Computing Offline Performance Summary
Before you Start
• You should have purchased and installed the Offline Performance
Summary license for computing performance summary.
On purchasing the license, you receive an entitlement certificate. Follow
the instructions in this certificate to install the license.
• Ensure that the data in the required direction(s) is already captured
and available in the Logic and Protocol Analyzer GUI for performance
summary computation. You may save the captured data in a Logic
Analyzer configuration (.ala) file and access this data offline for
performance summary computation.
Computing Offline Performance Summary
1 Click the PCIe Performance Overview tab in the Protocol Viewer window.
2 In the Data Range groupbox, specify the start and end points of the
captured PCIe data for which you want to compute performance
summary. Only the specified range of data is analyzed to compute
performance. Following options are available for setting this data range.
• Beginning and End of data - This data range selection ensures that
performance summary is computed for the entire trace.
• Begin Extent and End Extent - This data range selection ensures that
performance summary is computed only for the data that has been
marked by extent markers. The software automatically places extent
markers on the beginning and end of the current pan/zoom extents
defined in charts. When you change the pan/zoom extents in charts,
the extent markers are automatically moved to changed extents.
• Trigger - Selecting Trigger in the data range ensures that performance
summary is computed from the point where the U4301 module’s
trigger condition was met.
• Markers - Selecting markers in the data range ensures that
performance summary is computed for the specific portion of PCIe
traffic defined by markers. Refer to "Defining Markers for Setting the
Computation Range" on page 115 to know more.
3 For generating performance statistics, only complete transactions from
the captured trace are used. Select the Assume ACK checkbox to instruct
the software to assume ACKs for the transactions in which only ACK is
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12
missing. Assuming ACKs, therefore ensures that the transactions with
missing ACK are considered complete and used in performance
summary computation. You may want to use this Assume ACK option in
situations such as when you have filtered ACKs while data capture to
make more memory available to TLPs.
4 Click the Compute button displayed with the Data Range fields.
On clicking Compute, first the transactions are decoded from the
specified data range of PCIe trace. Then, statistics and charts are
computed from these decoded transactions and results are displayed.
Defining Markers for Setting the Computation Range
If the captured PCie traffic is too large and you want to view performance
summary for a specific portion of this traffic, then you can limit the
computation range by defining start and end markers in the PCIe traffic.
To define markers
1 From the upper pane of the Protocol Viewer, right- click the row in the
captured PCIe traffic that should act as the starting point for
performance summary computation.
2 Select Place Marker from the displayed context menu and then select an
existing marker or click New Marker to define a new marker at this
point.
Once markers are defined, these are available for selection in the Data
Range group box of the PCIe Performance Overview tab.
Saving the Computed Performance Summary Data
Once you computed the performance summary data, you can save the
performance configurations along with the captured PCIe traffic in a logic
analyzer .ala configuration file. On saving, the settings such as zoom, pan,
sample rate, markers, chart type, and chart order that you configured in
the PCIe Performance Overview tab are also saved in the .ala file along
with the PCIe trace data. Loading this .ala file retrieves these settings and
computes and displays performance summary based on the saved settings.
NOTE
You do not need the Offline Performance Summary software license to resample charts
from the computed performance summary. However, if you want to recompute
performance summary from the saved PCIe trace, then you need the Offline
Performance Summary software license.
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12 Viewing Offline Performance Summary
To save the performance summary settings
1 Click File > Save as.
2 In the Save As dialog box, specify the name of the file.
3 Ensure that the Standard Configuration (*.ala) option is selected as the file
type and All Data and Setup is selected in the File Options group box.
4 Click Save.
To access and view previously saved performance summary settings
1 Click File > Open.
2 In the Open dialog box, navigate to the Standard Configuration (*.ala) file in
which you saved the data.
3 Click Open.
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Viewing Offline Performance Summary
Interpreting the Performance Summary Results
Categories and Performance Statistics panes
The Categories pane displays a hierarchical list in which various
performance statistics are categorized in groups and sub- groups.
Clicking a category in this pane displays the link- wise statistics for
associated performance parameters in the Performance Statistics pane. The
following table briefly describes the performance statistics displayed for
categories.
Category
Performance Statistics Displayed
Bus Statistics
• Bandwidth (GBits/s): Shows the number of non- idle symbol bits transferred per second.
• Data Throughput (MBytes/s): Shows the number of TLP payload bytes transferred per
second.
• Payload Length (DWords): Shows the minimum, maximum, as well as average payload size
•
•
•
•
Transaction
Performance
for TLPs.
TLP Count (TLPs/s): Shows the number of TLPs transferred per second.
Link Efficiency (%): Shows the efficiency of the link. It is calculated as Symbol time for
payload / (Symbol time for all DLLP + Symbol time for all TLP + Symbol time for OS).
Link Utilization (%): Shows the percentage of non- idle symbols in total number of symbols
transferred.
TLP Utilization (%): Shows the percentage of TLP symbols in total number of symbols
transferred.
• Non- Posted Transactions: Shows the minimum, maximum, and average values of the
following performance parameters for all non- posted transactions.
• Response Time (ns): It is same as the duration of the transaction.
• Latency (us): It is the time duration between the end of a request transaction and the
arrival of its first completion.
• Throughput (MBytes/s): It is the length of complete data divided by the response time.
• Posted Transactions: Shows the minimum, maximum, and average values of the following
performance parameters for all posted transactions.
• Response Time (ns): It is same as the duration of the transaction.
• Throughput (MBytes/s): It is the length of complete data divided by the response time.
Some important points while viewing and interpreting performance
summary:
• If the statistics is displayed as 0 for a performance parameter, it
indicates that the packet(s) required to generate that statistics is not
found in the trace. Consequently, the chart corresponding to such a
performance parameter contains no data and is therefore not displayed
in the charts pane. Such a chart gets displayed only when the required
packets are found while computing performance summary to generate
data for the chart.
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12 Viewing Offline Performance Summary
• For calculating the statistics for the Completion parameter, only
Completions with Data packets are included. Any Completions without
Data packets found in the trace are ignored for this parameter’s
statistics calculations.
For instance, in the following screen, the Completion with Data packets
are used for calculating the minimum, maximum, and average payload
size for Completions. In the absence of Completion with Data packets
in the trace, the Completion statistics is shown as 0.
• Some performance parameters are displayed in blue color. This
indicates that the navigation to the associated PCIe packet is applicable
for that performance parameter. To know more, refer to "From the
Performance Statistics pane" on page 123.
Charts pane
This pane displays charts for all the performance parameters of a selected
category listed in the Categories pane.
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Viewing Offline Performance Summary
Color coding for charts
Different color- coding is used to display the performance data for
downstream and upstream direction in charts. The color legend used in
displayed at the top of the charts pane.
Viewing X and Y axis values in a chart
Hovering the mouse over a chart location displays the applicable values of
X- axis and Y- axis for that location.
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12 Viewing Offline Performance Summary
Navigating Through the Performance Summary Results
Navigating Through a Chart
To navigate through a chart horizontally, that is X- axis, click the Pan X-Axis
button displayed at the top of the charts pane.
To navigate through a chart horizontally and vertically, that is both axis,
click the Pan Both Axis button displayed at the top of the Charts pane. You
can then drag the chart up, down, left, and right.
Navigating Between Performance Statistics and Associated PCIe Data
By placing markers in charts
You can place markers in charts and use these markers to navigate to the
PCIe packet associated with the chart location at which you placed a
marker. Markers placed in charts are correlated to markers displayed in
the trace data in the upper pane of the Protocol Viewer.
This type of navigation is particularly useful when you notice a sudden
variation in a chart and want to navigate to the exact trace position that
corresponds to that chart location.
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Viewing Offline Performance Summary
To place a marker in charts
1 Double- click the location in the chart at which you want to place a
marker. A new marker is added to that chart location and the
corresponding trace location in the upper pane (trace view).
Alternatively, right- click the chart location where you want to place a
marker. Then select Place > New Marker or select an existing marker to
place that marker at the current location.
To navigate to a particular marker placed in charts
In situations when you have placed multiple markers in charts, you may
want to navigate to a particular marker and its associated trace position
in the upper pane. To do so, right- click anywhere in a chart, select Go To
and then select the marker to which you want to navigate.
On doing so, the chart display moves to the point at which the selected
marker is located. Also, the trace position corresponding to the selected
marker is highlighted in the upper pane.
NOTE
If the markers are not displayed in charts, click the Show Markers button at the top of
the charts pane.
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By using Extent Markers
When you pan/zoom a defined area in charts, Extent Markers are
automatically placed at the beginning and end of this defined pan/zoom
extent in charts. On changing the pan/zoom area, these markers are
automatically moved. There may be situations when you zoom a specific
area in charts and then want to navigate to the PCIe data associated with
the chart’s zoomed area in a Waveform Viewer or a Listing. To accomplish
this, you can navigate using Extent Markers.
To navigate using Extent markers:
1 Right- click anywhere in the zoomed area in a chart and select Go To.
2 Then select Begin Extent or End Extent to navigate to the PCIe data
associated with the beginning or end of the zoomed area.
The applicable PCIe data is highlighted in the upper pane of Protocol
Viewer as well as in Waveform and Listing viewers.
NOTE
122
If the Extent Markers are not visible, then click the Extent Markers button at the top of
the charts panes to display these markers in trace view as well as other viewers in
Logic and Protocol Analyzer application.
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12
From the Performance Statistics pane
For some performance parameters such as Minimum and Maximum, it is
possible to navigate directly to the PCIe packet that accounted for the
generation of a particular statistical value of that performance parameter.
Such performance parameters for which navigation to the PCIe packet is
applicable are displayed in blue color.
In the following screen, clicking the Maximum value found for the
Throughput parameter in the upstream direction highlights the PCIe packet
that accounted for that maximum value in the upper pane.
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12 Viewing Offline Performance Summary
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Customizing Charts
Changing the Sampling Rate
The trace data is sampled to compute statistics from these samples for
charts generation. This sampling is done as per the Sample Rate set for
charts. By default, the sample rate is set to 10 microseconds. You can
change this sample rate. Then you can resample the data to regenerate
charts based on the changed sampling rate.
To change the sample rate of charts
1 Access the PCIe Performance Overview tab.
button displayed with the Sample Rate field in the Charts
pane on the right.
2 Click the
3 In the Time dialog box, specify the value and unit for the sample rate.
The permissible range for sample rate is 1 us to 100 ms.
4 Click OK.
To regenerate charts based on the new sample rate
1 Click the Re-Sample button displayed with the Sample Rate field at the
top of the Charts pane.
Changing the Size of Charts
You can increase/decrease the height of charts by keeping the CTRL key
pressed and moving the mouse wheel up or down.
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12 Viewing Offline Performance Summary
Changing the Chart Display
You can change how data is presented in a performance chart. By default,
data is presented as Line chart type. The following chart type options are
available.
• Line -
• Large Dots -
• Small Dots -
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• Columns -
To change chart type for a performance chart
1 Click the Chart Type drop- down listbox from the title bar of the chart for
which you want to change chart type.
2 Select the required option from the drop- down list.
The chart is displayed as per the changed chart type.
Zooming In/Out Charts
You can zoom in or zoom out a defined area in the chart or the complete
chart.
To zoom X- Axis for a defined area in the chart
1 Click the Zoom X-Axis toggle button displayed at the top of the charts
pane to make it active.
2 Move the mouse pointer to the chart location from which you want to
begin zooming.
3 Left- click at this location and while keeping the left mouse button
pressed, drag the mouse to the chart location till which you want to
zoom the display. As you move the mouse, the zooming extent is
defined in chart and highlighted with grey.
When you release the left mouse button, the defined X- axis area is
zoomed for all the displayed charts.
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12 Viewing Offline Performance Summary
Similarly, you can zoom both X and Y axis of the defined area in the chart
by using the Zoom Both Axis button displayed at the top of the performance
charts pane.
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The X-axis zoom applies to all the displayed charts where as the Y-axis zoom (in both
axis zoom) applies only to the chart in which you define the area to zoom.
NOTE
You can also zoom in or zoom out complete charts. To do this, use the
following buttons in the Pan and Zoom section of the charts pane.
NOTE
•
- Zoom In magnifies the center 50% of the chart to the full width
of the chart.
•
- Zoom Out doubles the time displayed in the full width of the
chart.
•
- Zoom Out Full displays the entire range of Computed data
across the full width of the chart.
You can undo and redo zooms by clicking the
and Zoom section of the charts pane.
and
buttons in the Pan
Reordering Charts
Charts for various performance parameters of a category are displayed in
a defined order in the Charts pane. If required, you can change this
default ordering of charts.
To reorder charts
1 Right- click in the Charts pane and then select Reorder Charts...
2 In the Reorder PCIe Performance Charts dialog box, the charts for a
category are displayed. Click the chart to be reordered, drag it and
drop it to the required position in the charts sequence.
3 Click OK to confirm the reordering.
Charts are now redrawn and displayed as per the changed ordering.
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U4301A PCIe Gen3 Analyzer User Guide
U4301 PCIe Gen3 Analyzer
User Guide
Glossary
D
DUT
Device Under Test.
I
interposer Describes a probing method where the probe is located
between a slot and the PCI Express device under test.
M
midbus probe Describes a probing method where Soft Touch footprints are
designed into a DUT board between the controller and the device under
test.

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13 Glossary
132
U4301A PCIe Gen3 Analyzer User Guide
Index
A
L
advanced triggers (for PCIe Gen3 analyzer), 57
Assume ACK, 114
lane polarity inversion (for PCIe Gen3
analyzer), 26
lane reversal (for PCIe Gen3 analyzer), 25
license for decoding transactions, 87
link type (for PCIe Gen3 analyzer), 19
link width (for PCIe Gen3 analyzer), 21
link-specific triggers (for PCIe Gen3
analyzer), 60
LTSSM Overview pane, 76, 79
LTSSM states, 76, 79
B
Begin Extent, 114
bidirectional tuning, 46
bus statistics, 117
C
chart type, 126
charts, 119
clock source (for PCIe Gen3 analyzer), 23
completion queue, 89
connection diagram (for PCIe Gen3
analyzer), 22
Connection Setup, 15
D
decoded MSI-X table, 108
decoded transactions, 92
device setup, 87
DUT (Device Under Test), 131
E
End Extent, 114
Errored LTSSM states, 83
errored transactions, 95
Extent Markers, 122
F
fine tune, 47
G
glossary, 131
I
interposer, 131
U4301A PCIe Gen3 Analyzer User Guide
Physical Tuning file (.ptu), selecting in
analyzer, 44
Probing options, 15
probing options, 13
PRP addresses, 89
PRP entries, 103, 106
PRPs, 107
Q
queues, 88, 97
Quick Tune, 40
M
R
markers, 93, 115
markers in charts, 120
master lane (for PCIe Gen3 analyzer), 25
midbus probe, 131
MSI-X Interrupt transactions, 109
MSI-X table index entries, 108
resample charts, 125
N
namespace, 90
namespaces, 88
NVMe, 86
NVMe Admin command transactions, 102
NVMe controller, 101
NVMe controller initialization transactions, 101
NVMe I/O command transactions, 103
NVMe transactions, 101, 104
O
offline performance summary, 112
ordering of charts, 129
P
pan both axis, 120
pan X-axis, 120
PCIe Gen3 Analyzer (U4301), 3
PCIe Performance Overview tab, 112
performance charts, 118
performance parameters, 112, 117
performance statistics, 117
performance summary license, 114
physical layer tuning (.ptu) file, 38
Physical Tuning file (.ptu), 34
Physical Tuning file (.ptu), creating, 38
S
Sampling Rate, 125
simple triggers (for PCIe Gen3 analyzer), 54
Standard Tune, 40
submission queue, 89
T
transaction data, 93
transaction decode results, 95
transaction navigation, 97
transaction occurrences, 96, 97
transaction performance, 117
transactions set, 104
trigger clear (for PCIe Gen3 analyzer), 61
trigger favorites (for PCIe Gen3 analyzer), 61
trigger options, general (for PCIe Gen3
analyzer), 60
trigger position (for PCIe Gen3 analyzer), 60
tuning log, 41, 49
tuning PCIe Gen3 Analyzer (U4301), 33
tuning PCIe Gen3 Analyzer (U4301), preparing
for, 37
U
U4301 PCIe Gen3 Analyzer, 3
U4321A solid slot interposer, 37
U4322A midbus 3.0 probe, 37
U4324A PCIe Gen3 Flying Lead probe, 37
133
Index
V
visualize payload, 106
visualize PRPs, 107
Z
zoom both axis, 128
zoom charts, 127
zoom out full, 129
zoom X-axis, 127
134
U4301A PCIe Gen3 Analyzer User Guide
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