TL431-Q1 Adjustable Precision Shunt Regulator datasheet (Rev

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TL431A-Q1, TL431B-Q1
SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
TL431-Q1 Adjustable Precision Shunt Regulator
1 Features
3 Description
•
•
The TL431-Q1 is a three-pin adjustable shunt
regulator with specified thermal stability over
applicable automotive temperature ranges. The
output voltage can be set to any value from VREF
(approximately 2.5 V) to 36 V, with two external
resistors (see Figure 28). This device has a typical
output impedance of 0.2 Ω. Active output circuitry
provides a sharp turnon characteristic, making this
device an excellent replacement for Zener diodes in
many applications, such as onboard regulation,
adjustable power supplies, and switching power
supplies.
1
•
•
•
•
•
•
Qualified for Automotive Applications
AEC-Q100 Test Guidance With the Following:
– Device Temperature Grade 1: –40°C to 125°C
Ambient Operating Temperature Range
Reference Voltage Tolerance at 25°C:
– 1% (A Grade)
– 0.5% (B Grade)
Typical Temperature Drift:
– 14 mV (Q Temp)
Low Output Noise
0.2-Ω Typical Output Impedance
Sink-Current Capability: 1 mA to 100 mA
Adjustable Output Voltage: VREF to 36 V
2 Applications
•
•
•
•
•
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
TL431A-Q1
SOT-23 (5)
2.90 mm × 1.60 mm
TL431A-Q1,
TL431B-Q1
SOT-23 (3)
2.92 mm × 1.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Adjustable Voltage and Current Referencing
Secondary Side Regulation in Flyback SMPSs
Zener Replacement
Voltage Monitoring
Comparator With Integrated Reference
Simplified Schematic
VKA
Input
IKA
Vref
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TL431A-Q1, TL431B-Q1
SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
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Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
3
3
3
4
4
4
5
6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: TL431-Q1 ........................
Electrical Characteristics: TL431A-Q1 ......................
Electrical Characteristics: TL431B-Q1 ......................
Typical Characteristics ..............................................
Parameter Measurement Information .................. 9
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 12
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 Typical Applications ................................................ 13
10 Power Supply Recommendations ..................... 18
11 Layout................................................................... 18
11.1 Layout Guidelines ................................................. 18
11.2 Layout Example .................................................... 18
12 Device and Documentation Support ................. 19
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Documentation Support ........................................
Related Links ........................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
19
19
19
19
19
19
19
13 Mechanical, Packaging, and Orderable
Information ........................................................... 19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (March 2013) to Revision E
Page
•
Added Applications section, Device Information table, Pin Configuration and Functions section, Specifications
section, ESD Ratings table, Detailed Description section, Application and Implementation section, Power Supply
Recommendations section, Layout section, Device and Documentation Support section, and Mechanical,
Packaging, and Orderable Information section ...................................................................................................................... 1
•
Deleted Ordering Information table; see Package Option Addendum at the end of the data sheet ...................................... 1
•
Added Thermal Information table ........................................................................................................................................... 4
•
Changed RθJA values for 5-pin DBV (SOT-23) From: 206 To: 215 and for 3-pin DBZ (SOT-23) From: 206 To: 334.7......... 4
2
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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
NC
1
1
2
CATHODE
3
NC
(1)
DBZ Package
3-Pin SOT-23
Top View
5
ANODE
4
REF
CATHODE
1
REF
2
3
ANODE
Pin 2 is connected internally to ANODE
(die substrate) and must be left floating or
connected to ANODE.
Pin Functions
PIN
NAME
I/O
DESCRIPTION
DBV
DBZ
ANODE
5
3
O
Common pin, normally connected to ground.
CATHODE
3
1
I/O
Shunt current or voltage input
NC
1, 2
—
—
No connection (1)
REF
4
2
I
(1)
Threshold relative to common anode
Pin 2 of the 5-pin DBV (SOT-23) package is connected internally to ANODE (die substrate) and must be left floating or connected to
ANODE.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
Cathode voltage (2)
Continuous cathode current
–100
Low
Reference input current
mA
µA
High
Storage temperature, Tstg
(2)
V
150
–50
Operating junction temperature, TJ
(1)
UNIT
37
–65
10
mA
150
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Voltage values are with respect to the ANODE pin, unless otherwise noted.
6.2 ESD Ratings
VALUE
Human-body model (HBM), per AEC Q100-002
V(ESD)
(1)
Electrostatic discharge
(1)
UNIT
±2500
Charged-device model (CDM), per AEC Q100-011
±1000
Machine model (MM)
±200
V
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VKA
Cathode voltage
IKA
Cathode current
TA
Operating free-air temperature
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MIN
MAX
VREF
36
V
1
100
mA
–40
125
°C
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UNIT
3
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6.4 Thermal Information
TL431-Q1
THERMAL METRIC (1)
DBV (SOT-23)
DBZ (SOT-23)
5 PINS
3 PINS
UNIT
215
334.7
°C/W
135.2
113.5
°C/W
43
67.6
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
ψJT
Junction-to-top characterization parameter
19.6
6.7
°C/W
ψJB
Junction-to-board characterization parameter
42.1
65.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics: TL431-Q1
over recommended operating conditions, TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
2440
2495
2550
mV
14
34
mV
ΔVKA = 10 V – VREF
–1.4
–2.7
ΔVKA = 36 V – 10 V
–1
–2
VREF
Reference voltage
VKA = VREF, IKA = 10 mA, see Figure 20
VI(DEV)
Deviation of reference voltage over full
temperature (1)
VKA = VREF, IKA = 10 mA, TA = –40°C to 125°C,
see Figure 20
ΔVREF/ΔVKA
Ratio of change in reference voltage to the
change in cathode voltage
IKA = 10 mA,
see Figure 21
IREF
Reference current
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞, see Figure 21
2
4
µA
II(DEV)
Deviation of reference current over full
temperature (1)
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞,
TA = –40°C to 125°C, see Figure 21
0.8
2.5
µA
IMIN
Minimum cathode current for regulation
VKA = VREF, see Figure 20
0.4
1
mA
IOFF
OFF-state cathode current
VKA = 36 V, VREF = 0, see Figure 22
0.1
1
µA
IKA = 1 mA to 100 mA, VKA = VREF, f ≤ 1 kHz,
see Figure 20
0.2
0.5
Ω
|ZKA|
(1)
Dynamic impedance
(1)
mV/V
The deviation parameters (VI(DEV) and II(DEV)) are defined as the differences between the maximum and minimum values obtained over
the recommended temperature range.
6.6 Electrical Characteristics: TL431A-Q1
over recommended operating conditions, TA = 25°C (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF
Reference voltage
PARAMETER
VKA = VREF, IKA = 10 mA, see Figure 20
2470
2495
2520
mV
VI(DEV)
Deviation of reference voltage over full
temperature (1)
VKA = VREF, IKA = 10 mA, TA = –40°C to 125°C,
see Figure 20
14
34
mV
ΔVREF/ΔVKA
Ratio of change in reference voltage to the
change in cathode voltage
IKA = 10 mA,
see Figure 21
ΔVKA = 10 V – VREF
–1.4
–2.7
ΔVKA = 36 V – 10 V
–1
–2
IREF
Reference current
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞, see Figure 21
2
4
µA
II(DEV)
Deviation of reference current over full
temperature (1)
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞,
TA = –40°C to 125°C, see Figure 21
0.8
2.5
µA
IMIN
Minimum cathode current for regulation
VKA = VREF, see Figure 20
0.4
0.7
mA
IOFF
OFF-state cathode current
VKA = 36 V, VREF = 0, see Figure 22
0.1
0.5
µA
Dynamic impedance (1)
IKA = 1 mA to 100 mA, VKA = VREF, f ≤ 1 kHz,
see Figure 20
0.2
0.5
Ω
|ZKA|
(1)
4
mV/V
The deviation parameters (VI(DEV) and II(DEV)) are defined as the differences between the maximum and minimum values obtained over
the recommended temperature range.
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6.7 Electrical Characteristics: TL431B-Q1
over recommended operating conditions, TA = 25°C (unless otherwise noted)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VREF
Reference voltage
PARAMETER
VKA = VREF, IKA = 10 mA, see Figure 20
2483
2495
2507
mV
VI(DEV)
Deviation of reference voltage over full
temperature (1)
VKA = VREF, IKA = 10 mA, TA = –40°C to 125°C,
see Figure 20
14
34
mV
ΔVREF/ΔVKA
Ratio of change in reference voltage to the
change in cathode voltage
IKA = 10 mA,
see Figure 21
ΔVKA = 10 V – VREF
–1.4
–2.7
ΔVKA = 36 V – 10 V
–1
–2
IREF
Reference current
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞, see Figure 21
2
4
µA
II(DEV)
Deviation of reference current over full
temperature (1)
IKA = 10 mA, R1 = 10 kΩ, R2 = ∞,
TA = –40°C to 125°C, see Figure 21
0.8
2.5
µA
IMIN
Minimum cathode current for regulation
VKA = VREF, see Figure 20
0.4
0.7
mA
IOFF
OFF-state cathode current
VKA = 36 V, VREF = 0, see Figure 22
0.1
0.5
µA
Dynamic impedance (1)
IKA = 1 mA to 100 mA, VKA = VREF, f ≤ 1 kHz,
see Figure 20
0.2
0.5
Ω
|ZKA|
(1)
mV/V
The deviation parameters (VI(DEV) and II(DEV)) are defined as the differences between the maximum and minimum values obtained over
the recommended temperature range.
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6.8 Typical Characteristics
2600
2560
5
VREF = 2440 mV
VREF = 2495 mV
VREF = 2550 mV
4
Refrence Current (PA)
Reference Voltage (mV)
2580
2540
2520
2500
2480
2460
2440
3
2
1
2420
2400
-75
-50
-25
0
25
50
75
Free-Air Temperature (qC)
100
0
-75
125
-50
-25
D001
Data is for devices having the indicated value of VREF at IKA = 10 mA,
TA = 25°C.
Figure 1. Reference Voltage vs Free-air Temperature
0
25
50
75
Free-Air Temperature (qC)
100
125
D002
Figure 2. Reference Current vs Free-air Temperature
150
800
125
600
Cathode Current (PA)
Cathode Current (mA)
100
75
50
25
0
-25
-50
Imin
400
200
0
-75
-100
-2
-1
0
1
Cathode Voltage (V)
2
-200
-1
3
Figure 3. Cathode Current vs Cathode Voltage
2
3
D004
-0.85
-0.95
2
'VKA - mV/V
Off-State Cathode Current (PA)
1
Cathode Voltage (V)
Figure 4. Cathode Current vs Cathode Voltage
2.5
1.5
1
-1.05
-1.15
-1.25
0.5
0
-75
-1.35
-50
-25
0
25
50
75
Free-Air Temperature (qC)
100
Figure 5. OFF-State Cathode Current vs
Free-air Temperature
6
0
D003
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125
-1.45
-75
-50
-25
D005
0
25
50
75
Free-Air Temperature (qC)
100
125
D006
Figure 6. Ratio of Delta Reference Voltage to Delta Cathode
Voltage vs Free-air Temperature
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Typical Characteristics (continued)
6
Equivalent Input Noise Voltage (PV)
Equivalent Input Noise Voltage (nV/ÖHz)
260
240
220
200
180
160
140
120
100
10
4
3
2
1
0
-1
-2
-3
-4
-5
-6
100
1k
Frequency (Hz)
10k
100k
0
50
50
30
20
Reference Impedance (:)
100
40
3
4
30
20
10
5000 10000
100000
Frequency (Hz)
5
6
Time (s)
7
8
9
10
D008
10
5
3
2
1
0.5
0.3
0.2
0.1
1000
1000000
10000
100000
Frequency (Hz)
D001
Figure 9. Small-Signal Voltage Amplification vs Frequency
1000000
1E+7
D001
Figure 10. Reference Impedance vs Frequency
6
100
90
5
80
Cathode Current (mA)
Input and Output Voltage (V)
2
Figure 8. Equivalent Input Noise Voltage Over a 10-s Period
60
0
1000 2000
1
D007
Figure 7. Equivalent Input Noise Voltage vs Frequency
Small-Signal Voltage Amplification (dB)
5
4
3
2
A VKA = Vref
B VKA = 5 V
C VKA = 10 V
D VKA = 15 Vf
70
Stable
60
Stable
50
40
30
20
1
0
-1
10
0
1
2
3
4
Time (Ps)
5
6
7
D011
Figure 11. Pulse Response
0
0.001
0.01
0.1
Load Capacitance (PF)
1
10
D012
The areas under the curves represent conditions that may cause the
device to oscillate. For curves B, C, and D, R2 and VREF were
adjusted to establish the initial VKA and IKA conditions with CL = 0.
VBATT and CL then were adjusted to determine the ranges of stability
(see Figure 18 and Figure 19 for test circuits).
Figure 12. Stability Boundary Conditions for All TL431 and
TL431A Devices (Except for SOT23-3, SC-70,
and Q-TEMP Devices)
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Typical Characteristics (continued)
100
A VKA = Vref
B VKA = 5 V
C VKA = 10 V
D VKA = 15 Vf
90
Cathode Current (mA)
80
70
60
Stable
Stable
50
40
30
20
10
0
0.001
0.01
0.1
Load Capacitance (PF)
1
10
D013
The areas under the curves represent conditions that may cause the device to oscillate. For curves B, C, and D, R2 and VREF were adjusted
to establish the initial VKA and IKA conditions with CL = 0. VBATT and CL then were adjusted to determine the ranges of stability (see
Figure 18 and Figure 19 for test circuits).
Figure 13. Stability Boundary Conditions for All TL431B, TL432, SOT-23, SC-70, and Q-TEMP Devices
8
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7 Parameter Measurement Information
19.1 V
1 kΩ
500 µF
910 Ω
2000 µF
VCC
TL431
(DUT)
VCC
1 µF
TLE2027
AV = 10 V/mV
+
−
16 kΩ
16 kΩ
1 µF
To
Oscilloscope
−
16 Ω
160 kΩ
22 µF
TLE2027
+
820 Ω
33 kΩ
AV = 2 V/V
0.1 µF
33 kΩ
VEE
VEE
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Figure 14. Test Circuit for Equivalent Input Noise Voltage
Output
15 k Ω
220 Ω
IKA
Output
232 Ω
9 µF
Pulse
Generator
f = 100 kHz
+
−
50 Ω
8.25 k Ω
GND
GND
Figure 15. Test Circuit for Voltage Amplification
Figure 17. Test Circuit for Pulse Response
150 Ω
1 kΩ
Output
IKA
+
IKA
CL
50 Ω
VBATT
−
−
+
GND
Figure 16. Test Circuit for Reference Impedance
Figure 18. Test Circuit for Curve A
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VKA
Input
IKA
IKA
R1
+
CL
Iref
VBATT
−
Vref
R2
Figure 19. Test Circuit for Curves B, C, and D
VKA
Input
R1 ö
æ
VKA = Vref ç 1 +
+ Iref ´ R1
R2 ÷ø
è
Figure 21. Test Circuit for VKA > VREF
VKA
Input
Ioff
IKA
Vref
Figure 22. Test Circuit for IOFF
Figure 20. Test Circuit for VKA = VREF
10
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8 Detailed Description
8.1 Overview
This device has proven ubiquity and versatility across a wide range of applications, ranging from power to signal
path. This is due to its key components containing an accurate voltage reference and op amp, which are
fundamental analog building blocks. The TL431-Q1 can be used as a single voltage reference, error amplifier,
voltage clamp, or comparator with integrated reference.
The TL431-Q1 can be operated and adjusted to cathode voltages from 2.5 V to 36 V, making this part optimum
for a wide range of end equipments in industrial, auto, telecommunications, and computing. For this device to
behave as a shunt regulator or error amplifier, at least 1 mA (IMIN(MAX)) must be supplied to the cathode pin.
Under this condition, feedback can be applied from the CATHODE and REF pins to create a replica of the
internal reference voltage.
Various reference voltage options can be purchased with initial tolerances (at 25°C) of 0.5% and 1%. These
reference options are denoted by B (0.5%) or A (1%) in the part number (TL431x-Q1).
8.2 Functional Block Diagram
CATHODE
+
REF
_
V ref
ANODE
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Figure 23. Equivalent Schematic
CATHODE
800 Ω
800 Ω
20 pF
REF
150 Ω
3.28 kΩ
2.4 kΩ
7.2 kΩ
10 kΩ
4 kΩ
20 pF
1 kΩ
800 Ω
ANODE
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All component values are nominal.
Figure 24. Detailed Schematic
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8.3 Feature Description
The TL431-Q1 consists of an internal reference and amplifier that outputs a sink current based on the difference
between the reference pin and the virtual internal pin. The sink current is produced by the internal Darlington
pair, shown in Figure 24. A Darlington pair is used to allow this device to sink a maximum current of 100 mA.
When operated with enough voltage headroom (at least 2.5 V) and cathode current (IKA), the TL431-Q1 forces
the reference pin to 2.5 V. However, the reference pin can not be left floating, as IREF must be at least 4 µA (see
Specifications). This is because the reference pin is driven into an NPN, which requires base current to operate
properly.
When feedback is applied from the CATHODE and REF pins, the TL431-Q1 behaves as a Zener diode,
regulating to a constant voltage dependent on current being supplied into the cathode. This is due to the internal
amplifier and reference entering the proper operating regions. The same amount of current required in the above
feedback situation must be applied to this device in open loop, servo, or error amplifying implementations for it to
be in the proper linear region giving the device enough gain.
Unlike many linear regulators, the TL431-Q1 is internally compensated to be stable without an output capacitor
between the cathode and anode. However, if it is desired to use an output capacitor Figure 24 can be used as a
guide to assist in choosing the correct capacitor to maintain stability.
8.4 Device Functional Modes
8.4.1 Open Loop (Comparator)
When the cathode or output voltage or current of the TL431-Q1 is not being fed back to the reference or input pin
in any form, the device operates in open loop. With proper cathode current (IKA) applied to this device, the
TL431-Q1 has the characteristics shown in Figure 24. With such high gain in this configuration, the device is
typically used as a comparator. The integrated reference makes TL431 the prefered choice when trying to
monitor a certain level of a single signal.
8.4.2 Closed Loop
When the cathode or output voltage or current of the TL431-Q1 is being fed back to the reference or input pin in
any form, the device operates in closed loop. The majority of applications involving the TL431-Q1 use it in this
manner to regulate a fixed voltage or current. The feedback enables this device to behave as an error amplifier,
computing a portion of the output voltage and adjusting it to maintain the desired regulation. This is done by
relating the output voltage back to the reference pin in a manner to make it equal to the internal reference
voltage, which can be accomplished through resistive or direct feedback.
REF
ANODE
CATHODE
Figure 25. Logic Symbol
12
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SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
As this device has many applications and setups, there are many situations that this data sheet can not
characterize in detail. The linked application notes help the make the best choices when using this part.
Understanding Stability Boundary Conditions Charts in TL431, TL432 Data Sheet provides a deeper
understanding of this devices stability characteristics and aid the user in making the right choices when choosing
a load capacitor. Setting the Shunt Voltage on an Adjustable Shunt Regulator assists designers in setting the
shunt voltage to achieve optimum accuracy for this device.
9.2 Typical Applications
9.2.1 Comparator Application
Copyright © 2016, Texas Instruments Incorporated
Figure 26. Comparator Application Schematic
Copyright © 2005–2016, Texas Instruments Incorporated
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Typical Applications (continued)
9.2.1.1 Design Requirements
For this design example, use the parameters listed in Table 1 as the input parameters.
Table 1. Design Parameters
PARAMETER
VALUE
Input voltage
0 V to 5 V
Input resistance
10 kΩ
Supply voltage
24 V
Cathode current, IK
5 mA
Output voltage level
Approximately 2 V to VSUP
Logic input thresholds, VIH / VIL
VL
9.2.1.2 Detailed Design Procedure
When using the TL431-Q1 as a comparator with reference, determine the following:
• Input voltage range
• Reference voltage accuracy
• Output logic input high and low level thresholds
• Current source resistance
9.2.1.2.1 Basic Operation
In the configuration shown in Figure 26 the TL431-Q1 behaves as a comparator, comparing the REF pin voltage
to the internal virtual reference voltage. When provided a proper cathode current (IKA), the TL431-Q1 has enough
open loop gain to provide a quick response. This is shown in Figure 27, where the RSUP = 10 kΩ (IKA = 500 µA)
situation responds much slower than RSUP = 1 kΩ (IKA = 5 mA). With the TL431-Q1's maximum operating current
(IMIN) being 1 mA, operation below that could result in low gain, leading to a slow response.
9.2.1.2.2 Overdrive
Slow or inaccurate responses can also occur when the reference pin is not provided enough overdrive voltage.
This is the amount of voltage that is higher than the internal virtual reference. The internal virtual reference
voltage is within the range of 2.5 V ± (0.5%, 1%, or 1.5%) depending on which version is being used. The more
overdrive voltage provided, the faster the TL431-Q1 responds.
For applications where the TL431-Q1 is being used as a comparator, it is best to set the trip point to greater than
the positive expected error (for example: +1% for the A version). For fast response, setting the trip point to at
least 10% of the internal VREF should suffice.
For minimal drop or difference from VINREF to the REF pin, TI recommends using an input resistor <10 kΩ to
provide IREF
9.2.1.2.3 Output Voltage and Logic Input Level
For the TL431-Q1 to properly be used as a comparator, the logic output must be readable by the receiving logic
device. This is accomplished by knowing the input high and low level threshold voltage levels, typically denoted
by VIH and VIL.
As seen in Figure 26, the TL431-Q1's output low level voltage in open-loop or comparator mode is approximately
2 V, which is typically sufficient for 5-V supplied logic. However, would not work for 3.3-V and 1.8-V supplied
logic. To accommodate this a resistive divider can be tied to the output to attenuate the output voltage to a
voltage legible to the receiving low voltage logic device.
The TL431-Q1's output high voltage is equal to VSUP due to the TL431-Q1 being open-collector. If VSUP is much
higher than the receiving logic's maximum input voltage tolerance, the output must be attenuated to
accommodate the outgoing logic's reliability.
When using a resistive divider on the output, ensure the sum of the resistive divider (R1 and R2 in Figure 24) is
much greater than RSUP to not interfere with the TL431-Q1's ability to pull close to VSUP when turning off.
14
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TL431A-Q1, TL431B-Q1
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SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
9.2.1.2.4 Input Resistance
In this application, the TL431-Q1 requires an input resistance in addition to the reference current (IREF) to ensure
the device is in the proper operating regions while turning on. The actual voltage seen at the REF pin is
VREF = VIN – IREF × RIN. Because IREF can be as high as 4 µA, TI recommends using a resistance small enough
to mitigate the error that IREF creates from VIN.
9.2.1.2.5 Deviation Parameters and Calculating Dynamic Impedance
The deviation parameters, VI(DEV) and II(DEV), are defined as the differences between the maximum and minimum
values obtained over the recommended temperature range. The average full-range temperature coefficient of the
reference voltage (αVref) is defined in Equation 1.
æ V
ö
I(dev)
ç
÷ x 106
o
at 25 C ÷
ç
ppm è Vref
ø
=
o
DTA
C
a vref
Maximum Vref
VI(dev)
Minimum Vref
∆TA
where
•
ΔTA is the recommended operating free-air temperature range of the device
(1)
αVref can be positive or negative, depending on whether minimum VREF or maximum VREF, respectively, occurs at
the lower temperature.
Example:
Maximum VREF = 2496 mV at 30°C, minimum VREF = 2492 mV at 0°C, VREF = 2495 mV at 25°C, ΔTA = 70°C
for TL431.
æ 4 mV ö
6
ç
÷ x 10
2495
mV
23 ppm
ø
a vref = è
» o
70o C
C
(2)
Because minimum VREF occurs at the lower temperature, the coefficient is positive.
The dynamic impedance is defined as |ZKA| = ΔVKA / ΔIKA.
When the device is operating with two external resistors, see Figure 21, the total dynamic impedance of the
circuit is given by Equation 3.
R1 ö
DV
æ
z¢ =
» ZKA ç 1 +
R2 ÷ø
DI
è
(3)
9.2.1.3 Application Curve
5.5
5
4.5
4
Voltage (V)
3.5
3
2.5
2
1.5
1
Vin
Vka(Rsup=10k:)
Vka(Rsup=1k:)
0.5
0
-0.5
-0.001
-0.0006
-0.0002
0.0002
Time (s)
0.0006
0.001
D001
Figure 27. Output Response With Various Cathode Currents
Copyright © 2005–2016, Texas Instruments Incorporated
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9.2.2 Other Application Circuits
Figure 28 to Figure 40 show application circuit examples using the TL431-Q1 device. Customers must fully
validate and test any circuit before implementing a design based on an example in this section. Unless otherwise
noted, the design procedures in Comparator Application are applicable.
V I(BATT)
R
(see Note A)
VI(BATT)
VO
R1
0.1%
VO
TL431
R1 ö
æ
VO = ç 1 +
Vref
R2 ÷ø
è
TL431
Vref
Von ≈ 2 V
Voff ≈ VI(BATT)
Input
R2
0.1%
VIT ≈ 2.5 V
GND
RETURN
Copyright © 2016, Texas Instruments Incorporated
A. R must provide cathode current ≥1 mA to the TL431-Q1 at
minimum VI(BATT).
Copyright © 2016, Texas Instruments Incorporated
Figure 28. Shunt Regulator
Figure 29. Single-Supply Comparator with
Temperature-Compensated Threshold
VI(BATT)
VI(BATT)
IN
OUT
R
(see Note A)
VO
uA7805
2N222
2N222
Common
R1
30 Ω
R1 ö
æ
VO = ç 1 +
Vref
R2 ÷ø
è
4.7 kΩ
0.01 µF
TL431
TL431
R1 ö
æ
VO = ç 1 +
Vref
R2 ÷ø
è
Minimum VO = Vref + 5 V
R2
VO
R1
0.1%
R2
0.1%
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
A. R must provide cathode current ≥1 mA to the TL431-Q1 at
minimum VI(BATT).
Figure 30. Precision High-Current Series Regulator
VI(BATT)
Figure 31. Output Control of a Three-Terminal
Fixed Regulator
VI(BATT)
VO
VO
R1
R1
TL431
R1 ö
æ
VO = ç 1 +
Vref
R2 ÷ø
è
R2
C
(see Note 1)
TL431
R2
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
(1) See Figure 12 and Figure 13 to determine allowable values for
C.
Figure 32. High-Current Shunt Regulator
16
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Figure 33. Crowbar Circuit
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: TL431A-Q1 TL431B-Q1
TL431A-Q1, TL431B-Q1
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SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
IN
VI(BATT)
OUT
VI(BATT)
VO ≈ 5 V, 1.5 A
LM317
Adjust
8.2 kΩ
VO ≈ 5 V
Rb
(see Note 1)
243 Ω
0.1%
27.4 kΩ
0.1%
TL431
TL431
27.4 kΩ
0.1%
243 Ω
0.1%
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
(1) Rb must provide cathode current ≥1 mA to the TL431-Q1.
Figure 34. Precision 5-V, 1.5-A Regulator
Figure 35. Efficient 5-V Precision Regulator
R3
(see Note A)
12 V
VI(BATT)
R1B
R1A
VCC
6.8 kΩ
R1B ö
æ
Low Limit = ç 1 +
Vref
R2B ÷ø
è
TL431
R1A ö
æ
High Limit = ç 1 +
Vref
R2A ÷ø
è
LED on when Low Limit < VI(BATT) < High Limit
R2B
R2A
10 kΩ
5V
R4
(see Note A)
−
10 kΩ
0.1%
+
X
Not
Used
TL431
10 kΩ
0.1%
Copyright © 2016, Texas Instruments Incorporated
TL598
A. R3 and R4 are selected to provide the desired LED intensity and
cathode current ≥1 mA to the TL431-Q1 at the available VI(BATT).
Feedback
Copyright © 2016, Texas Instruments Incorporated
Figure 36. PWM Converter with Reference
Figure 37. Voltage Monitor
650 Ω
RCL
12 V
IO
0.1%
R
VI(BATT)
2 kΩ
Iout =
R1
TL431
Off
On
TL431
æ 12 V
ö
Delay = R ´ C ´ In ç
÷
è 12 V - Vref ø
C
R1 =
Vref
+ IKA
RCL
VI(BATT)
IO
+I
hFE KA
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 38. Delay Timer
Figure 39. Precision Current Limiter
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: TL431A-Q1 TL431B-Q1
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TL431A-Q1, TL431B-Q1
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www.ti.com
VI(BATT)
IO
I
O=
TL431
Vref
RS
RS
0.1%
Copyright © 2016, Texas Instruments Incorporated
Figure 40. Precision Constant-Current Sink
10 Power Supply Recommendations
When using the TL431-Q1 as a linear regulator to supply a load, designers typically use a bypass capacitor on
the output or cathode pin. When doing this, be sure that the capacitance is within the stability criteria shown in
Figure 12 and Figure 13.
To not exceed the maximum cathode current, be sure that the supply voltage is current limited. Also, be sure to
limit the current being driven into the REF pin, as not to exceed its absolute maximum rating.
For applications shunting high currents, pay attention to the cathode and anode trace lengths, adjusting the width
of the traces to have the proper current density.
11 Layout
11.1 Layout Guidelines
Bypass capacitors must be placed as close to the device as possible. Current-carrying traces must have widths
appropriate for the amount of current they are carrying; in the case of the TL431-Q1, these currents are low.
11.2 Layout Example
DBZ
(TOP VIEW)
Rref
Vin
REF
1
Rsup
Vsup
ANODE
3
CATHODE
GND
2
CL
GND
Figure 41. DBZ Layout Example
18
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Product Folder Links: TL431A-Q1 TL431B-Q1
TL431A-Q1, TL431B-Q1
www.ti.com
SGLS302E – MARCH 2005 – REVISED NOVEMBER 2016
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Understanding Stability Boundary Conditions Charts in TL431, TL432 Data Sheet (SLVA482)
• Setting the Shunt Voltage on an Adjustable Shunt Regulator (SLVA445)
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
TL431A-Q1
Click here
Click here
Click here
Click here
Click here
TL431B-Q1
Click here
Click here
Click here
Click here
Click here
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.5 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2005–2016, Texas Instruments Incorporated
Product Folder Links: TL431A-Q1 TL431B-Q1
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19
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL431AQDBVRQ1
ACTIVE
SOT-23
DBV
5
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TACQ
TL431AQDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
TAQU
TL431BQDBZRQ1
ACTIVE
SOT-23
DBZ
3
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 125
T3FU
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Feb-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TL431A-Q1, TL431B-Q1 :
• Catalog: TL431A, TL431B
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
TL431AQDBVRQ1
SOT-23
DBV
5
3000
180.0
8.4
TL431AQDBZRQ1
SOT-23
DBZ
3
3000
179.0
TL431BQDBZRQ1
SOT-23
DBZ
3
3000
179.0
3.2
3.2
1.4
4.0
8.0
Q3
8.4
3.15
2.95
1.22
4.0
8.0
Q3
8.4
3.15
2.95
1.22
4.0
8.0
Q3
Pack Materials-Page 1
W
Pin1
(mm) Quadrant
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Aug-2017
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL431AQDBVRQ1
SOT-23
DBV
5
3000
203.0
203.0
35.0
TL431AQDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
TL431BQDBZRQ1
SOT-23
DBZ
3
3000
203.0
203.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
1.75
1.45
PIN 1
INDEX AREA
1
0.1 C
B
A
5
2X 0.95
1.9
1.45 MAX
3.05
2.75
1.9
2
4
0.5
5X
0.3
0.2
3
(1.1)
C A B
0.15
TYP
0.00
0.25
GAGE PLANE
8
TYP
0
0.22
TYP
0.08
0.6
TYP
0.3
SEATING PLANE
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X (0.95)
3
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214839/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
2X(0.95)
4
3
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
4203227/C
PACKAGE OUTLINE
DBZ0003A
SOT-23 - 1.12 mm max height
SCALE 4.000
SMALL OUTLINE TRANSISTOR
C
2.64
2.10
1.4
1.2
PIN 1
INDEX AREA
1.12 MAX
B
A
0.1 C
1
0.95
3.04
2.80
1.9
3X
3
0.5
0.3
0.2
2
(0.95)
C A B
0.25
GAGE PLANE
0 -8 TYP
0.10
TYP
0.01
0.20
TYP
0.08
0.6
TYP
0.2
SEATING PLANE
4214838/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration TO-236, except minimum foot length.
www.ti.com
EXAMPLE BOARD LAYOUT
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X (0.95)
2
(R0.05) TYP
(2.1)
LAND PATTERN EXAMPLE
SCALE:15X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4214838/C 04/2017
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBZ0003A
SOT-23 - 1.12 mm max height
SMALL OUTLINE TRANSISTOR
PKG
3X (1.3)
1
3X (0.6)
SYMM
3
2X(0.95)
2
(R0.05) TYP
(2.1)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:15X
4214838/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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