Datasheet | Rev. 2.0 | 2014
IMM2G72D3(L)RVQ8AG (Die Revision B)
16GByte (2048M x 72 Bit)
16GB DDR3 VLP Registered DIMM
RoHS Compliant Product
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Version: Rev. 2.0, FEB 2015
2.0 – Editorial change in Table 5.
Updated CAS Latency support to include CL5
Added Operation temperature for Industrial Temperature Product in Table 10
Updated Input Switching Conditions in Table 13
Moved VSEH information from Table 14 to Table 15
Updated SPD information in Table 19
Version: Rev. 1.0, NOV 2013
1.0 - Initial release.
Remark:
Please refer to the last page of the i) Contents ii) List of Table iii) List of Figures .
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at
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IMM2G72D3(L)RVQ8AG
Features
240-Pin Registered Dual-In-Line Memory Module
Capacity: 16GB
JEDEC-Standard
Bi-directional Differential Data-Strobe
72 Bit Data Bus Width with ECC
Programmable CAS Latency (CL):
o PC3-12800: 5, 6, 7, 8, 9, 10, 11
o PC3-10600: 5, 6, 7, 8, 9
Programmable CAS Write Latency (CWL):
o PC3-12800: 5, 6, 7, 8
o PC3-10600: 5, 6, 7
Programmable Additive Latency (Posted /CAS): 0, CL-2 or CL-1(Clock)
On-Die Termination (ODT)
ZQ Calibration Supported
Burst Type (Sequential & Interleave)
Burst Length: 4, 8
Refresh Mode: Auto and Self
8192 Refresh Cycles / 64ms
Asynchronous Reset
On-board I2C Temperature Sensor with Integrated Serial Presence Detect (SPD) EEPROM
Gold Edge Contacts
100% RoHS-Compliant
Very Low Profile Module Height: 18.75mm (0.738 inch)
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IMM2G72D3(L)RVQ8AG
Table 1 - Ordering Information for RoHS Compliant Product
Part Number
Module Density Configuration # of Ranks
Module Type
IMM2G72D3xRVQ8AGBzzzy
16GB
16GB DDR3 VLP
Registered DIMM
2Gx72
4
Notes:
x: Operating Voltage
y: Operating Temperature
zzz: Speed Grade
Table 2 - Operating Voltage
Part Number
Operating Voltage
Blank
VDD, VDDQ = 1.5V (1.425V-1.575V)
VDD, VDDQ = 1.35V (1.283V-1.45V)
Backward compatible to VDD, VDDQ = 1.5V (1.425V-1.575V)
L
Table 3 - Temperature Grade
Part Number
Temperature Grade
Tcase
Blank
Commercial temperature
0°C to 95°C
I
Industrial temperature
-40°C to 95°C
Remark: Tcase is the case surface temperature on the center/top side of the DRAM. The refresh rate is required to double
when 85 oC < Tcase <= 95 oC.
Table 4 - Speed Grade
Part Number
Speed Grade
Max Clock Frequency (min. Clock Cycle time @
min. CAS Latency)
-125
PC3-12800 (DDR3-1600)
800MHz (1.25ns@CL=11)
-15E
PC3-10600 (DDR3-1333)
667MHz (1.5ns@CL=9)
Table 5 - Memory Chip Information
Part Number
Base Device
Brand
Base device
Voltage Type
IMM2G72D3LRVQ8AG-Bzzzy
I’M
IM8G08D3FBDG
1.35V
IMM2G72D3RVQ8AG-Bzzzy
I’M
IM8G08D3EBDG
1.5V
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Chip Packing
512Mx8x2
Lead Free
DDP
512Mx8x2
Lead Free
DDP
IMM2G72D3(L)RVQ8AG
Part Number Decoder
IMM
2G72
D3
(L) RV
Q 8 A G -B
Intelligent
125 I
Temperature Grade
Blank = Commercial
Temperature
(0°C to 95°C Tc)
Memory
Module
I = Industrial Temperature
Module Configuration
(-40 to 95°C Tc)
2G72 = 2Gx72 (16GB)
Speed Grade
Memory Type
15E = PC3-10600 / DDR3-1333
D3 = DDR3
125 = PC3-12800 / DDR3-1600
DDR3L option
IC Revision
Blank = 1.5 Volt
A = Revision A
L = 1.35 or 1.5 Volt (DDR3L)
B = Revision B
C = Revision C
Module FormForm-Factor
RV = VLP Registered DIMM
RoHSRoHS-compliance
G = Green / RoHS
Number of Ranks
Q = Quad Rank
Module PCB Revision
A = Revision A
B = Revision B
C = Revision C
DRAM Bit width
8 = using x8 components
Table 6 – Addressing
Parameter
16GB
Refresh count
Row address
Device bank address
Device configuration
Column address
Module rank address
Number of devices
8K
64K A[15:0]
8 BA[2:0]
8Gb (512Mx8x2 DDP)
1K A[9:0]
4 /S[3:0]
18
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IMM2G72D3(L)RVQ8AG
Table 7 - Pin Assignment
Pin
Name
Pin
Name
Pin
Name
Pin
Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
VREFDQ
VSS
D0
D1
VSS
/DQS0
DQS0
VSS
D2
D3
VSS
D8
D9
VSS
/DQS1
DQS1
VSS
D10
D11
VSS
D16
D17
VSS
/DQS2
DQS2
VSS
D18
D19
VSS
D24
D25
VSS
/DQS3
DQS3
VSS
D26
D27
VSS
CB0
CB1
VSS
/DQS8
DQS8
VSS
CB2
CB3
VSS
VTT
VTT
CKE0
VDD
BA2
/ERR_OUT
VDD
A11
A7
VDD
A5
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
VSS
D4
D5
VSS
TDQS9, DM0
/TDQS9, NC
VSS
D6
D7
VSS
D12
D13
VSS
TDQS10, DM1
/TDQS10, NC
VSS
D14
D15
VSS
D20
D21
VSS
TDQS11, DM2
/TDQS11, NC
VSS
D22
D23
VSS
D28
D29
VSS
TDQS12, DM3
/TDQS12, NC
VSS
D30
D31
VSS
CB4
CB5
VSS
TDQS17, DM8
/TDQS17, NC
VSS
CB6
CB7
VSS
NC
/RESET
CKE1
VDD
A15
A14
VDD
A12, /BC
A9
VDD
A8
A6
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
A2
VDD
CK1
/CK1
VDD
VDD
VREFCA
PAR_IN
VDD
A10, AP
BA0
VDD
/WE
/CAS
VDD
/S1
ODT1
VDD
/S2
VSS
D32
D33
VSS
/DQS4
DQS4
VSS
D34
D35
VSS
D40
D41
VSS
/DQS5
DQS5
VSS
D42
D43
VSS
D48
D49
VSS
/DQS6
DQS6
VSS
D50
D51
VSS
D56
D57
VSS
/DQS7
DQS7
VSS
D58
D59
VSS
SA0
SCL
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
A1
VDD
VDD
CK0
/CK0
VDD
/EVENT
A0
VDD
BA1
VDD
/RAS
/S0
VDD
ODT0
A13
VDD
/S3
VSS
D36
D37
VSS
TDQS13, DM4
/TDQS13, NC
VSS
D38
D39
VSS
D44
D45
VSS
TDQS14, DM5
/TDQS14, NC
VSS
D46
D47
VSS
D52
D53
VSS
TDQS15, DM6
/TDQS15, NC
VSS
D54
D55
VSS
D60
D61
VSS
TDQS16, DM7
/TDQS16, NC
VSS
D62
D63
VSS
VDDSPD
SA1
SDA
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Pin
Name
Pin
Name
Pin
Name
Pin
Name
59
60
A4
VDD
179
180
VDD
A3
119
120
SA2
VTT
239
240
VSS
VTT
Table 8 - Pin Description
Pin Name
Description
Pin Name
Description
VDD
SDRAM core power supply
VREFDQ
SDRAM I/O reference supply
VREFCA
SDRAM command/address reference
supply
VSS
Power supply return (ground)
A0-A15
SDRAM address bus
BA0-BA2
SDRAM bank addresses
CK0, CK1
SDRAM clocks
(positive line of differential pair)
/CK0, /CK1
SDRAM clocks
(negative line of differential pair)
/RAS
SDRAM row address strobe
/CAS
SDRAM column address strobe
/WE
SDRAM write enable
CKE0, CKE1
SDRAM clock enable lines
/S0-/S3
DIMM Rank Select Lines
ODT0, ODT1 On-die termination control lines
DQS0-DQS8
SDRAM data strobes
(positive line of differential pair)
/DQS0-/DQS8
SDRAM data strobes
(negative line of differential pair)
TDQS9TDQS17
Termination SDRAM data strobes
(positive line of differential pair)
/TDQS9/TDQS17
Termination SDRAM data strobes
(negative line of differential pair)
D0-D63
DIMM memory data bus
CB0-CB7
Data check bits Input/Output
DM0-DM8
Data Masks
SDA
EEPROM data line
SCL
EEPROM clock
VDDSPD
EEPROM positive power supply
SA0-SA2
EEPROM address input
/EVENT
Temperature event
PAR_IN
Parity Input
/RESET
Register and SDRAM control pin
/ERR_OUT
Parity Error Output
VTT
Termination Voltage
NC
Spare Pins (no connect)
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Figure 1 – Module Dimension 240 pin DDR3 SDRAM VLP Registered DIMM
B
A
A
B
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 9 - PCB Dimension
Symbol
MIN
NOM
MAX
A
18.60
18.75
18.90
A1
9.35
9.50
9.65
A2
0.05
0.20
0.35
A3
15.65
15.80
15.95
D
133.20
133.35
133.50
D1
12.00 Basic
D2
2.50 Basic
e1
47.00 Basic
e2
71.00 Basic
E1
4.00
Notes:
All dimensioning and tolerancing conform to ASME Y14.5M-1994.
Tolerances for all dimensions ±0.15 unless otherwise specified.
All dimensions are in millimeters.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
VSS
ZQ1
VTT
Datasheet Version 1.0
ZQ0
VSS
ZQ1
DQS0
DQS
DQS
/DQS0
/DQS
/DQS
DM0/DQS9
TDQS
TDQS
/DQS9
/TDQS
D0-D7
D0-D7
DQS
/DQS
/DQS
DM1/DQS10
TDQS
TDQS
/DQS10
/TDQS
D8-D15
D0-D7
U3
VSS
D0-D7
ZQ0
VSS
ZQ1
U2
VSS
ZQ0
VSS
D0-D7
ZQ1
U1
/TDQS
VSS
D0-D7
ZQ0
VSS
ZQ1
U10
ODT1
D0-D7
ODT1
D16-D23
CKE1
/TDQS
CKE1
TDQS
/DQS11
10
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ODT1
CKE1
/CS1
ODT0
CKE0
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
A[15:0] / BA[2:0]
/WE
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
ZQ1
/CS1
TDQS
CKE0
D0-D7
ODT0
/DQS
DM2/DQS11
ZQ0
VSS
/CS1
DQS
/DQS
VSS
ODT0
DQS
/CS0
U4
CKE0
D0-D7
CKE0
D24-D31
/CS0
/TDQS
/CS0
TDQS
/DQS12
/CK
TDQS
CK
/DQS
DM3/DQS12
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
A[15:0] / BA[2:0]
/WE
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
ZQ1
/CK
DQS2
/DQS2
/CK
D0-D7
A[15:0] / BA[2:0]
DQS
/DQS
VSS
/WE
DQS
ZQ0
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
DQS3
/DQS3
VSS
/CS0
DQS
/CS0
ZQ1
CK
U9
CK
ZQ1
CK
D0-D7
A[15:0] / BA[2:0]
CB0-CB7
/CK
DQS1
/DQS1
/CK
VSS
/WE
/TDQS
CK
ZQ1
CK
ZQ0
A[15:0] / BA[2:0]
VSS
/CAS
TDQS
/DQS17
A[15:0] / BA[2:0]
VSS
/WE
/RAS
TDQS
/WE
ZQ0
A[15:0] / BA[2:0]
VSS
/CAS
/DQS
DM8/DQS17
A[15:0] / BA[2:0]
VSS
/WE
/RAS
DQS
/DQS
/WE
ZQ0
/CAS
DQS
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
/RAS
VSS
A[15:0] / BA[2:0]
/WE
/CAS
DQS8
/DQS8
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
/RAS
VSS
A[15:0] / BA[2:0]
ZQ0
/WE
VSS
/CAS
/RAS
VDD
/RS3
RODT1A
/RS2
/PCK1A
PCK1A
VDD
RCKE1A
/RS1
RODT0A
RCKE0A
/RS0
/PCK0A
PCK0A
RA[15:0]A / BA[2:0]A
/RWEA
/RCASA
/RRASA
Figure 2 – Functional Block Diagram (Page 1 of 3)
/TDQS
U18
/TDQS
U13
/TDQS
U12
/TDQS
U11
VTT
IMM2G72D3(L)RVQ8AG
VSS
ZQ1
VTT
Datasheet Version 1.0
ZQ0
VSS
ZQ1
DQS7
DQS
DQS
/DQS7
/DQS
/DQS
DM7/DQS16
TDQS
TDQS
/DQS16
/TDQS
D56-D63
D0-D7
DQS
/DQS
/DQS
DM6/DQS15
TDQS
TDQS
/DQS15
/TDQS
D48-D55
D0-D7
U7
VSS
D0-D7
ZQ0
VSS
ZQ1
U8
/TDQS
VSS
D0-D7
ZQ0
VSS
ZQ1
U17
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ODT1
ZQ1
ODT1
VSS
CKE1
D0-D7
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
A[15:0] / BA[2:0]
ZQ0
/WE
VSS
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
U6
CKE1
D0-D7
/CS1
D40-D47
ODT0
/TDQS
/CS1
TDQS
/DQS14
ODT0
TDQS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
A[15:0] / BA[2:0]
/WE
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
ZQ1
CKE0
/DQS
DM5/DQS14
VSS
CKE0
DQS
/DQS
ZQ0
/CS0
DQS
/CK
D0-D7
/CK
DQS5
/DQS5
VSS
CK
ZQ1
CK
U5
/CS0
DQS
/CS0
D0-D7
/CK
DQS6
/DQS6
/CK
D32-D39
CK
ZQ1
CK
/TDQS
A[15:0] / BA[2:0]
TDQS
/DQS13
A[15:0] / BA[2:0]
VSS
/WE
TDQS
/WE
ZQ0
A[15:0] / BA[2:0]
VSS
/CAS
/DQS
DM4/DQS13
A[15:0] / BA[2:0]
VSS
/WE
/RAS
DQS
/DQS
/WE
ZQ0
/CAS
DQS
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
/RAS
VSS
A[15:0] / BA[2:0]
/WE
/CAS
DQS4
/DQS4
/CAS
/RAS
ODT1
CKE1
/CS1
ODT0
CKE0
/CS0
/CK
CK
/RAS
VSS
A[15:0] / BA[2:0]
ZQ0
/WE
VSS
/CAS
/RAS
VDD
/RS3
RODT1B
/RS2
/PCK1B
PCK1B
VDD
RCKE1B
/RS1
RODT0B
RCKE0B
/RS0
/PCK0B
PCK0B
RA[15:0]B/BA[2:0]B
/RWEB
/RCASB
/RRASB
Figure 3 – Functional Block Diagram (Page 2 of 3)
/TDQS
U14
/TDQS
U15
/TDQS
U16
VTT
IMM2G72D3(L)RVQ8AG
Figure 4 – Functional Block Diagram (Page 3 of 3)
/S0
/RS0: U1-U9
/S1
/RS1: U1-U9
/S2
/RS2: U10-U18
/S3
/RS3: U10-U18
RBA[2:0]A: U1-U4, U9-U13, U18
RBA[2:0]B: U5-U8, U14-U17
BA[2:0]
VDDSPD
RA[15:0]A: U1-U4, U9-U13, U18
RA[15:0]B: U5-U8, U14-U17
A[15:0]
U20
VDD
U1-U18
VTT
U1-U18
/RAS
/RRASA: U1-U4, U9-U13, U18
/RRASB: U5-U8, U14-U17
VREFCA
U1-U18
/CAS
/RCASA: U1-U4, U9-U13, U18
/RCASB: U5-U8, U14-U17
VREFDQ
U1-U18
VSS
U1-U18
/WE
ODT0
U19
1:2
REGISTER
ODT1
CK0
/CK0
CK1
/RWEA: U1-U4, U9-U13, U18
/RWEB: U5-U8, U14-U17
RODT0A: U1-U4, U9
RODT0B: U5-U8
RODT1A: U10-U13, U18
RODT1B: U14-U17
PCK0A: U1-U4, U9
PCK0B: U5-U8
PCK1A: U10-U13, U18
PCK1B: U14-U17
Thermal Sensor with SPD
SDA
SDA
SCL
SCL
/PCK0A: U1-U4, U9
/PCK0B: U5-U8
/PCK1A: U10-U13, U18
/PCK1B: U14-U17
U20
VDD
/EVENT
A0
A1
A2
SA0
SA1
SA2
VDDSPD
/EVENT
/CK1
PAR_IN
/ERR_OUT
/RESET
/RST: U1-U18
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Electrical Parameter
Table 10 - Absolute Maximum DC Ratings
Parameter
Symbol
Rating
Unit
Notes
Voltage on VDD, pin relative to VSS
VDD
-0.4V ~ 1.975
V
1,3
Voltage on VDDQ, pin relative to VSS
VDDQ
-0.4V ~ 1.975
V
1,3
Voltage on any pins relative to VSS
VIN, VOUT
-0.4V ~ 1.975
V
1
DRAM Storage temperature
TSTG
-55 ~ 100
o
C
1,2
DRAM Operation temperature (Standard
Product)
DRAM Operation temperature (Industrial
Temperature Product)
Tcase
0 ~ 95
o
C
2,4,6
Tcase
-40 ~ 95
o
C
2,5,6
Notes:
1
2
3
4
5
6
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Storage Temperature or DRAM operation temperature is the case surface temperature on the center/top
side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than 0.6 x
VDDQ, when VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between 0-95 °C under all operating
conditions.
The Normal Temperature Range specifies the temperatures when all DRAM specifications will be supported.
During operation, the DRAM case temperature must be maintained between -40-95 °C under all operating
conditions.
Some applications require operation of the Extended Temperature Range between 85 °C and 95 °C case
temperature. Full Specifications are guaranteed in this range but the following additional conditions apply
a) Refresh commands must be doubled in frequency, therefore reducing the refresh interval tREFI to 3.9us.
b) If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either
use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7
= 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b).
Table 11 - DC Electrical Characteristics and Operating Conditions
Parameter / Condition
Supply voltage
I/O supply voltage
Supply voltage
I/O supply voltage
Symbol
VDD
VDDQ
VDD
VDDQ
Rating
Units Notes
Min
Typ.
Max
1.283
1.35
1.45
1.425
1.5
1.575
V
V
V
V
1,2
1,2
1,2,3
1,2,3
Notes:
1
2
3
VDD and VDDQ must track one another. VDDQ must be less than or equal to VDD. VSS = VSSQ.
VDD and VDDQ may include AC noise of +/-50mV (250 kHz to 20 MHz) in addition to the DC (0 Hz to 250
kHz) specifications. VDD and VDDQ must be at same level for valid AC timing parameters.
Module is backward-compatible with 1.5V operation.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 12 - DC Electrical Characteristics and Input Conditions
Parameter / Condition
VIN low; DC/commands/address
buses (1.35V Operation)
VIN low; DC/commands/address
buses (1.5V Operation)
VIN high; DC/commands/address
buses (1.35V Operation)
VIN high; DC/commands/address
buses (1.5V Operation)
Input reference voltage;
command/address bus
I/O reference voltage DQ bus
Command/address termination
voltage
(system level, not direct DRAM
input)
Symbol
Rating
Units Notes
Min
Typ.
Max
VIL
VSS
-
-0.090
V
VIL
VSS
-
-0.100
V
VIH
0.090
-
VDD
V
VIH
0.100
-
VDD
V
VREFCA(DC)
0.49* VDD
0.50* VDD
0.51* VDD
V
1,2
VREFDQ(DC)
0.49* VDD
0.50* VDD
0.51* VDD
V
2,3
VTT
-
0.50* VDDQ
-
V
4
Notes:
1
2
3
4
VREFCA(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally
generated peak noise (noncommon mode) on VREFCA may not exceed ±1% × VDD around the VREFCA(DC)
value. Peak-to-peak AC noise on VREFCA should not exceed ±2% of VREFCA(DC).
DC values are determined to be less than 20 MHz in frequency. DRAM must meet specifications if the
DRAM induces additional AC noise greater than 20 MHz in frequency.
VREFDQ(DC) is expected to be approximately 0.5 × VDD and to track variations in the DC level. Externally
generated peak noise (noncommon mode) on VREFDQ may not exceed ±1% × VDD around the VREFDQ(DC)
value. Peak-to-peak AC noise on VREFDQ should not exceed ±2% of VREFDQ(DC).
VTT is not applied directly to the device. VTT is a system supply for signal termination resistors. MIN and
MAX values are system-dependent.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 13 - Input Switching Conditions
Parameter / Condition
Symbol
Value
Units
1.35V Operation 1.5V Operation
Input high AC voltage: Logic 1 @ 175mV
Input high AC voltage: Logic 1 @ 160mV
Input high AC voltage: Logic 1 @ 150mV
Input high AC voltage: Logic 1 @ 135mV
Input high DC voltage: Logic 1 @ 100mV
Input high DC voltage: Logic 1 @ 90mV
Input low DC voltage: Logic 0 @ -90mV
Input low DC voltage: Logic 0 @ -100mV
Input low AC voltage: Logic 0 @ -135mV
Input low AC voltage: Logic 0 @ -150mV
Input low AC voltage: Logic 0 @ -160mV
Input low AC voltage: Logic 0 @ -175mV
Parameter / Condition
Command and Address
VIH(AC175)min
VIH(AC160)min
VIH(AC150)min
VIH(AC135)min
VIH(DC100)min
VIH(DC90)min
VIL(DC90)max
VIL(DC100)max
VIL(AC135)max
VIL(AC150)max
VIL(AC160)max
VIL(AC175)max
160
135
90
-90
-135
-160
-
Symbol
175
150
100
-100
-150
-175
Value
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
mV
Units
1.35V Operation 1.5V Operation
Input high AC voltage: Logic 1
Input high AC voltage: Logic 1
Input high DC voltage: Logic 1
Input high DC voltage: Logic 1
Input low DC voltage: Logic 0
Input low DC voltage: Logic 0
Input low AC voltage: Logic 0
Input low AC voltage: Logic 0
DQ and DM
VIH(AC150)min
VIH(AC135)min
VIH(DC100)min
VIH(DC90)min
VIL(DC90)max
VIL(DC100)max
VIL(AC135)max
VIL(AC150)max
135
90
-90
-135
-
150
100
-100
-150
mV
mV
mV
mV
mV
mV
mV
mV
Notes:
1
2
3
4
All voltages are referenced to VREF. VREF is VREFCA for control, command, and address. All slew rates and
setup/hold times are specified at the DRAM ball. VREF is VREFDQ for DQ and DM inputs.
Input setup timing parameters (tIS and tDS) are referenced at VIL(AC)/VIH(AC), not VREF(DC).
Input hold timing parameters (tIH and tDH) are referenced at VIL(DC)/VIH(DC), not VREF(DC).
Single-ended input slew rate = 1 V/ns; maximum input voltage swing under test is 900mV (peak-to-peak).
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS)
Parameter / Condition
Differential input voltage logic
high – slew (1.35V Operation)
Differential input voltage logic
high – slew (1.5V Operation)
Differential input voltage logic
low – slew (1.35V Operation)
Differential input voltage logic
low – slew (1.5V Operation)
Differential input voltage logic
high
Differential input voltage logic
low
Differential Input Cross Point
Voltage relative to VDD/2 for
CK, CK
Differential Input Cross Point
Voltage relative to VDD/2 for
DQS, DQS
Symbol
Rating
Units Notes
Min
Max
VIH,diff
+180
-
mV
1
VIH,diff
+200
-
mV
1
VIL,diff
-
-180
mV
1
VIL,diff
-
-200
mV
1
VIH,diff(AC)
2* (VIH(AC) - VREF)
-
mV
2
VIL,diff(AC)
-
2* (VIL(AC) - VREF)
mV
3
VIX
-150
150
mV
VIX
-150
150
mV
Notes:
1
2
3
Defines slew rate reference points, relative to input crossing voltages.
Minimum DC limit is relative to single-ended signals; overshoot specifications are applicable.
Maximum DC limit is relative to single-ended signals; undershoot specifications are applicable.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 15 - Single-Ended Output Driver Characteristics
Parameter / Condition
Output slew rate: Single-ended;
For rising and falling edges,
measure between VOL(AC) = VREF 0.1 * VDDQ and VOH(AC) = VREF +
0.1 * VDDQ (1.35V Operation)
Output slew rate: Single-ended;
For rising and falling edges,
measure between VOL(AC) = VREF 0.1 * VDDQ and VOH(AC) = VREF +
0.1 * VDDQ (1.5V Operation)
Single-ended high level for
strobes
Single-ended high level for CK,
/CK
Single-ended low level for
strobes
Single-ended low level for CK,
/CK
Single-ended DC high-level
output voltage
Single-ended DC mid-level
output voltage
Single-ended DC low-level
output voltage
Single-ended AC high-level
output voltage
Single-ended AC low-level
output voltage
Test load for AC timing and
output slew rates
Symbol
Rating
Units Notes
Min
Max
SRQse
1.75
5
V/ns
1,2,3
SRQse
2.5
5
V/ns
1,2,3
VDDQ/2 + 175
-
mV
2
VDD/2 + 175
-
mV
2
-
VDDQ/2 - 175
mV
3
-
VDD/2 - 175
mV
3
VSEH
VSEL
VOH(DC)
0.8 * VDDQ
V
1
VOM(DC)
0.5 * VDDQ
V
1
VOL(DC)
0.2 * VDDQ
V
1
VOH(AC)
VTT + 0.1 * VDDQ
V
1,2
VOL(AC)
VTT - 0.1 * VDDQ
V
1,2
Output to VTT (VDDQ/2) via 25Ω resistor
Notes:
1
2
3
RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration
has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
VTT = VDDQ/2.
The 6 V/ns maximum is applicable for a single DQ signal when it is switching either from HIGH to LOW or
LOW to HIGH while the remaining DQ signals in the same byte lane are either all static or all switching the
opposite direction. For all other DQ signal switching combinations, the maximum limit of 6 V/ns is reduced
to 5 V/ns.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
Table 16 - Differential Output Driver Characteristics
Parameter / Condition
Output slew rate: Differential;
For rising and falling edges,
measure between VOL,diff(AC) = 0.2 * VDDQ and VOH,diff(AC) = + 0.2
* VDDQ (1.35V Operation)
Output slew rate: Differential;
For rising and falling edges,
measure between VOL,diff(AC) = 0.2 * VDDQ and VOH,diff(AC) = + 0.2
* VDDQ (1.5V Operation)
Differential high-level output
voltage
Differential low-level output
voltage
Test load for AC timing and
output slew rates
Symbol
Rating
Units Notes
Min
Max
SRQdiff
3.5
12
V/ns
1
SRQdiff
5
10
V/ns
1
VOH,diff(AC)
+0.2 * VDDQ
V
1
VOL,diff(AC)
-0.2 * VDDQ
V
1
Output to VTT (VDDQ/2) via 25Ω resistor
Notes:
1
2
RZQ of 240Ω (±1%) with RZQ/7 enabled (default 34Ω driver) and is applicable after proper ZQ calibration
has been performed at a stable temperature and voltage (VDDQ = VDD, VSSQ = VSS).
VREF = VDDQ/2; slew rate @ 5V/ns, interpolate for faster slew rate.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Table 17 - IDD Specifications with Conditions and Operation Current
Parameter / Condition
Symbol
Current
1.35V
1.5V
Operation Operation
Units
Notes
Operating current 0; One bank ACTIVATE-toPRECHARGE
IDD0
1476
1575
mA
1, 2
Operating current 1; One bank ACTIVATE-to-READto-PRECHARGE
IDD1
1566
1710
mA
1, 2
IDD2P0
1008
1080
mA
1, 3
IDD2P1
1008
1080
mA
1, 3
IDD2Q
1296
1440
mA
1, 3
IDD2N
2016
2160
mA
1, 3
IDD2NT
2376
2520
mA
1, 3
IDD3P
1080
1152
mA
1, 3
IDD3N
2232
2520
mA
1, 3
IDD4R
2556
2700
mA
1, 2
IDD4W
1701
1845
mA
1, 2
IDD5B
2331
2475
mA
1, 2
IDD6
648
720
mA
1, 3
IDD6ET
648
720
mA
1, 3
IDD7
2916
3150
mA
1, 2
IDD8
873
945
mA
1, 2
Precharge power-down current; Slow exit
Precharge power-down current; Fast exit
Precharge quiet standby current
Precharge standby current
Precharge standby ODT current
Active power-down current
Active standby current
Burst read operating current
Burst write operating current
Refresh current
Self refresh temperature current: MAX Tc = 85oC
Self refresh temperature current (SRT-enabled):
MAX Tc = 95oC
All banks interleaved read current
Reset current
Notes:
1
2
3
Value shown for DDR3 SDRAM only and are computed from values specified in the 8GBit component data
sheet.
One module rank in the active IDD, the other rank in IDD2P0.
All ranks in this IDD conditions.
Datasheet Version 1.0
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IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Table 18 - AC Timing Parameter and Operating Conditions
Parameter / Condition
Symbol
Clock period average: TC = 0oC to 85oC
DLL disable mode
TC => 85oC to 95oC
Clock periods average: DLL enable mode (CL =
11, CWL = 8)
Clock periods average: DLL enable mode (CL =
9, CWL = 7)
High pulse width average
Low pulse width average
Clock period jitter
DLL locked
DLL locking
Clock absolute period
t
Clock absolute high pulse width
t
Clock absolute low pulse width
t
Cycle-to-cycle jitter
t
Cumulative error across
DLL locked
DLL locking
2 cycles
3 cycles
4 cycles
5 cycles
6 cycles
7 cycles
8 cycles
9 cycles
10 cycles
11 cycles
12 cycles
n = 14,…49, 50
cycles
Clock Timing
CK (DLL_DIS) 8
8
t
CK (AVG)
1.25
DQS, /DQS to DQ skew, per access
DQ output hold time from DQS, /DQS
DQ Low-Z time from CK, /CK
DQ High-Z time from CK, /CK
DQS, /DQS rising to CK, /CK rising
DQS, /DQS differential input low pulse width
Max
Units
7800
3900
<1.5
ns
ns
t
1.5
<1.875
ns
t
0.47
0.47
-70
-60
t
CK (AVG) MIN + tJITper
MIN
0.43
0.53
0.53
70
60
t
CK (AVG) MAX + tJITper
MAX
-
t
0.43
-
CK (AVG)
CH (AVG)
CL (AVG)
t
JITper
t
JITper,Ick
t
CK (ABS)
t
CH (ABS)
CL (ABS)
-103
-122
-136
-147
-155
-163
-169
-175
-180
-184
-188
(1+0.68ln[n]) * tJITper
MIN
DQ Input Timing
Base (specification) tDS (AC135)
25
Data setup time to DQS,
/DQS (1.35V Operation)
Data setup time to DQS, Base (specification)
/DQS (1.5V Operation)
Data hold time from DQS, Base (specification)
/DQS (1.35V Operation)
Data hold time from DQS, Base (specification)
/DQS (1.5V Operation)
Minimum data pulse width
Datasheet Version 1.0
Min
JITcc
JITcc,Ick
t
ERR2per
t
ERR3per
t
ERR4per
t
ERR5per
t
ERR6per
t
ERR7per
t
ERR8per
t
ERR9per
t
ERR10per
t
ERR11per
t
ERR12per
t
ERRnper
t
140
120
103
122
136
147
155
163
169
175
180
184
188
(1+0.68ln[n]) * tJITper
Max
-
t
10
-
t
55
-
t
45
-
DS (AC150)
DH (DC90)
DH (DC100)
t
DIPW
360
DQ Output Timing
t
DQSQ
t
QH
0.38
-
t
225
225
LZDQ
-450
HZDQ
DQ Strobe Input Timing
t
DQSS
-0.27
t
DQSL
0.45
t
20
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100
-
0.27
0.55
CK
CK
ps
ps
ps
t
t
CK
(AVG)
t
CK
(AVG)
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
CK
(AVG)
ps
ps
t
t
CK
CK
t
IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Parameter / Condition
Symbol
DQS, /DQS falling setup to CK, /CK rising
DQS, /DQS falling hold from CK, /CK rising
DQS, /DQS differential input high pulse width
DQS, /DQS differential WRITE preamble
DQS, /DQS differential WRITE postamble
t
DQS, /DQS rising to/from CK, /CK
DQS, /DQS differential output high time
DQS, /DQS differential output low time
DQS, /DQS Low-Z time (RL-1)
DQS, /DQS High-Z time (RL+BL/2)
DQS, /DQS differential READ preamble
DQS, /DQS differential READ postamble
DLL locking time
CTRL, CMD, ADDR setup
to CK, /CK (1.35V
Operation)
CTRL, CMD, ADDR setup
to CK, /CK (1.5V
Operation)
CTRL, CMD, ADDR setup
to CK, /CK (1.35V
Operation)
t
RPST
0.3
Command and Address Timing
t
DLLK
512
Base (specification) tIS (AC160)
60
Max
Units
0.55
-
t
225
225
225
greater of tLZ(DQS) (MIN),
t
DQSK (MAX)
greater of tDQSCK (MIN)
+ tQSH (MIN), tHZ(DQS)
(MAX)
ps
t
CK
t
CK
ps
ps
t
CK
-
t
CK
ps
ps
CK
CK
t
CK
t
CK
t
CK
t
t
CK
Base (specification) tIS (AC175)
45
-
ps
Base (specification) tIS (AC135)
185
-
t
170
-
ps
ps
ps
ps
ps
t
130
-
ps
ps
t
120
-
ps
ps
t
IPW
RCD
t
RP
t
RAS
t
RC
t
RRD
t
FAW
t
WR
t
WTR
560
13.125
13.125
35
48.125
greater of 4tCK or 6ns
30
15
greater of 4tCK or 7.5ns
9 * tREFI
-
ps
ns
ns
ns
ns
t
CK
ns
ns
t
CK
t
RTP
CCD
t
DAL
greater of 4tCK or 7.5ns
4
WR + tRP/ tCK (AVG)
-
t
t
4
greater of 12tCK or 15ns
1
-
t
CTRL, CMD, ADDR setup Base (specification)
to CK, /CK (1.5V
Operation)
CTRL, CMD, ADDR hold
Base (specification)
from CK, /CK (1.35V
Operation)
CTRL, CMD, ADDR hold
Base (specification)
from CK, /CK (1.5V
Operation)
Minimum CTRL, CMD, ADDR pulse width
ACTIVATE to internal READ or WRITE delay
PRECHARGE command period
ACTIVATE-to-PRECHARGE command period
ACTIVATE-to-ACTIVATE command period
ACTIVATE-to-ACTIVATE minimum period
Four ACTIVATE windows (2KB page size)
Write recovery time
Delay from start of internal WRITE transaction
to internal READ command
READ-to-PRECHARGE time
/CAS-to-/CAS command delay
Auto precharge write recovery + precharge
time
MODE REGISTER SET command cycle time
MODE REGISTER SET command update delay
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register
exit
Datasheet Version 1.0
Min
DSS
0.18
t
DSH
0.18
t
DQSH
0.45
t
WPRE
0.9
t
WPST
0.3
DQ Strobe Output Timing
t
DQSCK
-225
t
QSH
0.40
t
QSL
0.40
t
LZDQS
-450
t
HZDQS
t
RPRE
0.9
IS (AC150)
IH (DC90)
IH (DC100)
t
t
MRD
MOD
t
MPRR
t
21
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CK
CK
t
CK
t
CK
CK
t
CK
t
IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Parameter / Condition
ZQCL command: Long
calibration time
POWER-UP and
RESET operation
Normal operation
ZQCS command: Short calibration time
Exit reset from CKE HIGH to valid command
REFRESH-to-ACTIVATE or REFRESH command
period
Maximum refresh
Tc<=85oC
period
Tc>85oC
Maximum average
Tc<=85oC
periodic refresh
Tc>85oC
Symbol
Min
Calibration Timing
t
ZQinit
greater of 512 tCK
t
ZQoper
greater of 256 tCK
ZQcs
greater of 64 tCK
Initialization and Reset Timing
t
XPR
greater of 5tCK or
t
RFC(min)+10ns
Refresh Timing
t
RFC
260
t
Units
-
t
-
t
-
t
-
ns
64 (1X)
32 (2X)
t
REFI
7.8 (64ms/8192)
3.9 (32ms/8192)
Self Refresh Timing
Exit self refresh to commands not requiring a tXS
greater of 5 tCK or
t
locked DLL
RFC+10ns
t
t
Exit self refresh to commands requiring a
XSDLL
DLLK (MIN)
locked DLL
t
Minimum CKE low pulse width for self refresh tCKESR
CKE (MIN) + tCK
entry to self refresh exit timing
Valid clocks after self refresh entry or power tCKSRE
greater of 5tCK or 10ns
down entry
t
Valid clocks before self refresh exit, powerCKSRX
greater of 5tCK or 10ns
down exit, or reset exit
Power-Down Timing
t
CKE MIN pulse width
CKE (MIN)
greater of 3tCK or 5ns
t
Command pass disable delay
CPDED
1
t
t
Power-down entry to power exit timing
PD
CKE (MIN)
9 * tREFI
Power-Down Entry Minimum Timing
t
ACTIVATE command to power-down entry
ACTPDEN
1
t
PRECHARGE/PRECHARGE ALL command to
PRPDEN
1
power-down entry
t
REFRESH command to power-down entry
REFPDEN
1
t
MRS command to power-down entry
MRSPDEN
MIN = tMOD (MIN)
READ/READ with auto precharge command to tRDPDEN
MIN = RL + 4 + 1
power-down entry
t
WRITE command to
BL8 (OTF, MRS)
WRPDEN
MIN = WL + 4 + tWR/tCK (AVG)
power-down entry
BC4OTF
t
WRPDEN
MIN = WL + 2 + tWR/tCK (AVG)
BC4MRS
t
WRITE with auto
BL8 (OTF, MRS)
WRAPDEN
MIN = WL + 4 + tWR + 1
precharge command to
BC4OTF
t
power-down entry
BC4MRS
WRAPDEN
MIN = WL + 2 + tWR + 1
Power-Down Exit Timing
DLL on, any valid command, or DLL off to
t
XP
greater of 3tCK or 6ns
commands not requiring locked DLL
Precharge power-down with DLL off to
t
XPDLL
greater of 10tCK or 24ns -commands requiring a locked DLL
ODT Timing
t
RTT turn-on from ODTL on reference
AON
-225
225
RTT turn-off from ODTL off reference
t
AOF
0.3
0.7
Datasheet Version 1.0
-
Max
22
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CK
CK
CK
t
CK
ms
us
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
CK
t
CK
t
t
CK
CK
t
t
CK
CK
t
CK
t
t
CK
t
CK
CK
t
t
CK
t
CK
t
CK
ps
t
CK
(AVG)
IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Parameter / Condition
Asynchronous RTT turn-on delay (power-down
with DLL off)
Asynchronous RTT turn-off delay (power-down
with DLL off)
ODT high time without write command or
with write command and BC4
ODT high time with Write command and BL8
RTT dynamic change skew
First DQS, /DQS rising edge
DQS, /DQS delay
Write leveling setup from rising CK, /CK
crossing to rising DQS, /DQS crossing
Write leveling hold from rising DQS, /DQS
crossing to rising CK, /CK crossing
Write leveling output delay
Write leveling output error
Datasheet Version 1.0
Symbol
Min
Max
Units
t
2
8.5
ns
t
AOFPD
2
8.5
ns
ODTH4
4
-
t
ODTH8
6
Dynamic ODT Timing
-
t
t
0.7
AONPD
ADC
0.3
Write Leveling Timing
WLMRD
40
t
WLDQSEN
25
t
CK
CK
t
CK
(AVG)
-
t
CK
CK
t
t
WLS
165
-
ps
tWLH
165
-
ps
t
0
0
7.5
2
ns
ns
WLO
WLOE
t
23
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IMM2G72D3(L)RVQ8AG
For part number IMM2G72D3(L)RVQ8AG-B125(I)
Table 19 - SPD Information
Byte NO. Description
Note
1.35V
Operation
0
176 / 256 / 0-116
92
1.2
DDR3 SDRAM
72bit Registered DIMM
4Gb 8banks
Row 16 / Col 10
1.35V/1.5V
1.5V
4Rank , x8
ECC, 72bit
2.5ps
1/8 (0.125ns)
1/8 (0.125ns)
1.25ns
5, 6, 7, 8, 9, 10, 11
12
0B
01
04
21
02
19
0B
52
01
08
0A
00
FE
-
00
13.125ns
15ns
13.125ns
69
78
69
6ns
30
13.125ns
35ns
69
11
18
48.125ns
81
260ns
20
260ns
08
7.5ns
3C
7.5ns
3C
30ns
30ns
00
F0
DLL off Mode, RZQ/6, RZQ/7
0-95oC Op. Temp. w/2x
refresh
With TS
Non-Standard SDRAM
83
05
30
31
Number of Serial PD Bytes Written / SPD
Device Size / CRC Coverage
SPD Revision
Key Byte / DRAM Device Type
Key Byte / Module Type
SDRAM Density and Banks
SDRAM Addressing
Module Nominal Voltage, VDD
Module Organization
Module Memory Bus Width
Fine Timebase (FTB) Dividend and Divisor
Medium Timebase (MTB) Dividend
Medium Timebase (MTB) Divisor
SDRAM Minimum Cycle Time (tCKmin)
Reserved
CAS Latencies Supported, Least Significant
Byte
CAS Latencies Supported, Most Significant
Byte
Minimum CAS Latency Time (tAAmin)
Minimum Write Recovery Time (tWRmin)
Minimum /RAS to /CAS Delay Time
(tRCDmin)
Minimum Row Active to Row Active Delay
Time (tRRDmin)
Minimum Row Precharge Time (tRPmin)
Upper Nibbles for tRAS and tRC
Minimum Active to Precharge Time
(tRASmin), LSB
Minimum Active to Active/Refresh Time
(tRCmin), LSB
Minimum
Refresh
Recovery
Time
(tRFCmin), LSB
Minimum
Refresh
Recovery
Time
(tRFCmin), MSB
Minimum Internal Write to Read Command
Delay Time (tWTRmin)
Minimum Internal Read to Precharge
Command Delay Time (tRTPmin)
Upper Nibble for tFAW
Minimum Four Activate Window Delay
Time (tFAWmin), LSB
SDRAM Optional Features
SDRAM Thermal and Refresh Options
32
33
Module Thermal Sensor
SDRAM Device Type
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
Datasheet Version 1.0
24
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Hex
1.5V
1.35V
1.5V
Operation Operation Operation
00
80
A1
IMM2G72D3(L)RVQ8AG
Byte NO. Description
Note
Hex
34-59
60
61
Reserved, General Section
Module Nominal Height
Module Maximum Thickness
00
04
11
62
63
Reference Raw Card Used
Address Mapping from Edge Connector to
DRAM
Heat Spreader Solution
Register vendor ID code (LSB)
Register vendor ID code (MSB)
Register Revision Number
Register Type
Register Control Word Function (RC0/RC1)
Register Control Word Function (RC2/RC3)
Register Control Word Function (RC4/RC5)
Register Control Word Function (RC6/RC7)
Register Control Word Function (RC8/RC9)
Register Control Word Function
(RC10/RC11)
Register Control Word Function
(RC12/RC13)
Register Control Word Function
(RC14/RC15)
Reserved
Module ID: Module Manufacturer’s JEDEC
ID Code
Module ID: Module Manufacturing
Location
Module ID: Module Manufacturing Date
Module ID: Module Serial Number
Cyclical Redundancy Code
Module Part Number
Module Revision Code
DRAM Manufacturer’s JEDEC ID Code
Manufacturer’s Specific Data
Open For Customer Use
18< Height <= 19
1< Tf <=2 (mm); 1< Tb <=2
(mm)
Raw card V0
1 Row of DRAM / 1 Register
Used
Without HS
SSTE32882
Moderate Drive
Moderate Drive
-
64
65
66
67
68
69
70
71
72
73
74
75
76
77-116
117-118
119
120-121
122-125
126-127
128-145
146-147
148-149
150-175
176-255
Datasheet Version 1.0
11
05
00
00
00
FF
00
00
50
55
00
00
00
-
00
-
00
Reserved
00
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
14 52
Reserved
Reserved
Reserved
Reserved
Reserved
25
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45 D8
IMM2G72D3(L)RVQ8AG
Contents
Features
3
Table 1 - Ordering Information for RoHS Compliant Product
4
Table 2 - Operating Voltage
4
Table 3 - Temperature Grade
4
Table 4 - Speed Grade
4
Table 5 - Memory Chip Information
4
Part Number Decoder
5
Table 6 – Addressing
5
Table 7 - Pin Assignment
6
Table 8 - Pin Description
7
Figure 1 – Module Dimension 240 pin DDR3 SDRAM VLP Registered DIMM
8
Table 9 - PCB Dimension
9
Figure 2 – Functional Block Diagram (Page 1 of 3)
10
Figure 3 – Functional Block Diagram (Page 2 of 3)
11
Figure 4 – Functional Block Diagram (Page 3 of 3)
12
Electrical Parameter
13
Table 10 - Absolute Maximum DC Ratings
13
Table 11 - DC Electrical Characteristics and Operating Conditions
13
Table 12 - DC Electrical Characteristics and Input Conditions
14
Table 13 - Input Switching Conditions
15
Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS)
16
Table 15 - Single-Ended Output Driver Characteristics
17
Table 16 - Differential Output Driver Characteristics
18
Table 17 - IDD Specifications with Conditions and Operation Current
19
Table 18 - AC Timing Parameter and Operating Conditions
20
Table 19 - SPD Information
24
Contents
26
List of Tables
27
List of Figures
27
Datasheet Version 1.0
26
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IMM2G72D3(L)RVQ8AG
List of Tables
Table 1 - Ordering Information for RoHS Compliant Product
4
Table 2 - Operating Voltage
4
Table 3 - Temperature Grade
4
Table 4 - Speed Grade
4
Table 5 - Memory Chip Information
4
Table 6 – Addressing
5
Table 7 - Pin Assignment
6
Table 8 - Pin Description
7
Table 9 - PCB Dimension
9
Table 10 - Absolute Maximum DC Ratings
13
Table 11 - DC Electrical Characteristics and Operating Conditions
13
Table 12 - DC Electrical Characteristics and Input Conditions
14
Table 13 - Input Switching Conditions
15
Table 14 - Differential Input Operating Conditions (CK, /CK and DQS, /DQS)
16
Table 15 - Single-Ended Output Driver Characteristics
17
Table 16 - Differential Output Driver Characteristics
18
Table 17 - IDD Specifications with Conditions and Operation Current
19
Table 18 - AC Timing Parameter and Operating Conditions
20
Table 19 - SPD Information
24
List of Figures
Figure 1 – Module Dimension 240 pin DDR3 SDRAM VLP Registered DIMM
8
Figure 2 – Functional Block Diagram (Page 1 of 3)
10
Figure 3 – Functional Block Diagram (Page 2 of 3)
11
Figure 4 – Functional Block Diagram (Page 3 of 3)
12
Datasheet Version 1.0
27
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IMM2G72D3(L)RVQ8AG
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