LT3758
High Input Voltage,
Boost, Flyback, SEPIC and
Inverting Controller
DESCRIPTION
FEATURES
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Wide Input Voltage Range: 5.5V to 100V
Positive or Negative Output Voltage Programming
with a Single Feedback Pin
Current Mode Control Provides Excellent Transient
Response
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
Synchronizeable to an External Clock
Output Overvoltage Protection
Low Shutdown Current < 1μA
Internal 7.2V Low Dropout Voltage Regulator
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
Small 10-Lead DFN (3mm × 3mm) and
MSOPE Packages
The LT®3758 is a wide input range, current mode, DC/DC
controller which is capable of generating either positive or
negative output voltages. It can be configured as either a
boost, flyback, SEPIC or inverting converter. The LT3758
drives a low side external N-channel power MOSFET from
an internal regulated 7.2V supply. The fixed frequency,
current-mode architecture results in stable operation over
a wide range of supply and output voltages.
The operating frequency of LT3758 can be set with an
external resistor over a 100kHz to 1MHz range, and can
be synchronized to an external clock using the SYNC pin.
A minimum operating supply voltage of 5.5V, and a low
shutdown quiescent current of less than 1μA, make the
LT3758 ideally suited for battery-powered systems.
The LT3758 features soft-start and frequency foldback
functions to limit inductor current during start-up and
output short-circuit.
APPLICATIONS
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The device is available in a small 10-lead DFN (3mm × 3mm)
or MSOPE package.
Automotive
Telecom
Industrial
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Patents pending.
TYPICAL APPLICATION
12V Output Nonisolated Flyback Power Supply
VIN
36V TO
72V
D1
CIN
2.2μF
100V
X7R
0.022μF
100V
1M
6.2k
T1
1,2,3
(SERIES)
VIN
SW
LT3758
GATE
SYNC
M1
105k
1%
SENSE
RT
SS
63.4k
200kHz
4,5,6
(PARALLEL)
DSN
SHDN/UVLO
44.2k
VOUT
12V
1.2A
FBX
GND INTVCC
VC
1N4148
5.1Ω
0.47μF
100pF
10k
10nF
CVCC
4.7μF
10V
X5R
0.030Ω
15.8k
1%
COUT
47μF
X5R
3758 TA01
3758f
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LT3758
ABSOLUTE MAXIMUM RATINGS
(Note 1)
VIN, SHDN/UVLO .....................................................100V
INTVCC .................................................... VIN + 0.3V, 20V
GATE .........................................................INTVCC + 0.3V
SYNC ..........................................................................8V
VC, SS.........................................................................3V
RT ............................................................................................... 1.5V
SENSE....................................................................±0.3V
FBX ................................................................. –6V to 6V
Operating Temperature Range
(Note 2) ............................................. –40°C to 125°C
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 125°C
PIN CONFIGURATION
TOP VIEW
TOP VIEW
1
10 VIN
FBX
2
9 SHDN/UVLO
SS
3
RT
4
8 INTVCC
7 GATE
SYNC
5
6 SENSE
VC
11
VC
FBX
SS
RT
SYNC
1
2
3
4
5
11
10
9
8
7
6
VIN
SHDN/UVLO
INTVCC
GATE
SENSE
MSE PACKAGE
10-LEAD PLASTIC MSOP
DD PACKAGE
10-LEAD (3mm s 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
TJMAX = 125°C, θJA = 40°C/W
EXPOSED PAD (PIN 11) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3758EDD#PBF
LT3758EDD#TRPBF
LDNK
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3758IDD#PBF
LT3758IDD#TRPBF
LDNK
10-Lead (3mm × 3mm) Plastic DFN
–40°C to 125°C
LT3758EMSE#PBF
LT3758EMSE#TRPBF
LTDNM
10-Lead (3mm × 3mm) Plastic MSOP
–40°C to 125°C
LT3758IMSE #PBF
LT3758IMSE#TRPBF
LTDNM
10-Lead (3mm × 3mm) Plastic MSOP
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3758f
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LT3758
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
VIN Operating Range
TYP
5.5
MAX
UNITS
100
V
VIN Shutdown IQ
SHDN/UVLO = 0V
SHDN/UVLO = 1.15V
0.1
1
6
μA
μA
VIN Operating IQ
VC = 0.3V, RT = 41.2k
1.6
2.2
mA
VIN Operating IQ with Internal LDO Disabled
VC = 0.3V, RT = 41.2k, INTVCC = 7.5V
350
400
μA
110
120
mV
l
SENSE Current Limit Threshold
SENSE Input Bias Current
100
Current Out of Pin
–65
μA
Error Amplifier
FBX Regulation Voltage (VFBX(REG))
FBX > 0V (Note 3)
FBX < 0V (Note 3)
FBX Overvoltage Lockout
FBX > 0V (Note 4)
FBX < 0V (Note 4)
FBX Pin Input Current
FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3)
Transconductance gm (ΔIVC /ΔFBX)
(Note 3)
VC Output Impedance
(Note 3)
VFBX Line Regulation (ΔVFBX /[ΔVIN • VFBX(REG)])
FBX > 0V, 5.5V < VIN < 100V (Notes 3, 6)
FBX < 0V, 5.5V < VIN < 100V (Notes 3, 6)
l
l
1.569
–0.816
1.6
–0.800
1.631
–0.784
V
V
6
7
8
11
10
14
%
%
70
100
10
nA
nA
–10
230
μS
5
0.006
0.005
VC Current Mode Gain (ΔVVC /ΔVSENSE)
MΩ
0.025
0.03
%/V
%/V
5.5
V/V
VC Source Current
VC = 1.5V
–15
μA
VC Sink Current
FBX = 1.7V
FBX = –0.85V
12
11
μA
μA
Oscillator
Switching Frequency
RT = 41.2k to GND, FBX = 1.6V
RT = 140k to GND, FBX = 1.6V
RT = 10.5k to GND, FBX = 1.6V
RT Voltage
FBX = 1.6V
270
300
100
1000
330
kHz
kHz
kHz
1.2
V
Minimum Off-Time
220
ns
Minimum On-Time
220
ns
SYNC Input Low
0.4
SYNC Input High
SS Pull-Up Current
1.5
SS = 0V, Current Out of Pin
–10
μA
Low Dropout Regulator
l
INTVCC Regulation Voltage
INTVCC Undervoltage Lockout Threshold
Falling INTVCC
UVLO Hysteresis
7
7.2
7.4
V
4.3
4.5
0.5
4.7
V
V
INTVCC Overvoltage Lockout Threshold
17.5
INTVCC Current Limit
VIN = 100V
VIN = 20V
11
16
50
INTVCC Load Regulation (ΔVINTVCC / VINTVCC)
0 < IINTVCC < 10mA, VIN = 8V
–1
–0.4
INTVCC Line Regulation (ΔVINTVCC / [ΔVIN • VINTVCC])
8V < VIN < 100V
Dropout Voltage (VIN – VINTVCC)
VIN = 6V, IINTVCC = 10mA
0.005
500
V
22
mA
mA
%
0.02
%/V
mV
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LT3758
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, SHDN/UVLO = 24V, SENSE = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
INTVCC Current in Shutdown
SHDN/UVLO = 0V, INTVCC = 8V
TYP
MAX
16
INTVCC Voltage to Bypass Internal LDO
UNITS
μA
7.5
V
1.27
V
0.4
V
Logic Inputs
l
SHDN/UVLO Threshold Voltage Falling
VIN = INTVCC = 8V
SHDN/UVLO Input Low Voltage
IVIN Drops Below 1μA
SHDN/UVLO Pin Bias Current Low
SHDN/UVLO = 1.15V
2
2.5
μA
SHDN/UVLO Pin Bias Current High
SHDN/UVLO = 1.33V
10
100
nA
t r Gate Driver Output Rise Time
CL = 3300pF (Note 5), INTVCC = 7.5V
22
ns
t f Gate Driver Output Fall Time
CL = 3300pF (Note 5), INTVCC = 7.5V
20
ns
1.17
1.7
1.22
Gate Driver
Gate Output Low (VOL)
Gate Output High (VOH)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3758E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
0.05
INTVCC
–0.05
V
V
LT3758I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 3: The LT3758 is tested in a feedback loop which servos VFBX to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
Note 4: FBX overvoltage lockout is measured at VFBX(OVERVOLTAGE) relative
to regulated VFBX(REG).
Note 5: Rise and fall times are measured at 10% and 90% levels.
Note 6: SHDN/UVLO = 1.33V when VIN = 5.5V.
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LT3758
TYPICAL PERFORMANCE CHARACTERISTICS
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
–792
1.604
VIN = 100V
1.602
1.600
REGULATED FEEDBACK VOLTAGE (mV)
REGULATED FEEDBACK VOLTAGE (V)
TA = 25°C, unless otherwise noted.
VIN = 24V
1.598
VIN = 8V
1.596
1.594
VIN = INTVCC = 5.5V
1.592
1.590
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
–794
VIN = INTVCC = 5.5V
–796
VIN = 8V
–798
–800
VIN = 100V
VIN = 24V
–802
–804
–50
–25
50
25
0
75
TEMPERATURE (°C)
3758 G01
100
125
3758 G02
Quiescent Current
vs Temperature, VIN
Dynamic Quiescent Current
vs Switching Frequency
1.8
35
CGATE = 3300pF
30
QUIESCENT CURRENT (mA)
VIN = 100V
1.7
25
IQ(mA)
VIN = 24V
1.6
VIN = INTVCC = 5.5V
20
15
10
1.5
5
1.4
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
0
125
0 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3758 G03
3758 G04
Normalized Switching
Frequency vs FBX
RT vs Switching Frequency
120
RT (kΩ)
NORMALIZED FREQUENCY (%)
1000
100
10
0 100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3758 G05
100
80
60
40
20
0
–0.8
–0.4
0
0.4
0.8
FBX VOLTAGE (V)
1.2
1.6
3758 G06
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LT3758
TYPICAL PERFORMANCE CHARACTERISTICS
Switching Frequency
vs Temperature
325
120
315
SENSE THRESHOLD (mV)
SWITCHING FREQUENCY (kHz)
SENSE Current Limit Threshold
vs Temperature
RT = 41.2k
320
TA = 25°C, unless otherwise noted.
310
305
300
295
290
285
115
110
105
100
280
275
–50
–25
0
25
50
75
TEMPERATURE (°C)
100
95
–50
125
–25
50
25
0
75
TEMPERATURE (°C)
125
3758 G08
3758 G07
SHDN/UVLO Threshold
vs Temperature
SENSE Current Limit Threshold
vs Duty Cycle
1.28
SHDN/UVLO VOLTAGE (V)
115
SENSE THRESHOLD (mV)
100
110
105
100
1.26
SHDN/UVLO RISING
1.24
SHDN/UVLO FALLING
1.22
1.20
95
0
20
40
60
DUTY CYCLE (%)
80
1.18
–50
100
–25
50
25
0
75
TEMPERATURE (°C)
3758 G09
125
3758 G10
SHDN/UVLO Hysteresis Current
vs Temperature
SHDN/UVLO Current vs Voltage
2.4
50
40
2.2
ISHDN/UVLO (μA)
SHDN/UVLO CURRENT (μA)
100
30
20
2.0
1.8
10
0
0
20
40
60
80
SHDN/UVLO VOLTAGE (V)
100
3758 G11
1.6
–50
–25
50
25
0
75
TEMPERATURE (°C)
100
125
3758 G12
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LT3758
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
INTVCC Minimum Output
Current vs VIN
INTVCC vs Temperature
7.4
45
TJ = 125°C
INTVCC CURRENT (mA)
40
INTVCC (V)
7.3
7.2
7.1
35
30
25
INTVCC = 4.7V
20
15
10
INTVCC = 6V
5
7.0
–50
0
50
25
0
75
TEMPERATURE (°C)
–25
1
125
100
10
VIN (V)
100
3758 G14
3758 G13
INTVCC Load Regulation
INTVCC Line Regulation
7.30
7.3
VIN = 8V
INTVCC VOLTAGE (V)
7.25
7.1
7
7.20
7.15
6.9
7.10
6.8
0
5
15
10
INTVCC LOAD (mA)
20
10 20 30 40 50 60 70 80 90 100
VIN (V)
3758 G16
0
25
3758 G15
INTVCC Dropout Voltage
vs Current, Temperature
900
125°C
800
DROPOUT VOLTAGE (mV)
INTVCC VOLTAGE (V)
7.2
700
75°C
600
25°C
500
400
0°C
300
–50°C
200
100
0
0
2
4
6
8
10
INTVCC LOAD (mA)
3758 G17
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LT3758
TYPICAL PERFORMANCE CHARACTERISTICS
Gate Drive Rise
and Fall Time vs CL
90
TA = 25°C, unless otherwise noted.
Gate Drive Rise
and Fall Time vs INTVCC
30
INTVCC = 7.2V
CL = 3300pF
80
25
RISE TIME
70
20
FALL TIME
RISE TIME
TIME (ns)
TIME (ns)
60
50
40
30
FALL TIME
15
10
20
5
10
0
0
5
10
15
20
25
30
0
3
CL (nF)
6
9
12
15
INTVCC (V)
3758 G18
3758 G19
FBX Frequency Foldback
Waveforms During Overcurrent
Typical Start-Up Waveforms
VIN = 48V
VIN = 48V
VOUT
20V/DIV
VOUT
10V/DIV
VSW
50V/DIV
IL1A + IL1B
1A/DIV
IL1A + IL1B
2A/DIV
2ms/DIV
3758 G20
SEE TYPICAL APPLICATION: 18V TO 72V INPUT,
24V OUTPUT SEPIC CONVERTER
50μs/DIV
3758 G21
SEE TYPICAL APPLICATION: 18V TO 72V INPUT,
24V OUTPUT SEPIC CONVERTER
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LT3758
PIN FUNCTIONS
VC (Pin 1): Error Amplifier Compensation Pin. Used to
stabilize the voltage loop with an external RC network.
FBX (Pin 2): Positive and Negative Feedback Pin. Receives the feedback voltage from the external resistor
divider across the output. Also modulates the switching
frequency during start-up and fault conditions when FBX
is close to GND.
SS (Pin 3): Soft-Start Pin. This pin modulates compensation pin voltage (VC) clamp. The soft-start interval is set
with an external capacitor. The pin has a 10μA (typical)
pull-up current source to an internal 2.5V rail. The softstart pin is reset to GND by an undervoltage condition
at SHDN/UVLO, an INTVCC undervoltage or overvoltage
condition or an internal thermal lockout.
RT (Pin 4): Switching Frequency Adjustment Pin. Set the
frequency using a resistor to GND. Do not leave this pin
open.
SYNC (Pin 5): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an RT resistor should be chosen to
program a switching frequency 20% slower than the SYNC
pulse frequency. Tie the SYNC pin to GND if this feature is
not used. SYNC is ignored when FBX is close to GND.
SENSE (Pin 6): The Current Sense Input for the Control
Loop. Kelvin connect this pin to the positive terminal of
the switch current sense resistor in the source of the NFET.
The negative terminal of the current sense resistor should
be connected to GND plane close to the IC.
GATE (Pin 7): N-Channel MOSFET Gate Driver Output.
Switches between INTVCC and GND. Driven to GND when
IC is shut down, during thermal lockout or when INTVCC
is above or below the overvoltage or UV thresholds,
respectively.
INTVCC (Pin 8): Regulated Supply for Internal Loads and
Gate Driver. Supplied from VIN and regulated to 7.2V (typical). INTVCC must be bypassed with a minimum of 4.7μF
capacitor placed close to pin. INTVCC can be connected
directly to VIN, if VIN is less than 17.5V. INTVCC can also
be connected to a power supply whose voltage is higher
than 7.5V, and lower than VIN, provided that supply does
not exceed 17.5V.
SHDN/UVLO (Pin 9): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
is okay to enable switching. Rising hysteresis is generated
by the external resistor divider and an accurate internal
2μA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
reduce VIN quiescent current below 1μA.
VIN (Pin 10): Input Supply Pin. Must be locally bypassed
with a 0.22μF, or larger, capacitor placed close to the
pin.
Exposed Pad (Pin 11): Ground. This pin also serves
as the negative terminal of the current sense resistor.
The Exposed Pad must be soldered directly to the local
ground plane.
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9
LT3758
BLOCK DIAGRAM
CDC
L1
D1
VOUT
•
VIN
R4
+
R3
CIN
L2
•
9
A10
IS1
2μA
2.5V
IS3
IS2
10μA
VC
1
–
+
VIN
1.22V
INTERNAL
REGULATOR
AND UVLO
G4
RC
CC1
1.72V
–
+
17.5V
+
A9
–
UVLO
Q3
CC2
G3
A11
CURRENT
LIMIT
7.2V LDO
8
+
–
TSD
165˚C
–0.88V
A12
VC
Q2
1.6V
FBX
FBX
INTVCC
A8
CVCC
5V UP
4.5V DOWN
DRIVER
G6
–
+
COUT2
R1
10
SHDN/UVLO
2.5V
R2 + COUT1
FBX
SR1
–
+A7
G5
R
GATE
G2
O
7
S
M1
PWM
COMPARATOR
+
A1
–
A6
VISENSE
SLOPE
–
+
110mV
SENSE
2
–0.8V
RAMP
+
A2
–
1.25V
RAMP
GENERATOR
–
+A3
G1
1.25V
+
+
–
SS
GND
RSENSE
100kHz-1MHz
OSCILLATOR
A4
Q1
FREQ
PROG
RT
SYNC
5
CSS
6
11
FREQUENCY
FOLDBACK
3
+
A5
–
4
3758 F01
RT
Figure 1. LT3758 Block Diagram Working as a SEPIC Converter
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LT3758
APPLICATIONS INFORMATION
Main Control Loop
The LT3758 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Operation can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1) and
turns on the external power MOSFET switch M1 through
driver G2. The switch current flows through the external
current sensing resistor RSENSE and generates a voltage
proportional to the switch current. This current sense
voltage VISENSE (amplified by A5) is added to a stabilizing
slope compensation ramp and the resulting sum (SLOPE)
is fed into the positive terminal of the PWM comparator A7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
The LT3758 has a switch current limit function. The current
sense voltage is input to the current limit comparator A6.
If the SENSE pin voltage is higher than the sense current
limit threshold VSENSE(MAX) (110mV, typical), A6 will reset
SR1 and turn off M1 immediately.
The LT3758 is capable of generating either positive or
negative output voltage with a single FBX pin. It can
be configured as a boost, flyback or SEPIC converter
to generate positive output voltage, or as an inverting
converter to generate negative output voltage. When
configured as a SEPIC converter, as shown in Figure 1,
the FBX pin is pulled up to the internal bias voltage of 1.6V
by a voltage divider (R1 and R2) connected from VOUT to
GND. Comparator A2 becomes inactive and comparator
A1 performs the inverting amplification from FBX to VC.
When the LT3758 is in an inverting configuration, the
FBX pin is pulled down to –0.8V by a voltage divider
connected from VOUT to GND. Comparator A1 becomes
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.
The LT3758 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
Programming Turn-On and Turn-Off Thresholds with
the SHDN/UVLO Pin
The SHDN/UVLO pin controls whether the LT3758 is
enabled or is in shutdown state. A micropower 1.22V
reference, a comparator A10 and a controllable current
source IS1 allow the user to accurately program the supply voltage at which the IC turns on and off. The falling
value can be accurately set by the resistor dividers R3
and R4. When SHDN/UVLO is above 0.7V, and below the
1.22V threshold, the small pull-down current source IS1
(typical 2μA) is active.
The purpose of this current is to allow the user to program
the rising hysteresis. The Block Diagram of the comparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
(R3 + R4)
R4
VVIN, RISING = 2µA • R3 + VIN, FALLING
VVIN, FALLING = 1.22 •
For applications where the SHDN/UVLO pin is only used
as a logic input, the SHDN/UVLO pin can be connected
directly to the input voltage VIN through a 1k resistor for
always-on operation.
3758f
11
LT3758
APPLICATIONS INFORMATION
An internal, low dropout (LDO) voltage regulator produces
the 7.2V INTVCC supply which powers the gate driver, as
shown in Figure 1. The LT3758 contains an undervoltage
lockout comparator A8 and an overvoltage lockout comparator A9 for the INTVCC supply. The INTVCC undervoltage
(UV) threshold is 4.5V (typical), with 0.5V hysteresis, to
ensure that the MOSFETs have sufficient gate drive voltage
before turning on. The logic circuitry within the LT3758 is
also powered from the internal INTVCC supply.
The INTVCC overvoltage threshold is set to be 17.5V
(typical) to protect the gate of the power MOSFET. When
INTVCC is below the UV threshold, or above the overvoltage threshold, the GATE pin will be forced to GND and the
soft-start operation will be triggered.
The INTVCC regulator must be bypassed to ground immediately adjacent to the IC pins with a minimum of 4.7μF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
driver.
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the power MOSFET.
The on-chip power dissipation can be a significant concern
when a large power MOSFET is being driven at a high
frequency and the VIN voltage is high. It is important to
limit the power dissipation through selection of MOSFET
and/or operating frequency so the LT3758 does not exceed
its maximum junction temperature rating. The junction
temperature TJ can be estimated using the following
equations:
TJ = TA + PIC • θJA
The LT3758 uses packages with an Exposed Pad for enhanced thermal conduction. With proper soldering to the
Exposed Pad on the underside of the package and a full
copper plane underneath the device, thermal resistance
(θJA) will be about 43°C/W for the DD package and 40°C/W
for the MSE package. For an ambient board temperature of
TA = 70°C and maximum junction temperature of 125°C,
the maximum IDRIVE (IDRIVE(MAX)) of the DD package can
be calculated as:
IDRIVE(MAX ) =
Based on the preceding equation and the INTVCC Minimum
Output Current vs VIN graph, the user can calculate the
maximum MOSFET gate charge the LT3758 can drive at
a given VIN and switch frequency. A plot of the maximum
QG vs VIN at different frequencies to guarantee a minimum
4.7V INTVCC is shown in Figure 2.
140
300kHz
120
100
80
60
TA = ambient temperature
40
θJA = junction-to-ambient thermal resistance
20
PIC = IC power consumption
= VIN • (IQ + IDRIVE)
IQ = VIN operation IQ = 1.6mA
IDRIVE = average gate drive current = f • QG
( TJ − T A )
1.28 W
− IQ =
− 1.6mA
VIN
(θ JA • VIN )
The LT3758 has an internal INTVCC IDRIVE current limit
function to protect the IC from excessive on-chip power
dissipation. The IDRIVE current limit decreases as the VIN
increases (see the INTVCC Minimum Output Current vs VIN
graph in the Typical Performance Characteristics section).
If IDRIVE reaches the current limit, INTVCC voltage will fall
and may trigger the soft-start.
QG (nC)
INTVCC Regulator Bypassing and Operation
1MHz
0
1
10
VIN (V)
100
3758 F02
Figure 2. Recommended Maximum QG vs VIN at Different
Frequencies to Ensure INTVCC Higher Than 4.7V
f = switching frequency
QG = power MOSFET total gate charge
3758f
12
LT3758
APPLICATIONS INFORMATION
As illustrated in Figure 2, a trade-off between the operating
frequency and the size of the power MOSFET may be needed
in order to maintain a reliable IC junction temperature.
Prior to lowering the operating frequency, however, be
sure to check with power MOSFET manufacturers for their
most recent low QG, low RDS(ON) devices. Power MOSFET
manufacturing technologies are continually improving, with
newer and better performance devices being introduced
almost yearly.
An effective approach to reduce the power consumption
of the internal LDO for gate drive is to tie the INTVCC pin
to an external voltage source high enough to turn off the
internal LDO regulator.
If the input voltage VIN does not exceed the absolute
maximum rating of both the power MOSFET gate-source
voltage (VGS) and the INTVCC overvoltage lockout threshold
voltage (17.5V), the INTVCC pin can be shorted directly
to the VIN pin. In this condition, the internal LDO will be
turned off and the gate driver will be powered directly
from the input voltage VIN. With the INTVCC pin shorted to
VIN, however, a small current (around 16μA) will load the
INTVCC in shutdown mode. For applications that require
the lowest shutdown mode input supply current, do not
connect the INTVCC pin to VIN.
or not the INTVCC pin is connected to an external voltage
source, it is always necessary to have the driver circuitry
bypassed with a 4.7μF low ESR ceramic capacitor to ground
immediately adjacent to the INTVCC and GND pins.
Operating Frequency and Synchronization
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
between efficiency and component size. Low frequency
operation improves efficiency by reducing gate drive current and MOSFET and diode switching losses. However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loop compensation. The LT3758 uses a constant-frequency
architecture that can be programmed over a 100kHz to
1000kHz range with a single external resistor from the
RT pin to ground, as shown in Figure 1. The RT pin must
have an external resistor to GND for proper operation of
the LT3758. A table for selecting the value of RT for a given
operating frequency is shown in Table 1.
Table 1. Timing Resistor (RT ) Value
SWITCHING FREQUENCY (kHz)
RT (kΩ)
100
140
200
63.4
300
41.2
400
30.9
500
24.3
600
19.6
700
16.5
800
14
900
12.1
1000
10.5
In SEPIC or flyback applications, the INTVCC pin can be
connected to the output voltage VOUT through a blocking
diode, as shown in Figure 3, if VOUT meets the following
conditions:
1. VOUT < VIN (pin voltage)
2. VOUT < 17.5V
3. VOUT < maximum VGS rating of power MOSFET
A resistor RVCC can be connected, as shown in Figure 3, to
limit the inrush current from VOUT. Regardless of whether
LT3758
DVCC
INTVCC
RVCC
VOUT
CVCC
4.7μF
GND
3758 F03
Figure 3. Connecting INTVCC to VOUT
3758f
13
LT3758
APPLICATIONS INFORMATION
The operating frequency of the LT3758 can be synchronized
to an external clock source. By providing a digital clock
signal into the SYNC pin, the LT3758 will operate at the
SYNC clock frequency. If this feature is used, an RT resistor
should be chosen to program a switching frequency 20%
slower than SYNC pulse frequency. The SYNC pulse should
have a minimum pulse width of 200ns. Tie the SYNC pin
to GND if this feature is not used.
Duty Cycle Consideration
Switching duty cycle is a key variable defining converter
operation. As such, its limits must be considered. Minimum
on-time is the smallest time duration that the LT3758 is
capable of turning on the power MOSFET. This time is
generally about 220ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3758 keeps the power switch off for at least
220ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Soft-Start
The LT3758 contains several features to limit peak switch
currents and output voltage (VOUT) overshoot during
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since VOUT is far from its final value,
the feedback loop is saturated and the regulator tries to
charge the output capacitor as quickly as possible, resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3758 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its final value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
section. The inductor current IL slewing rate is limited by
the soft-start function.
Besides start-up (with SHDN/UVLO), soft-start can also
be triggered by the following faults:
1. INTVCC > 17.5V
Programming the Output Voltage
2. INTVCC < 4.5V
The output voltage VOUT is set by a resistor divider, as
shown in Figure 1. The positive and negative VOUT are set
by the following equations:
3. Thermal lockout
⎛ R2 ⎞
VOUT, POSITIVE = 1.6 V • ⎜ 1+ ⎟
⎝ R1⎠
⎛ R2 ⎞
VOUT, NEGATIVE = –0.8 V • ⎜ 1+ ⎟
⎝ R1⎠
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
Any of these three faults will cause the LT3758 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10μA current source IS2 starts
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
TSS = CSS •
1.25V
10µA
3758f
14
LT3758
APPLICATIONS INFORMATION
FBX Frequency Foldback
When VOUT is very low during start-up or a GND fault on
the output, the switching regulator must operate at low
duty cycles to maintain the power switch current within
the current limit range, since the inductor current decay
rate is very low during switch off time. The minimum ontime limitation may prevent the switcher from attaining a
sufficiently low duty cycle at the programmed switching
frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3758 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normalized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
During frequency foldback, external clock synchronization is disabled to prevent interference with frequency
reducing operation.
Thermal Lockout
If LT3758 die temperature reaches 165°C (typical), the
part will go into thermal lockout. The power switch will
be turned off. A soft-start operation will be triggered. The
part will be enabled again when the die temperature has
dropped by 5°C (nominal).
Loop Compensation
Loop compensation determines the stability and transient
performance. The LT3758 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3758, a series resistor-capacitor
network is usually connected from the VC pin to GND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in parallel with the RC compensation network to attenuate the
VC voltage ripple induced from the output voltage ripple
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
SENSE Pin Programming
For control and protection, the LT3758 measures the
power MOSFET current by using a sense resistor (RSENSE)
between GND and the MOSFET source. Figure 4 shows a
typical waveform of the sense voltage (VSENSE) across the
sense resistor. It is important to use Kelvin traces between
the SENSE pin and RSENSE, and to place the IC GND as
close as possible to the GND terminal of the RSENSE for
proper operation.
Due to the current limit function of the SENSE pin, RSENSE
should be selected to guarantee that the peak current sense
voltage VSENSE(PEAK) during steady state normal operation
is lower than the SENSE current limit threshold (see the
Electrical Characteristics table). Given a 20% margin,
VSENSE(PEAK) is set to be 80mV. Then, the maximum
VSENSE
$VSENSE = CvVSENSE(MAX)
VSENSE(MAX)
VSENSE(PEAK)
t
DTS
TS
3758 F04
Figure 4. The Sense Voltage During a Switching Cycle
3758f
15
LT3758
APPLICATIONS INFORMATION
switch ripple current percentage can be calculated using
the following equation:
χ=
ΔVSENSE
80mV − 0.5 • ΔVSENSE
χ is used in subsequent design examples to calculate inductor value. ΔVSENSE is the ripple voltage across RSENSE.
The LT3758 switching controller incorporates 100ns timing
interval to blank the ringing on the current sense signal
immediately after M1 is turned on. This ringing is caused
by the parasitic inductance and capacitance of the PCB
trace, the sense resistor, the diode, and the MOSFET. The
100ns timing interval is adequate for most of the LT3758
applications. In the applications that have very large and
long ringing on the current sense signal, a small RC filter
can be added to filter out the excess ringing. Figure 5
shows the RC filter on the SENSE pin. It is usually sufficient to choose 22Ω for RFLT and 2.2nF to 10nF for CFLT.
Keep RFLT’s resistance low. Remember that there is 65μA
(typical) flowing out of the SENSE pin. Adding RFLT will
affect the SENSE current limit threshold:
VSENSE_ILIM = 110mV – 65μA • RFLT
M1
GATE
APPLICATION CIRCUITS
The LT3758 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
Boost Converter: Switch Duty Cycle and Frequency
The LT3758 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost converters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
The conversion ratio as a function of duty cycle is
VOUT
1
=
VIN 1− D
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT) and the input voltage (VIN). The maximum
duty cycle (DMAX) occurs when the converter has the
minimum input voltage:
LT3758
RFLT
DMAX =
SENSE
GND
CFLT
RSENSE
3758 F05
VOUT − VIN(MIN)
VOUT
Discontinuous conduction mode (DCM) provides higher
conversion ratios at a given frequency at the cost of reduced
efficiencies and higher switching currents.
Figure 5. The RC Filter on the SENSE Pin
Boost Converter: Inductor and Sense Resistor Selection
For the boost topology, the maximum average inductor
current is:
1
IL(MAX ) = IO(MAX ) •
1− DMAX
Then, the ripple current can be calculated by:
ΔIL = χ • IL(MAX ) = χ • IO(MAX ) •
1
1− DMAX
3758f
16
LT3758
APPLICATIONS INFORMATION
The constant χ in the preceding equation represents the
percentage peak-to-peak ripple current in the inductor,
relative to IL(MAX).
The inductor ripple current has a direct effect on the choice
of the inductor value. Choosing smaller values of ΔIL
requires large inductances and reduces the current loop
gain (the converter will approach voltage mode). Accepting
larger values of ΔIL provides fast transient response and
allows the use of low inductances, but results in higher input
current ripple and greater core losses. It is recommended
that χ fall within the range of 0.2 to 0.6.
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor,
the inductor value of the boost converter can be determined
using the following equation:
L=
VIN(MIN)
ΔIL • f
• DMAX
The peak and RMS inductor current are:
⎛ χ⎞
IL(PEAK ) = IL(MAX ) • ⎜ 1+ ⎟
⎝ 2⎠
χ2
IL(RMS) = IL(MAX ) • 1+
12
Based on these equations, the user should choose the
inductors having sufficient saturation and RMS current
ratings.
Set the sense voltage at IL(PEAK) to be the minimum of the
SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =
80 mV
IL(PEAK )
Boost Converter: Power MOSFET Selection
Important parameters for the power MOSFET include the
drain-source voltage rating (VDS), the threshold voltage
(VGS(TH)), the on-resistance (RDS(ON)), the gate to source
and gate to drain charges (QGS and QGD), the maximum
drain current (ID(MAX)) and the MOSFET’s thermal
resistances (RθJC and RθJA).
The power MOSFET will see full output voltage, plus a
diode forward voltage, and any additional ringing across
its drain-to-source during its off-time. It is recommended
to choose a MOSFET whose BVDSS is higher than VOUT by
a safety margin (a 10V safety margin is usually sufficient).
The power dissipated by the MOSFET in a boost converter is:
PFET = I2L(MAX) • RDS(ON) • DMAX + 2 • V2OUT • IL(MAX)
• CRSS • f/1A
The first term in the preceding equation represents the
conduction losses in the device, and the second term, the
switching loss. CRSS is the reverse transfer capacitance,
which is usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
MOSFET, its junction temperature can be obtained using
the following equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current, and the peak current is equal to:
⎛ χ⎞
ID(PEAK ) = IL(PEAK ) = ⎜ 1+ ⎟ • IL(MAX )
⎝ 2⎠
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT by a safety margin (a 10V
safety margin is usually sufficient).
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
3758f
17
LT3758
APPLICATIONS INFORMATION
The RθJA to be used in this equation normally includes the
RθJC for the device plus the thermal resistance from the board
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
these three parameters (ESR, ESL and bulk C) on the output
voltage ripple waveform for a typical boost converter is
illustrated in Figure 6.
tON
tOFF
$VCOUT
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
3758 F06
Figure 6. The Output Ripple Waveform of a Boost Converter
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔVESR and the charging/discharging ΔVCOUT. For the purpose of simplicity, we will choose
2% for the maximum output ripple, to be divided equally
between ΔVESR and ΔVCOUT. This percentage ripple will
change, depending on the requirements of the application, and the following equations can easily be modified.
For a 1% contribution to the total ripple voltage, the ESR
of the output capacitor can be determined using the following equation:
ESRCOUT ≤
0.01• VOUT
ID(PEAK )
For the bulk C component, which also contributes 1% to
the total ripple:
COUT ≥
IO(MAX )
0.01• VOUT • f
IRMS(COUT) ≥ IO(MAX ) •
DMAX
1− DMAX
Multiple capacitors are often paralleled to meet ESR requirements. Typically, once the ESR requirement is satisfied, the
capacitance is adequate for filtering and has the required
RMS current rating. Additional ceramic capacitors in parallel are commonly used to reduce the effect of parasitic
inductance in the output capacitor, which reduces high
frequency switching noise on the converter output.
Boost Converter: Input Capacitor Selection
VOUT
(AC)
$VESR
The output capacitor in a boost regulator experiences high
RMS ripple currents, as shown in Figure 6. The RMS ripple
current rating of the output capacitor can be determined
using the following equation:
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current waveform is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typically in the range of 10μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
The RMS input capacitor ripple current for a boost converter is:
IRMS(CIN) = 0.3 • ΔIL
FLYBACK CONVERTER APPLICATIONS
The LT3758 can be configured as a flyback converter for the
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Figure 7 shows
a simplified flyback converter.
The flyback converter has a very low parts count for multiple outputs, and with prudent selection of turns ratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
the high peak currents, high peak voltages and consequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
3758f
18
LT3758
APPLICATIONS INFORMATION
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to continuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compensation, and the disadvantage of higher peak-to-average
current and lower efficiency.
SUGGESTED
RCD SNUBBER
VIN
–
+
CIN
VSN
+
CSN
RSN
LS
LP
• Lower MOSFET RMS current ISW(RMS), but higher
MOSFET VDS peak voltage
D
NP:NS
ID
+
+
COUT
–
DSN
LT3758
SENSE
• Lower diode peak reverse voltage, but higher diode
RMS current ID(RMS)
• Higher transformer turns ratio (NP/NS)
ISW
GATE
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when selecting the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
M
+
VDS
–
RSENSE
GND
3758 F07
Figure 7. A Simplified Flyback Converter
Flyback Converter: Switch Duty Cycle and Turns Ratio
The flyback converter conversion ratio in the continuous
mode operation is:
VOUT NS D
=
•
VIN NP 1− D
Where NS/NP is the second to primary turns ratio.
Figure 8 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
period TS, three subintervals occur: DTS, D2TS, D3TS.
During DTS, M is on, and D is reverse-biased. During
D2TS, M is off, and LS is conducting current. Both LP and
LS currents are zero during D3TS.
The choice,
D
1
=
D + D2 3
(for discontinuous mode operation with a given D3) gives
the power MOSFET the lowest power stress (the product
of RMS current and peak voltage). The choice,
D
2
=
D + D2 3
(for discontinuous mode operation with a given D3) gives
the diode the lowest power stress (the product of RMS
current and peak voltage). An extreme high or low duty
cycle results in high power stress on the MOSFET or diode,
and reduces efficiency. It is recommended to choose a
duty cycle between 20% and 80%.
VDS
ISW
ISW(MAX)
The flyback converter conversion ratio in the discontinuous mode operation is:
ID
VOUT NS D
=
•
VIN NP D2
According to the preceding equations, the user has relative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
ID(MAX)
DTS
D2TS
TS
t
D3TS
3758 F08
Figure 8. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
3758f
19
LT3758
APPLICATIONS INFORMATION
Flyback Converter: Transformer Design for
Discontinuous Mode Operation
The transformer design for discontinuous mode of operation is chosen as presented here. According to Figure 8,
the minimum D3 (D3MIN) occurs when the the converter
has the minimum VIN and the maximum output power
(POUT). Choose D3MIN to be equal to or higher than 10%
to guarantee the converter is always in discontinuous
mode operation. Choosing higher D3 allows the use of
low inductances but results in higher switch peak current.
The user can choose a DMAX as the start point. Then, the
maximum average primary currents can be calculated by
the following equation:
ILP(MAX ) = ISW(MAX ) =
POUT(MAX )
DMAX • VIN(MIN) • η
where η is the converter efficiency.
If the flyback converter has multiple outputs, POUT(MAX)
is the sum of all the output power.
The maximum average secondary current is:
ILS(MAX ) = ID(MAX ) =
IOUT(MAX )
D2
where
The primary and second inductor values of the flyback
converter transformer can be determined using the following equations:
LP =
LS =
D2MAX • V 2IN(MAX ) • η
2 • POUT(MAX ) • f
D22 •( VOUT + VD)
2 • IOUT(MAX ) • f
The primary to second turns ratio is:
NP
L
= P
NS
LS
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary or
secondary) causes a voltage spike to occur after the MOSFET turn-off. This is increasingly prominent at higher load
currents, where more stored energy must be dissipated.
In some cases a snubber circuit will be required to avoid
overvoltage breakdown at the MOSFET’s drain node. There
are different snubber circuits, and Application Note 19 is
a good reference on snubber design. An RCD snubber is
shown in Figure 7.
The snubber resistor value (RSN) can be calculated by the
following equation:
D2 = 1 – DMAX – D3
the primary and secondary RMS currents are:
ILP(RMS) = 2 • ILP(MAX ) •
DMAX
3
ILS(RMS) = 2 • ILS(MAX ) •
D2
3
According to Figure 8, the primary and secondary peak
currents are:
ILP(PEAK) = ISW(PEAK) = 2 • ILP(MAX)
ILS(PEAK) = ID(PEAK) = 2 • ILS(MAX)
V 2SN − VSN • VOUT •
RSN = 2 •
NP
NS
I2SW(PEAK ) • L LK • f
where VSN is the snubber capacitor voltage. A smaller
VSN results in a larger snubber loss. A reasonable VSN is
2 to 2.5 times of:
VOUT • NP
NS
3758f
20
LT3758
APPLICATIONS INFORMATION
LLK is the leakage inductance of the primary winding,
which is usually specified in the transformer characteristics. LLK can be obtained by measuring the primary
inductance with the secondary windings shorted. The
snubber capacitor value (CCN) can be determined using
the following equation:
CCN =
VSN
ΔVSN • RCN • f
where ΔVSN is the voltage ripple across CCN. A reasonable
ΔVSN is 5% to 10% of VSN. The reverse voltage rating of
DSN should be higher than the sum of VSN and VIN(MAX).
Flyback Converter: Sense Resistor Selection
In a flyback converter, when the power switch is turned on,
the current flowing through the sense resistor (ISENSE) is:
ISENSE = ILP
Set the sense voltage at ILP(PEAK) to be the minimum of
the SENSE current limit threshold with a 20% margin. The
sense resistor value can then be calculated to be:
RSENSE =
80 mV
ILP(PEAK )
Flyback Converter: Power MOSFET Selection
For the flyback configuration, the MOSFET is selected with
a VDC rating high enough to handle the maximum VIN, the
reflected secondary voltage and the voltage spike due to
the leakage inductance. Approximate the required MOSFET
VDC rating using:
BVDSS > VDS(PEAK)
where
VDS(PEAK) = VIN(MAX) + VSN
The power dissipated by the MOSFET in a flyback converter is:
PFET = I2M(RMS) • RDS(ON) + 2 • V2DS(PEAK) • IL(MAX) •
CRSS • f/1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
From a known power dissipated in the power MOSFET, its
junction temperature can be obtained using the following
equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
Flyback Converter: Output Diode Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
Approximate the required peak repetitive reverse voltage
rating VRRM using:
VRRM >
NS
•V
+V
NP IN(MAX ) OUT
The power dissipated by the diode is:
PD = IO(MAX) • VD
and the diode junction temperature is:
TJ = TA + PD • RθJA
The RθJA to be used in this equation normally includes the
RθJC for the device, plus the thermal resistance from the board
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
Flyback Converter: Output Capacitor Selection
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
for the calculation of COUT and ESRCOUT.
The RMS ripple current rating of the output capacitors
in discontinuous operation can be determined using the
following equation:
IRMS(COUT ),DISCONTINUOUS ≥ IO(MAX ) •
4 − (3 • D2)
3 • D2
3758f
21
LT3758
APPLICATIONS INFORMATION
Flyback Converter: Input Capacitor Selection
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
discontinuous operation can be determined using the
following equation:
IRMS(CIN),DISCONTINUOUS ≥
POUT(MAX )
VIN(MIN) • η
•
4 − (3 • DMAX )
3 • DMAX
SEPIC CONVERTER APPLICATIONS
The LT3758 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
VOUT + VD
D
=
VIN
1− D
in continuous conduction mode (CCM).
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
Compared to the flyback converter, the SEPIC converter
has the advantage that both the power MOSFET and the
output diode voltages are clamped by the capacitors (CIN,
CDC and COUT), therefore, there is less voltage ringing
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the inductor L1 is in series
with the input, and the ripple current flowing through the
input capacitor is continuous.
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (VOUT), the input voltage (VIN) and the diode
forward voltage (VD).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
VOUT + VD
VIN(MIN) + VOUT + VD
SEPIC Converter: Inductor and Sense Resistor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but
can also be wound on the same core, since identical voltages are applied to L1 and L2 throughout the switching
cycle.
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
IL1(MAX ) = IIN(MAX ) = IO(MAX ) •
DMAX
1− DMAX
IL2(MAX ) =IO(MAX )
In a SEPIC converter, the switch current is equal to IL1 +
IL2 when the power switch is on, therefore, the maximum
average switch current is defined as:
ISW(MAX ) = IL1(MAX ) + IL 2(MAX ) = IO(MAX ) •
1
1− DMAX
and the peak switch current is:
⎛ χ⎞
1
ISW(PEAK ) = ⎜ 1+ ⎟ • IO(MAX ) •
1− DMAX
⎝ 2⎠
The constant χ in the preceding equations represents the
percentage peak-to-peak ripple current in the switch, relative to ISW(MAX), as shown in Figure 9. Then, the switch
ripple current ΔISW can be calculated by:
ΔISW = χ • ISW(MAX)
The inductor ripple currents ΔIL1 and ΔIL2 are identical:
ΔIL1 = ΔIL2 = 0.5 • ΔISW
The inductor ripple current has a direct effect on the
choice of the inductor value. Choosing smaller values of
3758f
22
LT3758
APPLICATIONS INFORMATION
ΔIL requires large inductances and reduces the current
loop gain (the converter will approach voltage mode).
Accepting larger values of ΔIL allows the use of low inductances, but results in higher input current ripple and
greater core losses. It is recommended that χ falls in the
range of 0.2 to 0.6.
χL 1 =
$ISW = CvISW(MAX)
χL 2 =
ISW(MAX)
t
DTS
TS
3758 F09
Figure 9. The Switch Current Waveform of the SEPIC Converter
Given an operating input voltage range, and having chosen
the operating frequency and ripple current in the inductor, the inductor value (L1 and L2 are independent) of the
SEPIC converter can be determined using the following
equation:
VIN(MIN)
L1= L2 =
•D
0.5 • ΔISW • f MAX
For most SEPIC applications, the equal inductor values
will fall in the range of 1μH to 100μH.
By making L1 = L2, and winding them on the same core, the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
VIN(MIN)
ΔISW • f
• DMAX
This maintains the same ripple current and energy storage
in the inductors. The peak inductor currents are:
IL1(PEAK) = IL1(MAX) + 0.5 • ΔIL1
IL2(PEAK) = IL2(MAX) + 0.5 • ΔIL2
The RMS inductor currents are:
IL1(RMS) = IL1(MAX ) • 1+
χ 2L1
12
ΔIL1
IL1(MAX )
χ 2L2
IL2(RMS) = IL2(MAX ) • 1+
12
where
ISW
L=
where
ΔIL2
IL2 (MAX )
Based on the preceding equations, the user should choose
the inductors having sufficient saturation and RMS current ratings.
In a SEPIC converter, when the power switch is turned on,
the current flowing through the sense resistor (ISENSE) is
the switch current.
Set the sense voltage at ISENSE(PEAK) to be the minimum
of the SENSE current limit threshold with a 20% margin.
The sense resistor value can then be calculated to be:
RSENSE =
80 mV
ISW(PEAK )
SEPIC Converter: Power MOSFET Selection
For the SEPIC configuration, choose a MOSFET with a
VDC rating higher than the sum of the output voltage and
input voltage by a safety margin (a 10V safety margin is
usually sufficient).
The power dissipated by the MOSFET in a SEPIC converter is:
PFET = I2SW(MAX) • RDS(ON) • DMAX
+ 2 • (VIN(MIN) + VOUT)2 • IL(MAX) • CRSS • f/1A
The first term in this equation represents the conduction
losses in the device, and the second term, the switching
loss. CRSS is the reverse transfer capacitance, which is
usually specified in the MOSFET characteristics.
For maximum efficiency, RDS(ON) and CRSS should be
minimized. From a known power dissipated in the power
3758f
23
LT3758
APPLICATIONS INFORMATION
MOSFET, its junction temperature can be obtained using
the following equation:
TJ = TA + PFET • θJA = TA + PFET • (θJC + θCA)
TJ must not exceed the MOSFET maximum junction
temperature rating. It is recommended to measure the
MOSFET temperature in steady state to ensure that absolute
maximum ratings are not exceeded.
SEPIC Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current, and the peak current is equal to:
⎛ χ⎞
1
ID(PEAK ) = ⎜ 1+ ⎟ • IO(MAX ) •
1− DMAX
⎝ 2⎠
It is recommended that the peak repetitive reverse voltage
rating VRRM is higher than VOUT + VIN(MAX) by a safety
margin (a 10V safety margin is usually sufficient).
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the following equation:
VOUT + VD
IRMS(CDC) > IO(MAX ) •
VIN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
INVERTING CONVERTER APPLICATIONS
The LT3758 can be configured as a dual-inductor inverting topology, as shown in Figure 10. The VOUT to VIN
ratio is:
VOUT − VD
D
=−
VIN
1− D
in continuous conduction mode (CCM).
The power dissipated by the diode is:
PD = IO(MAX) • VD
L1
VIN
The DC voltage rating of the DC coupling capacitor (CDC,
as shown in Figure 1) should be larger than the maximum
input voltage:
VCDC > VIN(MAX)
–
LT3758
GATE
The RθJA used in this equation normally includes the RθJC
for the device, plus the thermal resistance from the board,
to the ambient temperature in the enclosure. TJ must not
exceed the diode maximum junction temperature rating.
SEPIC Converter: Selecting the DC Coupling Capacitor
+
COUT
TJ = TA + PD • RθJA
The selections of the output and input capacitors of the
SEPIC converter are similar to those of the boost converter.
Please refer to the Boost Converter: Output Capacitor
Selection and Boost Converter: Input Capacitor Selection
sections.
L2
–
CIN
and the diode junction temperature is:
SEPIC Converter: Output and Input Capacitor Selection
CDC
+
M1
VOUT
+
D1
SENSE
RSENSE
GND
+
3758 F10
Figure 10. A Simplified Inverting Converter
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty cycle
of the main switch can be calculated based on the negative
output voltage (VOUT) and the input voltage (VIN).
The maximum duty cycle (DMAX) occurs when the converter
has the minimum input voltage:
DMAX =
VOUT − VD
VOUT − VD − VIN(MIN)
3758f
24
LT3758
APPLICATIONS INFORMATION
Inverting Converter: Inductor, Sense Resistor, Power
MOSFET, Output Diode and Input Capacitor Selections
The selections of the inductor, sense resistor, power
MOSFET, output diode and input capacitor of an inverting
converter are similar to those of the SEPIC converter. Please
refer to the corresponding SEPIC converter sections.
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
converters for similar output ripples. This is due to the fact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
output capacitors are continuous. The output ripple voltage
is produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
⎛
⎞
1
ΔVOUT(P – P) = ΔIL2 • ⎜ ESRCOUT +
8 • f • COUT ⎟⎠
⎝
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output voltage ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
IRMS(COUT) > 0.3 • ΔIL2
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor
(CDC, as shown in Figure 10) should be larger than the
maximum input voltage minus the output voltage (negative voltage):
VCDC > VIN(MAX) – VOUT
CDC has nearly a rectangular current waveform. During
the switch off-time, the current through CDC is IIN, while
approximately –IO flows during the on-time. The RMS
rating of the coupling capacitor is determined by the following equation:
DMAX
IRMS(CDC) > IO(MAX ) •
1− DMAX
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for CDC.
Board Layout
The high speed operation of the LT3758 demands careful
attention to board layout and component placement. The
Exposed Pad of the package is the only GND terminal of
the IC, and is important for thermal management of the
IC. Therefore, it is crucial to achieve a good electrical and
thermal contact between the Exposed Pad and the ground
plane of the board. For the LT3758 to deliver its full output
power, it is imperative that a good thermal path be provided to dissipate the heat generated within the package.
It is recommended that multiple vias in the printed circuit
board be used to conduct heat away from the IC and into
a copper plane with as much area as possible.
To prevent radiation and high frequency resonance
problems, proper layout of the components connected
to the IC is essential, especially the power paths with
higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
inductive ringing:
• In boost configuration, the high di/dt loop contains
the output capacitor, the sensing resistor, the power
MOSFET and the Schottky diode.
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding, the
power MOSFET and the sensing resistor. The high
di/dt secondary loop contains the output capacitor,
the secondary winding and the output diode.
• In SEPIC configuration, the high di/dt loop contains
the power MOSFET, sense resistor, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop contains power MOSFET, sense resistor, Schottky diode
and the coupling capacitor.
3758f
25
LT3758
APPLICATIONS INFORMATION
Check the stress on the power MOSFET by measuring its
drain-to-source voltage directly across the device terminals
(reference the ground of a single scope probe directly to
the source pad on the PC board). Beware of inductive
ringing, which can exceed the maximum specified voltage
rating of the MOSFET. If this ringing cannot be avoided,
and exceeds the maximum rating of the device, either
choose a higher voltage device or specify an avalancherated power MOSFET.
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
the top of the output capacitor (Kelvin connection), staying
away from any high dV/dt traces. Place the divider resistors near the LT3758 in order to keep the high impedance
FBX node short.
Figure 11 shows the suggested layout of the 10V to 40V
input, 48V output boost converter in the Typical Applications section.
The small-signal components should be placed away from
high frequency switching nodes. For optimum load regula-
CIN
CC1
L1
R3
RC
R1
1
R2
2
9
CSS
3
8
RT
4
7
5
6
LT3758
R4
CC2
VIN
10
CVCC
1
8
2
RS
VIAS TO GROUND
PLANE
COUT2
7
M1
3
6
4
5
COUT1
D1
VOUT
3758 F11
Figure 11. Suggested Layout of the 10V to 40V Input, 48V Output
Boost Converter in the Typical Applications Section
3758f
26
LT3758
APPLICATIONS INFORMATION
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
Table 2. Recommended Component Manufacturers
VENDOR
COMPONENTS
TELEPHONE
WEB ADDRESS
Capacitors
207-282-5111
avx.com
Inductors,
Transformers
952-894-9590
bhelectronics.com
Coilcraft
Inductors
847-639-6400
coilcraft.com
Cooper Bussmann
Inductors
888-414-2645
bussmann.com
Diodes
805-446-4800
diodes.com
MOSFETs
408-822-2126
fairchildsemi.com
Diodes
516-847-3000
generalsemiconductor.
com
International Rectifier
MOSFETs, Diodes
310-322-3331
irf.com
IRC
Sense Resistors
361-992-7900
irctt.com
Tantalum Capacitors
408-986-0424
kemet.com
AVX
BH Electronics
Diodes, Inc
Fairchild
General Semiconductor
Kemet
Magnetics Inc
Toroid Cores
800-245-3984
mag-inc.com
Microsemi
Diodes
617-926-0404
microsemi.com
Murata-Erie
Inductors, Capacitors
770-436-1300
murata.co.jp
Capacitors
847-843-7500
nichicon.com
Diodes
602-244-6600
onsemi.com
Panasonic
Capacitors
714-373-7334
panasonic.com
Pulse
Inductors
858-674-8100
pulseeng.com
Sanyo
Capacitors
619-661-6835
sanyo.co.jp
Sumida
Inductors
847-956-0667
sumida.com
Taiyo Yuden
Capacitors
408-573-4150
t-yuden.com
Nichicon
On Semiconductor
TDK
Capacitors, Inductors
562-596-1212
component.tdk.com
Thermalloy
Heat Sinks
972-243-4321
aavidthermalloy.com
Tokin
Capacitors
408-432-8020
nec-tokinamerica.com
Toko
Inductors
847-699-3430
tokoam.com
United Chemi-Con
Capacitors
847-696-2000
chemi-com.com
Vishay/Dale
Resistors
605-665-9301
vishay.com
Vishay/Siliconix
MOSFETs
800-554-5565
vishay.com
Würth Elektronik
Inductors
605-886-4385
we-online.com
Capacitors
207-324-4140
vishay.com
Small-Signal Discretes
631-543-7100
zetex.com
Vishay/Sprague
Zetex
3758f
27
LT3758
TYPICAL APPLICATIONS
10V to 40V Input, 48V Output Boost Converter
VIN
10V TO 40V
CIN
4.7μF
50V
X7R
x2
R3
200k
L1
18.7μH
VIN
D1
SHDN/UVLO
R4
32.4k
LT3758
SENSE
RT
SS
RT
41.2k
300kHz
CC2
100pF
+
FBX
GND INTVCC
VC
CSS
0.68μF
R2
464k
M1
GATE
SYNC
VOUT
48V
1A
RC
10k
CC1
10nF
CVCC
4.7μF
10V
X5R
RS
0.012Ω
COUT1
100μF
63V
COUT2
4.7μF
50V
X7R
x4
R1
15.8k
3758 TA02a
CIN, COUT2: MURATA GRM32ER71H475KA88L
COUT1: PANASONIC ECG EEV-TG1J101UP
D1: VISHAY SILICONIX 30BQ060
L1: PULSE PB2020.223
M1: VISHAY SILICONIX SI7460DP
Efficiency vs Output Current
Start-Up Waveforms
100
VIN = 24V
90
EFFICIENCY (%)
80
VIN = 40V
70
VOUT
20V/DIV
VIN = 24V
60
50
IL1
2A/DIV
40
30
VIN = 10V
5ms/DIV
20
10
0.001
0.1
0.01
OUTPUT CURRENT (A)
3758 TA02c
1
3758 TA02b
3758f
28
LT3758
TYPICAL APPLICATIONS
12V Output Nonisolated Flyback Power Supply
D1
VIN
36V TO 72V
CIN
2.2μF
100V
X7R
0.022μF
100V
1M
6.2k
VIN
DSN
SHDN/UVLO
44.2k
GATE
FBX
GND INTVCC
VC
0.47μF
10k
100pF
4,5,6
(PARALLEL)
105k
1%
M1
SENSE
RT
SS
63.4k
200kHz
T1
1,2,3
(SERIES)
SW
LT3758
SYNC
VOUT
12V
1.2A
10nF
1N4148
CVCC
4.7μF
10V
X5R
5.1Ω
15.8k
1%
0.030Ω
COUT
47μF
X5R
3758 TA03a
CIN: MURATA GRM32ER72A225KA35L
T1: COILTRONICS VP2-0066
M1: VISHAY SILICONIX SI4848DY
D1: ON SEMICONDUCTOR MBRS360T3G
DSN: VISHAY SILICONIX ES1D
COUT: MURATA GRM32ER61C476ME15L
Efficiency vs Output Current
Start-Up Waveform
100
VIN = 48V
VIN = 48V
90
EFFICIENCY (%)
80
70
60
VOUT
5V/DIV
50
40
30
20
0.01
5ms/DIV
0.1
1
OUTPUT CURRENT (A)
3758 TA03c
10
3758 TA03b
Frequency Foldback Waveforms
When Output Short-Circuit
VIN = 48V
VOUT
5V/DIV
VSW
50V/DIV
20μs/DIV
3758 TA03d
3758f
29
LT3758
TYPICAL APPLICATIONS
VFD (Vacuum Fluorescent Display) Flyback Power Supply
D1
COUT2
2.2μF
100V
X7R
4
VIN
9V TO 16V
D2
CIN
22μF
25V
178k
T1
1, 2, 3
VIN
SHDN/UVLO
32.4k
M1 SW
LT3758
SYNC
5
95.3k
GATE
VOUT
96V
80mA
VOUT2
64V
40mA
COUT1
1μF
100V
X7R
6
SENSE
RT
SS
FBX
GND INTVCC
VC
0.47μF
63.4k
200kHz
47pF
10k
10nF
CVCC
4.7μF
10V
X5R
0.019Ω
0.5W
1.62k
3758 TA04a
CIN: MURATA GRM32ER61E226KE15L
COUT1: MURATA GRM31CR72A105K01L
COUT2: MURATA GRM32ER72A225KA35L
D1: VISHAY SILICONIX ES1D
D2: VISHAY SILICONIX ES1C
M1: VISHAY SILICONIX SI4848DY
T1: COILTRONICS VP1-0102
(*PRIMARY = 3 WINDINGS IN PARALLEL)
Start-Up Waveforms
VIN = 12V
Switching Waveforms
VOUT1
VOUT2
VIN = 12V
VOUT1
1V/DIV
(AC)
VOUT2
1V/DIV
(AC)
VOUT1,
VOUT2
20V/DIV
VSW
50V/DIV
10ms/DIV
3758 TA04b
2μs/DIV
3758 TA04c
3758f
30
LT3758
TYPICAL APPLICATIONS
36V to 72V Input, 3.3V Output Isolated Telecom Power Supply
PA1277NL
4
5
VIN
36V TO 72V
0.022μF
100V
CIN
2.2μF
100V
X7R
5.6k
COUT
100μF
6.3V
x3
6
BAV21W
7
VOUT+
3.3V
3A
UPS840
3
1M
VIN
SHDN/UVLO
44.2k
FDC2512
10Ω
GATE
SENSE
SYNC
INTVCC
4.7μF
25V
X5R
FBX
RT
SS
63.4k
200kHz
GND
BAS516
2
4.7μF
25V
X5R
0.03Ω
LT3758
VOUT-
8
BAT54CWTIG
1
16k
274Ω
BAS516
VC
47pF
LT4430
PS2801-1
0.47μF
100pF
100k
2200pF
250VAC
0.47μF
VIN
1μF
GND COMP
OC 0.5V FB
OPTO
47nF
2k
22.1k
3758 TA05a
Efficiency vs Output Current
100
90
EFFICIENCY (%)
80
70
VIN = 36V
VIN = 72V
60
50
VIN = 48V
40
30
20
0.01
0.1
1
OUTPUT CURRENT (A)
10
3758 TA05b
3758f
31
LT3758
TYPICAL APPLICATIONS
18V to 72V Input, 24V Output SEPIC Converter
VIN
18V TO 72V
CIN
2.2μF
100V
X7R
CDC
2.2μF
100V
X7R, x2
•
232k
VIN
L1A
SHDN/UVLO
20k
D1
VOUT
24V
1A
LT3758
SYNC
GATE
M1
SENSE
280k
1%
0.025Ω
RT
SS
FBX
GND INTVCC
VC
41.2k
300kHz
L1B
•
20k
1%
0.47μF
10k
10nF
CVCC
4.7μF
10V
X5R
COUT
10μF
25V
X5R
x4
3757 TA06a
CIN, CDC: TAIYO YUDEN HMK325B7225KN-T
COUT: MURATA GRM31CR61E106KA12L
L1A, L1B: COILTRONICS DRQ127-470
M1: FAIRCHILD SEMICONDUCTOR FDMS2572
D1: ON SEMICONDUCTOR MBRS3100T3G
Efficiency vs Output Current
Load Step Waveform
100
VIN = 48V
90
VIN = 18V
EFFICIENCY (%)
80
VOUT
1V/DIV
(AC)
70
VIN = 48V
60
VIN = 72V
50
IOUT 0.8A
0.5A/DIV
0.2A
40
30
500μs/DIV
20
10
0.001
0.1
0.01
OUTPUT CURRENT (A)
1
3757 TA06b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveform
VIN = 48V
VIN = 48V
VOUT
20V/DIV
VOUT
10V/DIV
VSW
50V/DIV
IL1A + IL1B
1A/DIV
IL1A + IL1B
2A/DIV
2ms/DIV
3757 TA06c
3757 TA06d
50μs/DIV
3757 TA06e
3758f
32
LT3758
TYPICAL APPLICATIONS
10V to 40V Input, –12V Output Inverting Converter
CIN
4.7μF
50V
X7R
x2
CDC
4.7μF
50V
X7R, x2
•
R1
200k
VIN
L1A
SHDN/UVLO
R2
32.4k
L1B
VOUT
-12V
2A
•
VIN
10V TO 40V
LT3758
GATE
SYNC
M1
D1
SENSE
RT
SS
FBX
GND INTVCC
VC
41.2k
300kHz
105k
0.015Ω
7.5k
10k
0.47μF
6.8nF
CVCC
4.7μF
10V
X5R
COUT
22μF
16V
X5R
x4
3757 TA07a
CIN, CDC: MURATA GRM32ER71H475KA88L
COUT: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 30BQ060
L1A, L1B: COILTRONICS DRQ127-150
M1: VISHAY SILICONIX SI7850DP
Efficiency vs Output Current
Load Step Waveforms
100
EFFICIENCY (%)
80
VIN = 24V
VIN = 10V
90
VIN = 24V
VOUT
500mV/DIV
(AC)
VIN = 40V
70
60
50
IOUT 1.6A
1A/DIV
0.4A
40
30
500μs/DIV
20
10
0.001
0.1
1
0.01
OUTPUT CURRENT (A)
10
3757 TA07b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
VIN = 24V
VOUT
5V/DIV
3757 TA07c
VOUT VIN = 24V
10V/DIV
VSW
20V/DIV
IL1A + IL1B
2A/DIV
5ms/DIV
3757 TA07d
IL1A + IL1B
5A/DIV
50μs/DIV
3757 TA07e
3758f
33
LT3758
PACKAGE DESCRIPTION
DD Package
10-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1699)
R = 0.115
TYP
6
0.38 ± 0.10
10
0.675 ±0.05
3.50 ±0.05
1.65 ±0.05
2.15 ±0.05 (2 SIDES)
3.00 ±0.10
(4 SIDES)
PACKAGE
OUTLINE
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(SEE NOTE 6)
(DD) DFN 1103
5
0.200 REF
0.25 ± 0.05
0.50
BSC
2.38 ±0.05
(2 SIDES)
1
0.25 ± 0.05
0.50 BSC
0.75 ±0.05
0.00 – 0.05
2.38 ±0.10
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-2).
CHECK THE LTC WEBSITE DATA SHEET FOR CURRENT STATUS OF VARIATION ASSIGNMENT
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
3758f
34
LT3758
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev C)
BOTTOM VIEW OF
EXPOSED PAD OPTION
2.794 p 0.102
(.110 p .004)
5.23
(.206)
MIN
0.889 p 0.127
(.035 p .005)
1
0.05 REF
10
DETAIL “B”
CORNER TAIL IS PART OF
DETAIL “B” THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
NO MEASUREMENT PURPOSE
3.00 p 0.102
(.118 p .004)
(NOTE 3)
10 9 8 7 6
DETAIL “A”
0o – 6o TYP
1 2 3 4 5
GAUGE PLANE
0.53 p 0.152
(.021 p .006)
DETAIL “A”
0.18
(.007)
0.497 p 0.076
(.0196 p .003)
REF
3.00 p 0.102
(.118 p .004)
(NOTE 4)
4.90 p 0.152
(.193 p .006)
0.254
(.010)
0.29
REF
1.83 p 0.102
(.072 p .004)
2.083 p 0.102 3.20 – 3.45
(.082 p .004) (.126 – .136)
0.50
0.305 p 0.038
(.0197)
(.0120 p .0015)
BSC
TYP
RECOMMENDED SOLDER PAD LAYOUT
2.06 p 0.102
(.081 p .004)
SEATING
PLANE
0.86
(.034)
REF
1.10
(.043)
MAX
0.17 – 0.27
(.007 – .011)
TYP
0.50
(.0197)
BSC
0.1016 p 0.0508
(.004 p .002)
MSOP (MSE) 0908 REV C
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
3758f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LT3758
TYPICAL APPLICATIONS
8V to 72V Input, 12V Output SEPIC Converter
Efficiency vs Output Current
100
CIN
2.2μF
100V
X7R
x2
CDC
2.2μF
100V
D1
X7R, x2 MBRS3100T3G
•
154k
VIN
L1A
SHDN/UVLO
32.4k
90
LT3758
GATE
SYNC
M1
Si7456DP
SENSE
105k
1%
COUT1
47μF
20V
x2
10nF
VIN = 42V
VIN = 72V
60
50
40
20
15.8k
1%
10k
70
30
FBX
GND INTVCC
VC
0.47μF
VOUT
12V
2A
0.012Ω
RT
SS
41.2k
300kHz
+
L1B
•
VIN = 8V
80
EFFICIENCY (%)
VIN
8V TO 72V
COUT2
10μF
16V
X5R
x4
CVCC
4.7μF
10V
X5R
10
0.001
0.01
0.1
1
OUTPUT CURRENT (A)
10
3757 TA08b
3757 TA08a
L1A, L1B: COILTRONICS DRQ127-220
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1619
Current Mode PWM Controller
300kHz Fixed Frequency, Boost, SEPIC, Flyback Topology; 1.9V ≤ VIN ≤ 18V
LTC1624
Current Mode DC/DC Controller
VIN Up to 36V, 300kHz Operating Frequency; Buck, Boost, SEPIC Design,
SO-8 Package
LTC1871, LTC1871-1
No RSENSE™ Boost, Flyback and SEPIC Controller
2.5V ≤ VIN ≤ 36V, Current Mode Control, Programmable Operating
Frequency from 50kHz to 1MHz, 5V Gate Drive
LTC1871-7
No RSENSE Boost, Flyback and SEPIC Controller
7V Gate Drive Version of LTC1871
LTC1872
TSOT-23 Boost Controller
550kHz Fixed Frequency, Current Mode, 2.5V ≤ VIN ≤ 9.8V
LT1930
1.2MHz, SOT-23 Boost Converter
2.6V ≤ VIN ≤ 16V, Up to 34V Output, 1A Switch Current
LT1931
Inverting 1.2MHz, SOT-23 Converter
Positive-to-Negative DC/DC Conversion, Miniature Design
LTC3704
Positive-to-Negative DC/DC Controller
No RSENSE, Current Mode Control, 50kHz to 1MHz
LT3844
High Voltage, Current Mode Switching Regulator
Controller
Wide Input Range: 4V to 60V
LT3757
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ VIN ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Packages
LT3782A
2-Phase Step-Up DC/DC Controller
6V ≤ VIN ≤ 40V, 4A Gate Drive, 150kHz to 500kHz
LTC3803, LTC3803-3, Constant-Frequency, Current Mode DC/DC
LTC3803-5
Controller
Wide Input Range; Flyback, Boost and SEPIC Topologies, ThinSOT™
Package
LTC3805, LTC3805-5
Adjustable, Synchronizable Frequency, Current
Mode DC/DC Controller
VIN and VOUT Limited Only by External Components, Used in Flyback, Boost
and SEPIC Topologies
LT3845
Low IQ, High Voltage Single Output Synchronous
Step-Down DC/DC Controller
1.23V ≤ VOUT ≤ 36V, 4V ≤ VIN ≤ 60V, 120μA IQ
LTC3872
No RSENSE Boost, Flyback and SEPIC Controller
2.75V ≤ VIN ≤ 9.8V, Current Mode Control, TSOT-23 and 2mm × 3mm
DFN-8 Packages
No RSENSE and ThinSOT are trademarks of Linear Technology Corporation.
3758f
36 Linear Technology Corporation
LT 0709 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2009
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