Intel 852GME, Intel 852GMV and Intel 852PM

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Intel® 852GME, Intel® 852GMV and
Intel® 852PM Chipset Platforms
Design Guide
For Use with the Mobile Intel® Pentium® 4 Processor supporting HyperThreading Technology on 90-nm process technology, Mobile Intel®
Pentium® 4 Processor, Intel® Celeron® Processor, and Intel® Celeron® D
Processors on 90 nm Process and in the 478-pin Package
June 2004
Order Number: 253026-004
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Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability
whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to
fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended
for use in medical, life saving, or life sustaining applications.
The information provided in this report, and related materials and presentations, are intended to illustrate the effects of certain design variables as
determined by modeling, and are neither a recommendation nor endorsement of any specific system-level design practices or targets. The model results
are based on a simulated notebook configuration, and do not describe or characterize the properties of any specific, existing system design. A detailed
description of the simulated notebook configuration is available upon request.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future
definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Intel® 852GME/852PM/852GMV Chipsets, Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology,
Mobile Intel Pentium 4 processor and Intel Celeron processor may contain design defects or errors known as errata which may cause the product to
deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
I2C is a 2-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel.
Implementations of the I2C bus/protocol may require licenses from various entities, including Philips Electronics N.V. and North American Philips
Corporation.
Alert on LAN is a result of the Intel-IBM Advanced Manageability Alliance and a trademark of IBM.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature, may be obtained from:
Intel Corporation
www.intel.com
or call 1-800-548-4725
Intel, Intel logo, Pentium, Intel NetBurst, Celeron and Intel SpeedStep are registered trademarks or trademarks of Intel Corporation and its subsidiaries in
the United States and other countries.
*Other brands and names may be claimed as the property of others.
Copyright © Intel Corporation 2004
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Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
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Contents
1.
Introduction .................................................................................................................................19
1.1.
1.2.
2.
System Overview........................................................................................................................23
2.1.
2.2.
2.3.
3.
Intel 852GME Chipset Platform System Features.........................................................23
2.1.1.
Host Interface .................................................................................................23
2.1.1.1.
Mobile Intel Pentium 4 Processor supporting Hyper-Threading
Technology on 90-nm process technology .....................................23
2.1.1.2.
Mobile Intel Pentium 4 Processor ...................................................24
2.1.1.3.
Intel Celeron D Processor on 90 nm process and in the 478-pin
package...........................................................................................25
2.1.1.4.
Intel Celeron Processor ..................................................................25
2.1.2.
Intel 852GME Graphics Memory Controller Hub (GMCH).............................25
2.1.2.1.
Multiplexed AGP and Intel® DVO Interface.....................................25
2.1.2.2.
Accelerated Graphics Port (AGP) Interface....................................26
2.1.2.3.
Integrated System Memory DRAM Controller ................................26
2.1.2.4.
Internal Graphics Controller ............................................................26
2.1.3.
Package/Power ..............................................................................................27
2.1.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................27
2.1.5.
Firmware Hub (FWH) .....................................................................................28
Intel 852PM Chipset Platform System Features............................................................30
2.2.1.
Host Interface .................................................................................................30
2.2.1.1.
Mobile Intel Pentium 4 Processor ...................................................30
2.2.1.2.
Intel Celeron Processor ..................................................................30
2.2.2.
852PM Memory Controller Hub (MCH)..........................................................30
2.2.2.1.
Accelerated Graphics Port (AGP) Interface....................................30
2.2.2.2.
Integrated System Memory DRAM Controller ................................31
2.2.3.
Package/Power ..............................................................................................31
2.2.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................31
2.2.5.
Firmware Hub (FWH) .....................................................................................31
Intel 852GMV Chipset Platform System Features.........................................................33
2.3.1.
Host Interface .................................................................................................33
2.3.1.1.
Intel Celeron Processor ..................................................................33
2.3.2.
Intel 852GMV Graphics Memory Controller Hub (GMCH).............................33
2.3.2.1.
Multiplexed AGP and Intel® DVO Interface.....................................33
2.3.2.2.
Integrated System Memory DRAM Controller ................................34
2.3.2.3.
Internal Graphics Controller ............................................................34
2.3.3.
Package/Power ..............................................................................................34
2.3.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M) ................................35
2.3.5.
Firmware Hub (FWH) .....................................................................................35
General Design Considerations .................................................................................................37
3.1.
3.2.
4.
Referenced Documents .................................................................................................20
Conventions and Terminology .......................................................................................21
Recommended Board Stack-Up ....................................................................................37
Alternate Stack Ups .......................................................................................................39
FSB Design Guidelines ..............................................................................................................41
4.1.
FSB Routing Guidelines ................................................................................................41
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4.2.
4.3.
4.4.
4.5.
4.6.
5.
6.
Platform Power Requirements ................................................................................................... 63
System Memory Design Guidelines (DDR-SDRAM) ................................................................. 65
6.1.
6.2.
6.3.
4
Return Path Evaluation.................................................................................. 43
4.1.1.
OPTIMIZED/COMPAT# Topology for Intel® 852GME/852GMV/852PM
Only Platforms............................................................................................................... 43
General Topology and Layout Guidelines..................................................................... 44
4.3.1.
Data Signals .................................................................................................. 44
4.3.2.
Address Signals............................................................................................. 44
4.3.3.
Strobe Signals ............................................................................................... 44
4.3.4.
Common Clock Signals ................................................................................. 44
4.3.5.
Source Synchronous (SS) Signals ................................................................ 45
4.3.6.
Common Clock (CC) AGTL+ Signals ............................................................ 46
4.3.7.
Asynchronous AGTL+ Signals ...................................................................... 47
4.3.7.1.
Topologies ...................................................................................... 47
4.3.7.1.1.
Topology 1A: Open Drain (OD) Signals Driven by the
Processor – IERR# and FERR#................................... 47
4.3.7.1.2.
Topology 1B: Open Drain (OD) Signals Driven by the
Processor –THERMTRIP# ........................................... 48
4.3.7.1.3.
Topology 1C: Open Drain (OD) Signals Driven by the
Processor –PROCHOT# .............................................. 49
4.3.7.1.4.
Topology 2A: Open Drain (OD) Signals Driven by ICH4M – PWRGOOD ........................................................... 50
4.3.7.1.5.
Topology 2B: CMOS Signals Driven by ICH4-M –
DPSLP# ........................................................................ 51
4.3.7.1.6.
Topology 2C: CMOS Signals Driven by ICH4-M –
A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#,
and STPCLK#............................................................... 52
4.3.7.1.7.
Topology 3: CMOS Signals Driven by ICH4-M to CPU
and FWH – INIT#.......................................................... 53
4.3.7.2.
Voltage Translation Circuit ............................................................. 54
4.3.8.
AGTL+ I/O Buffer Compensation .................................................................. 54
4.3.8.1.
Mobile Intel Pentium 4 Processor AGTL+ I/O Buffer
Compensation ................................................................................ 55
4.3.9.
Processor RESET# Signal ............................................................................ 55
Host Vrefs...................................................................................................................... 57
ITP Debug Port.............................................................................................................. 57
4.5.1.
Logic Analyzer Interface (LAI) ....................................................................... 57
4.5.1.1.
Mechanical Considerations ............................................................ 57
4.5.1.2.
Electrical Considerations ................................................................ 57
Mobile Intel Pentium 4 Processor and 852GME/852GMV/852PMChipset FSB Signal
Package Lengths .......................................................................................................... 58
Length Matching and Length Formulas......................................................................... 66
Package Length Compensation .................................................................................... 66
Topologies and Routing Guidelines .............................................................................. 67
6.3.1.
Clock Signals – SCK[5:0], SCK#[5:0] ............................................................ 67
6.3.1.1.
Clock Topology Diagram ................................................................ 67
6.3.1.2.
Memory Clock Routing Guidelines ................................................. 68
6.3.1.3.
Clock Length Matching Requirements ........................................... 69
6.3.1.4.
Clock Reference Lengths ............................................................... 70
6.3.1.5.
Clock Package Length Table ......................................................... 71
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Clock Routing Example...................................................................72
6.3.1.6.
Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0]..........................................72
6.3.2.1.
Data Bus Topology..........................................................................74
6.3.2.2.
SDQS to Clock Length Matching Requirements.............................75
6.3.2.3.
Data to Strobe Length Matching Requirements..............................77
6.3.2.4.
SDQ to SDQS Mapping ..................................................................77
6.3.2.5.
SDQ/SDQS Signal Package Lengths .............................................79
6.3.2.6.
Memory Data Routing Example ......................................................80
6.3.3.
Control Signals – SCKE[3:0], SCS#[3:0] .......................................................81
6.3.3.1.
Control Signal Topology..................................................................82
6.3.3.2.
Control Signal Routing Guidelines ..................................................82
6.3.3.3.
Control to Clock Length Matching Requirements ...........................83
6.3.3.4.
Memory Control Routing Example ..................................................85
6.3.3.5.
Control Group Package Length Table ............................................86
6.3.4.
Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#.......86
6.3.4.1.
Command Topology 1.....................................................................87
6.3.4.2.
Command Topology 1 Routing Guidelines .....................................88
6.3.4.3.
Command Topology 1 Length Matching Requirements .................89
6.3.4.4.
Command Topology 2.....................................................................91
6.3.4.5.
Command Topology 2 Routing Guidelines .....................................92
6.3.4.6.
Command Topology 2 Length Matching Requirements .................93
6.3.4.7.
Command Topology 2 Routing Example ........................................95
6.3.4.8.
Command Topology 3.....................................................................96
6.3.4.9.
Command Topology 3 Routing Guidelines .....................................97
6.3.4.10. Command Topology 3 Length Matching Requirements .................98
6.3.4.11. Command Group Package Length Table .....................................100
6.3.5.
CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]...............................................101
6.3.5.1.
CPC Signal Topology....................................................................102
6.3.5.2.
CPC Signal Routing Guidelines ....................................................102
6.3.5.3.
CPC to Clock Length Matching Requirements .............................103
6.3.5.4.
CPC Group Package Length Table ..............................................104
6.3.6.
Feedback – RCVENOUT#, RCVENIN#.......................................................105
Routing Updates for “High-Density” Memory Device Support.....................................105
ECC Disable Guidelines ..............................................................................................105
6.5.1.
GMCH/MCH ECC Functionality Disable ......................................................105
6.5.2.
DDR Memory ECC Functionality Disable ....................................................106
System Memory Compensation...................................................................................106
SMVREF Generation ...................................................................................................106
DDR Power Delivery....................................................................................................106
External Thermal Sensor Based Throttling (ETS#) .....................................................107
6.9.1.
ETS# Usage Model ......................................................................................107
6.9.2.
ETS# Design Guidelines ..............................................................................107
6.9.3.
Thermal Sensor Routing and Placement Guidelines...................................107
6.3.2.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
7.
Integrated Graphics Display Port .............................................................................................109
7.1.
Analog RGB/CRT Guidelines ......................................................................................109
7.1.1.
RAMDAC/Display Interface..........................................................................109
7.1.2.
Reference Resistor (REFSET).....................................................................109
7.1.3.
RAMDAC Board Design Guidelines.............................................................110
7.1.4.
RAMDAC Routing Guidelines ......................................................................111
7.1.5.
DAC Power Requirements ...........................................................................113
7.1.6.
HSYNC and VSYNC Design Considerations...............................................114
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7.2.
7.3.
7.4.
7.5.
7.6.
8.
AGP Port Design Guidelines.................................................................................................... 128
8.1.
8.2.
9.
AGP Interface .............................................................................................................. 128
8.1.1.
AGP 2.0 ....................................................................................................... 128
8.1.2.
AGP Interface Signal Groups ...................................................................... 129
AGP Routing Guidelines ............................................................................................. 130
8.2.1.
1x Timing Domain Routing Guidelines ........................................................ 130
8.2.1.1.
Trace Length Requirements for AGP 1X...................................... 130
8.2.1.2.
Trace Spacing Requirements....................................................... 131
8.2.1.3.
Trace Length Mismatch ................................................................ 131
8.2.2.
2x/4x Timing Domain Routing Guidelines ................................................... 131
8.2.2.1.
Trace Length Requirements for AGP 2X/4X ................................ 131
8.2.2.2.
Trace Spacing Requirements....................................................... 132
8.2.2.3.
Trace Length Mismatch Requirements ........................................ 133
8.2.3.
AGP Clock Skew ......................................................................................... 134
8.2.4.
AGP Signal Noise Decoupling Guidelines................................................... 134
8.2.5.
AGP Interface Package Lengths ................................................................. 135
8.2.6.
AGP Routing Ground Reference ................................................................. 136
8.2.7.
Pull-ups ........................................................................................................ 136
8.2.8.
AGP VDDQ and VCC .................................................................................. 138
8.2.9.
VREF Generation for AGP 2.0 (2X and 4X) ................................................ 138
8.2.9.1.
1.5-V AGP Interface (2X/4X) ........................................................ 138
8.2.10. AGP Compensation ..................................................................................... 138
8.2.11. PM_SUS_CLK/AGP_PIPE# Design Consideration .................................... 138
Hub Interface............................................................................................................................ 140
9.1.
9.2.
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DDC and I2C Design Considerations.......................................................... 114
7.1.7.
LVDS Transmitter Interface......................................................................................... 114
7.2.1.
LVDS Length Matching Constraints ............................................................ 115
7.2.2.
LVDS Package Length Compensation........................................................ 115
7.2.3.
LVDS Routing Guidelines............................................................................ 116
Digital Video Out Port.................................................................................................. 118
7.3.1.
DVO Interface Signal Groups ...................................................................... 118
7.3.1.1.
DVOB Interface Signals................................................................ 118
7.3.1.2.
DVOC Interface Signals ............................................................... 118
7.3.1.3.
Common Signals for Both DVO Ports .......................................... 119
7.3.2.
DVOB and DVOC port Interface Routing Guidelines .................................. 119
7.3.2.1.
Length Mismatch Requirements................................................... 119
7.3.2.2.
Package Length Compensation ................................................... 120
7.3.2.3.
DVOB and DVOC Routing Guidelines ......................................... 120
7.3.2.4.
DVOB and DVOC Port Termination ............................................. 122
7.3.3.
DVOB and DVOC Assumptions, Definitions, and Specifications ................ 122
7.3.4.
DVOB and DVOC Simulation Method ......................................................... 123
DVOB and DVOC port Flexible (Modular) Design ...................................................... 124
7.4.1.
DVOB and DVOC Module Design ............................................................... 124
7.4.1.1.
Generic Connector Model............................................................. 125
DVO GMBUS and DDC Interface Considerations ...................................................... 125
7.5.1.
Leaving the GMCH DVOB or DVOC Port Unconnected ............................. 126
Miscellaneous Input Signals and Voltage Reference.................................................. 127
Hub Interface Compensation ...................................................................................... 140
Hub Interface Data HL[10:0] and Strobe Signals........................................................ 141
9.2.1.
HL[10:0] and Strobe Signals Internal Layer Routing ................................... 141
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9.3.
9.4.
10.
Terminating HL[11].......................................................................................143
9.2.2.
Hub VREF/VSWING Generation/Distribution ..............................................................143
9.3.1.
Single Generation Voltage Reference Divider Circuit..................................143
9.3.2.
Locally Generated Voltage Reference Divider Circuit .................................144
9.3.3.
Single GMCH and ICH4-M Voltage Generation / Separate Divider Circuit
for VSWING/VREF .......................................................................................145
9.3.4.
Separate GMCH and ICH4-M Voltage Generation / Separate Divider
Circuits for VREF and VSWING...................................................................146
Hub Interface Decoupling Guidelines ..........................................................................146
I/O Subsystem ..........................................................................................................................148
10.1.
10.2.
10.3.
10.4.
10.5.
10.6.
10.7.
IDE Interface ................................................................................................................148
10.1.1. Cabling .........................................................................................................148
10.1.2. Primary IDE Connector Requirements.........................................................149
10.1.3. Secondary IDE Connector Requirements....................................................150
10.1.4. Mobile IDE Swap Bay Support.....................................................................151
10.1.4.1. ICH4-M IDE Interface Tri-State Feature .......................................151
10.1.4.2. S5/G3 to S0 Boot Up Procedures for IDE Swap Bay ...................152
10.1.4.3. Power Down Procedures for Mobile Swap Bay ............................152
10.1.4.4. Power Up Procedures After Device “Hot” Swap Completed ........152
PCI ...............................................................................................................................153
AC’97 ...........................................................................................................................153
10.3.1. AC’97 Routing ..............................................................................................157
10.3.2. Motherboard Implementation .......................................................................157
10.3.2.1. Valid Codec Configurations ..........................................................158
10.3.3. SPKR Pin Configuration...............................................................................158
USB 2.0 Guidelines and Recommendations ...............................................................159
10.4.1. Layout Guidelines ........................................................................................159
10.4.1.1. General Routing and Placement...................................................159
10.4.1.2. USB 2.0 Trace Separation ............................................................160
10.4.1.3. USBRBIAS Connection.................................................................160
10.4.1.4. USB 2.0 Termination.....................................................................161
10.4.1.5. USB 2.0 Trace Length Pair Matching ...........................................161
10.4.1.6. USB 2.0 Trace Length Guidelines ................................................161
10.4.2. Plane Splits, Voids, and Cut-Outs (Anti-Etch)..............................................162
10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)......................162
10.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch) .....................162
10.4.3. USB Power Line Layout Topology ...............................................................162
10.4.4. EMI Considerations......................................................................................163
10.4.4.1. Common Mode Chokes ................................................................163
10.4.5. ESD ..............................................................................................................164
10.4.6. USB Selective Suspend ...............................................................................164
I/O APIC (I/O Advanced Programmable Interrupt Controller) .....................................164
SMBus 2.0/SMLink Interface .......................................................................................165
10.6.1. SMBus Architecture and Design Considerations.........................................166
10.6.1.1. SMBus Design Considerations .....................................................166
10.6.1.2. General Design Issues/Notes .......................................................167
10.6.1.3. High Power/Low Power Mixed Architecture..................................167
10.6.1.4. Calculating the Physical Segment Pull-Up Resistor .....................167
FWH .............................................................................................................................169
10.7.1. FWH Decoupling ..........................................................................................169
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10.7.2. In Circuit FWH Programming....................................................................... 169
10.7.3. FWH INIT# Voltage Compatibility................................................................ 169
10.7.4. FWH VPP Design Guidelines........................................................................ 170
10.7.5. FWH INIT# Assertion/Deassertion Timings................................................. 170
10.8. RTC ............................................................................................................................. 171
10.8.1. RTC Crystal ................................................................................................. 172
10.8.2. External Capacitors ..................................................................................... 173
10.8.3. RTC Layout Considerations ........................................................................ 174
10.8.4. RTC External Battery Connections.............................................................. 174
10.8.5. RTC External RTCRST# Circuit .................................................................. 175
10.8.6. VBIAS DC Voltage and Noise Measurements ............................................... 176
10.8.7. SUSCLK....................................................................................................... 176
10.8.8. RTC-Well Input Strap Requirements ........................................................... 176
10.9. Internal LAN Layout Guidelines .................................................................................. 176
10.9.1. Footprint Compatibility ................................................................................. 177
10.9.2. Intel® 82801DBM ICH4-M – LAN Connect Interface Guidelines ................. 178
10.9.2.1. Bus Topologies ............................................................................. 178
10.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point
Interconnect................................................................ 178
10.9.2.2. Signal Routing and Layout ........................................................... 179
10.9.2.3. Crosstalk Consideration ............................................................... 179
10.9.2.4. Impedances .................................................................................. 179
10.9.2.5. Line Termination ........................................................................... 180
10.9.2.6. Terminating Unused LAN Connect Interface Signals................... 180
10.9.3. Intel 82562ET / Intel 82562EM Guidelines .................................................. 180
10.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement..................................................................................... 180
10.9.3.2. Crystals and Oscillators................................................................ 180
10.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors................. 181
10.9.3.4. Critical Dimensions....................................................................... 181
10.9.3.4.1. Distance from Magnetics Module to RJ-45
(Distance A)................................................................ 182
10.9.3.4.2. Distance from Intel 82562ET / 82562ET to Magnetics
Module (Distance B) ................................................... 182
10.9.3.5. Reducing Circuit Inductance ........................................................ 182
10.9.3.5.1. Terminating Unused Connections.............................. 183
10.9.3.5.2. Termination Plane Capacitance ................................. 183
10.9.4. Intel 82562ET/EM Disable Guidelines......................................................... 184
10.9.5. Design and Layout Consideration for Intel 82540EP / 82551QM ............... 184
10.9.6. General Intel 82562ET/82562EM/82551QM/82540EP Differential Pair
Trace Routing Considerations ..................................................................... 185
10.9.6.1.1. Trace Geometry and Length ...................................... 186
10.9.6.1.2. Signal Isolation ........................................................... 186
10.9.6.1.3. Magnetics Module General Power and Ground Plane
Considerations............................................................ 187
10.9.6.2. Common Physical Layout Issues ................................................. 188
10.10. Power Management Interface ..................................................................................... 189
10.10.1. SYS_RESET# Usage Model ....................................................................... 189
10.10.2. PWRBTN# Usage Model............................................................................. 189
10.10.3. Power Well Isolation Control Strap Requirements ...................................... 189
10.11. CPU CMOS Considerations ........................................................................................ 190
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11.
Platform Clock Routing Guidelines...........................................................................................193
11.1.
11.2.
11.3.
11.4.
12.
System Clock Groups ..................................................................................................193
Clock Group Topologies and Routing Constraints ......................................................195
11.2.1. Host Clock Group.........................................................................................195
11.2.1.1. Host Clock Group General Routing Guidelines ............................197
11.2.1.2. Clock to Clock Length Matching and Compensation....................197
11.2.1.3. EMI Constraints.............................................................................197
11.2.2. CLK66 Clock Group .....................................................................................198
11.2.3. Host Clock to CLK66 Routing Recommendations .......................................199
11.2.4. CLK33 Clock Group .....................................................................................200
11.2.5. PCI Clock Group ..........................................................................................201
11.2.6. CLK14 Clock Group .....................................................................................202
11.2.7. DOTCLK Clock Group..................................................................................203
11.2.8. SSCCLK Clock Group..................................................................................204
11.2.9. USBCLK Clock Group..................................................................................205
CK-408 Clock Power Supply Decoupling ....................................................................205
CK-408 PWRDWN# Signal Connections ....................................................................206
Platform Power Delivery Guidelines.........................................................................................207
12.1.
12.2.
12.3.
12.4.
12.5.
12.6.
12.7.
Definitions ....................................................................................................................207
Platform Power Requirements.....................................................................................208
Voltage Supply.............................................................................................................209
12.3.1. Power Management States..........................................................................209
12.3.2. Power Supply Rail Descriptions...................................................................210
852GME/852GMV/852PMGMCH/ICH4-M Platform Power-Up Sequence .................211
12.4.1. ICH4-M Power Sequencing Requirements..................................................213
12.4.1.1. 3.3 V/1.5 V Power Sequencing .....................................................213
12.4.1.2. V5REF/ 3.3 V Sequencing................................................................213
12.4.1.3. V5REF_SUS Design Guidelines .........................................................214
12.4.2. GMCH Power Sequencing Requirements ...................................................215
12.4.3. DDR Power Sequencing Requirements ......................................................215
12.4.4. PWR ICH4-M SYS_RESET# Signal ............................................................216
DDR Power Delivery Design Guidelines .....................................................................216
12.5.1. DDR Interface Decoupling Guidelines .........................................................217
12.5.1.1. GMCH VCCSM Decoupling Guidelines........................................217
12.5.1.2. DDR SO-DIMM System Memory Decoupling Guidelines.............218
12.5.2. 2.5-V Power Delivery Guidelines .................................................................218
12.5.3. DDR Reference Voltage...............................................................................218
12.5.3.1. SMVREF Layout and Routing Recommendations........................220
12.5.3.2. DDR VREF Requirements ............................................................222
12.5.4. DDR SMRCOMP Resistive Compensation .................................................222
12.5.5. DDR VTT Termination..................................................................................223
Clock Driver Power Delivery Guidelines......................................................................224
Decoupling Recommendations....................................................................................226
12.7.1. Processor Decoupling Guidelines................................................................226
12.7.2. Intel 852GME/852GMV/852PMGMCH Decoupling Guidelines ...................226
12.7.3. Intel ICH4-M Decoupling Guidelines............................................................227
12.7.4. DDR VTT High Frequency and Bulk Decoupling.........................................228
12.7.5. Hub Interface Decoupling.............................................................................229
12.7.6. FWH Decoupling ..........................................................................................229
12.7.7. General LAN Decoupling .............................................................................229
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12.7.8. CK-408 Clock Driver Decoupling................................................................. 229
Intel 852GME/852GMV/852PMGMCH Analog Power Delivery.................................. 230
12.8.1. Analog Supply Filter Requirements ............................................................. 230
12.8.2. Recommended Routing/Component Placement ......................................... 231
12.9. Intel 852GME/852GMV/852PMMaximum Supply Current Numbers .......................... 231
12.10. Intel ICH4-M Power Consumption Numbers............................................................... 232
12.11. Thermal Design Power................................................................................................ 233
12.8.
13.
Test Signals ............................................................................................................................. 234
13.1.
13.2.
14.
Platform Design Checklist........................................................................................................ 236
14.1.
14.2.
14.3.
14.4.
14.5.
14.6.
14.7.
14.8.
14.9.
10
Mobile Intel Pentium 4 Processor Reserved Signals .................................................. 234
Intel 852GME / 852PM GMCH RSVD Signals ............................................................ 235
General Information..................................................................................................... 236
Customer Implementation of Voltage Rails................................................................. 237
Design Checklist Implementation................................................................................ 238
In Target Probe (ITP) .................................................................................................. 242
Decoupling Recommendations ................................................................................... 242
Power-up Sequence.................................................................................................... 243
CK-408 Clock Checklist............................................................................................... 245
14.7.1. Resistor Recommendations ........................................................................ 245
852GME/852GMV/852PMChecklist............................................................................ 247
14.8.1. System Memory........................................................................................... 247
14.8.1.1. GMCH System Memory Interface ................................................ 247
14.8.1.2. DDR SO-DIMM Interface.............................................................. 248
14.8.1.3. SO-DIMM Decoupling Recommendation ..................................... 250
14.8.2. FSB .............................................................................................................. 250
14.8.3. Hub Interface ............................................................................................... 251
14.8.4. Graphics Interfaces...................................................................................... 251
14.8.4.1. LVDS ............................................................................................ 251
14.8.4.2. AGP/DVO ..................................................................................... 251
14.8.4.3. DAC .............................................................................................. 255
14.8.5. Miscellaneous .............................................................................................. 256
14.8.6. GMCH Decoupling Recommendations ....................................................... 257
14.8.7. GMCH Power-up Sequence ........................................................................ 258
ICH4-M Checklist ........................................................................................................ 259
14.9.1. PCI Interface and Interrupts ........................................................................ 259
14.9.2. GPIO ............................................................................................................ 261
14.9.3. AGP_BUSY# Design Requirement ............................................................. 262
14.9.4. (SMBus) System Management Interface .................................................... 262
14.9.5. AC ’97 Interface ........................................................................................... 263
14.9.6. ICH4-M Power Management Interface ........................................................ 264
14.9.7. FWH/LPC Interface...................................................................................... 265
14.9.8. USB Interface .............................................................................................. 265
14.9.9. Hub Interface ............................................................................................... 265
14.9.10. RTC Circuitry ............................................................................................... 268
14.9.11. LAN Interface............................................................................................... 269
14.9.12. Primary IDE Interface .................................................................................. 269
14.9.13. Secondary IDE Interface ............................................................................. 270
14.9.14. Miscellaneous Signals ................................................................................. 270
14.9.15. ICH4-M Decoupling Recommendations ...................................................... 271
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14.9.16. ICH4-M Power-up Sequence .......................................................................272
14.10. USB Power Checklist...................................................................................................274
14.10.1. Downstream Power Connection ..................................................................274
14.11. FWH Checklist .............................................................................................................275
14.11.1. Resistor Recommendations.........................................................................275
14.12. LAN/HomePNA Checklist ............................................................................................275
14.12.1. Resistor Recommendations (for 82562ET / 82562 EM) ..............................275
14.12.2. Decoupling Recommendations ....................................................................276
15.
Schematics ...............................................................................................................................277
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Figures
Figure 1. Intel 852GME GMCH System Block Diagram .......................................................... 29
Figure 2. Intel 852PM Chipset System Block Diagram............................................................ 32
Figure 3. Intel 852GMV GMCH System Block Diagram .......................................................... 36
Figure 4. Recommended Board Stack-Up Dimensions........................................................... 38
Figure 5. Cross-Sectional View of 2:1 Ratio ............................................................................ 42
Figure 6. Cross-Sectional View of 2.5:1 Ratio ......................................................................... 43
Figure 7. Processor Topology.................................................................................................. 45
Figure 8. SS Topology for Address and Data .......................................................................... 46
Figure 9. Routing Illustration for Topology 1A ......................................................................... 47
Figure 10. Routing Illustration for Topology 1B ....................................................................... 48
Figure 11. Routing Illustration for Topology 1C ....................................................................... 49
Figure 12. Routing Illustration for Topology 2A ....................................................................... 50
Figure 13. Routing Illustration for Topology 2B ....................................................................... 51
Figure 14. Routing Illustration for Topology 2C ....................................................................... 52
Figure 15. Routing Illustration for Topology 3.......................................................................... 53
Figure 16. Voltage Translation Circuit for 3.3-V Receivers ..................................................... 54
Figure 17. Routing Recommendation for COMP[1:0] .............................................................. 55
Figure 18. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector... 56
Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector ......... 56
Figure 20. Memory Clock Routing Topology SCK/SCK#[5:0] ................................................. 67
Figure 21. Memory Clock Trace Length Matching Diagram .................................................... 70
Figure 22. Clock Signal Routing Example ............................................................................... 72
Figure 23. Data Signal Routing Topology ................................................................................ 74
Figure 24. SDQS to Clock Trace Length Matching Diagram................................................... 76
Figure 25. SDQ/SDM to SDQS Trace Length Matching Diagram ........................................... 78
Figure 26. Data Signals Group Routing Example.................................................................... 80
Figure 27. Control Signal Routing Topology............................................................................ 82
Figure 28. Control Signal to Clock Trace Length Matching Diagram ...................................... 84
Figure 29. Control Signals Group Routing Example................................................................ 85
Figure 30. Command Routing for Topology 1.......................................................................... 87
Figure 31. Topology 1 Command Signal to Clock Trace Length Matching Diagram .............. 90
Figure 32. Command Routing Topology 2 ............................................................................... 91
Figure 33. Topology 2 Command Signal to Clock Trace Length Matching Diagram .............. 94
Figure 34. Example of Command Signal Group ...................................................................... 95
Figure 35. Command Routing Topology 3 ............................................................................... 96
Figure 36. Topology 3 Command Signal to Clock Trace Length Matching Diagram .............. 99
Figure 37. Command per Clock Signal Routing Topology .................................................... 102
Figure 38. CPC Signals to Clock Length Matching Diagram................................................. 104
Figure 39. DDR Memory Thermal Sensor Placement ........................................................... 108
Figure 40. Rset Placement .................................................................................................... 110
Figure 41. GMCH DAC Routing Guidelines with Docking Connector ................................... 111
Figure 42. DAC R, G, B Routing and Resistor Layout Example............................................ 113
Figure 43. DVOB and DVOC Simulations Model................................................................... 123
Figure 44. Driver-Receiver Waveforms Relationship Specification ....................................... 123
Figure 45. DVO Enabled Simulation Model ........................................................................... 124
Figure 46. Generic Module Connector Parasitic Model......................................................... 125
Figure 47. GVREF Reference Voltage................................................................................... 127
Figure 48. AGP Layout Guidelines ........................................................................................ 132
Figure 49. DPMS Circuit ........................................................................................................139
Figure 50. Hub Interface Routing Example............................................................................ 140
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Figure 51. Single VREF/VSWING Voltage Generation Circuit for Hub Interface ................. 144
Figure 52. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit......... 145
Figure 53. Shared GMCH and ICH4-M Reference Voltage with Separate Voltage Divider
Circuit for VSWING and VREF .............................................................................. 145
Figure 54. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits
for ICH4-M and GMCH .......................................................................................... 146
Figure 55. Connection Requirements for Primary IDE Connector ........................................ 149
Figure 56. Connection Requirements for Secondary IDE Connector ................................... 150
Figure 57. PCI Bus Layout Example ..................................................................................... 153
Figure 58. Intel 82801DBM ICH4-M AC’97 – Codec Connection ......................................... 154
Figure 59. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology ................................. 155
Figure 60. Intel 82801DBM AC’97 – AC_SDOUT/AC_SYNC Topology............................... 155
Figure 61. Intel 82801DBM AC’97 – AC_SDIN Topology ..................................................... 156
Figure 62. Example Speaker Circuit...................................................................................... 159
Figure 63. Recommended USB Trace Spacing .................................................................... 160
Figure 64. USBRBIAS Connection ........................................................................................ 161
Figure 65. Good Downstream Power Connection................................................................. 163
Figure 66. Common Mode Choke Schematic ....................................................................... 163
Figure 67. SMBUS 2.0/SMLink Protocol ............................................................................... 166
Figure 68. High Power/Low Power Mixed VCC_SUSPEND/VCC_CORE Architecture ..................... 167
Figure 69. FWH VPP Isolation Circuitry ................................................................................ 170
Figure 70. RTCX1 and SUSCLK Relationship in ICH4-M..................................................... 171
Figure 71. External Circuitry for the ICH4-M Where the Internal RTC is Not Used .............. 171
Figure 72. External Circuitry for the ICH4-M RTC................................................................. 172
Figure 73. Diode Circuit to Connect RTC External Battery ................................................... 175
Figure 74. RTCRST# External Circuit for the ICH4-M RTC .................................................. 175
Figure 75. Intel 82801DBM ICH4-M/Platform LAN Connect Section.................................... 177
Figure 76. Single Solution Interconnect ................................................................................ 178
Figure 77. LAN_CLK Routing Example................................................................................. 179
Figure 78. Intel 82562ET / Intel 82562EM Termination ........................................................ 181
Figure 79. Critical Dimensions for Component Placement ................................................... 181
Figure 80. Termination Plane ................................................................................................ 183
Figure 81. Intel 82562ET/EM Disable and Power Down Circuitry ........................................ 184
Figure 82. Trace Routing....................................................................................................... 186
Figure 83. Ground Plane Separation..................................................................................... 187
Figure 84. RTC Power Well Isolation Control........................................................................ 190
Figure 85. ICH4-M CPU CMOS Signals with CPU and FWH ............................................... 191
Figure 86. Clock Distribution Diagram................................................................................... 194
Figure 87. Source Shunt Termination Topology ................................................................... 195
Figure 88. CLK66 Clock Group Topology ............................................................................. 198
Figure 89. BCLK to GCLKIN Timing Requirement................................................................ 199
Figure 90. CLK33 Group Topology ....................................................................................... 200
Figure 91. PCI Clock Group Topology .................................................................................. 201
Figure 92. CLK14 Clock Group Topology ............................................................................. 202
Figure 93. DOTCLK Clock Topology..................................................................................... 203
Figure 94. SSCCLK Clock Topology ..................................................................................... 204
Figure 95. USBCLK Clock Topology ..................................................................................... 205
Figure 96. Platform Power Delivery Architectural Block Diagram......................................... 208
Figure 97. GMCH / ICH4-M Platform Power-Up Sequence .................................................. 211
Figure 98. Power On Sequencing Timing Diagram (VR Circuitry)........................................ 213
Figure 99. Example V5REF / 3.3 V Sequencing Circuitry ......................................................... 214
Figure 100. V5REF_SUS with 5V_ALWAYS Connection Option (Recommended) ............. 214
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Figure 101. V5REF_SUS with 3.3V_ALWAYS and VCC5 or VCC5_SUS Connection
Option ..................................................................................................................... 215
Figure 102. DDR Power Delivery Block Diagram .................................................................. 217
Figure 103. DDR SMRCOMP Resistive Compensation ........................................................ 223
Figure 104. SMVSWINGL and SMVSWINGH Reference Voltage Generation Circuit.......... 223
Figure 105. Decoupling Capacitors Placement and Connectivity.......................................... 225
Figure 106. Minimized Loop Inductance Example................................................................. 228
Figure 107. Example Analog Supply Filter............................................................................. 230
Figure 108. Routing Illustration for INIT# ............................................................................... 241
Figure 109. VCCIOPLL, VCCA and VSSA Power Distribution.............................................. 241
Figure 110. Voltage Translation Circuit for PROCHOT# ....................................................... 241
Figure 111. Mobile Intel Pentium 4 Processor Power Up Sequence..................................... 244
Figure 112. Clock Power-down Implementation .................................................................... 246
Figure 113. Reference Voltage Level for SMVREF ............................................................... 248
Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit ........ 250
Figure 115. DPMS Clock Implementation.............................................................................. 253
Figure 116. Q-SWITCH Circuit .............................................................................................. 254
Figure 117. 852GME Power-up Sequence............................................................................ 258
Figure 118. Separated GMCH and ICH4-M VSWING/VREF Reference Voltage Circuit...... 266
Figure 119. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING
Circuit...................................................................................................................... 267
Figure 120. Single Generated GMCH and ICH4-M VSWING/VREF Reference
Voltage/ Local Voltage Divider Circuit for VSWING/VREF .................................... 267
Figure 121. External Circuitry for the RTC............................................................................. 268
Figure 122. ICH4 Power-up Sequence Waveforms............................................................... 273
Figure 123. Good Downstream Power Connection ............................................................... 274
Figure 124. LAN_RST# Design Recommendation ................................................................ 276
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Tables
Table 1. System Bus Routing Summary for the Processor..................................................... 41
Table 2. Processor System Bus Data Signal Routing Guidelines........................................... 45
Table 3. Processor System Bus Address Signal Routing Guidelines ..................................... 45
Table 4. Processor System Bus Control Signal Routing Guidelines....................................... 46
Table 5. Layout Recommendations for Topology 1A .............................................................. 47
Table 6. Layout Recommendations for Topology 1B .............................................................. 48
Table 7. Layout Recommendations for Topology 1C.............................................................. 49
Table 8. Layout Recommendations for Topology 2A .............................................................. 50
Table 9. Layout Recommendations for Topology 2B .............................................................. 51
Table 10. Layout Recommendations for Topology 2C............................................................ 52
Table 11. Layout Recommendations for Topology 3 .............................................................. 53
Table 12. Layout Recommendation for COMP[1:0] ................................................................ 55
Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector........ 57
Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths........... 58
Table 15. GMCH/MCH Chipset Memory Signal Groups ......................................................... 65
Table 16. Intel 852GME/852GMV/852PMChipset GMCH/MCH DDR 333 Length Matching
Formulas .................................................................................................................. 66
Table 17. Clock Signal Mapping.............................................................................................. 67
Table 18. Clock Signal Group Routing Guidelines.................................................................. 68
Table 19. Memory Clock Package Lengths............................................................................. 71
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing
Guidelines ................................................................................................................ 74
Table 21. SDQ/SDM to SDQS Mapping.................................................................................. 77
Table 22. Memory SDQ/SDM/SDQS Package Lengths ......................................................... 79
Table 23. Control Signal to SO-DIMM Mapping ...................................................................... 81
Table 24. Control Signal Routing Guidelines .......................................................................... 82
Table 25. Control Group Package Lengths ............................................................................. 86
Table 26. Command Topology 1 Routing Guidelines ............................................................. 88
Table 27. Command Topology 2 Routing Guidelines ............................................................. 92
Table 28. Command Topology 3 Routing Guidelines ............................................................. 97
Table 29. Command Group Package Lengths...................................................................... 100
Table 30. CPC Signal to SO-DIMM Mapping ........................................................................ 101
Table 31. CPC Signal Routing Guidelines ............................................................................ 102
Table 32. CPC Group Package Lengths ............................................................................... 104
Table 33. Recommended GMCH DAC Components............................................................ 112
Table 34. Signal Group and Signal Pair Names ................................................................... 115
Table 35. LVDS Signal Group Routing Guidelines ............................................................... 116
Table 36. LVDS Package Lengths ........................................................................................ 117
Table 37. DVO Interface Trace Length Mismatch Requirements ......................................... 119
Table 38. DVOB and DVOC Routing Guideline Summary.................................................... 120
Table 39. DVOB Interface Package Lengths ........................................................................ 121
Table 40. DVOC Interface Package Lengths ........................................................................ 122
Table 41. Allowable Interconnect Skew Calculation ............................................................. 124
Table 42. DVO Enabled Routing Guideline Summary .......................................................... 125
Table 43. GMBUS Pair Mapping and Options....................................................................... 126
Table 44. AGP 2.0 Signal Groups ......................................................................................... 129
Table 45. AGP 2.0 Data/Strobe Associations ....................................................................... 130
Table 46. Layout Routing Guidelines for AGP 1X Signals .................................................... 131
Table 47. Layout Routing Guidelines for AGP 2X/4X Signals............................................... 133
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Table 48. AGP 2.0 Data Lengths Relative to Strobe Length ................................................. 133
Table 49. AGP 2.0 Routing Guideline Summary ................................................................... 134
Table 50. AGP Interface Package Lengths ........................................................................... 135
Table 51. AGP Pull-Up/Pull-Down Requirements and Straps ............................................... 137
Table 52. AGP 2.0 Pull-up Resistor Values ........................................................................... 137
Table 53. Hub Interface RCOMP Resistor Values................................................................. 140
Table 54. Hub Interface Signals Internal Layer Routing Summary ....................................... 141
Table 55. Hub Interface Package Lengths for ICH4-M.......................................................... 142
Table 56. Hub Interface Package Lengths for GMCH ...........................................................142
Table 57. Hub Interface VREF/VSWING Reference Voltage Specifications......................... 143
Table 58. Recommended Resistor Values for Single VREF/VSWING Divider Circuit .......... 144
Table 59. Recommended Resistor Values for Separate HIVREF and HI_VSWING
Divider Circuits ....................................................................................................... 145
Table 60. Recommended Resistor Values for HIVREF and HI_VSWING Divider
Circuits for ICH4-M ................................................................................................. 146
Table 61. AC’97 AC_BIT_CLK Routing Summary................................................................. 155
Table 62. AC’97 AC_SDOUT/AC_SYNC Routing Summary ................................................ 156
Table 63. AC’97 AC_SDIN Routing Summary....................................................................... 156
Table 64. Supported Codec Configurations........................................................................... 158
Table 65. USBRBIAS/USBRBIAS# Routing Summary.......................................................... 161
Table 66. USB 2.0 Trace Length Guidelines (With Common-mode Choke) ......................... 161
Table 67. Bus Capacitance Reference Chart ........................................................................ 168
Table 68. Bus Capacitance/Pull-Up Resistor Relationship.................................................... 168
Table 69. RTC Routing Summary.......................................................................................... 172
Table 70. LAN Component Connections/Features ................................................................ 177
Table 71. LAN Design Guide Section Reference .................................................................. 178
Table 72. LAN LOM Routing Summary ................................................................................. 179
Table 73. Intel 82562ET/EM Control Signals......................................................................... 184
Table 74. Individual Clock Breakdown................................................................................... 193
Table 75. Host Clock Group Routing Constraints.................................................................. 196
Table 76. CLK66 Clock Group Routing Constraints .............................................................. 198
Table 77. CLK33 Clock Group Routing Constraints .............................................................. 200
Table 78. PCICLK Clock Group Routing Constraints ............................................................ 201
Table 79. CLK14 Clock Group Routing Constraints .............................................................. 202
Table 80. DOTCLK Clock Routing Constraints...................................................................... 203
Table 81. SSCCLK Clock Routing Constraints...................................................................... 204
Table 82. USBCLK Clock Routing Constraints...................................................................... 205
Table 83. Power Management States.................................................................................... 209
Table 84. Power Supply Rail Descriptions............................................................................. 210
Table 85. Timing Sequence Parameters for Figure 97.......................................................... 212
Table 86. Timing Sequence Parameters for Figure 98.......................................................... 213
Table 87. DDR Power-Up Initialization Sequence ................................................................. 216
Table 88. Absolute vs. Relative Voltage Specification........................................................... 219
Table 89. DDR-SDRAM SO-DIMM Voltage and Current Requirements............................... 219
Table 90. Intel GMCH System Memory Voltage and Current Requirements ........................ 220
Table 91. Termination Voltage and Current Requirements ................................................... 220
Table 92. GMCH System Memory I/O SMVREF Calculation ................................................ 221
Table 93. Effects of Varying Resistor Values in the Divider Circuit ....................................... 221
Table 94. DDR VREF Calculation.......................................................................................... 222
Table 95. Reference Distortion Due to Load Current ............................................................ 222
Table 96. Processor Decoupling Recommendation .............................................................. 226
Table 97. GMCH Decoupling Recommendations.................................................................. 226
Table 98. Decoupling Requirements for the Intel ICH4-M.....................................................228
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Table 99. Analog Supply Filter Requirements....................................................................... 231
Table 100. Icc Maximum Sustained Estimates (Icc REV0.3)................................................ 232
Table 101. Intel ICH4-M Power Consumption Measurements.............................................. 232
Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power ...... 233
Table 103. Intel ICH4-M Component Thermal Design Power............................................... 233
Table 104. GMCH “Intel Reserved” Signal Pin-Map Locations............................................. 235
Table 105. GST[2:0] Configurations...................................................................................... 256
Table 106. ICH4-M Power-up Timing Specifications ............................................................ 272
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Revision History
Rev.
Document
Number
Description
Date
-001
253026
Initial Release
June 2003
-002
253026
Updates include:
February 2004
Added information for 852GMV
-003
253026
Updates include:
May 2004
Added information for Mobile Intel Pentium 4 Processor supporting
Hyper-Threading Technology on 90-nm process technology
-004
253026
Updates include:
June 2004
Added information for Intel Celeron D Processor on 90 nm
process and in the 478-pin package
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1.
Introduction
This design guide provides Intel design recommendations for the Intel® 852GME, Intel® 852GMV
GMCH and the Intel® 852PM MCH chipset based systems. These design guidelines ensure maximum
flexibility for board designers while reducing the risk of board related issues. The Intel 852GME, Intel
852GMV and Intel 852PM chipsets are pin compatible. Carefully follow the design information and
debug recommendations in this document.
The Mobile Intel® Pentium® 4 processor, Mobile Intel® Pentium® 4 processor supporting HyperThreading Technology on 90-nm process technology, Intel® Celeron® processor, or the Intel® Celeron®
D processor on 90 nm process and in the 478-pin package in combination with the 852GME, 852GMV
or 852PM deliver high performance and professional mobile platform solution using internal and/or
external graphics. Section 2 provides an overview of system features of supported processor and chipset
combinations.
All recommendations will apply to all platforms unless specified. Any references to GMCH apply to all
platforms unless otherwise specified. Any reference to Mobile Intel Pentium 4 processor apply to
Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process
technology unless specified. Any reference to the Intel® Celeron® processor applies to the Intel®
Celeron® D processor on 90 nm process and in the 478-pin package unless specified.
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Introduction
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1.1.
Referenced Documents
Document
Document No./Location
®
®
http://developer.intel.com/
®
®
http://developer.intel.com/
Mobile Intel Pentium 4 Processor Datasheet
Mobile Intel Pentium 4 Processor supporting HyperThreading Technology on 90-nm process technology
Datasheet
®
®
http://developer.intel.com/
®
®
http://developer.intel.com/
Intel Celeron Processor on .13 Micron Process
Datasheet
Intel Celeron D Processor on 90 nm Process and in the
478-pin Package Datasheet
®
®
Intel 852GME Chipset GMCH and Intel 852PM Chipset
MCH Datasheet
®
®
http://developer.intel.com/
Intel 852GM/852GMV Chipset GMCH Datasheet
®
http://developer.intel.com/
®
http://developer.intel.com/
®
http://developer.intel.com/
®
http://developer.intel.com/
Intel DDR 200 JEDEC Spec Addendum Rev 0.9 or later
®
http://developer.intel.com/
Application Note AP-728: ICH/ICH2/ICH2M/ICH4S/ICH4M
Real Time Clock (RTC) Accuracy and Considerations
Under Test Conditions
http://developer.intel.com/
ITP700 Debug Port Design Guide
http://developer.intel.com/
JEDEC Standard, JESD79, Double Data Rate (DDR)
SDRAM Specification
http://www.jedec.org/
PC2100 DDR SDRAM Unbuffered SO-DIMM Reference
Design Specification
http://www.jedec.org/
Intel 852GME and Intel 852PM Chipset GMCH
Specification Update
Intel 852GM/852GMV Chipset GMCH Specification
Update
Intel I/O Controller Hub -Mobile(ICH4-M) Datasheet
Intel I/O Controller Hub-Mobile (ICH4-M) Specification
Update
20
http://developer.intel.com/
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
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1.2.
Conventions and Terminology
Terminology
Definition
AC
Audio Codec
AGP
Accelerator Graphic Port
AMC
Audio/Modem Codec
Anti-Etch
Any plane-split, void or cutout in a VCC or GND plane is referred to as an anti-etch
BER
Bit Error Rate
CMC
Common Mode Choke
EMI
Electro Magnetic Interference
ESD
Electrostatic Discharge
FS
Full Speed – Refers to USB 1.1 full speed
FWH
Firmware Hub – A non-volatile memory device used to store the system BIOS.
FSB
Front Side Bus – processor to GMCH interface
GMCH
Graphics Memory Controller Hub
HS
High Speed – Refers to USB 2.0
ICH4-M
I/O Controller Hub Fourth Generation – Mobile
LOM
LAN on Motherboard
LPC
Low Pin Count
LS
Low Speed – Refers to USB 1.0 low speed
MC
Modem Codec
MCH
Memory controller hub
PCM
Pulse Code Modulation
PLC
Platform LAN Connect
RTC
Real Time Clock
SMBus
System Management Bus – A two-wire interface through which various system
components can communicate
SPD
Serial Presence Detect
S/PDIF
Sony*/Phillips* Digital Interface
STD
Suspend-To-Disk
STR
Suspend-To-Ram
TCO
Total Cost of Ownership
UBGA
Micro Ball Grid Array
USB
Universal Serial Bus
VRM
Voltage Regulator Module
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2.
System Overview
2.1.
Intel 852GME Chipset Platform System Features
The 852GME chipset contains two core components: the Intel 852GME GMCH and the Intel ICH4-M.
The GMCH integrates the following
400/533 MHz FSB controller
266/333 MHz DDR controller
DVO muxed AGP interface, integrated graphics controller provides 3D, 2D, and display
capabilities while using a portion of system memory for graphics memory (UMA) to provide a cost
effective, high performance graphics solution
High-speed Accelerated Hub Architecture interface for communication with the ICH4-M
The ICH4-M integrates the following:
Ultra ATA 100/66/33 controller
USB host controller that supports the USB 1.1 and USB 2.0 specification
LPC interface
FWH Flash BIOS interface controller
PCI interface controller
AC’97 digital controller and a hub interface for communication with the GMCH. The 852GME
GMCH is a Graphics Memory Controller Hub (GMCH) designed for Mobile Intel Pentium 4
processor and Intel Celeron processor.
For further information about the 852GME platform features, refer to the Intel® 852GME Chipset
GMCH and Intel® 852PM Chipset MCH Datasheet and the Intel® 82801DBM I/O Controller Hub
(ICH4-M) Datasheet.
2.1.1.
Host Interface
The Intel 852GME GMCH can utilize a single processor. It supports a FSB frequency of 400/533 MHz
(100/133 MHz HCLK respectively) using scaleable FSB VCC.
2.1.1.1. Mobile Intel Pentium 4 Processor supporting Hyper-Threading
Technology on 90-nm process technology
Intel’s Mobile Intel® Pentium® 4 processor supporting Hyper-Threading Technology on 90-nm process
technology is a follow on to the Mobile Intel Pentium 4 processor in the 478-pin package with
enhancements to the Intel® NetBurstTM microarchitecture. The processor utilizes Flip-Chip Pin Grid
Array (FC-mPGA4) package technology, and plugs into a zero insertion force (ZIF) socket. The Mobile
Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process technology, like
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its predecessor, the Mobile Intel Pentium 4 processor in the 478-pin package, is based on the same Intel
32-bit microarchitecture and maintains the tradition of compatibility with IA-32 software.
The Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90-nm process
technology supports Hyper-Threading Technology. Hyper-Threading Technology allows a single,
physical processor to function as two logical processors. While some execution resources such as
caches, execution units, and buses are shared, each logical processor has its own architecture state with
its own set of general-purpose registers, control registers to provide increased system responsiveness in
multitasking environments, and headroom for next generation multi threaded applications. Intel
recommends enabling Hyper-Threading Technology with Microsoft Windows* XP Professional or
Windows*XP Home, and disabling Hyper-Threading Technology via the BIOS for all previous versions
of Windows operating systems. For more information on Hyper-Threading Technology, see
www.intel.com/info/hyperthreading. Refer to Section 6.1 for Hyper-Threading Technology
configuration details.
In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new
instructions, which further extend the capabilities of Intel processor technology. These new instructions
are called Streaming SIMD Extensions 3 (SSE3).These new instructions enhance the performance of
optimized applications for the digital home such as video, image processing and media compression
technology. 3D graphics and other entertainment applications such as gaming will have the opportunity
to take advantage of these new instructions as platforms with the Mobile Intel Pentium 4 processor
supporting Hyper-Threading Technology on 90-nm process technology and SSE3 become available in
the market place. The Mobile Intel Pentium 4 processor supporting Hyper-Threading Technology on 90nm process technology’s Intel NetBurst microarchitecture front side bus (FSB) utilizes a splittransaction, deferred reply protocol like the Mobile Pentium 4 processor. The Intel NetBurst
microarchitecture front side bus uses Source-Synchronous Transfer (SST) of address and data to
improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP
4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a "double-locked" or 2X address bus. Working together, the 4X data bus and 2X address
bus provide a data bus bandwidth of up to 4.3 GB/s.
The processor will feature Enhanced Intel SpeedStep® technology, which will enable real-time dynamic
switching between multiple voltages and operating frequency points. This results in optimal
performance without compromising low power. The processor features the Auto Halt, Stop Grant, Deep
Sleep, and Deeper Sleep low power states. The processor includes an address bus powerdown capability
which removes power from the address and data pins when the FSB is not in use. This feature is always
enabled on the processor.
Advanced transfer cache is a 1-MB, on-die level 2 (L2) cache
2.1.1.2.
Mobile Intel Pentium 4 Processor
The Mobile Intel Pentium 4 processor is based on the Intel NetBurst® micro-architecture. The Mobile
Intel Pentium 4 processor utilizes a 478-pin, Micro Flip-Chip Pin Grid Array (Micro-FCPGA) package
with Integrated Heat Spreader, and plugs into a surface-mount, Zero Insertion Force (ZIF) socket. The
Mobile Intel Pentium 4 processor maintains full compatibility with IA-32 software.
The Mobile Intel Pentium 4 processor is designed for uni-processor based high-performance systems.
Features of the processor include:
Hyper pipelined technology
533-MHz system bus quad-pumped bus running off a 133-MHz system clock making 4.3 GB/sec
data transfer rates possible
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The execution trace cache is a first level cache that stores approximately 12k decoded microoperations, which removes the decoder from the main execution path.
Advanced transfer cache is a 512-kB, on-die level 2 (L2) cache
2.1.1.3.
Intel Celeron D Processor on 90 nm process and in the 478-pin package
The Intel® Celeron® D processor on 90 nm process and in the 478-pin package uses Flip-Chip Pin Grid
Array 4 (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero Insertion Force
(ZIF) socket, referred to as the mPGA478B socket. The Intel® Celeron® D processor on 90 nm process
and in the 478-pin package is based on the same Intel 32-bit microarchitecture and maintains the
tradition of compatibility with IA-32 software.
In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new
instructions that further extend the capabilities of Intel processor technology. These new instructions are
called Steaming SIMD Extensions 3 (SSE3).
The Celeron D processor’s Front Side Bus (FSB) uses a split-transaction, deferred reply protocol like
the Intel® Pentium 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address and data
to improve performance by transferring data four times per bus clock (4X data transfer rate, as in AGP
4X). Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is
referred to as a "double-clocked" or 2X address bus. Working together, the 4X data bus and 2X address
bus provide a data bus bandwidth of up to 4.2 GB/s.
The processor includes an address bus powerdown capability that removes power from the address and
data pins when the FSB is not in use. This feature is always enabled on the processor.
2.1.1.4.
Intel Celeron Processor
The Intel Celeron processor utilizes Flip-Chip Pin Grid Array (FC-PGA2) package technology, and
plugs into a 478-pin surface mount, Zero Insertion Force (ZIF) socket, referred to as the mPGA478B
socket. The Intel Celeron processor maintains the tradition of compatibility with IA-32 software.
The Intel Celeron processor is designed for uni-processor based value systems. Features of the processor
include:
Hyper pipelined technology
400-MHz system bus quad-pumped bus running off a 100-MHz system clock making 3.2 GB/sec
data transfer rates possible
The execution trace cache is a first level cache that stores approximately 12-k, decoded microoperations, which removes the decoder from the main execution path.
2.1.2.
Intel 852GME Graphics Memory Controller Hub (GMCH)
2.1.2.1.
Multiplexed AGP and Intel® DVO Interface
The 852GME GMCH multiplexes an AGP interface with two Intel DVOs. The DVO ports can each
support a single channel DVO device. If both ports are active in single channel mode, they will have
identical display timings and data. Alternatively the DVO ports can combine to support dual channel
devices supporting higher resolutions and refresh rates. When an external AGP device is installed in the
system, all internal graphics driver (IGD) functionality are disabled.
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2.1.2.2.
Accelerated Graphics Port (AGP) Interface
Supports AGP 2.0 data transfers
Supports a single AGP (1X/2X/4X) device (either via a connector or on the motherboard)
Only supports 1.5-V VDDQ for AGP electricals
PCI semantic (FRAME# initiated) accesses to DRAM are snooped
AGP semantic (PIPE# and SBA) traffic to DRAM is not snooped on the FSB and is therefore not
coherent with the CPU caches
High priority access support
Delayed transaction support for AGP reads that cannot be serviced immediately
AGP Busy/Stop Protocol support
Support for D3 Hot and Cold Device states
AGP Clamping and Sense Amp control
2.1.2.3.
Integrated System Memory DRAM Controller
Supports up to two double-sided SO-DIMMs (four rows populated) with unbuffered
PC2100/PC2700 DDR-SDRAM (with or without ECC)
Supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb technologies for x8 and x16 width devices
Up to 1 GB (with 256-Mb technology and two SO-DIMMs) of PC2100/2700 DDR (with ECC) and
up to 2 GB (high density using 512-Mb technology)
Supports 266-MHz and 333-MHz DDR devices
64-bit data interface (72-bit with ECC)
Supports up to 16 simultaneous open pages
Support for SO-DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power
management support via self refresh mode using CKE
2.1.2.4.
Internal Graphics Controller
Graphics Core Frequency
Display / Render frequency up to 266 MHz
3D Graphics Engine
3D Setup and Render Engine
Zone Rendering
High quality performance Texture Engine
Analog Display Support
350-MHz integrated 24-bit RAMDAC
Hardware color cursor support
Accompanying I2C and DDC channels provided through multiplexed interface
Dual independent pipe for dual independent display
Simultaneous display: same images and native display timings on each display device
Digital Video Out Port (DVOB & DVOC) support
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DVOB & DVOC with 165-MHz dot clock support for each 12-bit interface
Compliant with DVI Specification 1.5
Dedicated LFP (local flat panel) support
Single or dual channel LVDS panel support up to UXGA panel resolution with frequency
range from 25 MHz to 112 MHz per channel
SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock
Supports data format of 18 bpp
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear Panel fitting
2.1.3.
Package/Power
732-pin Micro-FCBGA (37.5 mm x 37.5 mm)
VTTLF, VTTHF (1.05 V)
VCC, VCCASM, VCCHL, VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB (1.5 V)
VCCADAC, VCCDVO, VCCDLVDS, VCCALVDS, (1.5 V)
VCCSM, VCCQSM, VCCTXLVDS (2.5 V)
VCCGPIO (3.3 V)
2.1.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
Upstream Accelerated Hub Architecture interface for access to the GMCH
PCI 2.2 interface (6 PCI Request/Grant Pairs)
Bus Master IDE controller (supports Ultra ATA 100/66/33)
USB 1.1 and USB 2.0 Host Controllers
I/O APIC
SMBus 2.0 Controller
FWH Interface
LPC Interface
AC’97 2.2 / 2.3 Interface
Alert-On-LAN*
IRQ Controller
Package/Power
421-pin, BGA package (31 mm x 31 mm)
VCC1_5 (1.5 V main logic voltage), VCC3_3 (3.3 V main I/O voltage)
VCCSUS1_5 (1.5 V resume logic voltage), VCCSUS3_3 (3.3 V resume I/O voltage)
VCCLAN1_5 (1.5 V LAN logic voltage), VCCLAN3_3 (3.3 V LAN I/O voltage)
V5REF (5 V) , V5REF_SUS (5 V)
VCCRTC (2.0V – 3.3V)
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VCCHI (1.5 V)
2.1.5.
Firmware Hub (FWH)
An integrated hardware Random Number Generator (RNG)
Register-based locking
Hardware-based locking
5 GPIs
Package/Power
32-pin TSOP/PLCC
3.3-V core and 3.3 V/12 V for fast programming
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Figure 1. Intel 852GME GMCH System Block Diagram
Intel
Processor
CRT
RGB
400/533 MHz PSB
Panel
DVO Device /
AGP
Graphic
Controller
LVDS
DVO/AGP
Intel® 852GME
GMCH
732 Micro-FCBGA
200/266/333MHz
DDR
266 MHz HUB
Interface
ATA100 IDE (2)
LAN
USB 2.0/1.1 (6)
Intel ® 82801
DBM ICH4-M
421 BGA
Audio Codec
PCI 33MHz
AC’97 2.2
Moon2
Cardbus
LPC I/P
Audio Codec
FWH
SIO
KBC
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2.2.
Intel 852PM Chipset Platform System Features
The 852PM chipset contains two core components: the Intel 852PM GMCH and the Intel ICH4-M. The
MCH integrates following:
533 MHz FSB controller
266/333 MHz DDR controller
DVO muxed AGP interface
High-speed Accelerated Hub Architecture interface for communication with the ICH4-M
The ICH4-M integrates the following:
Ultra ATA 100/66/33 controller
USB host controller that supports the USB 1.1 and USB 2.0 specification
LPC interface
FWH Flash BIOS interface controller
PCI interface controller
AC’97 digital controller and a hub interface for communication with the GMCH. The 852PM MCH
is a Memory Controller Hub (MCH) designed for Mobile Intel Pentium 4 processor.
For further information about the 852PM platform features, reference the Intel® 852GME Chipset
GMCH and Intel® 852PM Chipset MCH Datasheet and the Intel® 82801DBM I/O Controller Hub
(ICH4-M) Datasheet.
2.2.1.
Host Interface
The 852PM MCH can utilize a single processor. It supports a FSB frequency of 400/533 MHz (100/133
MHz HCLK respectively) using scaleable FSB VCC.
2.2.1.1.
Mobile Intel Pentium 4 Processor
Please refer to Section 2.1.1.1 and Section 2.1.1.2
2.2.1.2.
Intel Celeron Processor
Please refer to Section2.1.1.3 and Section 2.1.1.4.
2.2.2.
852PM Memory Controller Hub (MCH)
2.2.2.1.
Accelerated Graphics Port (AGP) Interface
Supports AGP 2.0 data transfers
Supports a single AGP (1X/2X/4X) device (either via a connector or on the motherboard)
Only supports 1.5-V VDDQ for AGP electrical
PCI semantic (FRAME# initiated) accesses to DRAM are snooped
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AGP semantic (PIPE# and SBA) traffic to DRAM is not snooped on the FSB and is therefore not
coherent with the CPU caches
High priority access support
Delayed transaction support for AGP reads that cannot be serviced immediately
AGP Busy/Stop Protocol support
Support for D3 Hot and Cold Device states
AGP Clamping and Sense Amp control
2.2.2.2.
Integrated System Memory DRAM Controller
Supports up to two double-sided SO-DIMMs (4 rows populated) with unbuffered PC2100/PC2700
DDR-SDRAM (with or without ECC)
Supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb technologies for x8 and x16 width devices
Up to 1 GB (with 256-Mb technology and two SO-DIMMs) of PC2100/2700 DDR (with ECC) and
up to 2 GB (high density using 512-Mb technology)
Supports 266-MHz and 333-MHz DDR devices
64-bit data interface (72-bit with ECC)
Supports up to 16 simultaneous open pages
Support for SO-DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power
management support via self refresh mode using CKE
2.2.3.
Package/Power
732-pin Micro-FCBGA (37.5 mm x 37.5 mm)
VTTLF, VTTHF (1.05 V)
VCC, VCCASM, VCCHL, VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB (1.5 V)
VCCADAC, VCCDVO, VCCDLVDS, VCCALVDS, (1.5 V)
VCCSM, VCCQSM, VCCTXLVDS (2.5 V)
VCCGPIO (3.3 V)
2.2.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
Please refer to Section 2.1.4.
2.2.5.
Firmware Hub (FWH)
Please refer to Section 2.1.5.
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Figure 2. Intel 852PM Chipset System Block Diagram
Intel®
Processor
400/533MHz
AGP
Controller
AGP 2.0
Intel
852PM
MCH
732 Micro-FCBGA
HUB
Interface
ATA100 IDE (2)
USB 2.0/1.1 (6)
Audio Codec
200/266/333
MHz
DDR
Intel
82801 DBM
421 BGA
(ICH4-M)
421 BGA
LAN
PCI 33MHz
AC’97 2.2
Moon2
Cardbus
LPC I/P
Audio Codec
FWH
SIO
KBC
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2.3.
Intel 852GMV Chipset Platform System Features
The 852GMV chipset contains two core components: the Intel 852GMV GMCH and the Intel ICH4-M.
The GMCH integrates the following
400/533 MHz FSB controller
200/266 MHz DDR controller
Integrated graphics controller provides 3D, 2D, and display capabilities while using a portion of
system memory for graphics memory (UMA) to provide a cost effective, high performance
graphics solution
High-speed Accelerated Hub Architecture interface for communication with the ICH4-M
The ICH4-M integrates the following:
Ultra ATA 100/66/33 controller
USB host controller that supports the USB 1.1 and USB 2.0 specification
LPC interface
FWH Flash BIOS interface controller
PCI interface controller
AC’97 digital controller and a hub interface for communication with the GMCH. The 852GME
GMCH is a Graphics Memory Controller Hub (GMCH) designed for Mobile Intel Pentium 4
processor, Intel Celeron processor and Intel Celeron D processor on 90 nm process and in the 478pin package..
For further information about the 852GMV platform features, refer to the Intel® 852GM/GMV Chipset
GMCH Datasheet and the Intel® 82801DBM I/O Controller Hub (ICH4-M) Datasheet.
2.3.1.
Host Interface
The Intel 852GMV GMCH can utilize a single processor. It supports a FSB frequency of 400/533 MHz
(100/133 MHz HCLK respectively) using scaleable FSB VCC.
2.3.1.1.
Intel Celeron Processor
Please refer to Section2.1.1.3 and Section 2.1.1.4.
2.3.2.
Intel 852GMV Graphics Memory Controller Hub (GMCH)
2.3.2.1.
Multiplexed AGP and Intel® DVO Interface
The 852GME GMCH multiplexes an AGP interface with two Intel DVOs. The DVO ports can each
support a single channel DVO device. If both ports are active in single channel mode, they will have
identical display timings and data. Alternatively the DVO ports can combine to support dual channel
devices supporting higher resolutions and refresh rates.
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2.3.2.2.
Integrated System Memory DRAM Controller
Supports up to two double-sided SO-DIMMs (four rows populated) with unbuffered PC2100 DDRSDRAM (with or without ECC)
Supports 64 Mb, 128 Mb, 256 Mb, and 512 Mb technologies for x8 and x16 width devices
Up to 1 GB (with 256-Mb technology and two SO-DIMMs) of PC2100 DDR (with ECC) and up to
2 GB (high density using 512-Mb technology)
Supports 200-MHz and 266-MHz DDR devices
64-bit data interface (72-bit with ECC)
Supports up to 16 simultaneous open pages
Support for SO-DIMM Serial Presence Detect (SPD) scheme via SMBus interface STR power
management support via self refresh mode using CKE
2.3.2.3.
Internal Graphics Controller
Graphics Core Frequency
Display / Render frequency up to 133 MHz
3D Graphics Engine
3D Setup and Render Engine
Zone Rendering
High quality performance Texture Engine
Analog Display Support
350-MHz integrated 24-bit RAMDAC
Hardware color cursor support
Accompanying I2C and DDC channels provided through multiplexed interface
Dual independent pipe for dual independent display
Simultaneous display: same images and native display timings on each display device
Digital Video Out Port (DVOB & DVOC) support
DVOB & DVOC with 165-MHz dot clock support for each 12-bit interface
Compliant with DVI Specification 1.5
Dedicated LFP (local flat panel) support
Single or dual channel LVDS panel support up to UXGA panel resolution with frequency
range from 25 MHz to 112 MHz per channel
SSC support of 0.5%, 1.0%, and 2.5% center and down spread with external SSC clock
Supports data format of 18 bpp
LCD panel power sequencing compliant with SPWG timing specification
Compliant with ANSI/TIA/EIA –644-1995 spec
Integrated PWM interface for LCD backlight inverter control
Bi-linear Panel fitting
2.3.3.
Package/Power
732-pin Micro-FCBGA (37.5 mm x 37.5 mm)
VTTLF, VTTHF (1.05 V)
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VCC, VCCASM, VCCHL, VCCAHPLL, VCCAGPLL, VCCADPLLA, VCCADPLLB (1.5 V)
VCCADAC, VCCDVO, VCCDLVDS, VCCALVDS, (1.5 V)
VCCSM, VCCQSM, VCCTXLVDS (2.5 V)
VCCGPIO (3.3 V)
2.3.4.
Intel 82801DBM I/O Controller Hub 4-Mobile (ICH4-M)
Upstream Accelerated Hub Architecture interface for access to the GMCH
PCI 2.2 interface (6 PCI Request/Grant Pairs)
Bus Master IDE controller (supports Ultra ATA 100/66/33)
USB 1.1 and USB 2.0 Host Controllers
I/O APIC
SMBus 2.0 Controller
FWH Interface
LPC Interface
AC’97 2.2 / 2.3 Interface
Alert-On-LAN*
IRQ Controller
Package/Power
421-pin, BGA package (31 mm x 31 mm)
VCC1_5 (1.5 V main logic voltage), VCC3_3 (3.3 V main I/O voltage)
VCCSUS1_5 (1.5 V resume logic voltage), VCCSUS3_3 (3.3 V resume I/O voltage)
VCCLAN1_5 (1.5 V LAN logic voltage), VCCLAN3_3 (3.3 V LAN I/O voltage)
V5REF (5 V) , V5REF_SUS (5 V)
VCCRTC (2.0V – 3.3V)
VCCHI (1.5 V)
2.3.5.
Firmware Hub (FWH)
An integrated hardware Random Number Generator (RNG)
Register-based locking
Hardware-based locking
5 GPIs
Package/Power
32-pin TSOP/PLCC
3.3-V core and 3.3 V/12 V for fast programming
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Figure 3. Intel 852GMV GMCH System Block Diagram
®
®
Intel Celeron
Processor or
®
®
Intel Celeron D
Processor
CRT
RGB
400/533 MHz
Panel
DVO Device
LVDS
DVO
Intel® 852GMV
GMCH
732 Micro-FCBGA
200/266MHz
DDR
Graphic
Controller
266 MHz HUB
Interface
ATA100 IDE (2)
LAN
USB 2.0/1.1 (6)
Intel ® 82801
DBM ICH4-M
421
Audio Codec
PCI 33MHz
AC’97 2.2
Moon2
Cardbus
LPC I/P
Audio Codec
FWH
SIO
KBC
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3.
General Design Considerations
This section documents motherboard layout and routing guidelines. It does not discuss the functional
aspects of a bus or the layout guidelines for an add-in device.
Note: If the guidelines listed in this document are not followed, then thorough signal integrity and timing
simulations should be completed for each design. Even when the guidelines are followed, Intel
recommends that critical signals be simulated to ensure proper signal integrity and flight time. Any
deviation from the guidelines should be simulated.
The trace impedance typically noted (i.e. 55 ± 15% except for FSB signals 53 ± 15%) is the
“nominal” trace impedance for a 5-mil wide external trace and a 4-mil wide internal trace. However,
some stack-ups may lead to narrower or wider traces on internal or external layers in order to meet the
55- impedance target. It is important to consider the minimum and maximum impedance of a trace
based on the switching of neighboring traces when calculating flight times. Using wider spaces between
the traces can minimize this trace-to-trace coupling. In addition, these wider spaces reduce settling time.
Coupling between two traces is a function of the coupled length, the distance separating the traces, the
signal edge rate, and the degree of mutual capacitance and inductance. In order to minimize the effects
of trace-to-trace coupling, the routing guidelines documented in this section should be followed. Also,
all high speed, impedance controlled signals (e.g. FSB signals) should have continuous GND referenced
planes and cannot be routed over or under power/GND plane splits.
3.1.
Recommended Board Stack-Up
The Intel® 852GME/852GMV/852PM chipset based platforms require a board stack-up yielding a target
impedance of 55 ± 15%. Figure 4 shows an example of an 8-layer board stack-up. The left side of the
figure illustrates the starting dimensions of the metal and dielectric material thickness as well as drawn
trace width dimensions prior to lamination, conductor plating, and etching. After the motherboard
materials are laminated, conductors plated, and etched, somewhat different dimensions result. Dielectric
materials become thinner, under/over etching of conductors alters their trace width, and conductor
plating makes them thicker. It is important to note that for the purpose of extracting electrical models
from transmission line properties, the final dimensions of signals after lamination, plating, and etching
should be used.
The stack-up uses 1.2-mil (1 oz) copper on power planes to reduce I*R drops and 0.6-mil copper
thickness on signal layers L1, L3, L6, and L8. After plating, the external layers become 1.2 to 2 mils
thick.
To meet the nominal 55- characteristic impedance L1 and L8 micro-strip lines are drawn at 5-mil trace
width but end up with a 5.5-mil final trace width after etching. For the same reason, the 5-mil thick
prepreg between L1 and L2 starts at 5 mils but becomes 4.5 mils after lamination. This situation and
result also applies to L7 and L8.
To ensure impedance control of 55- , L1, and L8 micro-strip lines should reference solid ground planes
on L2 and L7, respectively.
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Figure 4. Recommended Board Stack-Up Dimensions
Internal signal traces on L3 and L6 are unbalanced strip-lines. To meet the nominal 55- characteristic
impedance for these traces, they reference solid ground plane on L2 and L7. Since the coupling to L4
and L5 is still significant, (especially true when thinner stack-ups use balanced strip- lines on internal
layers) these layers are converted to ground floods in the areas of the motherboard where the speed
critical interfaces like the FSB or DDR system memory are routed. In the remaining sections of the
motherboard layout the L4 and L5 layers are used for power delivery.
For 55- characteristic impedance L3 (L6) strip-lines have a 4-mil final trace width and are separated
by a core dielectric thickness of 4.8 mils after lamination from the L2 (L7) ground plane and 11.2-mil
thickness prepreg after lamination to separate it from L4 (L5). The starting thickness of these core and
prepreg dielectric layers before lamination is 5 mils and 12 mils, respectively.
L8 is also used for power delivery in many cases since it benefits from the thick copper plating of the
external layer plating as well as referencing the close (4.5-mil prepeg thickness) L7 ground plane. The
benefit of such a stack-up is low inductance power delivery.
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3.2.
Alternate Stack Ups
OEMs may choose to use different stack-ups (number of layers, thickness, trace width, etc.) from the
one example outlined in. Figure 4. However, the following key elements should be observed:
Final post lamination, post etching, and post plating dimensions should be used for electrical model
extractions.
Power plane layers should be 1-oz thick and signal layers should be ½ oz thick.
External l layers become 1 – 1.5 oz (1.2 – 2 mils) thick after plating
All high-speed signals should reference solid ground planes through the length of their routing and
should not cross plane splits. To guarantee this, both planes surrounding strip-lines should be GND.
Intel recommends that high-speed signal routing be done on internal, strip-line layers.
High-speed signals transitioning between layers next to the component, signal pins should be
accounted for by the GND stitching vias that would stitch all the GND plane layers in that area of
the motherboard. Due to the arrangement of processor and GMCH/MCH pin-maps, GND vias
placed near all GND lands will also be very close to high-speed signals that may be transitioning to
an internal layer. Thus, no additional ground stitching vias (besides the GND pin vias) are required
in the immediate vicinity of the processor and GMCH/MCH packages to accompany the signal
transitions from the component side into an internal layer.
High-speed routing on external layers should be minimized in order to avoid EMI. Routing on
external layers also introduces different delays compared to internal layers, making it extremely
difficult to do length matching if some routing is done on both internal and external layers.
Note: If Intel’s recommended stackup guidelines are not used, then the OEM is liable for all aspects of their
board design (for example, understanding impacts of SI and power distribution, etc.)
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4.
FSB Design Guidelines
The following layout guidelines support designs using the Mobile Intel Pentium 4 processor and the
Intel® 852GME/852GMV/852PMchipset.
Due to on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be
placed on the motherboard for most FSB signals. The exception to these are RESET#, BPM[5:0]#
signals which requires a 51.1 pull-up, and BR0 signal requires 220 + 5% pull-up to Vtt on the
processor end of the transmission line.
4.1.
FSB Routing Guidelines
Table 1 summarizes the FSB layout recommendations and provides detail on specific design issues.
Table 1. System Bus Routing Summary for the Processor
Parameter
Line to line spacing
Processor Routing Guidelines
Greater than or equal to 2:1 edge-to-edge spacing versus trace
width for address and address strobes. Greater than or equal to
2.5:1 edge-to-edge spacing versus trace width or greater for data
and data strobes.
See Figure 5 or an illustration of this recommendation.
Data Line lengths (agent to agent spacing)
1.0 inches– 6.0 inches from pin-to-pin. Data signals of the same
source synchronous group should be routed to the same pad-to-pad
length within ± 0.100 inches of the associated strobes. The pad is
defined as the attach point of the silicon die to the package
substrate. Length must be added to the system board to
compensate for package length differences. Signals in the same
source synchronous group should be routed on the same layer and
referenced to Vss.
DSTBn/p[3:0]#
A data strobe and its complement should be routed within ±0.025
inches of the same pad-to-pad length. The pad is defined as the
attach point of the silicon die to the package substrate. Length must
be added to the system board to compensate for package length
differences. DSTBn/p# should be routed on the same layer as their
associated data group and referenced to Vss.
Address line lengths (agent to agent spacing)
1.0 inches – 6.0 inches from pin-to-pin address signals of the same
source synchronous group should be routed to the same Pad-to-Pad
length within± 0.200 inches of the associated strobes. The pad is
defined as the attach point of the silicon die to the package
substrate. Length must be added to the system board to
compensate for package length differences. A layer transition may
occur if the reference plane remains the same (Vss) and the layers
are of the same configuration (all stripline or all microstrip).
ADSTBn/p[1:0]#
An address strobe should be routed to associated data signal within
± 0.200 “ of the same Pad-to-Pad length. The pad is defined as the
attach point of the silicon die to the package substrate. Length must
be added to the system board to compensate for package length
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Parameter
Processor Routing Guidelines
differences. A layer transition may occur if the reference plane
remains the same (Vss) and the layers are all of the same
configuration (all stripline or all microstrip).
Common Clock line lengths
2.0 inches – 6.0 inches
Topology
Stripline
Routing priorities
All associated signals and strobes should be routed on same layer
for entire length of bus. All signals should be referenced to Vss.
Ideally, layer changes should not occur for any signals. If a layer
change must occur, reference plane must be Vss and the layers
must all be of the same configuration (all stripline or all microstrip for
example).
Clock keepout zones
A spacing requirement of 16-20 mils should be maintained around
all clocks.
Trace Impedance
53 ohms ± 15%
Source Synchronous routing restrictions
There are no length-matching routing restrictions between (or within)
either the source-synchronous data or address groups. As long as
the strobe and associated line length routing guidelines are met for
each group, there is no need to length-match between the groups.
For example, one data group may be routed to the minimum
allowable length while another data group could be routed to the
maximum allowable length. Simulations have verified that the FSB
will still function correctly even under this extreme condition.
Refer to Intel®852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet for GMCH package
dimensions and refer to the Mobile Intel® Pentium® 4 Processor Datasheet or Mobile Intel® Pentium® 4
Processor supporting Hyper-Threading Technology on 90-nm process technology Datasheet for
processor package dimensions.
Figure 5. Cross-Sectional View of 2:1 Ratio
Reference Plane
trace
trace
2x
x
NOTE:
This is the edge-to-edge trace spacing versus width.
For address and address strobes; a trace spacing to width ratio of 2 to 1 ensures a low crosstalk
coefficient (based on geometries defined in 8 layer reference stackup). For data and data strobes; a trace
spacing to width ratio of 2.5 to 1 (or greater) ensures a low crosstalk coefficient (based on geometries
defined in 8 layer reference stackup). All the effects of crosstalk are difficult to simulate. A smaller ratio
would have an unpredictable impact due to crosstalk.
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Figure 6. Cross-Sectional View of 2.5:1 Ratio
Reference Plane
trace
trace
2.5x
x
4.1.1.
Return Path Evaluation
The return path is the route current takes to return to its source. It may take a path through ground
planes, power planes, other signals, integrated circuits, vias, VRMs, etc. Consider it as following a path
of least impedance back to the original source. Discontinuities in the return path often have signal
integrity and timing effects that are similar to the discontinuities in the signal conductor. Therefore, the
return paths need to be given similar considerations. A simple way to evaluate return path parasitic
inductance is to draw a loop that traces the current from the driver through the signal conductor to the
receiver, and then back through the ground/power plane to the driver again. The smaller the area of the
loop, the lower the parasitic inductance will be.
The following set of return path rules apply:
Always trace out the return current path and provide as much care to the return path as the path of
the signal conductor.
Decoupling capacitors do not adequately compensate for a plane split.
Do not allow splits in the reference planes in the path of the return current.
Do not allow routing of signals on the reference planes near system bus signals.
Maintain Vss as a reference plane for all system bus signals.
Do not route over via anti-pads or socket anti-pads.
4.2.
OPTIMIZED/COMPAT# Topology for Intel®
852GME/852GMV/852PM Only Platforms
The OPITIMIZED/COMPAT# pin tells the processor if the internal FSB signal impedance is set to 50
or 60 . By connecting the processor’s OPTIMIZED/COMPAT# pin AE26 pin to GND, the internal
FSB signal impedance is set to 50 . By leaving the pin as NC, the internal FSB signal impedance is set
to 60 . In order for the platform to be compatible with the Mobile Intel Pentium 4 processor, this pin
should be left as NC. If a platform is only used with the Mobile Intel Pentium 4 processor, then this pin
can be connected to GND.
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4.3.
General Topology and Layout Guidelines
The following topology and layout guidelines are subject to change. The guidelines are derived from
empirical testing with Intel® 852GME/852GMV/852PM chipset package models.
Below are the design recommendations for the data, address, strobes, common clock signals and others.
For the following discussion, the pad is defined as the attach point of the silicon die to the package
substrate.
4.3.1.
Data Signals
Data signals of the same source synchronous group should be routed to the same pad-to-pad length
within ± 0.100 inches of the associated strobes. As a result, additional trace will be added to some data
nets on the system board in order for all trace lengths within the same data group to be the same length
(± 0.100 inches) from the pad of the processor to the associated pad of the chipset.
Equation 1. Calculation to Determine Package Delta Addition to Motherboard Length for UP
Systems
delta net,strobe = (cpu_pkglen net − cpu_pkglen strobe* ) + (cs_pkglen net − cs_pkglen strobe )
Refer to the Intel® 852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet for GMCH
package dimensions and refer to the Mobile Intel® Pentium® 4 Processor Datasheet and the Mobile
Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process technology
Datasheet for package dimensions.
Note: Strobe package length is the average of the strobe pair.
4.3.2.
Address Signals
Address signals follow the same rules as data signals except address signals should be routed to the
same pad-to-pad length within ± 0.200 inches of the associated strobes. Address signals may change
layers if the reference plane remains Vss.
4.3.3.
Strobe Signals
A strobe and its complement should be routed to a length equal to their corresponding data group's mean
pad-to-pad length ± 0.025 inches.
4.3.4.
Common Clock Signals
Common clock signals should be routed to a minimum pin-to-pin motherboard length of 2.0 inches and
a maximum motherboard length of 6.0 inches.
Source synchronous groups and associated strobes should be routed on the same layer for the entire
length of the bus. This results in a significant reduction of the flight time skew since the dielectric
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thickness, line width, and velocity of the signals will be uniform across a single layer of the stackup.
There is no guarantee of a relationship of dielectric thickness, line width, and velocity between layers.
Figure 7. Processor Topology
Length L1
Processor
GMCH
Pad
Pad
Package trace
Motherboard PCB trace
4.3.5.
Source Synchronous (SS) Signals
Table 2. Processor System Bus Data Signal Routing Guidelines
Signal Names
Total Trace Length
Transmission
Line Type
CPU
GMCH
Min
(inches)
Max
(inches)
Nominal
Impedance
( )
Width & Spacing (mils)
DBI[3:0]#
DINV[3:0]#
Strip-line
1.0
6.0
53 ± 15%
4.5 & 11.5
D[63:0]#
HD[63:0]#
Strip-line
1.0
6.0
53 ±15%
4.5 & 11.5
DSTBN[3:0]#
HDSTBN[3:0]#
Strip-line
1.0
6.0
53 ± 15%
4.5 & 11.5
DSTBP[3:0]#
HDSTBP[3:0]#
Strip-line
1.0
6.0
53 ±15%
4.5 & 11.5
NOTE:
The Data signals within each group must be routed to within ± 0.100 inches of its associated “reference”
strobe. The complement strobe must be routed to within ± 0.025 inches of the associate “reference” strobe.
All traces within each signal group must be routed on the same layer (required). Intel recommends that
length of the strobes be centered to the average length of associated data or address traces to maximize
setup/hold time margins.
Table 3. Processor System Bus Address Signal Routing Guidelines
Signal Names
Total Trace Length
Transmission
Line Type
Width & Spacing (mils)
Min
(inches)
Max
(inches)
Strip-line
1.0
6.0
53 ± 15%
4.5 & 9
HREQ[4:0]#
Strip-line
1.0
6.0
53 ± 15%
4.5 & 9
HADSTB[1:0]#
Strip-line
1.0
6.0
53 ± 15%
4.5 & 9
CPU
GMCH
A[31:3]#
HA[31:3]#
REQ[4:0]#
ADSTB[1:0]#
NOTE:
Nominal
Impedance
( )
The Address signals within each group must be routed to within ± 0.200 of its associated strobe. All traces
within each signal group must be routed on the same layer (required). It is recommended that length of the
strobes be centered to the average length of associated data or address traces to maximize setup/hold time
®
®
®
®
margins. Please refer to Mobile Intel Pentium 4 Processor Datasheet orMobile Intel Pentium 4 Processor
supporting Hyper-Threading Technology on 90-nm process technology Datasheet for signals and
associated strobe.
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Figure 8. SS Topology for Address and Data
Processor
Vtt
Vtt
Pin
Chip Set
Pin
Pad
Pad
L1
4.3.6.
Common Clock (CC) AGTL+ Signals
Table 4. Processor System Bus Control Signal Routing Guidelines
Routing Trace Length
(Pin-to-Pin)
Signal Names
Topology
CPU
Max
(inches)
Min
(inches)
Width & spacing
(mils)
RESET#
CPURST#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
BR0#
BREQ0#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
BNR#
BNR#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
REQ[4:0]# HREQ[4:0]#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
BPRI#
BPRI#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
DEFER#
DEFER#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
LOCK#
HLOCK#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
TRDY#
HTRDY#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
DRDY#
DRDY#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
ADS#
ADS#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
DBSY#
DBSY#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
HIT#
HIT#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
HITM#
HITM#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
RS[2:0]#
RS[2:0]#
Stripline
6.0
2.0
53 ± 15%
4.5 & 11.5
NOTE:
46
GMCH
Nominal Impedance
(ohms)
Trace width of 4.5 mils and trace spacing of 11.5 mils within signal groups. Entire trace for each signal routed
on one layer (recommended) RESET# and BR0# are CC AGTL+ signals without ODT (On die termination).
For these signals Rtt should be placed near CPU: L2<= 0.5 inches. Rtt = 51.1 ±1%. Routing these signals to
4.0 inches ± 0.5 inches should maximize the setup and hold margin parameters while adhering to expected
mobile solution design constraints.
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4.3.7.
Asynchronous AGTL+ Signals
All signals must meet the AC and DC specifications as documented in the Mobile Intel® Pentium® 4
Processor Datasheet or the Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading
Technology on 90-nm process technology Datasheet.
Note: All AGTL+ signals within this document are same as GTL+.
4.3.7.1.
4.3.7.1.1.
Topologies
Topology 1A: Open Drain (OD) Signals Driven by the Processor – IERR# and
FERR#
The topology 1A OD signals IERR# and FERR# should adhere to the following routing and layout
recommendations. Table 5 lists the recommended routing requirements for the IERR# and FERR#
signals of the Mobile Intel Pentium 4 processor. The routing guidelines allow the signal to be routed as
either micro-strip or strip-lines using 53 ± 5% characteristic trace impedance. The pull-up voltage for
termination resistor Rtt is VCC_CORE.
Due to the dependencies on system design implementation, IERR# can be implemented in a number of
ways to meet design goals. IERR# can be routed as a test point or to any optional system receiver. Intel
recommends that the FERR# signal of the Mobile Intel Pentium 4 processor be routed to the FERR#
signal of the Intel ICH4-M.
Figure 9. Routing Illustration for Topology 1A
VCC_CORE
SYSTEM
RECEIVER
CPU
Rtt
L2
L1
L3
Table 5. Layout Recommendations for Topology 1A
L1
L2
L3
Rtt
Transmission Line Type
0.5” – 12.0”
0” – 3.0”
0” – 3.0”
56
± 5%
Micro-strip
0.5” – 12.0”
0” – 3.0”
0” – 3.0”
56
± 5%
Strip-line
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4.3.7.1.2.
Topology 1B: Open Drain (OD) Signals Driven by the Processor –THERMTRIP#
The Topology 1B OD signal THERMTRIP# should adhere to the following routing and layout
recommendations. Table 6 lists the recommended routing requirements for the THERMTRIP# signals of
the processor. The routing guidelines allow the signal to be routed as either micro-strip or strip-lines
using 53 ± 15% characteristic trace impedance. The pull-up voltage for termination resistor Rtt is
VCCP.
THERMTRIP# can be implemented in a number of ways to meet design goals. It can be routed to the
ICH4-M or any optional system receiver. Intel recommends that the THERMTRIP# signal of the
processor be routed to the THRMTRIP# signal of the ICH4-M. The ICH4-M’s THRMTRIP# signal is a
new signal to the I/O controller hub architecture that allows the ICH4-M to quickly put the whole
system into an S5 state whenever the catastrophic thermal trip point has been reached.
Figure 10. Routing Illustration for Topology 1B
VCC_CORE
ICH4-M
(or
SYSTEM
RECEIVER)
CPU
Rtt
L2
L1
L3
Table 6. Layout Recommendations for Topology 1B
48
L1
L2
L3
R1
Rtt
Transmission Line
Type
0.5” – 12.0”
0” – 3.0”
0” – 3.0”
56
± 5%
56
± 5%
Micro-strip
0.5” – 12.0”
0” – 3.0”
0” – 3.0”
56
± 5%
56
± 5%
Strip-line
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4.3.7.1.3.
Topology 1C: Open Drain (OD) Signals Driven by the Processor –PROCHOT#
The Topology 1C OD signal PROCHOT#, should adhere to the following routing and layout
recommendations. Table 7 lists the recommended routing requirements for the PROCHOT# signal. The
routing guidelines allow the signal to be routed as either a micro-strip or strip-line using 55 ± 15%
characteristic trace impedance. Figure 11 shows the recommended implementation for providing voltage
translation between the processor’s PROCHOT# signal and a system receiver that utilizes a 3.3-V
interface voltage (shown as VCCP).
Series resistor Rs is a component of the voltage translation logic and serves as a driver isolation resistor.
Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to emphasize
the placement of Rs with respect to Q1. The placement of Rs a distance L3 before the Q1 BJT is a
specific implementation of the generalized voltage translator circuit shown in Figure 11. Rs should be
placed at the beginning of the T-split from the PROCHOT# signal. The pull-up voltage for termination
resistor Rtt is VCCP.
Intel recommends that PROCHOT# be routed using the voltage translation logic shown in Figure 11.
Figure 11. Routing Illustration for Topology 1C
ICH4-M
or
System Receiver
3.3V
VCC_CORE
CPU
R1
Rtt
L1
R2
Q2
Q1
L2
L3
V_IO_RCVR
L4
3904
3904
Rs
Table 7. Layout Recommendations for Topology 1C
L1
L2
L3
L4
Rs
0.5 –
12.0”
03.0”
0–
3.0”
0.5 –
12.0”
5%
0.5 –
12.0”
03.0”
0–
3.0”
0.5 –
12.0”
5%
R1
R2
Rtt
Transmission
Line Type
±
1.3 k ±
5%
330 ±
5%
56 ±
5%
Micro-strip
±
1.3 k ±
5%
330 ±
5%
56 ±
5%
Strip-line
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4.3.7.1.4.
Topology 2A: Open Drain (OD) Signals Driven by ICH4-M – PWRGOOD
The Topology 2A OD signal PWRGOOD should adhere to the following routing and layout
recommendations.
Table 8 lists the recommended routing requirements for the PWRGOOD signal of the Mobile Intel
Pentium 4 processor. The routing guidelines allow the signal to be routed as either micro-strip or striplines using 53 ± 15% characteristic trace impedance. The pull-up voltage for termination resistor Rtt
is VCC_CORE.
Note: The Intel ICH4-M’s CPUPWRGD signal should be routed point-to-point to the Mobile Intel Pentium 4
processor’s PWRGOOD signal. The routing from the Mobile Intel Pentium 4 processor’s PWRGOOD
pin should fork out to both the termination resistor, Rtt, and the ICH4-M. Segments L1 and L2 from
Figure 17 should not T-split from a trace from the Mobile Intel Pentium 4 processor pin.
Figure 12. Routing Illustration for Topology 2A
VCC_CORE
CPU
ICH4-M
Rtt
L1
L2
Table 8. Layout Recommendations for Topology 2A
50
L1
L2
Rtt
Transmission Line Type
0.5” – 12.0”
0” – 3.0”
300
± 5%
Micro-strip
0.5” – 12.0”
0” – 3.0”
300
± 5%
Strip-line
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4.3.7.1.5.
Topology 2B: CMOS Signals Driven by ICH4-M – DPSLP#
The Topology 2B CMOS DPSLP# signal should adhere to the following routing and layout
recommendations illustrated in Figure 13. As listed in Table 9, the L1 and L2 segments of the DPSLP#
signal topology can be routed as either micro-strip or strip-lines using 53 ± 15% characteristic trace
impedance. Note that the Intel ICH4-M’s DPSLP# signal should be routed point-to-point with the daisy
chain topology shown. The routing of DPSLP# at the CPU should fork out to both the ICH4-M and the
GMCH. Segments L1 and L2 from Table 9 should not T-split from a trace from the Mobile Intel
Pentium 4 processor pin.
Figure 13. Routing Illustration for Topology 2B
GMCH
CPU
ICH4-M
L1
L2
Table 9. Layout Recommendations for Topology 2B
L1
L2
Transmission Line Type
0.5” – 12.0”
0.5” – 6.5”
Micro-strip
0.5” – 12.0”
0.5” – 6.5”
Strip-line
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4.3.7.1.6.
Topology 2C: CMOS Signals Driven by ICH4-M – A20M#, IGNNE#, LINT0/INTR,
LINT1/NMI, SLP#, SMI#, and STPCLK#
The Topology 2C CMOS A20M#, IGNNE#, LINT0/INTR, LINT1/NMI, SLP#, SMI#, and STPCLK#
signals should implement a point-to-point connection between the ICH4-M and the Mobile Intel
Pentium 4 processor. The routing guidelines allow both signals to be routed as either micro-strip or
strip-lines using 53 ± 15% characteristic trace impedance. No additional motherboard components are
necessary for this topology.
Figure 14. Routing Illustration for Topology 2C
CPU
ICH4-M
L1
Table 10. Layout Recommendations for Topology 2C
52
L1
Transmission Line Type
0.5” – 12.0”
Micro-strip
0.5” – 12.0”
Strip-line
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4.3.7.1.7.
Topology 3: CMOS Signals Driven by ICH4-M to CPU and FWH – INIT#
The signal INIT# should adhere to the following routing and layout recommendations. Table 11 lists the
recommended routing requirements for the INIT# signal of the ICH4-M. The routing guidelines allow
both signals to be routed as either micro-strip or strip-lines using 53 ± 15% characteristic trace
impedance.
Figure 15 shows the recommended implementation for providing voltage translation between the ICH4M’s INIT# voltage signaling level and any firmware hub (FWH) that utilizes a 3.3-V interface voltage
(shown as a supply V_IO_FWH). See Section 4.3.7.2 for more details on the voltage translator circuit.
For convenience, the entire topology and required transistors and resistors for the voltage translator is
shown in Figure 15.
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver isolation
resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor (BJT), Q1, to
emphasize the placement of Rs with respect to Q1. The placement of Rs a distance of L3 before the Q1
BJT is a specific implementation of the generalized voltage translator circuit shown in Figure 16. The
routing recommendations of transmission line L3 in Figure 15 is listed in Table 11 and Rs should be
placed at the beginning of the T-split of the trace from the ICH4-M’s INIT# pin.
Figure 15. Routing Illustration for Topology 3
3.3V
FWH
ICH4-M
CPU
R1
Q2
L2
Q1
L1
L3
V_IO_FWH
R2
L4
3904
3904
Rs
Table 11. Layout Recommendations for Topology 3
L1 + L2
L3
L4
Rs
R1
R2
0.5” – 12.0”
0” – 3.0”
0.5” – 6.0”
300
± 5%
1.3 k
± 5%
330
± 5%
Micro-strip
0.5” – 12.0”
0” – 3.0”
0.5” – 6.0”
300
± 5%
1.3 k
± 5%
330
± 5%
Strip-line
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
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4.3.7.2.
Voltage Translation Circuit
A voltage translation circuit or component is required on any signals where the voltage signaling level
between two components connected by a transmission line may cause unpredictable signal quality. The
recommended voltage translation circuit for the platform is shown in Figure 16. For the INIT# signal
(Section 4.3.7.1.7) a specialized version of this voltage translator circuit is used where the driver
isolation resistor, Rs, is place at the beginning of a transmission line that connects to the first bipolar
junction transistor, Q1. Though the circuit shown in Figure 16 was developed to work with signals that
require translation from VCC_CORE to a 3.3-V voltage level, the same topology and component values,
in general, can be adapted for use with other signals as well provided the interface voltage of the
receiver is also 3.3 V. Any component value changes or component placement requirements for other
signals must be simulated in order to guarantee good signal quality and acceptable performance from the
circuit.
In addition to providing voltage translation between driver and receiver devices, the recommended
circuit also provides filtering for noise and electrical glitches. A larger driver isolation resistor, Rs, can
be used on the collector of Q1, however, it will result in a slower response time to the output falling
edge. In the case of the INIT# signal, resistors with values as close as possible to those listed in Figure
16 should be used without exception.
With the low VCC_CORE signaling level of the processor system bus, the voltage translation circuit
provides ample isolation of any transients or signal reflections at the input of transistor Q1 from
reaching the output of transistor Q2. Based on simulation results, the voltage translation circuit can
effectively isolate transients as large as 200 mV and that last as long as 60 ns.
Figure 16. Voltage Translation Circuit for 3.3-V Receivers
3.3V
3.3V
1.3K ohm
+/- 5%
From Driver
330 ohm
+/- 5%
Rs
4.3.8.
R1
330 ohm
+/- 5%
R2
Q2
To Receiver
3904
Q1
3904
AGTL+ I/O Buffer Compensation
The Mobile Intel Pentium 4 processor has two pins, COMP[1:0], and the 852GME / 852PM chipset
GMCH has two pins, HXRCOMP and HYRCOMP, that require compensation resistors to adjust the
AGTL+ I/O buffer characteristics to specific board and operating environment characteristics. Also, the
GMCH requires two special reference voltage generation circuits to pins HXSWING and HYSWING
for the same purpose described above. Refer to the Mobile Intel® Pentium® 4 Processor Datasheet,
Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology on 90-nm process
technology Datasheet and Intel® 852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet
for details on resistive compensation.
54
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4.3.8.1.
Mobile Intel Pentium 4 Processor AGTL+ I/O Buffer Compensation
The COMP[1:0] signals adhere to the following routing recommendation. Table 12 illustrates the
recommendation topology.
Table 12. Layout Recommendation for COMP[1:0]
Trace width
Trace Spacing
L1
Rpd
15 mil
25 mils
0.5 inches Maximum
61.9
± 1%
Figure 17. Routing Recommendation for COMP[1:0]
PROCESSOR
L1
Rpd
4.3.9.
Processor RESET# Signal
The RESET# signal is a common clock signal driven by the GMCH CPURESET# pin. In a production
system where no ITP700FLEX debug port is implemented, a simple point-to-point connection between
the CPURESET# pin of the GMCH and the processor’s RESET# pin is recommended (see Figure
18).On-die termination of the AGTL+ buffers on both the processor and the GMCH provide proper
signal quality for this connection. Length L1 of this interconnect should be limited to minimum of 1 inch
and maximum of 6.5 inches.
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Figure 18. Processor RESET# Signal Routing Topology with NO ITP700FLEX Connector
CPU
GMCH
L1
For a system that implements an ITP700FLEX debug port, a more elaborate topology is required in
order to guarantee proper signal quality at both the processor signal pad and the ITP700FLEX input
receiver. In this case the topology illustrated in Figure 19 should be implemented. The CPURESET#
signal from the GMCH should fork out (do not route one trace from GMCH pin and then T-split)
towards the processor’s RESET# pin as well as towards the Rtt and Rs resistive termination network
placed next to the ITP700FLEX debug port connector. Rtt (54.9 + 1%) pulls-up to the VCCP voltage
and is placed at the end of the L2 line that is limited to a 12-inch maximum length. Rs (22.6 ± 1%)
should be placed right next to Rtt to minimize the routing between them in the vicinity of the
ITP700FLEX connector to limit the L3 length to less than 0.5 inches. ITP700FLEX operation requires
the matching of L2 + L3 - L1 length to the length of the BPM[4:0]# signals length within ± 50 ps.
Currently 1% tolerance resistors are recommended for Rs and Rtt. The use of 5% tolerant resistors for
these resistors, and whether it could provide adequate signal quality performance, is under investigation.
Figure 19. Processor RESET# Signal Routing Topology with ITP700FLEX Connector
VVC_CORE
Rtt
CPU
L4
GMCH
L1
RESET#
CPURESET#
ITPFLEX
Connector
L3
L2
RESET#
Rs
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Table 13. Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector
4.4.
L1
L1+L4
L2 + L3
L3
0.1” – 0.5”
1.0” – 6.0”
12.0” max
0.5” max
Rs
Rs = 150
Rtt
± 1%
Rtt = 51
± 1%
Host Vrefs
The AGTL+ VREF provides a reference voltage for all of the FSB signals on the CP. It is required that a
voltage divider yields 0.63 *VCC_AVG where VCC_AVG is the average voltage of VCC_CPU and
GMCH_VTT. The output is then routed to the CPU’s GTLREF.
4.5.
ITP Debug Port
Please refer to the ITP700 Debug Port Design Guide, which can be found on
http://developer.intel.com/design/Xeon/guides/249679.htm.
4.5.1.
Logic Analyzer Interface (LAI)
Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use in
debugging the Mobile Intel Pentium 4 processor system. Tektronix* and Agilent* should be contacted
to get specific information about their logic analyzer interfaces. The following information is general in
nature. Specific information must be obtained from the logic analyzer vendor.
Due to the complexity of the Mobile Intel Pentium 4 processor system, the LAI is critical in providing
the ability to probe and capture system bus signals. There are two sets of considerations to keep in mind
when designing Mobile Intel Pentium 4 processor that can make use of an LAI: mechanical and
electrical.
4.5.1.1.
Mechanical Considerations
The LAI is installed between the processor socket and the Mobile Intel Pentium 4 processor. The LAI
pins plug into the socket, while the Mobile Intel Pentium 4 processor plugs into a socket on the LAI.
Cabling that is part of the LAI egresses the system to allow an electrical connection between the Mobile
Intel Pentium 4 processor and a logic analyzer. The maximum volume occupied by the LAI, known as
the keepout volume, as well as the cable egress restrictions, should be obtained from the logic analyzer
vendor. System designers must make sure that the keepout volume remains unobstructed inside the
system. Note that it is possible that the keepout volume reserved for the LAI may include space
normally occupied by the Mobile Intel Pentium 4 processor heat sink. If this is the case, the logic
analyzer vendor will provide a cooling solution as part of the LAI.
4.5.1.2.
Electrical Considerations
The LAI will also affect the electrical performance of the system bus; therefore, it is critical to obtain
electrical load models from each of the logic analyzers to be able to run system level simulations to
prove that their tool will work in the system. Contact the logic analyzer vendor for electrical
specifications and load models for the LAI solution they provide.
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4.6.
Mobile Intel Pentium 4 Processor and
852GME/852GMV/852PMChipset FSB Signal Package
Lengths
Table 14 lists the package trace lengths of the Mobile Intel Pentium 4 processor and the
852GME/852GMV/852PMGMCH for the source synchronous data and address signals. All the signals
within the same group are routed to the same length as listed below with ± 0.1-mil accuracy. As a result
of this package trace length matching, no motherboard trace length compensation is needed for these
signals. Refer to Section 4.1 for further details. The Mobile Intel Pentium 4 processor and 852GME
GMCH package traces are routed as micro-strip lines with a nominal characteristic impedance of 53 ±
15%.
Table 14. Mobile Intel Pentium 4 Processor and 852GME Chipset Package Lengths
Processor lengths
Signal
Processor
Ball
GMCH Lengths
Length
(inches)
Signal
GMCH ball
Length
(mils)
Address Group 0
ADSTB[0]#
L5
0.210
HADSTB[0]#
T26
419
A[3]#
K2
0.368
HA[3]#
P23
468
A[4]#
K4
0.265
HA[4]#
T25
353
A[5]#
L6
0.155
HA[5]#
T28
551
A[6]#
K1
0.415
HA[6]#
R27
523
A[7]#
L3
0.304
HA[7]#
U23
274
A[8]#
M6
0.144
HA[8]#
U24
333
A[9]#
L2
0.372
HA[9]#
R24
327
A[10]#
M3
0.327
HA[10]#
U28
560
A[11]#
M4
0.246
HA[11]#
V28
566
A[12]#
N1
0.394
HA[12]#
U27
522
A[13]#
M1
0.408
HA[13]#
T27
501
A[14]#
N2
0.349
HA[14]#
V27
562
A[15]#
N4
0.241
HA[15]#
U25
375
A[16]#
N5
0.198
HA[16]#
V26
491
REQ[0]#
J1
0.427
HREQ[0]#
R28
569
REQ[1]#
K5
0.207
HREQ[1]#
P25
378
REQ[2]#
J4
0.270
HREQ[2]#
R23
247
REQ[3]#
J3
0.337
HREQ[3]#
R25
383
REQ[4]#
H3
0.356
HREQ[4]#
T23
276
AA26
504
Address Group 1
ADSTB[1]#
58
R5
0.214
HADSTB[1]#
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Processor lengths
GMCH Lengths
A[17]#
T1
0.470
HA[17]#
Y24
457
A[18]#
R2
0.404
HA[18]#
V25
389
A[19]#
P3
0.303
HA[19]#
V23
284
A[20]#
P4
0.246
HA[20]#
W25
414
A[21]#
R3
0.334
HA[21]#
Y25
429
A[22]#
T2
0.388
HA[22]#
AA27
545
A[23]#
U1
0.458
HA[23]#
W24
382
A[24]#
P6
0.156
HA[24]#
W23
353
A[25]#
U3
0.379
HA[25]#
W27
536
A[26]#
T4
0.281
HA[26]#
Y27
556
A[27]#
V2
0.417
HA[27]#
AA28
631
A[28]#
R6
0.166
HA[28]#
W28
579
A[29]#
W1
0.493
HA[29]#
AB27
558
A[30]#
T5
0.217
HA[30]#
Y26
484
A[31]#
U4
0.285
HA[31]#
AB28
617
Data Group 0
DSTBN[0]#
E22
0.338
HDSTBN[0]#
J28
763
DSTBP[0]#
F21
0.326
HDSTBP[0]#
K27
662
D[0]#
B21
0.414
HD[0]#
K22
329
D[1]#
B22
0.475
HD[1]#
H27
620
D[2]#
A23
0.538
HD[2]#
K25
438
D[3]#
A25
0.608
HD[3]#
L24
387
D[4]#
C21
0.386
HD[4]#
J27
600
D[5]#
D22
0.386
HD[5]#
G28
693
D[6]#
B24
0.535
HD[6]#
L27
518
D[7]#
C23
0.464
HD[7]#
L23
329
D[8]#
C24
0.515
HD[8]#
L25
458
D[9]#
B25
0.590
HD[9]#
J24
438
D[10]#
G22
0.274
HD[10]#
H25
504
D[11]#
H21
0.203
HD[11]#
K23
319
D[12]#
C26
0.589
HD[12]#
G27
620
D[13]#
D23
0.462
HD[13]#
K26
494
D[14]#
J21
0.183
HD[14]#
J23
393
D[15]#
D25
0.550
HD[15]#
H26
554
DBI[0]#
E21
0.309
DINV[0]#
J25
514
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Processor lengths
GMCH Lengths
Data Group 1
DSTBN[1]#
K22
0.301
HDSTBN[1]#
C27
788
DSTBP[1]#
J23
0.306
HDSTBP[1]#
D26
736
D[16]#
H22
0.272
HD[16]#
F25
593
D[17]#
E24
0.480
HD[17]#
F26
634
D[18]#
G23
0.358
HD[18]#
B27
834
D[19]#
F23
0.418
HD[19]#
H23
412
D[20]#
F24
0.443
HD[20]#
E27
714
D[21]#
E25
0.508
HD[21]#
G25
522
D[22]#
F26
0.513
HD[22]#
F28
731
D[23]#
D26
0.597
HD[23]#
D27
766
D[24]#
L21
0.176
HD[24]#
G24
493
D[25]#
G26
0.524
HD[25]#
C28
837
D[26]#
H24
0.412
HD[26]#
B26
815
D[27]#
M21
0.171
HD[27]#
G22
453
D[28]#
L22
0.245
HD[28]#
C26
768
D[29]#
J24
0.401
HD[29]#
E26
691
D[30]#
K23
0.313
HD[30]#
G23
464
D[31]#
H25
0.473
HD[31]#
B28
914
DBI[1]#
G25
0.458
DINV[1]#
E25
628
Data Group 2
60
DSTBN[2]#
K22
0.252
HDSTBN[2]#
E22
538
DSTBP[2]#
J23
0.266
HDSTBP[2]#
E21
502
D[32]#
M23
0.300
HD[32]#
B21
664
D[33]#
N22
0.226
HD[33]#
G21
501
D[34]#
P21
0.178
HD[34]#
C24
683
D[35]#
M24
0.371
HD[35]#
C23
675
D[36]#
N23
0.271
HD[36]#
D22
633
D[37]#
M26
0.454
HD[37]#
C25
747
D[38]#
N26
0.437
HD[38]#
E24
619
D[39]#
N25
0.383
HD[39]#
D24
655
D[40]#
R21
0.165
HD[40]#
G20
358
D[41]#
P24
0.343
HD[41]#
E23
608
D[42]#
R25
0.381
HD[42]#
B22
828
D[43]#
R24
0.329
HD[43]#
B23
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Processor lengths
GMCH Lengths
D[44]#
T26
0.420
HD[44]#
F23
563
D[45]#
T25
0.380
HD[45]#
F21
460
D[46]#
T22
0.221
HD[46]#
C20
647
D[47]#
T23
0.279
HD[47]#
C21
654
DBI[2]#
P26
0.441
DINV[2]#
B25
784
Data Group 3
DSTBN[3]#
W22
0.298
HDSTBN[3]#
D18
505
DSTBP[3]#
W23
0.300
HDSTBP[3]#
E18
463
D[48]#
U26
0.419
HD[48]#
G18
372
D[49]#
U24
0.324
HD[49]#
E19
511
D[50]#
U23
0.270
HD[50]#
E20
548
D[51]#
V25
0.384
HD[51]#
G17
326
D[52]#
U21
0.167
HD[52]#
D20
575
D[53]#
V22
0.252
HD[53]#
F19
469
D[54]#
V24
0.341
HD[54]#
C19
598
D[55]#
W26
0.447
HD[55]#
C17
541
D[56]#
Y26
0.454
HD[56]#
F17
372
D[57]#
W25
0.426
HD[57]#
B19
649
D[58]#
Y23
0.336
HD[58]#
G16
347
D[59]#
Y24
0.386
HD[59]#
E16
490
D[60]#
Y21
0.222
HD[60]#
C16
522
D[61]#
AA25
0.426
HD[61]#
E17
431
D[62]#
AA22
0.268
HD[62]#
D16
509
D[63]#
AA24
0.394
HD[63]#
C18
579
DBI[3]#
V21
0.202
DINV[3]#
G19
431
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5.
Platform Power Requirements
Please contact your Intel field representative for more information on the electrical requirements for the
DC-to-DC voltage regulator for the Mobile Intel Pentium 4 processor and Intel Celeron processor.
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6.
System Memory Design Guidelines
(DDR-SDRAM)
The Intel 852GME/852GMV/852PMGMCH/MCH Double Data Rate (DDR) SDRAM system memory
interface consists of SSTL-2 compatible signals. These SSTL-2 compatible signals have been divided
into several signal groups: Data, Control, Command, CPC, Clock, and Feedback signals. Table 15
summarizes the different signal groupings. Refer to the Intel® 852GME Chipset GMCH and Intel®
852PM Chipset MCH Datasheet for details on the signals listed.
Table 15. GMCH/MCH Chipset Memory Signal Groups
Group
Clocks
Data
Control
Command
CPC
Feedback
Signal Name
Description
SCK[5:0]
DDR-SDRAM Differential Clocks - (3 per SO-DIMM)
SCK#[5:0]
DDR-SDRAM Inverted Differential Clocks - (3 per SO-DIMM)
SDQ[63:0]
Data Bus
SDQ[71:64]
Check Bits for ECC Function
SDQS[8:0]
Data Strobes
SDM[8:0]
Data Mask
SCKE[3:0]
Clock Enable - (One per Device Row)
SCS#[3:0]
Chip Select - (One per Device Row)
SMA[12:6,3,0]
Memory Address Bus
SBA[1:0]
Bank Select
SRAS#
Row Address Select
SCAS#
Column Address Select
SWE#
Write Enable
SMA[5,4,2,1]
Command per Clock (SO-DIMM0)
SMAB[5,4,2,1]
Command per Clock (SO-DIMM1)
RCVENOUT#
Receive Enable Output (no external connection)
RCVENIN#
Receive Enable Input (no external connection)
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6.1.
Length Matching and Length Formulas
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group, all of which are recommended to achieve optimal SI and timing. In addition to the
absolute length limits provided in the individual guideline tables, more restrictive length matching
formulas are also provided that further restrict the minimum to maximum length range of each signal
group with respect to clock, within the overall boundaries defined in the guideline tables, as required to
guarantee adequate timing margins. These secondary constraints are referred to as length matching
constraints and the formulas used are referred to as length matching formulas.
All signal groups except the clocks and feedback signals are length matched per slot to the DDR clocks,
with the clocks themselves being length tuned to a fixed length across each SO-DIMM slot. The
amount of minimum to maximum length variance allowed for each group around the clock reference
length varies from signal group to signal group depending on the amount of timing variance which can
be tolerated. A simple summary of the length matching formulas for each signal group is provided in
the tables below.
Table 16. Intel 852GME/852GMV/852PMChipset GMCH/MCH DDR 333 Length Matching Formulas
Signal Group
Minimum Length
Maximum Length
Control to Clock
Clock –2.0”
Clock - 0.5”
Command to Clock
Clock – 2.0”
Clock + 2.0”
CPC to Clock
Clock – 2.0”
Clock - 1.0”
Strobe to Clock
Clock – 2.0”
Clock + 0.5”
Data to Strobe
Strobe – 25 mils
Strobe + 25 mils
NOTES:
1. All length matching formulas are based on GMCH/MCH die-pad to SO-DIMM connector pin total length.
2. Backward compatible and supports DDR200 and DDR266
3. Package length tables are provided for all signals in order to facilitate this pad to pin matching. Note that the
clock length used for length matching may vary by SO-DIMM slot, based on SO-DIMM spacing. Length
formulas should be applied to each SO-DIMM slot independently. An offset of up to 1.0 inch between clock
groups is allowed under the guidelines. The full geometry and routing guidelines along with the exact length
matching formulas and associated diagrams are provided in the individual signal group guidelines sections to
follow.
6.2.
Package Length Compensation
As mentioned in Section 6.1, all length matching is done GMCH/MCH die-pad to SO-DIMM pin. The
reason for this is to compensate for the package length variation across each signal group. The
GMCH/MCH does not equalize package lengths internally as some previous GMCH/MCH components
have, and therefore, the GMCH/MCH requires length matching.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the min and max length bounds of a signal group
based on clock length, whereas package length compensation refers to the process of compensating for
package length variance across a signal group. There is of course some overlap in that both affect the
target length of an individual signal. It is recommended that the initial route be completed based on the
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length matching formulas in conjunction with nominal package lengths and that package length
compensation be performed as secondary operation.
6.3.
Topologies and Routing Guidelines
The GMCH/MCH DDR SDRAM system memory interface implements the low swing, high-speed,
terminated SSTL_2 topology. This section contains information on the recommended interconnect
topologies and routing guidelines for each of the signal groups that comprise the DDR interface. When
implemented as defined, these guidelines provide a robust DDR solution on a GMCH/MCH chipset
based design.
6.3.1.
Clock Signals – SCK[5:0], SCK#[5:0]
The clock signal group includes the differential clock pairs SCK/SCK#[5:0]. The GMCH/MCH
generates and drives these differential clock signals required by the DDR interface; therefore, no
external clock driver is required for the DDR interface. The GMCH/MCH only supports unbuffered
DDR SO-DIMMs; three differential clock pairs are routed to each SO-DIMM connector. Table 17
summarizes the clock signal mapping.
Table 17. Clock Signal Mapping
6.3.1.1.
Signal
Relative To
SCK/SCK#[2:0]
SO-DIMM0
SCK/SCK#[5:3]
SO-DIMM1
Clock Topology Diagram
The GMCH/MCH provides six differential clock output pairs, or three clock pairs per SO-DIMM
socket. The motherboard clock routing topology is shown below for reference. Refer to the routing
guidelines in Figure 20 for detailed length and spacing rules for each segment. The clock signals should
be routed as closely coupled differential pairs over the entire length. Spacing to other DDR signals
should not be less than 20 mils. Isolation spacing to non-DDR signals should be 25 mils.
Figure 20. Memory Clock Routing Topology SCK/SCK#[5:0]
GM CH
S O -D IM M P A D S
P1
L1
L2
GM CH
P in
R1
P1
L1
L2
D iffe r e n tia l P a irs
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6.3.1.2.
Memory Clock Routing Guidelines
Table 18. Clock Signal Group Routing Guidelines
Parameter
Definition
Signal Group
SCK[5:0] and SCK#[5:0]
Topology
Differential Pair Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
(see note on trace width below)
42
+/-15% (for reference only)
Differential Mode Impedance (Zdiff)
(see note on trace width below)
70
+/- 15% (for reference only)
Nominal Trace Width
(see note on trace width and exceptions for
breakout region below)
Inner Layers: 7 mils
Outer Layers: 8 mils (pin escapes only)
Nominal Pair Spacing (edge to edge)
(see exceptions for breakout region below)
Inner Layers: 4 mils
Outer Layers: 5 mils (pin escapes only)
Minimum Pair to Pair Spacing
exceptions for breakout region below)
(see
20 mils
Minimum Serpentine Spacing
20 mils
Minimum Spacing to Other DDR Signals
(see exceptions for breakout region below)
20 mils
Minimum Isolation Spacing to non-DDR Signals
25 mils
Maximum Via Count
2 (per side)
Package Length Range – P1
1000 mils +/- 350 mils (Refer to Table 19 for exact lengths.)
Trace Length Limits – L1
Max = 300 mils (breakout segment)
Total MB Length Limits – L1 + L2
Min = 0.5”
Max = 5.0”
Total Length – P1 + L1 + L2
Total length target is determined by placement (see Figure 20)
Total length for SO-DIMM0 group = X0 (see Figure 21)
Total length for SO-DIMM1 group = X1 (see Figure 21)
SCK to SCK# Length Matching
Match total length to +/- 10 mils (see Section 6.3.1.3)
Clock to Clock Length Matching (Total Length)
Match all SO-DIMM0 clocks to X0 +/- 25 mils (see Figure 21)
Match all SO-DIMM1 clocks to X1 +/- 25 mils (see Figure 21)
Breakout Exceptions
(Reduced geometries for GMCH/MCH breakout
region)
Inner Layers: 4 mil trace, 4 mil pair space allowed
Outer Layers: 5 mil trace, 5 mil pair space allowed
Pair to pair spacing of 5 mils allowed
Spacing to other DDR signals of 5 mils allowed
Maximum breakout length is 0.3”
NOTES:
1. Pad to pin length tuning is utilized on clocks in order to achieve minimal variance. Package lengths range
between approximately 600 mils and 1400 mils. Exact package lengths for each clock signal are provided at
the end of this section. Overall target length should be established based on placement and routing flow. The
resulting motherboard segment lengths must fall within the ranges specified.
2. The DDR clocks should be routed on internal layers, except for pin escapes. It is recommended that pin escape
vias be located directly adjacent to the ball pads on all clocks. Surface layer routing should be minimized.
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3. Clock differential impedance is controlled indirectly through the single ended impedance specification for the
board. Clock signal integrity and edge rates are improved when clock trace widths are widened from the
standard 55 Ω single ended trace width. As the table indicates, a trace width of approximately 3 mils wider than
standard width was found to be optimal (i.e. inner layers: 4 mils std + 3 mils = 7 mils). The nominal single
ended impedance of the widened clock traces is in the range of 42 Ω, and the nominal differential impedance is
in the range of 70 Ω. However, impedance control is implemented through geometry control; these values are
for reference only.
4. Exceptions to the trace width and spacing geometries are allowed in the breakout region in order to fan-out the
interconnect pattern. Reduced spacing should be avoided as much as possible.
6.3.1.3.
Clock Length Matching Requirements
The GMCH/MCH chipset provides three differential clock pair for each SO-DIMM. A differential clock
pair is made up of a SCK signal and its complement signal SCK#. Refer to Section 6.1 for more details
on length matching requirements.
The differential pairs for one SO-DIMM are:
SCK[0] / SCK#[0]
SCK[1] / SCK#[1]
SCK[2] / SCK#[2]
The differential pairs for the second SO-DIMM are:
SCK[3] / SCK#[3]
SCK[4] / SCK#[4]
SCK[5] / SCK#[5]
The two sets of differential clocks must be length tuned on the motherboard such that any pair to pair
package length variation is tuned out. The three pairs associated with SO-DIMM0 are tuned to a fixed
overall length, including package, and the three pairs associated with SO-DIMM1 are tuned to a fixed
overall length.
The two traces associated with each clock pair are length matched within the package; however some
additional compensation may be required on the motherboard in order to achieve the ± 10 mil length
tolerance within the pair.
Between clock pairs the package length varies substantially. Therefore, the motherboard length of each
clock pair must be length adjusted to tune out package variance. The total length including package
should be matched to within ± 25 mils of each other, as shown in Figure 21. This may result in a clock
length variance of as much as 700 mils on the motherboard.
The first step in determining the routing lengths for clocks and all other clock relative signal groups is to
establish the target length for each SO-DIMM clock group. These target lengths are shown as X0 and
X1, in Figure 21. These are the lengths to which all clocks within the corresponding group will be
matched and the reference length values used to calculate the length ranges for the other signal groups.
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6.3.1.4.
Clock Reference Lengths
The clock reference length for each SO-DIMM clock group is determined by first determining the
longest total clock length required to complete the clock routing. A table of clock package lengths is
provided in Table 19 to assist in this calculation. Once the longest total length is determined for each
clock group, this becomes a lower bound for the associated clock reference length. At this point it is
helpful to have completed a test route of the SDQ/SDQS bus such that final clock reference lengths can
be defined with consideration of the impact on SDQ/SDQS bus routability. Some iteration may be
required.
Once the reference lengths X0 and X1 are defined then the next step is to tune each clock pairs’
motherboard trace segment lengths as required such that the overall length of each clock equals the
associated clock reference length plus or minus the 25 mil tolerance. Again, the reference length for the
two sets of clocks should be offset by the nominal routing length between SO-DIMM connectors.
Figure 21. Memory Clock Trace Length Matching Diagram
S O -D IM M 0
C lo c k R e fe re n c e L e n g th X 0
G M C H P ackage
SCK0
S CK #0
S C K 0 L e n g th = X 0
S C K # 0 L e n g th = X 0
S C K 1 L e n g th = X 0
S C K # 1 L e n g th = X 0
S C K 2 L e n g th = X 0
S C K # 2 L e n g th = X 0
SCK1
GM CH
D ie
S CK #1
SCK2
S CK #2
L e n g th = X 0 + /-2 5 m ils
N o te : A ll le n g th s a re m e a s u re d fro m G M C H d ie -p a d to
S O -D IM M 0 c o n n e c to r p a d s .
S O -D IM M 0
S O -D IM M 1
C lo c k R e fe re n c e L e n g th X 1
G M C H P ackage
SCK3
SCK 3#
SCK4
GM CH
D ie
SCK 4#
SCK5
SCK #5
S C K 3 L e n g th = X 1
S C K # 3 L e n g th = X 1
S C K 4 L e n g th = X 1
S C K # 4 L e n g th = X 1
S C K 5 L e n g th = X 1
S C K # 5 L e n g th = X 1
L e n g th = X 1 + /-2 5 m ils
N o te : A ll le n g th s a re m e a s u re d fro m G M C H d ie -p a d to
S O -D IM M 1 c o n n e c to r p a d s .
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6.3.1.5.
Clock Package Length Table
The package length data in the table below should be used to tune the motherboard length of each
SCK/SCK# clock pair between the GMCH/MCH and the associated SO-DIMM socket. It is
recommended that die-pad to SO-DIMM pin length be tuned to within ± 25 mils in order to optimize
timing margins on the interface.
Table 19. Memory Clock Package Lengths
Signal
Pin Number
Package Length
(mils)
SCK_0
AB2
1177
SCK#_0
AA2
1169
SCK_1
AC26
840
SCK#_1
AB25
838
SCK_2
AC3
1129
SCK#_2
AD4
1107
SCK_3
AC2
1299
SCK#_3
AD2
1305
SCK_4
AB23
643
SCK#_4
AB24
656
SCK_5
AA3
1128
SCK#_5
AB4
1146
Package length compensation can be performed on each individual clock output thereby matching total
length on SCK/SCK# exactly, or alternatively the average package length can be used for both outputs
of a pair and length tuning done with respect to the motherboard portion only.
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6.3.1.6.
Clock Routing Example
Figure 22 is an example of a board routing for the clock signal group.
Figure 22. Clock Signal Routing Example
GMCH
Clocks
SODIMM0
SODIMM1
6.3.2.
Data Signals – SDQ[71:0], SDM[8:0], SDQS[8:0]
The GMCH/MCH data signals are source synchronous signals that include a 72-bit wide data bus, which
includes 8 check bits for Error Checking and Correction (ECC), a set of 9 Data Mask bits, and a set of 9
data strobe signals. There is an associated data strobe and data mask bit for each of the 8-bit, data byte
groups, making for a total of nine, 10-bit byte lanes. This section summarizes the SDQ/SDM to SDQS
routing guidelines and length matching recommendations.
The data signals include SDQ[71:0], SDM[8:0], and SDQS[8:0]. The data signals should transition from
an external layer to an internal signal layer under the GMCH/MCH. Keep to the same internal layer until
transitioning back to an external layer at the series resistor. After the series resistor, the signal should
transition from the external layer to the same internal layer and route to SO-DIMM0. At SO-DIMM0,
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the signal should transition to an external layer and connect to the appropriate pad of the connector.
After the SO-DIMM0 transition, continue to route the signal on the same internal layer to SO-DIMM1.
Transition back out to an external layer and connect to the appropriate pad of SO-DIMM1. Connection
to the termination resistor should be via the same internal layer with a transition back to the external
layer near the resistor. External trace lengths should be minimized.
To facilitate routing, swapping of the byte lanes is allowed for SDQ[63:0] only. Bit swapping within the
byte lane is also allowed for SDQ[63:0] only. The check bits, SDQ[71:64], cannot be byte lane swapped
with another SDQ byte lane. Also, bit swapping within the SDQ[71:64] byte lane is not allowed. It is
suggested that the parallel termination be placed on both sides of SO-DIMM1 to simplify routing and
minimize trace lengths. All internal and external signals should be ground referenced to keep the path of
the return current continuous.
Resistor packs are acceptable for the series (Rs) and parallel (Rt) data and strobe termination resistors,
but data and strobe signals can’t be placed within the same R pack as the command or control signals.
The table and diagrams below depict the recommended topology and layout routing guidelines for the
DDR-SDRAM data signals.
Intel recommends that the full data bus SDQ[71:0], mask bus SDM[8:0], and strobe signals SDQS[8:0]
be routed on the same internal signal layer. It is required that the SDQ byte group and the associated
SDM and SDQS signals within a byte lane be routed on the same internal layer.
The total length of SDQ, SDM, and SDQS traces between the GMCH/MCH and the SO-DIMMs must
be within the range defined in the overall guidelines, and is also constrained by a length range boundary
based on SCK/SCK# clock length, and a SDQ/SDM to SDQS length matching requirement within each
byte lane. Note also that all length matching must be done inclusive of package length. A table of SDQ,
SDM, and SDQS package lengths is provided at the end of this Section to facilitate this process.
There are two levels of matching implemented on the data bus signals.
The first is the length range constraint on the SDQS signals based on clock reference length.
The second is SDQ/SDM to SDQS length matching within a byte lane.
The length of the SDQS signal for each byte lane must fall within a range determined by the clock
reference length, as defined in the SDQS to SCK/SCK length matching section. The actual length of
SDQS for each byte lane may fall anywhere within this range based on placement and routing flow.
Once the SDQS length for a byte lane is established, the SDQ and SDM signals within the byte lane
must be length matched to each other, inclusive of package length, as described in the SDQ to SDQS
length matching Section 6.3.2.3.
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6.3.2.1.
Data Bus Topology
Figure 23. Data Signal Routing Topology
Vtt
GMCH
GM CH
Die
Rs
L1
P1
Rt
L2
L4
L3
S0
SO-DIMM0 PAD
S1
SO-DIMM1 PAD
The data signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to non-DDR
related signals. Data signals should be routed on inner layers with minimized external trace lengths.
Table 20. Intel 852GME Chipset GMCH/MCH Memory Data Signal Group Routing Guidelines
Parameter
Signal Group
SDQ[71:0], SDQS[8:0], SDM[8:0]
Motherboard Topology
Daisy Chain with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
Minimum Spacing to Trace Width Ratio
74
Definition
+/- 15%
Inner layers: 4 mils
Outer layers: 5 mils
SDQ/SDM: 2 to 1 (e.g. 8 mil space to 4 mil trace)
SDQS: 3 to 1 (e.g. 12 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
700 mils +/- 300 mils (See Table 22 for details)
Trace Length L1 – GMCH/MCH Signal Ball to Series
Termination Resistor Pad
Min = 0.5”
Max = 3.75”
Trace Length L2 – Series Termination Resistor Pad to
First SO-DIMM Via
Max = 0.75”
Stub Length S0, S1 – Stub from Via to SO-DIMM Pad
Max = 0.25”
Total Length L1 + L2 + S0 – Total Length from
GMCH/MCH to First SO-DIMM Pad
Min = 0.5”
Total Length L1 + L2 + L3 + S1 – Total Length from
GMCH/MCH to Second SO-DIMM Pad
Min = 0.75”
Total Length S0 + L3 + S1– Total SO-DIMM pad to SODIMM pad spacing
Min = 0.25”
Max = 4.0”
Max = 4.5”
Max = 1.0”
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Parameter
Definition
Trace Length L4 – Last SO-DIMM Via to Parallel
Termination Resistor Pad
Max = 1.0”
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Length Matching Requirements
SDQS to SCK/SCK# See length matching Section 6.3.2.2
SDQ/SDM to SDQS, to +/- 25mils, within each byte lane
NOTES:
1. Power distribution vias from Rt to Vtt are not included in this count.
2. The overall minimum and maximum length to the SO-DIMM must comply with clock length matching
requirements.
3. It is possible to route using 4 vias if trace segments L2 and L4 are routed on the same external layer as the
associated SO-DIMM, for example if L2 is on the same layer as SO-DIMM0.
6.3.2.2.
SDQS to Clock Length Matching Requirements
The first step in length matching is to determine the SDQS length range based on the SCK/SCK#
reference length defined previously. The total length of the SDQS strobe signals, including package
length, between the GMCH/MCH die-pad and the SO-DIMMs must fall within the range defined in the
formulas below. See the clock Section for the definition of the clock reference length. Refer to Figure
23 for the definition of the various trace segments. The length tuning requirements are also depicted in
Figure 24. Refer to Section 6.1 for more details on length matching and length formula requirements.
Length range formula for SO-DIMM0:
X0 = SCK/SCK#[2:0] total reference length, including package length
Y0 = SDQS[8:0] total length = GMCH/MCH package + L1 + L2 + S0, as shown in Figure 24,
where: ( X0 – 2.0” )
Y0
( X0 + 0.5” ) for DDR 200/266/333
Length range formula for SO-DIMM1,
X1 = SCK/SCK#[5:3] total reference length, including package length
Y1 = SDQS[8:0] total length = GMCH/MCH package + L1 + L2 + L3 + S1, as shown Figure 24,
where:
( X0 – 2.0” )
Y0
( X0 + 0.5” ) for DDR 200/266/333
Length matching is only performed from the GMCH/MCH to the SO-DIMMs, and does not involve the
length of L4, which can vary over its entire range. Intel recommends that routing segment length L3
between SO-DIMM0 to SO-DIMM1 be held fairly constant and equal to the offset between clock
reference lengths X0 and X1. This will produce the most straightforward length-matching scenario.
Note that a nominal SDQS package length of 750 mils can be used to estimate MB lengths prior to
performing package length compensation. Refer to Section 6.2 for more details on package length
compensation.
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Figure 24. SDQS to Clock Trace Length Matching Diagram
S O -D IM M 0
G MCH Package
S D Q S [8:0 ]
S D Q S L e n g th = Y 0 , w h e re
GM CH
D ie
S C K [2:0 ]
S C K # [2 :0]
C lo c k R e fe re n c e L en g th = X 0
N o te : A ll le n g ths a re m e asu re d fro m G M C H d ie p a d to S O -D IM M c o n n e cto r p a d .
S O -D IM M 0
G M C H P a c ka g e
GM CH
D ie
S D Q S [8:0 ]
S O -D IM M 1
S D Q S L e n g th = Y 1
S C K [5:3 ]
S C K #[5 :3]
C lo c k R e f. L e n g th = X1
N o te : A ll le n g ths a re m e asu re d fro m G M C H d ie p a d to S O -D IM M c o n n e cto r p a d .
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6.3.2.3.
Data to Strobe Length Matching Requirements
The data bit signals, SDQ[71:0] are grouped by byte lanes and associated with a data mask signal
SDM[8:0], and a data strobe, SDQS[8:0].
The data and mask signals must be length matched to their associated strobe within ± 25 mils,
including package.
For SO-DIMM0 this length matching includes the motherboard trace length to the pads of the SODIMM0 connector (L1 + L2 + S0) plus package length.
For SO-DIMM1, the motherboard trace length to the pads of the SO-DIMM1 connector (L1 + L2 +
L3 + S1) plus package length.
Refer to Section 6.2 for more details on package length compensation.
Length range formula for SDQ and SDM,
X = SDQS total length, including package length, as defined previously
Y = SDQ, SDM total length, including package length, within same byte lane as show in Figure 25,
where: ( X – 25 mils )
Y
( X + 25 mils )
Length matching is not required from the SO-DIMM1 to the parallel termination resistors. Figure 25 on
the following page depicts the length matching requirements between the SDQ, SDM, and SDQS
signals within a byte lane. Byte lane mapping is defined in Table 21 below.
6.3.2.4.
SDQ to SDQS Mapping
Table 21 below defines the mapping between the nine byte lanes, nine mask bits, and the nine SDQS
signals, as required to do the required length matching.
Table 21. SDQ/SDM to SDQS Mapping
Signal
Mask
Relative To
SDQ[7:0]
SDM[0]
SDQS[0]
SDQ[15:8]
SDM[1]
SDQS[1]
SDQ[23:16]
SDM[2]
SDQS[2]
SDQ[31:24]
SDM[3]
SDQS[3]
SDQ[39:32]
SDM[4]
SDQS[4]
SDQ[56:40]
SDM[5]
SDQS[5]
SDQ[55:48]
SDM[6]
SDQS[6]
SDQ[63:56]
SDM[7]
SDQS[7]
SDQ[71:64]
SDM[8]
SDQS[8]
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Figure 25. SDQ/SDM to SDQS Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SDQ[0]
SDQ[1]
SDQ Length (Y) = (X ±25 mils)
SDQ[2]
SDQ[3]
GMCH
Die
SDQS[0]
SDQS Length = X
SDQ[4]
SDQ[5]
SDQ[6]
SDQ Length (Y) = (X ±25 mils)
SDQ[7]
SDM[0]
SDM Length (Y) = (X ±25 mils)
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
Note: Only one byte lane is shown for
reference. Each byte lane is matched
independently.
GMCH Package
SO-DIMM1
SDQ[0]
SDQ[1]
SDQ[2]
SDQ[3]
GMCH
Die
SO-DIMM0
SDQS[0]
SDQ[4]
SDQ Length (Y) =
(X +/-25 mils)
SDQS Length = X
SDQ[5]
SDQ[6]
SDQ[7]
SDM[0]
SDQ Length (Y) =
(X +/-25 mils)
SDM Length (Y) =
(X ±25 mils)
Note: All lengths are measured from GMCH diepad to SO-DIMM connector pads.
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6.3.2.5.
SDQ/SDQS Signal Package Lengths
The package length data in Table 22 below should be used to tune the length of each SDQ, SDM, and
SDQS motherboard trace as required to achieve the overall length matching requirements defined in the
prior sections.
Table 22. Memory SDQ/SDM/SDQS Package Lengths
Signal
Pin
Number
Pkg
Length
(mils)
Signal
Pin
Number
Pkg
Length
(mils)
Signal
Pin
Number
Pkg
Length
(mils)
SDQ_00
AF2
785
SDQ_24
AH10
648
SDQ_48
AE23
592
SDQ_01
AE3
751
SDQ_25
AH11
622
SDQ_49
AH23
752
SDQ_02
AF4
690
SDQ_26
AG13
572
SDQ_50
AE24
666
SDQ_03
AH2
903
SDQ_27
AF14
655
SDQ_51
AH25
817
SDQ_04
AD3
682
SDQ_28
AG11
599
SDQ_52
AG23
639
SDQ_05
AE2
739
SDQ_29
AD12
460
SDQ_53
AF23
667
SDQ_06
AG4
741
SDQ_30
AF13
536
SDQ_54
AF25
707
SDQ_07
AH3
845
SDQ_31
AH13
642
SDQ_55
AG25
783
SDQ_08
AD6
607
SDQ_32
AH16
766
SDQ_56
AH26
834
SDQ_09
AG5
756
SDQ_33
AG17
558
SDQ_57
AE26
701
SDQ_10
AG7
685
SDQ_34
AF19
510
SDQ_58
AG28
808
SDQ_11
AE8
558
SDQ_35
AE20
579
SDQ_59
AF28
756
SDQ_12
AF5
734
SDQ_36
AD18
408
SDQ_60
AG26
782
SDQ_13
AH4
825
SDQ_37
AE18
458
SDQ_61
AF26
748
SDQ_14
AF7
644
SDQ_38
AH18
658
SDQ_62
AE27
673
SDQ_15
AH6
912
SDQ_39
AG19
596
SDQ_63
AD27
608
SDQ_16
AF8
622
SDQ_40
AH20
677
SDQ_64
AG14
566
SDQ_17
AG8
624
SDQ_41
AG20
730
SDQ_65
AE14
477
SDQ_18
AH9
676
SDQ_42
AF22
562
SDQ_66
AE17
571
SDQ_19
AG10
634
SDQ_43
AH22
702
SDQ_67
AG16
530
SDQ_20
AH7
710
SDQ_44
AF20
563
SDQ_68
AH14
701
SDQ_21
AD9
508
SDQ_45
AH19
644
SDQ_69
AE15
421
SDQ_22
AF10
569
SDQ_46
AH21
716
SDQ_70
AF16
491
SDQ_23
AE11
469
SDQ_47
AG22
783
SDQ_71
AF17
530
SDM_0
AE5
838
SDQS_0
AG2
925
SDM_1
AE6
693
SDQS_1
AH5
838
SDM_2
AE9
538
SDQS_2
AH8
756
SDM_3
AH12
606
SDQS_3
AE12
466
SDM_4
AD19
492
SDQS_4
AH17
678
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6.3.2.6.
Signal
Pin
Number
Pkg
Length
(mils)
Signal
Pin
Number
Pkg
Length
(mils)
SDM_5
AD21
470
SDQS_5
AE21
487
SDM_6
AD24
557
SDQS_6
AH24
770
SDM_7
AH28
917
SDQS_7
AH27
858
SDM_8
AH15
685
SDQS_8
AD15
418
Signal
Pin
Number
Pkg
Length
(mils)
Memory Data Routing Example
Figure 26 is an example of a board routing for the Data signal group. The majority of the Data signal
route is on an internal layer, both external layers can be used for parallel termination R-pack placement.
Figure 26. Data Signals Group Routing Example
From GMCH/MCH
Data Signals
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6.3.3.
Control Signals – SCKE[3:0], SCS#[3:0]
The GMCH/MCH control signals, SCKE[3:0] and SCS#[3:0], are clocked into the DDR SDRAM
devices using clock signals SCK/SCK#[5:0]. The GMCH/MCH drives the control and clock signals
together, with the clocks crossing in the valid control window. The GMCH/MCH provides one chip
select (CS) and one clock enable (CKE) signal per SO-DIMM physical device row. Two chip select and
two clock enable signals will be routed to each SO-DIMM. Refer to Table 23 for the CKE and CS#
signal to SO-DIMM mapping.
Table 23. Control Signal to SO-DIMM Mapping
Signal
Relative To
SO-DIMM Pin
SCS#[0]
SO-DIMM0
AD23
SCS#[1]
SO-DIMM0
AD26
SCS#[2]
SO-DIMM1
AC22
SCS#[3]
SO-DIMM1
AC25
SCKE[0]
SO-DIMM0
AC7
SCKE[1]
SO-DIMM0
AB7
SCKE[2]
SO-DIMM1
AC9
SCKE[3]
SO-DIMM1
AC10
The control signal routing should transition from an external layer to an internal signal layer under the
GMCH/MCH, keep to the same internal layer until transitioning back out to an external layer to connect
to the appropriate pad of the SO-DIMM connector and the parallel termination resistor. If the layout
requires additional routing before the termination resistor, return to the same internal layer and transition
back out to an external layer immediately prior to parallel termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground reference to keep the path of return current continuous. Intel suggests that all control
signals be routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) control termination resistors, but control signals can
not be placed within the same R pack as the data or command signals. Figure 27 and Table 24 below
depict the recommended topology and layout routing guidelines for the DDR-SDRAM control signals.
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6.3.3.1.
Control Signal Topology
Figure 27. Control Signal Routing Topology
Vtt
GMCH
Rt
GMCH
Pin
P1
w
L2
L1
S1
SO-DIMM0,1 PAD
The control signals should be routed using 2 to 1 trace spacing to trace width ratio for signals within the
DDR group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR
related signals. Control signals should be routed on inner layers with minimized external trace lengths.
6.3.3.2.
Control Signal Routing Guidelines
Table 24. Control Signal Routing Guidelines
Parameter
Routing Guidelines
Signal Group
SCKE[3:0], SCS#[3:0]
Motherboard Topology
Point-to-Point with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
±15%
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
500 mils ± 250 mils (Refer to Table 25 for details)
Stub Length S1 – Stub from Via to SO-DIMM Pad
Max = 0.25”
Min = 0.5 inches
Trace Length L1+S1 – Total length from GMCH/MCH Signal
Ball to SO-DIMM Pad
Max = 5.5 inches for DDR 266
Max = 4.5 inches for DDR 333
Trace Length L2 – SO-DIMM via to Parallel Termination
Resistor Pad
Max = 2.0 inches
Parallel Termination Resistor (Rt)
56
Maximum Recommended Motherboard Via Count Per Signal
3
Length Matching Requirements
CTRL to SCK/SCK# [5:0] See length matching
Section 6.3.3.3 and Figure 28.
± 5%
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
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2. Power distribution vias from Rt to Vtt are not included in this count.
3. It is possible to route using two vias if one via is shared that connects to the SO-DIMM pad and parallel
termination resistor.
4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
6.3.3.3.
Control to Clock Length Matching Requirements
The length of the control signals, between the GMCH/MCH die pad and the SO-DIMM must fall within
the range defined below, with respect to the associated clock reference length. Refer to Figure 27 for a
definition of the various trace segments that make up this path. The length of trace from the SO-DIMM
to the termination resistor need not be length matched. The length matching requirements are also
depicted in Figure 28. Refer to Section 6.1 for more details on length matching requirements.
Length range formula for SO-DIMM0:
X0 = SCK/SCK#[2:0] total reference length, including package length.
Y0 = SCS#[1:0] & SCKE[1:0] total length = GMCH/MCH package length + L1 + S1, as shown in
Figure 28
where:
( X0 – 2.0” )
Y0
( X0 - 0.5” ) for DDR 200/266/33
Length range formula for SO-DIMM1:
X1 = SCK/SCK#[5:3] total reference length, including package length.
Y1 = SCS#[3:2] & SCKE[3:2] total length = GMCH/MCH package length + L1 + S1, as shown in
Figure 28,
where:
( X1 – 2.0” )
Y1
( X1 - 0.5” ) for DDR 200/266/33
No length matching is required from the SO-DIMM to the termination resistor. Figure 28 on the
following page depicts the length matching requirements between the control signals and clock. A
nominal CS/CKE package length of 500 mils can be used to estimate baseline MB lengths. Refer to
Section 6.2 for more details on package length compensation.
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Figure 28. Control Signal to Clock Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SCS#[1:0]
SCKE[1:0]
CNTRL Length = Y0
GMCH
Die
SCK[2:0]
SCK#[2:0]
Clock Ref. Length = X0
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
SO-DIMM0
GMCH Package
SO-DIMM1
SCS#[3:2]
SCKE[3:2]
CNTRL Length = Y1
GMCH
Die
SCK[5:3]
SCK#[5:3]
Clock Ref. Length = X1
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
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6.3.3.4.
Memory Control Routing Example
Figure 29 is an example of a board routing for the Control signal group.
Figure 29. Control Signals Group Routing Example
From GMCH
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6.3.3.5.
Control Group Package Length Table
The package length data in Table 25 below should be used to match the overall length of each command
signal to its associated clock reference length. Note that due to the relatively small variance in package
length and adequate timing margins it is acceptable to use a fixed 500-mil nominal package length for
all control signals, thereby reducing the complexity of the motherboard length calculations.
Table 25. Control Group Package Lengths
6.3.4.
Signal
Pin Number
Package
Length (mils)
Signal
Pin
Number
Package
Length (mils)
SCS#[0]
AD23
502
SCKE[0]
AC7
443
SCS#[1]
AD26
659
SCKE[1]
AB7
389
SCS#[2]
AC22
544
SCKE[2]
AC9
386
SCS#[3]
AC25
612
SCKE[3]
AC10
376
Command Signals – SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#,
SWE#
The GMCH/MCH chipset command signals, SMA[12:0], SBA[1:0], SRAS#, SCAS#, and SWE#
clocked into the DDR SDRAMs using the clock signals SCK/SCK#[5:0]. The GMCH/MCH drives the
command and clock signals together, with the clocks crossing in the valid command window. There are
three supported topologies for the command signal group. Topology 1 is a daisy chain topology.
Topology 2 implements a T routing topology. Both topologies allow series resistors to be placed
between the two SO-DIMMs to dampen the SO-DIMM to SO-DIMM resonance. Topology 2 is the
topology that best allows for placement of the SO-DIMMs back to back in the butterfly configuration,
thus minimizing the SO-DIMM footprint area. Topology 3 allows the series resistors to be physically
placed after the farthest SO-DIMM, when there is no room between the two connectors. Note that series
resistors are essential in all of the three topologies.
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6.3.4.1.
Command Topology 1
The command signal routing should transition from an external layer to an internal signal layer under
the GMCH/MCH. Keep to the same internal layer until transitioning back to an external layer
immediately prior to connecting the SO-DIMM0 connector pad. At the via transition for SO-DIMM0,
continue the signal route on the same internal layer to the series termination resistor (Rs), collocated to
SO-DIMM1. At this resistor the signal should transition to an external layer immediately prior to the pad
of Rs. After the series resistor, Rs, continue the signal route on the external layer landing on the
appropriate connector pad of SO-DIMM1. After SO-DIMM1, transition to the same internal layer or
stay on the external layer and route the signal to Rt.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can not be placed within the same R-packs as data, strobe, or control signals. Figure 30 and
Table 26 below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.
Figure 30. Command Routing for Topology 1
GMCH
GMCH
Pin
Vtt
Rs
P1
L1
L2
w
L4
L3
w
Rt
S0
SO-DIMM0 PAD
S1
SO-DIMM1 PAD
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils spacing to non-DDR
related signals. Command signals should be routed on inner layers with minimized external traces.
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6.3.4.2.
Command Topology 1 Routing Guidelines
Table 26. Command Topology 1 Routing Guidelines
Parameter
Routing Guidelines
Signal Group
SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology
Daisy Chain with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
± 15%
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
500 mils +/- 250 mils
(See Table 29 for exact package lengths.)
Stub Lengths S0, S1
Max = 0.25”
Trace Length L1 + S0 – GMCH/MCH Command Signal
Ball to First SO-DIMM Pad
Min = 0.5 inch
Total Length L1 + L2 + L3 + S1 – Total Length from
GMCH/MCH Ball to Second SO-DIMM Pad
Min = 1.0”
Max = 4.0 inches
Max = 7.0”
Total Length S0 + L2 + L3 + S1– Total SO-DIMM pad to
SO-DIMM pad spacing
Max = 3.0”
Trace Length L4 – Second SO-DIMM Via to Parallel
Resistor Pad
Max = 1.5 inches
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Maximum Recommended Motherboard Via Count Per
Signal
6
CMD to SCK/SCK# [5:0]
Length Matching Requirements
See length matching Section 6.3.4.3 and Figure 31 for
details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4. It is possible to route using four vias if one via is shared that connects to the SO-DIMM1 pad and parallel
termination resistor.
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6.3.4.3.
Command Topology 1 Length Matching Requirements
The routing length of the command signals, between the GMCH/MCH die pad and the SO-DIMM must
be within the range defined below, with respect to the associated clock reference length. Refer to Figure
30 for a definition of the various motherboard trace segments. The length of trace from the SO-DIMM
to the termination resistor need not be length matched. The length matching requirements are also
depicted in Figure 31. Refer to Section 6.1 for more details on length matching requirements.
Length range formula for SO-DIMM0:
X0 = SCK/SCK#[2:0] total reference length, including package length.
Y0 = CMD signal total length = GMCH/MCH package + L1 + S0, as shown in Figure 31,
where:
( X0 – 2.0” )
Y0
( X0 + 2.0” ) for DDR 200/266/333
Length range formula for SO-DIMM1:
X1 = SCK/SCK#[5:3] total reference length, including package length.
Y1 = CMD signal total length = GMCH/MCH package + L1 + L2 + L3 + S1, as shown in Figure 31,
where:
( X1 – 2.0” )
Y1
( X1 + 2.0” ) for DDR 200/266/333
No length matching is required from SO-DIMM1 to the termination resistor. Figure 31 on the following
page depicts the length matching requirements between the command signals and clock. A nominal
CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for
more details on package length compensation.
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Figure 31. Topology 1 Command Signal to Clock Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SMAA[12:6,3,0]
SBA[1:0],
RAS#, CAS#,
WE#
CMD Length = Y0
GMCH
Die
SCK[2:0]
Clock Reference Length = X0
SCK#[2:0]
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
SO-DIMM0
GMCH Package
SMAA[12:6,3,0]
SBA[1:0],
RAS#, CAS#,
WE#
SO-DIMM1
CMD Length = Y1
GMCH
Die
SCK[5:3]
SCK#[5:3]
Clock Ref Length = X1
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
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6.3.4.4.
Command Topology 2
The command signal routing should transition from an external layer to an internal signal layer under
the GMCH/MCH. Keep to the same internal layer until transitioning back to an external layer at the
series resistor Rs. At this point there is a T in the topology. One leg of the T will route through Rs and
either transition back to the same internal layer or stay external and landing on the appropriate connector
pad of SO-DIMM0. If it was necessary to return to the internal layer the signal should return to the
external layer immediately prior to landing on the appropriate connector pad of SO-DIMM0. The other
leg of the T will continue on the same internal layer and return to the external layer immediately prior to
landing on the appropriate connector pad of SO-DIMM1. If possible, stay on the external layer and
connect to the parallel termination resistor or if the parallel termination resistor is on the opposite side of
the board from the SO-DIMM1 connector then share the via and route to the parallel termination
resistor. If sharing the via or using the opposite side of the board is not possible, continue on the same
internal layer and route to the external layer immediately prior to the termination resistor.
External trace lengths should be minimized. It is suggested that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. It is recommended that
command signal group be routed on same internal layer.
It is suggested that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can not be placed within the same R-packs as data, strobe or control signals. Figure 32 and Table
27 below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.
Figure 32. Command Routing Topology 2
GMCH
Vtt
Rt
GMCH
Pin
P1
L1
L3
S0
L4
S1
Rs
SO-DIMM1 PAD
L2
SO-DIMM0 PAD
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to nonDDR related signals. Command signals should be routed on inner layers with minimized external trace
lengths.
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6.3.4.5.
Command Topology 2 Routing Guidelines
Table 27. Command Topology 2 Routing Guidelines
Parameter
Routing Guidelines
Signal Group
SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology
Branched T with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
± 15%
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
500 mils ± 250 mils
(See Table 29 for exact package length.)
Stub Length S0, S1
Max = 0.25”
Trace Length L2 – Series Resistor Pad to First SO-DIMM
Pad
Max = 1.0 inches
Total Length L1+ S0 + L2 – Total length from GMCH/MCH
ball to First SO-DIMM pad
Min = 0.5”
Total Length L1+ L3 + S1 – Total length from GMCH/MCH
ball to Second SO-DIMM pad
Min = 1.0”
Max = 5.0”
Max = 7.0”
Total Length S0 + L2 + L3 + S1– Total SO-DIMM pad to
SO-DIMM pad spacing
Max = 3.0”
Trace Length L4 – Second SO-DIMM Via to Parallel
Resistor Pad
Max = 1.5”
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Maximum Recommended Motherboard Via Count Per
Signal
6
CMD to SCK/SCK# [5:0]
Length Matching Requirements
See length matching Section 6.3.4.6 and Figure 33 for
details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series
termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that
connects to the SO-DIMM1 pad and parallel termination resistor.
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6.3.4.6.
Command Topology 2 Length Matching Requirements
The routed length of the command signals, between the GMCH/MCH package ball and the SO-DIMM
must be within the range defined below, with respect to the associated clock reference length. Refer to
Figure 32 for a definition of the various motherboard trace segments. The length of trace from the SODIMM to the termination resistor need not be length matched. The length matching requirements are
also depicted in Figure 33. Refer to Section 6.1 for more details on length matching requirements.
Length range formula for SO-DIMM0
X0 = SCK/SCK#[2:0] total reference length, including package length.
Y0 = CMD signal total length = GMCH/MCH package + L1 + L2 + S0, as shown in Figure 33,
where:
( X0 – 2.0” )
Y0
( X0 + 2.0” ) for DDR 200/266/333
Length range formula for SO-DIMM1
X2 = SCK/SCK#[5:3] total reference length, including package length.
Y2 = CMD signal total length = GMCH/MCH package length + L1 + L3 + S1, as shown in Figure 33,
where:
( X1 – 2.0” )
Y1
( X1 + 2.0” ) for DDR 200/266/333
No length matching is required from SO-DIMM1 to the termination resistor. Figure 33 on the following
page depicts the length matching requirements between the command signals and clock. A nominal
CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for
more details on package length compensation.
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Figure 33. Topology 2 Command Signal to Clock Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SMAA[12:6,3,0]
SBA[1:0],
SRAS#, SCAS#,
SWE
CMD Length = Y0
GMCH
Die
SCK[2:0]
Clock Reference Length = X0
SCK#[2:0]
Note: All lengths are measured from MCH die
pad to SO-DIMM connector pad.
SO-DIMM0
GMCH Package
SO-DIMM1
SMAA[12:6,3,0]
SBA[1:0],
SRAS#, SCAS#,
SWE#
CMD Length = Y1
GMCH
Die
SCK[5:3]
SCK#[5:3]
Clock Ref Length = X1
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
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6.3.4.7.
Command Topology 2 Routing Example
Figure 34 is an example of a board routing for the Command signal group.
Figure 34. Example of Command Signal Group
From GMCH
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6.3.4.8.
Command Topology 3
This topology is recommended when the SO-DIMMS are too close together for the series resistor to be
placed between connectors. In this topology the series resistors are placed behind the second SODIMM.
External trace lengths should be minimized. It is suggested that the parallel termination be placed on
both sides of the board to simplify routing and minimize trace lengths. All internal and external signals
should be ground referenced to keep the path of the return current continuous. Intel recommends that the
command signal group be routed on same internal layer.
Intel suggests that the parallel termination (Rt) be placed on both sides of the board to simplify routing
and minimize trace lengths. All internal and external signals should be ground referenced to keep the
path of the return current continuous.
Resistor packs are acceptable for the series and parallel command termination resistors but command
signals can not be placed within the same R-packs as data, strobe or control signals. The diagrams and
tables below depict the recommended topology and layout routing guidelines for the DDR-SDRAM
command signals routing to SO-DIMM0 and SO-DIMM1.
Figure 35. Command Routing Topology 3
MCH
Vtt
Rt
MCH
Pin
P1
L1
L2
S0
L4
S1
Rs
SO-DIMM0 PAD
L3
SO-DIMM1 PAD
The command signals should be routed using a 2 to 1 trace spacing to trace width ratio for signals within
the DDR group, except clocks and strobes. There should be a minimum of 20 mils of spacing to nonDDR related signals. Command signals should be routed on inner layers with minimized external trace
lengths.
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6.3.4.9.
Command Topology 3 Routing Guidelines
Table 28. Command Topology 3 Routing Guidelines
Parameter
Routing Guidelines
Signal Group
SMA[12:6,3,0], SBA[1:0], SRAS#, SCAS#, SWE#
Motherboard Topology
Branched T with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
± 15%
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
500 mils ± 250 mils
(See Table 29 for exact package lengths.)
Stub Length S0, S1
Max = 0.25”
Total Length L1+ S0 – Total length from GMCH/MCH
ball to First SO-DIMM pad
Min = 0.5”
Trace Length L3 – Series Resistor Pad to Second SODIMM Pad
Total Length L1+L2 + L3 + S1 – Total length from
GMCH/MCH ball to Second SO-DIMM pad
Max = 4.0”
Max = 1.0”
Min = 1.0”
Max = 7.0”
Total Length S0 + L2 + L3 + S1– Total SO-DIMM pad
to SO-DIMM pad spacing
Max = 3.0”
Trace Length L4 – Second SO-DIMM Via to Parallel
Resistor Pad
Max = 1.5”
Series Termination Resistor (Rs)
10
± 5%
Parallel Termination Resistor (Rt)
56
± 5%
Maximum Recommended Motherboard Via Count Per
Signal
6
CMD to SCK/SCK# [5:0]
Length Matching Requirements
See length matching Section 6.3.4.10 and Figure 36 for
details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
4. It is possible to route using three vias if one via is shared that connects to the SO-DIMM0 pad and series
termination resistor, if a via is shared that connects L1 to series termination and if one via is shared that
connects to the SO-DIMM1 pad and parallel termination resistor.
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6.3.4.10. Command Topology 3 Length Matching Requirements
The routed length of the command signals, between the GMCH/MCH package ball and the SO-DIMM
must be within the range defined below, with respect to the associated clock reference length. Refer to
Figure 32 for a definition of the various motherboard trace segments. The length of trace from the SODIMM to the termination resistor need not be length matched. The length matching requirements are
also depicted in Figure 33. Refer to Section 6.1 for more details on length matching requirements.
Length range formula for SO-DIMM0:
X0 = SCK/SCK#[2:0] total reference length, including package length.
Y0 = CMD signal total length = GMCH/MCH package + L1 + S0, as shown in Figure 36,
where:
( X0 – 2.0” )
Y0
( X0 + 2.0” ) for DDR 200/266/333
Length range formula for SO-DIMM1:
X2 = SCK/SCK#[5:3] total reference length, including package length.
Y2 = CMD signal total length = GMCH/MCH package length + L1 + L2 +L3 + S1, as shown in
Figure 36,
where:
( X1 – 2.0” )
Y1
( X1 + 2.0” ) for DDR 200/266/333
No length matching is required from SO-DIMM1 to the termination resistor. Figure 33 on the following
page depicts the length matching requirements between the command signals and clock. A nominal
CMD package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section 6.2 for
more details on package length compensation.
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Figure 36. Topology 3 Command Signal to Clock Trace Length Matching Diagram
SO-DIMM0
GMCH Package
SMAA[12:6,3,0]
SBA[1:0],
RAS#, CAS#,
WE#
CMD Length = Y0
GMCH
Die
SCK[2:0]
Clock Reference Length = X0
SCK#[2:0]
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
SO-DIMM0
GMCH Package
SMAA[12:6,3,0]
SBA[1:0],
RAS#, CAS#,
WE#
SO-DIMM1
to termination
CMD Length = Y1
GMCH
Die
SCK[5:3]
SCK#[5:3]
Clock Ref Length = X1
Note: All lengths are measured from GMCH die
pad to SO-DIMM connector pad.
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6.3.4.11. Command Group Package Length Table
The package length data in Table 29 below should be used to match the overall length of each command
signal to its associated clock reference length.
Table 29. Command Group Package Lengths
100
Signal
Pin Number
Pkg Length
(mils)
SMA[0]
AC18
420
SMA[3]
AD17
472
SMA[6]
AD8
591
SMA[7]
AD7
596
SMA[8]
AC6
630
SMA[9]
AC5
681
SMA[10]
AC19
377
SMA[11]
AD5
683
SMA[12]
AB5
609
SBA[0]
AD22
592
SBA[1]
AD20
435
SCAS#
AC24
562
SRAS#
AC21
499
SWE#
AD25
751
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6.3.5.
CPC Signals – SMA[5,4,2,1], SMAB[5,4,2,1]
The GMCH/MCH chipset CPC (clock-per-command) signals, SMA[5,4,2,1] and SMAB[5,4,2,1]are
“clocked” into the DDR SDRAM devices using clock signals SCK/SCK#[5:0]. The GMCH/MCH drives
the CPC and clock signals together, with the clocks crossing in the valid command window. The
GMCH/MCH provides one set of CPC signals per SO-DIMM slot.
Refer to Table 23 for the CKE and CS# signal to SO-DIMM mapping.
Table 30. CPC Signal to SO-DIMM Mapping
Signal
Relative To
SO-DIMM Pin
SMA[1]
SO-DIMM0
AD14
SMA[2]
SO-DIMM0
AD13
SMA[4]
SO-DIMM0
AD11
SMA[5]
SO-DIMM0
AC13
SMAB[1]
SO-DIMM1
AD16
SMAB[2]
SO-DIMM1
AC12
SMAB[4]
SO-DIMM1
AF11
SMAB[5]
SO-DIMM1
AD10
The CPC signal routing should transition from an external layer to an internal signal layer under the
GMCH/MCH. Keep to the same internal layer until transitioning back out to an external layer to connect to
the appropriate pad of the SO-DIMM connector and the parallel termination resistor. If the layout requires
additional routing before the termination resistor, return to the same internal layer and transition back out
to an external layer immediately prior to parallel termination resistor.
External trace lengths should be minimized. Intel suggests that the parallel termination be placed on both
sides of the board to simplify routing and minimize trace lengths. All internal and external signals should
be ground reference to keep the path of return current continuous. Intel suggests that all CPC signals be
routed on the same internal layer.
Resistor packs are acceptable for the parallel (Rt) CPC termination resistors. Figure 37 and Table 31 below
depict the recommended topology and layout routing guidelines for the DDR-SDRAM CPC signals.
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6.3.5.1.
CPC Signal Topology
Figure 37. Command per Clock Signal Routing Topology
V tt
GM CH
Rt
GM CH
P in
P1
w
L2
L1
S1
SO -D IM M 0,1 P A D
The CPC signals should be routed using 2 to 1 trace space to width ratio for signals within the DDR
group, except clocks and strobes. There should be a minimum of 20-mils of spacing to non-DDR related
signals. CPC signals should be routed on inner layers with minimized external trace lengths.
6.3.5.2.
CPC Signal Routing Guidelines
Table 31. CPC Signal Routing Guidelines
Parameter
Routing Guidelines
Signal Group
SMA[5,4,2,1], SMAB[5,4,2,1]
Motherboard Topology
Point-to-Point with Parallel Termination
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
±15%
Inner layers: 4 mils
Outer layers: 5 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DDR Signals
20 mils
Package Length P1
Stub Length S1
500 mils ± 250 mils
(See Table 32 for exact package lengths.)
Max = 0.25”
Min = 0.5 inches
Trace Length L1 – GMCH/MCH Control Signal Ball to SO-DIMM
Pad
Max = 5.5 inches for DDR266
Max = 4.5 inches for DDR333
102
Trace Length L2 – SO-DIMM Via to Parallel Termination Resistor
Pad
Max = 2.0 inches
Parallel Termination Resistor (Rt)
56
Maximum Recommended Motherboard Via Count Per Signal
3
± 5%
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CPC to SCK/SCK# [5:0]
Length Matching Requirements
See length matching Section 6.3.5.3 for
details.
NOTES:
1. Recommended resistor values and trace lengths may change in a later revision of the design guide.
2. Power distribution vias from Rt to Vtt are not included in this count.
3. It is possible to route using two vias if one via is shared that connects to the SO-DIMM pad and parallel
termination resistor.
4. The overall maximum and minimum length to the SO-DIMM must comply with clock length matching
requirements.
6.3.5.3.
CPC to Clock Length Matching Requirements
The total length of the CPC signals, between the GMCH/MCH die pad and the SO-DIMM must fall
within the range defined below, with respect to the associated clock reference length. Refer to Figure 37
for a definition of the various trace segments. The length the trace from the SO-DIMM to the
termination resistor need not be length matched. Refer to Section 6.1 for more details on length
matching requirements. A table of CPC signal package length is provided in Section 6.3.5.4.
Length range formula for SO-DIMM0:
X0 = SCK/SCK#[2:0] total reference length, including package length.
Y0 = SMA[5,4,2,1] total length = GMCH/MCH package + L1 + S1, as shown in,
where: ( X0 – 2.0” )
Y0
( X0 - 1.0” ) for DDR 200/266/333
Length range formula for SO-DIMM1:
X1 = SCK/SCK#[5:3] total reference length, including package length.
Y1 = SMAB[5,4,2,1] total length = GMCH/MCH package + L1 + S1, as shown in,
where: ( X1 – 2.0” )
Y1
( X1 - 1.0” ) for DDR 200/266/333
No length matching is required from SO-DIMM1 to the termination resistor.
on the following page depicts the length matching requirements between the CPC signals and clock. A
nominal CPC package length of 500 mils can be used to estimate baseline MB lengths. Refer to Section
6.2 for more details on package length compensation.
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Figure 38. CPC Signals to Clock Length Matching Diagram
SO-DIMM0
GMCH Package
SMA[5,4,2,1]
CPC Length = Y0
GMCH
Die
SCK[2:0]
SCK#[2:0]
Clock Reference Length = X0
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pad.
SO-DIMM0
SO-DIMM1
GMCH Package
CPC Length = Y1
SMAB[5,4,2,1]
GMCH
Die
SCK[5:3]
Clock Ref Length = X1
SCK#[5:3]
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pad.
6.3.5.4.
CPC Group Package Length Table
The package length data in the table below should be used to match the overall length of each CPC
signal to its associated clock reference length.
Table 32. CPC Group Package Lengths
104
Signal
Pin
Number
Pkg Length
(mils)
Signal
Pin
Number
Pkg Length
(mils)
SMA[1]
AD14
398
SMAB[1]
AD16
427
SMA[2]
AD13
443
SMAB[2]
AC12
395
SMA[4]
AD11
430
SMAB[4]
AF11
716
SMA[5]
AC13
346
SMAB[5]
AD10
631
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6.3.6.
Feedback – RCVENOUT#, RCVENIN#
The Intel 852GME/852GMV/852PMchipset GMCH/MCH provides a feedback signal called “receive
enable” (RCVEN#), which is used to measure timing for the read data.
The RCVENOUT# signal is shunted directly to RCVENIN# inside the package in order to reduce
timing variance. With this change it is no longer necessary to provide an external connection.
However, it is recommended that both signals be transitioned to the bottom side with vias located
adjacent to the package ball in order to facilitate probing.
6.4.
Routing Updates for “High-Density” Memory Device
Support
Simulation results show that the current DDR layout and routing guidelines for the Intel
852GME/852GMV/852PMchipset-based platforms can support “high-density” SO-DIMM memory
modules. Please contact your Intel field representative for command signal group related BIOS settings
for supporting high-density SO-DIMM modules.
6.5.
ECC Disable Guidelines
The GMCH/MCH can be configured to operate in an ECC data integrity mode that allows multiple bit
error detection and single bit error correction. This option to support ECC DDR memory modules is
dependent on design objectives. By default, ECC functionality is disabled on the platform.
6.5.1.
GMCH/MCH ECC Functionality Disable
If non-ECC memory modules are to be the only supported memory type on the platform, then the eight
DDR check bits signals, associated strobe, data mask bit, and differential clock pairs associated with the
ECC device for each SO-DIMM can be left as no connects on the GMCH/MCH. For the GMCH/MCH,
this includes SDQ[71:64], SDQS8, SDM8 and the two differential clock pairs that are not routed to the
SO-DIMMs.
The 852GME/852GMV/852PMchipset GMCH/MCH provides the capability to enable and disable the
CS/CKE control and SCK signals to unpopulated SO-DIMMs to save power. Although DDR SODIMM connectors may provide motherboard lands for three clock pairs, non-ECC SO-DIMMs only
require two pairs.
The GMCH/MCH provides some flexibility on how the SCK clock pairs, control signals, and CPC
signals are assigned to the SO-DIMMs, provided that BIOS initialization of memory matches the
hardware configuration. Two examples are listed below. Please contact your Intel field representative
for memory reference code for more details.
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Example 1
Example 2
SO-DIMM0
SO-DIMM1
SO-DIMM0
SO-DIMM1
SCK0,1,2
SCK3,4,5
SCK0,1,2
SCK3,4,5
SMAA[1,2,4,5]
SMAB[1,2,4,5]
SMAB[1,2,4,5]
SMAA[1,2,4,5]
SCKE0,1; SCS#0,1
SCKE2,3; SCS#2,3
SCKE0,1; SCS#0,1 SCKE2,3; SCS#2,3
On platforms where ECC memory is supported, it is important that all relevant SDQ, SDQS, and SCK
signals to the SO-DIMMs be disabled when the system is populated with only non-ECC or a
combination of ECC and non-ECC memory.
Please contact your Intel field representative for information on memory initialization and register
programming.
6.5.2.
DDR Memory ECC Functionality Disable
It is imperative that systems that do not support ECC memory ensure the SCK clock pairs that are
normally sent to ECC SO-DIMMs be disabled. If the SCK clock pairs associated with the check bit
signals were left floating in a non-ECC memory only system and ECC memory was used in one or more
of the SO-DIMM slots, this could cause the ECC device on the SO-DIMM to be enabled. If SDQ[71:64]
is disabled/tri-stated or not routed, then these floating inputs can cause the ECC device to draw current
and potentially compromise the ECC device.
In JEDEC PC2100 DDR SDRAM Unbuffered SO-DIMM Reference Design Specification, Rev 1.0, it is
noted that pin 89 and pin 91 (CK2 and CK2#) of the SO-DIMM connector are reserved for x72 modules
or registered modules. By default, 852GME/852GMV/852PMdoes not drive SCK2, SCK2#, SCK5,
SCK5#. Therefore, it is important to make sure that the memory modules are not expected to use all
clock pairs.
6.6.
System Memory Compensation
See Section 12.5.4 for details.
6.7.
SMVREF Generation
See Section 12.5.3.1 for details.
6.8.
DDR Power Delivery
See Section 12.5.4 for details.
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6.9.
External Thermal Sensor Based Throttling (ETS#)
The GMCH/MCH’s ETS# input pin is an active low input that can be used with an external thermal
sensor to monitor the temperature of the DDR SO-DIMMs for a possible thermal condition. Assertion of
ETS# will result in the limiting of DRAM bandwidth on the DDR memory interface to reduce the
temperature in the vicinity of the system memory.
By default, the functionality and input buffer associated with ETS# are disabled. Also, the GMCH/MCH
can be programmed to send an SERR, SCI, or SMI message to the ICH4-M upon the assertion of this
signal. External thermal sensors that are suitable for the purpose described above would need to have a
small form factor and be able to accurately monitor the ambient temperature in the vicinity of the DDR
system memory.
6.9.1.
ETS# Usage Model
The thermal sensors targeted for this application with the GMCH/MCH’s ETS# are planned to be
capable of measuring the ambient temperature only and should be able to assert ETS# if the
preprogrammed thermal limits/conditions are met or exceeded. Because many variables within a mobile
system can affect the temperature measured at any given point, the expected usage and effectiveness of
ETS# is also very focused. Factors such as thermal sensor placement, airflow within a mobile chassis,
adjacent components, thermal sensor sensitivity, and thermal sensor response time, allow ETS# to be
effectively used for controlling skin temperatures. However, due to the location of the thermal sensor,
ETS# should not be used for measuring or controlling the Tj or Tcase parameters of DDR-SDRAM
devices since it cannot respond quickly enough to dynamic changes in DRAM power.
6.9.2.
ETS# Design Guidelines
ETS#, as implemented in the GMCH/MCH, is an active low signal and does not have an integrated pullup to maintain a logic 1. As a result of this, an external 8.2-k to 10-k pull-up resistor should be
provided near the ETS# pin, connected to 3.3 V. Ideally, the thermal sensor should implement an open
drain type output buffer to drive ETS#. A system is expected to have one thermal sensor per SO-DIMM
connector on the motherboard.
6.9.3.
Thermal Sensor Routing and Placement Guidelines
Routing guidelines and other special, motherboard design considerations will vary with the vendor and
type of thermal sensor chosen for this ETS# application. As a result, vendor specific design guidelines
should also be followed closely to ensure proper operation of this feature. As a general rule, system
designers should follow good design practices in ensuring good signal integrity on this signal as well as
achieving adequate isolation from adjacent signals. Also, any thermal design considerations (e.g. proper
ground flood placement underneath the external thermal sensor; proper isolation of the differential
signal routing for thermal diode applications, etc.) for the external thermal sensor itself should also be
met.
The many factors that can affect the accuracy of ambient temperature measurements by thermal sensors
make the placement of them a very critical and especially challenging task. Ideally, one thermal sensor
should be placed near each SO-DIMM in a system. The thermal sensor should be located in an area
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where the effects of airflow and effects of conduction from adjacent components are minimized. This
allows for the best correlation of thermal sensor temperature to chassis or notebook surface temperature.
See Figure 39 for details.
Assuming airflow is negligible within a system, the optimal placement of the thermal sensor is on the
surface of the motherboard directly beneath the shadow of an SO-DIMM module centered longitudinally
and laterally in relation to the outline of the SO-DIMM. The thermal sensor should have a form factor
small enough to allow it to fit beneath double-sided memory modules (i.e. modules with memory
devices on both sides of a module). If placement within the outline of an SO-DIMM is not possible, then
the next best option is to locate it within approximately 15 mm (0.6 inches) of the outline/SO-DIMM
shadow. Again, this assumes negligible effects from airflow.
Please refer to the Intel® 852GM Chipset Mobile Thermal Design Guide for more details.
Figure 39. DDR Memory Thermal Sensor Placement
15mm
15mm
15mm
15mm
Hashed Area:
Recommended area for
DRAM ETS# sensor on
motherboard.
Best Location is sensor
under SO-DIMM. May not
Best Location is sensor
be mechanically feasible
in all designs due to small
gap between SO-DIMM
and motherboard.
Sensor location within approx 15mm of
SO -DIMM
outline
noteffective
be as
SO-DIMM outline
will
notwill
bebeas
at controlling fast transient temperature
changes.
108
Top View
View –
– SO-DIMM
SO-DIMM
Top
Side View – SO-DIMM
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7.
Integrated Graphics Display Port
Note: This section of this document applies to Intel 852GME GMCH chipsets.
The GMCH contains four display ports: an analog CRT port, a dedicated LVDS port, and two 12-bit
Digital Video Out (DVO) ports. Section 7.1 will discuss the CRT and RAMDAC routing requirements.
Section 7.2 will discuss the dedicated LVDS port. Section 7.3 will discuss the DVOB and DVOC design
guideline. Section 7.4 provides recommendations for a flexible modular design guideline for DVOB
and DVOC muxed interfaces. Section 7.5 provides recommendations for the GPIO signal group.
7.1.
Analog RGB/CRT Guidelines
7.1.1.
RAMDAC/Display Interface
The GMCH integrated graphics/chipset design interfaces to an analog display via a RAMDAC. The
RAMDAC is a subsection of the graphics controller display engine and consists of three identical 8-bit
digital-to-analog converter (DAC) channels, one for the display’s red, green, and blue electron guns.
Each RGB output is doubly terminated with a 75- resistance: One 75- resistance is connected from
the DAC output to the board ground, and the other termination resistance exists within the display. The
equivalent DC resistance at the output of each DAC is 37.5 . The current output from each DAC flows
into this equivalent resistive load to produce a video voltage, without the need for external buffering.
There is also a pi-filter on each channel that is used to reduce high-frequency noise and to reduce EMI.
In order to maximize the performance, the filter impedance, cable impedance, and load impedance
should be matched.
Since the DAC operates at pixel frequencies up to 350 MHz, special attention should be paid to signal
integrity and EMI. RGB routing, component placement, component selection, cable and load
impedance (monitor) all play a large role in the analog display’s quality and robustness. This holds true
for all resolutions, but especially for those at 1600x1200 resolutions or higher.
7.1.2.
Reference Resistor (REFSET)
A reference resistor, Rset, is used to set the reference current for the DAC. This resistor is an external
resistor with a 1% tolerance that is placed on the circuit board. A reference resistor can be selected from
a range between 124 to 137 (1%). Based on board design, DAC RGB outputs may be measured
when the display is completely white. If the RGB voltage value is between 665 mV to 770 mV, then the
video level is within VESA specification and the resistor value that was chosen will be optimal for
board design.
A reference voltage is generated on the GMCH from a bandgap voltage reference circuit. The bandgap
reference voltage level is approximately 1.2 V and this voltage is divided by four to generate the
reference voltage. The VESA video standard defines the LSB current for each DAC channel. The
RAMDAC reference current is designed on-die to be equal to 32 LSB. Therefore, the external reference
resistor value is defined as:
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Equation 2.
Rset =
Vreference
(Vbg / 4)
=
Ireference 32 * (73.2uA)
A 1271% precision resistor value is the recommend value to use. See Figure 40 for the
recommended Rset placement.
Note: When using 852GME platform with external graphics only, Rset resistor is not needed.
Figure 40. Rset Placement
Intel 852GM E
Chipset
IRE F ball
R esistor
Solder
Pads
Rset
127Ω , 1% , 1/16W
S MT m etal film
resistor
Short, wide route
connecting the
resistor to the IRE F
ball
Resistor
Top Side of
M otherboard
No toggling signals
should be routed near this
reference resistor
Large via or m ultiple
vias straight dow n to
ground plane
7.1.3.
RAMDAC Board Design Guidelines
Care should be taken when routing the analog RAMDAC signals. This is especially true to successfully
support high display resolution where pixel frequency can be as high as 350 MHz. Intel recommends
that each analog R, G, B signal be routed single-endedly. The analog RGB signals should be routed with
an impedance of 37.5 . Intel recommends that these be routed on an inner routing layer and that it be
shielded with VSS planes, if possible. Spacing between DAC channels and to other signals should be
maximized; 20-mil spacing is recommended. The RGB signals require pi filters that should be placed
near the VGA connector. It consists of two 3.3-pF caps with a 75 Ω ferrite bead at 100 MHz between
them. The RGB signals should have a 75-Ω, 1% terminating pull-down resistor. The complement signals
(R#, G#, and B#) should be grounded to the ground plane.
Note: When using 852GME/852GMV/852PMwith external graphics only, the RGB 75-Ω termination resistors
are not needed.
Intel recommends that the pi filter and terminating resistors be placed as close as possible to the VGA
connector. After the 75- termination resistor, the RGB signals routing to the pi-filters and the VGA
110
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connector should ideally be routed with 75impedance as possible.
impedance (~ 5 mil traces), or as close to 75-
The RGB signals also require protection diodes between 1.5 V and ground. These diodes should have
low C ratings (~5 pF max) and small leakage current (~ 10 A at 120˚C) and should be properly
decoupled with a 0.1- F cap. These diodes and decoupling should be placed to minimize power rail
inductance. The choice between diodes (or diode packs) should comprehend the recommended electrical
characteristics in addition to cost.
The RGB signals should be length matched as closely as possible (from the GMCH to the VGA
connector) and should not exceed 200 mils of mismatch.
7.1.4.
RAMDAC Routing Guidelines
Figure 41. GMCH DAC Routing Guidelines with Docking Connector
1.5V
Motherboard
C1
VCCDACA1 VCCDACA2
C2
FB
1.5V 37.5 Ω
traces
R1
D
C
75 Ω trace
C
Switch
RED
Red
DAC
Channel
Docking Station
Place C1 and C2 as
close to package as
possible
D
C1
RED#
Pin 1 Red
1.5V 37.5 Ω
traces
D
R1
C
75 Ω trace
D
R1
Pin 2 Green
FB
C
75 Ω trace
C
C
Pin 3 Blue
Switch
GREEN
Green
DAC
Channel
FB
37.5 Ω trace
C1
VGA
Connector
on main
board
37.5 Ω trace FB
GREEN#
R1
C
75 Ω trace
C
Red
FB
1.5V 37.5 Ω
traces
R1
D
BLUE
Blue
DAC
Channel
C
75 Ω trace
C
37.5 Ω trace
Switch
D
C1
R1
FB
C
Green
75 Ω trace
C
Docking
Connector
BLUE#
IREF
VSSDACA
VGA
Connector
on docking
station
Place components in
Close proximity to VGA
& Docking connectors
Place components in
Close proximity to VGA
& Docking connectors
REFSET
Place ESD diodes to
minimize power rail
inductance – place C1 as
close to diodes as possible
Blue
Do NOT route any highfrequency signals in the
shaded area
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
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The DAC channel (red, green, blue) outputs should be routed as single-ended shielded routes to an
analog switch to support a docking station. An analog switch should be used in order to provide the
proper termination that is required for high-performance video signal integrity. See Table 33. The
analog switch should exhibit a low “on” resistance (< 8 ) and low parasitic capacitance (<10 pF). The
output routing from the analog switch should be routed as single-ended, 37.5-Ω impedance to the 75termination resistors that are located near the VGA connector on the motherboard and the VGA
connector on the docking station. The single-ended routing after these 75- termination resistors to the
pi-filter and then to the VGA connector should be ideally 75- . The recommended routing of the
termination resistors is shown in Table 33.
Table 33. Recommended GMCH DAC Components
Recommended DAC Board Components
Component
Value
R1
Refset
1
Tolerance
Power
Type
75.0
1%
1/16 W
SMT, Metal Film
127.0
1%
1/16 W
SMT, Metal Film
C1
0.1 µF
20%
-----
SMT, Ceramic
C2
0.01 µF
20%
-----
SMT, Ceramic
C
3.3 pF
10%
-----
SMT, Ceramic
California Micro Devices –
D
PAC DN006
-------
350 mW
ESD diodes for VGA, SOIC package
Or equivalent diode array
FB
75
Analog
Switch
NOTE:
112
@ 100 MHz
--------
-------
-------
-------
Rated for a continuous
channel current of 100
mA (min)
MuRata* BLM11B750S
Ron < 8
, Con < 10pF
Texas Instruments SN74CB3Q3306
Not needed when using 852PM platform or 852GME platform with external graphics.
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Figure 42. DAC R, G, B Routing and Resistor Layout Example
Complement Output Intel 852GME DAC Output
Chipset
(e.g. BLUE)
(e.g. BLUE#)
Via to
ground
plane
20 mil Space between channels
20 mil Space between channels
37.5Ω Trace Impedance
37.5Ω Trace Impedance
75Ω Trace Impedance
75Ω Trace Impedance
VGA
Π-Filter
VGA
Π-Filter
ANALOG
SWITCH
75.0Ω, 1%, 1/16W,
75.0down to ground
75.0
75.0Ω,
1%, 1/16W, SMT metal film resistor
Large via or multiple vias straight
plane
Large via or multiple vias straight down to ground plane
No toggling signals sho
No toggling signals should be routed near these video outputs
Termination Resistor placed on Dock Station
Near VGA connector
NOTE:
7.1.5.
Termination Resistor placed on Motherboard
Near VGA connector
The routing to the docking connector is not shown in this figure; however, this routing scheme applies to the
docking connector as well.
DAC Power Requirements
The DAC requires a 1.5-V supply through its two VCCADAC balls. The two may share a set of
capacitors, 0.1 F and 0.01 F, but this connection should have low inductance. Separate analog power
or ground planes are not required for the DAC.
However, since the DAC is an analog circuit, it is particularly sensitive to AC noise seen on its power
rail. Designs should provide as clean and quiet a supply as possible to the VCCA_DAC. Additional
filtering and/or separate voltage rail may be needed to do so. On the Intel CRB, there is a placeholder
for a LC filter in case there is noise present in the VCCA power rail.
Video DAC Power Supply DC Specification: 1.50 V ± 5%
Video DAC Power Supply AC Specification:
+/- 0.3% from 0.10 Hz to 10 MHz
+/- 0.95% from 10 MHz to max pixel clock frequency
Absolute minimum voltage at the VCCA package ball = 1.40 V
Please refer to the Intel® 852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet for
AC/CD specification.
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7.1.6.
HSYNC and VSYNC Design Considerations
HSYNC and VSYNC signals are connected to the analog display attached to the VGA connector. These
are 3.3-V outputs from the GMCH. Some monitors have been found to drive HSYNC and VSYNC
signals during reset. Because these signals are used as straps on the 852GME, the GMCH can enter an
illegal state under these conditions. In order to prevent these signals from being driven to the GMCH
during reset, system designers must ensure the GMCH is isolated from any monitor driving HSYNC or
VSYNC while PCI_RST# is active. Appropriate logic is required between the GMCH and the VGA
connector (both the on-board VGA connector and the VGA connector at the docking station) to
accomplish this.
Intel’s recommended option is to use an analog switch (i.e. discrete FET, Q-buffer) to switch these
signals between the on-board VGA connector and the docking connector. In this case, footprints for a
series resistor and an optional capacitor are needed on each of these signals to meet the VESA electrical
specifications for video signals. Resistor and capacitor values of 39 Ω and 33 pF respectively are used
on the CRB. These values were calculated based on the GMCH buffer strength and board routing.
Customers are recommended to perform a signal integrity check specific to their board topology to
determine the appropriate resistor and capacitor values for their platforms.
An alternative option is to use a unidirectional buffer on each of these signals. For each of the HSYNC
and VSYNC signals, a footprint for a series resistor must be placed between the GMCH and the
unidirectional buffer to prevent excessive overshoot and undershoot at the input of the buffer.
Consideration should also be taken in designing the filter circuit on the output of these buffers to ensure
that the VESA electrical specifications for video signals are met at both the on-board VGA connector as
well as on the docking station. Customers are strongly encouraged to perform complete signal integrity
validation at the input of the buffer and at the VGA connectors.
7.1.7.
DDC and I2C Design Considerations
DDCADATA and DDCACLK are 3.3-V IO buffers connecting the GMCH to the monitor. If higher
signaling voltage (5 V) is required by the monitor, level shifting devices may be used. Pull-up resistors
of 2.2-k (or of the appropriate value derived from simulation) are required on each of these signals.
7.2.
LVDS Transmitter Interface
The Intel LVDS (Low Voltage Differential Signaling) transmitter serializer converts up to 24 bits of
parallel digital RGB data, (8 bits per RGB), along with up to 4 bits for control (SHFCLK, HSYNC,
VSYNC, DE) into 2, 4 channel serial bit streams, for output by the LVDS transmitter.
The transmitter is fully differential and utilizes a current mode drive with a high impedance output. The
drive current develops a differential swing in the range of 250 mV to 450 mV across a 100termination load.
The parallel digital data is serially converted to a 7-bit serial bit stream that is transmitted over the 8
channel LVDS interface at 7x the input clock. The differential output clock channel transmits the output
clock at the input clock frequency. While the differential output channels transmit the data at the 7x
clock rate (1 bit time is 7x the input clock). The 7x serializer will synchronize and regenerate and input
clock from 35 MHz to 112 MHz. Typical operation is at 65 MHz (15.4 ns), therefore, at a 7x clock rate,
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1 bit time would be 2.2 ns. With data cycle times as small as 2.2 ns, propagation delay mismatch is
critical, such that intra-channel skew (skew between the inverting and non-inverting output) must be
kept minimal.
LIBG pin is a current reference on the LVDS interface. A 1.5-k
platform is being used with external graphics only option.
pull down is required unless 855GME
The following differential signal groups comprise the LVDS Interface. The topology rules for each
group are defined in subsequent sections.
Table 34. Signal Group and Signal Pair Names
Channel
Signal Group
Signal Pair Names
Channel A
Clocks
ICLKAM, ICLKAP
Data Bus
IYAM[3:0], IYAP[3:0]
Clocks
ICLKBM, ICLKBP
Data Bus
IYBM[3:0], IYBP[3:0]
Channel B
7.2.1.
LVDS Length Matching Constraints
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group. These recommendations are provided to achieve optimal SI and timing. In addition
to the absolute length limits provided, more restrictive length matching requirements are also provided.
The additional requirements further restrict the minimum to maximum length range of each signal group
with respect to clock strobe, as required to guarantee adequate timing margins.
7.2.2.
LVDS Package Length Compensation
As mentioned in Section 7.2.1, all length matching is done from GMCH die-pad to LVDS connector
pin. The reason for this is to compensate for the package length variation across each signal group in
order to minimize timing variance. The GMCH does not equalize package lengths internally as some
previous GMCH components have, and therefore, the GMCH requires a length matching process. See
Table 36 for the GMCH LVDS package lengths information.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the minimum and maximum length bounds of a signal
group based on clock length, whereas package length compensation refers to the process of
compensating for package length variance across a signal group. There is of course some overlap in that
both affect the target length of an individual signal. Intel recommends that the initial route be completed
based on the length matching formulas in conjunction with nominal package lengths and that package
length compensation be performed as secondary operation.
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7.2.3.
LVDS Routing Guidelines
Each LVDS channel is required to be length matched to within ± 20 mils of the LVDS clock strobe
signals. The two complementary signals in each clock strobe pair, as well as in each data pair, are also
required to be length matched to within ± 20 mils of each other. See Table 35 for summary of LVDS
signal group routing guidelines.
Table 35. LVDS Signal Group Routing Guidelines
Parameter
Signal Group
LVDS
Topology
Differential Pair Point to Point
Reference Plane
Ground Referenced
Differential Mode Impedance (Zdiff)
100
Nominal Trace Width
4 mils
Nominal Pair Spacing (edge to edge)
7 mils
Minimum Pair to Pair Spacing
(see exceptions for breakout region below)
20 mils
Minimum Serpentine Spacing
20 mils
Minimum Spacing to Other LVDS Signals
(see exceptions for breakout region below)
20 mils
Minimum Isolation Spacing to non-LVDS Signals
20 mils
Maximum Via Count
2 (per line)
Package Length Range
± 15%
550 mils ± 150mils
(See LVDS package length Table 36 for exact lengths)
Total Length
Max 10”
Data to Clock Length Matching
Match all segments to within ± 20 mils of associated clock pair
Clock to Clock# Length Matching (Total Length)
Match clocks to ± 20 mils
Data to Data# Length Matching (Total Length)
Match data to ± 20 mils
Breakout Exceptions
Breakout section should be as shorter as possible. Try to
maintain trace width as 4 mils, spacing 7 mils, while the spacing
between pairs can be 10-20 mils.
(Reduced geometries for GMCH breakout region)
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The traces associated with the LVDS transmitter timing domain signals are differential traces terminated
across 100 ± 15 % and should be routed as:
Strip-line only.
Isolate all other signals from the LVDS signals to prevent coupling from other sources onto the
LVDS lines.
Use controlled impedance traces that match the differential impedance of your transmission
medium (i.e. cable) and termination resistor
Run the differential pair trace lines as close together as possible as soon as they leave the IC, not
greater than 10 mils. This will help eliminate reflections and ensure noise is coupled as common
mode. Plus, noise induced on the differential lines is much more likely to appear as common mode,
which is rejected by the receiver.
The LVDS transmitter timing domain signals have a maximum trace length of 10.0 inches. This
maximum applies to all of the LVDS Transmitter signals.
Traces must be ground referenced and must not switch layers between the GMCH and connector.
When choosing cables, it is important to remember:
Use controlled impedance media. The differential impedance of cable LVDS uses should be 100
± 15%. Cables should not introduce major impedance discontinuities that cause signal reflection.
Balanced cables (twisted pair) are usually better than unbalanced cables (ribbon cable, multiconductor) for noise reduction and signal quality.
Cable length must be less than 16 inches.
Table 36. LVDS Package Lengths
GMCH Signal
Name
Package Trace
Length (mils)
503.7
ICLKAP
502.0
ICLKAM
498.8
ICLKAM
499.1
IYAP0
399.6
IYBP0
359.8
IYAM0
385.4
IYBM0
353.7
CHANNEL
IYAP1
487.5
CHANNEL
IYBP1
524.7
A
IYAM1
466.2
B
IYBM1
516.6
IYAP2
572.6
IYBP2
623.3
IYAM2
566.2
IYBM2
604.2
IYAP3
643.2
IYBP3
441.8
IYAM3
637.8
IYBM3
441.7
Signal Group
GMCH Signal
Name
Package Trace
Length (mils)
ICLKAP
Signal Group
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7.3.
Digital Video Out Port
The 852GME GMCH digital video out (DVO) port interface supports a wide variety of third party DVO
compliant devices (e.g. TV encoder, TMDS transmitter or integrated TV encoder and TMDS
transmitter).The 852GME has two dedicated DVO’s (DVOB and DVOC). Intel’s DVO port is a 1.5-V
only interface that can support transactions up to 165 MHz. Some of the DVO port command signals
may require voltage translation circuit depending on the third party device.
7.3.1.
DVO Interface Signal Groups
7.3.1.1.
DVOB Interface Signals
Input Signals
DVOBFLDSTL
Output Data Signals
DVOBHSYNC
DVOBVSYNC
DVOBBLANK#
DVOBD[11:0]
Output Strobe Signals
DVOBCLK (DVOBCLK[0])
DVOBCLK# (DVOBCLK[1])
7.3.1.2.
DVOC Interface Signals
Input Signals
DVOCFLDSTL
Output Data Signals
DVOCHSYNC
DVOCVSYNC
DVOCBLANK#
DVOCD[11:0]
Output Strobe Signals
DVOCCLK (DVOCCLK[0])
DVOCCLK# (DVOCCLK[1])
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7.3.1.3.
Common Signals for Both DVO Ports
Input Signals
DVOBCCLKINT
DVOBCINTR#
ADDID[7:0]
DVODETECT
Voltage References, PLL Power Signals
DVORCOMP
GVREF
7.3.2.
DVOB and DVOC port Interface Routing Guidelines
For 852GME platforms, guidelines will apply for both interfaces.
7.3.2.1.
Length Mismatch Requirements
The routing guidelines presented in the following subsections define the recommended routing
topologies, trace width and spacing geometries, and absolute minimum and maximum routed lengths for
each signal group, which are recommended to achieve optimal SI and timing. In addition to the absolute
length limits provided in the individual guideline tables, more restrictive length matching requirements
are also provided which further restrict the minimum to maximum length range of each signal group
with respect to clock strobe, within the overall boundaries defined in the guideline tables, as required to
guarantee adequate timing margins. These secondary constraints are referred to as length matching
constraints. The amount of minimum to maximum length variance allowed for each group around the
clock strobe reference length varies from signal group to signal group depending on the amount of
timing variation, which can be tolerated. Refer to Table 37 for DVO length matching requirements.
Table 37. DVO Interface Trace Length Mismatch Requirements
Data Group
Signal Matching to
Strobe Clock
DVO Clock Strobes
Associated With the Group
Clock Strobe Matching
Notes
DVOBD [11:0]
± 100 mils
DVOBCLK[1:0]
± 10 mils
1,2
DVOCD [11:0]
± 100 mils
DVOCCLK[1:0]
± 10 mils
1,2
NOTE:
Data signals of the same group should be trace length matched to the clock within ±100 mil including
package lengths.
All length matching formulas are based on GMCH die-pad to DVO device pin total length. Package
length table are provided for all signals in order to facilitate this pad to pin matching.
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7.3.2.2.
Package Length Compensation
As mentioned in Section 7.3.2.1, all length matching is done from the GMCH die-pad to the DVO
connector pin. The reason for this is to compensate for the package length variation across each signal
group in order to minimize timing variance. The GMCH does not equalize package lengths internally as
some previous GMCH components have, and therefore, the GMCH requires a length matching process.
See Table 39 for the DVOB package lengths information and see Table 40 for DVOC package lengths
information.
Package length compensation should not be confused with length matching as discussed in the previous
section. Length matching refers to constraints on the minimum and maximum length bounds of a signal
group based on clock length, whereas package length compensation refers to the process of adjusting
out package length variance across a signal group. There is of course some overlap in that both affect
the target length of an individual signal. Intel recommends that the initial route be completed based on
the length matching formulas in conjunction with nominal package lengths and that package length
compensation be performed as secondary operation.
7.3.2.3.
DVOB and DVOC Routing Guidelines
Table 38 provides the DVOB and DVOC routing guideline summary.
Table 38. DVOB and DVOC Routing Guideline Summary
Parameter
120
Definition
Signal Group
DVOBD [11:0], DVCBD [11:0]
Motherboard Topology
Point to point
Reference Plane
Ground Referenced
Characteristic Trace Impedance (Zo)
55
Nominal Trace Width
Inner layers: 4 mils
Minimum Spacing to Trace Width Ratio
2 to 1 (e.g. 8 mil space to 4 mil trace)
Minimum Isolation Spacing to non-DVO Signals
20 mils
Minimum Spacing to Other DVO Signals
12 mils (see exceptions for breakout region below)
Minimum Spacing of DVOBCLK [1:0] or DVOCCLK
[1:0] to any other signals
12 mils
Package Length Range – P1
See Table 39 and Table 40 for package lengths.
Total Length –
Max 6”
Data to Clock Strobe Length Matching Requirements
+ 100 mils (See Table 37 for length matching requirements)
CLK0 to CLK1 Length Matching Requirements
+ 10 mils (See Table 37 for length matching requirements.)
± 15%
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The routing guideline recommendations in this section apply for both interfaces. Refer to Table 39 for
GMCH DVOB package lengths and Table 40 for GMCH DVOC package lengths. The DVO interface
signals are routed point to point as follows:
All signals should be routed as striplines (inner layers).
All signals in a signal group should be routed on the same layer. Routing studies have shown that
these guidelines can be met. The trace length and trace spacing requirements must not be violated
by any signal.
Route the DVOBCLK[1:0] or DVOCCLK[1:0] signal pairs 4 mils wide and 8 mils apart with a
max trace length of 6in. This signal pair should be a minimum of 12 mils from any adjacent
signals.
In order to break out of the 852GME GMCH, the DVOB and/or DVOC data signals can be routed
with a trace width of 4 mils and a trace spacing of 7 mils. The signals should be separated to a trace
width of 4 mils and a trace spacing of 8 mils within 0.3 inches of the GMCH component.
Table 39. DVOB Interface Package Lengths
Signal
Pin Number
Package Length (mils)
DVOBBLANK#
L2
583
DVOBCCLKINT
M3
520
DVOBCINTR#
G2
712
DVOBCLK
P3
475
DVOBCLK#
P4
439
DVOBD[0]
R3
489
DVOBD[1]
R5
439
DVOBD[2]
R6
343
DVOBD[3]
R4
415
DVOBD[4]
P6
409
DVOBD[5]
P5
387
DVOBD[6]
N5
466
DVOBD[7]
P2
553
DVOBD[8]
N2
568
DVOBD[9]
N3
504
DVOBD[10]
M1
611
DVOBD[11]
M5
510
DVOBFLDSTL
M2
566
DVOBHSYNC
T6
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Table 40. DVOC Interface Package Lengths
Signal
Pin Number
Package Length (mils)
DVOCBLANK#
L3
541
DVOCCLK
J3
601
DVOCCLK#
J2
675
DVOCD[0]
K5
489
DVOCD[1]
K1
692
DVOCD[2]
K3
622
DVOCD[3]
K2
685
DVOCD[4]
J6
536
DVOCD[5]
J5
518
DVOCD[6]
H2
720
DVOCD[7]
H1
771
DVOCD[8]
H3
649
DVOCD[9]
H4
625
DVOCD[10]
H6
521
DVOCD[11]
G3
762
DVOCFLDSTL
H5
566
DVOCHSYNC
K6
491
DVOCVSYNC
L5
440
7.3.2.4.
DVOB and DVOC Port Termination
The DVO interface does not require external termination.
7.3.3.
DVOB and DVOC Assumptions, Definitions, and Specifications
The source synchronous solution space consists of all designs in which the flight time mismatch
between a strobe and its associated data is less than the total allowable skew:
Tskew = Tflightdata - Tflightstrobe
Where Tflightdata and Tflightstrobe are the driver-pad-to-receiver-pin flight times of the data and the strobe
respectively.
The DVO physical interface is a point-to-point topology using 1.5-V signaling. The DVO uses a 165MHz clock.
The flight time skew simulations simulate all parameters that could cause a skew between two signals,
including motherboard and add-in card line lengths, effective capacitance in the buffer models, crosstalk
on each of the different interconnect combinations, data pattern dependencies, and ISI induced skews.
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7.3.4.
DVOB and DVOC Simulation Method
A model for simulation purposes is shown in Figure 43. The DVO component is a third party-chip.
Figure 43. DVOB and DVOC Simulations Model
tDVb, tDVa
tDSu, tDh
DVO I/F
DVO
(Device)
GMCH
DVOB/DVOC
Control, Data
Figure 44. Driver-Receiver Waveforms Relationship Specification
Driver
Strobe
Driver
Data
Data2
Data1
tDVb
Data3
Data4
tDVa
Clock Delay
Data Delay
Receiver
Strobe
Receiver
Data
Data1
tDSu
Data2
Data3
Data4
tDh
The setup margin and the hold margin for a particular design depends on the values of the data valid
times and the data setup and hold times on both the driver and the receiver sides. However, note that
available margins are not absolute values. Any skew due to routing and loading differences, any
coupling differences in the parallel traces, and any effects of SSO (ISI, ground bounce, etc.) should be
accounted for in the timing budget as they will reduce the total available margin for the design.
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Table 41. Allowable Interconnect Skew Calculation
Component
Skew Element
Driver
Data Valid before Strobe
tDVb
Data Valid after Strobe
tDVa
Interconnect
Allowable Skew
Receiver
Data Setup to Strobe
Symbol
7.4.
Hold
570
tDSu
Units
ps
TBD
Data Hold from Strobe
NOTE:
Setup
770
ps
TBD
ps
TBD
ps
tDh
TBD
ps
All numbers in this table are from the 852GME GMCH specification documents that are applicable for this
interface. For third party receiver devices, please refer to appropriate third party vendor specifications.
DVOB and DVOC port Flexible (Modular) Design
The GMCH supports flexible design interfaces described in this section.
7.4.1.
DVOB and DVOC Module Design
The 852GME GMCH supports a DVO module design connected to the GMCH through a generic
connector. Simulation method is the same as in Section 7.3.4. Lengths L1 and L2 are determined by
simulation as L1= 4 inches and L2= 2 inches. Refer to Figure 46 for the generic connector parasitic
model.
Figure 45. DVO Enabled Simulation Model
DVOB &
DVOC I/F
GMCH
L1
L2
tDVb, tDVa tDVb, tDVa,
tDSu, tDh tDSu, tDh
Connector
with
DVO
module
Generic
Connector
All signals should be routed as striplines (inner layers).All signals in a signal group should be routed on
the same layer. Routing studies have shown that these guidelines can be met. The trace length and trace
spacing requirements must not be violated by any signal. Trace length mismatch for all signals within a
signal group should be as close to ± 100 mils with respect to the strobe clocks as possible to provide
optimal timing margin.
Table 42 shows DVO enabled routing guideline summary.
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Table 42. DVO Enabled Routing Guideline Summary
Signal
Maximum
Length
Trace Width
Trace Spacing
Length
Mismatch
DVO Timing
Domain
L1=4 in
4 mils
8 mils
± 100 mils
Notes
L2=2 in
For DVO module case, the simulation model is the same as Figure 45 and the routing guideline is the
same as in
Table 42; each strobe pair must be separated from other signals by at least 12 mils. For multiplexed
design, more conservative length mismatch (± 0.1 inches) is adopted.
7.4.1.1.
Generic Connector Model
Figure 46 shows the generic connector model used in simulation for flexible DVO implementation.
This is only for reference. Actual connector may have different parasitic values. Designs using this
approach need to be simulated first.
Figure 46. Generic Module Connector Parasitic Model
Motherboard
C1
7.5.
R
L
20mΩ
2.5nH
2.21 pF
Module
C2
2.21 pF
DVO GMBUS and DDC Interface Considerations
The GMCH DVOB and/or DVOC port controls the video front-end devices via the GMBUS (I2C)
interface. DDCADATA and DDCACLK should be connected to the CRT connector. The GMBUS
should be connected to the DVO device, as required by the specifications for those devices. The
protocol and bus may be used to configure registers in the TV encoder, TMDS transmitter, or any other
external DVI device. The GMCH also has an option to utilize the DDCPCLK and DDCPDATA to
collect EDID (Extended Display Identification) from a digital display panel.
Pull-ups (or pull-ups with the appropriate value derived from simulating the signal) typically ranging
from 2.2 k to 10 k are required on each of these signals.
The following GMCH signal groups list the five possible GMBUS pairs.
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Table 43. GMBUS Pair Mapping and Options
Pair
#
Signal Name
0
DDCADATA
Buffer
Type
LCLKCTRLA
DDC for Analog monitor (CRT)
connection.
This can not be shared with other
DDC or I2C pairs due to legacy
monitor issues.
3.3 V
For control of SSC clock generator
devices down on motherboard.
If SSC is not supported then can
be used for DVOB or DVOC
GMBUS.
3.3 V
DDC for Digital Display connection via
the integrated LVDS display port for
support for EDID panel.
If EDID panels are not supported.
Can optionally use as GMBUS
for DVOB or DVOC.
1.5 V
GMBUS control of DVI devices (TMDS
or TV encoder)
Can optionally use as GMBUS
for DVOB or DVOC.
1.5 V
GMBUS control of DVI devices (TMDS
or TV encoder)
Can optionally use as GMBUS
for DVOB or DVOC.
1.5 V
DDC for Digital Display connection via
TMDS device
Can optionally use as GMBUS
for DVOB or DVOC.
LCLKCTRLB
DDCPDATA
2
DDCPCLK
MDVIDATA
3
MDVICLK
MI2CDATA
4
MI2CCLK
MDDCDATA
5
MDDCCLK
NOTE:
Notes
3.3 V
DDCACLK
1
Description
All GMBUS pairs can be optionally programmed to support any interface and is programmed through the
BMP utility.
If any of GMBUS pairs (expect DDCADATA/DDCCLK for CRT) are not used, 2.2 k – 100 k pull-up
(or pull-ups with the appropriate value derived from simulating the signal), resistors are required except
for LCLKCTRLA/LCLKCTRLB GMBUS pair. This will prevent the GMCH DVOB interface from
confusing noise on these lines for false cycles.
7.5.1.
Leaving the GMCH DVOB or DVOC Port Unconnected
If the motherboard does not implement any of the possible video devices with the DVO port, please
follow the guidelines recommended on the motherboard. DVO Output signals may be left unconnected
if they are not used.
Pull-down resistors are required for the following signals if not used:
DVOBFLDSTL
DVOCFLDSTL
DVOBCCLKINT
Pull-up resistors are required for the following signals if not used:
DVOBCINTR#
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7.6.
Miscellaneous Input Signals and Voltage Reference
ADDID[7]: Pulldown to ground with a 1-k resistor when using the DVOB or DVOC port. This
is a VBIOS strapping option to load the TPV AIM module for DVOB and DVOC port. Pulldown
not required if DVOB or DVOC is not enabled.
ADDID[6:0]: Leave unconnected (NC).
DVODETECT: Leave unconnected (NC) when using the DVOB or DOVC port.
AGPBUSY#: Connect directly to ICH4-M. A 10-k, pullup resistor is required, unless using 852PM
platform or 852GME platform with external graphics
DVORCOMP is used to calibrate the DVOB buffers. It should be connected to ground via a
40.2resistor using a routing guideline of 10-mil trace and 20-mil spacing.
DPMS: connects to 1.5 V version of the ICH4-M’s SUSCLK or a clock that runs during S1.
GVREF: Reference voltage for the DVOB and DVOC input buffers. Refer to the figure below for
proper signal conditioning.
Figure 47. GVREF Reference Voltage
+V1.5S
1 KΩ 1%
GVREF (to DVO device)
0.1 µF
GVREF(to GMCH)
1 KΩ 1%
0.1 µF
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8.
AGP Port Design Guidelines
For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest
AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org.
8.1.
AGP Interface
The852GME/852GMV/852PMAGP buffers operate in only one mode: 1.5-V drive, not 3.3-V safe. This
mode is compliant with the AGP 2.0 Specification.
AGP 4X, 2X and 1X must operate at 1.5 V. The AGP interface supports up to 4X AGP signaling. AGP
semantic cycles to DRAM are not snooped on the host bus.
The MCH/GMCH supports PIPE# or SBA [7:0] AGP address mechanisms, but not both simultaneously.
Either the PIPE# or the SBA [7:0] mechanism must be selected during system initialization.
The AGP interface is clocked from a 66-MHz clock. The AGP interface is asynchronous to the host bus,
system memory, and internal graphics device. When AGP interface has been enabled, the internal
graphics will be disabled using GMCH strapping option. The AGP interface is synchronous to the hub
interface with a clock ratio of 1:1 (66 MHz : 66 MHz).
The GMCH multiplexes the AGP signal interface with two DVO ports. These DVO ports are capable of
supporting a variety of digital display devices such as TMDS transmitters and TV-Out encoders. It is
possible to use the DVO ports in dual-channel mode to support higher resolutions and refresh rates
(single channel mode is limited to a 165-MHz pixel clock rate).
8.1.1.
AGP 2.0
The AGP Interface Specification, Revision 2.0, enhances the functionality of the original AGP Interface
Specification, Revision 1.0, by allowing 4X data transfers (i.e., 4 data samples per clock), and 1.5-volt
operation. The 4X operation of the AGP interface provides for "quad-pumping" of the AGP AD
(address/data) and SBA (side-band addressing) buses. That is, data is sampled four times during each
66-MHz AGP clock. This means that each data cycle is ¼ of a 15-ns (66-MHz) clock or 3.75 ns. It is
important to understand that 3.75 ns is the data cycle time, not the clock cycle time. During 2X
operation, data is sampled twice during a 66-MHz clock cycle.
Therefore, the data cycle time is 7.5 ns. To allow for these high-speed data transfers, the 2X mode of
AGP operation uses source-synchronous data strobing. During 4X operation, the AGP interface uses
differential source-synchronous strobing.
With data cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is
critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on
the data lines will cause the settling time to be long. If the mismatch between a data line and the
associated strobe is too great, or if there is noise on the interface, incorrect data will be sampled. The
low-voltage operation on AGP (1.5 V) requires even more noise immunity.
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8.1.2.
AGP Interface Signal Groups
The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X/4X timing
domain signals, and miscellaneous signals. Each group has different routing requirements.
In addition, within the 2X/4X timing domain signals, there are three sets of signals. All signals in the
2X/4X timing domain must meet minimum and maximum trace length requirements, as well as trace
width and spacing requirements. Because of the multiplexed AGP/DVO interface, there are trace length
matching requirements within each set of 2X/4X signals, as well as between sets of 2X/4X signals. The
signal groups are listed in following table.
Table 44. AGP 2.0 Signal Groups
1X Signals
2X signals
4X Signals
CLK (3.3 V)
2X signals include all 1X signals and:
4X signals include all 1X signals and:
GRBF#
GADSTB_[1:0]
GADSTB_[1:0]
GWBF#
GSBSTB
GADSTB_[1:0]#
GST_[2:0]
GAD_[31:0] signals and associated
GC/BE_[3:0]# signals are running at 2X
mode.
GSBSTB
GPIPE#
GREQ#
GGNT#
GSBSTB#
GAD_[31:0] signals and associated
GC/BE_[3:0]# signals are running at 4X
mode.
GPAR
GFRAME#
GIRDY#
GTRDY#
GSTOP#
GDEVSEL#
GAD_[31:0]
GC/BE_[3:0]#
GADSTB_[1:0]
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Table 45. AGP 2.0 Data/Strobe Associations
Data
Associated Strobe in 1X
Associated
Strobe in 2X
Associated Strobes
in 4X
AD[15:0] and C/BE[1:0]#
Strobes are not used in 1X
mode. All data is sampled on
rising clock edges.
AD_STB0
AD_STB0,
AD_STB0#
AD[31:16] and C/BE[3:2]#
Strobes are not used in 1X
mode. All data is sampled on
rising clock edges.
AD_STB1
AD_STB1,
AD_STB1#
SBA[7:0]
Strobes are not used in 1X
mode. All data is sampled on
rising clock edges.
SB_STB
SB_STB, SB_STB#
The routing guidelines for each group of signals (1X timing domain signals, 2X/4X timing domain
signals, and miscellaneous signals) will be addressed separately.
8.2.
AGP Routing Guidelines
8.2.1.
1x Timing Domain Routing Guidelines
8.2.1.1.
Trace Length Requirements for AGP 1X
This section contains information on the 1X timing domain routing guidelines. The AGP 1X timing
domain signals (refer to Table 46) have a maximum trace length of 10 inches. The target impedance is
55- ± 15%. This maximum applies to ALL of the signals listed as 1X timing domain signals in Table
46. In addition to this maximum trace length requirement (refer to Table 46 and Table 47) these signals
must meet the trace spacing and trace length mismatch requirements in Sections 8.2.1.2 and 8.2.1.3.
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Table 46. Layout Routing Guidelines for AGP 1X Signals
1X signals
Max. Length (inches)
Width (mils)
Space (mils)
CLK_AGP_SLT
10
4
4
AGP_PIPE#
10
4
4
AGP_RBF#
10
4
4
AGP_WBF#
10
4
4
AGP_ST[2:0]
10
4
4
AGP_FRAME#
10
4
4
AGP_IRDY#
10
4
4
AGP_TRDY#
10
4
4
AGP_STOP#
10
4
4
AGP_DEVSEL#
10
4
4
AGP_REQ#
10
4
4
AGP_GNT#
10
4
4
AGP_PAR
10
4
4
8.2.1.2.
Trace Spacing Requirements
AGP 1X timing domain signals (refer to Table 46) can be routed with 4-mil minimum trace separation.
8.2.1.3.
Trace Length Mismatch
There are no trace length mismatch requirements for 1X timing domain signals. These signals must meet
minimum and maximum trace length requirements.
8.2.2.
2x/4x Timing Domain Routing Guidelines
8.2.2.1.
Trace Length Requirements for AGP 2X/4X
These trace length guidelines apply to ALL of the signals listed as 2X/4X timing domain signals in
Table 47. In addition to these maximum trace length requirements, these signals must meet the trace
spacing and trace length mismatch requirements in Sections 8.2.2.2 and 8.2.2.3.
The maximum line length and mismatch requirements are dependent on the routing rules used on the
motherboard. These routing rules were created to give design freedom by making tradeoffs between
signal coupling (trace spacing) and line lengths. These routing rules are divided by trace spacing. In 1:2
spacing, the distance between the traces is two times the width of traces.
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Figure 48. AGP Layout Guidelines
(Width:Space)
1:2 Strobe to Strobe# Routing
1:3 Strobe to Data Routing
GMCH
+/-
1:2 routing
6.0” max length
0.1” mismatch to
associated strobe
AGP
Controller
For 2X/4X lines in AGP interface, the max length is 6.0 inches (pin to pin) and 1:2 trace spacing is
required. 2X signals must be matched to their associated strobe within 0.1 inch. 4X signals must be
matched to both of their associated strobes within 0.1 inch. Reduce line length mismatch to ensure
added margin.
8.2.2.2.
Trace Spacing Requirements
AGP 2X/4X timing domain signals (refer to Table 47) must be routed as documented in Table 47. They
should be routed using 4-mil traces. Additionally, the signals can be routed with 5-mil spacing when
breaking out of the GMCH/MCH. The routing must widen to the requirement in Table 48 within 0.3
inches of the GMCH/MCH package.
Since the strobe signals (AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, SB_STB, and SB_STB#) act
as clocks on the source synchronous AGP interface, special care should be taken when routing these
signals. Because each strobe pair is truly a differential pair, the pair should be routed together (e.g.
AD_STB0 and AD_STB0# should be routed next to each other). The two strobes in a strobe pair should
be routed on 4-mil traces with 8 mils of space (1:2) between them. This pair should be separated from
the rest of the AGP signals (and all other signals) by at least 15 mils (1:3). The strobe pair must be
length matched to less than ± 0.1 inches (that is, a strobe and its compliment must be the same length
within ± 0.1 inches).
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Table 47. Layout Routing Guidelines for AGP 2X/4X Signals
Maximum
Length (inch)
Signal
Trace Space
(mils)
(4 mil traces)
Length
Mismatch
(inch)
Relative To
Notes
2X/4X Timing
Domain Set#1
6
8
± 0.1
AGP_ADSTB0 and
AGP_ADSTB0#
AGP_ADSTB0,
AGP_ADSTB0# must
be the same length (±10
mils)
2X/4X Timing
Domain Set#2
6
8
± 0.1
AGP_ADSTB1 and
AGP_ADSTB1#
AGP_ADSTB1,
AGP_ADSTB1# must
be the same length (±10
mils)
2X/4X Timing
Domain Set#3
6
8
± 0.1
AGP_SBSTB and
AGP_SBSTB #
AGP_SBSTB,
AGP_SBSTB# must be
the same length (±10
mils)
8.2.2.3.
Trace Length Mismatch Requirements
Table 48. AGP 2.0 Data Lengths Relative to Strobe Length
Max Trace Length
Trace Spacing
Strobe Length
Min Trace Length
Max Trace Length
< 6 in
1:2
X
X – 0.1 in
X + 0.1 in
The trace length minimum and maximum (relative to strobe length) should be applied to each set of
2X/4X timing domain signals independently. If AD_STB0 is 5 inches and ADSTB0# is 5.01 inches,
then AD[15:0] and C/BE[1:0] must be between 4.91 inches and 5.1 inches. However, AD_STB1 and
ADSTB1# can be 3.5 inches and 3.51 inches (and therefore AD[31:16] and C/BE#[3:2] must be
between 3.41 inches and 3.6 inches). In addition, all 2X/4X timing domain signals must meet the
maximum trace length requirements.
All signals should be routed as strip lines (inner layers).
All signals in a signal group should be routed on the same layer. Routing studies have shown that
these guidelines can be met. The trace length and trace spacing requirements must not be violated
by any signal. Trace length mismatch for all signals within a signal group should be as close to 0
inches as possible to provide optimal timing margin.
The strobe pair must be length matched to less than ± 0.01 inches (that is, a strobe and its compliment
must be the same length within ± 0.01 inches).
Table 49 shows the AGP 2.0 routing summary.
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Table 49. AGP 2.0 Routing Guideline Summary
Maximum
Length
Trace
Spacing
(4 mil
traces)
Length Mismatch
Relative To
Notes
1X Timing Domain
10 in
4 mils
No Requirement
N/A
None
2X/4X Timing
Domain Set#1
6 in
8 mils
± 0.1 in
AD_STB0 and
AD_STB0#
AD_STB0, AD_STB0#
must be the same
length
2X/4X Timing
Domain Set#2
6 in
8 mils
± 0.1 in
AD_STB1 and
AD_STB1#
AD_STB1, AD_STB1#
must be the same
length
2X/4X Timing
Domain Set#3
6 in
8 mils
± 0.1 in
SB_STB and
SB_STB#
SB_STB, SB_STB#
must be the same
length
Signal
8.2.3.
AGP Clock Skew
The maximum total AGP clock skew, between the GMCH/MCH and the graphics component, is 1 ns for
all data transfer modes. This 1 ns includes skew and jitter, which originates on the motherboard, add-in
module (if used), and clock synthesizer. Clock skew must be evaluated not only at a single threshold
voltage, but also at all points on the clock edge that falls in the switching range. The 1 ns skew budget is
divided such that the motherboard is allotted 0.9 ns of clock skew (the motherboard designer shall
determine how the 0.9 ns is allocated between the board and the synthesizer).
8.2.4.
AGP Signal Noise Decoupling Guidelines
The main focus of these guidelines is to minimize signal integrity problems on the AGP interface of the
Intel chipset GMCH/MCH. The following guidelines are not intended to replace thorough system
validation on Intel chipset-based products.
A minimum of six 0.01-µF capacitors are required and must be as close as possible to the MCH-M.
These should be placed within 70 mils of the outer row of balls on the GMCH/MCH for VDDQ
decoupling. Ideally, this should be as close as possible.
The designer should evenly distribute placement of decoupling capacitors in the AGP interface
signal field.
Intel recommends that the designer use a low-ESL ceramic capacitor, such as with a 0603 bodytype X7R dielectric.
In order to add the decoupling capacitors within 70 mils of the GMCH/MCH and/or close to the
vias, the trace spacing may be reduced as the traces go around each capacitor. The narrowing of
space between traces should be minimal and for as short a distance as possible (1.0 inch max.).
In addition to the minimum decoupling capacitors, the designer should place bypass capacitors at vias
that transition the AGP signal from one reference signal plane to another. One extra 0.01 uF capacitor
per 10 vias is required. The capacitor should be placed as close as possible to the center of the via field.
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8.2.5.
AGP Interface Package Lengths
Table 50. AGP Interface Package Lengths
Signal
Pin
Number
Package
Length (mils)
Signal
Pin
Number
Package
Length (mils)
GAD0
T6
339
GADSTB_0
P3
475
GAD1
T5
362
GADSTBB_0
P4
439
GAD2
R5
440
GADSTB_1
J3
601
GAD3
R3
489
GADSTBB_1
J2
675
GAD4
R4
415
GSBA_0
E5
686
GAD5
R6
343
GSBA_1
F5
617
GAD6
P5
387
GSBA_2
E3
738
GAD7
P6
409
GSBA_3
E2
865
GAD8
N5
466
GSBA_4
G5
668
GAD9
N3
504
GSBA_5
F4
688
GAD10
N2
568
GSBA_6
G6
518
GAD11
M5
510
GSBA_7
F6
613
GAD12
M1
611
GSBSTB
F2
799
GAD13
M3
520
GSBSTBB
F3
761
GAD14
M2
566
GPIPEB
D5
644
GAD15
T7
296
GCBEB_0
P2
553
GAD16
L5
440
GCBEB_1
L2
583
GAD17
K6
491
GCBEB_2
L4
515
GAD18
L3
541
GCBEB_3
J5
518
GAD19
K5
489
GST_0
C4
750
GAD20
K1
692
GST_1
C3
797
GAD21
K3
622
GST_2
C2
856
GAD22
K2
685
GRBFB
D3
962
GAD23
J6
536
GWBFB
D2
947
GAD24
H1
772
GFRAMEB
M6
486
GAD25
H2
720
GIRDYB
K7
751
GAD26
H4
625
GTRDYB
N7
350
GAD27
H3
649
GSTOPB
P7
423
GAD28
G3
762
GDEVSELB
N6
399
GAD29
H6
521
GREQB
B3
762
GAD30
G2
712
GGNTB
B2
849
GAD31
H5
566
GPAR
L7
623
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8.2.6.
AGP Routing Ground Reference
Intel strongly recommends that at least the following critical signals be referenced to ground from the
MCH and GMCH to an AGP controller connector using a minimum number of vias on each net:
AD_STB0
AD_STB0#
AD_STB1
AD_STB1#
SB_STB
SB_STB#
G_TRDY#
G_IRDY#
G_GNT#
ST[2:0].
8.2.7.
Pull-ups
The AGP 2.0 Specification requires AGP control signals to have pull-up resistors to VDDQ to ensure
they contain stable values when no agent is actively driving the bus. Also, the AD_STB[1:0]# and
ST_STB# strobes require pull-down resistors to GND. The Intel 852GME/852GMV/852PMchipset
MCH/GMCH has integrated many of these pull-up/pull-down resistors on the AGP interface and a few
other signals not required by the AGP 2.0 Specification. Pull-ups are allowed on any signal except
AD_STB[1:0]# and SB_STB#.
The Intel chipset GMCH has no support for the PERR# and SERR# pins of an AGP graphics controller
that supports PERR# and SERR#. Pull-ups to a 1.5-V source are required down on the motherboard in
such cases.
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Table 51. AGP Pull-Up/Pull-Down Requirements and Straps
Signal
AGP 2.0 Signal Pull-Up/
Pull-Down Requirements
MCH-M Integrated Pull-Up/
Pull-Down
DEVSEL#
Pull-Up
FRAME#
Pull-Up
GNT#
Pull-Up
Notes
INTA#
Pull-Up
3, 5
INTB#
Pull-Up
3, 5
IRDY#
Pull-Up
PERR#
Pull-Up
2
PIPE#
Pull-Up
RBF#
Pull-Up
REQ#
Pull-Up
SERR#
Pull-Up
2
ST[2:0]
Pull-Down
STOP#
1
Pull-Up
4
Pull-Up
TRDY#
Pull-Up
WBF#
Pull-Up
AD_STB[1:0]
Pull-Up
AD_STB[1:0]#
Pull-Down
SB_STB
Pull-Up
SB_STB#
Pull-Down
SBA[7:0]
Pull-Up
1
NOTES:
1. The Intel chipset GMCH has integrated pull-ups to ensure that these signals do not float when there is no add-in
card in the connector.
2. The Intel chipset MCH-M does not implement the PERR# and SERR# signals. Pull-ups on the motherboard are
required for AGP graphics controllers that implement these signals.
3. The Intel chipset MCH does not implement interrupt signals. AGP graphics controller’s INTA# and INTB#
signals must but routed to the system PCI interrupt request handler where the pull-up requirement should be
met as well. For 852GME/PM /ICH4-M chipset-based systems, they can be routed to the ICH4-M’s PIRQ
signals that are open drain and require pull-ups on the motherboard.
4. ST[1:0] provide the strapping options for 100-MHz FSB operation and DDR memory, respectively.
5. INTA# and INTB# should be pulled to 3.3 V, not VDDQ.
6. The pull-up/pull-down resistor value requirements are shown in Table 52.
Table 52. AGP 2.0 Pull-up Resistor Values
Rmin
Rmax
4k
16 k
The recommended AGP pull-up/pull-down resistor value is 8.2 k .
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8.2.8.
AGP VDDQ and VCC
AGP specifies two separate power planes: VCC and VDDQ. VCC is the core power for the graphics
controller and VDDQ is the interface voltage.
8.2.9.
VREF Generation for AGP 2.0 (2X and 4X)
8.2.9.1.
1.5-V AGP Interface (2X/4X)
The voltage divider networks consist of AC and DC elements. The reference voltage that should be
supplied to the Vref pins of the GMCH/MCH and the graphics controller is ½ * VDDQ. Two, 1-k ±
1% resistors can be used to divide VDDQ down to the necessary voltage level.
The Vref divider network should be placed as close to the AGP interface as is practical to get the benefit
of the common mode power supply effects. However, the trace spacing around the Vref signals must be
a minimum of 25 mils to reduce crosstalk and maintain signal integrity.
8.2.10.
AGP Compensation
The 852GME chipset MCH-M AGP interface supports resistive buffer compensation. For PCBs with
characteristic impedance of 55 , tie the GRCOMP pin to a 40.2 ± 1% pull-down resistor (to ground)
via a 10-mil wide, very short ( 0.5 inches) trace.
AGP Link:
http://www.intel.com/technology/agp/info.htm
AGP StressTool Link:
http://www.intel.com/technology/agp/downloads/agp_stress.htm
8.2.11.
PM_SUS_CLK/AGP_PIPE# Design Consideration
The following design consideration provides the option to support both AGP and DVO devices with one
ADD Connector. Refer to Figure 49 and customer reference schematics for more detail.
The GMCH expects either the PM_SUS_CLK signal from the ADD connector when there is a no AGP
device or the AGP_PIPE# signal when there is an AGP device. The AGP_TYPEDET# signal is driven
high when no AGP card is detected, allowing DPMS_CLK to be driven by PM_SUS_CLK. In the case
where an AGP card is detected, AGP_TYPE# signal goes high which allows DMPS_CLK to be driven
by AGP_PIPE#.
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Figure 49. DPMS Circuit
Q6D2
BSS138
PM_SUS_CLK
19,37
3
Q6D1
BSS138
2
AGP_PIPE#_FET
2
3
DPMS_CLK 7
R6D7
8
1
+V12S 17,23,27,37,45
1
DPMS_CLK
100K
AGP_TY PEDET#
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9.
Hub Interface
The GMCH and ICH4-M pin-map assignments have been optimized to simplify the hub interface
routing between these devices. Intel recommends that the hub interface signals be routed directly from
the GMCH to the ICH4-M with all signals referenced to VSS. Layer transitions should be kept to a
minimum. If a layer change is required, use only two vias per net and keep all data signals and
associated strobe signals on the same layer.
The hub interface signals are broken into two groups: data signals (HL) and strobe signals (HLSTB).
For the 11-bit hub interface, HL[10:0] are associated with the data signals while HLSTB and HLSTB#
are associated with the strobe signals.
Figure 50. Hub Interface Routing Example
HLSTB#/HLSTBF
HLSTB/HLSTBS
ICH4-M
GMCH
HL[10:0]
CLK66
CLK66
CLK408
9.1.
Hub Interface Compensation
This section documents the routing guidelines for the 11-bit hub interface using enhanced (parallel)
termination. This hub interface connects the ICH4-M to the GMCH. The ICH4-M should strap its
HLRCOMP pin to VCC=1.5 V, as summarized in Table 53. The 852GME chipset GMCH should strap its
HLRCOMP pin to VCC=1.5V as summarized in Table 53.
The trace impedance must equal 55
± 15%
Table 53. Hub Interface RCOMP Resistor Values
Component
140
Trace Impedance
HLCOMP Resistor
Value
HLCOMP Resistor Tied
to
ICH4-M
55
± 15%
48.7
± 1%
Vcc1_5
852GME/852PM
55
± 15%
37.4
± 1%
Vcc1_5
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9.2.
Hub Interface Data HL[10:0] and Strobe Signals
The hub interface HL[10:0] data signals should be routed on the same layer as hub interface Strobe
signals.
9.2.1.
HL[10:0] and Strobe Signals Internal Layer Routing
Traces should be routed 4 mils wide with 8 mils trace spacing (4 on 8) and 20 mils spacing from other
signals. In order to break out of the GMCH and ICH4-M packages, the HL[10:0] signals can be routed 4
on 7. The signal must be separated to 4 on 8 within 300 mils from the package.
The minimum HL[10:0] on board signal trace length is 1.5 inches, while the maximum is 6 inches. The
HL[10:0] signals must be matched within ± 100 mils of the HLSTB differential pair. There is no explicit
matching requirement between the individual HL[10:0] signals.
The hub interface strobe signals HLSTB and HLSTB# should be routed as a differential pair, 4 mils
wide with 8 mils trace spacing (4 on 8). The maximum length for strobe signals is 6 inches. Each strobe
signal must be the same length and each HL[10:0] signal must be matched to within ± 100 mils of the
strobe signals. All length matching should be done from GMCH die to the ICH4-M die. Refer to the
package length Table 54 and Table 55.
Table 54. Hub Interface Signals Internal Layer Routing Summary
Signal
Min
length
(inch)
Max
length
(inch)
Width
(mils)
Space
(mils)
HL[10:0]
1.5”
6”
4
8
HLSTB
1.5”
6”
4
8
Misma
tch
length
(mils)
Relative
To
Space
with other
signals
(mils)
± 100
Differential
HLSTB
pair
20
± 100
Data lines
20
HLSTB#
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HLSTB and
HLSTB# must
be ± 10 mils of
each other
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Table 55. Hub Interface Package Lengths for ICH4-M
Signal
Pin Number
Package Length (mils)
HUB_PD0
L19
551
HUB_PD1
L20
562
HUB_PD2
M19
552
HUB_PD3
M21
567
HUB_PD4
P19
599
HUB_PD5
R19
627
HUB_PD6
T20
623
HUB_PD7
R20
593
HUB_PD8
P23
668
HUB_PD9
L22
559
HUB_PD10
N22
682
HUB_PD11
K21
560
HUB_CLK
T21
605
HUB_PSTRB
P21
541
HUB_PSTRB#
N20
565
Table 56. Hub Interface Package Lengths for GMCH
142
Signal
Pin Number
Package Length (mils)
HL[0]
U7
281
HL[1]
U4
408
HL[2]
U3
476
HL[3]
V3
484
HL[4]
W2
551
HL[5]
W6
355
HL[6]
V6
328
HL[7]
W7
343
HL[8]
T3
499
HL[9]
V5
399
HL[10]
V4
457
GCLKIN
Y3
539
HLSTB
W3
504
HLSTB#
V2
548
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9.2.2.
Terminating HL[11]
The HL[11] signal exists on the ICH4-M but not the GMCH and is not used on the platform. HL[11]
must be pulled down to ground via a 56- resistor.
9.3.
Hub VREF/VSWING Generation/Distribution
The hub interface reference voltage (VREF) is used on both the GMCH (HLVREF) and the ICH4-M
(HIREF). The hub interface also has a reference voltage (VSWING) for the GMCH (PSWING) and the
ICH4-M (HI_VSWING), to control voltage swing and impedance strength of the hub interface buffers.
The VREF voltage requirements must be set appropriately for proper operation. See Table 57 for the
VREF and VSWING voltage specifications. Sections 9.3.1 to 9.3.4 provide details on the different
options for VREF and VSWING voltage divider circuitry requirements.
Table 57. Hub Interface VREF/VSWING Reference Voltage Specifications
9.3.1.
VREF
VSWING
HIREF (ICH4-M)
HLVREF (GMCH)
HI_VSWING (ICH4-M)
PSWING (GMCH)
350 mV +/- 8%
800 mV +/- 8%
NOTES
See Sections 9.3.1 to 9.3.4for recommendations for the
VREF/VSWING voltage generation circuitry. See Table 60 for
recommended resistor values.
Single Generation Voltage Reference Divider Circuit
The GMCH and ICH4-M may share the same single voltage divider circuit. This option provides one
voltage divider circuit to generate both VREF and VSWING reference voltage. The reference voltage
for both VREF and VSWING must meet the voltage specification in Table 57.
If the voltage specifications are not met, then an individual, locally generated, voltage divider circuit is
required. The maximum trace length from the GMCH to ICH4-M is 4 inches or less. The voltage divider
circuit should be place midway between the GMCH and ICH4-M. Normal precautions should be taken
to minimize crosstalk to other signals (< 10-15 mV). If the trace length exceeds 4 inches, then the
locally generated voltage reference divider should be used. See Section 9.3.2 for the more details.
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Figure 51. Single VREF/VSWING Voltage Generation Circuit for Hub Interface
VCCHI
R1
PSW ING
C1
GMCH
HLVREF
C2
C5
R2
C4
C6
C3
HI_VSW ING
ICH4-M
HIREF
R3
The resistor values, R1, R2, and R3 must be rated at 1% tolerance. See Table 59 for recommended
resistor values. The selected resistor values ensure that the reference voltage tolerance is maintained
over the input leakage specification. Two, 0.1-µF capacitors (C1 and C3) should be placed close to the
divider. In addition, the 0.01-µF bypass capacitor (C2, C4, C5, and C6) should be placed within
0.25 inches of HLVREF/VREF pin (for C4 and C6) and HI_VSWING pin (for C2 and C5).
Table 58. Recommended Resistor Values for Single VREF/VSWING Divider Circuit
Recommended Resistor Values
VCCHI
Option 1
R1 = 80.6
1%
R2 = 51.1
1%
R3 = 40.2
1%
1.5 V
Option 2
R1 = 255
1%
R2 = 162
1%
R3 = 127
1%
1.5 V
Option 3
R1 = 226
1%
R2 = 147
1%
R3 = 113
1%
1.5 V
C1 and C3 = 0.1 µF (near divider)
C2, C4, C5, C6 = 0.01 µF (near component)
9.3.2.
Locally Generated Voltage Reference Divider Circuit
This section describes the option to generate the voltage references separately for GMCH and ICH4-M,
to be used if the routing distance between GMCH and ICH4-M is greater than 4 inches. One voltage
divider circuit is used to generate both HIVREF and HI_VSWING voltage references for ICH4-M.
Another voltage divider circuit is used for GMCH. The reference voltage for both HIVREF and
HI_VSWING must meet the voltage specification in Table 59. The resistor values R1, R2, and R3 must
be rated at 1% tolerance (see Table 59). Normal care needs to be taken to minimize crosstalk to other
signals (< 10-15 mV). If the voltage specifications are not met then individually generated voltage
divider circuit for HIVREF and HI_VSWING is required.
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Figure 52. ICH4-M and GMCH Locally Generated Reference Voltage Divider Circuit
VCCHI
VCCH I
R1
R1
C5
C1
R2
PSW ING
R2
GMCH
C6
C3
C4
C3
HI_VSW ING
ICH4
HLVREF
R3
9.3.3.
C2
C1
HIREF
R3
Single GMCH and ICH4-M Voltage Generation / Separate
Divider Circuit for VSWING/VREF
This section describes the option to use one voltage divider circuit for VREF, shared by both ICH4-M
and GMCH, while using another voltage divider circuit for VSWING. This allows for tuning the two
reference voltages independently. The reference voltage for both HIVREF and HI_VSWING must meet
the voltage specification in Table 59. Normal care needs to be taken to minimize crosstalk to other
signals (< 10-15 mV).
Figure 53. Shared GMCH and ICH4-M Reference Voltage with Separate Voltage Divider Circuit for
VSWING and VREF
VCCHI=1.5V
R4
R4 = 43.2 Ω ± 1%,
R5 = 49.9 Ω ± 1%,
R6 = 78.7 Ω ± 1%,
R7 = 24.2 Ω ± 1%
R6
PVSWING
C1 and C3 = 0.1 µF
(near divider)
HI_VSWING
HLVREF
HIREF
GMCH
R5
C6
C5
R7
Intel®
ICH4
C2, C4, C5, C6 =
0.01µF (near
component)
C4
C3
C1
C2
Table 59. Recommended Resistor Values for Separate HIVREF and HI_VSWING Divider Circuits
Signal
Recommended Resistor Values
HIVREF
(350 mV)
R4 = 43.2
1%
R5 = 49.9
1%,
HI_VSWING
(800 mV)
R6 = 78.7
1%
R7 = 24.2
1%,
VCCHI
VCCHI=1.5 V
Capacitor value
C3 = 0.1 µF (near divider)
C2, C5 = 0.01 µF (near component)
VCCHI=1.5 V
C1 = 0.1 µF (near divider)
C4, C6 = 0.01 µF (near component)
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9.3.4.
Separate GMCH and ICH4-M Voltage Generation / Separate
Divider Circuits for VREF and VSWING
This option allows for tuning the voltage references HIVREF and HI_VSWING individually, for both
ICH4-M and GMCH. The reference voltage for both HIVREF and HI_VSWING must meet the voltage
specification in Table 60. Normal care needs to be taken to minimize crosstalk to other signals (< 10-15
mV).
Figure 54. Individual HIVREF and HI_VSWING Voltage Reference Divider Circuits for ICH4-M and
GMCH
VCCHI
VCCGMCH
R8
R4
R10
PSWING
R6
HI_VSWING
HLVREF
HIVREF
GMCH
R9
C6
C5
ICH4-M
R11
R5
C2
C3
C1
C4
R7
C3
C1
Table 60. Recommended Resistor Values for HIVREF and HI_VSWING Divider Circuits for ICH4-M
Chipset
Component
ICH4-M
852GME/PM
9.4.
Signal
Recommended Resistor
Values
HIVREF
(350mV)
R4 = 487
1%
R5 = 150
1%,
HI_VSWING
(800mV)
R6 = 130
1%
R7 = 150
1%,
HLVREF
(350mV)
R8 = 243
1%
R9 = 100
1%
PSWING
(800mV)
R10 = 49.9
1%
R11 = 100
1%
VCCHI
VCCHI=1.5 V
Capacitor value
C3 = 0.1 µF (near divider)
C2 = 0.01 µF (near component)
VCCHI=1.5 V
C1 = 0.1 µF (near divider)
C4 = 0.01 µF (near component)
VCCGMCH=1.5 V
C3 = 0.1 µF (near divider)
C6 = 0.01 µF (near component)
VCCGMCH=1.5 V
C1 = 0.1 µF (near divider)
C5 = 0.01 µF (near component)
Hub Interface Decoupling Guidelines
To improve I/O power delivery, use two 0.1-µF capacitors per each component (i.e. the ICH4-M and
GMCH). These capacitors should be placed within 50 mils from each package, adjacent to the rows that
contain the hub interface. If the layout allows, wide metal fingers running on the VSS side of the board
should connect the VCCHI side of the capacitors to the VCCHI power pins. Similarly, if layout allows,
metal fingers running on the VCCHI side of the board should connect the groundside of the capacitors to
the VSS power pins.
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10.
I/O Subsystem
10.1.
IDE Interface
This section contains guidelines for connecting and routing the Intel 82801DBM ICH4-M IDE interface.
The ICH4-M has two independent IDE channels. This section provides guidelines for IDE connector
cabling and motherboard design, including component and resistor placement, and signal termination for
both IDE channels. The ICH4-M has integrated the series resistors that have been typically required on
the IDE data signals (PDD[15:0] and SDD[15:0]) running to the two ATA connectors. While it is not
anticipated that additional series termination resistors will be required, OEMs should verify motherboard
signal integrity through simulation. Additional external, 0- resistors can be incorporated into the
design to address possible noise issues on the motherboard. The additional resistor layout increases
flexibility by offering stuffing options at a later date.
The IDE interface can be routed with 5-mil traces on 7-mil spaces, and must be less than 8 inches long
(from ICH4-M to IDE connector). Additionally, the maximum length difference between the shortest
data signal and the longest strobe signal of a channel is 0.5 inches.
10.1.1.
Cabling
Length of cable: Each IDE cable must be equal to or less than 18 inches.
Capacitance: Less than 35 pF.
Placement: A maximum of 6 inches between drive connectors on the cable. If a single drive is
placed on the cable it should be placed at the end of the cable. If a second drive is placed on the
same cable, it should be placed on the next closest connector to the end of the cable (6 inches away
from the end of the cable).
Grounding: Provide a direct low impedance chassis path between the motherboard ground and hard
disk drives.
ICH4-M Placement: The ICH4-M must be placed equal to or less than 8 inches from the ATA
connector(s).
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10.1.2.
Primary IDE Connector Requirements
Figure 55. Connection Requirements for Primary IDE Connector
22 to 47Ω
†
PCIRST#
PDD[15:0]
PDA[2:0]
PDIOR#
®
Intel
ICH4-M
PDIOW#
PDDREQ
PDDACK#
3.3V
3.3V
4.7K
8.2~10K
PIORDY (PRDSTB / PWDMARDY#)
Primary IDE Connector
PDCS[3,1]#
IRQ[14]
PDIAG# / CBLID#
GPIOx
CSEL
10K
† Due to ringing,
PCIRST# must be
buffered
The following are connection requirements for Primary IDE Connector:
22 - 47 series resistors are required on RESET#. The correct value should be determined for
each unique motherboard design, based on signal quality.
An 8.2 k
- 10 k
pull-up resistor is required on IRQ14 to VCC3_3.
A 4.7-k
pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
Series resistors can be placed on the control and data lines to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Primary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the
IDE interface.
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10.1.3.
Secondary IDE Connector Requirements
Figure 56. Connection Requirements for Secondary IDE Connector
22 - 47Ω
PCIRST# †
SDA[2:0]
SDCS[3,1]#
SDIOR#
®
Intel
ICH4-M
SDIOW#
SDDREQ
SDDACK#
3.3V
3.3V
4.7K
8.2~10K
SIORDY (SRDSTB / SWDMARDY# )
Secondary IDE Connector
SDD[15:0]
IRQ[15]
PDIAG# / CBLID#
GPIOy
CSEL
10K
† Due to ringing,
PCIRST# must be
buffered
The following are connection requirements for Secondary IDE Connector:
22 - 47 series resistors are required on RESET#. The correct value should be determined for
each unique motherboard design, based on signal quality.
An 8.2 k
- 10 k
pull-up resistor is required on IRQ15 to VCC3_3.
A 4.7-k
pull-up resistor to VCC3_3 is required on PIORDY and SIORDY.
Series resistors can be placed on the control and data lines to improve signal quality. The resistors
are placed as close to the connector as possible. Values are determined for each unique
motherboard design.
The 10-k resistor to ground on the PDIAG#/CBLID# signal is required on the Secondary
Connector. This change is to prevent the GPI pin from floating if a device is not present on the IDE
interface.
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10.1.4.
Mobile IDE Swap Bay Support
Systems that require the support for an IDE “hot” swap drive bay can be designed to utilize the ICH4M’s IDE interface disable feature to achieve this functionality. To support a mobile “hot” swap bay, the
ICH4-M allows the IDE output signals to be tri-stated or driven low and input buffers to be turned off.
This requires certain hardware and software requirements to be met for proper operation.
From a hardware perspective, the equivalent of two spare control signals (e.g. GPIO’s) and a FET are
needed to properly utilize the IDE tri-state feature. An IDE drive must have a reset signal (i.e. first
additional control signal) driving its reset pin and a power supply that is isolated from the rest of the
IDE interface. To isolate the power supplied to the IDE drive bay, a second additional control signal is
needed to control the enabling/disabling of a FET that supplies a separate plane flood powering the IDE
drive and its interface.
Although actual hardware implementations may vary, the isolated reset signal and power plane
are strict requirements. Systems that connect the IDE swap bay drive to the same power plane and
reset signals of the ICH4-M should not use this IDE tri-state feature. Many IDE drives use the control
and address lines as straps that are used to enter test modes. If the IDE drive is powered up along with
the ICH4-M while the IDE interface is tri-stated rather than being driven to the default state, then the
IDE drive could potentially enter a test mode. To avoid such a situation, the aforementioned hardware
requirements or equivalent solution should be implemented.
10.1.4.1. ICH4-M IDE Interface Tri-State Feature
The new IDE interface tri-state capabilities of the ICH4-M also include a number of configuration bits
that must be programmed accordingly for proper system performance. The names of the critical
registers, their location, and brief description are listed below.
1. B0:D31:F0 Offset D5h (BACK_CNTL – Backed Up Control register) bits [7:6] need to be set to 1
in order to enable the tri-stating of the primary and secondary IDE pins when the interfaces are put
into reset. By default both bits are set to 1.
2. B0:D31:F0 Offset D0-D3h (GEN_CNTL – General Control register) bit [3] should be set to 1 in
order to lock the state of bits [7:6] at B0:D31:F0 Offset D5h. This prevents any inadvertent
reprogramming of the IDE interface pins to a non-tri-state mode during reset by a rogue software
program. By default this bit is set to 0 and BIOS should set this bit to 1. This is a write once bit
only and requires a PCIRST# to reset to 0. Thus, this bit also needs to be set to 1 after resume
from S3-S5.
3. B0:D31:F1 Offset 54h (IDE_CONFIG – IDE I/O Configuration register) bits [19:18]
(SEC_SIG_MODE) and bits [17:16] (PRIM_SIG_MODE) control the reset states of the
secondary and primary IDE channels, respectively. The values in SEC_SIG_MODE and
PRIM_SIG_MODE are tied to the values set by the BACK_CNTRL register bits [7:6],
respectively. When bits [7:6] are set to 1, the PRIM_SIG_MODE and SEC_SIG_MODE will be
set to 01 for tri-state when the either IDE channel is put in reset.
4. B0:D31:F1 Offset 40-41h (Primary) and 42-23h (Secondary) bit [5] and bit [1] (IDE_TIM – IDE
Timing register) are the IORDY Sample Point Enable bits for drive 1 and 0 of the primary and
secondary IDE channels, respectively. By default, these bits are set to 0 and during normal power
up, should be set to 1 by the BIOS to enable IORDY assertion from the IDE device when an
access is requested.
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10.1.4.2.
S5/G3 to S0 Boot Up Procedures for IDE Swap Bay
The procedures listed below summarize the steps that must be followed during power up of an IDE
swap bay drive:
1. ICH4-M powers up, IDE interface is tri-stated, disk drive is not powered up. IDE drive is
recognized as being on a separate power plane and its reset is different from the ICH4-M.
2. BIOS powers on the IDE drive. e.g. GPIO is used to switch on a FET on the board.
3. Once the IDE drive and interface is powered up, the ICH4-M exits from tri-state mode and begins
to actively drive the interface.
4. Once ready, the BIOS can de-assert the reset signal to the IDE drive, e.g. GPIO routed to the IDE
drive’s reset pin.
10.1.4.3. Power Down Procedures for Mobile Swap Bay
The procedures listed below summarize the steps that must be followed in order to remove an IDE
device from the mobile swap bay:
1. User indicates to the system that removal of IDE device from the mobile swap bay should begin.
Once the system recognizes that all outstanding IDE accesses have completed, the reset signal to
the swap device should be asserted.
2. The IDE channel (primary or secondary) that the device resides on should then be set to drive low
mode rather than the default tri-state mode. This requires setting the IDE_CONFIG register
(B0:D31:F0 Offset 54h) bits [19:18] or [17:16] to 10 (10b). This will cause all IDE outputs to the
IDE drive to drive low rather than the default tri-state (which is useful during boot up to prevent
any IDE drives from entering a test mode).
3. The IORDY Sample Point Enable bit of the IDE_TIM register for the appropriate IDE device
should then be set to 0 to disable IORDY sampling by the ICH4-M. This ensures that zeros will
always be returned if the OS attempts to access the IDE device being swapped.
4. Power to the isolated power plane of the IDE device can then be removed and the system can
indicate to the user that the mobile swap bay can be removed and the IDE device replaced.
10.1.4.4. Power Up Procedures After Device “Hot” Swap Completed
The procedures listed below summarize the steps that must be followed after a new IDE device has been
added to the mobile swap bay and the swap bay must be powered back up:
1. Once the IDE swap bay is replaced into the system, the power plane to the device should be
enabled once again.
2. The IORDY Sample Point Enable bit of the IDE_TIM register for the appropriate IDE device
should then be set to 1 to enable IORDY sampling by the ICH4-M. This allows the OS to access
the IDE device once again and waits for the assertion of IORDY in response to an access request.
3. Once the system IDE interface is configured for normal operation once again, the reset signal to
the swap device should be de-asserted to allow the drive to initialize.
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10.2.
PCI
The Intel 82801DBM ICH4-M provides a PCI Bus interface that is compliant with the PCI Local Bus
Specification Revision 2.2. The implementation is optimized for high performance data streaming when
the ICH4-M is acting as either the target or the initiator in the PCI bus.
The ICH4-M supports six PCI Bus masters (excluding the ICH4-M), by providing six REQ#/GNT#
pairs. In addition, the ICH4-M supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed
with a PCI REQ#/GNT# pair.
Figure 57. PCI Bus Layout Example
1
Intel ®
ICH4
2
3
4
5
L1
6
L2
L3
L4
L5
L6
10.3.
AC’97
The Intel 82801DBM ICH4-M implements an AC’97 2.1, 2.2, and 2.3 compliant digital controller.
Please contact your codec IHV (Independent Hardware Vendor) for information on 2.2 compliant
products. The AC’97 2.2 specification is on the Intel website:
http://developer.intel.com/ial/scalableplatforms/audio/index.htm - 97spec/
The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data
streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The
AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion.
Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the
ICH4-M AC-link allows a maximum of three codecs to be connected. Figure 58 shows a three-codec
topology of the AC-link for the ICH4-M.
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Figure 58. Intel 82801DBM ICH4-M AC’97 – Codec Connection
AC / MC / AMC
RESET#
SDATA_OUT
SYNC
Intel®
ICH4
BIT_CLK
SDATA_IN0
SDATA_IN1
Primary
Codec
SDATA_IN2
AC / MC / AMC
Secondary
Codec
AC / MC / AMC
Tertiary
Codec
NOTE:
If a modem codec is configured as the primary AC-link Codec, there should not be any Audio Codecs
residing on the AC-link. The primary codec may be connected to AC_SDIN0 as documented in the Intel
ICH4-M Datasheet.
Clocking is provided from the primary codec on the link via AC_BIT_CLK, and is derived from a
24.576-MHz crystal or oscillator. Refer to the primary codec vendor for crystal or oscillator
requirements. AC_BIT_CLK is a 12.288-MHz clock driven by the primary codec to the digital
controller (ICH4-M) and to any other codec present. That clock is used as the time base for latching and
driving data. Clocking AC_BIT_CLK directly off the CK-408 clock chip’s 14.31818-MHz output is
not supported.
The ICH4-M supports wake-on-ring from S1M-S5 via the AC’97 link. The codec asserts AC_SDIN to
wake the system. To provide wake capability and/or caller ID, standby power must be provided to the
modem codec.
The ICH4-M has weak pull-down/pull-ups that are always enabled. This will keep the link from floating
when the AC-link is off or there are no codecs present.
If the Shut-off bit is not set, it implies that there is a codec on the link. Therefore, AC_BIT_CLK and
AC_SDOUT will be driven by the codec and the ICH4-M respectively. However, AC_SDIN0,
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AC_SDIN1, and AC_SDIN2 may not be driven. If the link is enabled, the assumption can be made that
there is at least one codec.
Figure 59. Intel 82801DBM ICH4-M AC’97 – AC_BIT_CLK Topology
Intel®
ICH4
AC_BIT_CLK
L1
R1
L3
L3
R2
L4
L2
C
O
N
N
Primary
Codec
Table 61. AC’97 AC_BIT_CLK Routing Summary
AC’97 Routing Requirements
Maximum Trace Length
(inches)
Series Termination
Resistance
5 on 5
L1 = (1 to 8) – L3
R1 = 33
L2 = 0.1 to 6
R2 = Option 0 resistor
for debugging purposes
L3 = 0.1 to 0.4
AC_BIT_CLK Signal
Length Matching
N/A
- 47
L4 = (1 to 6) – L3
NOTES:
1. Simulations were performed using Analog Device’s* Codec (AD1885) and the Cirrus Logic’s* Codec
(CS4205b). Results showed that if the AD1885 codec was used a 33- resistor was best for R1 and if the
CS4205b codec was used a 47- resistor for R1 was best.
2. Bench data shows that a 47- resistor for R1 is best for the Sigmatel* 9750 codec.
Figure 60. Intel 82801DBM AC’97 – AC_SDOUT/AC_SYNC Topology
Intel®
ICH4-M
AC_SDOUT
L2
L3
R2
L1
L3
C
O
N
N
R1
L4
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Table 62. AC’97 AC_SDOUT/AC_SYNC Routing Summary
AC’97 Routing Requirements
Maximum Trace Length
(inches)
Series Termination
Resistance
5 on 5
L1 = (1 to 6) – L3
R1 = 33
L2 = 1 to 8
R2 = R1 if the connector
card that will be used
with the platform does
not have a series
termination on the card.
Otherwise R2 = 0
L3 = 0.1 to 0.4
L4 = (0.1 to 6) – L3
AC_SDOUT/AC_SYNC
Signal Length
Matching
N/A
- 47
NOTES:
1. Simulations were performed using Analog Device’s* Codec (AD1885) and the Cirrus Logic’s* Codec
(CS4205b). Results showed that if the AD1885 codec was used a 33- resistor was best for R1 and if the
CS4205b codec was used a 47- resistor for R1 was best.
2. Bench data shows that a 47- resistor for R1 is best for the Sigmatel* 9750 codec.
Figure 61. Intel 82801DBM AC’97 – AC_SDIN Topology
Codec
Y5
R1
Intel®
ICH4-M
AC_SDIN2
AC_SDIN1
AC_SDIN0
Y1
Y2
Y4
Y3
Y3
R2
CONN
Y1
R2
Y1
R2
Y1
AC97_SDATA_IN2
AC97_SDATA_IN1
AC97_SDATA_IN0
Table 63. AC’97 AC_SDIN Routing Summary
AC’97 Routing Requirements
Maximum Trace Length
(inches)
Series Termination
Resistance
5 on 5
Y1 = 0.1 to 0.4
R1 = 33
Y2 = (1 to 8) – Y1
R2 = R1 if the connector
card that will be used with
the platform does not have
a series termination on the
card. Otherwise R2 = 0
Y3 = (1 to 14) – Y1
Y4 = (1 to 6) – Y1
- 47
AC_SDIN Signal
Length Matching
N/A
Y5 = (0.1 to 6) – Y1
NOTES:
1. Simulations were performed using Analog Device’s Codec (AD1885) and the Cirrus Logic’s Codec (CS4205b).
Results showed that if the AD1885 codec was used a 33- resistor was best for R1 and if the CS4205b codec
was used a 47- resistor for R1 was best.
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2. Bench data shows that a 47-
10.3.1.
resistor for R1 is best for the Sigmatel 9750 codec.
AC’97 Routing
To ensure the maximum performance of the codec, proper component placement and routing techniques
are required. These techniques include properly isolating the codec, associated audio circuitry, analog
power supplies, and analog ground plane, from the rest of the motherboard. This includes plane splits
and proper routing of signals not associated with the audio section. Contact your vendor for devicespecific recommendations.
The basic recommendations are as follows:
Special consideration must be given for the ground return paths for the analog signals.
Digital signals routed in the vicinity of the analog audio signals must not cross the power plane
split lines. Analog and digital signals should be located as far as possible from each other.
Partition the board with all analog components grouped together in one area and all digital
components in another.
Separate analog and digital ground planes should be provided, with the digital components over the
digital ground plane, and the analog components, including the analog power regulators, over the
analog ground plane. The split between planes must be a minimum of 0.05 inches wide.
Keep digital signal traces, especially the clock, as far as possible from the analog input and voltage
reference pins.
Do not completely isolate the analog/audio ground plane from the rest of the board ground plane.
There should be a single point (0.25 inches to 0.5 inches wide) where the analog/isolated ground
plane connects to the main ground plane. The split between planes must be a minimum of 0.05
inches wide.
Any signals entering or leaving the analog area must cross the ground split in the area where the
analog ground is attached to the main motherboard ground. That is, no signal should cross the
split/gap between the ground planes, which would cause a ground loop, thereby greatly increasing
EMI emissions and degrading the analog and digital signal quality.
Analog power and signal traces should be routed over the analog ground plane.
Digital power and signal traces should be routed over the digital ground plane.
Bypassing and decoupling capacitors should be close to the IC pins, or positioned for the shortest
connections to pins, with wide traces to reduce impedance.
All resistors in the signal path or on the voltage reference should be metal film. Carbon resistors
can be used for DC voltages and the power supply path, where the voltage coefficient, temperature
coefficient, and noise are not factors.
Regions between analog signal traces should be filled with copper, which should be electrically
attached to the analog ground plane. Regions between digital signal traces should be filled with
copper, which should be electrically attached to the digital ground plane.
Locate the crystal or oscillator close to the codec.
10.3.2.
Motherboard Implementation
The following design considerations are provided for the implementation of an ICH4-M platform using
AC’97. These design guidelines have been developed to ensure maximum flexibility for board
designers, while reducing the risk of board-related issues. These recommendations are not the only
implementation or a complete checklist, but they are based on the ICH4-M platform.
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Active components such as FET switches, buffers or logic states should not be implemented on the
AC-link signals, except for AC_RST#. Doing so would potentially interfere with timing margins
and signal integrity.
The ICH4-M supports wake-on-ring from S1M-S5 states via the AC’97 link. The codec asserts
AC_SDIN to wake the system. To provide wake capability and/or caller ID, standby power must be
provided to the modem codec. If no codec is attached to the link, internal pull-downs will prevent
the inputs from floating, so external resistors are not required.
PC_BEEP should be routed through the audio codec. Care should be taken to avoid the introduction
of a pop when powering the mixer up or down.
10.3.2.1. Valid Codec Configurations
Table 64. Supported Codec Configurations
Option
Primary Codec
Secondary Codec
Tertiary Codec
Notes
1
Audio
Audio
Audio
1
2
Audio
Audio
Modem
1
3
Audio
Audio
Audio/Modem
1
4
Audio
Modem
Audio
1
5
Audio
Audio/Modem
Audio
1
6
Audio/Modem
Audio
Audio
1
NOTES:
1. For power management reasons, codec power management registers are in audio space. As a result, if there is
an audio codec in the system it must be Primary.
2. There cannot be two modems in a system since there is only one set of modem DMA channels.
3. The ICH4-M supports a codec on any of the AC_SDIN lines, however the modem codec ID must be either 00 or
01.
10.3.3.
SPKR Pin Configuration
SPKR is used as both the output signal to the system speaker and as a functional strap. The strap
function enables or disables the “TCO Timer Reboot function” based on the state of the SPKR pin on
the rising edge of PWROK. When enabled, the ICH4-M sends an SMI# to the processor upon a TCO
timer timeout. The status of this strap is readable via the NO_REBOOT bit (bit 1, D31: F0, Offset D4h).
The SPKR signal has a weak integrated pull-down resistor (the resistor is only enabled during
boot/reset). Therefore, its default state is a logical zero or set to reboot. To disable the feature, a jumper
can be populated to pull the signal line high (see Figure 62). The value of the pull-up must be such that
the voltage divider output caused by the pull-up, the effective pull-down (Reff), and the ICH4-M’s
integrated pull-down resistor will be read as logic high (0.5 * VCC3_3 to VCC3_3 + 0.5 V).
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Figure 62. Example Speaker Circuit
VCC3_3
R Value is
Implementation
Specific
Intel®
ICH4-M
Integrated
Pull-down
Stuff Jumper to Disable
Timeout Feature
(No Reboot)
SPKR
9K
Effective Impedance
Due to Speaker and
Codec Circuit
- 50KΩ
Reff
10.4.
USB 2.0 Guidelines and Recommendations
10.4.1.
Layout Guidelines
10.4.1.1. General Routing and Placement
Use the following general routing and placement guidelines when laying out a new design. These
guidelines will help to minimize signal quality and EMI problems. The USB 2.0 validation efforts
focused on a four-layer motherboard where the first layer is a signal layer, the second plane is power,
the third plane is ground and the fourth is a signal layer. This results in the placement of most of the
routing on the fourth plane (closest to the ground plane), allowing a higher component density on the
first plane.
1. Place the ICH4-M and major components on the un-routed board first. With minimum trace
lengths, route high-speed clock, periodic signals, and USB 2.0 differential pairs first. Maintain
maximum possible distance between high-speed clocks/periodic signals to USB 2.0 differential
pairs and any connector leaving the PCB (i.e. I/O connectors, control and signal headers, or power
connectors).
2. USB 2.0 signals should be ground referenced (on recommended stack-up this would be the
bottom signal layer).
3. Route USB 2.0 signals using a minimum of vias and corners. This reduces reflections and
impedance changes.
4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90°
turn. This reduces reflections on the signal by minimizing impedance discontinuities. (As shown
in Figure 62).
5. Do not route USB 2.0 traces under crystals, oscillators, clock synthesizers, magnetic devices or
ICs that use and/or duplicate clocks.
6. Stubs on high-speed USB signals should be avoided, as stubs will cause signal reflections and
affect signal quality. If a stub is unavoidable in the design, the sum of all stubs for a particular
signal line should not exceed 200 mils.
7. Route all traces over continuous planes (VCC or GND), with no interruptions. Avoid crossing
over anti-etch if at all possible. Crossing over anti-etch (plane splits) increases inductance and
radiation levels by forcing a greater loop area. Likewise, avoid changing layers with USB 2.0
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traces as much as practical. It is preferable to change layers to avoid crossing a plane split. Refer
to 10.4.2.
8. Separate signal traces into similar categories and route similar signal traces together (such as
routing differential pairs together).
9. Keep USB 2.0 USB signals clear of the core logic set. High current transients are produced during
internal state transitions and can be very difficult to filter out.
10. Follow the 20*h thumb rule by keeping traces at least 20*(height above the plane) away from the
edge of the plane (VCC or GND, depending on the plane the trace is over). For the suggested
stack-up the height above the plane is 4.5 mils. This calculates to a 90-mil spacing requirement
from the edge of the plane. This helps prevent the coupling of the signal onto adjacent wires and
also helps prevent free radiation of the signal from the edge of the PCB.
10.4.1.2. USB 2.0 Trace Separation
The separation guidelines are as follows:
1. Maintain parallelism between USB differential signals with the trace spacing needed to achieve
90- differential impedance. Deviations will normally occur due to package breakout and routing
to connector pins. Just ensure the amount and length of the deviations is kept to the minimum
possible.
2. Use an impedance calculator to determine the trace width and spacing required for the specific
board stack-up being used. 4-mil traces with 4.5-mil spacing results in approximately 90differential trace impedance.
3. Minimize the length of high-speed clock and periodic signal traces that run parallel to high speed
USB signal lines, to minimize crosstalk. Based on EMI testing experience, the minimum
suggested spacing to clock signals is 50 mils.
4. Based on simulation data, use 20-mil minimum spacing between high-speed USB signal pairs and
other signal traces for optimal signal quality. This helps to prevent crosstalk.
Figure 63. Recommended USB Trace Spacing
Low-speed
non periodic
signal
DP1
20
4
DM1
4.5
4
DP2
20
4
Distance in mils
Clock/Highspeed
periodic signal
DM2
4.5
4
50
10.4.1.3. USBRBIAS Connection
The USBRBIAS pin and the USBRBIAS# pin can be shorted and routed 5 on 5 to one end of a 22.6
±1% resistor to ground. Place the resistor within 500 mils of the ICH4-M and avoid routing next to
clock pins.
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Figure 64. USBRBIAS Connection
Intel®
ICH4-M
USBRBIAS
22.6Ω+/- 1%
USBRBIAS#
Table 65. USBRBIAS/USBRBIAS# Routing Summary
USBRBIAS/ USBRBIAS#
Routing Requirements
Maximum Trace Length
Signal Length Matching
Signal Referencing
5 on 5
500 mils
N/A
N/A
10.4.1.4. USB 2.0 Termination
A common-mode choke should be used to terminate the USB 2.0 bus. Place the common-mode choke as
close as possible to the connector pins. See Section 10.4.4 for details.
10.4.1.5. USB 2.0 Trace Length Pair Matching
USB 2.0 signal pair traces should be trace length matched. Max trace length mismatch between USB 2.0
signal pair should be no greater that 150 mils.
10.4.1.6. USB 2.0 Trace Length Guidelines
Table 66. USB 2.0 Trace Length Guidelines (With Common-mode Choke)
Configuration
Back Panel
Signal
Referencing
Ground
Signal Matching
The max mismatch
between data pairs
should not be
greater than 150
mils
Motherboard
Trace Length
17 inches
Card Trace
Length
N/A
Maximum Total
Length
17 inches
NOTES:
1. These lengths are based upon simulation results and may be updated in the future.
2. All lengths are based upon using a common-mode choke (see Section 10.4.4.1 for details on common-mode
choke).
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10.4.2.
Plane Splits, Voids, and Cut-Outs (Anti-Etch)
The following guidelines apply to the use of plane splits voids and cutouts.
10.4.2.1. VCC Plane Splits, Voids, and Cut-Outs (Anti-Etch)
Use the following guidelines for the VCC plane.
1. Traces should not cross anti-etch, for it greatly increases the return path for those signal traces.
This applies to USB 2.0 signals, high-speed clocks, and signal traces as well as slower signal
traces that might be coupling to them. USB signaling is not purely differential in all speeds (i.e.
the full-speed single ended zero is common mode).
2. Avoid routing of USB 2.0 signals 25 mils of any anti-etch to avoid coupling to the next split or
radiating from the edge of the PCB.
When breaking signals out from packages it is sometimes very difficult to avoid crossing plane splits or
changing signal layers, particularly in today’s motherboard environment that uses several different
voltage planes. Changing signal layers is preferable to crossing plane splits if a choice has to be made
between one or the other.
If crossing a plane split is completely unavoidable, proper placement of stitching caps can minimize the
adverse effects on EMI and signal quality performance caused by crossing the split. Stitching capacitors
are small-valued capacitors (1 F or lower in value) that bridge voltage plane splits close to where high
speed signals or clocks cross the plane split. The capacitor ends should tie to each plane separated by the
split. They are also used to bridge, or bypass, power and ground planes close to where a high-speed
signal changes layers. As an example of bridging plane splits, a plane split that separates VCC5 and
VCC3_3 planes should have a stitching cap placed near any high-speed signal crossing. One side of the
cap should tie to VCC5 and the other side should tie to VCC3_3. Stitching caps provide a high frequency
current return path across plane splits. They minimize the impedance discontinuity and current loop area
that crossing a plane split creates.
10.4.2.2. GND Plane Splits, Voids, and Cut-Outs (Anti-Etch)
Avoid anti-etch on the GND plane.
10.4.3.
USB Power Line Layout Topology
The following is a suggested topology for power distribution of Vbus to USB ports. Circuits of this type
provide two types of protection during dynamic attach and detach situations on the bus: inrush current
limiting (droop) and dynamic detach fly-back protection. These two different situations require both
bulk capacitance (droop) and filtering capacitance (for dynamic detach fly-back voltage filtering). It is
important to minimize the inductance and resistance between the coupling capacitors and the USB ports.
That is, capacitors should be placed as close as possible to the port and the power carrying traces should
be as wide as possible, preferably, a plane. A good rule is to make the power carrying traces wide
enough that the system fuse will blow on an over current event. If the system fuse is rated at 1 amp, then
the power carrying traces should be wide enough to carry at least 1.5 amps.
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Figure 65. Good Downstream Power Connection
5V
5V Sus
5V
Switch
Thermister
Vcc
1
470pF
220uF
Gnd
Vcc
Port1
4
1
470pF
Gnd
10.4.4.
Port2
4
EMI Considerations
The following guidelines apply to the selection and placement of common-mode chokes and ESD
protection devices.
10.4.4.1. Common Mode Chokes
Testing has shown that common-mode chokes can provide required noise attenuation. A design should
include a common-mode choke footprint to provide a stuffing option in the event the choke is needed to
pass EMI testing. Figure 66 shows the schematic of a typical common-mode choke and ESD
suppression components. The choke should be placed as close as possible to the USB connector signal
pins.
Figure 66. Common Mode Choke Schematic
Vcc
D+
Common Mode
Choke
USB A
Connector
D ESD Supression
Components
Common mode chokes distort full-speed and high-speed signal quality. As the common mode
impedance increases, the distortion will increase, so you should test the effects of the common mode
choke on full speed and high-speed signal quality. Common mode chokes with a target impedance of 80
to 90 at 100 MHz generally provide adequate noise attenuation.
Finding a common mode choke that meets the designer’s needs is a two-step process:
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1.
2.
10.4.5.
A part must be chosen with the impedance value that provides the required noise attenuation. This
is a function of the electrical and mechanical characteristics of the part chosen and the frequency
and strength of the noise present on the USB traces that you are trying to suppress.
Once you have a part that gives passing EMI results the second step is to test the effect this part
has on signal quality. Higher impedance common-mode chokes generally have a greater damaging
effect on signal quality, so care must be used when increasing the impedance without doing
thorough testing. Thorough testing means that the signal quality must be checked for low-speed,
full-speed and high-speed USB operation.
ESD
Classic USB (1.0/1.1) provided ESD suppression using in line ferrites and capacitors that formed a low
pass filter. This technique doesn’t work for USB 2.0 due to the much higher signal rate of high-speed
data. A device that has been tested successfully is based on spark gap technology. Proper placement of
any ESD protection device is on the data lines between the common-mode choke and the USB
connector data pins as shown in Figure 66. Other types of low-capacitance ESD protection devices may
work as well but were not investigated. As with the common mode choke solution, it is recommended to
include footprints for some type of ESD protection device as a stuffing option in case it is needed to
pass ESD testing.
10.4.6.
USB Selective Suspend
The USB Specification states maximum current consumption on the "USB bus" is 500 mA for normal
operation, 2.5 mA for suspend power when remote wakeup is to be supported and 500 µA otherwise.
However, some Bluetooth* devices may require more current in suspend state than specified in the USB
specification. Therefore, the system designers should ensure that, on their particular system
implementation, there is enough current supplied to the Bluetooth device during suspend state in order
for selective suspend to function properly.
10.5.
I/O APIC (I/O Advanced Programmable Interrupt
Controller)
The Intel ICH4-M is designed to be backwards compatible with a number of the legacy interrupt
handling mechanisms as well as to be compliant with the latest I/O (x) APIC architecture. In addition to
implementing two, 8259 interrupt controllers (PIC), the ICH4-M also incorporates an Advanced
Programmable Interrupt Controller (APIC) that is implemented via the 3-wire serial APIC bus that
connects all I/O and local APICs. Advancement in the interrupt delivery and control architecture of the
ICH4-M is represented by support for the I/O (x) APIC specification where PCI devices deliver
interrupts as write cycles that are written directly to a register representing the desired interrupt. These
are ultimately delivered via the serial APIC bus or FSB. Furthermore, on
852GME/852GMV/852PMbased systems, the ICH4-M has the option to let the integrated I/O APIC
behave as an I/O (x) APIC. This allows the ICH4-M to deliver interrupts in a parallel manner rather than
just a serial one and is accomplished by I/O APIC writing to a region of memory that is snooped by the
processor and thereby processor knows what interrupt goes active.
On 852GME/852GMV/852PMbased platforms, the serial I/O APIC bus interface of the ICH4-M should
be disabled. I/O (x) APIC is supported on the platform and the servicing of interrupts is accomplished
via a BFSB interrupt delivery mechanism.
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The serial I/O APIC bus interface of the ICH4-M should be disabled as follows.
1. Tie APICCLK directly to ground.
2.
Tie APICD0, APICD1 to ground through a 10-k
using XOR chain testing)
resistor. (Separate pull-downs are required if
The processors discussed in this document do not have pins dedicated for a serial I/O APIC bus
interface and thus, no hardware change is necessary. However, it is strongly encouraged to enable I/O
APIC support in the BIOS and operating system on 852GME/852GMV/852PMbased systems rather
than the legacy 8259 interrupt controller due to the performance benefits and efficiencies that the I/O (x)
APIC architecture enjoys over the older PIC architecture.
10.6.
SMBus 2.0/SMLink Interface
The SMBus interface on the ICH4-M uses two signals SMBCLK and SMBDATA to send and receive
data from components residing on the bus. These signals are used exclusively by the SMBus host
controller. The SMBus host controller resides inside the ICH4-M.
The ICH4-M incorporates an SMLink interface supporting Alert-on-LAN*, Alert-on-LAN2*, and a
slave functionality. It uses two signals SMLINK[1:0]. SMLINK[0] corresponds to a SMBus clock signal
and SMLINK[1] corresponds to a SMBus data signal. These signals are part of the SMB slave
interface.
For Alert-on-LAN functionality, the ICH4-M transmits heartbeat and event messages over the interface.
When using the Intel 82562EM Platform LAN Connect component, the ICH4-M’s integrated LAN
controller will claim the SMLink heartbeat and event messages and send them out over the network. An
external, Alert-on-LAN2*enabled LAN controller (i.e. Intel 82562EM 10/100 Mbps platform LAN
connect) will connect to the SMLink signals to receive heartbeat and event messages, as well as access
the ICH4-M SMBus slave interface. The slave interface function allows an external micro-controller to
perform various functions. For example, the slave write interface can reset or wake a system, generate
SMI# or interrupts, and send a message. The slave read interface can read the system power state, read
the watchdog timer status, and read system status bits.
Both the SMBus host controller and the SMBus slave interface obey the SMBus 1.0 protocol, so the two
interfaces can be externally wire-OR’ed together to allow an external management ASIC (such as Intel
82562EM 10/100 Mbps platform LAN connect) to access targets on the SMBus as well as the ICH4-M
slave interface. Additionally, the ICH4-M supports slave functionality, including the Host Notify
protocol, on the SMLink pins. Therefore, in order to be fully compliant with the SMBus 2.0
specification (which requires the Host Notify cycle), the SMLink and SMBus signals must be tied
together externally. This is done by connecting SMLink[0] to SMBCLK and SMLink[1] to SMBDATA.
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Figure 67. SMBUS 2.0/SMLink Protocol
SPD Data
Host Controller and
Slave Interface
SMBus
Temperature on
Thermal Sensor
Network
Interface Card
on PCI Bus
SMBCLK
Microcontroller
SMBDATA
Intel® ICH4
SMLink
SMLink0
SMLink1
Wire OR
(optional)
Motherboard
LAN
Controller
SMbus-SMlink_IF
Intel does not support external access of the ICH4-M’s Integrated LAN controller via the SMLink
interface. Also, Intel does not support access of the ICH4-M’s SMBus slave interface by the ICH4-M’s
SMBus host controller. Refer to the Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4-M)
Datasheet for full functionality descriptions of the SMLink and SMBus interface.
10.6.1.
SMBus Architecture and Design Considerations
10.6.1.1. SMBus Design Considerations
SMBus design solutions will vary for all platforms. The total bus capacitance and device capabilities
must be considered when designing SMBus segments. Routing SMBus to the PCI slots makes the
design process even more challenging since they add so much capacitance to the bus. This extra
capacitance has a large affect on the bus time constant which in turn affects the bus rise and fall times.
Primary considerations in the design process are:
1. Device class (High/Low power). Most designs use primarily high power devices.
2. Are there devices that must run in S3?
3. Amount of VCC_SUSPEND current available, i.e. minimizing load of VCC_ SUSPEND.
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10.6.1.2. General Design Issues/Notes
Regardless of the architecture used, there are some general considerations.
1. The pull-up resistor size for the SMBus data and clock signals is dependent on the bus load (this
includes all device leakage currents). Generally the SMBus device that can sink the least amount
of current is the limiting agent on how small the resistor can be. The pull-up resistor cannot be
made so large that the bus time constant (Resistance X capacitance) does not meet the SMBus rise
and fall time specification.
2. The maximum bus capacitance that a physical segment can reach is 400 pF.
3. The Intel ICH4-M does not run SMBus cycles while in S3.
4. SMBus devices that can operate in S3 must be powered by the VCC_ SUSPEND supply.
10.6.1.3. High Power/Low Power Mixed Architecture
This design allows for current isolation of high and low current devices while also allowing SMBus
devices to communicate during the S3 state. VCC_SUSPEND leakage is minimized by keeping non-essential
devices on the core supply. This is accomplished by the use of a “FET” to isolate the devices powered
by the core and suspend supplies. See Figure 68.
Figure 68. High Power/Low Power Mixed VCC_SUSPEND/VCC_CORE Architecture
Non- Standby devices
-
Vcc
Vcc
Devices running in Standby
Devices running in Standby
VccSus3_3 VccSus
VccSus VccSus3_3
Current Isolation
Logic
SMBus
Buffered Power Good Signal From
Power Supply
Low
Current
Non Standby
- devices
SMBus
Vcc
Vcc
SMBus
Buffered Power Good Signal From
Power Supply
ICH4
High
Current
Added Considerations for Mixed Architecture
1. The bus switch must be powered by VCC_SUSPEND.
2. Devices that are powered by the VCC_ SUSPEND well must not drive into other devices that are
powered off. This is accomplished with the “bus switch.”
3. The bus bridge can be a device like the Phillips PCA9515.
10.6.1.4. Calculating the Physical Segment Pull-Up Resistor
The following tables are provided as a reference for calculating the value of the pull-up resistor that may
be used for a physical bus segment. If any physical bus segment exceeds 400 pF, then a bus bridge
device like the Phillips* PCA9515 must be used to separate the physical segment into two segments that
individually have a bus capacitance less than 400 pF.
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Table 67. Bus Capacitance Reference Chart
Device
# of Devices/
Trace Length
Capacitance Includes
Cap (pF)
ICH4-M
1
Pin Capacitance
12
CK408
1
Pin Capacitance
10
SODIMMS
2
Pin Capacitance (10 pF) + 1 inch worth of trace
capacitance (2 pF/inch) per SO-DIMM and 2 pF
connector capacitance per SO-DIMM
28
PCI
Slots
2
Each PCI add-in card is allowed up to 40 pF + 3 pF per
each connector
86
3
3
Bus
Trace
Length
in inches
42
129
4
172
5
215
6
258
2 pF per inch of trace length
≥24
48
≥36
72
≥48
96
Table 68. Bus Capacitance/Pull-Up Resistor Relationship
Physical Bus Segment Capacitance
168
Pull-Up Range (For Vcc = 3.3 V
0 to 100 pF
8.2 k
to 1.2 k
100 to 200 pF
4.7 k
to 1.2 k
200 to 300 pF
3.3 k
to 1.2 k
300 to 400 pF
2.2 k
to 1.2 k
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10.7.
FWH
The following provides general guidelines for compatibility and design recommendations for supporting
the FWH device. The majority of the changes will be incorporated in the BIOS. Refer to the FWH BIOS
Specification or equivalent.
10.7.1.
FWH Decoupling
Refer to Section 12.7.6 for more details.
10.7.2.
In Circuit FWH Programming
All cycles destined for the FWH will appear on PCI. The ICH4-M hub interface to PCI bridge will put
all CPU boot cycles out on PCI (before sending them out on the FWH interface). If the ICH4-M is set
for subtractive decode, these boot cycles can be accepted by a positive decode agent on the PCI bus.
This enables the ability to boot from a PCI card that positively decodes these memory cycles. In order to
boot from a PCI card, it is necessary to keep the ICH4-M in subtractive decode mode. If a PCI boot card
is inserted and the ICH4-M is programmed for positive decode, there will be two devices positively
decoding the same cycle.
10.7.3.
FWH INIT# Voltage Compatibility
The FWH INIT# signal trip points need to be considered because they are NOT consistent among
different FWH manufacturers. The INIT# signal is active low. Therefore, the inactive state of the ICH4M INIT# signal needs to be at a value slightly higher than the VIH min FWH INIT# pin specification.
The inactive state of this signal is typically governed by the formula V_CPU_IO(min) – noise margin.
Therefore, if the V_CPU_IO(min) of the processor is 1.60 V, the noise margin is 200 mV and the VIH
min spec of the FWH INIT# input signal is 1.35 V, there would be no compatibility issue because 1.6 V
– 0.2 V = 1.40 V which is greater than the 1.35 V minimum of the FWH. If the VIH min of the FWH was
1.45 V, then there would be an incompatibility and logic translation would need to be used. The
examples above do not take into account any noise that may be encountered on the INIT# signal. Care
must be taken to ensure that the VIH min specification is met with ample noise margin. In applications
where it is necessary to use translation logic, refer to Section 4.3.7.2.
The solution assumes that level translation is necessary. The figure in Section 4.3.7.1.7 implements a
solution for the ICH4-M FWH signal INIT#. Trace lengths and resistor values can be found in Table 5.
The voltage translator circuitry is shown in Figure 16. Intel strongly recommended that any system that
implements a FWH should have its INIT# input connected to the ICH4-M.
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10.7.4.
FWH VPP Design Guidelines
The VPP pin on the FWH is used for programming the flash cells. The FWH supports VPP of 3.3 V or 12
V. If VPP is 12 V, the flash cells will program about 50% faster than at 3.3 V. However, the FWH only
supports 12-V VPP for 80 hours (3.3 V on Vpp does not affect the life of the device). The 12-V VPP
would be useful in a programmer environment, which is typically an event that occurs very infrequently
(much less than 80 hours). The VPP pin MUST be tied to 3.3 V on the motherboard.
In some instances, it is desirable to program the FWH during assembly with the device soldered down
on the board. In order to decrease programming time it becomes necessary to apply 12 V to the VPP pin.
The following circuit will allow testers to put 12 V on the VPP pin while keeping this voltage separated
from the 3.3-V plane to which the rest of the power pins are connected. This circuit also allows the
board to operate with 3.3 V on this pin during normal operation.
Figure 69. FWH VPP Isolation Circuitry
3.3V
12V (From Motherboard)
1K
FET
VPP
10.7.5.
FWH INIT# Assertion/Deassertion Timings
Due to the large routing solution space and necessity of a voltage translator in the design of a FWH on
852GME/852GMV/852PMand ICH4-M based platforms, the following timing requirements must be
met to ensure proper system operation.
For INIT# assertion timings, a conservative analysis of the worst case signal propagation times shows
that no timing concerns exist because the ICH4-M asserts INIT# for 16 PCI clocks (485 ns) before
deasserting. This provides adequate time for INIT# to propagate to both the processor and FWH.
For the INIT# deassertion event, the critical timing is the minimum period of time before the processor
is ready to begin fetching code from the FWH after the INIT# based reset begins. This minimum period
is conservatively set at 1 CPU clock (10 ns). This also represents the maximum allowed propagation
time for the INIT# signal from the ICH4-M to the FWH.
Systems that use alternative devices (i.e. not a FWH) to store the firmware may or may not require the
use of INIT#. If INIT# is not used, an analysis should be done to ensure there is no negative impact to
system operation. If INIT# is implemented on such a device, voltage translation may be necessary, and
the assertion/deassertion timings noted above still apply.
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10.8.
RTC
The Intel 82801DBM ICH4-M contains a real time clock (RTC) with 256 bytes of battery backed
SRAM. The internal RTC module provides two key functions: keeping date and time and storing system
data in its RAM when the system is powered down.
The ICH4-M uses a crystal circuit to generate a low-swing 32-kHz input sine wave. This input is
amplified and driven back to the crystal circuit via the RTCX2 signal. Internal to the ICH4-M, the
RTCX1 signal is amplified to drive internal logic as well as generate a free running full swing clock
output for system use. This output ball of the ICH4-M is called SUSCLK. This is illustrated in Figure
70.
Figure 70. RTCX1 and SUSCLK Relationship in ICH4-M
Low-Swing 32.768 kHz
Sine Wave Source
RTCX1
Internal
Oscillator
Full-Swing 32.768 kHz
Output Signal
ICH4-M
SUSCLK
For further information on the RTC, please consult Application Note AP-728 ICH Family Real Time
Clock (RTC) Accuracy and Considerations Under Test Conditions. This application note is valid for the
ICH4-M.
Even if the ICH4-M internal RTC is not used, it is still necessary to supply a clock input to RTCX1 of
the ICH4-M because other signals are gated off that clock in suspend modes. However, in this case the
frequency accuracy (32.768 kHz) of the clock inputs is not critical; a cheap crystal can be used or a
single clock input can be driven into RTCX1with RTCX2 left as no connect; Figure 71 illustrates the
connection. This is not a validated feature on the ICH4-M. Please note that the peak-to-peak swing
on RTCX1 cannot exceed 1.0 V.
Figure 71. External Circuitry for the ICH4-M Where the Internal RTC is Not Used
RTCX1
32 KHz
5M
RTCX2
Internal
External
No Connection
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10.8.1.
RTC Crystal
The Intel 82801DBM ICH4-M RTC module requires an external oscillating source of 32.768 kHz
connected on the RTCX1 and RTCX2 balls. Figure 72 documents the external circuitry that comprises
the oscillator of the ICH4-M RTC.
Figure 72. External Circuitry for the ICH4-M RTC
VCCRTC
3.3V Sus
1uF
RTCX2
1kΩ
R1
10MΩ
32.768 kHz
Xtal
Vbatt
RTCX1
C3
0.047uF
C1
18pF
R2
10MΩ
C2
18pF
VBIAS
VBIAS, VCCRTC, RTCX1, and RTCX2 are ICH4 pins
VBIAS is used to bias the ICH4 Internal Oscillator
VCCRTC powers the RTC well of the ICH4
RTCX1 is the Input to the Internal Oscillator
RTCX2 is the feedback for the external crystal
Notes
Reference Designators Arbitrarily Assigned
3.3V Sus is Active Whenever System Plugged In
Vbatt is Voltage Provided By Battery
NOTES:
1. The exact capacitor value needs to be based on what the crystal maker recommends.
(Typical values for C1 and C2 are 18 pF, based on crystal load of 12.5 pF.)
2. VCCRTC: Power for RTC Well
3. RTCX2: Crystal Input 2 – Connected to the 32.7 68 kHz crystal.
4. RTCX1: Crystal Input 1 – Connected to the 32.7 68 kHz crystal.
5. VBIAS: RTC BIAS Voltage – This ball is used to provide a reference voltage and this DC voltage sets a current,
which is mirrored throughout the oscillator and buffer circuitry.
6. VSS: Ground
Table 69. RTC Routing Summary
RTC Routing
Requirements
Maximum Trace
Length To Crystal
Signal
Length
Matching
R1, R2, C1, and C2
tolerances
5 mil trace width
(results in ~2 pF per
inch)
1 inch
NA
R1 = R2 = 10 M
± 5%
Signal
Referencing
Ground
C1 = C2 = (NPO class)
See Section 10.9.2 for
calculating a specific
capacitance value for C1
and C2
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10.8.2.
External Capacitors
To maintain the RTC accuracy, the external capacitor C3 needs to be 0.047 µF and capacitor values C1
and C2 should be chosen to provide the manufacturer’s specified load capacitance (Cload) for the crystal
when combined with the parasitic capacitance of the trace, socket (if used), and package. The following
equation can be used to choose the external capacitance values.
Equation 3.
Cload = [(C1 + Cin1 + Ctrace1)*(C2 + Cin2 + Ctrace2)]/[(C1 + Cin1 + Ctrace1 + C2 + Cin2 + Ctrace2)] + Cparasitic
Where:
Cload = Crystal’s load capacitance. This value can be obtained from Crystal’s specification.
Cin1, Cin2 = input capacitances at RTCX1, RTCX2 balls of the ICH4-M. These values can be
obtained in the ICH4-M’s data sheet.
Ctrace1, Ctrace2 = Trace length capacitances measured from Crystal terminals to RTCX1, RTCX2
balls. These values depend on the characteristics of board material, the width of signal traces and
the length of the traces. A typical value, based on a 5 mil wide trace and a ½ ounce copper pour, is
approximately equal to :
Ctrace = trace length * 2 pF/inch
Cparasitic = Crystal’s parasitic capacitance. This capacitance is created by the existence of 2 electrode
plates and the dielectric constant of the crystal blank inside the Crystal part. Refer to the crystal’s
specification to obtain this value.
Ideally, C1, C2 can be chosen such that C1 = C2. Using the equation of Cload above, the value of C1, C2
can be calculated to give the best accuracy (closest to 32.768 kHz) of the RTC circuit at room
temperature. However, C2 can be chosen such that C2 > C1. Then C1 can be trimmed to obtain the
32.768 kHz.
In certain conditions, both C1, C2 values can be shifted away from the theoretical values (calculated
values from the above equation) to obtain the closest oscillation frequency to 32.768 kHz. When C1, C2
values are smaller then the theoretical values, the RTC oscillation frequency will be higher.
The following example illustrates the use of the practical values C1, C2 in the case that theoretical values
cannot guarantee the accuracy of the RTC in low temperature condition:
Example:
According to a required 12-pF load capacitance of a typical crystal that is used with the ICH4-M, the
calculated values of C1 = C2 is 10 pF at room temperature (25°C) to yield a 32.768-kHz oscillation.
At 0°C the frequency stability of crystal gives – 23 ppm (assumed that the circuit has 0 ppm at 25°C).
This makes the RTC circuit oscillate at 32.767246 kHz instead of 32.768 kHz.
If the values of C1, C2 are chosen to be 6.8 pF instead of 10 pF, the RTC will oscillate at a higher
frequency at room temperature (+23 ppm) but this configuration of C1 / C2 makes the circuit oscillate
closer to 32.768 kHz at 0°C. The 6.8-pF value of C1 and 2 is the practical value.
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Note that the temperature dependency of crystal frequency is a parabolic relationship (ppm / degree
square). The effect of changing the crystal’s frequency when operating at 0°C (25°C below room
temperature) is the same when operating at 50°C (25°C above room temperature).
10.8.3.
RTC Layout Considerations
Since the RTC circuit is very sensitive and requires high accuracy oscillation, reasonable care must be
taken during layout and routing of the RTC circuit. Some recommendations are:
1. Reduce trace capacitance by minimizing the RTC trace length. The ICH4-M requires a trace
length less than 1 inch on each branch (from crystal’s terminal to RTCXn ball). Routing the RTC
circuit should be kept simple to simplify the trace length measurement and increase accuracy on
calculating trace capacitances. Trace capacitance depends on the trace width and dielectric
constant of the board’s material. On FR-4, a 5-mil trace has approximately 2 pF per inch.
2. Trace signal coupling must be limited as much as possible by avoiding the routing of adjacent PCI
signals close to RTCX1 & RTCX2, and VBIAS.
3. Ground guard plane is highly recommended.
4. The oscillator VCC should be clean; use a filter, such as an RC low-pass, or a ferrite inductor.
10.8.4.
RTC External Battery Connections
The RTC requires an external battery connection to maintain its functionality and its RAM while the
ICH4-M is not powered by the system.
Example batteries are Duracell* 2032, 2025, or 2016 (or equivalent), which can give many years of
operation. Batteries are rated by storage capacity. The battery life can be calculated by dividing the
capacity by the average current required. For example, if the battery storage capacity is 170 mAh
(assumed usable) and the average current required is 5 µA, the battery life will be at least:
170,000 µAh / 5 µA = 34,000 h = 3.9 years
The voltage of the battery can affect the RTC accuracy. In general, when the battery voltage decays, the
RTC accuracy also decreases. High accuracy can be obtained when the RTC voltage is in the range of
3.0 V to 3.3 V.
The battery must be connected to the ICH4-M via a Schottky diode circuit for isolation. The Schottky
diode circuit allows the ICH4-M RTC-well to be powered by the battery when the system power is not
available, but by the system power when it is available. To do this, the diodes are set to be reverse
biased when the system power is not available. Figure 73 is an example of a diode circuit that is used.
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Figure 73. Diode Circuit to Connect RTC External Battery
V CCSUS 3_3
VccRTC
1.0uF
1K
A standby power supply should be used in a mobile system to provide continuous power to the RTC
when available, which will significantly increase the RTC battery life and thereby the RTC accuracy.
10.8.5.
RTC External RTCRST# Circuit
Figure 74. RTCRST# External Circuit for the ICH4-M RTC
VCCSUS3_3
DIODE/
BATTERY
CIRCUIT
VccRTC
1.0uF
1K
180K
RTCRST #
0.1uF
RTCRST#
CIRCUIT
The ICH4-M RTC requires some additional external circuitry. The RTCRST# signal is used to reset the
RTC well. The external capacitor and the external resistor between RTCRST# and the RTC battery
(VBAT) were selected to create an RC time delay, such that RTCRST# will go high some time after the
battery voltage is valid. The RC time delay should be in the range of 18 ms - 25 ms. Any resistor and
capacitor combination that yields the proper time constant is acceptable. When RTCRST# is asserted, bit
2 (RTC_PWR_STS) in the GEN_PMCON_3 (General PM Configuration 3) register is set to 1, and
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remains set until software clears it. As a result, when the system boots, the BIOS knows that the RTC
battery has been removed.
This RTCRST# circuit is combined with the diode circuit (shown in Figure 73) whose purpose is to
allow the RTC well to be powered by the battery when the system power is not available. Figure 74 is an
example of this circuitry that is used in conjunction with the external diode circuit.
10.8.6.
VBIAS DC Voltage and Noise Measurements
VBIAS is a DC voltage level that is necessary for biasing the RTC oscillator circuit. This DC voltage
level is filtered out from the RTC oscillation signal by the RC network of R2 and C3 (see Figure 72).
Therefore, it is a self-adjusting voltage. Board designers should not manually bias the voltage level on
VBIAS. Checking VBIAS level is used for testing purposes only to determine the right bias condition of
the RTC circuit.
VBIAS should be at least 200 mV DC. The RC network of R2 and C3 will filter out most of AC signal
noise that exists on this ball. However, the noise on this ball should be kept minimal in order to
guarantee the stability of the RTC oscillation.
Probing VBIAS requires the same technique as probing the RTCX1, RTCX2 signals (using Op-Amp).
See Application Note AP-728 for further details on measuring techniques.
Note: VBIAS is very sensitive to environmental conditions.
10.8.7.
SUSCLK
SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the
quality of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be between
30-70%. If the SUSCLK duty cycle is beyond 30-70% range, it indicates a poor oscillation signal on
RTCX1 and RTCX2.
SUSCLK can be probed directly using normal probe (50- input impedance probe) and it is an
appropriated signal to check the RTC frequency to determine the accuracy of the ICH4-M’s RTC clock
(see Application Note AP-728 for further details).
10.8.8.
RTC-Well Input Strap Requirements
All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER#) must be either pulled up to VCCRTC or
pulled-down to ground while in the G3 state. RTCRST# when configured as shown in Figure 74 meets
this requirement. RSMRST# should have a weak external pull-down to ground and INTRUDER#
should have a weak external pull-up to VCCRTC. This will prevent these nodes from floating in G3, and
correspondingly will prevent ICCRTC leakage that can cause excessive coin-cell drain. The PWROK
input signal should also be configured with an external weak pull-down.
10.9.
Internal LAN Layout Guidelines
The Intel 82801DBM ICH4-M provides several options for LAN capability. The platform supports
several components depending upon the target market. Available LAN components include the Intel
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82540EP Gigabit Ethernet Controller, Intel® 82551QM Fast Ethernet Controller, Intel® 82562ET, and
Intel® 82562EM Platform LAN Connect components.
Table 70. LAN Component Connections/Features
LAN Component
Connection
Features
®
PCI
Gigabit Ethernet
(1000BASE-T) with
Alert Standard Format
(ASF) alerting
Gigabit Ethernet, ASF 1.0
alerting, PCI 2.2 compatible
®
PCI
Performance 10/100
Ethernet with ASF
alerting
Ethernet 10/100 connection,
ASF 1.0 alerting, PCI 2.2
compatible
®
LCI
Advanced 10/100
Ethernet
Ethernet 10/100 connection,
Alert on LAN* (AoL)
®
LCI
Basic 10/100 Ethernet
Ethernet 10/100 connection
Intel 82540EP (196 BGA)
Intel 82551QM (196 BGA)
Intel 82562EM (48 Pin SSOP)
Intel 82562ET (48 Pin SSOP)
NOTE:
10.9.1.
Interface to
ICH4-M
Design guidelines are provided for each required interface and connection.
Footprint Compatibility
The Intel 82540EP Gigabit Ethernet Controller and the Intel 82551QM Fast Ethernet Controller are all
manufactured in a footprint compatible 15 mm x 15 mm (1-mm pitch), 196-ball grid array package.
Many of the critical signal pin locations on the 82540EM and the 82551QM are identical, allowing
designers to create a single design that accommodates any one of these parts. Because the usage of some
pins on the 82540EM differs from the usage on the 82551QM, the parts are not referred to as “pin
compatible.” The term “footprint compatible” refers to the fact that the parts share the same package
size, same number and pattern of pins, and layout of signals. This allows for flexible, cost effective, and
multipurpose design.
Design guidelines are provided for each required interface and connection. Refer to the following
figures and the subsequent table for the corresponding section of this design guide.
Figure 75. Intel 82801DBM ICH4-M/Platform LAN Connect Section
A
Intel®
ICH4
B
82562EM/
82562ET
Magnetic
Module
82551QM
Connector
PCI
82540EP
Refer to the PCI
Specific ation
C
Refer to the selected Intel
LAN component
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Table 71. LAN Design Guide Section Reference
Layout Section
10.9.2.
Figure 75 Reference
Design Guide Section
Intel ICH4-M – LAN Connect Interface (LCI)
A
Reference Section 10.9.2
Intel 82562ET / Intel 82562EM
B
Reference Section 10.9.2
Intel 82551QM / Intel 82540EP
C
Reference Section 10.9.5
®
Intel 82801DBM ICH4-M – LAN Connect Interface Guidelines
This section contains guidelines on how to implement a Platform LAN Connect device on a system
motherboard. It should not be treated as a specification and the system designer must ensure that the
system meets the specified timings. Special care must be given to matching the LAN_CLK traces to
those of the other signals. The following signal lines are used on this interface:
LAN_CLK
LAN_RSTSYNC
LAN_RXD[2:0]
LAN_TXD[2:0]
This interface supports Intel 82562ET and Intel 82562EM components. Signal lines LAN_CLK,
LAN_RSTSYNC, LAN_RXD[0], and LAN_TXD[0] are shared by all components. The AC
characteristics for this interface are found in the Intel® 82801DBM I/O Controller Hub 4 Mobile (ICH4M) Specification Update.
10.9.2.1. Bus Topologies
The Platform LAN Connect Interface can be configured in several topologies:
Direct point-to-point connection between the ICH4-M and the LAN component
LOM Implementation
10.9.2.1.1. LOM (LAN On Motherboard) Point-To-Point Interconnect
The following are guidelines for a single solution motherboard. Either Intel 82562EM or Intel 82562ET
is uniquely installed.
Figure 76. Single Solution Interconnect
L
LAN_CLK
Intel®
ICH4-M
LAN_RSTSYNC
LAN_RXD[2:0]
Platform
LAN
Connect
(PLC)
LAN_TXD[2:0]
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Table 72. LAN LOM Routing Summary
Trace
Impedance
55
± 15%
LAN Routing
Requirements
5 on 10
Maximum Trace
Length
4.5 to 12 inches
Signal
Referencing
Ground
LAN Signal Length
Matching
Data signals must be equal to
or no more than 0.5 inches
(500 mils) shorter than the
LAN clock trace.
10.9.2.2. Signal Routing and Layout
Platform LAN Connect Interface signals must be carefully routed on the motherboard to meet the timing
and signal quality requirements of this interface specification. The following are some general
guidelines that should be followed. Intel recommends that the board designer simulate the board routing
to verify that the specifications are met for flight times and skews due to trace mismatch and crosstalk.
On the motherboard the length of each data trace is either equal in length to the LAN_CLK trace or up
to 0.5 inches shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard
trace in each group.)
Figure 77. LAN_CLK Routing Example
LAN_CLK
LAN_RXD0
10.9.2.3. Crosstalk Consideration
Noise due to crosstalk must be carefully controlled to a minimum. Crosstalk is the key cause of timing
skews and is the largest part of the tRMATCH skew parameter. tRMATCH is the sum of the trace length
mismatch between LAN_CLK and the LAN data signals. To meet this requirement on the board, the
length of each data trace is either equal to or up to 0.5 inches shorter than the LAN_CLK trace.
Maintaining at least 100 mils of spacing should minimize noise due to crosstalk from non-PLC signals.
10.9.2.4. Impedances
The motherboard impedances should be controlled to minimize the impact of any mismatch between the
motherboard. An impedance of 55 ± 15% is strongly recommended; otherwise, signal integrity
requirements may be violated.
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10.9.2.5. Line Termination
Line termination mechanisms are not specified for the LAN connect interface. Slew rate controlled
output buffers achieve acceptable signal integrity by controlling signal reflection, over/undershoot, and
ringback. A 0- to 33- series resistor can be installed at the driver side of the interface should the
developer have concerns about over/undershoot.
Note: The receiver must allow for any drive strength and board impedance characteristic within the specified
ranges.
10.9.2.6. Terminating Unused LAN Connect Interface Signals
The LAN connect interface on the ICH4-M can be left as a no-connect if it is not used.
10.9.3.
Intel 82562ET / Intel 82562EM Guidelines
For correct LAN performance, designers must follow the general guidelines outlined in Section 10.9.6.
Additional guidelines for implementing an Intel 82562ET or Intel 82562EM Platform LAN Connect
component are provided below.
10.9.3.1. Guidelines for Intel 82562ET / Intel 82562EM Component
Placement
Component placement can affect signal quality, emissions, and temperature of a board design. This
section will provide guidelines for component placement. Careful component placement can:
Decrease potential problems directly related to electromagnetic interference (EMI), which could
cause failure to meet FCC and IEEE test specifications.
Simplify the task of routing traces. To some extent, component orientation will affect the
complexity of trace routing. The overall objective is to minimize turns and crossovers between
traces.
Minimizing the amount of space needed for the Ethernet LAN interface is important because all other
interfaces will compete for physical space on a motherboard near the connector edge. As with most
subsystems, the Ethernet LAN circuits need to be as close as possible to the connector. Thus, it is
imperative that all designs be optimized to fit in a very small space.
10.9.3.2. Crystals and Oscillators
To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges.
Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals
should also be kept away from the ethernet magnetics module to prevent interference of communication.
The retaining straps of the crystal (if they should exist) should be grounded to prevent the possibility
radiation from the crystal case and the crystal should lay flat against the PC board to provide better
coupling of the electromagnetic fields to the board.
For a noise free and stable operation, place the crystal and associated discrete components as close as
possible to the Intel 82562ET/EM, keeping the trace length as short as possible and do not route any
noisy signals in this area.
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10.9.3.3. Intel 82562ET / Intel 82562EM Termination Resistors
The 100 ± 1% resistor used to terminate the differential transmit pairs (TDP/TDN) and the 121
± 1% receive differential pairs (RDP/RDN) should be placed as close to the Platform LAN connect
component (Intel 82562ET or Intel 82562EM) as possible. This is due to the fact these resistors are
terminating the entire impedance that is seen at the termination source (i.e. Intel 82562ET), including the
wire impedance reflected through the transformer.
Figure 78. Intel 82562ET / Intel 82562EM Termination
Intel®
ICH4-M
LAN Connect Interface
Intel®
82562ET
Magnetics
Module
RJ45
Place termination resistors as close to the Intel®
82562ET/EM as possible
10.9.3.4. Critical Dimensions
There are two dimensions to consider during layout. Distance A from the line RJ-45 connector to the
magnetics module and distance B from the Intel 82562ET or Intel 82562EM to the magnetics module.
The combined total distances A and B must not exceed 4 inches (preferably, less than 2 inches). See
Figure 79.
Figure 79. Critical Dimensions for Component Placement
B
Intel ®
ICH4-M
Intel®
82562ET/EM
A
Magnetics
Module
Line
RJ45
EEPROM
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Distance
Priority
Guideline
A
1
< 1 inch
B
2
< 1 inch
10.9.3.4.1. Distance from Magnetics Module to RJ-45 (Distance A)
The distance A in Figure 79 above should be given the highest priority in board layout. The distance
between the magnetics module and the RJ-45 connector should be kept to less than one inch of
separation. The following trace characteristics are important and should be observed:
Differential Impedance: The differential impedance should be 100 . The single ended trace
impedance will be approximately 50 ; however, the differential impedance can also be affected by
the spacing between the traces.
Trace Symmetry: Differential pairs (such as TDP and TDN) should be routed with consistent
separation and with exactly the same lengths and physical dimensions (for example, width).
Caution: Asymmetric and unequal length traces in the differential pairs contribute to common mode noise. This
can degrade the receive circuit’s performance and contribute to radiated emissions from the transmit
circuit. If the Intel 82562ET must be placed further than a couple of inches from the RJ-45 connector,
distance B can be sacrificed. Keeping the total distance between the Intel 82562ET and RJ-45 will as
short as possible should be a priority.
Note: Measured trace impedance for layout designs targeting 100 often result in lower actual impedance.
OEMs should verify actual trace impedance and adjust their layout accordingly. If the actual impedance
is consistently low, a target of 105 to 110 should compensate for second order effects.
10.9.3.4.2. Distance from Intel 82562ET / 82562ET to Magnetics Module (Distance B)
Distance B should also be designed to be less than one inch between devices. The high-speed nature of
the signals propagating through these traces requires that the distance between these components be
closely observed. In general, any section of traces that is intended for use with high-speed signals should
observe proper termination practices. Proper termination of signals can reduce reflections caused by
impedance mismatches between device and traces. The reflections of a signal may have a high
frequency component that may contribute more EMI than the original signal itself. For this reason, these
traces should be designed to a 100- differential value. These traces should also be symmetric and equal
length within each differential pair.
10.9.3.5. Reducing Circuit Inductance
The following guidelines show how to reduce circuit inductance in both back planes and motherboards.
Traces should be routed over a continuous ground plane with no interruptions. If there are vacant areas
on a ground or power plane, the signal conductors should not cross the vacant area. This increases
inductance and associated radiated noise levels. Noisy logic grounds should be separated from analog
signal grounds to reduce coupling. Noisy logic grounds can sometimes affect sensitive DC subsystems
such as analog to digital conversion, operational amplifiers, etc. All ground vias should be connected to
every ground plane; and similarly, every power via, to all power planes at equal potential. This helps
reduce circuit inductance. Another recommendation is to physically locate grounds to minimize the loop
area between a signal path and its return path. Rise and fall times should be as slow as possible because
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signals with fast rise and fall times contain many high frequency harmonics that can radiate
significantly. The most sensitive signal returns closest to the chassis ground should be connected
together. This will result in a smaller loop area and reduce the likelihood of crosstalk. The effect of
different configurations on the amount of crosstalk can be studied using electronics modeling software.
10.9.3.5.1. Terminating Unused Connections
In Ethernet designs, it is common practice to terminate unused connections on the RJ-45 connector and
the magnetics module to ground. Depending on overall shielding and grounding design, this may be
done to the chassis ground, signal ground, or a termination plane. Care must be taken when using
various grounding methods to insure that emission requirements are met. The method most often
implemented is called the “Bob Smith” Termination. In this method, a floating termination plane is cut
out of a power plane layer. This floating plane acts as a plate of a capacitor with an adjacent ground
plane. The signals can be routed through 75- resistors to the plane. Stray energy on unused pins is then
carried to the plane.
10.9.3.5.2. Termination Plane Capacitance
Intel recommends that the termination plane capacitance equal a minimum value of 1500 pF. This helps
reduce the amount of crosstalk on the differential pairs (TDP/TDN and RDP/RDN) from the unused
pairs of the RJ-45. Pads may be placed for an additional capacitance to chassis ground, which may be
required if the termination plane capacitance is not large enough to pass EFT (Electrical Fast Transient)
testing. If a discrete capacitor is used, to meet the EFT requirements it should be rated for at least 1000
Vac.
Figure 80. Termination Plane
TDP
N/C
TDN
RDP
RJ-45
RDN
Magnetics Module
Termination Plane
Addition Capacitance that may need to be
added for EFT testing
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10.9.4.
Intel 82562ET/EM Disable Guidelines
To disable the Intel 82562ET/EM, the device must be isolated (disabled) prior to reset (RSM_PWROK)
asserting. Using a GPIO, such as GPO28 to be LAN_Enable (enabled high), LAN will default to
enabled on initial power-up and after an AC power loss. This circuit shown below will allow this
behavior. The BIOS controlling the GPIO can disable the LAN micro-controller.
Note: LAN_RST# needs to be held low for 10ms after power is stable. It is assumed that RSMRST# logic will
provide this delay. Because GPIO28 will default to high during power up, an AND gate has been
implemented to ensure the required delay for LAN_RST# is met.
Figure 81. Intel 82562ET/EM Disable and Power Down Circuitry
3.3V Sus
LAN_RST#
GPIO_LAN_ENABLE
MMBT3906
10K 5%
Intel® 82562EM/ET Disable
10K 5%
There are four pins that can put the Intel 82562ET/EM controller in different operating states: Test_En,
Isol_Tck, Isol_Ti, and Isol_Tex. Table 73 describes the operational/disable features for this design.
The four control signals shown in the below table should be configured as follows: Test_En should be
pulled-down thru a 100- resistor. The remaining three control signals should each be connected
through 100- series resistors to the common node “Intel 82562ET/EM _Disable” of the disable circuit.
Table 73. Intel 82562ET/EM Control Signals
Test_En
Isol_Tck
Isol_Ti
Isol_Tex
State
0
0
0
0
Enabled
0
1
1
1
Disabled w/ Clock (low power)
1
1
1
1
Disabled w/out Clock (lowest power)
In addition, if the LAN Connect Interface of the ICH4-M is not used, the VccLAN1_5 and the
VccLAN3_3 are still required to be powered during normal operating states. It is acceptable to power
the VccLAN1_5 and VccLAN3_3 power pins by the same voltage source that supplies power to the
Vcc1_5 and Vcc3_3 power pins. Also, the LAN_RST# pin of the ICH4-M should be pulled-down to
GND with a 10-k resistor to keep the interface disabled.
10.9.5.
Design and Layout Consideration for Intel 82540EP / 82551QM
For specific design and layout considerations for the Intel 82540EP Gigabit Ethernet Controller and the
Intel 82551QM Faster Ethernet Controller, please refer to the following documents:
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82551QM / 82540EM Interchangeable LOM Design Application Note (AP 432) (Reference
#10565)
82540EP Gigabit Ethernet Controller Networking Silicon Product Preview Datasheet
82540EP Gigabit Ethernet Controller Specification Update
82540EP/82541EI & 82562EZ(EX) Dual Footprint Design Guide Application Note (AP-444)
(Reference# 12504)
10.9.6.
General Intel 82562ET/82562EM/82551QM/82540EP Differential
Pair Trace Routing Considerations
Trace routing considerations are important to minimize the effects of crosstalk and propagation delays
on sections of the board where high-speed signals exist. Signal traces should be kept as short as possible
to decrease interference from other signals, including those propagated through power and ground
planes.
Observe the following suggestions to help optimize board performance.
Note: Some suggestions are specific to a 4.3-mil stack-up.
Maintain constant symmetry and spacing between the traces within a differential pair.
Keep the signal trace lengths of a differential pair equal to each other.
Keep the total length of each differential pair under 4 inches. (Many customer designs with
differential traces longer than 5 inches have had one or more of the following issues: IEEE phy
conformance failures, excessive EMI (Electro Magnetic Interference), and/or degraded receive
BER (Bit Error Rate).)
Do not route the transmit differential traces closer than 100 mils to the receive differential traces.
Do not route any other signal traces both parallel to the differential traces, and closer than 100 mils
to the differential traces (300 mils is recommended).
Keep maximum separation between differential pairs to 7 mils.
For high-speed signals, the number of corners and vias should be kept to a minimum. If a 90° bend
is required, it is recommended to use two 45° bends instead. Refer to Figure 82.
Traces should be routed away from board edges by a distance greater than the trace height above
the ground plane. This allows the field around the trace to couple more easily to the ground plane
rather than to adjacent wires or boards.
Do not route traces and vias under crystals or oscillators. This will prevent coupling to or from the
clock. And as a general rule, place traces from clocks and drives at a minimum distance from
apertures by a distance that is greater than the largest aperture dimension.
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Figure 82. Trace Routing
45
Trace Routing
10.9.6.1.1. Trace Geometry and Length
The key factors in controlling trace EMI radiation are the trace length and the ratio of trace-width to
trace-height above the ground plane. To minimize trace inductance, high-speed signals and signal layers
that are close to a ground or power plane should be as short and wide as practical. Ideally, this trace
width to height above the ground plane ratio is between 1:1 and 3:1. To maintain trace impedance, the
width of the trace should be modified when changing from one board layer to another if the two layers
are not equidistant from the power or ground plane. Differential trace impedances should be controlled
to be approximately 100 . It is necessary to compensate for trace-to-trace edge coupling, which can
lower the differential impedance by up to 10 , when the traces within a pair are closer than 30 mils
(edge to edge).
Traces between decoupling and I/O filter capacitors should be as short and wide as practical. Long and
thin traces are more inductive and reduce the intended effect of decoupling capacitors. Also, for similar
reasons traces to I/O signals and signal terminations should be as short as possible. Vias to the
decoupling capacitors should be sufficiently large in diameter to decrease series inductance.
Additionally, the PLC should not be closer than one inch to the connector/magnetics/edge of the board.
10.9.6.1.2. Signal Isolation
Some rules to follow for signal isolation:
Separate and group signals by function on separate layers if possible. Maintain a gap of 100 mils
between all differential pairs (Ethernet) and other nets, but group associated differential pairs
together.
Note: Over the length of the trace run, each differential pair should be at least 0.3 inches away from any
parallel signal traces.
Physically group together all components associated with one clock trace to reduce trace length and
radiation.
Isolate I/O signals from high speed signals to minimize crosstalk, which can increase EMI emission
and susceptibility to EMI from other signals.
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Avoid routing high-speed LAN traces near other high-frequency signals associated with a video
controller, cache controller, CPU, or other similar devices.
10.9.6.1.3. Magnetics Module General Power and Ground Plane Considerations
To properly implement the common mode choke functionality of the magnetics module the chassis or
output ground (secondary side of transformer) should be separated from the digital or input ground
(primary side) by a physical separation of 100 mils minimum
Figure 83. Ground Plane Separation
0.10 Inches Minimum Spacing
Magnetics Module
Void or Separate
Ground Plane
Separate Chassis Ground Plane
Good grounding requires minimizing inductance levels in the interconnections and keeping ground
returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly
reduce EMI radiation.
Some rules to follow that will help reduce circuit inductance in both back planes and motherboards.
Route traces over a continuous plane with no interruptions (don’t route over a split plane). If there
are vacant areas on a ground or power plane, avoid routing signals over the vacant area. This will
increase inductance and EMI radiation levels.
Separate noisy digital grounds from analog grounds to reduce coupling. Noisy digital grounds may
affect sensitive DC subsystems.
All ground vias should be connected to every ground plane; and every power via should be
connected to all power planes at equal potential. This helps reduce circuit inductance.
Physically locate grounds between a signal path and its return. This will minimize the loop area.
Avoid fast rise/fall times as much as possible. Signals with fast rise and fall times contain many
high frequency harmonics, which can radiate EMI.
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The ground plane beneath the filter/transformer module should be split. The RJ-45 connector side
of the transformer module should have chassis ground beneath it. By splitting ground planes
beneath transformer, noise coupling between the primary and secondary sides of the transformer
and between the adjacent coils in the transformer is minimized. There should not be a power plane
under the magnetics module.
10.9.6.2.
Common Physical Layout Issues
A list of common physical layer design and layout mistakes in LAN on motherboard designs is provide
below:
1. Unequal length of the two traces within a differential pair. Inequalities create common-mode noise
and will distort the transmit or receive waveforms.
2. Lack of symmetry between the two traces within a differential pair. (Each component and/or via
that one trace encounters, the other trace must encounter the same component or a via at the same
distance from the PLC.) Asymmetry can create common-mode noise and distort the waveforms.
3. Excessive distance between the PLC and the magnetics or between the magnetics and the RJ-45
connector. Beyond a total distance of about 4 inches, it can become extremely difficult to design
a spec-compliant LAN product. Long traces on FR4 (fiberglass epoxy substrate) will attenuate the
analog signals. In addition, any impedance mismatch in the traces will be aggravated if they are
longer (see #9 below). The magnetics should be as close to the connector as possible (≤ one inch).
4. Routing any other trace parallel to and close to one of the differential traces. Crosstalk getting
onto the receive channel will cause degraded long cable BER. Crosstalk getting onto the transmit
channel can cause excessive emissions (failing FCC) and can cause poor transmit BER on long
cables. At a minimum, other signals should be kept 0.3 inches from the differential traces.
5. Routing the transmit differential traces next to the receive differential traces. The transmit trace
that is closest to one of the receive traces will put more crosstalk onto the closest receive trace and
can greatly degrade the receiver's BER over long cables. After exiting the PLC, the transmit traces
should be kept 0.3 inches or more away from the nearest receive trace. The only possible
exceptions are in the vicinities where the traces enter or exit the magnetics, the RJ-45, and the
PLC.
6. Use of an inferior magnetics module. The magnetics modules that we use have been fully tested
for IEEE PLC conformance, long cable BER, and for emissions and immunity. (Inferior
magnetics modules often have less common-mode rejection and/or no auto transformer in the
transmit channel.)
7. Use of an 82555 or 82558 physical layer schematic in a PLC design. The transmit terminations
and decoupling are different. There are also differences in the receive circuit. Please follow the
appropriate reference schematic or application note.
8. Not using (or incorrectly using) the termination circuits for the unused pins at the RJ-45 and for
the wire-side center-taps of the magnetics modules. These unused RJ pins and wire-side centertaps must be correctly referenced to chassis ground via the proper value resistor and a capacitance
or termplane. If these are not terminated properly, there can be emissions (FCC) problems, IEEE
conformance issues, and long cable noise (BER) problems. The application notes have schematics
that illustrate the proper termination for these unused RJ pins and the magnetics center-taps.
9.
188
Incorrect differential trace impedances. It is important to have approximately 100- impedance
between the two traces within a differential pair. This becomes even more important as the
differential traces become longer. It is very common to see designs that have differential trace
impedances between 75 and 85 , even when designed for 100 . (To calculate differential
impedance, many impedance calculators only multiply the single-ended impedance by two. This
does not take into account edge-to-edge capacitive coupling between the two traces. When the
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two traces within a differential pair are kept close† to each other, the edge coupling can lower the
effective differential impedance by 5 - 20 . A 10- - 15- drop in impedance is common.)
Short traces will have fewer problems if the differential impedance is a little off.
10. Use of capacitor that is too large between the transmit traces and/or too much capacitance from
the magnetic's transmit center-tap (on the Intel 82562ET side of the magnetics) to ground. Using
capacitors more than a few pF in either of these locations can slow the 100 Mbps rise and fall time
so much that they fail the IEEE rise time and fall time specs. This will also cause return loss to fail
at higher frequencies and will degrade the transmit BER performance. Caution should be
exercised if a cap is put in either of these locations. If a cap is used, it should almost certainly be
less than 22 pF. (6 pF to 12 pF values have been used on past designs with reasonably good
success.) These caps are not necessary, unless there is some overshoot in 100 Mbps mode.
Note: It is important to keep the two traces within a differential pair close† to each other. Keeping them close
(close should be considered to be less than 0.030 inches between the two traces within a differential
pair. 0.007 inch trace-to-trace spacing is recommended) helps to make them more immune to crosstalk
and other sources of common-mode noise. This also means lower emissions (i.e. FCC compliance) from
the transmit traces and better receive BER for the receive traces.
10.10.
Power Management Interface
10.10.1.
SYS_RESET# Usage Model
The System Reset signal (SYS_RESET#) of the ICH4-M can be connected directly to a reset button or
any other equivalent driver in the system where the desired effect is to immediately put the system into
reset. If an ITP700FLEX debug port is implemented on the system, Intel recommends that the DBR#
signal of the ITP interface be connected to SYS_RESET# as well. If SYS_RESET# is implemented, a
weak pull-up resistor pulled-up to the 3.3-V standby rail (VccSUS3_3) should also be implemented to
ensure that no potential floating inputs to SYS_RESET# cause a system reset. The ICH4-M will
debounce signals on this pin (16 ms) and allow the SMBus to go idle before resetting the system. This
delay to allow all outstanding SMBus cycles to complete first and to prevent a slave device on the
SMBus from “hanging” by resetting in the middle of an SMBus cycle.
10.10.2.
PWRBTN# Usage Model
The Power Button signal (PWRBTN#) of the ICH4-M can be connected directly to a power button or
any other equivalent driver (e.g. power management controller) where the desired effect is to indicate a
system request to go to a sleep state (if in a normal operating mode) or to cause a wake event (if in a
sleep state already). This signal is internally pulled-up in the ICH4-M to the 3.3-V standby rail
(VccSUS3_3) through a weak pull-up resistor (20 k nominal). The ICH4-M has 16 ms of internal
debounce logic on this pin.
10.10.3. Power Well Isolation Control Strap Requirements
The RSMRST# signal of the ICH4-M must transition from 20% signal level to 80% signal level and
vice-versa in 50 µs. Slower transitions may result in excessive droop on the VCCRTC node during Sxto-G3 power state transitions (removal of AC power). Droop on this node can potentially cause the
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CMOS to be cleared or corrupted, the RTC to loose time after several AC power cycles, or the intruder
bit might assert erroneously.
The circuit shown in Figure 84 can be implemented to control well isolation between the VccSUS3_3
and RTC power-wells in the event that RSMRST# is not being actively asserted during the discharge of
the standby rail or does not meet the above rise/fall time.
Figure 84. RTC Power Well Isolation Control
No Stuff
MMBT3906
RSMRST#
generation
from MB logic
RSMRST#
ICH4-
10KΩ
BAV99
BAV99
2.2KΩ
No Stuff
10.11.
CPU CMOS Considerations
The Intel 82801DBM ICH4-M has been designed to be voltage compatible with the CMOS signals of
the Mobile Intel Pentium 4 processor and Intel Celeron processor. For these processor-based systems,
the ICH4-M’s V_CPU_IO rail uses the same 1.05-V voltage as the VCCP rails for the processor. It is
important to verify that the voltage requirements of all CPU and ICH4-M signals are compatible with
the FWH as well. See Section 10.7.3 for FWH details. Figure 85 shows a typical interface between the
ICH4-M, CPU, and FWH. See Section 4.3.7.1.6 for recommended topologies and routing guidelines.
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Figure 85. ICH4-M CPU CMOS Signals with CPU and FWH
V_CPU_IO @ 1.05 V
Processor
FERR#
Output Signals
INI
T#
9
ICH4-M
FWH
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11.
Platform Clock Routing Guidelines
11.1.
System Clock Groups
The system clocks are considered a subsystem in themselves. At the center of this subsystem is the
Clock Synthesizer/Driver component. Several vendors offer suitable products, as defined in the Intel
CK408 Synthesizer/Driver Specification. This device provides the set of clocks required to implement a
platform level motherboard solution. Table 74 below provides a breakdown of the various individual
clocks.
Note: When used in 852GME /852PM platforms, the CK408 is configured in the unbuffered mode and a host
clock swing of 710 mV.
Table 74. Individual Clock Breakdown
Comments
Clock Group
Frequency
Driver/Pin
Receiver/s
HOST_CLK
100/133 MHz
CK408
CPU[2:0]
CPU
MCH
Debug Port
Length matched
CK408
3V66[5:0]
MCH
ICH4-M
Length matched
CLK66
66 MHz
AGPCLK
66 MHz
CLK33
33 MHz
CK408
AGP Connector
3V66[5:0]
AGP Controller
CK408
ICH4-M
PCIF[2:0]
Differential signaling
Length matched to CLK66 *
* CLK66 length minus 4.0”
Length matched to CLK66
Synchronous but not edge aligned with CLK66
Phase delay of 1.5 ns to 3.5 ns
33 MHz
PCICLK
(Expansion)
33 MHz
CK408
SIO
PCI[6:0]
FWH
CK408
PCI Conn #1
PCI[6:0]
PCI Conn #2
PCI Conn #3
CLK14
DOTCLK
14 MHz
48 MHz
Length matched to CLK33 *
* CLK33 length minus 2.5”
CK408
ICH4
REF0
SIO
CK408
MCH
Independent clock
MCH
Independent clock
ICH4-M
Independent clock
Independent clock
48MHz
SSCCLK
48/66 MHz
CK408
VCH
USBCLK
48 MHz
CK408
48 MHz
Figure 86 depicts the system clock subsystem including the clock generator, major platform
components, and all the related clock interconnects.
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Figure 86. Clock Distribution Diagram
ITP
CPU
Low Voltage Dif f erential Clocks
100/133 MHz MCH Hostclock
852GME/PM
MCH/GMCH
A
G
P
CLK66
SSC
DOT CLK
SSCCLK
100/133MHz
Outputs
PCICLK
PCICLK
PCICLK
VCH
CLK33
/2
CK408
DI
M
M
DDRCLK s
AGPCLK
100 /133 MHz CPU Hostclock
100/133 MHz Debug Hostclock
DI
M
M
DDR Clocks
Dif f erential Pairs
(133 MHz)
CLK33
66MHz
PCI Slot0
PCI Slot1
PCI Slot2
SIO
FWH
CLK33
48MHz
PLL
14MHz
PLL
CLK66
ICH4
CLK14
Clock Distribution
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USBCLK
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11.2.
Clock Group Topologies and Routing Constraints
The topology diagrams and routing constraint tables provided on the following pages define the
recommended topology and routing rules for each of the platform level clocks. These topologies and
rules have been simulated and verified to produce the required waveform integrity and timing
characteristics for reliable platform operation.
11.2.1.
Host Clock Group
The host clocks are routed point to point as closely coupled differential pairs on the motherboard, with
dedicated buffers for each of the three loads. These clocks utilize a Source Shunt Termination scheme as
shown Figure 87.
Figure 87. Source Shunt Termination Topology
L1
Rs
L2
L4
L1'
Rs
L2'
L4'
L3
CK408
Rt
L3'
Rt
CPU
GMCH
ITP
The clock driver differential bus output structure is a “Current Mode Current Steering” output that
develops a clock signal by alternately steering a programmable constant current to the external
termination resistors Rt. The resulting amplitude is determined by multiplying IOUT by the value of Rt.
The current IOUT is programmable by a resistor and an internal multiplication factor so the amplitude of
the clock signal can be adjusted for different values of Rt to match impedances or to accommodate
future load requirements.
The recommended termination for the differential bus clock is a “Source Shunt termination.” Parallel Rt
resistors perform a dual function, converting the current output of the clock driver to a voltage and
matching the driver output impedance to the transmission line. The series resistors Rs provide isolation
from the clock driver’s output parasitics, which would otherwise appear in parallel with the termination
resistor Rt.
The recommended value for Rt is a 49.9 ohm ± 1% resistor. The tight tolerance is required to minimize
crossing voltage variance. The recommended value for Rs is 33 ± 5%. Simulations have shown that
Rs values above 33 provide no benefit to signal integrity but only degrade the edge rate.
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The MULT0 pin (CK408 pin #43) should be pulled-up through a 10 k to VCC – setting the
multiplication factor to 6. The IREF pin (CK408 pin #42) should be tied to ground through a 475
% resistor – making the IREF 2.32 mA.
±1
Table 75. Host Clock Group Routing Constraints
Parameter
Definition
Class Name
HOST_CLK
Class Type
Individual Differential Pairs
Topology
Differential Source Shunt Terminated
Reference Plane
Ground Referenced (contiguous over length)
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Differential Mode Impedance (Zdiff)
100 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Inner Layer Pair Spacing (edge to edge)
4.0 mils
(except as allowed below)
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Nominal Outer Layer Pair Spacing (edge to edge)
5.0 mils
(except as allowed below)
Minimum Spacing to Other Signals
25 mils
Serpentine Spacing
25 mils
Maximum Via Count
5 (per side)
Series Termination Resistor Value
33 ohms ± 5%
Shunt Termination Resistor Value
49.9 ohms ± 1%
Trace Length Limits – L1 & L1’
Up to 500mils
Trace Length Limits – L2 & L2’
Up to 200 mils
Trace Length Limits – L3 & L3’
Up to 500 mils
Trace Length Limits – L4 & L4’
2.0” to 8.0”
Total Length Range– L1 + L2 + L4
2.0” to 8.5”
Length Matching Required
Yes (Pin to Pad)
Clk to Clk# Length Matching
± 10 mils (per segment)
± 10 mils (overall)
Clock to Clock Length Matching
CPU HCLK = ITP HCLK = (MCH HCLK – 0.25”)
Tolerance = ± 20 mils
Breakout Region Exceptions
No breakout exceptions allowed
NOTES:
1. Differential pairs should be routed as a closely coupled side-by-side pair on a single layer over their entire
length.
2. To minimize skew, Intel recommends that all clocks be routed on a single layer. If clock pairs are to be routed
on multiple layers, the routed length on each layer should be equalized across all clock pairs.
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As specified in the table above, the nominal length of the clock pair terminating at the 852GME GMCH should
be routed 0.25 inches shorter than the other two clock pairs. This is to compensate for a difference in package
length between the CPU and the GMCH.
4. A trace length offset (depends on CK408 vendor clock skew) between CLK66 going to the GMCH (GCLKIN)
and HCLK going to the GMCH (BCLK) is recommended in order to prevent the CLK66 rising edge from
occurring within the +/- 350ps keepout area on either side of the HCLK edge.
3.
11.2.1.1. Host Clock Group General Routing Guidelines
The general guidelines are as follows:
When routing the 100-MHz differential clocks, do not split up the two halves of a differential clock
pair between layers and route to all agents on the same physical routing layer referenced to ground.
If a layer transition is required, make sure that the skew induced by the vias used to transition
between routing layers is compensated in the traces to other agents.
Do not place vias between adjacent complementary clock traces and avoid differential vias. Vias
placed in one half of a differential pair must be matched by a via in the other half. Differential vias
can be placed within length L1, between clock driver and Rs, if needed to shorten length L1.
11.2.1.2. Clock to Clock Length Matching and Compensation
The HCLK pairs to the CPU and GMCH should be matched as close as possible in total length from
CK408 pin to the die-pad of the receiving device. In addition, the L1/L1’ segments of all three clock
pairs should be length matched to within ± 10 mils. Pair to pair overall length matching requires
knowledge of the package lengths of various CPUs, and the GMCH, as well as the effective length of
the CPU socket/interposer if used. This information is provided in table below and Table 76.
Once routing lengths are defined for the CPU and GMCH, match the motherboard length of the ITP
clock pair to the motherboard length of the CPU clock pair.
Parameter
Length
Mobile Intel Pentium 4 processor, Intel Celeron processor
package Length
485 mils
Intel 852GME/852GMV/852PMChipset GMCH package
length
1142 mils
CPU Socket Equivalent Length
157 mils
11.2.1.3. EMI Constraints
Clocks are a significant contributor to EMI and should be treated with care. The following
recommendations can aid in EMI reduction:
Maintain uniform spacing between the two halves of differential clocks.
Route clocks on physical layer adjacent to the VSS reference plane only.
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11.2.2.
CLK66 Clock Group
The 66-MHz clocks are series terminated and routed point to point on the motherboard, with dedicated
buffers for each of the loads. These clocks are all length tuned to match each other and the CLK33
clocks.
Figure 88. CLK66 Clock Group Topology
Rs
L1
L2
GMCH
ICH4
CK408
Table 76. CLK66 Clock Group Routing Constraints
Parameter
Definition
Class Name
CLK66
Class Type
Individual Nets
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Serpentine Spacing
20 mils
Maximum Via Count
4 (per side)
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils (breakout segment)
Trace Length Limits – L2
4.0” to 8.5”
Total Length Range – L1 + L2
4.0” to 9.0”
Length Matching Required
Yes (Pin to Pin)
Clock to Clock Length Matching
± 100 mils CLK66 to CLK66
Breakout Region Exceptions. (Reduced spacing for GMCH &
ICH breakout region)
4 mil trace with 4 mil space in inners
5 mil trace with 5 mil space on outers
Maximum breakout length is 0.3”
NOTES:
1. The overall length of CLK66 is considered the reference length for all other clocks, except USBCLK and CLK14.
The length of this clock should be set within the range and then used as the basis for defining the length of all
other length matched clocks.
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2. A trace length offset (depends on CK408 vendor clock skew) between CLK66 going to the GMCH (GCLKIN)
and HCLK going to the GMCH (BCLK) is recommended in order to prevent the CLK66 rising edge from
occurring within the +/- 350 ps keepout area on either side of the HCLK edge
11.2.3.
Host Clock to CLK66 Routing Recommendations
The rising edge of the HCLK (BCLK) input must either lead or lag the rising edge of CLK66
(GCLKIN) by more than 350 ps at the input balls of the GMCH as measured at the 50% point of each
rising edge. Refer to the following figure for details:
Figure 89. BCLK to GCLKIN Timing Requirement
When assessing whether a system design meets the required BCLK/GCLKIN phase relationship, the
following factors should be taken into account:
Selected clock synthesizer chip’s worst case (minimum) phase relationship between CLK66
(GCLKIN) and HCLKx (BCLK) rising edges. This includes the following clock timing
parameters:
Min phase offset. Since the CK408 spec does not specify the phase offset between CLK66 and
CPUx, the actual worst case (min) offset must be determined by consulting with the selected
clock synthesizer chip's vendor.
Cycle-to-cycle jitter on each clock output. Max jitter is specified by the CK408 clock spec,
but may be less than the max specified for any particular CK408 compatible clock synthesizer
chip.
Trace length difference between BCLK and GCLKIN routing.
Board manufacturing variations affecting signal delay across clock traces.
All relevant variables should be evaluated over the system’s full specified operating temperature
range.
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11.2.4.
CLK33 Clock Group
The 33-MHz clocks are series terminated and routed point to point on the motherboard with dedicated
buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks; however, they
are out of phase due to an internal phase delay in the CK408.
Figure 90. CLK33 Group Topology
Rs
L1
L2
ICH4
SIO, FWH
CK408
Table 77. CLK33 Clock Group Routing Constraints
Parameter
Definition
Class Name
CLK33
Class Type
Individual Nets
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Serpentine Spacing
20 mils
Maximum Via Count
4
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500mils
Trace Length Limits – L2
4.0” to 8.5”
Total Length Range – L1 + L2
CLK66 Length
Length Matching Required
Yes (Pin to Pin)
Clock to Clock Matching
± 100 mils
CLK33 to CLK33 to CLK66
Breakout Region Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
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11.2.5.
PCI Clock Group
The PCI clocks are series terminated and routed point to point as on the motherboard between the
CK408 and the PCI connectors with dedicated buffers for of the three slots. These clocks are
synchronous to the CLK33 clocks and are length tuned to compensate for the segment on the PCI
daughtercard.
Figure 91. PCI Clock Group Topology
Rs
L1
L2
L3
Trace on Card
PCI
Connector
CK408
PCI Device
Table 78. PCICLK Clock Group Routing Constraints
Parameter
Definition
Class Name
PCICLK
Class Type
Individual Nets
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Serpentine Spacing
20 mils
Maximum Via Count
4
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils (breakout segment)
Trace Length Limits – L2
1.5” to 8.0”
Trace Length Limits – L3
2.5” (as per PCI specification)
Total Length Range – L1 + L2 + L3
CLK33 – 2.5” (for nominal matching)
Length Matching Required
Yes (Pin to Pin)
Clock to Clock Length Matching
± 2.0” PCICLK to PCICLK to (CLK33 – 2.5”)
Breakout Region Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
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11.2.6.
CLK14 Clock Group
The 14-MHz clocks are series terminated and routed point to point on the motherboard. A single clock
output is shared between the two loads. These clocks are length tuned to each other but are not
synchronous with any other clocks.
Figure 92. CLK14 Clock Group Topology
Rs
L1
L2A
CK408
ICH4
Rs
L2B
SIO
Table 79. CLK14 Clock Group Routing Constraints
Parameter
Definition
Class Name
CLK14
Class Type
Individual Nets
Topology
Dual Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Serpentine Spacing
20 mils
Maximum Via Count
4 (per driver/receiver path)
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils
Trace Length Limits – L2A, L2B
2.0” to 8.5”
Total Length Range – L1 + L2A & L1 + L2B
2.0” to 9.0”
Length Matching Required
Yes (Pin to Pin)
Clock to Clock Length Matching
± 500 mils
CLK14A to CLK14B
Breakout Region Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
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11.2.7.
DOTCLK Clock Group
The 48-MHz DOTCLK is series terminated and routed point to point on the motherboard. This clock
operates independently and is not length tuned to any other clock.
Figure 93. DOTCLK Clock Topology
Rs
L1
L2
GMCH
CK408
Table 80. DOTCLK Clock Routing Constraints
Parameter
Definition
Class Name
DOTCLK
Class Type
Individual Net
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
25 mils
Maximum Via Count
4
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils
Trace Length Limits – L2
2.0” to 8.0”
Total Length Range – L1 + L2
2.0” to 8.5”
Length Matching Required
No
Breakout Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
NOTES:
1. The DOTCLK is used internally by the GMCH to generate the pixel clock and must exhibit very low jitter. Care
should be taken to avoid routing through noisy areas and spacing rules should be observed. Guard traces may
be employed if necessary with ground stake vias on no less than 0.5-inch intervals.
2. If external graphics is only supported on the platform then dotclock does not need to be connected to GMCH.
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11.2.8.
SSCCLK Clock Group
The 48/66 MHz SSCCLK operates independently and is not length tuned to any other clock. This clock
employs a spread-spectrum device in its path to reduce EMI. The overall clock path is divided into two
segments as shown below with each segment series terminated and routed point to point.
Figure 94. SSCCLK Clock Topology
Rs
L1
L2
SSC
CK408
GMCH
Rs
L3
L4
Table 81. SSCCLK Clock Routing Constraints
Parameter
Definition
Class Name
SSCCLK
Class Type
Individual Net
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Maximum Via Count
4 (per driver/receiver path)
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils
Trace Length Limits – L2
1.0” to 4.0”
Trace Length Limits – L3
Up to 500 mils
Trace Length Limits – L4
1.0” to 7.0”
Total Length Range – L1 + L2 + L3 + L4
3.0” to 8.5”
Length Matching Required
No
Breakout Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
NOTE:
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11.2.9.
USBCLK Clock Group
The 48-MHz USBCLK is series terminated and routed point to point on the motherboard. This clock
operates independently and is not length tuned to any other clock.
Figure 95. USBCLK Clock Topology
Rs
L1
L2
GMCH
CK408
Table 82. USBCLK Clock Routing Constraints
Parameter
Definition
Class Name
USBCLK
Class Type
Individual Net
Topology
Series Terminated Point to Point
Reference Plane
Ground Referenced
Single Ended Trace Impedance ( Zo )
55 ohms ± 15%
Nominal Inner Layer Trace Width
4.0 mils
Nominal Outer Layer Trace Width
5.0 mils (pin escapes only)
Minimum Spacing (see exceptions below)
20 mils
Maximum Via Count
4
Series Termination Resistor Value
33 ohms ± 5 %
Trace Length Limits – L1
Up to 500 mils
Trace Length Limits – L2
3.0” to 12.0”
Total Length Range – L1 + L2
3.0” to 12.5”
Length Matching Required
No
Breakout Exceptions
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3”
11.3.
CK-408 Clock Power Supply Decoupling
See Section 12.7.8 for details.
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11.4.
CK-408 PWRDWN# Signal Connections
The PWRDWN# input of the CK-408 clock chip is required to be driven by both the SLP_S1# and
SLP_S3# signals from the ICH4-M, i.e. the PWRDWN# pin of the CK-408 should be driven by the
output of the logical AND of the SLP_S1# and SLP_S3# signals. This configuration best allows
CPU[2:0] to be tri-stated during S1-M or lower (numerically higher) states.
For systems that do not support S1M but do support the S3 state, the PWRDWN# input of the CK-408
clock chip should be connected to the SLP_S3# output of the ICH4-M. It is not recommended that
PWRDWN# be pulled-up to the CK-408’s 3.3-V power supply if the S3 state is the second highest,
power consuming state supported by the platform (i.e. S1M and S2 not supported). The advantage of
using SLP_S3# rather than the 3.3-V supply to qualify PWRDWN# is that it reduces the likelihood of
the CK-408 clocks driving into unpowered components and potentially damaging the clock input
buffers. Also SLP_S3# can help reduce power consumption because it will be asserted before the 3.3-V
supply will be shut off, thus minimizing the amount of time that the clocks will be left toggling.
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12.
Platform Power Delivery Guidelines
12.1.
Definitions
S0 / Full-On operation. During Full-On operation, all components on the motherboard are powered
and the system is fully functional.
S1-M / Power-On-Suspend (POS, Mobile). In the mobile implementation of the Power-OnSuspend state, the outputs of the clock chip stopped in order to save power. All components remain
powered but may or may not be in a low power state.
S3 / Suspend-To-RAM (STR). In the STR state, the system state is stored in main memory and all
unnecessary system logic is turned off. Only main memory and logic required to wake the system
remain powered.
S4 / Suspend-To-Disk (STD). In the STD state, the system state is stored in non-volatile secondary
storage (e.g. a hard disk) and all unnecessary system logic is turned off. Only logic required to
wake the system remain powered. Standby power rails may or may not be powered depending on
system design and the presence of AC or battery power.
S5 / Soft-Off. The Soft-Off state corresponds to the G2 state. Restart is only possible with the
power button.
Full-Power operation. During Full-Power operation, all components remain powered. Full-power
operation includes both Full-On and the S1M (CPU Stop-Grant state).
Suspend operation. During suspend operation, power is removed from some components on the
motherboard. 852GME chipset-based systems can be designed to support a number of suspend
states such as Power-On-Suspend (S1M), Suspend-to-RAM (S3), Suspend-to-Disk (S4), and SoftOff (S5).
Core power rail. A power rail that is only on during full-power operation. These power rails are on
when the PSON signal is asserted to the ATX power supply.
Standby power rail. A power rail that in on during suspend operation (these rails are also on during
full-power operation). These rails are on at all times (when the power supply is plugged into AC
power). The only standby power rail that is distributed directly from the ATX power supply is: 5
VSB (5 V Standby). There are other standby rails that are created with voltage regulators on the
motherboard.
Derived power rail. A derived power rail is any power rail that is generated from another power
rail using an on-board voltage regulator. For example, 3.3 VSB is usually derived (on the
motherboard) from 5 VSB using a voltage regulator.
Dual power rail. A dual power rail is derived from different rails at different times (depending on
the power state of the system). Usually, a dual power rail is derived from a standby supply during
suspend operation and derived from a core supply during full-power operation. Note that the
voltage on a dual power rail may be misleading.
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12.2.
Platform Power Requirements
Figure 96 below shows the power delivery architecture for an example
852GME/852GMV/852PMchipset platform. This power delivery architecture supports the “Instantly
Available PC Design Guidelines” via the S3 system state. To ensure that enough power is available
during S3, a thorough power budget should be completed. The power requirements should include each
device’s power requirements, both in suspend and in Full-On. The power requirements should be
compared against the power budget supplied by the power supply. Due to the requirements of main
memory and PCI 3.3 Vaux (and possibly other devices in the system), it is necessary to create a dual
power rail.
The solutions given in this document are only examples. There are many power distribution methods
that achieve similar results. It is critical, when deviating from these examples, to consider the effect of
the change.
Figure 96. Platform Power Delivery Architectural Block Diagram
Processor
VCC_CORE = IMVP-V
System Bus
400 MT/S
AGP/DVO
+V1.5S
852GME/PM
CRT
VCCP = IMVP-V
2.1 - 2.7 GB/s
DDR266 x 2
DDR333 x 2
+V1.25
+V2.5
+V1.5S
+V3.3S
+V2.5
LVDS
+V1.5
+V2.5
8 -Bit Hub
Interface
266MB/s
USB
ICH4-M
+V3.3
+V5 Al way s
+V3.3S
+V1.5 Alway s
+V1.5LAN
ATA 66/100
IDE
PCI Bus
+V3.3S
+V3.3 Alway s
+V3.3LAN
+V5S
+VCC_RTC
+V3.3S
+V5S
208
FWH
VCC_IO = IMVP-V
+V1.5S
Moon2
+V5S
AC97
CardBus
LAN
+V3.3
+V3.3Al way s
+V5
+V3.3
+V3.3
SMC
SIO
KBC
+V3.3Al way s
+V3.3S
+V3.3Al way s
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12.3.
Voltage Supply
12.3.1.
Power Management States
Table 83. Power Management States
Signal
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
+V*ALW
+V*
+V*S
Clocks
FULL ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1M (POS)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (STR)
LOW
LOW
HIGH
HIGH
ON
ON/OFF
OFF
OFF
S4 (STD)
LOW
LOW
LOW
HIGH
ON
ON/OFF
OFF
OFF
S5 (Soft Off)
LOW
LOW
LOW
LOW
ON
ON/OFF
OFF
OFF
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12.3.2.
Power Supply Rail Descriptions
Table 84. Power Supply Rail Descriptions
Signal Names
Voltage
(V)
Current
(A)
Tolerance
Enable
Description
+V1_25
1.25
0.01
± 3.2%
SLP_S4# - HIGH
DDR Termination
+V1_5
1.5
0.03
± 5%
SLP_S4# - HIGH
LAN logic
+V1_5S
1.5
1.35
± 5%
SLP_S3# - HIGH
GMCH DVO-Core, DLVDS,
DAC, ALVD, ICH4-M core,
VCCHL
+V1_5ALWAYS
1.5
0.1
± 5%
+V3ALWAYS
ICH4-M Resume
+V2_5
2.5
8.12
± 5%
SLP_S4# - HIGH
GMCH DDR I/O, LVDS
DDR SO-DIMM
210
+V3ALWAYS
3.3
0.4
± 5%
+VDC_ON
ICH4-M Resume, SMC/KBC,
AC’97
+V3
3.3
0.9
± 5%
SLP_S5# - HIGH
ICH4-M resume I/O & LAN I/O,
Cardbus, AC’97, RS232
+V3S
3.3
7.0
± 5%
SLP_S3# - HIGH
ICH4-M I/O, CK-408, FWH,
SIO, AC’97, IDE
+V5
5
9.0
± 5%
SLP_S5# - HIGH
USB, AC’97, HDD, DVD, CDROM, +V2_5, +V1_25
+V5S
5
1.0
± 5%
SLP_S3# - HIGH
ICH4-M, MSE/KBD, FDD, IDE
+V5ALWAYS
5
3.0
± 5%
+VDC
USB Supply
+V12S
12
0.2
± 5%
SLP_S3# - HIGH
Cardbus
+VCC_CORE
IMVP-V
TBD
IMVP-V
+VCC_VID -HIGH
See IMVP-V Design Guide for
detail
+VCCP
IMVP-V
TBD
IMVP-V
+VCC_VID
See IMVP-V Design Guide for
detail
+VCC_VID
1.2
TBD
IMVP-V
VR_ON
See IMVP-V Design Guide for
detail
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12.4.
852GME/852GMV/852PMGMCH/ICH4-M Platform
Power-Up Sequence
Figure 97 describes the power-on timing sequence for a GMCH / ICH4-M-based platform.
Figure 97. GMCH / ICH4-M Platform Power-Up Sequence
System
State
G3
G3
S5
S4
S3
S0
S0 state
Hub interface "CPU
Reset Complete"
message
STPCLK#,
CPUSLP#
T186
T184
Frequency
Straps
Strap Values
Normal Operation
T185
PCIRST#
T178
T181
SUS_STAT#
T177
PWROK, VGATE
T176
Vcc
SLP_S3#
T183b
T181
T18 3a
SLP_S4#
T183
SLP_S5#
Running
SUSCLK
T182
RSMRST#,
RSM_PWROK
T173
VccSus
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Table 85. Timing Sequence Parameters for Figure 97
Symbol
Description
Min
Max
Units
Notes
Fig
T173
VccSus supplies active to RSMRST#
inactive
5
-
ms
Figure 97
T175b
VccLAN supplies active to LAN_RST#
active
10
-
ms
Figure 97
T176
Vcc supplies active to PWROK, VGATE
active
10
-
ms
Figure 97
T177
PWROK and VGATE active and
SYS_RESET# inactive to SUS_STAT#
inactive
32
38
RTCCLK
Figure 97
T178
SUS_STAT# inactive to PCIRST# inactive
1
3
RTCCLK
Figure 97
T181
VccSus active to SLP_S5#, SUS_STAT#
and PCIRST# active
50
ns
Figure 97
T182/T183
RSMRST# inactive to SUSCLK running,
SLP_S5# inactive
110
ms
T183a
SLP_S5# inactive to SLP_S4# inactive
1
2
RTCCLK
Figure 97
T183b
SLP_S4# inactive to SLP_S3# inactive
1
2
RTCCLK
Figure 97
T184
Vcc active to STPCLK#, CPUSLP#,
STP_CPU#, STP_PCI#, SLP_S1#,
C3_STAT# inactive, and CPU Frequency
Strap signals high
50
ns
Figure 97
T185
PWROK and VGATE active and
SYS_RESET# inactive to SUS_STAT#
inactive and CPU Frequency Straps
latched to strap values
32
38
RTCCLK
2
Figure 97
T186
CPU Reset Complete to Frequency Straps
signals unlatched from strap values
7
9
CLK66
3
Figure 97
1
Figure 97
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
2. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
3. This transition is clocked off the 66-MHz CLK66. 1 CLK66 is approximately 15 ns.
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Figure 98. Power On Sequencing Timing Diagram (VR Circuitry)
BCLK
Vcc
PWRGOOD
T9
T10
RESET#
VCCVID
T7
T8
VID_GOOD
VID[4:0]
Table 86. Timing Sequence Parameters for Figure 98
Sym
12.4.1.
Description
T7
VCCVID > 1V to VID_GOOD high
T8
VID_GOOD to Vcc valid maximum time
T9
PWRGOOD inactive pulse width
T10
PWRGOOD to RESET# deassertion time
Min
Max
1
Units
Notes
Fig
us
Figure 98
ms
Figure 98
10
BCLKS
Figure 98
1
ms
Figure 98
50
ICH4-M Power Sequencing Requirements
12.4.1.1. 3.3 V/1.5 V Power Sequencing
No power sequencing requirements exist for the associated 3.3 V/1.5 V rails of the Intel ICH4-M. It is
generally good design practice to power up the core before or at the same time as the other rails.
12.4.1.2. V5REF/ 3.3 V Sequencing
V5REF is the reference voltage for 5-V tolerance on inputs to the Intel ICH4-M. V5REF must be powered
up before VCC3_3, or after VCC3_3 within 0.7 V. Also, V5REF must power down after VCC3_3, or before
VCC3_3 within 0.7 V. It must also power down after or simultaneous to VCC3_3. These rules must be
followed in order to ensure the safety of the Intel ICH4-M. If the rule is violated, internal diodes will
attempt to draw power sufficient to damage the diodes from the VCC3_3 rail. Figure 99 shows a sample
implementation of how to satisfy the V5REF/ 3.3 V sequencing rule.
This rule also applies to the stand-by rails, but in most platforms, the VCCSUS3_3 rail is derived from the
VCCSUS5 and therefore, the VCCSUS3_3 rail will always come up after the VCCSUS5 rail. As a result,
V5REF_SUS will always be powered up before VCCSUS3_3. In platforms that do not derive the VCCSUS3_3 rail
from the VCCSUS5 rail, this rule must be comprehended in the platform design.
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Figure 99. Example V5REF / 3.3 V Sequencing Circuitry
12.4.1.3. V5REF_SUS Design Guidelines
In order to meet reliability and testing requirements for the USB interface, the following design
recommendations for the V5REF_SUS pins of the ICH4-M should be followed. Changes to the USB
specification regarding continuous short conditions must be addressed. The USB 1.1 specification
requires host controllers to withstand a continuous short between the USB 5-V connector supply to a
USB signal at the connector for an unspecified duration of time. Also, the USB 2.0 specification
requires a host controller to withstand a short between the USB 5-V connector supply to a USB signal at
the connector for 24 hours. The recommendation is to provide a 5V_ALWAYS (active S0-S5) supply to
the V5REF_SUS pins if available (see Figure 100). If such a supply rail is not readily available on the
platform, then an alternative implementation using a 3.3V_ALWAYS (active S0-S5) and a VCC5
(active S0-S1M) or VCCSUS5 (active S0-S3) rail can be used instead (see Figure 101).
Figure 100. V5REF_SUS with 5V_ALWAYS Connection Option (Recommended)
5V_ALWAYS
Customer specific or
Intel recommended
USB power circuit
V5REF_SUS1
V5REF_SUS2
0.1uF
ICH4-M
USB D+
USB D-
USB Power (5V)
Customer specific or
Intel recommended
USB interface
circuits
GND
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Figure 101. V5REF_SUS with 3.3V_ALWAYS and VCC5 or VCC5_SUS Connection Option
VCC5 or VCCSUS5
Customer specific or
Intel recommended
USB power circuit
3.3V_ALWAYS
D1*
V5REF_SUS1
V5REF_SUS2
D2*
USB Power (5V)
0.1uF
ICH4-M
USB D+
USB D-
Customer specific or
Intel recommended
USB interface
circuits
USB D+
USB D-
GND
Note: D1 and D2 are BAT54 or Equivalent Schottky Diodes
12.4.2.
GMCH Power Sequencing Requirements
No GMCH power sequencing requirements exist for the 852GME / 852PM GMCH platform. All
GMCH power rails should be stable before deasserting reset, but the power rails can be brought up in
any order desired. Good design practice would have all GMCH power rails come up as close in time as
possible, with the core voltage coming up first.
The ICH4-M’s CPUPWRGOOD output represents the logical AND of its PWROK and VGATE inputs.
When VGATE is asserted, it indicates that core power and the PCICLK are stable and PCIRST# will be
de-asserted a minimum of 1 ms later. It is the responsibility of the system designers to ensure that the
power and timing requirements for the processor and GMCH are met.
12.4.3.
DDR Power Sequencing Requirements
No DDR-SDRAM power sequencing requirements are specified during power up or power down if the
following criteria are met:
VDD and VDDQ are driven from a single power converter output.
VTT is limited to 1.44 V (reflecting VDDQ(max)/2 + 50 mV VREF variation + 40 mV VTT
variation)
VREF tracks VDDQ/2
A minimum resistance of 42 (22 series resistor + 22
the input current from the VTT supply into any pin.
parallel resistor ± 5% tolerance) limits
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If the above criteria can not be met by the system design, then Table 87 below must be adhered to during
power up.
Table 87. DDR Power-Up Initialization Sequence
Voltage Description
12.4.4.
Sequencing
Voltage Relationship to Avoid Latch-up
VDDQ
After or with VDD
< VDD + 0.3 V
VTT
After or with VDDQ
< VDDQ + 0.3 V
VREF
After or with VDDQ
< VDQ + 0.3 V
PWR ICH4-M SYS_RESET# Signal
The Intel ICH4-M has a new signal called ICH4-M SYSRST#. This signal is an input to the ICH4-M
and provides a way to activate a system reset. In previous designs with ICH3-M, system reset logic was
often tied into PWROK, forcing an asynchronous reset. For a cleaner design, Intel recommends that
system reset logic such as a debug port reset signal and/or a reset button, if used, be connected to this
signal. SYS_RESET# provides an intelligent way to reset the system since it will wait up to 25 ms ± 2
ms for SMBus traffic to idle before initiating a system reset. Not only will some combinational logic
that may have been needed for PWROK be unnecessary—reset button debounce circuitry is also not
needed as the ICH4-M has this built-in. SYS_RESET# is in the resume I/O well of the ICH4-M and so
circuitry connected to this signal must also be on the resume, or always on, rail.
12.5.
DDR Power Delivery Design Guidelines
The main focus of these GMCH guidelines is to minimize signal integrity problems and improve the
power delivery to of the GMCH system memory interface and the DDR SO-DIMMs. This document is
not the original source for these specifications. Refer to the following documents for the latest details on
voltage and current requirements found in this design guide.
JEDEC Standard, JESD79, Double Data Rate (DDR) SDRAM Specification
Intel DDR 20 JEDEC Spec Addendum Rev 0.9 or later
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Figure 102. DDR Power Delivery Block Diagram
+V5
Switching
Regulator
Vin
+V2_5
Vout
Sense Adj.
10K
10K
+
SMVREF
-
+V5
Switching
Regulator
Vin
Vout
+V1_25
Sense Adj.
12.5.1.
DDR Interface Decoupling Guidelines
The following decoupling recommendations for the DDR system memory interface are subject to
change.
12.5.1.1. GMCH VCCSM Decoupling Guidelines
Every GMCH ground and VCCSM power ball in the system memory interface should have its own via.
For the VCCSM pins of the GMCH, a minimum of eleven, 0603 form factor, 0.1- , high frequency
capacitors is required and must be placed within 150 mils of the GMCH package. The eleven capacitors
should be evenly distributed along the GMCH DDR system memory interface and must be placed
perpendicular to the GMCH with the power (2.5 V) side of the capacitors facing the GMCH. The trace
from the power end of the capacitor should be as wide as possible and it must connect to a 2.5-V power
ball on the outer row of balls on the GMCH. Each capacitor should have their 2.5-V via placed directly
over and connected to a separate 2.5-V copper finger, and they should be as close to the capacitor pad as
possible, within 25 mils. The ground end of the capacitors must connect to the ground flood and to the
ground plane through a via. This via should be as close to the capacitor pad as possible, within 25 mils,
and with as thick a trace as possible.
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12.5.1.2. DDR SO-DIMM System Memory Decoupling Guidelines
Discontinuities in the DDR signal return paths will occur when the signals transition between the
motherboard and the SO-DIMMs. To account for this ground to 2.5-V discontinuity, a minimum of nine
0603 0.1-µF high frequency bypass capacitors is required between the SO-DIMMs to help minimize any
anticipated return path discontinuities that will be created. The bypass capacitors should be connected to
2.5 V and ground. The ground trace should connect to a via that transitions to the ground plane. The
ground via should be placed as close to the ground pad as possible. The 2.5-V trace should connect to a
via that transitions to the 2.5-V copper flood and it should connect to the closet 2.5-V SO-DIMM pin on
either the first o second SO-DIMM connector, with a wide trace. The capacitors 2.5-V traces should be
distributed as evenly as possible amongst the two SO-DIMMs. Finally, the 2.5-V via should be placed as
close to the 2.5-V pad as possible.
12.5.2.
2.5-V Power Delivery Guidelines
The 2.5-V power for the GMCH system memory interface and the DDR SO-DIMMs is delivered around
the DDR command, control, and clock signals. Special attention must be paid to the 2.5-V copper
flooding to ensure proper GMCH and SO-DIMM power delivery. This 2.5-V flood must extend from
the GMCH 2.5-V power vias all the way to the 2.5-V DDR voltage regulator and its bulk capacitors,
located at the end of the DDR channel beyond the second SO-DIMM connector. The 2.5-V DDR
voltage regulator must connect to the 2.5-V flood with a minimum of six vias, and the SO-DIMM
connector 2.5-V pins as well as the GMCH 2.5-V power vias must connect to the 2.5-V copper flood.
The copper flooding to the GMCH should include at least seven fingers to allow for the routing of the
DDR signals and for optimal GMCH power delivery. The copper fingers must be kept as wide as
possible in order to keep the loop inductance path from the 2.5-V voltage regulator to the GMCH at a
minimum. In the areas where the copper flooding necks down around the GMCH make sure to keep
these neck down lengths as short as possible. The 2.5-V copper flooding under the SO-DIMM
connectors must encompass all the SO-DIMM 2.5-V pins and must be sold except for the small areas
where the clocks are routed within the SO-DIMM pin field where they connect to their specified SODIMM pins.
Additionally, a small 2.5-V copper flood shape should be placed under the GMCH to encompass and
increase the copper flooding to the back row of the 2.5-V GMCH pins. This flood must not be placed
under any of the DDR signals. In order to maximize the copper flooding, these signals should be kept as
short as possible in order to reduce the amount of serpentining needed in this area on the bottom layer.
Also, a minimum of 12-mil isolation spacing should be maintained between the copper flooding and the
DDR signals. Finally, the six, GMCH, 2.5-V, high-frequency decoupling capacitors located on the top
signal layer should have their 2.5-V via placed directly over and connected to a separate 2.5-V copper
finger.
12.5.3.
DDR Reference Voltage
Table 88, Table 89, and Table 90 group the voltage and current specifications together for the memory,
GMCH, and termination voltage respectively. There are three voltages specified for a DDR VR system.
Although there are only two unique voltage regulators for 2.5 V and 1.25-V nominal, each specific
power rail described here has a unique specification.
For convenience, tolerances are given in both % and volts though validation should be done using the
spec exactly as it is written. If this states a tolerance in terms of volts (e.g. VREF says ± 0.025 V), then
that specific voltage tolerance should be used, not a percentage of the measured value. Likewise,
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percentages should be used where stated. If not stated, then either way is fine. Voltage specs are defined
as either “Absolute” or “Relative.” These are described in Table 88.
Note: VREF to SO_DIMM and GMCH should stay on during S3 state on all 852 chipset families.
Table 88. Absolute vs. Relative Voltage Specification
Type of Specification
Description
Absolute Specification
This is a standard specification most commonly used. This means that
the voltage limits are based on a fixed nominal voltage and have a
symmetric ± tolerance added to determine the acceptable voltage
range. For example, a VDD spec does not depend on any other
voltage levels. It is simply 2.5 V ± 8%.
Relative Specification
This is a specification whose nominal value is not fixed but is relative
to or is a function of another voltage. This means that the other
voltage must be measured to know what the nominal value is and
then the symmetrical ± tolerance added to that measured value. For
example, a VREF spec depends on the actual value of VDD to
determine VDD/2 and then tolerance ± 0.050 V from this calculated
value.
In the following three tables, only the 2.5-V supply is a fixed, absolute specification, whereas all of the
1.25-V nominal supplies are relative to the 2.5-V supply directly or another 1.25-V supply, which is
then relative to the 2.5-V supply. Due to these 1.25-V relative specifications, it is important that the
1.25-V supply can track the variations in the 2.5-V supply and respond according to the 2.5-V
variations. This can be implemented as shown in the block diagram in Figure 102 where the 2.5-V
output is divided in half and used to generate the 1.25-V reference into the 1.25-V, VR controller
design. In this manner, the 1.25-V VR will respond proportionally to variations in the 2.5-V supply,
improving the voltage margin of the relative supply requirements and overall memory system stability.
As of publication of this document, all specifications were current. However, it is realized that the
current specifications are considered to be higher than actually expected and will be reduced in future
specifications.
Table 89. DDR-SDRAM SO-DIMM Voltage and Current Requirements
Parameter
Symbol
Unit
Definition
Minimum
Nominal
Maximum
Core Supply
Voltage, Static
Vdd
Volts, V
Vdd
2.3
2.5
2.7
I/O Supply
Voltage, Static
VddQ
Volts, V
VddQ
2.3
2.5
2.7
Core Supply
Current, Static
Idd
Amperes, A
5.0
I/O Supply
Current, Static
IddQ
Amperes, A
0.920
Absolute I/O
Reference Supply
Voltage, Static
VREF
Volts, V
I/O Reference
Supply Current,
Static
Iref
Amperes, A
Vdd/2 + 0.05 V
Vdd/2 – 0.05
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Table 90. Intel GMCH System Memory Voltage and Current Requirements
Parameter
Symbol
Unit
GMCH DDR Supply
Voltage (I/O), Static
VCCSM
Volts, V
GMCH DDR Supply
Current, Static
Ivccsm
Amperes, A
Intel GMCH
Reference Supply
Voltage, Static
SMVREF
Volts, V
Intel GMCH
Reference Supply
Current, Static
Isdref
Amperes, A
SMRCOMP
Termination Supply
Voltage, Static
Vtt
Volts, V
SMRCOMP
Termination Supply
Current, Static
Ittrc
Amperes, A
Definition
VCCSM
Minimum
2.375
Nominal
2.5
Maximum
2.625
2.8
VCCSM/2 +
2%
VCCSM/2 –
2%
VCCSM/2
VCCSM/2
+ 2%
0.01
SMVref + 0.04
V
SMVref – 0.04
SMVref
SMVref +
0.04
0.025
Table 91. Termination Voltage and Current Requirements
Parameter
Symbol
Unit
Termination Supply
Voltage, Static
Vtt
Volts, V
Termination Supply
Current, Static
Itt
Amperes, A
Minimum
SMVref – 0.04V
Nominal
SMVref
Maximum
SMVref + 0.04V
2.4
12.5.3.1. SMVREF Layout and Routing Recommendations
There is one SMVREF pin on the 852GME / 852PM GMCH that is used to set the reference voltage
level for the DDR system memory signals (SMVREF_0). The reference voltage must be supplied to the
SMVREF pin. The voltage level that needs to be supplied to this pin must be equal to VCCSM/2. Note
in Figure 102 that although SMVREF is generated from the 2.5-V supply, a buffer is used as well. A
buffer has also been used to provide this reference to the system for the GMCH and memory. This is the
“VREF” signals to the DDR memory devices and the “SMVREF” signals (SMVREF_0) to the GMCH.
The reference design utilizes this buffer to provide the necessary current to these devices, which a
simple voltage divider is not capable of providing. The reference voltage supplied to SMVREF has the
tightest tolerance in the memory system of ± 2%. A simple resistor divider is not a voltage regulator and
is most definitely not a current source. Any current drawn across the resistor divider used to generate
this 1.25-V reference will cause a voltage drop across the top resistor, which distorts or biases this
reference to a lower voltage. The clarification below summarizes SMVREF.
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Table 92. GMCH System Memory I/O SMVREF Calculation
Name
VCCSM
PURPOSE
1
SMVREF
GMCH DDR SUPPLY VOLTAGE (I/O), GMCH REFERENCE SUPPLY
STATIC
VOLTAGE, STATIC
VCCSM
SMVREF = (VCCSM ± 5%) / 2
VOLTAGE Nominal (V)
2.500 "± 5%"
1.250 "± 2%"
TOLERANCE (±V)
0.125
0.025
Vmax(V)
2.625
1.275
Vmin(V)
2.375
1.225
Ivccsm (max)
Isdref (max)
1.400
0.010
Imax (A)
NOTE:
GMCH VREF REQUIREMENTS: the GMCH core is called "VCCSM" =+2.5 V ± 5%. SMVREF is ("VCCSM"±
5%)/2 ± 2%. Whether the 2.5 V is 5% high or low, the voltage needs to be divided by 2 with a 2% accuracy.
Therefore, use 1% resistors or better.
As shown in Table 92, the max current required by the GMCH for the SMVREF input is 0.010 A. This
is too big of a load for a resistor divider. Some sample calculations are shown in Table 93; it is
impossible to maintain regulation within 2% using a resistive divider without using a resistor so small
that the 2.5-V current requirement becomes prohibitive. Hence, a buffer is required due to the 10-mA
current requirement of the GMCH SMVREF.
Table 93. Effects of Varying Resistor Values in the Divider Circuit
Rdivider
( )
Leakage
(A)
Rtop Vdroop
(V)
I(2.5) total = 2.5 V/2R
(A)
1
0.01
0.01
1.25
10
0.01
0.1
0.125
100
0.01
1
0.0125
1000
0.01
10
0.00125
10000
0.01
100
0.000125
100000
0.01
1000
1.25E-05
1000000
0.01
10000
1.25E-06
NOTES:
1. Rdivider: This is the resistor value selected to form the divider. Assumes both top and values are equal as
required for divide by 2.
2. Leakage: This is the amount of leakage current which needs to sourced from the 2.5-V supply, across the
divider’s top resistor (Rtop) and out to the GMCH SMVREF input or the DDR VREF input. This current does not
go across the bottom resistor.
3. Rtop Vdroop: This is the resulting voltage droop across Rtop as a result of the leakage current.
4. I(2.5) total = 2.5 V/2R. This is the total current through divider. This is calculated to consider the amount of
current & power used as a DC current through the divider.
5. The implementation of a buffer is also required by the DDR. The same VREF may be used for both GMCH and
the DDR as well.
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12.5.3.2. DDR VREF Requirements
Making the same calculations for the DDR loading, the max VREF load is 1 mA; therefore, a divider is
STILL NOT feasible as the load of 1 mA causes unacceptable drop across even a small Rs, which
wastes power.
Table 94. DDR VREF Calculation
Name
Vdd
Vref
Purpose
Core Supply Voltage, Static
I/O Reference Supply Voltage, Static
Vdd
Vref = (Vdd=/-8%) / 2
2.500 (± 8%)
1.250
Tolerance (+/-V)
0.200
0.025
Vmax(V)
2.700
1.300
Vmin(V)
2.300
1.200
Idd
Iref
5.000
0.001
VOLTAGE Nominal (V)
RDDP spec says
NOTE:
The DDR core is called "Vdd" =+2.5 V ±8% (=± 0.2 V). VREF is ("Vdd"± 8%)/2 ± 50 mV. Whether the 2.5 V is
8% high or low, that voltage must be able to be divided by 2, within 50-mV accuracy. Therefore, use 1%
resistors or better.
Table 95. Reference Distortion Due to Load Current
NOTE:
12.5.4.
R( )
I(A)
Vdroop(V)
I(2.5) total=2.5 V/2R(A)
1
0.001
0.001
1.25
10
0.001
0.01
0.125
100
0.001
0.1
0.0125
1000
0.001
1
0.00125
10000
0.001
10
0.000125
100000
0.001
100
1.25E-05
1000000
0.001
1000
1.25E-06
As for the GMCH, a calculation can be made for the DDR. This shows that even with the slight load of 1 mA
by the DDR, it is still not feasible to use a simple resistor divider. Using the max leakage specs provided and
trying to maintain an error of less than 1% (12.5 mV), one needs to decrease the resistor values such that
the current just to source the divider becomes unacceptable. A divider alone does not become an acceptable
solution until current requirements are in the 100-µA range. Today, it is not possible to guarantee this type of
current requirement for these applications. Therefore, the use of a buffer is highly recommended for these
reference voltage requirements.
DDR SMRCOMP Resistive Compensation
The 852GME / 852PM GMCH requires a system memory compensation resistor, SMRCOMP, to adjust
buffer characteristics to specific board and operation environment characteristics. Refer to the Intel®
852GME Chipset GMCH and Intel® 852PM Chipset MCH Datasheet and Figure 103 for details on
resistive compensation.
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Figure 103. DDR SMRCOMP Resistive Compensation
+V2.5
0.1 µF
60.4Ω +/- 1%
SMRCOMP
60.4Ω +/- 1%
The GMCH’s system memory resistive compensation mechanism also requires the generation of
reference voltages to the SMVSWINGL and SMVSWINGH pins with a value of 1/3*VCCP. The
schematic for SMVSWINGL and SMVSWINGH voltage generation is illustrated in
Figure 104. Two resistive dividers with R1a = R2b = 150 ± 1% and R1b = R2a = 604 ± 1%
generate the SMVSWINGL and SMVSWINGH voltages. SMVSWINGL and SMVSWINGH
components should be placed within 0.5 inches of their respective pins and connected with a 15-mil
wide trace. To avoid coupling with any other signals, maintain a minimum of 25 mils of separation to
other signals.
Figure 104. SMVSWINGL and SMVSWINGH Reference Voltage Generation Circuit
+VCCSM
+VCCSM
R1a
R1b
150
604
SMVSWiNGL
0.1 µF
12.5.5.
SMVSWINGL
SMVSWINGH
SMVSWiNGH
R2a
R2b
604
150
MCH/GMCH
0.1 µF
DDR VTT Termination
The recommended topology for DDR-SDRAM Data, Control, and Command signal groups requires that
all these signals to be terminated to a 1.25-V source, VTT, at then end of the memory channel opposite
the GMCH. A solid 1.25-V termination island should be used to for this purpose. The VTT termination
island should be placed on the top signal layer, just beyond the last SO-DIMM connector and must be at
least 50-mils wide. The Data and Command signals should be terminated using one resistor per signal.
Resistor packs and ± 5% tolerant resistors are acceptable for this application. Only signals from the
same DDR signal group can share a resistor pack. See Section 12.5.1 and Section 12.7 for details on
high frequency and bulk decoupling requirements.
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12.6.
Clock Driver Power Delivery Guidelines
Special care must be taken to provide a quiet VDDA supply to the Ref VDD, VDDA, and the 48-MHz
VDD. These VDDA signals are especially sensitive to switching noise induced by the other VDDs on
the cock chip. They are also sensitive to switching noise generated elsewhere in the system such as the
CPU VRM. The CLC pi-filter should be designed to provide the best reasonable isolation. Intel
recommends that a solid ground plane be underneath the clock chip on Layer 2. (Assuming top trace is
Layer 1.) Intel also recommends that a ground flood be placed directly under the clock chip to provide a
low impedance connection for the VSS pins.
For ALL power connections to planes, decoupling capacitors and vias, the maximum trace width
allowable and shortest possible lengths should be used to ensure lowest possible inductance. The
decoupling capacitors should be connected as shown in the illustration taking care to connect the VDD
pins directly to the VDD side of the capacitors. However, the VSS pins should not be connected directly
to the VSS side of the capacitors. Instead they should be connected to the ground flood under the part
that is via’ed to the ground plane. This is done to avoid VDD glitches propagating out and getting
coupled through the decoupling capacitors to the VSS pins. This method has been shown to provide the
best clock performance.
The ground flood should be via’ed through to the ground plane with no less than 12-16 vias under the
part. It should be well connected. For all power connections, heavy duty and/or dual vias should be
used. It is imperative that the standard signal vias and small traces not be used for connecting
decoupling capacitors and ground floods to the power and ground planes. VDDA should be generated
by using a CLC pi-filter. This VDDA should be connected to the VDD side of the three capacitors that
require it using a hefty trace on the top layer. This trace should be routed from the CLC pi-filter using a
star topology.
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Figure 105. Decoupling Capacitors Placement and Connectivity
VddA
Vdd
XTAL_In
XTAL_Out
Vss
C1
Vs
s
1
56
2
55
54
3
4
Vdd
PCIF 1
6
51
CPU
/0
PCIF 2
7
50
Vdd
8
49
CPU
1
48
CPU
/1
9
PCI 0
10
PCI 1
11
47
46
12
Vss
C5
45
CPU
2
44
Vdd
14
43
Mult
0
42
IRE
F
PCI 4
16
PCI 5
17
PCI 6
18
Vdd
19
Vss
PWRD
WN#
20
21
41
40
39
38
37
36
S2
US
B
48
MHz
DO
T
48
MHz
Vss
48 MHz
3V66_1 /
VCH
23
34
PCI_Sto
p#
24
33
3V66
_0
25
Vd
SCL
Vdd
32 Vss
Kd
Vss
A
27
28
31
VddA
Vdd
48 MHz
35
26
Vdd
Vss Iref
22
Vdd
A
Vtt_Pwr
gd #
Vs
s
Gr
ou
nd
Flo
od
Vss
Vdd
13
15
Vdd
Vss
PCI 3
Vss
C6
Vdd
CPU
/2
66Buff0
/ 3V66_2
66Buf
/f1
3V66_
66Buf
3
/f2
3V66_
4
66In /
3V66_5
VddA
CPU_Sto
p#
CPU
0
Vdd
Vss
53
52
PCI 2
C3
Vss Plane Vias
S0
5
Vdd
Vss
S1
PCIF 0
Vss
C2
REF
0
Vs
s
30
SCL
K
29
SDAT
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Vdd
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12.7.
Decoupling Recommendations
Intel recommends proper design and layout of the system board bulk and high frequency decoupling
capacitor solution to meet the transient tolerances for each component. To meet the component transient
load steps, it is necessary to properly place bulk and high frequency capacitors close to the component
power and ground pins.
12.7.1.
Processor Decoupling Guidelines
Table 96. Processor Decoupling Recommendation
Signal
Configuration
F
Qty
VCC[VCC_IMVP]
Tie to VCC
680uF
9
VCC[VCC_CORE]
Tie to VCC
22uF
14
VCC[VCC_CORE]
Tie to VCC
680uF
9
Notes
Nine X 680uF, 8 m
Note: Decoupling guidelines are recommendations based on Intel’s reference board design. Layout and PCB
board design must be considered when deciding on overall decoupling solution.
12.7.2.
Intel 852GME/852GMV/852PMGMCH Decoupling Guidelines
Bulk decoupling is based on VR solution used on the CRB design. Table 97 below outlines the
minimum GMCH decoupling requirements.
Table 97. GMCH Decoupling Recommendations
Pin Name
Configuration
F
Qty
Type
Notes
VCC
Tie to VCC1_5S
0.1 µF
4
XR7, 0603, 16 V, 10%
1 X 0.1 µF with in 200mils
10 µF
1
XR5, 1206, 6.3 V, 20%
3 X 0.1 µF on bottom side
150 µF
2
SPC, E, 6.3 V, 20%
0.1 µF
2
XR7, 0603, 16 V, 10%
10 µF
1
XR5, 1206, 6.3 V, 20%
150 µF
1
SPC, E, 6.3 V, 20%
VTTLF
Tie to VCCP
2 X 0.1 µF on bottom side
VTTHF
Tie to GND
0.1 µF
5
XR7, 0603, 16 V, 10%
VCCHL
Tie to VCC1_5S
0.1 µF
2
XR7, 0603, 16 V, 10%
1 X 0.1 µF with in 200 mils
10 µF
1
XR5, 1206, 6.3 V, 20%
1 X 0.1 µF on bottom side
0.1 µF
11
XR7, 0603, 16 V, 10%
100 µF
2
TANT, D, 10 V, 20%
10 X 0.1 µF with in 200
mils
VCCSM
Tie to VCC2_5
1 X 0.1 µF on bottom side
VCCDVO
226
Tie to VCC1_5S
0.1 µF
2
XR7, 0603, 16 V, 10%
1 X 0.1 µF with in 200 mils
10 µF
1
XR5, 1206, 6.3 V, 20%
1 X 0.1 µF on bottom side
150 µF
1
SPC, E, 6.3 V, 20%
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Pin Name
Configuration
F
Qty
Type
Notes
Tie to VCC1_5S
0.1 µF
1
XR7, 0603, 16 V, 10%
1 X 0.1 µF with in 200 mils
22 µF
1
TANT, B, 10 V, 20%
47 µF
1
TANT, D, 10 V, 20%
0.1 µF
3
XR7, 0603, 16 V, 10%
1 X 0.1 µF with in 200 mils
22 µf
1
TANT, B, 10 V, 20%
2 X 0.1 µF on bottom side
47 µF
1
TANT, D, 10 V, 20%
0.1 µF
1
XR7, 0603, 16 V, 10%
SMVREF
0.1 µF
1
XR7, 0603, 16 V, 10%
SMVSWINGL
0.1 µF
1
XR7, 0603, 16 V, 10%
SMVSWINGH
0.1 µF
1
XR7, 0603, 16 V, 10%
HDVREF
220 pF
1 µF
3
3
XR7, 0603, 25 V, 10%
XR5, 0603, 6.3 V, 20%
HAVREF
0.1 µF
1
XR7, 0603, 16 V, 10%
HCCREF
0.1 µF
1
XR7, 0603, 16 V, 10%
HXVSWING
0.1 µF
1
XR7, 0603, 16 V, 10%
VCCDLVDS
1
VCCTXLVDS
1
VCCGPIO
NOTE:
12.7.3.
Tie to VCCSus2_5
Tie to Vcc3_3S
1 X 0.1 µF on bottom side
If designing with external graphics decoupling are not required. Still need to connect the power pins.
Intel ICH4-M Decoupling Guidelines
The Intel ICH4-M is capable of generating large current swings when switching between logic high and
logic low. This condition could cause the component voltage rails to drop below specified limits. To
avoid this type of situation, ensure that the appropriate amount of bulk capacitance is added in parallel to
the voltage input pins. Intel recommends that the developer use the amount of decoupling capacitors
specified in Table 98 to ensure the component maintains stable supply voltages. The capacitors should
be placed as close to the package as possible (100 mils nominal). Rotate caps that set over power planes
so that the loop inductance is minimized (see Figure 106). The basic theory for minimizing loop
inductance is to consider which voltage is on Layer 2 (power or ground) and spin the decoupling cap
with the opposite voltage towards the BGA (Ball Grid Array). This greatly minimizes the total loop
inductance. Intel recommends that for prototype board designs the designer include pads for extra
power plane decoupling caps.
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Figure 106. Minimized Loop Inductance Example
Copper
Plane
Under BGA
Trace
connecting
Pad to Via
Decoupling
Cap
BGA
BALL
GND
Ball
BGA
S
PWR
Ball
BGA
BALL
Layer 1
4.5 mils nominal
Layer 2
PWR
PAD
Layer 3
48 mils nominal
GND
GND
Layer 4
VIA
Current Flow to Decoupling Cap
Table 98. Decoupling Requirements for the Intel ICH4-M
Pin
Decoupling
Requirements
Decoupling Type (Pin type)
Decoupling Placement
VCC3_3
(6) 0.1 µF
Decoupling Cap (Vss)
Place near balls: A4, A1, H1, T1,
AC10, and AC18
VCCSUS3_3
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: A22 and AC5
VCCLAN3_3
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: E9 and F9
V_CPU_IO
(1) 0.1 µF
Decoupling Cap (Vcc)
Place near ball: AA23
VCC1_5
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: K23 and C23
VCCSUS1_5
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: A16 and AC1
VCCLAN1_5
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: F6 and F7
V5REF
(1) 0.1 µF
Decoupling Cap (Vcc)
Place near ball: E7
V5REF_SUS
(1) 0.1 µF
Decoupling Cap (Vss)
Place near ball: A16
VCCRTC
(1) 0.1 µF
Decoupling Cap (Vcc)
Place near ball: AB5
VCCHI
(2) 0.1 µF
Decoupling Cap (Vss)
Place near balls: T23 and N23
VCCPLL
(1) 0.1 µF
Decoupling Cap (Vcc)
Place near ball: C22
(1) 0.01 µF
NOTES:
1. Capacitors should be placed less than 100 mils from the package.
2. ICH4 -M balls listed in the “Decoupling Placement” guidelines column may not necessarily correlate to a VCC
power ball and may include signal balls from different interfaces.
12.7.4.
DDR VTT High Frequency and Bulk Decoupling
The VTT Island must be decoupled using high-speed bypass capacitors, one 0603, 0.1-µF capacitor per
two DDR signals. These decoupling capacitors connect directly to the VTT island and to ground, and
must be spread out across the termination island so that all the parallel termination resistors are near
high frequency capacitors. The capacitor ground via should be as close to the capacitor pad as possible,
within 25 mils with as thick a trace as possible. The ground end of the capacitors must connect to the
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ground flood on Layer 2 and to the ground plane on Layer 3 through a via. Finally, the distance from
any DDR termination resistor pin to a VTT capacitor pin must not exceed more then 100 mils.
12.7.5.
Hub Interface Decoupling
See Section 9.4 for details.
12.7.6.
FWH Decoupling
A 0.1-µF capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple
high frequency noise, which may affect the programmability of the device. Additionally, a 4.7-µF
capacitor should be placed between the VCC supply pins and the VSS ground pins to decouple low
frequency noise. The capacitors should be placed no further than 390 mils from the VCC supply pins.
12.7.7.
General LAN Decoupling
All VCC pins should be connected to the same power supply.
All VSS pins should be connected to the same ground plane.
Four to six decoupling capacitors, including two 4.7-µF capacitors are recommended
Place decoupling as close as possible to power pins.
12.7.8.
CK-408 Clock Driver Decoupling
The decoupling caps should be connected taking care to connect the VDD pins directly to the VDD side
of the caps. However, the VSS pins should not be connected directly to the VSS side of the caps.
Instead, they should be connected to the ground flood under the part that is via’ed to the ground plane.
This is done to avoid VDD glitches propagating out and getting coupled through the decoupling caps to
the VSS pins. This method has been shown to provide the best clock performance.
The decoupling requirements for a CK-408 compliant clock synthesizer are as follows:
One 10-µF bulk decoupling cap in a 1206 package placed close to the VDD generation circuitry.
Six 0.1-µF high frequency decoupling caps in a 0603 package placed close to the VDD pins on the
CK-408.
Three 0.1-µF high frequency decoupling caps in a 0603 package placed close to the VDDA pins on
the CK-408.
One 10-µF bulk decoupling cap in a 1206 package placed close to the VDDA generation circuitry
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12.8.
Intel 852GME/852GMV/852PMGMCH Analog Power
Delivery
12.8.1.
Analog Supply Filter Requirements
Table 99 summarizes the eight analog circuits that require filtered supplies on the 852GME / 852PM
GMCH. The analog circuits are:
VCCASM
VCCQSM
VCCAHPLL
VCCADPLLA
VCCADPLLB
VCCADAC
VCCAGPLL
VCCALVDS
Note: VCCADAC, VCCAHPLL, VCCAGPLL, and VCCALVDS do not require an RLC filter but do require
decoupling capacitors.
Figure 107. Example Analog Supply Filter
Low Pass Filtering
*RDAMP
L
Filtered VCC
VCC
Noise
CBULK
CHIGH
*RDAMP is not required for all
filters
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Table 99. Analog Supply Filter Requirements
Required
852GME /
852PM Filters
Rdamp
Rdamp
Location
IVCCASM
None
N/A
VCCQSM
1
VCCAHPLL
1210 1 µH DCRmax
s
0.169
Cbulk
Chigh
100 µF
0603 0.1 µF X5R
In series with
capacitor
0805 0.68 µH DCRmax 0.80
s
1206 4.7 µF
X5R
0603 0.1 µF X5R
N/A
None
None
0603 0.1 µF X5R
1
1
In series with
inductor
0805 0.10 µH
220 µF
0603 0.1 µF X5R
VCCADPLLB
1
In series with
inductor
0805 0.10 µH
220 µF
0603 0.1 µF X5R
VCCADPLLA
1
None
N/A
None
None
0603 0.1 µF X5R
0603 0.01 µF X5R
VCCAGPLL
None
N/A
None
None
0603 0.1 µF X5R
None
N/A
None
None
0603 0.1 µF X5R
VCCADAC
VCCALVDS
NOTE:
12.8.2.
None
L
2
If designing with external graphics decoupling is not required. Still need to connect power pin.
Recommended Routing/Component Placement
Recommended routing/component placement is as follows:
Each filter inductor and capacitors should be placed as close to the GMCH as possible.
If possible, route a trace from the VSSADAC and VSSALVDS balls to the capacitor before
terminating to ground.
12.9.
Intel 852GME/852GMV/852PMMaximum Supply Current
Numbers
Table 100 shows the preliminary Intel 852GME / 852PM GMCH maximum supply current estimates.
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Table 100. Icc Maximum Sustained Estimates (Icc REV0.3)
12.10.
Platform Component
Performance 133Gfx/400/533 FSB/266DDR
2 SO-DIMMs/4 Rows
1.5 V Core
1.4 A
1.5 V LVDS (Digital)
0.07 A
1.5 V DAC & LVDS (Analog)
0.07 A
1.5 V DVO
0.09 A
2.5 V LVDS I/O
0.05 A
1.5 V GTL
TBD
3.3 V GPIO
N/A
1.5 V HUBLink
0.09 A
1.2 V DDR DLLs
0.40 A
2.5 V DDR
2.07 A
Intel ICH4-M Power Consumption Numbers
Table 101 shows the preliminary Intel ICH4-M power consumption estimates.
Table 101. Intel ICH4-M Power Consumption Measurements
Power Plane
Maximum Power Consumption
S0
S1-M
S3
S4/S5
G3
1.5 V Core
500 mA
85 mA
N/A
N/A
N/A
3.3 V I/O
480 mA
0.44 mA
N/A
N/A
N/A
1.5 V LAN
11.25 mA
11.25 mA
0 mA
0 mA
N/A
3.3 V LAN
0.6 mA
0.6 mA
1.5 V SUS
79 mA
46 mA
8 mA
8 mA
N/A
3.3 V SUS
166 mA
0.7 mA
0.06 mA
0.06 mA
N/A
N/A
N/A
N/A
N/A
5 µA
V_CPU_IO
2.5 mA
2.5 mA
N/A
N/A
N/A
Vcc HI (HI 1.5 – 1.5V)
99 mA
99 mA
N/A
N/A
N/A
V5REF
10 µA
10 µA
N/A
N/A
N/A
V5REF_SUS
10 µA
10 µA
10 µA
10 µA
10 µA
VCCRTC
0 mA
N/A
NOTES:
1. 3.3-V SUS and 1.5-V SUS assume 6 high-speed ports populated.
2. Vcc HI power consumption is dependent on the Hub Interface being used
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12.11.
Thermal Design Power
The thermal design power is the estimated maximum possible expected power generated in a component
by a realistic application. It is based on extrapolations in both hardware and software technology over
the life of the product. It does not represent the expected power generated by a power virus. The thermal
design power numbers for the 852GME/ 52PM GMCH and Intel ICH4-M are listed below.
Table 102. Intel 852GME/852GMV/852PMGMCH Component Thermal Design Power
852GME/852GMV/852PMGMCH - Thermal Design Power Consumption Dissipation (estimated)
852GME/852GMV/852PMGMCH
3.8 W (maximum)
Table 103. Intel ICH4-M Component Thermal Design Power
Intel ICH4 - Thermal Design Power Consumption Dissipation (estimated)
Intel ICH4-M
2.2 W (maximum)
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13.
Test Signals
The Mobile Intel Pentium 4 processor and 852GME/852GMV/852PMGMCH may have signals listed as
“RSVD”, “NC”, or other name whose functionality is Intel reserved. The following section contains
recommendations on how these Intel reserved signals on the processor or GMCH should be handled.
13.1.
Mobile Intel Pentium 4 Processor Reserved Signals
The Mobile Intel Pentium 4 processor has NC and TESTHI signals that are Intel reserved in the pinmap. For connection recommendations on the TESTHI signals, refer to the latest Mobile Intel®
Pentium® 4 Processor Datasheet or Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading
Technology on 90-nm process technology. All NC signals must remain unconnected.
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13.2.
Intel 852GME / 852PM GMCH RSVD Signals
The Intel 852GME / 852PM GMCH has a total of 32 RSVD and 12 NC signals that are Intel reserved in
the pin-map. The recommendation is to provide test points for all RSVD signals. All NC signals should
be left as no connects. The location of the Intel reserved signals in the GMCH pin-map is listed in Table
104.
Table 104. GMCH “Intel Reserved” Signal Pin-Map Locations
Signal Name
Ball Name
Signal Name
Ball Name
NC
AJ29
RSVD
J5
NC
AH29
RSVD
H2
NC
B29
RSVD
H1
NC
A29
RSVD
H3
NC
AJ28
RSVD
H4
NC
A28
RSVD
H5
NC
AA9
RSVD
K6
NC
AJ4
RSVD
L5
NC
AJ2
RSVD
F12
NC
A2
RSVD
D12
NC
AH1
RSVD
B12
NC
B1
RSVD
AA5
RSVD
AA22
RSVD
L4
RSVD
L3
RSVD
F3
RSVD
J3
RSVD
D3
RSVD
J2
RSVD
B3
RSVD
K5
RSVD
F2
RSVD
K1
RSVD
D2
RSVD
H6
RSVD
C2
RSVD
G3
RSVD
B2
RSVD
K3
RSVD
D7
RSVD
K2
RSVD
J6
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14.
Platform Design Checklist
This checklist provides design recommendation and guidelines for Intel 852GME/PM chipset platform
for use with the Mobile Intel Pentium 4 processor and Intel Celeron processor. This checklist highlights
design considerations that should be reviewed prior to manufacturing a motherboard that implements the
852GME/PM chipset. The items contained in this checklist address important connections to these
devices and critical supporting circuitry. This is not a complete list, and it does not guarantee that a
design will function properly.
Note: Unless otherwise specified the default tolerance on resistors is ± 5%.
Note: The (S) reference after power rails such as VCC3_3 (S) indicates a switched rail - one that is powered
off during S3-S5. This work is ongoing, and the recommendations and considerations herein are subject
to change.
14.1.
General Information
The following section should be filled out by the OEM or Intel field representative.
Processor
Processor Min Frequency targeted for this platform
Processor Max Frequency targeted for this platform
Voltage Regulator Solution
Part#/Vendor:
Target ICC(max):
Target Thermal Envelope (Watts)
Battery Life
Target:
Form Factor
Panel Vendor and Size
Part#/Vendor:
Backlight Inverter
Part#/Vendor:
DVO Device
Part#/Vendor:
LOM or mini-PCI LAN?
Wireless Solution?
Target FCS (First Customer Ship) Date
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14.2.
Customer Implementation of Voltage Rails
Fill in schematic name of voltage rails and mark boxes of when rails are powered on.
Name of Rail
On S0-S1
On S3
On S4
On S5
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14.3.
Design Checklist Implementation
The voltage rail designations in this design checklist are as general as possible. The following table
describes the equivalent voltage rails in the Intel CRB schematics.
Checklist Rail
Intel CRB Rail
On S0-S1
Vcc1_25
+V1.25S [DDR_Vtt]
X
Vcc1_5
+V1.5S_GMCH_CORE,
X
On S3
On S4
On S5
Notes
4
+V1.5S_GMCH_HUB,
+V1.5S_GMCH_DVO/AGP,
+V1.5S_GMCH_ALVDS,
+V1.5S_GMCH_ADAC,
+V1.5S_GMCH_DLVDS,
+V1.5S_ICH,
+V1.5S_ICHHUB
+V1.5S_GMCH_HGPLL,
+V1.5S GMCH DPLL,
+V1.5_ICHLAN
VccSus1_5
X
X
V1_5ALWAYS
+V1.5A_ICH
X
X
VccSus2_5
+V2.5_GMCH_SM,
X
X
1,3
X
X
+V2.5_GMCH_QSM,
+V2.5_GMCH_TXLVDS,
Vcc3_3
+V3.3S_ICH,
X
+V3.3S_GMCH_GPIO,
+V3.3S_CLKRC,
+V3.3S_SPD,
+V3.3S_LVDS,
VccSus3_3
+V3.3_ICHLAN,
X
1,2,3
+V3.3_LAN
238
V3ALWAYS
+V3.3ALWAYS_ICH
X
Vcc5
+V5S_DAC
X
X
X
X
VccSus5
+V5_USB
X
X
V5ALWAYS
+V5A_ICH
X
X
X
X
Vcc12
+V12S
X
VccRTC
+V_RTC
X
X
X
X
VCC
+VCC_IMVP
X
VCCIOPLL
+VCC_IMVP
X
VCCA
+VCC_IMVP
X
1,3
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Checklist Rail
Intel CRB Rail
On S0-S1
Vcc1_25
+V1.25S [DDR_Vtt]
X
VccCORE
+VCC_CORE
X
On S3
On S4
On S5
Notes
4
NOTES:
1. A rail powered in Sx is dependent on implementation.
2. VccLANx rail is powered on in Sx is dependent on implementation.
3. xALWAYS rail can be the SUS rail depending on implementation.
4. Vcc1_25 is the 1.25 V VTT rail for DDR.
Pin Name
System
Pull-up/Pull-down
Series
Termination
Voltage
Translation
A20M#
Notes
9
Point-to-point connection to ICH4-M.
BR0#
220 pull-up to
VCC
Point-to-point connection to GMCH,
with resistor placed by GMCH.
COMP[1:0]
61.9 ± 1% pulldown to gnd
Resistor placed within 0.5” of
processor pin. Trace should be at
least 25 mils.
DPSLP#
Point-to-point connection to GMCH.
FERR#
56
pull-up to VCC
GTLREF[3:0]
GTLREF needs to
be 63% of VCC
Point-to-point connection to ICH4-M,
with resistor placed by ICH4-M.
Voltage divider should be placed
within 0.5” of processor pin. Place 1µF cap by the resistor divider, 220
pF by the processor pin. Minimum
one GTLREF pin require to be
connected as recommended above.
51.1
± 1% pull-up
to VCC
86.6 ± 1% pulldown to gnd
GHI#
300 pull-up to
VCC
Point-to-point connection to ICH4-M.
IERR#
56
IERR# is a 1.05-V signal. Voltage
translation logic may be required if
used.
pull-up to VCC
INIT#
R1 = 2 k
R2 = 300
Rs = 300
Point-to-point connection to ICH4-M.
Voltage transition circuit is required if
connecting to FWH. Signal is T-split
from the ICH4-M to FWH.
See Figure 108.
IGNNE#
Point-to-point connection to ICH4-M.
LINT0/INTR
Point-to-point connection to ICH4-M.
LINT1/NMI
Point-to-point connection to ICH4-M.
PROCHOT#
100-k
VCC
pull up to
R1 = 1.3 k
R2 = 330
Rs = 330
Please refer to CRB schematic for
more datials.
If Voltage Translation is Required:
Driver isolation resistor should be
placed at the beginning of the T-split
to the system receiver. The receiver
at the output of the voltage
translation circuit can be any
receiver that can function properly
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Pin Name
System
Pull-up/Pull-down
Series
Termination
Voltage
Translation
Notes
9
with the PROCHOT# signal.
See Figure 110.
BOOTSELEC
T
Connects to CPU VR module. This
pin will shift load line depends on
Processor. Please refer to IMVP-5
specification for more information.
OPTIMIZED/C
OMPAT#
Please refer to Processor Datasheet
for resistor recommendation.
PWRGOOD
300 pull-up to
VCC
RESET#
51
pull-up to VCC
If USING
ITP700FLEX
150
from
pull-up to
ITP700FLEX
If ITP700FLEX is Not Used: Pointto-point connection to GMCH.
If ITP700FLEX is Used: RESET#
connects from processor to GMCH
and then forks out to ITP700 FLEX,
with pull-up and series damping
resistor placed next to ITP.
SLP#
Point-to-point connection to ICH4-M.
SMI#
Point-to-point connection to ICH4-M.
STPCLK#
Point-to-point connection to ICH4-M.
TESTHI[5:0],
TESTHI[10:8]
56
pull up to VCC
THERMTRIP#
56
pull-up to VCC
VCC[85:0]
Connect to VCC
VCCA, VSSA,
VCCIOPLL
Connect to VCC via
filter
VCCSENSE,
VSSSENSE
Connect to test vias
VSS[182:0]
Connect to gnd
NOTE:
240
Point-to-point connection to ICH4-M,
with resistor placed by the
processor.
Point-to-point connection to ICH4-M,
with resistor placed by ICH4-M.
THERMTRIP# is a VCC signal. If
connecting to other device, voltage
translation logic may be required.
Please refer to Figure 109
Default tolerance for resistors is ± 5% unless otherwise specified.
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Figure 108. Routing Illustration for INIT#
Figure 109. VCCIOPLL, VCCA and VSSA Power Distribution
-
+VCC
1
VCCA
33uF
VSSA
2
10uH 10%
1
VCCIOP
2
10uH 10%
Processor
Figure 110. Voltage Translation Circuit for PROCHOT#
3.3V
3.3V
1.3K
+/-5%
330
From Driver
+/-5%
Rs
R1
330
R2
+/-5%
To Receiver
Q2
3904
Q1
3904
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14.4.
In Target Probe (ITP)
Pin Name
System Pull-up /
Pull-down
BPM[5:0]#
51
DBR#
150-240 pull-up to
V3ALWAYS
RESET#
51
Series Termination
Resistor (
pull-up to VCC
pull-up to VCC
If USING ITP700FLEX
If using ITP on interporser card,
then DBR# should also be
connected to DBRESET pin at the
processor.
150
from pull-up to
ITP700FLEX
Connect to TCK pin of processor.
27.4
gnd
TDI
150
TDO
75
TMS
39.2
VCC
± 1% pull-up to
Connect to processor, with resistor
placed by ITP.
TRST#
680
pull-down to gnd
Connect to processor.
VTAP,
VTT[1:0]
Connect to VCC
± 1% pull-down to
Connect to processor, with resistor
placed by ITP.
pull-up to VCC
Connect to processor, with resistor
placed by Processor.
pull-up to VCC
Connect to processor, with resistor
placed by ITP. If ITP not used, this
signal can be left as NC.
One 0.1-µF decoupling cap is
required.
The above recommendation is only for ITP700FLEX. If using other ITP, please refer to the appropriate ITP
documents.
Decoupling Recommendations
Signal
Configuration
Value
Qty
Notes
VCC[Vcc_Core]
Connect to VCC
22 µF
14
X5R/X7R, 1206 package. Use for high
frequency decoupling. Bulk decoupling
will depend on the VR solution. The
maximum Equivalent Series Resistance
should be equal to or less than 2.5 m
VCC[Vcc_Core]
Connect to VCC
9
680 µF
NOTE:
242
See Note 1
TCK
NOTE:
9
Connect to processor, with resistors
placed by the processor.
FBO
14.5.
Notes
9
Nine X 680 µF, 8 m
Decoupling guidelines are recommendations based on our reference board design. Customers will need to
take layout & PCB board design into consideration when deciding on overall decoupling solution.
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14.6.
Power-up Sequence
Sym
Timing Parameters
Min
Ta
VccVID active to VID_GOOD
Tb
VID_GOOD valid to Vcc active
Tc
BCLK stable to PWRGOOD active
10
Td
PWRGOOD active to RESET# inactive
1
NOTE:
Max
1
50
10
Unit
Notes
ms
Please refer to the
Processor Datasheet. See
Figure 111.
ms
Please refer to the
Processor Datasheet. See
Figure 111.
BCLKs
Please refer to the
Processor Datasheet. See
Figure 111.
ms
Please refer to the
Processor Datasheet. See
Figure 111.
9
Please refer to latest processor datasheet.
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Figure 111. Mobile Intel Pentium 4 Processor Power Up Sequence
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14.7.
CK-408 Clock Checklist
14.7.1.
Resistor Recommendations
Pin Name
System
Pull-up/Pull-down
3V66[0]
Series
Resistor
9
Notes
33
If the signal is used, one 33-ohm
series resistor is required. If the signal
is NOT used, it should be left as NC
(Not Connected) or connected to a test
point.
33
Use 66 BUF[1] (pin 22) for GMCH.
Use one of the other two signals for
ICH4-M.
33
Use one pair for the processor and
another pair for GMCH. If on-board
ITP is implemented, the third pair of
clock signals is used for the ITP
connector. Otherwise, it can be routed
to the dedicated ITP clock pins on the
processor socket.
48MDOT
33
Connect to GMCH’s DREFCLK .
3V66/VCH
33
3V66[1]
66BUF[2:0]
CPU[0], CPU[0]#
CPU[1], CPU[1]#
CPU[2], CPU[2]#
49.9
gnd
± 1% pull- down to
1
Two possible topologies:
1. Use directly for GMCH’s
DREFSSCLK.
2. Use as input to an SSC component
and use the SSC component output
GMCH’s DREFSSCLK
IREF
475
± 1% pull-down to gnd
MULT[0]
10 k
pull-up to Vcc3_3
1
PCI[6:0]
33
Connect to various PCI devices.
PCIF[2],
PCIF[1],
PCIF[0]
33
Use one clock for ICH4-M. Unused
clock pins should be left as NC or
connected to a test point.
PWRDWN#
AND gate
This signal is needed for supporting
S1M. It needs to be driven low by both
SLP_S1# and SLP_S3# through an
AND gate.
REF
33
See Figure 112
SEL[2]
1 k-20 k
SEL[1]
330 k-20 k
Vcc3_3
This is the 14.318-MHz clock
reference signal for ICH4-M, SIO and
LPC. Each receiver requires one 33ohm series resistor.
pull-down to gnd
pull- up to
Connects to proceesor BSEL[0]
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Pin Name
System
Pull-up/Pull-down
SEL[0]
330 k-20 k
Vcc3_3
33
XTAL_IN,
XTAL_OUT
9
Connect to ICH4-M’s 48-MHz clock
input.
Connect to a 14.318-MHz crystal,
placed within 500 mils of CK-408
VDDA
Connect to Vcc3_3
VSS[5:0], VSSA
Connect to gnd
VSSIREF
Connect to gnd
NOTE:
Notes
pull- up to
48MUSB
VDD[7:0],
Series
Resistor
Refer to clock vendor datasheet for
decoupling info.
When using external graphics, may replace series resistor with 100-
resistor because signal is not needed.
Figure 112. Clock Power-down Implementation
VccSus3_3
PM_SLP_S1#
PM_SLP_S3#
246
CLK_PWRDWN#
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14.8.
852GME/852GMV/852PMChecklist
14.8.1.
System Memory
14.8.1.1. GMCH System Memory Interface
Pin Name
System
Pull-up/Pull-down
Series
Resistor
Notes
RCVENIN#
This signal should be routed to a via next
to ball and left as a NC (No Connect).
RCVENOUT#
This signal should be routed to via next
to ball and left as a NC (No Connect).
SBA[1:0], SCAS#,
SRAS#, SWE#
56
pull-up to Vcc1_25
10
SCKE[3:0],
SCS#[3:0]
56
pull-up to Vcc1_25
SDQ[63:0],
SDM[7:0],
SDQS[7:0]
56
pull-up to Vcc1_25
10
SDQ[71:64],
SDM8, SDQS8
56
pull-up to Vcc1_25
10
For 852GME, if ECC support is not
implemented, SDQ[71:64], SDM8, and
SDQS8 should be left as NC. For ECC
support, these signals connect to SODIMMs.
SMA[12:6,3,0]
56
pull-up to Vcc1_25
10
Three topologies available for routing
these signals.
SMA[5,4,2,1]
56
pull-up to Vcc1_25
9
Three topologies available for routing
these signals.
SMAB[5,4,2,1]
Use SMA[5,4,2,1] for one SO-DIMM
connector; use SMAB[5,4,2,1] for the
other SO-DIMM connector.
SCK0, SCK0#
SCK1, SCK1#
These clock signals connect to SO-DIMM
0.
SCK2, SCK2#
For M-GM, if ECC supported is not
implemented, these clock signals should
be left as NC. For ECC support, these
signals connect to SO-DIMM 0.
SCK3, SCK3#
SCK4, SCK4#
These clock signals connect to SO-DIMM
1.
SCK5, SCK5#
For 852GME, if ECC supported is not
implemented, these clock signals should
be left as NC. For ECC support, these
signals connect to SO-DIMM 1.
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Pin Name
System
Series
Resistor
Pull-up/Pull-down
SMVREF
10 k 1% pull-up to
VccSus2_5
10 k
1% pull-down to gnd
9
Notes
Signal voltage level = VccSus2_5/ 2.
Note that a buffer is used to provide the
necessary current and reference voltage
to SMVREF. Place a 0.1-µF cap by
GMCH.
See Figure 113.This signal may be
optionally connected to Vcc2_5 and
powered off in S3.
SMVSWINGL
SMVSWINGH
SMRCOMP
604 1% pull-up to
VccSus2_5
Signal voltage level = 1/5 * VccSus2_5.
150
This signal may be optionally connected
to Vcc2_5 and powered off in S3.
Need 0.1 µF cap at pin.
1% pull-down to gnd
150 1% pull-up to
VccSus2_5
Signal voltage level = 4/5 * VccSus2_5.
604
This signal may be optionally connected
to Vcc2_5 and powered off in S3.
Need 0.1 µF cap at pin.
1% pull-down to gnd
60.4 1% pull-up to
VccSus2_5
Signal voltage level = 1/2 * VccSus2_5.
60.4
gnd
This signal may be optionally connected
to Vcc2_5 and powered off in S3.
Need 0.1 µF cap by the voltage divider.
1% pull-down to
Figure 113. Reference Voltage Level for SMVREF
VccSus2_5
10k+/- 1%
GMCH
+
-
10k+/-1 %
SMVREF
SMVREF_0
0.1 uF
14.8.1.2. DDR SO-DIMM Interface
Pin Name
Configuration
VREF[2:1]
248
Notes
9
Signal voltage level = VCCSus2_5 / 2.
VDD[33:1]
Connect to VccSus2_5
VDDSPD
Connect to Vcc3_3
SA[2:0]
Connect to either VC3_3 or
gnd
Power must be provided during S3.
These lines are used for strapping the SPD address for each
SO-DIMM.
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VSS[31:1]
Connect to gnd
RESET(DU)
Signal can be left as NC (“Not Connected)
VDDID
Signal can be left as NC (“Not Connected)
DU[4:1]
Signal can be left as NC (“Not Connected)
GND[1:0]
Signal can be left as NC (“Not Connected)
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14.8.1.3.
SO-DIMM Decoupling Recommendation
Pin Name
F
Vcc1_25
Qty
0.1 µF
Place one 0.1 µF cap and one 0.01 µF close to every 4 pullup resistors terminated to Vcc1_25 (VTT for DDR signal
termination). In S3, Vcc1_25 is powered OFF.
0.01 µF
Vcc2_5Sus
14.8.2.
9
Notes
0.1 µF
9
100-150 µF
4
A minimum of 9 high frequency caps are recommeneded to
be placed bewteen the SO-DIMMS. A minimum of 4 low
frequency caps are required.
FSB
Pin Name
System
9
Notes
Pull-up/Pull-down
HXSWING,
HYSWING
301
1% pull-up to VCC
150
1% pull-down to gnd
Signal voltage level = 1/3 of VCC. C1a=0.1 µF. C1b=0.1
µF. Trace should be 10-mil wide with 20-mil spacing.
HXRCOMP,
HYRCOMP
27.4
1% pull down to gnd
One pulled-down resistor per pin. Trace should be 10-mil
wide with 20-mil spacing.
HDVREF[2:0]
49.9
1% pull-up to VCC
100
1% pull-down to gnd
Signal voltage level = 2/3 of VCC. Need one 0.1 µF cap
and one 1 µF cap for voltage divider.
See Figure 114.
HAVREF
HCCVREF
49.9
1% pull-up to VCC
100
1% pull-down to gnd
49.9
1% pull-up to VCC
100
1% pull-down to gnd
Signal voltage level = 2/3 of VCC. Need one 0.1 µF cap
and one 1 µF cap for voltage divider.
Signal voltage level = 2/3 of VCC. Need one 0.1 µF cap
and one 1 µF cap for voltage divider.
Figure 114. 852GME HXSWING & HYSWING Reference Voltage Generation Circuit
+VCC
+VCC
301R1a
1%
301
1%
HXSWING
150
1%
250
C1a
HXSWING
HYSWING
GMCH
HYSWING]
C1b
150
1%
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14.8.3.
Hub Interface
Pin Name
System
Notes
9
Pull-up/Pull-down
14.8.4.
HLVREF
See Section 14.9.9.
Signal voltage level = 0.35 V ± 8%.
PSWING
See Section 14.9.9.
Signal voltage level = 0.8 V ± 8%.
HLZCOMP
48.7
1% pull-up to VCC
Graphics Interfaces
14.8.4.1. LVDS
Pin Name
System
Notes
9
Pull-up/Pull-down
LIBG
1.5 k
1% pull-down to gnd
YAP[3:0]/YAM[3:0]
If any of these LVDS data pairs are unused, they can
be left as “no connect.”
YBP[3:0]/YBM[3:0]
CLKAP/CLKAM
If any of these LVDS clock pairs are not used, they
can be left as “no connect.”
CLKBP/CLKBM
LVREFH, LVREFL,
LVBG
These signals should be left as NC.
14.8.4.2. AGP/DVO
Pin Name
System
Notes
9
Pull-up/Pull-down
DVORCOMP
40.2
1% pull-down to gnd
GVREF
1k
1% pull-up to Vcc1_5
1k
1% pull-down to gnd
GAD[28:25]/DVOCD[11:6]
Trace should be 10-mil wide with 20-mil
spacing.
Signal voltage level = 1/2 of Vcc1_5. Need 0.1
µF cap at pin.
If unused, these signals can be left as NC.
GCBE#3/DVOCD5
GAD[23:19]/DVO[4:0]
GADSTB1/DVOCCLK
GADSTB#/DVOCCLK#
GAD17/DVOCHSYNC
GAD16/DVOCVSYNC
GAD18/DVOCBLANK#
GAD31/DVOCFLDSTL
100 k
pull-down to gnd
Pull-down resistor required only if signal is
unused (10 k-100 k). It is up to DVO device to
drive this signal.
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Pin Name
System
Notes
9
Pull-up/Pull-down
GAD30/DVOBCINTR#
100 k
pull-up to Vcc1_5
Pull-up resistor required only if signal is
unused (10 k-100 k). It is up to the DVO
device to drive this signal.
GAD13/DVOBCCLKINT
100 k
pull-down to gnd
Pull-down resistor required only if signal is
unused (10 k-100 k). It is up to the DVO
device to drive this signal.
GAD3/DVOBD0
If AGP is not used these should left as NC.
GAD2/DVOBD1
GAD5/DVOBD2
GAD4/DVOBD3
GAD7/DVOBD4
GAD6/DVOBD5
GAD8/DVOBD6
GCBE#0/DVOBD7
GAD10/DVOBD8
GAD9/DVOBD9
GAD12/DVOBD10
GAD11/DVOBD11
GADSTB0/DVOBCLK
GADSTB#0/DVOBCLK#
GAD0/DVOBHSYNC
GAD1/DVOBVSYNC
GBCE#1/DVOBBLANK#
GAD30/DVOBFLDSTL (pin
M2)
100 k
pull-down to gnd
For 852GME, pull-down resistor required on
this signal (10 k-100 k). If AGP has been
used pin doesn’t require pull-down.
GIRDY/MI2CCLK,
GDEVSEL/MI2CDATA
2.2 k
pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is
1.5-V tolerant. It may require voltage
translation circuit. If AGP has been used pin
doesn’t require pull-up.
GTRDY/MDVICLK,
GFRAME#/MDVIDATA
2.2 k
pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is
1.5-V tolerant. It may require voltage
translation circuit. If AGP has been used pin
doesn’t require pull-up.
GSTOP#/MDDCCLK,
GAD15/MDDCDATA
2.2 k
pull-up to Vcc1_5
Pull-up resistor required on each signal even if
they are unused (2.2 k-100 k). This signal is
1.5-V tolerant. It may require voltage
translation circuit. If AGP has been used pin
doesn’t require pull-up.
GSBA[6:0]/ADDID[6:0]
GSBA7/ADDID7
252
Leave as NC.
1 k pull-down to gnd if
DVO device is onboard
If DVO interface is not used, this signal can be
left as “no connect”. Otherwise, pull-down is
needed. If AGP has been used pin doesn’t
require pull-down.
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Pin Name
System
Notes
9
Pull-up/Pull-down
GPAR/DVODETECT
1k
pull-up to Vcc1_5
if DVO interface is unused
If DVO interface is used, leave as NC. This
signal has internal pull-down.
GPIPE#/DPMS
If AGP is not used, connect this signal to 1.5-V
version of ICH4-M’s SUSCLK or a clock that
runs during S1. See Figure 115.
GST[2:0]
These AGP signals are also used for
strapping purposes. See Section 14.8.5 for
details. Isolation circuit is needed for normal
operation. See Figure 116.
Figure 115. DPMS Clock Implementation
Vcc1_5
1K
To GMCH
PM_SUS_CLK
3
From
DPMS pin
ICH4-M
BSS138
SUS_CLK 1
2
SUSCLK
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Figure 116. Q-SWITCH Circuit
254
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14.8.4.3.
DAC
Pin Name
System Pull-up /Pull-down
In Series
Notes
REFSET
127
RED #
Connect to gnd
Need to connect to RED’s return path
BLUE #
Connect to gnd
Need to connect to BLUE’s return path
GREEN#
Connect to gnd
Need to connect to GREEN’s return path
RED
On GMCH side of ferrite bead:
1% pull-down to gnd
75 1% pull-down to gnd, 3.3
pF cap to gnd, ESD diode
protection for Vcc1_5
Ferrite bead:
75 at
100 MHz
3.3 pF cap to gnd
On GMCH side of ferrite bead:
75 1% pull-down to gnd, 3.3
pF cap to gnd, ESD diode
protection for Vcc1_5
Ferrite bead:
75 at
100 MHz
3.3 pF cap to gnd
On GMCH side of ferrite bead:
75 1% pull-down to gnd, 3.3
pF cap to gnd, ESD diode
protection for Vcc1_5
Ferrite bead:
75 at
100 MHz
Ferrite bead for EMI suppression between
GMCH and VGA connector.
See lastest Intel Customer Reference
Schematics for more details.
Ferrite bead for EMI suppression between
GMCH and VGA connector.
See latest Intel Customer Reference
Schematics for more details.
When using external graphics, the 75
1% pull-down to gnd is not needed.
On VGA side of ferrite bead:
3.3 pF cap to gnd
HSYNC
See latest Intel Customer Reference
Schematics for more details.
When using external graphics, the 75
1% pull-down to gnd is not needed.
On VGA side of ferrite bead:
GREEN
Ferrite bead for EMI suppression between
GMCH and VGA connector.
When using external graphics, the 75
1% pull-down to gnd is not needed.
On VGA side of ferrite bead:
BLUE
9
39
Connect to unidirectional buffer to prevent
potential electrical overstress and illegal
operation of the GMCH.
See lastest Intel Customer Reference
Schematics for more details.
VSYNC
39
Connect to unidirectional buffer to prevent
potential electrical overstress and illegal
operation of the GMCH.
See lastest Intel Customer Reference
Schematics for more details.
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14.8.5.
Miscellaneous
Pin Name
System
9
Notes
Pull-up/Pull-down
EXTTS
10 k
1% pull-up to Vcc3_3
DPWR# (pin AA22)
No Connect
LCLKCTLB
LCLKCTLA
Leave as NC if not used.
GST2, GST1, GST0
Leave as NC or 1K
pull-up to Vcc1_5
These pins have internal pull-down.
Future
852GME/852GMV/852PMdesigns
only need GST2 to strap the FSB
frequency to 400 MHz or 533 MHz.
GST0 and GST1 may be left as NC.
Current
852GME/852GMV/852PMdesigns
may still use the GST configurations in
Table 105.
Table 105. GST[2:0] Configurations
Straps Read
Through
HPLLCC[2:0]
256
FSB
Frequency
System
Memory
Frequency
GFX Core
Clock - Low
GFX Core
Clock High
Config #
000
400 MHz
266 MHz
133 MHz
200 MHz
0
001
400 MHz
200 MHz
100 MHz
200 MHz
1
010
400 MHz
200 MHz
100 MHz
133 MHz
2
011
400 MHz
266 MHz
133 MHz
266 MHz
3
100
533 MHz
266 MHz
133 MHz
200 MHz
4
101
533 MHz
266 MHz
133 MHz
266 MHz
5
110
533 MHz
333 MHz
166 MHz
266 MHz
6
111
400 MHz
333 MHz
166 MHz
250 MHz
7
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14.8.6.
GMCH Decoupling Recommendations
Pin Name
VCC[17:0]
VTTLF[20:0]
Configuration
Connect to Vcc1_5S
Connect to VCC
VTTHF[4:0]
F
Qty
0.1 µF
4
150 µF
2
10 µF
1
0.1 µF
2
150 µF
1
1
5
Connect pins directly to caps.
2
Bulk decoupling is based on VR
solutions used on CRB design.
0.1 µF
10 µF
1
VCCSM[36:0]
Connect to VccSus2_5
0.1 µF
11
150 µF
2
VCCQSM[1:0]
Connect to VccSus2_5
with filter network
0.1 µF
1
4.7 µF+1
1 each
Connect to Vcc1_5S
with filter network
0.1 µF
1
100 µF
1
VCCAGP/VCCD
VO[15:0]
Connect to Vcc1_5
0.1 µF
2
10 µF
1
VCCADAC[1:0]
Connect to Vcc1_5
VCCALVDS
VCCDLVDS[3:0]
VCCTXLVDS[3:
0]
VCCGPIO
Connect to Vcc1_5
Connect to Vcc1_5
Connect to VccSus2_5
Connect to Vcc3_3
Bulk decoupling is based on VR
solutions used on CRB design.
10 µF
Connect to Vcc1_5S
150 µF
1
0.01 µF
1
Bulk decoupling is based on VR
solutions used on CRB design.
0.68 uH from power supply to GMCH
pins. On GMCH side of inductor: one
0.1 µF to GND, 4.7 µF + 1 to GND
1 uH from power supply to GMCH
pins, with caps on GMCH side of
inductor.
Bulk decoupling is based on VR
solutions used on CRB design.
Route VSSADAC to other side of the
caps, then to ground.
0.1 µF
1
220 µF (no
stuff)
1
A 0-ohm 0805 resisor is
recommended between the caps and
Vcc1_5. This and the 220 µF cap
footprints are there in case there is
noise issue with the VGA supply.
Route VSSALVDS to other side of the
caps, then to ground.
0.1 µF
1
0.01 µF
1
0.1 µF
1
22 µF
1
47 µF
1
0.1 µF
3
Bulk decoupling is based on VR
solutions used on CRB design.
Bulk decoupling is based on VR
solutions used on CRB design.
22 µf
1
47 µF
1
This power signal may be optionally
connected to Vcc2_5 and powered off
in S3.
0.1 µF
1
10 µF
1
Bulk decoupling is based on VR
solutions used on CRB design.
VCCAHPLL
Connect to VCC1_5S
0.1 µF
1
VCCAGPLL
Connect to VCC1_5S
0.1 µF
1
9
Bulk decoupling is based on VR
solutions used on CRB design.
0.1 µF
VCCHL[7:0]
VCCASM[1:0]
Notes
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Pin Name
VCCADPLLA
VCCADPLLB
NOTE:
14.8.7.
Configuration
Connect to VCC1_5S
with filter network
Connect to VCC1_5S
with filter network
F
Qty
0.1 µF
1
220 µF
1
0.1 µF
1
220 µF
1
9
Notes
0.1 µH from power supply to GMCH
pins, with caps on GMCH side of
inductor.
0.1 µH from power supply to GMCH
pins, with caps on GMCH side of
inductor.
Decoupling guidelines are recommendations based on our reference board design. Customers will need to
take layout and PCB board design into consideration when deciding on overall decoupling solution.
GMCH Power-up Sequence
Timing Parameters
PWROK active to RSTIN# inactive.
Min
Max
1
RSTIN# inactive to CPURST# inactive.
1
Unit
9
Notes
®
ms
Please refer to the Intel
852GME Chipaer GMCH and
®
Intel 852PM Chipset MCH
Datasheet.
ms
Please refer to Intel 852GME
®
Chipaer GMCH and Intel
852PM Chipset MCH
Datasheet.
®
Figure 117. 852GME Power-up Sequence
CPURST#
1ms max
RSTIN#
1ms min
PWROK
GMCH PWR
Rails
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14.9.
ICH4-M Checklist
Note: All inputs to the ICH4-M must not be left floating. Many GPIO signals are fixed inputs that must be
pulled up to different sources.
14.9.1.
PCI Interface and Interrupts
Pin Name
System Pull-up /Pulldown
PCI_DEVSEL#
8.2 k
pull-up to Vcc3_3
PCI_FRAME#
8.2 k
pull-up to Vcc3_3
PCI_GPIO0 / REQA#
PCI_GPIO1 / REQB_L/REQ5#
8.2 k
pull-up to Vcc3_3
PCI_GPIO16 / GNTA#
Notes
9
Each signal requires a pull-up resistor.
GNTA is also used as a strap for “top block
swap”. It is sampled on the rising edge of
PWROK. By default, this signal is HIGH
(strap function DISABLED). It can be
enabled by a pull-down to gnd through a 1k resistor.
PCI_IRDY#
8.2 k
pull-up to Vcc3_3
PCI_LOCK#
8.2 k
pull-up to Vcc3_3
PCI_PERR#
8.2 k
pull-up to Vcc3_3
PCI_SERR#
8.2 k
pull-up to Vcc3_3
PCI_STOP#
8.2 k
pull-up to Vcc3_3
PCI_TRDY#
8.2 k
pull-up to Vcc3_3
PCI_REQ[4:0]#
8.2 k
pull-up to Vcc3_3
PCI_PME#
Each signal requires a pull-up resistor.
ICH4-M has internal pull-up to VccSus3_3.
PCI_RST#
8.2 k
Vcc3_3
k
pull-up to
APICCLK
Pull down to GND (If
NOT Used)
APICD[1:0]
10 k pull-down to gnd (If
NOT Used)
If XOR chain testing is NOT used: Pull
down the signals through a shared 10kohm resistor, if NOT USED.
If XOR chain testing is used: Each signal
requires a separate 10K pull-down
resistor.
INT_IRQ[15:14]
8.2 k
pull-up to Vcc3_3
Each signal requires a pull-up resistor.
INT_PIRQ#[A:D]
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
8.2 k
pull-up to Vcc3_3
External pull up is required for
INT_PIRQ#[A:D]. External pull up is
required when muxed signal
(INT_PIRQ[E:H]#/ GPIO[2:5]) is
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Pin Name
System Pull-up /Pulldown
INT_PIRQH#/GPIO5
INT_SERIRQ
260
Notes
9
implemented as PIRQ.
8.2 k
pull-up to Vcc3_3
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14.9.2.
GPIO
Note: Ensure ALL unconnected signals are OUTPUTS ONLY. GPIO[7:0] are 5-V tolerant.
Recommendations
9
GPIO[7] & [5:0]:
These pins are in the Main Power Well. Pull-ups must use the VCC3_3 plane.
Unused core well inputs must be pulled up to VCC3_3.
GPIO[1:0] can be used as REQ[B:A]#.
GPIO[1] can be used as PCI REQ[5]#.
GPIO[5:2] can be used as PIRQ[H:E]#.
These signals are 5 V tolerant.
These pins are inputs.
GPIO[8] & [13:11]:
These pins are in the Resume Power Well. Pull-ups go to VCCSus3_3 plane.
Unused resume well inputs must be pulled up to VCCSus3_3.
These are the only GPIs that can be used as ACPI compliant wake events.
These signals are not 5V tolerant.
GPIO[8] can be used as SMC_EXTSMI#
GPIO[11] can be used as SMBALERT#.
GPIO[13] can be used as SMC_WAKE_SCI#
These pins are inputs
GPIO[23:16]:
Fixed as output only. Can be left NC.
In Main Power Well (VCC3_3).
GPIO[17:16] can be used as GNT[B:A]#.
GPIO[17] can be used as PCI GNT[5]#.
STP_PCI#/GPIO[18] – used in Mobile as STP_PCI# only.
SLP_S1#/GPIO[19] - used in Mobile as SLP_S1# only.
STP_CPU#/GPIO[20] - used in Mobile as STP_CPU# only.
C3_STAT#/GPIO[21] - used in Mobile as C3_STAT# only.
CPUPERF#/GPIO[22] - open drain signal. Used in Mobile as CPUPERF# only.
SSMUXSEL/GPIO[23] - used in Mobile as SSMUXSEL only.
GPIO[28,27,25,24]:
I/O pins. Default as outputs. Can be left as NC.
These pins are in the Resume Power Well.
CLKRUN#/GPIO[24] (Note: use VCC3_3 if signal is required to be pulled-up)
GPIO[28, 27, 25] From resume power well (VCCSus3_3). (Note: use VCC3_3 if this signal is required to be
pulled-up)
These signals are NOT 5-V tolerant.
GPIO[25] can be used as AUDIO_PWRDN.
GPIO[43:32]:
I/O pins. From main power well (VCC3_3).
Default as outputs when enabled as GPIOs.
These signals are NOT 5-V tolerant.
GPIO[32] can be used as AGP_SUSPEND#.
GPIO[33] can be used as KSC_VPPEN#.
GPIO[34] can be used as SER_EN.
GPIO[35] can be used as FWH_WP#.
GPIO[36] can be used as FWH_TBL#.
GPIO[40] can be used as IDE_PATADET.
GPIO[41] can be used as IDE_SATADET.
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14.9.3.
AGP_BUSY# Design Requirement
Signal
System
Notes
9
Pull-up/Pull-down
AGPBUSY#/GPIO6
10 k pull-up to
Vcc3_3
This ICH4-M signal requires a pull-up to the switched 3.3-V
rail (powered OFF during S3).
This ICH4-M signal must be connected to the AGP_BUSY#
output of GMCH.
When using external graphics, AGP_BUSY# may be left as
NC to the GMCH.
NOTE:
14.9.4.
Please also consult Intel for the latest AGP Busy and Stop signal implementation.
(SMBus) System Management Interface
Pin Name
System
Notes
Pull-up/Pull-down
SM_INTRUDER#
100 k pull-up to
VccRTC
SMB_ALERT#/
GPIO[11]
10 k pull-up to
V3ALWAYS
SMBCLK,
SMBDATA,
SMLINK[1:0]
Pull-up to V3ALWAYS
RTC well input requires pull-up (10 k-100 k) to reduce
leakage from coin cell battery in G3.
Require external pull-up resistors. Pull up value is
determined by bus characteristics. CRB schematics use 10k pull-up resistors.
The SMBus and SMLink signals must be connected
together externally in S0 for SMBus 2.0 compliance:
SMBCLK connected to SMLink[0] and SMBDATA
connected to SMLink[1].
262
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14.9.5.
AC ’97 Interface
Pin Name
System
Pull-up/Pull-down
AC_BIT_CLK
None
Series
Termination
Resistor
33-47
Notes
9
The internal pull-down resistor is controlled by
the AC’97 Global Control Register, ACLINK
Shut Off bit:
1 = enabled; 0 = disabled
When no AC'97 devices are connected to the
link, BIOS must set the ACLINK Shut Off bit
for the internal keeper resistors to be
ENABLED. At that point, pull-ups/pull-downs
are NOT needed on ANY of the link signals.
AC_SDATAIN[2:0]
None
33-47
A series termination resistor is required for the
PRIMARY CODEC.
A series termination resistor is required for the
SECONDARY and TERTIARY CODEC if the
resistor is not found on CODEC.
AC_SDATAOUT
None
33-47
A series termination resistor is required for the
PRIMARY CODEC.
One series termination resistor is required for
the SECONDARY/ TERTIARY CODEC
connector card if the resistor is not found on
the connector card.
AC_SYNC
None
33-47
A series termination resistor is required for the
PRIMARY CODEC.
One series termination resistor is required for
the SECONDARY/ TERTIARY CODEC
connector card if the resistor is not found on
the connector card.
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14.9.6.
ICH4-M Power Management Interface
Pin Name
System
9
Notes
Pull-up/Pull-down
PM_DPRSLPVR
Signal has integrated pull-down in ICH4-M.
PM_SLP_S1#/GPIO19
PM_SLP_S3#,
PM_SLP_S4#,
PM_SLP_S5#
Signals driven by ICH4-M.
PM_BATLOW#
10-k pull-up to
V3ALWAYS
PM_CLKRUN#
10-k
Pull up is not required if it is used. However,
signal must not float if it is NOT being used
IF NOT USED
pull-up to Vcc3_3
PM_PWRBTN#
PM_PWROK
Has integrated pull-up of 18 k
Weak pull-down to gnd
– 42 k
RTC well input requires pull-down to reduce
leakage from coin cell battery in G3. Input must
not float in G3.
This signal should be connected to power
monitoring logic and should go high no sooner
than 10 ms after both Vcc3_3 and Vcc1_5 have
reached their nominal voltages. CRB uses 100
k pull-down.
PM_RI#
10-k pull-up to
V3ALWAYS
If this signal is enabled as a wake event, it needs
to be powered during a power loss event. If this
signal goes low (active), when power returns the
RI_STS bit will be set and the system will
interpret that as a wake event.
PM_RSMRST#
Weak pull-down to gnd
RSMRST# is a RTC well input and requires pulldown to reduce leakage from coin cell battery in
G3. Input must not float in G3.
This signal should be connected to power
monitoring logic and should go high no sooner
than 10 ms after both Vcc3_3 and Vcc1_5 have
reached their nominal voltages. CRB uses 100
K pull-down.
Timing Requirement: See LAN_RST#.
PM_THRM#
8.2 k
Pull-up to Vcc3_3
PM_SYSRST#
10 k pull-up to V3ALWAYS
if not actively driven.
If TEMP SENSOR not sued
264
External pull-up not required if connecting to
temperature sensor.
This signal to ICH4-M should not float. It needs
to be at valid level all the time.
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
Platform Design Checklist
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14.9.7.
FWH/LPC Interface
Pin Name
System
Notes
9
Pull-up/Pull-down
No extra pull-ups required. Connect straight to FWH/LPC.
LPC_AD[3:0]
14.9.8.
USB Interface
Pin Name
System
Notes
9
Pull-up/Pull-down
USB_OC[5:0]#
10 k
pull-up to V3ALWAYS
if not driven
USBRBIAS,
USBRBIAS#
14.9.9.
22.6
± 1% pull-down to gnd
No pull-up is required if signalsl are driven.. Signals
must NOT float if they are not being used.
Connect signals together and pull down through a
common resistor, placed within 500 mils of the ICH4M. Avoid routing next to clock pin.
Hub Interface
Pin Name
System
Notes
9
Pull-up/Pull-down
HUB_RCOMP
48.7
1% pull-up to to Vcc1_5
HUB_VREF,
HUB_VSWING
Please refer to Figure 118 and
Figure 119 and Figure 120
HUB_PD11
56
Place resistor within 0.5” of ICH4-M pad using a
thick trace.
HUB_VREF signal voltage level = 0.35 V ± 8%.
HUB_VSWING signal voltage level = 0.80 V ±
8%. Three options are available for generating
these references.
pull-down to gnd
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Figure 118. Separated GMCH and ICH4-M VSWING/VREF Reference Voltage Circuit
VCC_GMCH_Hub = 1.5V
R1
86.6_1%
PVSWING
R2
C1
F
100_1%
GMCH
VCC_GMCH_Hub = 1.5V
R3
HLVREF
R4
C2
F
VCC_ICH_Hub = 1.5V
R1
130_1%
HUB_VSWING
R2
C1
F
F
150_1%
ICH4-M
VCC_ICH_Hub = 1.5V
R3
HUB_VREF
R4
C2
F
F
266
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Figure 119. Single or Locally Generated GMCH & ICH4-M HIVREF/HI_VSWING Circuit
VCCHI=1.5V
R1
PVSWING
C5
C1
GMCH
HLVREF
HI_VSWING
C2
C3
R1 = 226 Ω ± 1%,
R2 = 147 Ω ± 1%,
R3 = 113 Ω ± 1%
HIREF
C4
C6
Option 1
ICH4-M
R2
Option 2
R1 = 80.6 Ω ± 1%,
R2 = 51.1 Ω ± 1%,
R3 = 40.2 Ω ± 1%
R3
Option 3
VCCHI=1.5V
R1 = 255 Ω ± 1%,
R2 = 162 Ω ± 1%,
R3 = 127 Ω ± 1%
VCCHI=1.5V
R1
C1 and C3 = 0.1 µF
(near divider)
R1
C2
R2
PVSWING
C2
C4
Intel®
ICH4
R2
GMCH
C4
HLVREF
C2, C4, C5, C6 =
0.01µF (near
component)
HI_VSWING
HIREF
R3
R3
Figure 120. Single Generated GMCH and ICH4-M VSWING/VREF Reference Voltage/ Local Voltage
Divider Circuit for VSWING/VREF
VCCHI=1.5V
R4
R4 = 43.2 Ω ± 1%,
R5 = 49.9 Ω ± 1%,
R6 = 78.7 Ω ± 1%,
R7 = 24.2 Ω ± 1%
R6
PVSWING
HI_VSWING
HLVREF
HIREF
(G)MCH
R5
C6
C5
R7
Intel®
ICH4
C1 and C3 = 0.1 µF
(near divider)
C2, C4, C5, C6 =
0.01µF (near
component)
C4
C3
C1
C2
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14.9.10.
RTC Circuitry
Pin Name
System
In Series
9
Notes
Pull-up/Pull-down
RTCRST#
180 k pull-up to
VccRTC
RTCRST# requires 18-25 ms delay. Use a 0.1-µF
cap to ground Pull up with 180-k resistor. Any
resistor or capacitor combination that yields a time
constant is acceptable.
CLK_RTCX1,
CLK_RTCX2
Connect a 32.768-kHZ crystal oscillator across these
pins with a 10-M resistor and a decoupling cap at
each signal. Values for C1 and C2 are dependent on
crystal.
See Figure 121. Note 1
CLK_VBIAS
1k
0.047 µF
Connect to CLK_RTCX1 through a 10-M resistor.
Connect to VBATT through a 1 k in series with a
0.047-µF capacitor. Note 2
NOTES:
1. Voltage Swing on RTCX1 pin should not exceed 1.0 V.
2. Recommendation for VBIOS 200 mV-350 mV.
Figure 121. External Circuitry for the RTC
VCCRTC
3.3V Sus
1uF
RTCX2
1kΩ
R1
10M Ω
32.768 kHz
Xtal
Vbatt
RTCX1
C3
0.047uF
C1
C2
R2
10M Ω
VBIAS
Notes
Reference Designators Arbitrarily Assigned
3.3V Sus is Active Whenever System Plugged In
Vbatt is Voltage Provided By Battery
268
VBIAS, VCCRTC, RTCX1, and RTCX2 are ICH4-M pins
VBIAS is used to bias the ICH4 Internal Oscillator
VCCRTC powers the RTC well of the ICH4-M
RTCX1 is the Input to the Internal Oscillator
RTCX2 is the feedback for the external crystal
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
Platform Design Checklist
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14.9.11.
LAN Interface
Pin Name
System
Notes
9
Pull-up/Pull-down
LAN_JCLK
LAN_RST#
Connect to LAN_CLK on the platform LAN Connect
Device. If LAN interface is not used, leave the signal
unconnected (NC).
10-k
pull-down to gnd
If ICH4-M LAN not used
Timing Requirement: Signal should be connected to power
monitoring logic, and should go high no sooner than 10 ms
after both VccSus3_3 and VccSus1_5 have reached their
nominal voltages.
NOTE: If ICH4-M LAN controller is NOT used, pull
LAN_RST# down through a 10-k resistor.
LAN_RXD[2:0],
LAN_TXD[2:0]
Connect to LAN_RXD on the platform LAN Connect
Device.
If LAN interface is not used, leave the signal unconnected
(NC)
LAN_RSTYSNC
Connect to LAN_RSTSYNC on Platform LAN Connect
Devce.
If LAN interface is not used, leave the signal unconnected
(NC).
14.9.12.
Primary IDE Interface
Pin Name
System
Pull-up/Pulldown
Series
Damping
Notes
IDE_PDD[15:0]
These signals have integrated series resistors.
IDE_PDA[2:0],
IDE_PDCS1#,
IDE_PDCS3#,
IDE_PDDACK#,
IDE_PDIOW#,
IDE_PDIOR#
These signals have integrated series resistors. Pads
for series resistors can be implemented should the
system designer have signal integrity concerns.
IDE_PDDREQ
These signals have integrated series resistors and pulldown resistors in ICH4-M.
IDE_PIORDY
IDE_PRST#
4.7K pull-up
to Vcc3_3
9
This signal has integrated series resistor in ICH4-M.
22-47
The signal must be buffered to provide IDE_RST# for
improved signal integrity.
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14.9.13.
Secondary IDE Interface
Pin Name
System
Pull-up/Pulldown
Notes
IDE_SDD[15:0]
These signals have integrated series resistors.
IDE_SDA[2:0],
IDE_SDCS1#,
IDE_SDCS3#,
IDE_SDDACK#,
IDE_SDIOW#,
IDE_SDIOR#
These signals have integrated series resistors. Pads for
series resistors can be implemented should the system
designer have signal integrity concerns.
IDE_SDDREQ
These signals have integrated series resistors and pull-down
resistors in ICH4-M.
IDE_SIORDY
4.7 k pull-up
to Vcc3_3
IDE_SRST#
14.9.14.
Series
Damping
This signal has integrated series resistor in ICH4-M.
22-47
The signal must be buffered to provide IDE_RST# for
improved signal integrity..
Miscellaneous Signals
Pin Name
System
Notes
Pull-up/Pull-down
SPKR
SPKR is a strapping option for the TCO Timer Reboot function
and is sampled on the rising edge of PWROK. An integrated
weak pull-down is enabled only at boot/reset. Status of strap is
readable via the NO_REBOOT bit (D31:F0, Offset D4h, bit 1)
1 = disabled; 0 = enabled (normal operation)
To disable, a jumper can be populated to pull SPKR high. Value
of pull-up must be such that the voltage divider output caused by
the pull-up, effective impedance of speaker and codec circuit,
and internal pull-down will be read as logic high (0.5 * Vcc3_3 to
Vcc3_3 + 0.5)
270
9
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14.9.15.
ICH4-M Decoupling Recommendations
Pin Name
Configuration
Value
Q
Notes
VCC1.5
Connect to Vcc1_5
0.1 µF
2
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 22 µF
and one 100 µF.
VCC3.3
Connect to Vcc3_3
0.1 µF
6
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses two 22 µF.
VCCSUS1.5
Connect to
V1_5ALWAYS
0.1 µF
2
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 10 µF.
VCCSUS3.3
Connect to
V3ALWAYS
0.1 µF
2
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 22 µF.
VCCLAN1.5
Connect to
VccSus1_5
0.1 µF
2
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 22 µF.
VCCLAN3.3
Connect to
VccSus3_3
0.1 µF
2
4.7 µF
1
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 22 µF.
Connect to Vcc5
through 1 k
0.1 µF
1
1 µF
1
Connect to
V5ALWAYS through
1k
0.1 µF
1
1 µF
1
VCC_CPU_IO
Connect to VCC
0.1 µF
1
1 µF
1
VCCLL
Connect to Vcc1_5
0.1 µF
1
0.01 µF
1
VCCRTC
Connect to VccRTC
0.1 µF
1
VCCHI
Connect to Vcc1_5
0.1 µF
2
VCC5REF
VCC5REFSUS
NOTE:
9
Caps from VCC5REF to ground. Also
connect diode from VCC5REF to
Vcc3_3.
Caps from VCC5REFSUS to ground.
Also connect diode from
VCC5REFSUS to V3ALWAYS.
Please refer to latest Platform RDDP
for the implementaion.
Low frequency decoupling is
dependent on layout and power
supply design. CRB uses one 22 µF.
All decoupling guidelines are recommendations based on our reference board design. Customers will need
to take their layout, and PCB board design into consideration when deciding on their overall decoupling
solution. Capacitors should be place less than 100 mils from the package.
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14.9.16.
ICH4-M Power-up Sequence
Table 106. ICH4-M Power-up Timing Specifications
Sym
Description
Min
Max
Units
T173
Notes
VccSus supplies active to LAN_RST#,
RSMRST# inactive
10
-
ms
T176
Vcc1.5, Vcc3.3, VccHI supplies active to
PWROK, VGATE active
10
-
ms
4
T177
PWROK and VGATE active and SYS_RESET#
inactive to SUS_STAT# inactive
32
38
RTCCLK
2
T178
SUS_STAT# inactive to PCIRST# inactive
1
3
RTCCLK
2
T181
VccSus active to SLP_S5#, SUS_STAT# and
PCIRST# active
50
ns
T182/T183
RSMRST# inactive to SUSCLK running,
SLP_S5# inactive
110
ms
1
T183a
SLP_S5# inactive to SLP_S4# inactive
1
2
RTCCLK
2
T183b
SLP_S4# inactive to SLP_S3# inactive
1
2
RTCCLK
2
T184
Vcc_CPU_IO active to STPCLK#, CPUSLP#
inactive, and CPU Frequency Strap signals high
50
ns
T185
PWROK and VGATE active and SYS_RESET#
inactive to SUS_STAT# inactive and CPU
Frequency Straps latched to strap values
32
38
RTCCLK
2
T186
CPU Reset Complete to Frequency Straps
signals unlatched from strap values
7
9
CLK66
3
9
NOTES:
1. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay from
RTCRST# and the RSMRST# inactive to SUSCLK toggling may be as much as 1000 ms.
2. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
3. This transition is clocked off the 66-MHz CLK66. 1 CLK66 is approximately 15 ns.
4. It is not necessary for PWROK to be asserted before or after PM_VGATE is asserted. However, if PWROK is
asserted after PM_VGATE, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock).
Similarly, if PM_VGATE is asserted after PWROK, it must be delayed 3-10 ms from PWRGD from the VR
(which enables clock).
5. Please refer to ICH4-M for latest specifications.
272
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Figure 122. ICH4 Power-up Sequence Waveforms
S ystem
S tate
G3
G3
S5
S4
S3
S0
S0 state
H ub interface
"C PU R eset
C om plete"
m essage
S TPC LK#,
C P U SLP#
T186
T184
Frequenc y
Straps
Strap
V l
Norm al Operation
T185
PC IR ST#
T178
T181
S U S_STA T#
T177
PW R O K , V G ATE
LA N _R S T#
T176
Vcc
(V*, V*S, Vlan)
SLP_S 3#
T183b
T181
T183a
S LP _S4#
S LP _S5#
T183
Running
S U SC LK
T182
R S MR S T#
T173
VccSus
(V*A lwa ys)
NOTE:
It is not necessary for PWROK to be asserted before or after PM_VGATE is asserted. However, if PWROK is
asserted after PM_VGATE, it must be delayed 3-10 ms from PWRGD from the VR (which enables clock).
Similarly, if PM_VGATE is asserted after PWROK, it must be delayed 3-10 ms from PWRGD from the VR
(which enables clock).
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14.10.
USB Power Checklist
14.10.1.
Downstream Power Connection
Pin Name
USB_VCC[E:A]
9
Notes
One 220 µF and two 470 pF are recommended for every two power lines. Either a
thermister or a power distribution switch (with short circuit and thermal protection) is
required.
See Figure 123.
Figure 123. Good Downstream Power Connection
5V
5V Sus
5V
Switch
Thermister
Vc
Vcc
220uF
470pF
Gnd
Vcccc
470pF
G
Gnd
1
Port
4
1
Port
4
Ferrite Bead
5V Sus
PWR
Distribution
Switch
Vc
Vc c
100-150uF
470pF
Gnd
1
Port
4
Ferrite Bead
Vcccc
470pF
100-150uF
G
Gnd
274
1
Port
4
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
Platform Design Checklist
R
14.11.
FWH Checklist
14.11.1.
Resistor Recommendations
Pin Name
System
Pull-up/Pull-down
FGPI[4:0]
100
pull-down to gnd
IC
10 k
pull-down to gnd
RST#
Series
Damping
9
Notes
Each signal requires a 100
pull-down resistor.
100
ID[3:0]
Signals are recommended to be connected to
test points.
RSVD[5:1]
Signals are recommended to be connected to
test points.
NC[8:1]
The signals should be left as NC (“Not
Connected”)
14.12.
LAN/HomePNA Checklist
14.12.1.
Resistor Recommendations (for 82562ET / 82562 EM)
Pin Name
System
Pull-up/Pull-down
ISOL_EX,
ISOL_TCK,
ISOL_TI
Term
Resistor
10 k pull-up to
VccSus3_3LAN
Notes
9
If LAN is enabled, all three signals needs to
be pulled up to VccSus3_3LAN through a
common 10-k pull-up resistor.
See Figure 124.
RBIAS10
549
gnd
± 1%pull-down to
RBIAS100
619
gnd
± 1%pull-down to
RDP, RDN
121
±1%
Connect 121-ohm resistor between RDP and
RDN.
TDP, TDN
100
± 1%
Connect 100-ohm resistor between TDP and
TDN.
TESTEN
100
pull-down to gnd
X1, X2
Connect a 25-MHz crystal across these two
pins. 22 pF on each pin to ground.
LAN_RST#
On CRB, the power monitoring logic waits for
PM_PWROK to go high before deasserting
this signal to enable the LAN device. It also
keeps this signal high during S3.
See Figure 124.
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Figure 124. LAN_RST# Design Recommendation
VccS us3_3LA N
82562EM
10k
IS O L_TC K
IS O L_TI
IS O L_E X
LA N _R S T#
14.12.2.
Decoupling Recommendations
Signal Name
276
Configuration
F
Qty
VCC[2:1],
VCC[2:1],
VCCA[2:1],
VCCT[4:1]
Connect to
VccSus3_3LAN
0.1 µF
4.7 µF
4
2
VCCR[2:1]
Connect to
VccSus3_3LAN via filter
0.1 µF
4.7 µF
1
1
Notes
9
4.7 uH from power supply to
VCCR pins. Caps on VCCR
side of the inductor.
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
Schematics
R
15.
Schematics
Refer to the following pages for schematics.
Intel® 852GME, Intel® 852GMV and Intel® 852PM Chipset Platforms Design Guide
277
A
B
C
D
E
Intel® 852GME Platform with the Mobile Intel® Pentium® 4 Processor,
Mobile Intel® Pentium® 4 Processor supporting Hyper-Threading Technology
on 90-nm process technology, Intel® Celeron® Processor and
4
4
Intel® Celeron® D Processor Customer Reference Board
Fan
Header
PG 38
Proc
Thermal
Sensor
PG 5
Mobile Intel
Pentium 4
Processor
ITP
CK-408
PG 5
Clocking
SS
Clocking
PG 6
PG 6
478 uFCPGA
Test Points
PG 37
PG 3,4
IMVP-V VR
PG 42
PG 39,40,41
PG 11
PG 16
732 uFCBGA
USB4
PG 22 PG 22 PG 23
ATA 100
33MHz PCI
421 BGA
USB 2.0
LAN CONNECT
PG 18,19,20,21
Docking
Connector
USB2
PG 43
Q-Switch
Hub Interface
66MHz
PG 10
ICH4-M
PG 24
PG 25
PG 28
USB1
USB3
82562EM
2
PG 30
MDC
Header
PG 27
RJ45
PG 37
FWH
LPC, 33MHz
8 Mbit
LPC
SLOT
PG 28
USB0
AC97
PG 28
2
EVMC SLOT
DDR VR
5V PCI SLOT 3
IDE1
USB5
(Docking)
IDE0
PG 29
PG 31
PG 44
SIO
On Board VR
PORT 80--83
1.5V Always,
5V Always
1.5V
SMC/KBC
PG 33
PC87393
Suspend
Timer
Turner
System
DC/DC
Connector
3
PG 47
PG 17
PG 26,27
PG 29
PG 14
PG 7,8,9,10
DAC
PG 29
SODIMM1
852GME
GMCH
LVDS
(CRT)
DDR SDRAM
266/333 MHz
5V PCI SLOT 2
Backlight
Connector
PG 16
3
SODIMM0
PG 13
AGP/DVO Bus
PG 15
PG 12
PG 13
PSB/533
5V PCI SLOT 1
ADD/AGP
Connector
GMCH VR
PG 34
PS/2
PG 36
Hitachi H8S
2149
PG 32
LPC PM
Headers
PS/2
PG 36
PG 37
PG 33
PG 21
1
Serial
Parallel
FIR
FDD
PG 35
PG 35
PG 35
PG 35
Scan
KB
PG 36
1
I
Title
Size
A
Date:
A
B
C
BLOCK DIAGRAM
Document Number
Project:
Friday, May 21, 2004
D
Sheet
1
Rev
of
E
46
A
B
C
D
E
CUSTOMER REFERENCE PLATFORM
SCHEMATIC ANNOTATIONS AND BOARD INFORMATION
2
I C / SMB Addresses
Voltage Rails
Default Jumper Settings
4
3
4
+VDC
+VCC_IMVP
+VCC_VID
+V1.5S
+V1.25S
+V1.5S
+V1.5ALWAYS
+V1.5
+V2.5
+V3.3ALWAYS
+V3.3
+V3.3S
+V5ALWAYS
+V5
+V5S
+V12S
-V12S
Primary DC system power supply (10 to 21V)
Core/VTT voltage for processor & VTT for GMCH
1.2V for processor PLL and VID circuitry
1.5V for GMCH core/hub interface
1.25V DDR Termination voltage
1.5V switched power rail (off in S3-S5)
1.5V always on power rail
1.5V power rail (off in S4-S5)
2.5V power rail for DDR
3.3V always on power rail
3.3V power rail (off in S4-S5)
3.3V switched power rail (off in S3-S5)
5.0V for ICH4M's VCC5REFSUS
5.0V power rail (off in S4-S5)
5.0V switched power rail (off in S3-S5)
12.0V switched power rail (off in S3-S5)
-12.0V switched power rail for PCI (off in S3-S5)
Device
Clock Generator
Spread Spectrum Clock
SO-DIMM0
SO-DIMM1
Thermal Sensor Header
LVDS Backlight Inverter
Dock Connector
Smart Battery
Smart Battery Charger
Smart Selector
Bluetooth Header
LPC Pwr Mngmnt Header
LPC Pwr Mngmnt Header
Thermal Diode
Address
1101 001x
1101 010x
1010 000x
1010 001x
1001 000x
____ ____
____ ____
0001 011x
0001 001x
0001 010x
____ ____
____ ____
____ ____
1001 110x
Hex
D2
D4
A0
A2
90
__
__
16
12
14
__
__
__
9C
Bus
SMB_ICH_S
SMB_ICH_S
SMB_ICH_S
SMB_ICH_S
SMB_ICH
SMB_ICH
SMB_ICH
SMB_SB
SMB_SB
SMB_SB
SMB_SB
SMB_SB
SMB_THRM
SMB_THRM
EV Support:
DV0-DV3
V5-V8
PV0-PV3
DV4
V9-V12
I1-I4
EP1-EP4
PV4
V1-V4
0101 0001
0101 0010
0101 0011
0101 0100
0101 0101
0101 0110
0101 0111
0101 0100
0101 1001
51
52
53
54
55
56
57
58
59
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
SMB_ICH
Jumper
J7B1
J7B3
J7B4
J7B5
J7B6
J6E1
J6C2
J7F1
J3H1
J2J3
J8J2
J9E2
J9E4
J9E5
J9B1
J9A1
J8A2
J8A1
J9H1
J9G2
J1F1
J1G1
J1G2
J1G3
J1G4
J1H1
J1H2
J3G1
J3G2
Option
1-X
1-2
1-2
1-X
1-X
1-2
1-X
2-3
1-X
1-2
1-2
2-3
2-3
1-2
1-2
1-2
2-3
1-X
1-2
2-3
1-2
2-3
2-3
2-3
2-3
2-3
1-X or 2-3
1-2 or 2-3
1-2 or 2-3
Default
1-2
1-X
1-X
1-2
1-2
2-3
1-2
1-2
1-2
1-X
2-3
1-2
1-2
2-3
1-X
1-X
1-2
1-2
1-X
1-2
1-X
1-2
1-2
1-2
1-2
1-2
1-2
1-X
1-X
Page
Description
GMCH Strap: PSB Voltage
08
08
GMCH Strap: DVO/AGP
08
GMCH Strap: Clock Config
GMCH Strap: Clock Config
08
GMCH Strap: Clock Config
08
LVDS EV
08
AGP D3 Hot Support (3.3V)
15
AGP D3 On Support (1.5V)
15
Docking VGA Enable
17
CMOS Clear
19
19
CRB/SV Detect
Moon ISA Support
23
23
Moon ISA Support
23
Moon ISA Support
SMC/KBC Hardware Programming 32
KBC 60/64 Decode Disable
32
SMC/KBC Disable
32
NMI Jumper, SMC Programming
33
33
Port 80-81/82-83 Select
SIO Disable
34
Manual VID Strap Enable
39
VID0 Strap
39
39
VID1 Strap
VID2 Strap
39
39
VID3 Strap
39
VID4 Strap
VID5 Strap
39
DDR EV Support
43
DDR VR Vsense
43
3
PCI Devices
Device
Slot 1
Slot 2
Slot 3
IDSEL #
AD16
AD17
AD18
REQ/GNT #
1
1
2
2
3
3
Docking
LAN
AD28
(AD24 internal)
4
4
LEDs and Switches
PC/PCI
A
A
A
Interrupts
F, G, H, E
G, F, E, H
C, D, B, A
(E, F, G, H optional)
D, A, B, C
(E internal)
B
2
Wake Events
LED
Primary IDE
Secondary IDE
SMC/KBC Num Lock
SMC/KBC Scroll Lock
SMC/KBC Caps Lock
S0 State
S1 State
S3 State
S4 State
S5 State
VID0
VID1
VID2
VID3
VID4
VID5
Page
27
27
32
32
32
38
38
38
38
38
39
39
39
39
39
39
Reference
DS2J2
DS2J1
DS8A1
DS8A2
DS8B1
DS1H1
DS1H3
DS1H2
DS2H2
DS2H1
DS1J4
DS1J3
DS1J2
DS2J4
DS2J3
DS1J1
Switch
Virtual Battery On/Off
Lid
Power On/Off
Reset
Page
32
32
44
44
Reference
SW8A1
SW9A1
SW8J1
SW7J1
RI# (Ring Indicate) from serial port
PME# (Power Management Event) from PCI/mini-PCI slots,
ADD slot, LPC slot
I/O from the LAN Interface
LID switch attached to SMC
USB
AC97 wake on ring
SmLink for AOL II
Hot Key from the scan matrix keyboard
2
Net Naming Conventions
Suffix
= Active Low signal
#
Prefix
H
= Host
M = DDR Memory
Power States
PCB Footprints
As seen from top
SIGNAL
SLP_S1#
STATE
SLP_S3#
SLP_S4#
SLP_S5# +V*ALWAYS
+V*
+V*S
Clocks
SOT-23
1
Full ON
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1M (Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend To Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
Title
S5 / Soft OFF
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Size
A
Date:
3
1
2
A
TP = Test Point (does not
connect anywhere else)
B
C
1
SOT23-5
5
2
3
1
4
Notes and Annotations
Document Number
Project:
Friday, May 21, 2004
D
Sheet
2
Rev
of
E
46
B
C
TP_CPU_A35# AB1
TP_CPU_A34# Y1
TP_CPU_A33# W2
TP_CPU_A32# V3
H_A#31
U4
H_A#30
T5
H_A#29
W1
H_A#28
R6
H_A#27
V2
H_A#26
T4
H_A#25
U3
H_A#24
P6
H_A#23
U1
H_A#22
T2
H_A#21
R3
H_A#20
P4
H_A#19
P3
H_A#18
R2
H_A#17
T1
R5
H_ADSTB#1
A35#
A34#
A33#
A32#
A31#
A30#
A29#
A28#
A27#
A26#
A25#
A24#
A23#
A22#
A21#
A20#
A19#
A18#
A17#
ADSTB1#
4
8
H_A#[16:3]
8
H_ADSTB#0
H_A#[31:17]
3
8
DP3#
DP2#
DP1#
DP0#
DEFER#
DRDY#
DBSY#
L25
K26
K25
J26
E2
H2
H5
TESTHI8
TESTHI9
TESTHI10
BR0#
U6
W4
Y3
H6
IERR#
AC3
INIT#
W5
LOCK#
CONTROL
8
G1
AC1
V5
AA3
G2
D2
H_ADS#
8
TP_CPU_AP0#
TP_CPU_AP1#
TP_CPU_BINIT#
8
U2E1A
H_D#[15:0]
H_D#15
H_D#14
H_D#13
H_D#12
H_D#11
H_D#10
H_D#9
H_D#8
H_D#7
H_D#6
H_D#5
H_D#4
H_D#3
H_D#2
H_D#1
H_D#0
H_BNR# 8
H_BPRI# 8
TP_CPU_DP3#
TP_CPU_DP2#
TP_CPU_DP1# 4,5,9,10,18,20,40,41,47,48
TP_CPU_DP0#
+VCC_IMVP
H_DEFER# 8
H_DRDY# 8
H_DBSY# 8
R2T1
H_REQ#[4:0]
ADDR GROUP 1
8
H_REQ#4
H_REQ#3
H_REQ#2
H_REQ#1
H_REQ#0
ADS#
AP0#
AP1#
BINIT#
BNR#
BPRI#
MCERR#
RESET#
RS2#
RS1#
RS0#
RSP#
TRDY#
HIT#
HITM#
H_BR3# 2 RP2D1B 7 56
H_BR2# 4 RP2D1D 5 56
H_BR1# 3 RP2D1C 6 56
220
H_BR0#
4,5,9,10,18,20,40,41,47,48 +VCC_IMVP
H_IERR_PU# 1 RP2D1A 8 56
H_INIT#
8
8
8
8
8
H_D#31
H_D#30
H_D#29
H_D#28
H_D#27
H_D#26
H_D#25
H_D#24
H_D#23
H_D#22
H_D#21
H_D#20
H_D#19
H_D#18
H_D#17
H_D#16
18,37
4,5,9,10,18,20,40,41,47,48
G4
H_LOCK# 8
+VCC_IMVP
V6
TP_CPU_MCERR#
AB25
F4
G5
F1
AB2
J6
H_RS#2
H_RS#1
H_RS#0
TP_CPU_RSP#
R3R1
NO_STUFF_51
H_RS#2
H_RS#1
H_RS#0
H_CPURST# 5,8
8
8
8
8
8
8
H_TRDY# 8
F3
E3
H_DINV#0
H_DSTBN#0
H_DSTBP#0
H_D#[31:16]
H_DINV#1
H_DSTBN#1
H_DSTBP#1
D25
J21
D23
C26
H21
G22
B25
C24
C23
B24
D22
C21
A25
A23
B22
B21
E21
E22
F21
D15#
D14#
D13#
D12#
D11#
D10#
D9#
D8#
D7#
D6#
D5#
D4#
D3#
D2#
D1#
D0#
DBI0#
DSTBN0#
DSTBP0#
H25
K23
J24
L22
M21
H24
G26
L21
D26
F26
E25
F24
F23
G23
E24
H22
G25
K22
J23
D31#
D30#
D29#
D28#
D27#
D26#
D25#
D24#
D23#
D22#
D21#
D20#
D19#
D18#
D17#
D16#
DBI1#
DSTBN1#
DSTBP1#
DATA GRP 0
A16#
A15#
A14#
A13#
A12#
A11#
A10#
A9#
A8#
A7#
A6#
A5#
A4#
A3#
ADSTB0#
REQ4#
REQ3#
REQ2#
REQ1#
REQ0#
ADDR GROUP 0
N5
N4
N2
M1
N1
M4
M3
L2
M6
L3
K1
L6
K4
K2
L5
H3
J3
J4
K5
J1
E
DATA GRP 1
H_A#16
H_A#15
H_A#14
H_A#13
H_A#12
H_A#11
H_A#10
H_A#9
H_A#8
H_A#7
H_A#6
H_A#5
H_A#4
H_A#3
D
DATA GRP 2
U2E1B
DATA GRP 3
A
D47#
D46#
D45#
D44#
D43#
D42#
D41#
D40#
D39#
D38#
D37#
D36#
D35#
D34#
D33#
D32#
DBI2#
DSTBN2#
DSTBP2#
T23
T22
T25
T26
R24
R25
P24
R21
N25
N26
M26
N23
M24
P21
N22
M23
P26
R22
P23
H_D#47
H_D#46
H_D#45
H_D#44
H_D#43
H_D#42
H_D#41
H_D#40
H_D#39
H_D#38
H_D#37
H_D#36
H_D#35
H_D#34
H_D#33
H_D#32
D63#
D62#
D61#
D60#
D59#
D58#
D57#
D56#
D55#
D54#
D53#
D52#
D51#
D50#
D49#
D48#
DBI3#
DSTBN3#
DSTBP3#
AA24
AA22
AA25
Y21
Y24
Y23
W25
Y26
W26
V24
V22
U21
V25
U23
U24
U26
V21
W22
W23
H_D#63
H_D#62
H_D#61
H_D#60
H_D#59
H_D#58
H_D#57
H_D#56
H_D#55
H_D#54
H_D#53
H_D#52
H_D#51
H_D#50
H_D#49
H_D#48
H_D#[47:32] 8
4
H_DINV#2 8
H_DSTBN#2 8
H_DSTBP#2 8
H_D#[63:48] 8
3
H_DINV#3 8
H_DSTBN#3 8
H_DSTBP#3 8
Processor-MobilSkt
H_HIT#
8
H_HITM# 8
Processor-MobilSkt
6 CLK_CPU_BCLK
R2F1
49.9_1%
4,5,9,10,18,20,40,41,47,48
6 CLK_CPU_BCLK#
R2F2
49.9_1%
R3F1
49.9_1%
H_THERMDA
H_THERMDC
PM_THRMTRIP#
39,40 H_PROCHOT#
+VCC_IMVP
4,5,9,10,18,20,40,41,47,48
RP4C1C 6
56
3 H_TESTHI5
RP4C1B 7
56
2 H_TESTHI4
RP3C1C 6
56
3 H_TESTHI3
RP3C1B 7
56
2 H_TESTHI2
RP3C1D 5
56
4 H_TESTHI1
RP4C1A 8
56
1 H_TESTHI0
TP_CPU_NC0
TP_CPU_NC1
1
40 H_VIDPWRGD
H_VID5
+VCC_VID
R2R1
0
C2R1
0.1uF
A20M#
FERR#/PBE#
IGNNE#
D1
E5
B5
Y4
LINT0
LINT1
SMI#
STPCLK#
B3
C4
A2
C3
THERMDA
THERMDC
THERMTRIP#
PROCHOT#
AC23
AC24
AC20
AC21
AA2
AD24
A22
A7
AD2
AD3
TP_CPU_NC4
AE21
VCC_VID_CPU_D AF3
TP_CPU_NC6
AF24
TP_CPU_NC7
AF25
TESTHI5
TESTHI4
TESTHI3
TESTHI2
TESTHI1
TESTHI0
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
AD6
AD5
A6
H_BSEL0 6
H_BSEL1 6
PM_CPUPERF# 19,37
DPSLP#
SLP#
AD25
AB26
H_DPSLP# 7,18,37
H_CPUSLP# 18,37
COMP0
COMP1
L24
P1
GTLREF3
GTLREF2
GTLREF1
GTLREF0
H_COMP0
H_COMP1
R3R5
R2R5
B
61.9_1%
61.9_1%
AA21 TP_GTLREF3
AA6
F20 TP_GTLREF1
F6 TP_GTLREF0
2
4,5,9,10,18,20,40,41,47,48
Trace length: Less
than 1.5 inch
R2R2
51.1_1%
C2R6
C2R8
220PF
BPM5#
BPM4#
BPM3#
BPM2#
BPM1#
BPM0#
ITPCLKOUT0
ITPCLKOUT1
DBR#
TCK
TDI
TDO
TMS
TRST#
SKTOCC#
AB4
AA5
Y6
AC4
AB5
AC6
AA20
AB22
AE25
D4
C1
D5
F7
E6
+VCC_IMVP
H_GTLREF 47
H_BPM5_PREQ# 5
H_BPM4_PRDY# 5
H_BPM3_ITP# 5
H_BPM2_ITP# 5
H_BPM1_ITP# 5
H_BPM0_ITP# 5
H_ITPCLKOUT0
H_ITPCLKOUT1
1
4
C
1UF
4,5,9,10,18,20,40,41,47,48
56
8 RP3C1A
56
RP4C1D
5
ITP_DBRESET# 5,44,47
H_TCK
5
H_TDI
5
H_TDO
5
H_TMS
5
H_TRST# 5
R1F9
680
R2R4
86.6
1%
Place 1 GTLREF cap near
each pin under processor.
Title
AF26 TP_CPU_SKTOCC#
Processor-MobilSkt
<NO_STUFF>
VCC_VID_CPU_D
A
HOST
CLK
C6
B6
B2
BSEL0
FSBSEL1
GHI#
1
5
5
49.9_1%
REF & COMP
H_A20M#
H_FERR#
H_IGNNE#
H_INTR
H_NMI
H_SMI#
H_STPCLK#
TAP/ITP
R3F2
18
18
18
18,37
18,37
18,37
18,37
BCLK0
BCLK1
ITP_CLK0
ITP_CLK1
LEGACY CPU
6 CLK_ITP_CPU#
AF22
AF23
AC26
AD26
THERM
2
39
R2T3
300
U2E1C
6 CLK_ITP_CPU
40
+VCC_IMVP
2
Note: Host Clock
terminations are at
the source (CK408)
4,5,9,10,18,20,40,41,47,48
+VCC_IMVP
+VCC_IMVP
R6H11
56
PM_THRMTRIP#
19 PM_THRMTRIP#
Processor 1 of 2
Project:
Size
Custom
Date:
Friday, May 21, 2004
D
Document Number
Sheet
3
Rev
of
E
46
1
A
B
3
40 BOOTSELECT
2
TP_PSC_50_60_Buffer
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS104
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
B4
B8
C11
C13
C15
C17
C19
C2
C22
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
E1
E11
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
F8
G21
G24
G3
G6
H1
H23
H26
H4
J2
J22
J25
J5
K21
K24
T21
T24
T3
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
K3
D
3,5,9,10,18,20,40,41,47,48
E
+VCC_IMVP
U2E1D
A10
A12
A14
A16
A18
A20
A8
AA10
AA12
AA14
AA16
AA18
AA8
AB11
AB13
AB15
AB17
AB19
AB7
AB9
AC10
AC12
AC14
AC16
AC18
AC8
AD11
AD13
AD15
AD17
AD19
AD7
AD9
AE10
AE12
AE14
AE16
AE18
AE20
AE6
AE8
AF11
AF13
E14
E16
E18
E20
E8
F11
F13
F15
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
VCC18
VCC19
VCC20
VCC21
VCC22
VCC23
VCC24
VCC25
VCC26
VCC27
VCC28
VCC29
VCC30
VCC31
VCC32
VCC33
VCC34
VCC35
VCC36
VCC37
VCC38
VCC39
VCC40
VCC41
VCC42
VCC43
VCC44
VCC45
VCC46
VCC47
VCC48
VCC49
VCC50
VCC51
R2D3
POWER
4
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
C
Processor-MobilSkt
VSS
U2E1E
A11
A13
A15
A17
A19
A21
A24
A26
A3
A9
AA1
AA11
AA13
AA15
AA17
AA19
AA23
AA26
AA4
AA7
AA9
AB10
AB12
AB14
AB16
AB18
AB20
AB21
AB24
AB3
AB6
AB8
AC11
AC13
AC15
AC17
AC19
AC2
AC22
AC25
AC5
AC7
AC9
AD1
AD10
AD12
AD14
AD16
AD18
AD21
AD23
AD4
AD8
AE11
AE13
AE15
AE17
AE19
AE22
AE24
AE26
AE7
AE9
AF1
AF10
AF12
AF14
AF16
AF18
AF20
AF6
AF8
B10
B12
B14
B16
B18
B20
B23
B26
VCC52
VCC53
VCC54
VCC55
VCC56
VCC57
VCC58
VCC59
VCC60
VCC61
VCC62
VCC63
VCC64
VCC65
VCC66
VCC67
VCC68
VCC69
VCC70
VCC71
VCC72
VCC73
VCC74
VCC75
VCC76
VCC77
VCC78
VCC79
VCC80
VCC81
VCC82
VCC83
VCC84
VCC85
F17
F19
F9
AF15
AF17
AF19
AF2
AF21
AF5
AF7
AF9
B11
B13
B15
B17
B19
B7
B9
C10
C12
C14
C16
C18
C20
C8
D11
D13
D15
D17
D19
D7
D9
E10
E12
4
VCC_IMVP_CPU_D
VCC_IMVP_CPU_D
Layout Note:
C3D4 should be placed within 600 mils of the
VCCA and VSSA pins
VCCA should be routed in parallel and next to
VSSA
AE1
AE2
AE3
AE4
AE5
H_VID4
H_VID3
H_VID2
H_VID1
H_VID0
VCCA
VCCSENSE
VCCIOPLL
VSSA
VSSSENSE
VCCVID
AD20
A5
AE23
AD22
A4
AF4
H_VCCA
PWRGOOD
AB23
VID4
VID3
VID2
VID1
VID0
0
H_VID[4:0]
39
3,5,9,10,18,20,40,41,47,48
3
+VCC_IMVP
L4D2
1
C3D4
33uF
L4D1
CORE_VCCSENSE 40
H_VCCIOPLL
H_VSSA
1
2
10uH 10%
CORE_VSSSENSE 40
3,40
2
10uH 10%
2
+VCC_VID
Processor-MobilSkt
3,5,9,10,18,20,40,41,47,48
TP2E2 TP2E1
+VCC_IMVP
R3R2
300
H_PWRGD 18,37
1
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
R1
R23
R26
R4
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
VSS169
VSS170
VSS171
VSS172
VSS173
VSS174
VSS175
VSS176
VSS177
VSS178
VSS179
VSS180
VSS181
VSS182
1
Title
Size
A
Date:
A
B
C
Processor 2 of 2
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
4
E
46
A
B
C
D
E
Processor Thermal Sensor
6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
4
3
RP2A1C
10K
ADD0
ADD1
0
H_THERMDC_D
H_THERMDC
4
7
8
NO_STUFF_3Pin_Recepticle
J4A1
VCC
DXP
DXN
ADD0
ADD1
STBY#
15
SMBDATA
SMBCLK
ALERT#
12
14
11
GND1
GND2
NC1
NC2
NC3
NC4
NC5
1
5
9
13
16
STBY#
6
2
3
4
10
6
7
0
H_THERMDA_D
R3B1
RP2A1B
10K
U3A1
H_THERMDA
C3A10
2200PF
3
R2B2
1K
RP2A1D
10K
R3A7
3
R3B2
1K
5
4
C3A9
0.1UF
+V3.3S
2
6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
Address Select Straps
Current Address:
1001 110x
SMB_THRM_DATA 32,37
SMB_THRM_CLK 32,37
THRM_ALERT#
R2B1
NO_STUFF_0
PM_THRM# 19,21,32,37
ADM1023
Layout Note:
Route H_THERMDA and
H_THERMDC on same
layer.
10 mil trace on 10 mil
spacing.
2
THERMDP
1
THERMDN
Note: No Stuff for
Normal Operation
GND2
GND0
GND1 3 4 5 6 GND3
3
3
Thermal Diode Conn
Note:
If using Thermal Diode
Conn, NO STUFF
C3A10 and U3A1.
Place TDO
pullup resistor
within 2" of
ITP.
3,4,9,10,18,20,40,41,47,48
Place TDI pullup
resistor within
300ps of the
processor
+VCC_IMVP
R1F4
R1F8
R1F10
R2T2
51
75
39.2_1%
150
H_BPM[5:0]*
signals should
be matched to
within 0.25" of
each other and
not longer than
6.0".
Place 0.1uF cap within
0.1" of VTT pins on ITP.
1
Place RESET# serial
resistor within 0.1" and
RESET pull up resistor
should be close to ITP
within 90ps
2
Place TMS
pullup resistor
within 1" of
ITP.
3,4,9,10,18,20,40,41,47,48
+VCC_IMVP
15,19,20,21,22,23,27,28,29,32,36,37,38,39,44,48
3,4,9,10,18,20,40,41,47,48
2
+VCC_IMVP
+V3.3ALWAYS
The ITP should be at
the end of the
H_CPURST#
transmission line but
less than 6.0" from
the processor.
3
3
3
3
3
H_TDI
H_TMS
H_TCK
H_TDO
H_TRST#
3,8
H_CPURST#
3
H_TCK
6
6
CLK_ITP#
CLK_ITP
2
J1F2
Run separate H_TCK
trace to processor for
FBO and TCK pins on
ITP.
R1F5
RESET_FLEX#
12
11
R1F6
27.4_1%
2
TDI
TMS
TCK
TDO
TRST#
RESET#
VTT0
VTT1
VTAP
27
28
26
DBR#
DBA#
25
24
BCLKn
BCLKp
BPM0#
BPM1#
BPM2#
BPM3#
BPM4#
BPM5#
23
21
19
17
15
13
10
14
16
18
20
22
GND0
GND1
GND2
GND3
GND4
GND5
NC1
NC2
0.1uF
R1F2
R2D5
R2D7
R2D9
R2D8
R2D4
51
51
51
51
51
51
Place BPM pullups
near processor.
ITP_DBRESET# 3,44,47
DBA# may be left
unconnected.
H_BPM0_ITP# 3
H_BPM1_ITP# 3
H_BPM2_ITP# 3
H_BPM3_ITP# 3
H_BPM4_PRDY# 3
H_BPM5_PREQ# 3
Title
Size
A
Date:
B
R2D6
1
4
6
ITP700-FLEXCON
Place TCK
pulldown resistor
within 1" of ITP.
C1F1
150
FBO
8
9
1
1
A
150
1
2
5
7
3
C
Processor Thermal Sensor & ITP
Document Number
Project:
Friday, May 21, 2004
D
Sheet
5
Rev
of
E
46
A
B
C
D
E
5,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
+V3.3S_CLKRC
J3F2
3
4
+V3.3S_CLKVDD
Place crystal within 500
mils of CK_408
1
2
C2F4
22UF
Place 0ohm near
crystal.
1UF
C3U3
0.1UF
1
C3F4
NO_STUFF_10pF
2
C3F2
C2U1
0.1UF
NO_STUFF_10pF
C2F2
22UF
1
8
14
19
32
37
46
50
+V3.3S_CLKVDD5
No stuff; caps are
internal to CK-408.
R3F8
330
R2U2
1
H_BSEL1
3
BSEL0_Q
3
BSEL1_Q
2
2
No Stuff
Measurement Point
CK408 CLOCK
SWING CONFIG
0.7 VOLTS
33
CPUC2
R2F4
33
CPU1
R3F14
33
CPU1#
R3F15
33
48
CK408_SEL2
40
55
54
25
34
MULT0
R2G1
33
CLK_66SSC
Keep stub short -->
J3F1
1
R2F3
CPU2#
CPUT1
10K
NO_STUFF_10K
SSC_CLK_IN
CPU2
44
CPUC1
8,11,12,16,18,39 SMB_DATA_S
8,11,12,16,18,39 SMB_CLK_S
CR3F2
NO_STUFF_BAR43
NO_STUFF_BAR43
CR3F1
45
XTAL_OUT
39 VR_PWRGD_CK408#
NO_STUFF_0
CPUT2
XTAL_IN
1K
NO_STUFF_0
R3U2
27
3
19,37 PM_STPPCI#
R2U1
R3U3
VSSA
XTAL_OUT
1
H_BSEL0
26
49
19,37,39,40 PM_STPCPU#
0
VDDA
2
19,37,38,44 PM_SLP_S1#
+V3.3S_CLKRC
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
XTAL_IN
CK408_SEL0
R3F7
NO_STUFF_0
R3U1
C2U2
C2U3
C3U2
0.1UF
0.1UF
0.1UF
+V3S_CLKVDDA
C2G1
CK_IREF
R2U3
475_1%
R2G2
CPUT0
52
CPU0
CPUC0
51
CPU0#
66IN/3V66_5
24
66OUT
66B2/3V66_4
23
66BUF2
22
66BUF1
21
66BUF0
PCIF2
SEL2
SEL1
SEL0
PWRDWN#
PCI_STOP#
66B1/3V66_3
66B0/3V66_2
PCIF2
7
28
VTT_PWRGD#
PCIF1
6
43
MULT0
PCIF0
5
PCIF0
29
SDATA
PCI6
18
PCI6
30
SCLOCK
PCI5
17
PCI5
33
3V66_0
PCI4
16
PCI4
35
3V66_1/VCH
PCI3
13
PCI3
42
IREF
PCI2
12
PCI2
PCI1
11
PCI1
VSS0
VSS1
VSS6
VSS2
VSS3
VSS4
VSS5
1
5,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
C2G12
0.1UF
CLK_CPU_BCLK 3
CLK_CPU_BCLK# 3
R3F5
R3F13
R2F9
33
33
RP2F3B
2
7
33
3 RP2F3C 6
33
4 RP2F3D 5
33
2 RP3F1B 7
33
CLK_ITP
CLK_HUBLAI 10
CLK_MCH66 7
CLK_ICH66 18
CLK_ICHPCI
33
3 RP3F1C 6
33
2 RP2F2B 7
33
3 RP2F2C 6
33
4 RP2F2D 5
33
1 RP2F1A 8
33
2 RP2F1B 7
33
3 RP2F1C 6
33
4 RP2F1D 5
33
1 RP3F1A 8
PCI0
10
PCI0
48MUSB
39
USB
48MDOT
38
DOT
R2F6
33
REF
56
CLK_REF0
R3F20
33
R3F17
33
R2F5
18
CLK_PCI_PORT80 33
CLK_PCI_SLOT3 23
CLK_PCI_SLOT2 22
CLK_PCI_SLOT1 22
CLK_DOCKPCI 24
CLK_FWHPCI
31
CLK_SIOPCI 34
CLK_SMCPCI 32
CLK_LPCPCI 37
33
R3F19
CLK_ICH48 19
SSC_CLK_IN
CLKIN
2
VDD
2
1
3
1
GND
PD#
SCLK
SDATA
8
R2G8
3
C2G3 1
2 NO_STUFF_10pF
C2G2 1
2 NO_STUFF_10pF
C2G8 1
2 NO_STUFF_10pF
C3G3 1
2 NO_STUFF_10pF
C3G2 1
2 NO_STUFF_10pF
C2G7 1
2 NO_STUFF_10pF
C2G101
2 NO_STUFF_10pF
C2G6 1
2 NO_STUFF_10pF
C2G5 1
2 NO_STUFF_10pF
C2G4 1
2 NO_STUFF_10pF
C2G9 1
2 NO_STUFF_10pF
C3G4 1
2 NO_STUFF_10pF
C3G6 1
2 NO_STUFF_10pF
C2F1 1
2 NO_STUFF_10pF
C3F5 1
2 NO_STUFF_10pF
C3F1 1
2 NO_STUFF_10pF
C3F3 1
2 NO_STUFF_10pF
2
CLK_LPC14 37
CLK_SIO14 34
33
CLK_ICH14 19
R2G4
NO_STUFF_0
6 SSC_SDATA
R2G6
NO_STUFF_0
R2G3
0
R2G5
0
LCLKCTLA 7,16
SMB_CLK_S 8,11,12,16,18,39
LCLKCTLB 7,8,16
SMB_DATA_S 8,11,12,16,18,39
1
+V3.3S
DREFSSCLK_D
33
ICS91718
REF_OUT
R2G9
R2G10
10K
A
CLK_ITP# 5
49.9_1%
PM_SLP_S1# 19,37,38,44
7 SSC_SCLK
4 CLKOUT REF_OUT 5
5,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
DREFSSCLK
CLK_ITP_CPU# 3
DREFCLK 7
U2G2
0.1UF
5
CLK_ITP_CPU 3
NO_STUFF_33
33
Keep stub short -->
1UF
CLK_MCH_BCLK 8
CLK_MCH_BCLK# 8
49.9_1%
CLK_AGP_SLOT 15
+V3.3S
C2G13
2
R3F16
NO_STUFF_33
R3F9
VSSIREF
CK-408
7
0.01_1%
300ohm@100MHz
R3F6
CPU_STOP#
4
9
15
20
31
36
47
0.1UF
1
C2F7
R3F12
53
41
C2F5
22UF
0.1UF
U3F1
+V3.3S_CLKRC
FB2F2
300ohm@100MHz
1
2
R3F10
NO_STUFF_1K
1
C3U1
0.1UF
C2U7
CK408_SEL1
IREF
R2U3
475 1%
C2F3
0.1UF
4
3
MULT
C2U6
0.1UF
FB2F3
14.318MHZ
Y3F1
1
2
R3F11
330
3
0.1UF
R3F18
NO_STUFF_0
+V3.3S_CLKRC
3
C2U4
C2U5
R2F7
FB2F1
1
2
300ohm@100MHz
2
NO_STUFF_SMA CON
4
1
5
2
XTAL_IN_D
1
B
10K
Title
Size
A
Date:
C
CK-408
Document Number
Project:
Friday, May 21, 2004
D
Sheet
6
Rev
of
E
46
A
B
C
13 M_CB[7:0]
AC18
AD14
AD13
AD17
AD11
AC13
AD8
AD7
AC6
AC5
AC19
AD5
AB5
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA5
M_AA6
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_AA12
M_AA0
12,13,14
M_AA[2:1] 11,14
AD16
AC12
AF11
AD10
M_AB1
M_AB2
M_AB4
M_AB5
M_AA[12:6] 12,13,14
SMA_B1
SMA_B2
SMA_B4
SMA_B5
SCKE0
SCKE1
SCKE2
SCKE3
SCS0#
SCS1#
SCS2#
SCS3#
AC7
AB7
AC9
AC10
AD23
AD26
AC22
AC25
M_AB[5:4]
M_CKE0
M_CKE1
M_CKE2
M_CKE3
M_CS0#
M_CS1#
M_CS2#
M_CS3#
12,14
11,12,14
11,12,14
12,14
12,14
11,12,14
11,12,14
12,14
12,14
SBA0
SBA1
AD22
AD20
M_BS0#
M_BS1#
12,13,14
12,13,14
SRAS#
SCAS#
SWE#
AC21
AC24
AD25
M_RAS#
M_CAS#
M_WE#
12,13,14
12,13,14
12,13,14
SCK[0]
SCK[0]#
SCK[1]
SCK[1]#
SCK[2]
SCK[2]#
SCK[3]
SCK[3]#
SCK[4]
SCK[4]#
SCK[5]
SCK[5]#
AB2
AA2
AC26
AB25
AC3
AD4
AC2
AD2
AB23
AB24
AA3
AB4
SDM0
SDM1
SDM2
SDM3
SDM4
SDM5
SDM6
SDM7
SDM8
AE5
AE6
AE9
AH12
AD19
AD21
AD24
AH28
AH15
M_CLK_DDR0 11
M_CLK_DDR0# 11
M_CLK_DDR1 11
M_CLK_DDR1# 11
M_CLK_DDR2 11
M_CLK_DDR2# 11
M_CLK_DDR3 12
M_CLK_DDR3# 12
M_CLK_DDR4 12
M_CLK_DDR4# 12
M_CLK_DDR5 12
M_CLK_DDR5# 12
M_DM[8:0] 13
AC15
AC16
RCVENOUT#
RCVENIN#
C5F13
0.1UF
SMVREF
852GME
GAD3/DVOBD0
GAD2/DVOBD1
GAD5/DVOBD2
GAD4/DVOBD3
GAD7/DVOBD4
GAD6/DVOBD5
GAD8/DVOBD6
GCBE#0/DVOBD7
GAD10/DVOBD8
GAD9/DVOBD9
GAD12/DVOBD10
GAD11/DVOBD11
15
15
15
15
15
AGP_ADSTB0
AGP_ADSTB#0
AGP_AD0
AGP_AD1
AGP_CBE#1
15 AGP_AD14
P3
P4
T6
T5
L2
M2
GADSTB0/DVOBCLK
GADSTB#0/DVOBCLK#
GAD0/DVOBHSYNC
GAD1/DVOBVSYNC
GCBE#1/DVOBBLANK#
GAD14/DVOBFLDSTL
15 AGP_AD30
15 AGP_AD13
G2
M3
GAD30/DVOBCINTR#
GAD13/DVOBCCLKINT
8,9,48
+V1.5S_GMCH_AGP
R6E3
100K
12,13,14
M_AA[5:4] 11,14
R6E5
100K
M_AB[2:1] 12,14
M_DM0
M_DM1
M_DM2
M_DM3
M_DM4
M_DM5
M_DM6
M_DM7
M_DM8
15
R6E6
100K
TP_M_RCVO#
TP_M_RCVI#
MCH_SMRCOMP 10
MCH_SMVSWINGL 10
MCH_SMVSWINGH 10
C5F6
C5F5
0.1UF
0.1UF
E8
DAC_REFSET 10
B6
G9
DAC_DDCACLK 17,24
DAC_DDCADATA 17,24
IYAM0
IYAM1
IYAM2
IYAM3
IYAP0
IYAP1
IYAP2
IYAP3
IYBM0
IYBM1
IYBM2
IYBM3
IYBP0
IYBP1
IYBP2
IYBP3
ICLKAM
ICLKAP
ICLKBM
ICLKBP
15
15
15
15
15
AGP_STB1
AGP_STB#1
AGP_AD17
AGP_AD16
AGP_AD18
J3
J2
K6
L5
L3
H5
GADSTB1/DVOCCLK
DDCPCLK
GADSTB#1/DVOCCLK# DDCPDATA
GAD17/DVOCHSYNC
GAD16/DVOCVSYNC PANELBKLTCTL
GAD18/DVOCBLANK# PANELBKLTEN
GAD31/DVOCFLDSTL PANELVDDEN
AGP_IRDY#
AGP_DEVSEL#
AGP_TRDY#
AGP_FRAME#
AGP_STOP#
AGP_AD15
K7
N6
N7
M6
P7
T7
GIRDY#/MI2CCLK
GDEVSEL#/MI2CDATA
GTRDY#/MDVICLK
GFRAME#/MDVIDATA
GSTOP#/MDDCCLK
GAD15/MDDCDATA
E5
F5
E3
E2
G5
F4
G6
F6
L7
D5
GSBA0/ADDID0
GSBA1/ADDID1
GSBA2/ADDID2
GSBA3/ADDID3
GSBA4/ADDID4
GSBA5/ADDID5
GSBA6/ADDID6
GSBA7/ADDID7
GPAR/DVODETECT
GPIPE#/DPMS
F1
GVREF
AGP_SBA0
AGP_SBA1
AGP_SBA2
AGP_SBA3
AGP_SBA4
AGP_SBA5
AGP_SBA6
AGP_SBA7
15,47 AGP_VREF
Layout note: Route to
vias near ball
REFSET
DDCACLK
DDCADATA
GAD19/DVOCD0
GAD20/DVOCD1
GAD21/DVOCD2
GAD22/DVOCD3
GAD23/DVOCD4
GCBE#3/DVOCD5
GAD25/DVOCD6
GAD24/DVOCD7
GAD27/DVOCD8
GAD26/DVOCD9
GAD29/DVOCD10
GAD28/DVOCD11
15
15
15
15
15
15
15 AGP_SBA[7:0]
0.1UF
DAC_BLUE 17
K5
K1
K3
K2
J6
J5
H2
H1
H3
H4
H6
G3
R6D2
100K
C6E1
C9
D9
C8
D8
A7
A8
H10
J9
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_CBE#3
AGP_AD25
AGP_AD24
AGP_AD27
AGP_AD26
AGP_AD29
AGP_AD28
AGP_AD31
Place C6E1 near
GMCH
BLUE
BLUE#
GREEN
GREEN#
RED
RED#
HSYNC
VSYNC
15
15
15
15
15
15
15
15
15
15
15
15
8,15 AGP_DETECT
15 AGP_PIPE#
AJ22
AJ19
SMVSWINGL
SMVSWINGH
R3
R5
R6
R4
P6
P5
N5
P2
N2
N3
M1
M5
M_AA3
AB1
SMRCOMP
AJ24
43 SM_VREF_MCH
AGP_AD3
AGP_AD2
AGP_AD5
AGP_AD4
AGP_AD7
AGP_AD6
AGP_AD8
AGP_CBE#0
AGP_AD10
AGP_AD9
AGP_AD12
AGP_AD11
DAC
SMA_A0
SMA_A1
SMA_A2
SMA_A3
SMA_A4
SMA_A5
SMA_A6
SMA_A7
SMA_A8
SMA_A9
SMA_A10
SMA_A11
SMA_A12
15
15
15
15
15
15
15
15
15
15
15
15
15,19 AGP_BUSY#
F7
AGPBUSY#
10 MCH_GRCOMP
6
CLK_MCH66
D1
Y3
DVO_GRCOMP
GCLKIN
RSVD0
15 AGP_SBSTB
15 AGP_SBSTB#
15 AGP_GNT#
15 AGP_REQ#
8,15 AGP_ST2
8,15 AGP_ST1
8,15 AGP_ST0
15 AGP_WBF#
15 AGP_RBF#
AA5
F2
F3
B2
B3
C2
C3
C4
D2
D3
TP_RSVD10 D7
L4
15
AGP_CBE#2
LVDS
M_DQS0
M_DQS1
M_DQS2
M_DQS3
M_DQS4
M_DQS5
M_DQS6
M_DQS7
M_DQS8
RVSD0
GSBSTB
GSBSTB#
GGNT#
GREQ#
GST[2]
GST[1]
GST[0]
GWBF#
GRBF#
RVSD4
GCBE#[2]
DAC_GREEN 17
DAC_RED 17
4
DAC_HSYNC 17
DAC_VSYNC 17
G14
E15
C15
C13
F14
E14
C14
B13
H12
E12
C12
G11
G12
E11
C11
G10
D14
E13
E10
F10
LVDS_YAM0 16
LVDS_YAM1 16
LVDS_YAM2 16
LVDS_YAM3 16
LVDS_YAP0 16
LVDS_YAP1 16
LVDS_YAP2 16
LVDS_YAP3 16
LVDS_YBM0 16
LVDS_YBM1 16
LVDS_YBM2 16
LVDS_YBM3 16
LVDS_YBP0 16
LVDS_YBP1 16
LVDS_YBP2 16
LVDS_YBP3 16
LVDS_CLKAM 16
LVDS_CLKAP 16
LVDS_CLKBM 16
LVDS_CLKBP 16
B4
C5
LVDS_DDCPCLK 16
LVDS_DDCPDATA 16
G8
F8
A5
LVDS_BKLTCTL 16
LVDS_BKLTEN 16
LVDS_VDDEN 16
3
RSVD1
RSVD2
D12
F12
TP_LVDS_REFH
TP_LVDS_REFL
RSVD3
LIBG
B12
A10
LVDS_LVBG
DREFCLK
DREFSSCLK
LCLKCTLA
LCLKCTLB
B7
B17
H9
C6
DREFCLK 6
DREFSSCLK 6
LCLKCTLA 6,16
LCLKCTLB 6,8,16
DPWR#
DPSLP#
RSTIN#
AA22
Y23
AD28
H_DPSLP# 3,18,37
PCI_RST# 8,10,18,33
PWROK
J11
IMVP_PWRGD 39,41
EXTTS0
VSS182
D6
AJ1
MCH_EXTTS0 8
MCH_DETECT# 48
No Stuff
J5C2
LVDS_LIBG 8
CLKS
MISC
2
AG2
AH5
AH8
AE12
AH17
AE21
AH24
AH27
AD15
M_DQS[8:0] 13
SDQS0
SDQS1
SDQS2
SDQS3
SDQS4
SDQS5
SDQS6
SDQS7
SDQS8
NC
3
SDQ0
SDQ1
SDQ2
SDQ3
SDQ4
SDQ5
SDQ6
SDQ7
SDQ8
SDQ9
SDQ10
SDQ11
SDQ12
SDQ13
SDQ14
SDQ15
SDQ16
SDQ17
SDQ18
SDQ19
SDQ20
SDQ21
SDQ22
SDQ23
SDQ24
SDQ25
SDQ26
SDQ27
SDQ28
SDQ29
SDQ30
SDQ31
SDQ32
SDQ33
SDQ34
SDQ35
SDQ36
SDQ37
SDQ38
SDQ39
SDQ40
SDQ41
SDQ42
SDQ43
SDQ44
SDQ45
SDQ46
SDQ47
SDQ48
SDQ49
SDQ50
SDQ51
SDQ52
SDQ53
SDQ54
SDQ55
SDQ56
SDQ57
SDQ58
SDQ59
SDQ60
SDQ61
SDQ62
SDQ63
SDQ64
SDQ65
SDQ66
SDQ67
SDQ68
SDQ69
SDQ70
SDQ71
DVO
4
AF2
AE3
AF4
AH2
AD3
AE2
AG4
AH3
AD6
AG5
AG7
AE8
AF5
AH4
AF7
AH6
AF8
AG8
AH9
AG10
AH7
AD9
AF10
AE11
AH10
AH11
AG13
AF14
AG11
AD12
AF13
AH13
AH16
AG17
AF19
AE20
AD18
AE18
AH18
AG19
AH20
AG20
AF22
AH22
AF20
AH19
AH21
AG22
AE23
AH23
AE24
AH25
AG23
AF23
AF25
AG25
AH26
AE26
AG28
AF28
AG26
AF26
AE27
AD27
AG14
AE14
AE17
AG16
AH14
AE15
AF16
AF17
DDR SYSTEM MEMORY
M_DATA0
M_DATA1
M_DATA2
M_DATA3
M_DATA4
M_DATA5
M_DATA6
M_DATA7
M_DATA8
M_DATA9
M_DATA10
M_DATA11
M_DATA12
M_DATA13
M_DATA14
M_DATA15
M_DATA16
M_DATA17
M_DATA18
M_DATA19
M_DATA20
M_DATA21
M_DATA22
M_DATA23
M_DATA24
M_DATA25
M_DATA26
M_DATA27
M_DATA28
M_DATA29
M_DATA30
M_DATA31
M_DATA32
M_DATA33
M_DATA34
M_DATA35
M_DATA36
M_DATA37
M_DATA38
M_DATA39
M_DATA40
M_DATA41
M_DATA42
M_DATA43
M_DATA44
M_DATA45
M_DATA46
M_DATA47
M_DATA48
M_DATA49
M_DATA50
M_DATA51
M_DATA52
M_DATA53
M_DATA54
M_DATA55
M_DATA56
M_DATA57
M_DATA58
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
M_CB0
M_CB1
M_CB2
M_CB3
M_CB4
M_CB5
M_CB6
M_CB7
E
U5E1B
U5E1E
13 M_DATA[63:0]
D
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
2
B1 TP_MCH_NC0
AH1
A2 TP_MCH_NC2
AJ2
A28 TP_MCH_NC4
AJ28 TP_MCH_NC5
A29 TP_MCH_NC6
B29 TP_MCH_NC7
AH29 TP_MCH_NC8
AJ29 TP_MCH_NC9
AA9 TP_MCH_NC10
AJ4 TP_MCH_NC11
NC1
NC3
1
1
852GME
Title
GMCH (1 of 3)
Size Project:
A
Date:
Friday, May 21, 2004
A
B
C
D
Document Number
Sheet
Rev
of
7
E
46
C
1
2
3
4
5
6
6,11,12,16,18,39 SMB_DATA_S
6,11,12,16,18,39 SMB_CLK_S
7 MCH_EXTTS0
6Pin_HDR
Note: Host Clock
terminations are at
the source (CK408)
CLK_MCH_BCLK#
CLK_MCH_BCLK
3 H_REQ#[4:0]
3
R3F4
R3F3
49.9_1% 49.9_1%
3
3
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
R28
P25
R23
R25
T23
T26
AA26
HREQ0#
HREQ1#
HREQ2#
HREQ3#
HREQ4#
HADSTB0#
HADSTB1#
AD29
AE29
H28
K28
B20
B18
BCLK#
BCLK
HYRCOMP
HYSWING
HXRCOMP
HXSWING
H_ADSTB#0
H_ADSTB#1
6 CLK_MCH_BCLK#
6 CLK_MCH_BCLK
10 MCH_HYRCOMP
10,47 MCH_HYSWING
10 MCH_HXRCOMP
10,47 MCH_HXSWING
C4E2 C5R2
2
Layout Note:
Route
MCH_HXSWING,
MCH_HYSWING
10 mil trace, 20 mil
space
0.1UF 0.1UF
3
3
3
3
3
3
3
3
3
3
3
3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
3,5
H_CPURST#
C5T1
1
10,47 MCH_HDVREF
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
C5T2
1UF
2
0.1UF
10 MCH_HCCVREF
10 MCH_HAVREF
C4E5
0.1UF
C5T8
C4E6
1UF
0.1UF
2
1
1
10,18 HUB_PD[10:0]
A
10,18
10,18
10
10
10,47
HUB_PSTRB
HUB_PSTRB#
HUB_HLZCOMP
MCH_PSWING
MCH_HLVREF
J28
C27
E22
D18
K27
D26
E21
E18
J25
E25
B25
G19
HDSTBN0#
HDSTBN1#
HDSTBN2#
HDSTBN3#
HDSTBP0#
HDSTBP1#
HDSTBP2#
HDSTBP3#
DINV0#
DINV1#
DINV2#
DINV3#
F15
CPURST#
K21
J21
J17
Y28
Y22
HDVREF0
HDVREF1
HDVREF2
HCCVREF
HAVREF
U7
U4
U3
V3
W2
W6
V6
W7
T3
V5
V4
W3
V2
T2
U2
W1
C6T1
C6T2
0.1UF
0.1UF
B
HI_0
HI_1
HI_2
HI_3
HI_4
HI_5
HI_6
HI_7
HI_8
HI_9
HI_10
HLSTB
HLSTB#
HLRCOMP
PSWING
HLVREF
K22
H27
K25
L24
J27
G28
L27
L23
L25
J24
H25
K23
G27
K26
J23
H26
F25
F26
B27
H23
E27
G25
F28
D27
G24
C28
B26
G22
C26
E26
G23
B28
B21
G21
C24
C23
D22
C25
E24
D24
G20
E23
B22
B23
F23
F21
C20
C21
G18
E19
E20
G17
D20
F19
C19
C17
F17
B19
G16
E16
C16
E17
D16
C18
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS0#
RS1#
RS2#
L28
M25
N24
M28
N28
N27
P27
M23
N25
P28
M26
N23
P26
M27
Board Default
Optional Override
J7B1
PSB Voltage Select
Shunt for 1.2V
No shunt for 1.05V
J7B3
DVO/AGP Strap
No shunt for DVO
Shunt for AGP
GMCH Frequency Strapping
J7B6 J7B5
0
0
0
0
1
0
1
0
0
1
0
1
1*
1*
1
1
SM
Freq
267
200
200
267
267
267
333
333
GFX Freq
Range
133 - 200
100 - 200
100 - 133
133 - 267
133 - 200
133 - 267
167 - 267
167 - 250
4
0 = No Shunt, 1 = Shunt
7,9,48
5,6,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V1.5S_GMCH_AGP
+V3.3S
1K
1K
1K
1K
1K
3
15,16,17,18,20,23,24,25,27,34,35,39,40,44,47
+V5S
STRAP_CTLB
C6B6
U7B2
6,7,16 LCLKCTLB
7,15 AGP_DETECT
7,15 AGP_ST0
7,15 AGP_ST1
7,15 AGP_ST2
3
4
7
8
11
1A1
1A2
1A3
1A4
1A5
14
17
18
21
22
2A1
2A2
2A3
2A4
2A5
1
13
7,10,18,33 PCI_RST#
1OE#
2OE#
0.1UF
VCC
24
1B1
1B2
1B3
1B4
1B5
2
5
6
9
10
2B1
2B2
2B3
2B4
2B5
15
16
19
20
23
STRAP_J_ST0 1
GND
12
STRAP_J_ST2 1
J7B1
STRAP_J_CTLB
1
STRAP_J_PAR
2
J7B3
1
2
J7B4
2
J7B5
STRAP_J_ST1 1
2
J7B6
2
SN74CBTD3384
2
10K R6C10
STRAP_OE2#
J6E1 Default: pins
2-3. For EV work
jumper pins 1-2
J6E1
48
EPOT_VW0
1
2
LVDS_LIBG 7
3
EPOT_DEFAULT R6E7
1.5K_1%
1
Title
Size
A
Date:
C
PSB
Freq
400
400
400
400
533
533
533
400
* Default
H_ADS# 3
H_TRDY# 3
H_DRDY# 3
H_DEFER# 3
H_HITM# 3
H_HIT#
3
H_LOCK# 3
H_BR0#
3
H_BNR# 3
H_BPRI# 3
H_DBSY# 3
H_RS#0
3
H_RS#1
3
H_RS#2
3
852GME
J7B4
0
1
0
1
0
1
0*
1
R7C2
10K
HD0#
HD1#
HD2#
HD3#
HD4#
HD5#
HD6#
HD7#
HD8#
HD9#
HD10#
HD11#
HD12#
HD13#
HD14#
HD15#
HD16#
HD17#
HD18#
HD19#
HD20#
HD21#
HD22#
HD23#
HD24#
HD25#
HD26#
HD27#
HD28#
HD29#
HD30#
HD31#
HD32#
HD33#
HD34#
HD35#
HD36#
HD37#
HD38#
HD39#
HD40#
HD41#
HD42#
HD43#
HD44#
HD45#
HD46#
HD47#
HD48#
HD49#
HD50#
HD51#
HD52#
HD53#
HD54#
HD55#
HD56#
HD57#
HD58#
HD59#
HD60#
HD61#
HD62#
HD63#
Function
R7C1
J5D1
HA3#
HA4#
HA5#
HA6#
HA7#
HA8#
HA9#
HA10#
HA11#
HA12#
HA13#
HA14#
HA15#
HA16#
HA17#
HA18#
HA19#
HA20#
HA21#
HA22#
HA23#
HA24#
HA25#
HA26#
HA27#
HA28#
HA29#
HA30#
HA31#
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
R7B3
R5C10
4
P23
T25
T28
R27
U23
U24
R24
U28
V28
U27
T27
V27
U25
V26
Y24
V25
V23
W25
Y25
AA27
W24
W23
W27
Y27
AA28
W28
AB27
Y26
AB28
HOST
+V3.3S
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
HUB I/F
External Thermal Sensor Header
5,6,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
GMCH Strapping Options
H_D#[63:0]
U5E1A
H_A#[31:3]
E
STRAP_PAR
STRAP_ST0
STRAP_ST1
STRAP_ST2
3
3
D
R7B5
B
R7B4
A
GMCH (2 of 3)
Document Number
Project:
Friday, May 21, 2004
D
Sheet
8
Rev
of
E
46
B
2
1
VSS
3
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
VSS35
VSS36
VSS37
VSS38
VSS39
VSS40
VSS41
VSS42
VSS43
VSS44
VSS45
VSS46
VSS47
VSS48
VSS49
VSS50
VSS51
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
AJ26 VSS181
T9 VSS180
L6 VSS179
E28 VSS178
D28 VSS177
C22 VSS176
AJ20 VSS174
AJ18 VSS173
AJ12 VSS172
AJ10 VSS171
AA29 VSS170
W29 VSS169
4
C1
G1
L1
U1
AA1
AE1
R2
AG3
AJ3
D4
G4
K4
N4
T4
W4
AA4
AC4
AE4
B5
U5
Y5
Y6
AG6
C7
E7
G7
J7
M7
R7
AA7
AE7
AJ7
H8
K8
P8
T8
V8
Y8
AC8
E9
L9
N9
R9
U9
W9
AB9
AG9
C10
J10
AA10
AE10
D11
F11
H11
AB11
AC11
AJ11
J12
AA12
AG12
A13
D13
F13
H13
N13
R13
U13
AB13
AE13
J14
P14
T14
AA14
AC14
D15
H15
N15
R15
U15
AB15
AG15
F16
J16
P16
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
VSS102
VSS103
VSS105
VSS106
VSS107
VSS108
VSS109
VSS110
VSS111
VSS112
VSS113
VSS114
VSS115
VSS116
VSS117
VSS118
VSS119
VSS120
VSS121
VSS122
VSS123
VSS124
VSS125
VSS126
VSS127
VSS128
VSS129
VSS130
VSS131
VSS132
VSS133
VSS134
VSS135
VSS136
VSS137
VSS138
VSS139
VSS140
VSS141
VSS142
VSS143
VSS144
VSS145
VSS146
VSS147
VSS148
VSS149
VSS150
VSS151
VSS152
VSS153
VSS154
VSS155
VSS156
VSS157
VSS158
VSS159
VSS160
VSS161
VSS162
VSS163
VSS164
VSS165
VSS166
VSS167
VSS168
42,47
T16
AA16
AE16
A17
D17
H17
N17
R17
U17
AB17
AC17
F18
J18
AA18
AG18
A19
D19
H19
AB19
AE19
F20
J20
AA20
AC20
A21
D21
H21
M21
P21
T21
V21
Y21
AA21
AB21
AG21
B24
F22
J22
L22
N22
R22
U22
W22
AE22
A23
D23
AA23
AC23
AJ23
F24
H24
K24
M24
P24
T24
V24
AA24
AG24
A25
D25
AA25
AE25
G26
J26
L26
N26
R26
U26
W26
AB26
A27
F27
AC27
AG27
AJ27
AC28
AE28
C29
E29
G29
J29
L29
N29
U29
C
+V1.5S_GMCH
1
48
2
J6D1
R6D1
D
3,4,5,10,18,20,40,41,47,48
C5T4
C5T12
C5T7
C5T10
C6D3
C6E2
0.1UF
0.1UF
U5E1D
10UF
0.1UF
+V1.5S_GMCH_CORE
10
NO_STUFF_0.01_1%
R6T11
0.1UF
150uF
150uF
+V1.5S_GMCH_HUB
C6E10
C6E9
C5T9
48 +V1.5S_GMCH_CORE
10UF
0.1UF
0.1UF
C4D2
0.1UF
C6E11
0.1UF
+V1.5S_GMCH_DPLLA_D
L5D1
R5R1
1
2
0.10uH 10%
1
+V1.5S_GMCH_DPLLA
C5D5
C5D15
220uF
0.1UF
+V1.5S_GMCH_DPLLB_D
L5D2
R5D1
1
2
0.10uH 10%
1
+V1.5S_GMCH_DPLLB
C5D7
C5D20
220uF
0.1UF
15,19,20,44,47,48 +V1.5S
7,8,48
R6T1
+V1.5S_GMCH_AGP
0.01_1%
C6E7 C6E4
C5T6 C6E5
10UF 150uF
0.1UF 0.1UF
+V1.5S_GMCH_ADAC 17
R5R2
0.01_1%
ADAC_D
R5R7
R5R4
0
C5D3
Layout note: Route
VSSADAC trace to cap
(no via at GMCH).
NO_STUFF_220uF
11,12,43
C5D16
0.1UF 0.01UF
+V1.5S_GMCH_ALVDS
0.01_1%
Layout note: Route
VSSALVDS trace to cap
(no via at GMCH).
R5R3
C5D9
C5D11 C5D18
0.1UF 0.01UF
+V1.5S_GMCH_DLVDS
0.01_1%
+C5D6
C5D2
C5D19
47uF
22UF
0.1UF
+V2.5
47
R5R5
+V2.5_GMCH_TXLVDS
0.01_1%
+
C5D4
C5D1
C5R3 C5D17 C5D10
47uF
22UF
0.1UF 0.1UF 0.1UF
J15
P13
T13
N14
R14
U14
P15
T15
AA15
N16
R16
U16
P17
T17
AA17
AA19
W21
H14
VCC0
VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
VCC8
VCC9
VCC10
VCC11
VCC12
VCC13
VCC14
VCC15
VCC16
VCC17
V1
Y1
W5
U6
U8
W8
V7
V9
VCCHL0
VCCHL1
VCCHL2
VCCHL3
VCCHL4
VCCHL5
VCCHL6
VCCHL7
D29
Y2
VCCAHPLL
VCCAGPLL
A6
B16
VCCADPLLA
VCCADPLLB
E1
J1
N1
E4
J4
M4
E6
H7
J8
L8
M8
N8
R8
K9
M9
P9
VCCAGP/DVO0
VCCAGP/DVO1
VCCAGP/DVO2
VCCAGP/DVO3
VCCAGP/DVO4
VCCAGP/DVO5
VCCAGP/DVO6
VCCAGP/DVO7
VCCAGP/DVO8
VCCAGP/DVO9
VCCAGP/DVO10
VCCAGP/DVO11
VCCAGP/DVO12
VCCAGP/DVO13
VCCAGP/DVO14
VCCAGP/DVO15
A9
B9
B8
VCCADAC0
VCCADAC1
VSSADAC
A11
B11
VCCALVDS
VSSALVDS
G13
B14
J13
B15
VCCDLVDS0
VCCDLVDS1
VCCDLVDS2
VCCDLVDS3
F9
B10
D10
A12
VCCTXLVDS0
VCCTXLVDS1
VCCTXLVDS2
VCCTXLVDS3
A3
A4
VCCGPIO_0
VCCGPIO_1
VTTLF0
VTTLF1
VTTLF2
VTTLF3
VTTLF4
VTTLF5
VTTLF6
VTTLF7
VTTLF8
VTTLF9
VTTLF10
VTTLF11
VTTLF12
VTTLF13
VTTLF14
VTTLF15
VTTLF16
VTTLF17
VTTLF18
VTTLF19
VTTLF20
G15
H16
H18
J19
H20
L21
N21
R21
U21
H22
M22
P22
T22
V22
Y29
K29
F29
AB29
A26
A20
A18
VTTHF0
VTTHF1
VTTHF2
VTTHF3
VTTHF4
A22
A24
H29
M29
V29
VCCSM0
VCCSM1
VCCSM2
VCCSM3
VCCSM4
VCCSM5
VCCSM6
VCCSM7
VCCSM8
VCCSM9
VCCSM10
VCCSM11
VCCSM12
VCCSM13
VCCSM14
VCCSM15
VCCSM16
VCCSM17
VCCSM18
VCCSM19
VCCSM20
VCCSM21
VCCSM22
VCCSM23
VCCSM24
VCCSM25
VCCSM26
VCCSM27
VCCSM28
VCCSM29
VCCSM30
VCCSM31
VCCSM32
VCCSM33
VCCSM34
VCCSM35
VCCSM36
AC1
AG1
AB3
AF3
Y4
AJ5
AA6
AB6
AF6
Y7
AA8
AB8
Y9
AF9
AJ9
AB10
AA11
AB12
AF12
AA13
AJ13
AB14
AF15
AB16
AJ17
AB18
AF18
AB20
AF21
AJ21
AB22
AF24
AJ25
AF27
AC29
AF29
AG29
VCCQSM0
VCCQSM1
AJ6
AJ8
VCCASM0
VCCASM1
AD1
AF1
852GME
Resistor provided for
power measurement
(plane underneath
resistor will have to
be cut).
R4R1
NO_STUFF_0.01_1%
4
C5T3
C5T5 C5R1
+ C4D1
0.1UF
0.1UF 10UF
270uF
Place these caps
on the top side
C5D12
MCH_PWR_VTTHF0
MCH_PWR_VTTHF1
MCH_PWR_VTTHF2
MCH_PWR_VTTHF3
MCH_PWR_VTTHF4
0.1uF
C5D13 0.1uF
C4E1 0.1uF
C4E3
0.1uF
0.1uF
C4E4
3
11,12,43
+V2.5_GMCH_SM
+V2.5
R4U1
0.01_1%
1
2
J4F1
C5F1 C5T14 C5T13 C5F3
0.1UF 0.1UF 0.1UF 0.1UF
C5T11 C5F8 C5T15
C5F4 C5F9 C5F7 C5T16
0.1UF 0.1UF 0.1UF
0.1UF 0.1UF 0.1UF 0.1UF
C5F12
C5F11
150uF
150uF
10,43,48 +V2.5_GMCH_SM
2
L5F1
+V2.5_GMCH_QSM
C5F10
C5F2
4.7UF
0.1UF
0.68uH
10%
R5F5
QSM_R
1
+V1.5S_GMCH_ASM 1
C6E14
48
L6F1
+V1.5S_GMCH_CORE
2
1uH 20%
+
0.1UF
C6E13
100uF
1
5,6,8,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
48
R5R6
+V3.3S_GMCH_GPIO
0.01_1%
Title
C5D8 C5D14
852GME
10UF 0.1UF
A
+VCC_IMVP
C6D6
NO_STUFF_0.01_1%
48
E
+V1.5S_GMCH_CORE
POWER
A
U5E1C
B
C
Size
A
Date:
GMCH (3 of 3)
Document Number
Project:
Friday, May 21, 2004
D
Sheet
Rev
of
9
E
46
A
B
C
GMCH-GT Compensation & Reference Voltages
3,4,5,9,18,20,40,41,47,48
+VCC_IMVP
3,4,5,9,18,20,40,41,47,48
D
E
LAI Hub Interface
8,18 HUB_PD[10:0]
J6U1
NO_STUFF_HUBLINK
+VCC_IMVP
Host
R5R9
301_1%
R4T1
301_1%
R5R10
4
8,47 MCH_HXSWING
HUB_PD0
R4E2
8,47 MCH_HYSWING
150_1%
HUB_PD2
150_1%
+VCC_IMVP
LAI_HUB_PIN10
R6F12
LAI_HUB_PIN18
392_1%
R5D2
R5T2
49.9_1%
R5T1
1
8 MCH_HXRCOMP
2
R6F10
8,18 HUB_PSTRB#
27.4_1%
100_1%
HUB_PD6
R4E1
1
8 MCH_HYRCOMP
HUB_PD7
2
3,4,5,9,18,20,40,41,47,48
R6F16
392_1%
LAI_HUB_PIN34
LAI_HUB_PIN38
R6F21
392_1%
27.4_1%
+VCC_IMVP
LAI_HUB_PIN26
392_1%
8,47 MCH_HDVREF
3,4,5,9,18,20,40,41,47,48
392_1%
LAI_HUB_PIN6
R6F1
392_1%
HUB_PD4
3,4,5,9,18,20,40,41,47,48
R6E8
+VCC_IMVP
3
R4T2
49.9_1%
R4E4
8 MCH_HCCVREF
R5T4
49.9_1%
R5T5
8 MCH_HAVREF
100_1%
Digital Video Port
100_1%
DAC
R6D6
7 MCH_GRCOMP
System Memory
+V1.5S_GMCH_HUB
9,43,48
9
+V2.5_GMCH_SM
+V1.5S_GMCH_HUB
R6T4
86.6_1%
R6T2
R5F3
150_1%
R6T3
8 HUB_HLZCOMP
48.7_1%
8 MCH_PSWING
R5F1
100_1%
7 MCH_SMVSWINGH
9,43,48
9
604 1%
+V2.5_GMCH_SM
+V1.5S_GMCH_HUB
R5F4
604
1%
No Stuff
C6T3
NO_STUFF_470PF
MCH_GTLREF2
150_1%
9,43,48
A
392_1%
LAI_HUB_PIN11
HUB_PD1
R6F5
392_1%
R6F11
392_1%
R6F13
392_1%
LAI_HUB_PIN19
LAI_HUB_PIN23
4
HUB_PD3
CLK_HUBLAI 6
HUB_PSTRB 8,18
R6F17
392_1%
LAI_HUB_PIN31
HUB_PD5
LAI_HUB_PIN35
PCI_RST# 7,8,18,33
R6F18
392_1%
R6F22
392_1%
LAI_HUB_PIN47
HUB_PD9
3
R6F25
392_1%
HUB_PD10
LAI_HUB_PIN59
R6G1
392_1%
LAI_HUB_PIN71
HUB_PD8
Layout Note: The following signals should
have 10 mil spacing and must be routed 20
mil from any other trace.
2
Manufacturing Support
MCH_HXSWING
MCH_HYSWING
MCH_HDVREF
MCH_HXRCOMP
MCH_HYRCOMP
MCH_HCCVREF
MCH_HLVREF
MCH_SMVSWINGL
MCH_SMRCOMP
MCH_SMVSWINGH
HUB_HLZCOMP
MCH_PSWING
DAC_REFSET
MCH_GRCOMP
MCH_HAVREF
J4D1
ANCHOR_CLIP_GHOST
J6D2
ANCHOR_CLIP_GHOST
J4F2
ANCHOR_CLIP_GHOST
J6F1
ANCHOR_CLIP_GHOST
+V2.5_GMCH_SM
R6T10
1
C6T5
R6T12
100_1%
C6T4
MCH_GTLREF3
NO_STUFF_0
R6F4
LAI_HUB_PIN7
ASSEMBLY_LABEL
8,47 MCH_HLVREF
R6T8
R5F2
7 MCH_SMVSWINGL
R6T7
324_1%
R6T6
NO_STUFF_56.2_1%
1
MCH_HLVREF
127 1%
9
Hub Interface
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
R5R8
7 DAC_REFSET
40.2_1%
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
0.1UF
60.4_1%
7 MCH_SMRCOMP
60.4_1%
NO_STUFF_0.01UF
B
C
Title
R6T9
Size
A
Date:
GMCH Circuitry
Project:
Document Number
Friday, May 21, 2004
D
Sheet
10
Rev
of
E
46
A
B
C
D
E
5,6,8,9,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
12
R4W1
+V3.3S_SPD
0.01_1%
Power plane for Serial Presence Detect logic
12,13,14 M_DATA_R_[63:0]
4
13
M_AA_FR_0
7,14 M_AA[2:1]
13
M_AA_FR_3
7,14 M_AA[5:4]
13 M_AA_FR_[12:6]
13 M_BS0_FR#
13 M_BS1_FR#
12,13,14 M_CB_R[7:0]
3
7
7
7
7
7
7
7,12,14
7,12,14
13
13
13
7,12,14
7,12,14
M_AA_FR_0
M_AA1
M_AA2
M_AA_FR_3
M_AA4
M_AA5
M_AA_FR_6
M_AA_FR_7
M_AA_FR_8
M_AA_FR_9
M_AA_FR_10
M_AA_FR_11
M_AA_FR_12
M_CB_R0
M_CB_R1
M_CB_R2
M_CB_R3
M_CB_R4
M_CB_R5
M_CB_R6
M_CB_R7
M_CLK_DDR0
M_CLK_DDR0#
M_CLK_DDR1#
M_CLK_DDR1
M_CLK_DDR2
M_CLK_DDR2#
M_CKE0
M_CKE1
M_CAS_FR#
M_RAS_FR#
M_WE_FR#
M_CS0#
M_CS1#
6,8,12,16,18,39 SMB_CLK_S
6,8,12,16,18,39 SMB_DATA_S
12,13,14 M_DM_R_[8:0]
2
12,13,14 M_DQS_R[8:0]
M_DM_R_0
M_DM_R_1
M_DM_R_2
M_DM_R_3
M_DM_R_4
M_DM_R_5
M_DM_R_6
M_DM_R_7
M_DM_R_8
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7
M_DQS_R8
J6H1A
CON200_DDR-SODIMM
112
111
110
109
108
107
106
105
102
101
115
100
99
97
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12
A13(DU)
117
116
98
71
73
79
83
72
74
80
84
35
37
158
160
89
91
96
95
120
118
119
121
122
194
196
198
195
193
86
BA0
BA1
BA2(DU)
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
CK0
CK0#
CK1#
CK1
CK2
CK2#
CKE0
CKE1
CAS#
RAS#
WE#
S0#
S1#
SA0
SA1
SA2
SCL
SDA
RESET(DU)
12
26
48
62
134
148
170
184
78
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
DM8
11
25
47
61
133
147
169
183
77
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
5
7
13
17
6
8
14
18
19
23
29
31
20
24
30
32
41
43
49
53
42
44
50
54
55
59
65
67
56
60
66
68
127
129
135
139
128
130
136
140
141
145
151
153
142
146
152
154
163
165
171
175
164
166
172
176
177
181
187
189
178
182
188
190
4
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_38
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
12,43,47,48
12
+V2.5_DDR
9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192
+V3.3S_SPD
J6H1B CON200_DDR-SODIMM
VDD1
VSS1 3
VDD2
VSS2 15
VDD3
VSS3 27
VDD4
VSS4 39
VDD5
VSS5 51
VDD6
VSS6 63
VDD7
VSS7 75
VDD8
VSS8 87
VDD9
VSS9 103
VDD10
VSS10 125
VDD11
VSS11 137
VDD12
VSS12 149
VDD13
VSS13 159
VDD14
VSS14 161
VDD15
VSS15 173
VDD16
VSS16 185
VDD17
VSS17 4
VDD18
VSS18 16
VDD19
VSS19 28
VDD20
VSS20 38
VDD21
VSS21 40
VDD22
VSS22 52
VDD23
VSS23 64
VDD24
VSS24 76
VDD25
VSS25 88
VDD26
VSS26 90
VDD27
VSS27 104
VDD28
VSS28 126
VDD29
VSS29 138
VDD30
VSS30 150
VDD31
VSS31 162
VDD32
VSS32 174
VDD33
VSS33 186
199
197
1
2
12,43 SM_VREF_DIMM
C6V2
0.1UF
VDDID
VDDSPD
VREF1
VREF2
DU1
DU2
DU3
DU4
GND0
GND1
3
85
123
124
200
201
202
SO-DIMM_RSVD_FR
2
+V2.5_DDR
9,12,43
12,43,47,48
+V2.5
R4F1
0.01_1%
C4G1
150uF
C4G2
150uF
C6W2
0.1UF
C4W2
0.1UF
C4W3
0.1UF
C6W8
0.1UF
C5W3
0.1UF
C5W5
0.1UF
C5W4
0.1UF
C5W6
0.1UF
Layout note: Place capacitors between and near DDR connector if possible
SO-DIMM 0
1
1
Title
Size
A
Date:
A
B
C
DDR SO-DIMMs (1 of 2)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
11
E
46
A
B
C
D
E
11,13,14 M_DATA_R_[63:0]
M_AA0
M_AB1
M_AB2
7,13,14 M_AA0
4
7,14 M_AB[2:1]
M_AA3
M_AB4
M_AB5
M_AA6
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
M_AA12
7,13,14 M_AA3
7,14 M_AB[5:4]
7,13,14 M_AA[12:6]
7,11,14
7,13,14
7,13,14
11,13,14
M_CS0#
M_BS0#
M_BS1#
M_CB_R[7:0]
M_CB_R0
M_CB_R1
M_CB_R2
M_CB_R3
M_CB_R4
M_CB_R5
M_CB_R6
M_CB_R7
M_CKE0, M_CKE1, M_CS0#, M_CS1#
are only for LAI support.
3
11
+V3.3S_SPD
7
7
7
7
7
7
7,14
7,14
7,13,14
7,13,14
7,13,14
7,14
7,14
M_CLK_DDR3
M_CLK_DDR3#
M_CLK_DDR4#
M_CLK_DDR4
M_CLK_DDR5
M_CLK_DDR5#
M_CKE2
M_CKE3
M_CAS#
M_RAS#
M_WE#
M_CS2#
M_CS3#
6,8,11,16,18,39 SMB_CLK_S
6,8,11,16,18,39 SMB_DATA_S
7,11,14 M_CKE0
11,13,14 M_DM_R_[8:0]
2
11,13,14 M_DQS_R[8:0]
112
111
110
109
108
107
106
105
102
101
115
100
99
97
117
116
98
71
73
79
83
72
74
80
84
35
37
158
160
89
91
96
95
120
118
119
121
122
194
196
198
195
193
86
M_DM_R_0
M_DM_R_1
M_DM_R_2
M_DM_R_3
M_DM_R_4
M_DM_R_5
M_DM_R_6
M_DM_R_7
M_DM_R_8
12
26
48
62
134
148
170
184
78
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_DQS_R5
M_DQS_R6
M_DQS_R7
M_DQS_R8
11
25
47
61
133
147
169
183
77
J6H2ACON200_DDR-SODIMM_REV
DQ0 5
A0
DQ1 7
A1
DQ2 13
A2
DQ3 17
A3
DQ4 6
A4
DQ5 8
A5
DQ6 14
A6
DQ7 18
A7
DQ8 19
A8
DQ9 23
A9
DQ10 29
A10/AP
DQ11 31
A11
DQ12 20
A12
DQ13 24
A13(DU)
DQ14 30
DQ15 32
BA0
DQ16 41
BA1
DQ17 43
BA2(DU)
DQ18 49
CB0
DQ19 53
CB1
DQ20 42
CB2
DQ21 44
CB3
DQ22 50
CB4
DQ23 54
CB5
DQ24 55
CB6
DQ25 59
CB7
DQ26 65
CK0
DQ27 67
CK0#
DQ28 56
CK1#
DQ29 60
CK1
DQ30 66
CK2
DQ31 68
CK2#
DQ32 127
CKE0
DQ33 129
CKE1
DQ34 135
CAS#
DQ35 139
RAS#
DQ36 128
WE#
DQ37 130
S0#
DQ38 136
S1#
DQ39 140
SA0
DQ40 141
SA1
DQ41 145
SA2
DQ42 151
SCL
DQ43 153
SDA
DQ44 142
RESET(DU)
DQ45 146
DQ46 152
DM0
DQ47 154
DM1
DQ48 163
DM2
DQ49 165
DM3
DQ50 171
DM4
DQ51 175
DM5
DQ52 164
DM6
DQ53 166
DM7
DQ54 172
DM8
DQ55 176
DQ56 177
DQS0
DQ57 181
DQS1
DQ58 187
DQS2
DQ59 189
DQS3
DQ60 178
DQS4
DQ61 182
DQS5
DQ62 188
DQS6
DQ63 190
DQS7
M_DATA_R_0
M_DATA_R_1
M_DATA_R_2
M_DATA_R_3
M_DATA_R_4
M_DATA_R_5
M_DATA_R_6
M_DATA_R_7
M_DATA_R_8
M_DATA_R_9
M_DATA_R_10
M_DATA_R_11
M_DATA_R_12
M_DATA_R_13
M_DATA_R_14
M_DATA_R_15
M_DATA_R_16
M_DATA_R_17
M_DATA_R_18
M_DATA_R_19
M_DATA_R_20
M_DATA_R_21
M_DATA_R_22
M_DATA_R_23
M_DATA_R_24
M_DATA_R_25
M_DATA_R_26
M_DATA_R_27
M_DATA_R_28
M_DATA_R_29
M_DATA_R_30
M_DATA_R_31
11
M_DATA_R_32
M_DATA_R_33
M_DATA_R_34
M_DATA_R_35
M_DATA_R_36
M_DATA_R_37
M_DATA_R_3811,43 SM_VREF_DIMM
M_DATA_R_39
M_DATA_R_40
M_DATA_R_41
M_DATA_R_42
M_DATA_R_43
M_DATA_R_44
M_DATA_R_45
M_DATA_R_46
M_DATA_R_47
M_DATA_R_48
M_DATA_R_49
M_DATA_R_50
M_DATA_R_51
M_DATA_R_52
M_DATA_R_53
M_DATA_R_54
M_DATA_R_55
M_DATA_R_56
M_DATA_R_57
M_DATA_R_58
M_DATA_R_59
M_DATA_R_60
M_DATA_R_61
M_DATA_R_62
M_DATA_R_63
11,43,47,48
+V2.5_DDR
+V3.3S_SPD
C6W6
0.1UF
+V2.5_DDR
9
21
33
45
57
69
81
93
113
131
143
155
157
167
179
191
10
22
34
36
46
58
70
82
92
94
114
132
144
156
168
180
192
199
197
1
2
J6H2B CON200_DDR-SODIMM_REV
VSS1 3
VDD1
VSS2 15
VDD2
VSS3 27
VDD3
VSS4 39
VDD4
VSS5 51
VDD5
VSS6 63
VDD6
VSS7 75
VDD7
VSS8 87
VDD8
VSS9 103
VDD9
VSS10 125
VDD10
VSS11 137
VDD11
VSS12 149
VDD12
VSS13 159
VDD13
VSS14 161
VDD14
VSS15 173
VDD15
VSS16 185
VDD16
VSS17 4
VDD17
VSS18 16
VDD18
VSS19 28
VDD19
VSS20 38
VDD20
VSS21 40
VDD21
VSS22 52
VDD22
VSS23 64
VDD23
VSS24 76
VDD24
VSS25 88
VDD25
VSS26 90
VDD26
VSS27 104
VDD27
VSS28 126
VDD28
VSS29 138
VDD29
VSS30 150
VDD30
VSS31 162
VDD31
VSS32 174
VDD32
VSS33 186
VDD33
VDDID
VDDSPD
VREF1
VREF2
4
3
85
123
124
200
201
202
DU1
DU2
DU3
DU4
GND0
GND1
M_CKE1 7,11,14
SO-DIMM_RSVD
M_CS1# 7,11,14
9,11,43
11,43,47,48
+V2.5
2
R4V1
C6H2
150uF
C6G2
150uF
C5V2
0.1UF
C4V1
0.1UF
C4W1
0.1UF
C5V3
0.1UF
C6V1
0.1UF
C5V1
0.1UF
C5W1
0.1UF
C5W2
0.1UF
0.01_1%
C6W1
0.1UF
DQS8
SO-DIMM 1
Layout note: Place capacitors between and near DDR connector if possible
SO-DIMM1 is placed further from GMCH
than SO-DIMM0
1
1
Title
Size
A
Date:
A
B
C
DDR SO-DIMMs (2 of 2)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
12
E
46
A
B
C
D
E
M_DATA_R_[63:0] 11,12,14
4
3
M_DATA_R_0
M_DATA32
4 RP5G11D
5 10
M_DATA_R_32
3 RP6G3C 6 10
M_DATA_R_1
M_DATA33
3 RP5G11C
6 10
M_DATA_R_33
1 RP6G3A 8 10
M_DATA_R_2
M_DATA34
1 RP5G11A8 10
M_DATA_R_34
4 RP6G4D 5 10
M_DATA_R_3
M_DATA35
4 RP4G5D 5 10
4 RP6G1D 5 10
M_DATA_R_4
M_DATA36
8 RP5G6A 1 10
M_DATA5
3 RP6G1C 6 10
M_DATA_R_5
M_DATA37
7 RP5G6B 2 10
M_DATA6
1 RP6G1A 8 10
M_DATA_R_6
M_DATA38
M_DATA7
4 RP6G2D 5 10
M_DATA_R_7
M_DATA39
M_DATA8
3 RP6G4C 6 10
M_DATA_R_8
M_DATA9
2 RP6G4B 7 10
M_DATA10
M_DATA0
4 RP6G3D 5 10
M_DATA1
M_DATA2
M_DATA3
M_DATA4
7,12,14 M_AA[12:6]
M_AA_FR_[12:6] 11
M_AA12
7 RP5G14B2 10
M_AA_FR_12
M_DATA_R_35
M_AA11
6 RP5G14C
3 10
M_AA_FR_11
M_DATA_R_36
M_AA10
6 RP5G1C 3 10
M_AA_FR_10
M_DATA_R_37
M_AA9
8 RP5G14A1 10
M_AA_FR_9
5 RP5G6D 4 10
M_DATA_R_38
M_AA8
5 RP5G14D
4 10
M_AA_FR_8
4 RP4G3D 5 10
M_DATA_R_39
M_AA7
8 RP5G7A 1 10
M_AA_FR_7
M_DATA40
3 RP4G5C 6 10
M_DATA_R_40
M_AA6
7 RP5G7B 2 10
M_AA_FR_6
M_DATA_R_9
M_DATA41
2 RP4G5B 7 10
M_DATA_R_41
7,12,14 M_AA3
M_AA3
5 RP5G7D 4 10
M_AA_FR_3
1 RP5G12A8 10
M_DATA_R_10
M_DATA42
4 RP4G6D 5 10
M_DATA_R_42
7,12,14 M_AA0
M_AA0
7 RP5G1B 2 10
M_AA_FR_0
M_DATA11
2 RP5G12B7 10
M_DATA_R_11
M_DATA43
3 RP4G6C 6 10
M_DATA_R_43
M_DATA12
3 RP6G2C 6 10
M_DATA_R_12
M_DATA44
3 RP4G3C 6 10
M_DATA_R_44
M_DATA13
2 RP6G2B 7 10
M_DATA_R_13
M_DATA45
2 RP4G3B 7 10
M_DATA_R_45
M_DATA14
4 RP5G2D 5 10
M_DATA_R_14
M_DATA46
4 RP4G4D 5 10
M_DATA_R_46
M_DATA15
3 RP5G2C 6 10
M_DATA_R_15
M_DATA47
3 RP4G4C 6 10
M_DATA_R_47
M_DATA16
3 RP5G12C
6 10
M_DATA_R_16
M_DATA48
2 RP4G6B 7 10
M_DATA_R_48
M_DATA17
4 RP5G12D
5 10
M_DATA_R_17
M_DATA49
1 RP4G6A 8 10
M_DATA_R_49
M_CB6
4 RP5G5D 5 10
M_CB_R6
M_DATA18
3 RP5G9C 6 10
M_DATA_R_18
M_DATA50
3 RP4G7C 6 10
M_DATA_R_50
M_CB5
2 RP5G5B 7 10
M_CB_R5
M_DATA19
2 RP5G9B 7 10
M_DATA_R_19
M_DATA51
2 RP4G7B 7 10
M_DATA_R_51
M_CB4
1 RP5G5A 8 10
M_CB_R4
M_DATA20
2 RP5G2B 7 10
M_DATA_R_20
M_DATA52
2 RP4G4B 7 10
M_DATA_R_52
M_CB3
M_DATA21
1 RP5G2A 8 10
M_DATA_R_21
M_DATA53
1 RP4G4A 8 10
M_DATA_R_53
M_CB2
4 RP5G13D
5 10
M_CB_R2
M_DATA22
3 RP5G3C 6 10
M_DATA_R_22
M_DATA54
3 RP4G1C 6 10
M_DATA_R_54
M_CB1
2 RP5G13B7 10
M_CB_R1
M_DATA23
2 RP5G3B 7 10
M_DATA_R_23
M_DATA55
2 RP4G1B 7 10
M_DATA_R_55
M_CB0
1 RP5G13A8 10
M_CB_R0
M_DATA24
1 RP5G9A 8 10
M_DATA_R_24
M_DATA56
1 RP4G7A 8 10
M_DATA_R_56
M_DATA25
4 RP5G10D
5 10
M_DATA_R_25
M_DATA57
4 RP4G8D 5 10
M_DATA_R_57
M_DATA26
2 RP5G10B7 10
M_DATA_R_26
M_DATA58
2 RP4G8B 7 10
M_DATA_R_58
1 RP5G10A8 10
M_DATA_R_27
1 RP4G8A 8 10
M_DATA_R_59
1 RP5G3A 8 10
M_DATA_R_28
1 RP4G1A 8 10
M_DATA_R_60
8 RP5G4A 1 10
M_DATA_R_29
4 RP4G2D 5 10
M_DATA_R_61
6 RP5G4C 3 10
M_DATA_R_30
2 RP4G2B 7 10
M_DATA_R_62
5 RP5G4D 4 10
M_DATA_R_31
1 RP4G2A 8 10
M_DATA_R_63
M_DATA27
M_DATA28
M_DATA29
M_DATA30
2
M_DATA31
M_DATA59
M_DATA60
M_DATA61
M_DATA62
M_DATA63
7 M_CB[7:0]
M_CB7
R5G1
R5G2
10
10
4
M_AA_FR_3 11
M_AA_FR_0 11
M_CB_R7
3
M_CB_R3
M_CB_R[7:0] 11,12,14
7 M_DQS[8:0]
7 M_DATA[63:0]
M_DQS8
3 RP5G13C
6 10
M_DQS_R8
M_DQS7
6 RP4G8C 3 10
M_DQS_R7
M_DQS6
5 RP4G7D 4 10
M_DQS_R6
M_DQS5
8 RP4G5A 1 10
M_DQS_R5
M_DQS4
2 RP5G11B7 10
M_DQS_R4
M_DQS3
3 RP5G10C
6 10
M_DQS_R3
M_DQS2
5 RP5G9D 4 10
M_DQS_R2
M_DQS1
8 RP6G4A 1 10
M_DQS_R1
M_DQS0
7 RP6G3B 2 10
M_DQS_R0
2
M_DQS_R[8:0] 11,12,14
7 M_DM[8:0]
7,12,14 M_BS0#
5 RP5G1D 4 10
7,12,14 M_BS1#
8 RP5G1A 1 10
7,12,14 M_CAS#
8 RP5G8A 1 10
7,12,14 M_RAS#
5 RP5G8D 4 10
7,12,14 M_WE#
7 RP5G8B 2 10
1
M_BS0_FR# 11
M_BS1_FR# 11
M_CAS_FR# 11
M_RAS_FR# 11
M_WE_FR# 11
M_DM0
2 RP6G1B 7 10
M_DM_R_0
M_DM1
8 RP6G2A 1 10
M_DM_R_1
M_DM2
5 RP5G3D 4 10
M_DM_R_2
M_DM3
7 RP5G4B 2 10
M_DM_R_3
M_DM4
3 RP5G6C 6 10
M_DM_R_4
M_DM5
1 RP4G3A 8 10
M_DM_R_5
M_DM6
5 RP4G1D 4 10
M_DM_R_6
M_DM7
6 RP4G2C 3 10
M_DM_R_7
M_DM8
3 RP5G5C 6 10
M_DM_R_8
1
M_DM_R_[8:0] 11,12,14
Title
DDR Series Termination
Size
Project:
Custom
Date:
Friday, May 21, 2004
A
B
C
D
Document Number
Sheet
Rev
of
13
E
46
1
A
B
56
C5W15
0.1UF
C5W26
0.1UF
C5H2
0.01UF
C6H4
0.01UF
C4H4
0.1UF
C4W9
0.01UF
C5W10
0.01UF
C4W13
0.01UF
C5W31
0.1UF
C6W9
0.1UF
C4W12
0.1UF
C5W33
0.01UF
C5W22
0.01UF
C5W37
0.1UF
C5W36
0.01UF
C5W25
0.01UF
C5H1
0.1UF
C6W11
0.1UF
C6W10
0.01UF
C5W39
0.1UF
C5W20
0.01UF
C5W35
0.1UF
C5W13
0.1UF
C5W24
0.01UF
C4W14
0.1UF
C5W38
0.01UF
C5W30
0.01UF
C4W15
0.01UF
C4W11
0.01UF
C5W18
0.01UF
C6W12
0.1UF
C5W23
0.1UF
C4W8
0.1UF
C4H2
0.1UF
C5W27
0.01UF
C5W9
0.1UF
C5W17
0.1UF
C4W7
0.01UF
C5W12
0.01UF
C5W34
0.01UF
C4W5
0.01UF
C5W32
0.01UF
C5W16
0.01UF
C4W4
0.1UF
C6H3
0.1UF
C6H5
0.1UF
C5W8
0.1UF
C5W7
0.1UF
C
7,12
7,12
M_CKE3
M_CKE2
7,12,13
7,12,13
+V1.25S
Title
Size
A
Date:
56
56
D
56
56
56
Project:
Friday, May 21, 2004
56
56
56
M_CS2#
M_CS3#
R5H8
7,12
7,12
M_DQS_R5
M_DQS_R6
3 RP5H3C 6
56
2 RP5H3B 7
56
1 RP5H1A 8
56
3 RP5H5C 6
56
8 RP5H14A 1
56
6 RP5H14C 3
56
2 RP5H5B 7
56
2 RP5J1B 7
56
RP5H1D5
4
56
RP5J1C6
3
56
RP5J1D5
4
56
7 RP5H14B 2
56
1 RP5H5A 8
56
R5H9
56
R4H6
56
R4H5
56
R4H2
56
8
8
2
7
1
4 RP5H8D
56
3 RP5H8C
56
2 RP5H8B
56
1 RP5H8A
56
1 RP5H12A
56
2 RP5H12B
56
3 RP5H12C
56
4 RP5H12D
56
7,12
7,12
7,12
7,12
Sheet
14
E
M_CB_R2
M_CB_R0
6
5
7,11,12 M_CKE0
7,11,12 M_CKE1
M_CB_R1
8
D
7
M_CB_R4
M_CB_R3
M_CB_R5
7
7,12,13 M_AA3
8
M_CB_R7
M_CB_R6
5
M_DQS_R0
M_DQS_R1
M_DQS_R2
M_DQS_R3
M_DQS_R4
M_AA0
M_AA1
M_AA2
M_AA3
M_AA4
M_AA5
M_AA6
6
4 RP5H13D 5
56
5 RP5H3D 4
56
R5W1
56
R5H5
56
R5H4
56
R5H2
56
R5H1
56
R6H5
56
R6H4
56
5
4
1
3
3
2
4
M_DATA_R_[63:0]
M_DQS_R7
M_DQS_R8
M_AA7
M_AA8
M_AA9
M_AA10
M_AA11
5 RP5H4D
56
7 RP5H4B
56
6 RP5H1C
56
6 RP5H4C
56
8 RP5H4A
56
5 RP5H5D
56
4 RP5H14D
56
C
M_DM_R_8
43,47,48
R4H7
C4W16
0.1UF
R4H4
C5W14
0.01UF
M_DM_R_7
C5W28
0.1UF
M_DM_R_6
C4H3
0.01UF
R4H3
C4W6
0.1UF
M_DM_R_5
C4W10
0.1UF
R5H10
C5W11
0.1UF
M_DM_R_4
C5W21
0.1UF
R5H7
C5W19
0.1UF
M_DM_R_3
+V1.25S
R5H6
Layout note: Place one cap close to every 2 pullup resistors terminated to +V1.25.
M_DM_R_2
C6W14
0.1UF
3
M_AA[5:4]
R6H8
C5W29
0.01UF
6 RP5H13C
56
8 RP5H13A
56
2 RP5H1B
56
7 RP5H13B
56
1 RP5H3A
56
1 RP5J1A
56
5 M_DATA_R_0
6 M_DATA_R_1
7 M_DATA_R_2
8 M_DATA_R_3
8 M_DATA_R_4
7 M_DATA_R_5
6 M_DATA_R_6
5 M_DATA_R_7
1 M_DATA_R_8
2 M_DATA_R_9
3 M_DATA_R_10
4 M_DATA_R_11
4 M_DATA_R_12
3 M_DATA_R_13
2 M_DATA_R_14
1 M_DATA_R_15
5 M_DATA_R_16
6 M_DATA_R_17
7 M_DATA_R_18
8 M_DATA_R_19
8 M_DATA_R_20
7 M_DATA_R_21
6 M_DATA_R_22
5 M_DATA_R_23
5 M_DATA_R_24
6 M_DATA_R_25
7 M_DATA_R_26
8 M_DATA_R_27
8 M_DATA_R_28
7 M_DATA_R_29
6 M_DATA_R_30
5 M_DATA_R_31
M_AA[2:1]
M_DM_R_1
C6W13
0.01UF
M_AA12
8
4 RP5H7D
56
3 RP5H7C
56
2 RP5H7B
56
1 RP5H7A
56
1 RP5H11A
56
2 RP5H11B
56
3 RP5H11C
56
4 RP5H11D
56
4 RP5H6D
56
3 RP5H6C
56
2 RP5H6B
56
1 RP5H6A
56
1 RP5H10A
56
2 RP5H10B
56
3 RP5H10C
56
4 RP5H10D
56
8 RP5H2A
56
7 RP5H2B
56
6 RP5H2C
56
5 RP5H2D
56
5 RP6J1D
56
6 RP6J1C
56
7 RP6J1B
56
8 RP6J1A
56
4 RP6H1D
56
3 RP6H1C
56
2 RP6H1B
56
1 RP6H1A
56
1 RP6H2A
56
2 RP6H2B
56
3 RP6H2C
56
4 RP6H2D
56
7,11
7
6
5
1
2
3
4
8
7
6
5
5
6
7
8
8
7
6
5
5
6
7
8
8
7
6
5
5
6
7
8
7,11
R6H7
2
B
M_DM_R_0
3
M_DATA_R_63 1 RP4H3A
56
M_DATA_R_622 RP4H3B
56
M_DATA_R_613 RP4H3C
56
M_DATA_R_604 RP4H3D
56
M_DATA_R_594 RP4J3D
56
M_DATA_R_583 RP4J3C
56
M_DATA_R_572 RP4J3B
56
M_DATA_R_561 RP4J3A
56
M_DATA_R_551 RP4H2A
56
M_DATA_R_542 RP4H2B
56
M_DATA_R_533 RP4H2C
56
M_DATA_R_524 RP4H2D
56
M_DATA_R_514 RP4J2D
56
M_DATA_R_503 RP4J2C
56
M_DATA_R_492 RP4J2B
56
M_DATA_R_481 RP4J2A
56
M_DATA_R_471 RP4H1A
56
M_DATA_R_462 RP4H1B
56
M_DATA_R_453 RP4H1C
56
M_DATA_R_444 RP4H1D
56
M_DATA_R_434 RP4J1D
56
M_DATA_R_423 RP4J1C
56
M_DATA_R_412 RP4J1B
56
M_DATA_R_401 RP4J1A
56
M_DATA_R_395 RP5H9D
56
M_DATA_R_386 RP5H9C
56
M_DATA_R_377 RP5H9B
56
M_DATA_R_368 RP5H9A
56
M_DATA_R_354 RP5J2D
56
M_DATA_R_343 RP5J2C
56
M_DATA_R_332 RP5J2B
56
M_DATA_R_321 RP5J2A
56
A
7,12,13 M_AA0
E
43,47,48
of
+V1.25S
7,11,12 M_CS0#
7,11,12 M_CS1#
M_CB_R[7:0] 11,12,13
7,12,13 M_AA[12:6]
4
M_DQS_R[8:0]
4
Document Number
46
3
11,12,13 M_DATA_R_[63:0]
11,12,13 M_DQS_R[8:0]
7,12,13 M_AA[12:6]
M_BS0#
M_BS1#
7,12,13 M_WE#
2
7,12,13 M_RAS#
7,12,13 M_CAS#
M_AB5
M_AB4
M_AB2
M_AB1
11,12,13 M_DM_R_[8:0]
1
DDR Parallel Termination
Rev
B
C
5,19,20,21,22,23,27,28,29,32,36,37,38,39,44,48
B48
B50
PERR#
SERR#
B46
DEVSEL#
AGP_REQ#
B8
7 AGP_FRAME#
A41
7
7 AGP_GNT#
2
7
AGP_IRDY#
22,23,32,37 PCI_GATED_RST#
A8
RST#
AGP_TRDY#
AGP_RBF#
AGP_WBF#
B12
A14
7
AGP_STOP#
18,21,23,24 INT_PIRQB#
18,21,23,24 INT_PIRQA#
A2
RBF#
WBF#
TYPEDET#
STOP#
B6
A6
INTB#
INTA#
B1
1
TRDY#
A47
7,8 AGP_DETECT
A50
7,8 AGP_ST0
7,8 AGP_ST1
7,8 AGP_ST2
B10
A10
B11
OVRCNT#
PAR
ST0
ST1
ST2
AGP_PIPE#
A12
PIPE#
18,22,23,37 PCI_PME#
A48
PME#
A4
B4
USBUSB+
7
VDDQ1.5_1
VDDQ1.5_2
VDDQ1.5_3
VDDQ1.5_4
VDDQ1.5_5
VDDQ1.5_6
VDDQ1.5_7
VDDQ1.5_8
VDDQ1.5_9
B34
B40
B47
B58
B64
A34
A40
A58
A64
Vrefcg
Vrefgc
B66
A66
SBA0
SBA1
SBA2
SBA3
SBA4
SBA5
SBA6
SBA7
C/BE0#
C/BE1#
C/BE2#
C/BE3#
+V3.3S_AGP
4
R6C14
100K
AGP_TYPEDET#
R6E2 2.2k
AGP_TRDY# 1
2
R6E1 2.2k
AGP_STOP# 1
2
+V3.3S_AGP
9,19,20,44,47,48 +V1.5S
R7F4
8.2K
J7F2
+V1.5S_AGP
R6D3
1K_1%
AGP_VREF 7,47
19,37 PM_C3_STAT#
19,32,34,37 PM_SUS_STAT#
AGP_SBA[7:0] 7
C7T1
3
6Pin_HDR
R6D5
1K_1%
0.1UF
Place C7T1 near
ADD slot
AGP_CBE#0
AGP_CBE#1
AGP_CBE#2
AGP_CBE#3
Mobile Sideband
Header For Validation
only
1
2
3
4
5
6
7,19 AGP_BUSY#
8,16,17,18,20,23,24,25,27,34,35,39,40,44,47
+V5S_AGP
R7C4
7
7
7
7
+V5S
0.01_1%
C7C4
C7C6
C7C7
22UF
0.1UF
0.1UF
+V1.5S
9,19,20,44,47,48
J7F1
+V1.5S_AGP
C6E3
NO_STUFF_150uF
NO_STUFF_150uF
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
B14
B22
A3
A11
A22
A24
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
B5
B13
B19
B23
B31
B37
B49
B55
B61
A5
A13
A19
A23
A31
A37
A49
A55
A61
R7U1
C7E8 +
C6D5
100uF
C7D5
22UF
C7E5
0.1UF
18,19,20,23,27,30,32,35,37,38,39,43,44
C7E6
0.1UF
C6E6
0.1UF
B
C7D4
0.1UF
C6D4
0.1UF
C6E8
0.1UF
+V1.5
1
20
2
C6E12
0.1UF
2
3
0.01_1%
CON3_HDR
+V3.3
+VDC
16,21,44
+VDC
R6P3
100K
D3 hot and D3 on Support
Jumper D3cold
(default)
J6C2
1-2
J7F1
1-2
D3hot
1-X
1-2
U6P1
D3on
16,21,44
SI4420DY
1-X
2-3
R6P2
100K
J6C2
4
AGP_D3H_EN 1
2 AGP_D3H_EN_J
C6C7
0.1UF
1
R6P4
C7D3
C6C9
22UF
22UF
+ C7C8
100uF
C6C8
C6D2
C6D1
0.1UF
0.1UF
0.1UF
Title
C
Q6P1
BSS138
Q6P2
BSS138
1
PM_SLP_S3# 19,25,32,37,38,
1
0.002_1%
+V3.3S_AGP
Size
A
Date:
A
AGP_PIPE# 7
AGP_PIPE#
R7D1 2.2k
AGP_IRDY# 1
2
B15AGP_SBA0
A15AGP_SBA1
B17AGP_SBA2
A17AGP_SBA3
B20AGP_SBA4
A20AGP_SBA5
B21AGP_SBA6
A21AGP_SBA7
A57
B51
B39
A33
3
17,23,27,37,38,44 +V12S
R6D4 2.2k
AGP_FRAME# 1
2
0.1UF
GNT#
A7
7
7
B52
A52
2
AGP_PIPE#_FET
FRAME#
IRDY#
7
VDDQ1
VDDQ2
2
REQ#
B41
A46
AGP_TYPEDET#
CLK
B9
B16
B25
B28
A9
A16
A25
A28
R7E1 2.2k
AGP_DEVSEL# 1
2
C6C6
3
19,37 PM_SUS_CLK
3
7 AGP_DEVSEL#
B7
VCC3.3_1
VCC3.3_2
VCC3.3_3
VCC3.3_4
VCC3.3_5
VCC3.3_6
VCC3.3_7
VCC3.3_8
R6E4 2.2k
AGP_AD15 1
2
2
8.2K
AD_STB1#
AD_STB1
AD_STB0#
AD_STB0
SB_STB#
SB_STB
+V5S_AGP
B24
B3
B217,23,27,37,38,44 +V12S
A1
PM_SLP_S3
8.2K
6 CLK_AGP_SLOT
ADD_PERR#
ADD_SERR#
A32
B32
A59
B59
A18
B18
3.3Vaux
5.0V2
5.0V1
12V
3
R7E4 R7E2
7 AGP_STB#1
7 AGP_STB1
7 AGP_ADSTB#0
7 AGP_ADSTB0
7 AGP_SBSTB#
7 AGP_SBSTB
ADD 124
Q6C4
BSS138
2
+V1.5S_AGP
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
Q6C2
BSS138
8
7
6
5
3
A65
B65
A63
B63
A62
B62
A60
B60
B57
A56
B56
A54
B54
A53
B53
A51
A39
B38
A38
B36
A36
B35
A35
B33
A30
B30
A29
B29
A27
B27
A26
B26
9,19,20,44,47,48 +V1.5S
3
2
1
4
AGP_AD0
AGP_AD1
AGP_AD2
AGP_AD3
AGP_AD4
AGP_AD5
AGP_AD6
AGP_AD7
AGP_AD8
AGP_AD9
AGP_AD10
AGP_AD11
AGP_AD12
AGP_AD13
AGP_AD14
AGP_AD15
AGP_AD16
AGP_AD17
AGP_AD18
AGP_AD19
AGP_AD20
AGP_AD21
AGP_AD22
AGP_AD23
AGP_AD24
AGP_AD25
AGP_AD26
AGP_AD27
AGP_AD28
AGP_AD29
AGP_AD30
AGP_AD31
E
1
J6C1
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
+V3.3ALWAYS
D
1
A
AGP/ADD (AGP Digital Display) Conn
Project:
Document Number
Friday, May 21, 2004
D
Sheet
15
Rev
of
E
46
A
B
C
+V3.3S
D
5,6,8,9,11,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S_LVDSDDC
LVDS Interface
R5N4
100K
C5N1
C5B7
C5B9
1000PF
0.1UF
22UF
LVDS_VDDEN_D#
Q5B1
7 LVDS_YAM1
7 LVDS_YAP1
1
7 LVDS_YAM2
7 LVDS_YAP2
NO_STUFF_BSS138
7 LVDS_CLKAM
7 LVDS_CLKAP
R5B4
7 LVDS_YBM0
7 LVDS_YBP0
NO_STUFF_100
2
R5N2
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
7 LVDS_DDCPCLK
7 LVDS_DDCPDATA
7 LVDS_YAM0
7 LVDS_YAP0
Q5B2
BSS138
1
7 LVDS_VDDEN
J6B1
2.2k
2
+V3.3S_LVDS_PANEL
2
3 LVDS_VDDEN#
100K
3
3
R5N3
R6N4
2.2k
2
Q5B3
2
SI2307DS
0.01_1%
R6N3
1
R5N5
1
5,6,8,9,11,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
+V3.3S_LVDS
4
0.01_1%
1
R6N5
+V3.3S
E
100K
7 LVDS_YBM1
7 LVDS_YBP1
3
7 LVDS_YBM2
7 LVDS_YBP2
7 LVDS_CLKBM
7 LVDS_CLKBP
4
Test points for 24bpp support
R6C2
NO_STUFF_0
7 LVDS_YAM3
7 LVDS_YAP3
R6C1
NO_STUFF_0
7 LVDS_YBM3
7 LVDS_YBP3
3
LVDS,CONN30
BIOS Note: Disable both
BKLTSEL lines before
enabling one.
LVDS Panel Backlight
+V3.3S
5,6,8,9,11,18,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
8,15,17,18,20,23,24,25,27,34,35,39,40,44,47
+VDC
15,21,44
+V5S
+V5S
8,15,17,18,20,23,24,25,27,34,35,39,40,44,47
2
U5B2
34 LVDS_BKLTSEL0
7 LVDS_BKLTCTL
R5B3
1
2
3
4
OE1#
1A
1B
GND
8,15,17,18,20,23,24,25,27,34,35,39,40,44,47
+V5S
8
7
6
5
VCC
OE2#
2B
2A
C5B6
R5N6
0.1UF
0.01_1%
R5P5
74CBT3306
0.01_1%
NO_STUFF_0.01_1%
R5P4 NO STUFF
NO_STUFF_0.01_1%
Option to power
backlight with
5.0V
2
+V3.3S_LVDSBKLT +VCC_LVDSBKLT
LVDS_BKLTSEL1 34
R5B2
SMB_DATA_D
R5P3
0
SMB_DATA_S 6,8,11,12,18,39
J5C1
100K
R5B1
NO_STUFF_0
LCLKCTLB 6,7,8
1
2
3
4
5
6
7
No Stuff
LVDS_BRIGHTNESS
7 LVDS_BKLTEN
6,8,11,12,18,39 SMB_CLK_S
6,7
LCLKCTLA
R5C2
R5P1
R5P2
0
SMB_CLK_D
NO_STUFF_0
No Stuff
INVERTER CONN
100K
1
1
Title
Size
A
Date:
A
B
C
LVDS
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
16
E
46
A
B
C
C6R2
C6R1
E
+V5S_F_DAC
C6R3
F3A1
0.1UF
R4A1
100K
+1
CR4M6
4
1
2
4
I/O1
I/O2
I/O3
I/O6
I/O5
I/O4
1N4148
8
6
5
4.7K
Q4M1
1
DDC_GATE
DAC_RED
DAC_GREEN
DAC_BLUE
OE1#
1A
1B
GND
VCC
OE2#
2B
2A
FB3A7
50OHM
2
1
1
R4M1
2.2k
100
DDC_OE2#
DAC_QA_DDCADATA
2
7,24 DAC_DDCACLK
R3M1
2.2k
0.1UF
R4N1
8
7
6
5
2
3
1
2
3
4
C4N1
DDC_VCC
Vn
U4B1
DDC_OE1#
100
4
1
R4M2
DDC_SRC
R3N1
2
1.1A
2
R3A6
1K
3
0.1UF
1
0.1UF
ESD DIODE ARRAY
3
Vp
CR6D1
D
15,23,27,37,38,44 +V12S
8,15,16,18,20,23,24,25,27,34,35,39,40,44,47 +V5S
+V1.5S_GMCH_ADAC
7
9
74CBT3306
7,24 DAC_DDCADATA
DAC_QA_DDCACLK
DAC_Q_VSYNC
R3A4
39
DAC_Q_HSYNC
R3A2
39
C4A4
C4A3
NO_STUFF_3.3pF
NO_STUFF_3.3pF
C3A3
33pF
C3A6
33pF
3
+V5S_L_DAC
Layout Note:
Place 75 ohm resistors near connector.
Use 37.5 ohm traces from GMCH to 75
ohm resistors.
3
DAC_L_VSYNC
DAC_L_HSYNC
C6B1
DOCK_QPCIEN#_J
NO_STUFF_3.3pF
DAC_Q_RED
1
U6B2
+V5S
C6N3
0.1UF
IN
SOURCE1 NO
6
2
V+
COM
5
DAC_RED 7
3
GND
SOURCE2 NC
4
DOCK_RED 25
DAC_L_RED
2
DAC_Q_GREEN
1
FB3A2
DAC_L_GREEN
2
75Ohm@100MHz
DAC_Q_BLUE
SPDT
1
FB3A3
DAC_L_BLUE
2
75Ohm@100MHz
C6B3
R3A1
C3A2
R3A3
C3A5
R3A5
C3A8
C3A1
C3A4
C3A7
75_1%
3.3pF
75_1%
3.3pF
75_1%
3.3pF
3.3pF
3.3pF
3.3pF
CONN,MISC,49P,D-SUB,3-IN-1
J2A1C
40
35
41
36
42
37
43
38
44
39
75Ohm@100MHz
DAC_Q_RED
1
FB3A1
45
46
47
48
49
NO_STUFF_3.3pF
2
2
U6B4
C6N2
0.1UF
IN
SOURCE1 NO
6
2
V+
COM
5
DAC_BLUE 7
3
GND
SOURCE2 NC
4
DOCK_BLUE 25
8,15,16,18,20,23,24,25,27,34,35,39,40,44,47
8,15,16,18,20,23,24,25,27,34,35,39,40,44,47
SPDT
U6B6
J3H1 Docking VGA Enable:
Default setting stuffed.
R3H4
J3H1
C6B2
C6N1
0.1UF
IN
SOURCE1 NO
6
2
V+
COM
5
SOURCE2 NC
4
3
GND
SPDT
DAC_Q_GREEN
DAC_GREEN 7
DOCK_GREEN 25
2
33K
13
DOCK_QPCIEN#_J
U3H1F
74HC14
12
7 DAC_VSYNC
DAC_Q_VSYNC
DAC_QPCIEN
DOCK_QPCIEN#_J
R6B1
DOCK_HSYNC
39
25
7 DAC_HSYNC
DAC_Q_HSYNC
NO_STUFF_3.3pF
C7B3
DAC_QPCIEN
DOCK_Q_VSYNC
0.1UF
DAC_VSYNC
7
+V5S
1
2
3
4
OE1#
1A
2Y
GND
VCC
OE2#
1Y
2A
8
7
6
5
0.1UF
DAC_QPCIEN
DOCK_Q_HSYNC
DAC_HSYNC
7
SN74LVC2G125
DOCK_VSYNC
39
NO_STUFF_3.3pF
C6N6
Title
C6B5
C
1
25
Size
A
Date:
B
8
7
6
5
C6N4
R6N1
A
C6N5
VCC
OE2#
1Y
2A
U6B5
DOCK_QPCIEN#_J
NO_STUFF_3.3pF
NO_STUFF_3.3pF
OE1#
1A
2Y
GND
SN74LVC2G125
8,15,16,18,20,23,24,25,27,34,35,39,40,44,47
C6B4
1
1
2
3
4
7
1
DOCK_Q_VSYNC
DOCK_Q_HSYNC
U6B3
+V5S
1
24,25 DOCK_QPCIEN#
NO_STUFF_3.3pF
+V5S
+V5S
14
+V5S
DAC_Q_BLUE
1
DAC (CRT) Connector
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
17
E
46
C
D
3,4,5,9,10,20,40,41,47,48
3
2
ICH4-M
PCI
I/F
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
TP_GNT0#
22
22
23
24
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
C1
E6
A7
B7
D6
PCI_GNT0#
PCI_GNT1#
PCI_GNT2#
PCI_GNT3#
PCI_GNT4#
21
21,22
21,22
21,23
21,24
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
B1
A2
B3
C7
B6
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_REQ3#
PCI_REQ4#
CLK_ICHPCI
PCI_DEVSEL#
PCI_FRAME#
PCI_REQA#
PCI_REQB#
PCI_GNTA#
PCI_GNTB#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI_PME#
P5
M3
F1
B5
A6
E8
C5
L5
G1
L4
M2
W2
U5
K5
F3
F2
PCI_CLK
PCI_DEVSEL#
PCI_FRAME#
PCI_GPIO0/REQA#
PCI_GPIO1/REQB_L/REQ5#
PCI_GPIO16/GNTA#
PCI_GPIO17/GNTB_L/GNT5#
PCI_IRDY#
PCI_PAR
PCI_PERR#
PCI_LOCK#
PCI_PME#
PCI_RST#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
6
21,22,23,24
21,22,23,24
22,23
24
19,22,23
24
21,22,23,24
22,23,24
21,22,23
21,22,23,24
15,22,23,37
21,22,23,24 PCI_SERR#
21,22,23,24 PCI_STOP#
21,22,23,24 PCI_TRDY#
PCI_C/BE0#
PCI_C/BE1#
PCI_C/BE2#
PCI_C/BE3#
Interrupt
I/F
22,23,24
22,23,24
22,23,24
22,23,24
J2
K4
M4
N4
Y22
AB23
U23
AA21
W21
V22
AB22
V21
Y23
U22
U21
W23
V23
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PD11
HUB_CLK
L19
L20
M19
M21
P19
R19
T20
R20
P23
L22
N22
K21
T21
HUB_PSTRB#
HUB_PSTRB
HUB_RCOMP
HUB_VREF
HUB_VSWING
N20
P21
R23
M23
R22
Hub
I/F
CPU I/F
PART A
CPU_A20GATE
CPU_A20M#
CPU_DPSLP#
CPU_FERR#
CPU_IGNNE#
CPU_INIT#
CPU_INTR
CPU_NMI
CPU_PWRGOOD
CPU_RCIN#
CPU_SLP#
CPU_SMI#
CPU_STPCLK#
INT_APICCLK
INT_APICD0
INT_APICD1
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#/GPIO2
INT_PIRQF#/GPIO3
INT_PIRQG#/GPIO4
INT_PIRQH#/GPIO5
INT_IRQ14
INT_IRQ15
INT_SERIRQ
SM_INTRUDER# 21,37
SMB_CLK
SMB_DATA
CPU_SLP#
CPU_SMI#
CPU_STPCLK#
56
0
0
0
0
R6H12
R6H1
56
H_INTR 3,37
H_NMI 3,37
H_PWRGD 4,37
H_RCIN# 32,37
H_CPUSLP# 3,37
H_SMI# 3,37
H_STPCLK# 3,37
0
0
0
HUB_PD[10:0]
HUB_PD0
HUB_PD1
HUB_PD2
HUB_PD3
HUB_PD4
HUB_PD5
HUB_PD6
HUB_PD7
HUB_PD8
HUB_PD9
HUB_PD10
HUB_PD11
H_A20M# 3
H_DPSLP# 3,7,37
H_FERR# 3
H_IGNNE# 3
0
0
0
R6W14
R6H10
R6W15
8,10
NO_STUFF_0
PSMI#
47
20
+V1.5S_ICHHUB
PLACE RCOMP resistor
within 0.5" of ICH pad using
a thick trace
R6H3
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD0
LAN_TXD1
LAN_TXD2
LAN_JCLK
LAN_RSTSYNC
LAN_RST#
A10
A9
A11
B10
C10
A12
C11
B11
Y5
1
2
3
4
EEP_DIN
0
H_INIT#
3,37
20
+V1.5S_ICHHUB
The pad of R6H10
needs to be overlap
with R6H12
HUB_VREF_ICH
R6W9
C6W4
20
R6W12
130_1%
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
INT_PIRQE#
INT_PIRQF#
INT_PIRQG#
INT_PIRQH#
15,21,23,24
15,21,23,24
21,23,24
21,23,24
21,22,23
21,22,23
21,22,23
21,22,23,37
C6W7
C6W5
R6W13
0.01UF
0.1UF
150_1%
+V3.3_ICHLAN
U7G1
CS VCC
SK
DC
DI ORG
DO GND
8
7
6
5
2
C7G1
TP_EEP_DC
TP_EEP_ORG
HUB INTERFACE LAYOUT:
Route signals with 4/8 trace/space routing. Signals
must match +/- 0.1" of HUB_STB/STB# signals
8,15,16,17,20,23,24,25,27,34,35,39,40,44,47
+V5S
U6G1
21,22,23,24,47 SMB_CLK
6,8,11,12,16,39 SMB_CLK_S
U8G2
1
2
3
4
OE1#
1A
1B
GND
VCC
OE2#
2B
2A
8
7
6
5
0.1UF
SMB_S_OE2#
SMB_DATA_S 6,8,11,12,16,39
SMB_DATA 21,22,23,24,47
74CBT3306
R6G4
R6G2
100
R6W2
10K
R6W8
10K
This Bus Switch prevents
leakage of the SMBus into
devices powered on the
switched rail.
C6F3
SMB_S_OE1#
INT_APICCLK
INT_APICD0
INT_APICD1
HUB INTERFACE VSWING VOLTAGE
0.1UF
100
5
3
0.1UF
150_1%
C8G3
0.1UF
R6W10
487_1%
47
0.01UF
AT88SC153
LAN_RXD0 30
LAN_RXD1 30
EEPROM for ICH4-M LAN
LAN_RXD2 30
(Atmel AT93C66-10PC-2.7)
LAN_TXD0 30
LAN_TXD1 30
EEP_DOUT 19
LAN_TXD2 30
LAN_JCLK 30
LAN_RST 30
PM_LANPWROK 30,32
R9Y1
R6W5
0
1
1
BUF_PCI_RST#
4
A
Title
74AHC1G08 2
3
22,23,24,26,31,32,34,37
4
R6J1
C6W3
7,8,10,33 PCI_RST#
1
CR8G2A
3904
5
300
+V1.5S_ICHHUB
EEP_CS
EEP_SK
10K
4
HUB_PSTRB# 8,10
HUB_PSTRB 8,10
HUB_RCOMP_ICH
HUB_VREF_ICH
HUB_VSWING_ICH
J19
H19
K20
D5
C2
B4
A3
R7F11
0
C8 INT_PIRQE#_D
R7F10
0
D7 INT_PIRQF#_D
R7F3
0
C3 INT_PIRQG#_D
INT_PIRQH#_D
R7G3
0
C4
AC13
INT_IRQ14 21,26,37 20
AA19
INT_IRQ15 21,26,37
J22
INT_SERIRQ 22,23,24,32,34,37
D10
D11
A8
C12
15,19,20,23,27,30,32,35,37,38,39,43,44
H_INIT#_D
FWH_INIT# 31
1
48.7_1%
ICH4-M
+V3.3
R6H14
INT_APICCLK
INT_APICD0
INT_APICD1
EEP_CS
EEP_DIN
EEP_DOUT
EEP_SHCLK
6
CR8G2B
3904
2
3
RCOMP R should be 2/3
board impedance
CLK_ICH66 6
R8G9
300
R8G8
2K
R6W19
SMB_ALERT# 21,37
H_A20GATE 36
CPU_A20M#
R6W21
CPU_DPSLP#
R6H15
CPU_FERR#
R6W18
CPU_IGNNE#
R6W16
CPU_INIT#
CPU_INTR
R6W17
CPU_NMI
R6H13
CPU_PWRGOOD
R6W20
+V3.3S
1
W6
AC3
AB1
AC4
AB4
AA5
E
5,6,8,9,11,16,20,21,23,26,31,33,34,35,36,38,39,40,41,44,48
H_INIT#_DQ
2
SM_INTRUDER#
SMLINK0
SMLINK1
SMB_CLK
SMB_DATA
SMB_ALERT#/GPIO11
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
EEPROM
I/F
4
H5
J3
H3
K1
G5
J4
H4
J5
K2
G2
L1
G4
L2
H2
L3
F5
F4
N1
E5
N2
E3
N3
E4
M5
E2
P1
E1
P2
D3
R1
D2
P4
LAN
I/F
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
System
Management
I/F
U7G2A
22,23,24 PCI_AD[31:0]
+VCC_IMVP
SMB_DATA
B
SMB_CLK
A
Size
A
Date:
Buffer to reduce loading on PCI_RST#
B
C
ICH4-M (1 of 3)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
18
E
46
74AHC1G08
2
3
24,37 +V3.3S_ICH
4
R6V2
NO_STUFF_1K
AC_SPKR
R7V6 NO_STUFF_10K
AC_SDATAOUT
R7V7 NO_STUFF_1K
PCI_GNTA# 18,22,23
R7V8 NO_STUFF_1K
EEP_DOUT 18
Board Default
Optional Override
NO STUFF
STUFF for No Reboot
NO STUFF
STUFF for safe mode
R7V7 A16 swap override
NO STUFF
STUFF for A16 swap override
Reserved
NO STUFF
STUFF
R7V6
R7V8
Safe Mode Boot
31,32,33,34,37
31,32,33,34,37
31,32,33,34,37
31,32,33,34,37
+V3.3ALWAYS
37
20,21
CR2G1
34
1
LPC_DRQ#0
2
SIO_DRQ#0
74AHC1G08
4
3
3
1
+V_RTC
U8G1
5
RTC Circuitry
4,48
27 AC_BITCLK
27 AC_RST#
27 AC_SDATAIN0
27 AC_SDATAIN1
27 AC_SDATAIN2
27 AC_SDATAOUT
27 AC_SYNC
5,15,20,21,22,23,27,28,29,32,36,37,38,39,44,48
+V3.3ALWAYS
0.1UF C8G1
3
BAT54
C7Y2
1UF
CMOS Settings J2J3
Clear CMOS SHUNT
Keep CMOS OPEN
CR2F1
1
2
J21
Y20
V19
3
RTC_RST#
delay
18-25ms
R2J5
180K
BAT54
2
V_RTCBATT_D
C2J2
J2J3
33
T2
R4
T4
U2
U3
U4
T5
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
ICH_DRQ#0
37 LPC_DRQ#1
31,32,33,34,37 LPC_FRAME#
28
28
28
29
29
USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
28
28
28
29
29
USB_PN0
USB_PN1
USB_PN2
USB_PN3
USB_PN4
28
28
28
Layout: Route
29
USB_RBIAS/RBIAS# 29
29
Differentially
RTC_RST#
R7V5
B8
C13
D13
A13
B13
D9
ACSYNC_D C9
1
V_RTCBATT
C2F6
0.047UF
1
R7Y1
10M
BT1H1
Battery_Holder
2
USB_RBIAS
USB_RBIAS#
J20
G22
F20
G20
F21
H20
F23
H22
G23
H21
F22
E23
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
0
0
0
0
0
0
0
0
0
0
0
0
1
GPIO32
GPIO33
GPIO34
GPIO35
GPIO36
GPIO37
GPIO38
GPIO39
GPIO40
GPIO41
GPIO42
GPIO43
Y7J1
32.768KHZ
1
1
2
A
R7J2
R8W10
R7W1
R8W11
R7Y2
R9F1
0
0
0
0
0
0
ICH_GPIO7 37
SMC_EXTSMI# 32,34,36,37
SMC_RUNTIME_SCI# 32,36,37
SMC_WAKE_SCI# 32,36,37
AUDIO_PWRDN 27
ICH_MFG_MODE 37
CRB_DET#
Y13
AB14
AB21
AC22
IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2
AA13
AB13
W13
AA20
AC20
AC21
IDE_PDA0
IDE_PDA1
IDE_PDA2
IDE_SDA0
IDE_SDA1
IDE_SDA2
IDE_PDD0
IDE_PDD1
IDE_PDD2
IDE_PDD3
IDE_PDD4
IDE_PDD5
IDE_PDD6
IDE_PDD7
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
26
26
26
26
4
J9F3
1
2
26
26
NO_STUFF_MFG-TEST-JUMPER
26
26
26
26
IDE_PDD[15:0] 26
AB11 IDE_PDD0
AC11 IDE_PDD1
IDE_PDD2
Y10
+V3.3ALWAYS
IDE_PDD3
AA10 5,15,20,21,22,23,27,28,29,32,36,37,38,39,44,48
IDE_PDD4
AA7
R8J17
IDE_PDD5
AB8
IDE_PDD6
Y8
IDE_PDD7
AA8
10K
J8J2
IDE_PDD8
AB9
IDE_PDD9
Y9
1
IDE_PDD10
CRB_DET#_D 2
AC9
IDE_PDD11
W9
3
AB10 IDE_PDD12
CON3_HDR
IDE_PDD13
W10
IDE_PDD14
W11
IDE_PDD15
Y11
IDE_SDD[15:0] 26
IDE_SDD0
W17
CRB/SV Detect
AB17 IDE_SDD1
IDE_SDD2
Default: 2-3 for CRB
W16
AC16 IDE_SDD3
IDE_SDD4
W15
AB15 IDE_SDD5
IDE_SDD6
W14
AA14 IDE_SDD7
IDE_SDD8
Y14
AC15 IDE_SDD9
AA15 IDE_SDD10
IDE_SDD11
Y15
AB16 IDE_SDD12
IDE_SDD13
Y16
AA17 IDE_SDD14
IDE_SDD15
Y17
Y12
AB19
AA11
AB18
AC12
Y18
W12
AA18
AB12
AC19
IDE_PDDACK# 26
IDE_SDDACK# 26
IDE_PDDREQ 26
IDE_SDDREQ 26
IDE_PDIOR# 26
IDE_SDIOR# 26
IDE_PDIOW# 26
IDE_SDIOW# 26
IDE_PIORDY 26
IDE_SIORDY 26
CLK_14
CLK_48
RTCRST#
CLK_RTCX1
CLK_RTCX2
CLK_VBIAS
J23
F19
W7
AC7
AC6
Y6
CLK_ICH14 6
CLK_ICH48 6
SPKR
THRMTRIP#
H23
W20
AC_SPKR 27
PM_THRMTRIP# 3
IDE_PDDACK#
IDE_SDDACK#
IDE_PDDREQ
IDE_SDDREQ
IDE_PDIOR#
IDE_SDIOR#
IDE_PDIOW#
IDE_SDIOW#
IDE_PIORDY
IDE_SIORDY
GPIO
GPIO7
GPIO8
GPIO12
GPIO13
GPIO25
GPIO27
IDE_PDCS1#
IDE_PDCS3#
IDE_SDCS1#
IDE_SDCS3#
IDE_SDD0
IDE_SDD1
IDE_SDD2
IDE_SDD3
IDE_SDD4
IDE_SDD5
IDE_SDD6
IDE_SDD7
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
USB
I/F
R3
V4
V5
W3
V2
W1
W4
2
RTC_RST#
RTC_X1
RTC_X2
RTC_VBIAS
1
1K
PM_SUS_CLK 15,37
Title
2
SUS_CLK
Q8H1
BSS138
1
10pF
B
3
ICH4-M
2
C7J4
GPIO_7
GPIO_8
GPIO_12
GPIO_13
GPIO_25
GPIO_27
GPIO_28
R8H1
R7J1
10M
Cap values depend on Xtal
E
3
C7Y1 10pF
2
1
LPC
I/F
A23
B23
RTC_RST#
RTC_VBIAS
RTC_X1
RTC_X2
2
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_DRQ0#
LPC_DRQ1#
LPC_FRAME#
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
9,15,20,44,47,48 +V1.5S
1
AC'97
I/F
B15
C14
A15
B14
A14
D14
0.1UF
R6W7
37 AGP_SUSPEND#
R6G3
R6V1
33 KSC_VPPEN#
R8W9
35 SER_EN
R6W1
31,37 FWH_WP#
R6W3
31,37 FWH_TBL#
R7F9
22.6_1%
21 ICH_FAB_REV0
R6F26
21 ICH_FAB_REV1
R6F27
21 ICH_FAB_REV2
R6J3
26,37 IDE_PATADET
R6W6
26,37 IDE_SATADET
R6W4
23 PCI_NOGO
R6J6
TP_GPIO43_D
AC_BITCLK
AC_RST#
AC_SDATAIN0
AC_SDATAIN1
AC_SDATAIN2
AC_SDATAOUT
AC_SYNC
USB_PP0
USB_PP1
USB_PP2
USB_PP3
USB_PP4
USB_PP5
USB_PN0#
USB_PN1#
USB_PN2#
USB_PN3#
USB_PN4#
USB_PN5#
USB_RBIAS
R2F8
1K
PM_GMUXSEL/GPIO23
PM_CPUPERF#/GPIO22
PM_VGATE/VRMPWRGD
C20
A21
C18
A19
C16
TP_USB_PP5 A17
D20
B21
D18
B19
D16
TP_USB_PN5 B17
USB_OC0#
USB_OC1#
USB_OC2#
USB_OC3#
USB_OC4#
USB_OC5#
PART B
IST
Function
No Reboot
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
PM_STPCPU#
PM_STPPCI#
SUS_CLK
PM_SUS_STAT#
PM_THRM#
37 PM_GMUXSEL
3,37 PM_CPUPERF#
37,41 DELAYED_VR_PWRGD
ICH4M Strapping Options
R6V2
ICH4-M
IDE
I/F
1
4
6,37,38,44 PM_SLP_S1#
AGP_BUSY#
PM_SYSRST#
PM_BATLOW#
PM_C3_STAT#
PM_CLKRUN#
PM_DPRSLPVR
PM_PWRBTN#
PM_PWROK
PM_RI#
PM_RSMRST#
Clocks
5
U2G1
D
U7G2B
R2 PM_AGPBUSY#/GPIO6
Y3 PM_SYSRST#
AB2 PM_BATLOW#
T3 PM_C3_STAT#/GPIO21
AC2 PM_CLKRUN#/GPIO24
V20 PM_DPRSLPVR
AA1 PM_PWRBTN#
AB6 PM_PWROK
Y1 PM_RI#
AA6 PM_RSMRST#
W18 PM_SLP_S1#/GPIO19
Y4 PM_SLP_S3#
Y2 PM_SLP_S4#
AA2 PM_SLP_S5#
W19 PM_STPCPU#/GPIO20
Y21 PM_STPPCI#/GPIO18
AA4 PM_SUS_CLK
AB3 PM_SUS_STAT#/LPCPD#
V1 PM_THRM#
Power
Management
7,15
44
32,36,37
15,37
SLP_S1#_D
21,22,23,24,32,34,37
37,39,40
PM_SLP_S3#
32,37
21,25,32,37,39
21,35,37
R6H9
21,32,37
1
2SLP_S1#
68 15,25,32,37,38,43,44
20,32,37,38,43,44
37,38
6,37,39,40
6,37
33,37
15,32,34,37
5,21,32,37
C2G11
0.1UF
C
15,18,20,23,27,30,32,35,37,38,39,43,44
Unmuxed
GPIO
B
+V3.3
Misc
A
C
Size
A
Date:
ICH4-M (2 of 3)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
19
E
46
A
B
C
D
U7G2C
R7G4
C7W6
C7W15
C7W18
10UF
0.1UF
0.1UF
NO_STUFF_0.1UF
No Stuff
+V1.5_ICHLAN
4
0.01_1%
+V3.3
R7G5
C8G2
C7W7 C7W8
22UF
0.1UF 0.1UF
15,18,19,23,27,30,32,35,37,38,39,43,44
18
VCCSUS1.5_0
VCCSUS1.5_1
VCCSUS1.5_2
VCCSUS1.5_3
VCCSUS1.5_4
VCCSUS1.5_5
VCCSUS1.5_6
VCCSUS1.5_7
F6
F7
VCCLAN1.5_0
VCCLAN1.5_1
E9
F9
VCCLAN3.3_0
VCCLAN3.3_1
E7
V6
VCC5REF1
VCC5REF2
+V3.3_ICHLAN
VCC5REF
0.01_1%
C7G7
C7W3 C7V3
C7G6
22UF
0.1UF 0.1UF
4.7UF
+V5A_ICH
9,15,19,44,47,48 +V1.5S
18
R6G5
E15
C6H1
C7W14C7W12
22UF
0.1UF 0.1UF
L23
M14
P18
T22
C22
R7V4 VCCPLL
C7V2
C7V1
P14
U18
AA23
0.01UF
R6H6
+V5S
C7W22
1UF
0.1UF
2
18,23,24,25,27,34,35,39,40,44,47
C7W16
19,21,22,24,37 +V3.3S_ICH
5,15,19,21,22,23,27,28,29,32,36,37,38,39,44,48
1
R8G5
1K
CR8G1
BAT54
3
1
2
VCC5REFSUS1
VCCHI_0
VCCHI_1
VCCHI_2
VCCHI_3
VCC1.5_0
VCC1.5_1
VCC1.5_2
VCC1.5_3
VCC1.5_4
VCC1.5_5
VCC1.5_6
VCC1.5_7
K10
K12
K18
K22
P10
T18
U19
V14
VCCRTC
AB5
+V3.3S_ICH
C7J3
C7J2
C7W2 C7W5 C7W10C7W13C7W17C7W9
22UF
22UF
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF
+V1.5S_ICH
21,28,29
+ C7G5
100uF
C7W19
1UF
0.1UF
VCC_CPU_IO_0
VCC_CPU_IO_1
VCC_CPU_IO_2
R7V2
1K
3
C7G2
C7G8
C7W11
C7W20
22UF
0.1UF
0.1UF
9,15,19,44,47,48
0.01_1%
+V_RTC
3
5,15,19,21,22,23,27,28,29,32,36,37,38,39,44,48
+V3.3ALWAYS_ICH
+V3.3ALWAYS
R7G1
C7G4
C7V4 C7W21C7W4
22UF
0.1UF 0.1UF 0.1UF
0.01_1%
+V1.5
15
R8J2
10K
6
5
2
1
U8H2
+V5A_ICH
C8J1
C7G3
1
IN
2
GND
3
0.1UF
OUT
5
POK
4
4
POK
R8J9
10K
2
2
R8J4
20k_1%
+V3.3ALWAYS
C8H1
0.1UF
10UF
C8J3
U7G2D
ICH4-M
R8J10
1K
2
CR8J1A
3904
6
CR8J1B
3904
5
4
R8J5
2 POK_D
Q8J2
BSS138
1
470
1
2
POK_DQ
3
Q8J3
BSS138
1
2
VSS
V1.5_PWRGD
A1 VSS0
A4 VSS1
A16 VSS2
A18 VSS3
A20 VSS4
A22 VSS5
AA3 VSS6
AA9 VSS7
AA12 VSS8
AA16 VSS9
AA22 VSS10
AB7 VSS11
AB20 VSS12
AC1 VSS13
AC5 VSS14
AC10VSS15
AC14VSS16
AC18VSS17
AC23VSS18
B9 VSS19
B12 VSS20
B16 VSS21
B18 VSS22
B20 VSS23
B22 VSS24
C6 VSS25
C15 VSS26
C17 VSS27
C19 VSS28
C21 VSS29
C23 VSS30
D1 VSS31
D4 VSS32
D8 VSS33
D12 VSS34
D15 VSS35
D17 VSS36
D19 VSS37
D21 VSS38
D22 VSS39
D23 VSS40
E10 VSS41
E14 VSS42
E16 VSS43
E17 VSS44
E18 VSS45
E19 VSS46
E21 VSS47
E22 VSS48
F8 VSS49
G3 VSS50
G6 VSS51
ICH4-M
3
R8J8
1K
39
B
C8J2
10UF
MAX8888
G19
G21
H1
J6
K3
K11
K13
K19
K23
L10
L11
L12
L13
L14
L21
M1
M11
M12
M13
M20
M22
N5
N10
N11
N12
N13
N14
N19
N21
N23
P3
P11
P13
P20
P22
R5
R18
R21
T1
T19
T23
U20
V3
V15
V17
W5
W8
W22
Y7
Y19
VSS52
VSS53
VSS54
VSS55
VSS56
VSS57
VSS58
VSS59
VSS60
VSS61
VSS62
VSS63
VSS64
VSS65
VSS66
VSS67
VSS68
VSS69
VSS70
VSS71
VSS72
VSS73
VSS74
VSS75
VSS76
VSS77
VSS78
VSS79
VSS80
VSS81
VSS82
VSS83
VSS84
VSS85
VSS86
VSS87
VSS88
VSS89
VSS90
VSS91
VSS92
VSS93
VSS94
VSS95
VSS96
VSS97
VSS98
VSS99
VSS100
VSS101
R8J11
10K
SHDN#
1
PM_SLP_S4# 19,32,37,38,43,44
Title
Size
A
Date:
A
21,22,23
U8H3
SI3442DY
+V1.5ALWAYS
+V3.3ALWAYS
5,15,19,21,22,23,27,28,29,32,36,37,38,39,44,48
1
+V1.5
+V5
10UF
1UF
4
+V1.5S
15
+V3.3ALWAYS
5,15,19,21,22,23,27,28,29,32,36,37,38,39,44,48
1
+V5_ALWAYS
0.01_1%
C7J1
0.1UF
E11
F10
21,37
F15
F16
F18
K14
V7
V8
V9
F17
CR7G2
BAT54
VCC5REF
C7W1
VCCSUS3.3_0
VCCSUS3.3_1
VCCSUS3.3_2
VCCSUS3.3_3
VCCSUS3.3_4
VCCSUS3.3_5
VCCSUS3.3_6
VCCSUS3.3_7
VCCSUS3.3_8
VCCSUS3.3_9
5,6,8,9,11,16,18,21,23,2
R7V3
19,21
VCCPLL
+V3.3S
R6H2
ICH4-M
For power measurement, cut the
+VCC_IMVP plane and populate
R6H6.
1
NO_STUFF_0.01_1%
1
0.1UF
POWER
A5
B2
H6
H18
J1
J18
K6
M10
P6
P12
U1
V10
V16
V18
AC8
AC17
+VCC_IMVP
9,15,19,44,47,48
+V1.5S
3
0
ICH4-M
VCC3.3_0
VCC3.3_1
VCC3.3_2
VCC3.3_3
VCC3.3_4
VCC3.3_5
VCC3.3_6
VCC3.3_7
VCC3.3_8
VCC3.3_9
VCC3.3_10
VCC3.3_11
VCC3.3_12
VCC3.3_13
VCC3.3_14
VCC3.3_15
+V1.5S_ICHHUB
0.01_1%
3,4,5,9,10,18,40,41,47,48
19,21,22,24,37
E12
E13
E20
F14
G18
R6
T6
U6
3 PM_SLP_S4#_Q2
+V1.5
C6G1
PM_SLP_S4#_Q1
0.01_1%
15
E
+V1.5A_ICH
3
+V1.5ALWAYS
R8J7
C
ICH4-M (3 of 3)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
20
E
46
B
C
20,37 +V3.3ALWAYS_ICH
6 10K
7 10K
+V3.3ALWAYS
19,20,22,24,37 +V3.3S_ICH
19,20
18,37 SM_INTRUDER#
R2J4
R8H2
+V5_ALWAYS Generation
V5A_PWRGD
8
U5C3
V5A_COSC
RUN_SS
C5C16
47pF
C5C14
3300pF
1
COSC
2
RUN/SS
Vout=0.8(1+Rtop/Rbot)
Vout=0.8(1+(3.92k/750))= 4.98V
IMAX OUT = 50mV / 10mohms = 5A
7
R5P6
NO_STUFF_680K
4
Place these caps
near U5C3
TG
16
V5A_TG
BOOST
15
V5A_BOOST
C5P1
1
2
8
R5C8
37.4k_1%
SW
ITH
VIN
SGND
7
VOSENSE
5
6
14
V5A_SW
13
CR5C3
MBR0520LT1
INTVCC
12
+V5_ALWAYS
1
L5C1
SENSE-
BG
11
SENSE+
PGND
10
1
6
C5P5
C5P6
330pF
100K
2
2 1
4.7uH
C5P2
C5C12
C5P4
1UF
10UF
0.1UF
0.01_1%
2
CR5C1
B320A
4
R5C7
10_1%
3
R5C9
10_1%
3
2
1
V5A_BG
1
47pF
C5C11
LTC1735-1
47pF
V5A_SENSE+
+V3.3S
C5C15
1000PF
8.2K
R5C6
3.92k_1%
V5A_SENSEV5A_VOSENSE
19,25,32,37,39 PM_PWROK
19,32,37 PM_RSMRST#
R8H4
R8J6
20,28,29
R4C16
5
Q5C1B
Si4966DY
V5A_INTVCC
4
Q5C1A
Si4966DY
2
0.47uF
3
V5A_ITH
+V_RTC
5,6,8,9,11,16,18,20,23,26,31,33,34,35,36,38,39,40,41,44,48
5,19,32,37 PM_THRM#
39
PGOOD
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
10K
10K
10K
9
5
6
6
7
8
8
5
7
6
6
8
7
5
5
8
8
8
7
5
8
6
7
5
8
7
5
EXTVCC
RP8H2D 4
RP8H3C 3
RP8H2C 3
RP8H2B 2
RP8H2A 1
RP8H3A 1
RP8H3D 4
RP8H3B 2
RP8H1C 3
RP8G3C 3
RP8G2A 1
RP8H1B 2
RP8H1D 4
RP7J1D 4
RP7J1A 1
RP8H1A 1
RP8G3A 1
RP8G3B 2
RP8G3D 4
RP7F2A 1
RP7F2C 3
RP7F2B 2
RP7F2D 4
RP7E1A 1
RP7E1B 2
RP8H7D 4
15,16,44
100K_1%
V5A_ITH_D
18,22,23,24 PCI_FRAME#
18,22,23,24 PCI_IRDY#
18,22,23,24 PCI_TRDY#
4
18,22,23,24 PCI_STOP#
18,22,23,24 PCI_SERR#
18,22,23,24 PCI_DEVSEL#
18,22,23 PCI_PERR#
18,22,23,24 PCI_LOCK#
18 PCI_REQ0#
18,22 PCI_REQ1#
18,22 PCI_REQ2#
18,23 PCI_REQ3#
18,24 PCI_REQ4#
18,26,37 INT_IRQ14
18,26,37 INT_IRQ15
15,18,23,24 INT_PIRQA#
15,18,23,24 INT_PIRQB#
18,23,24 INT_PIRQC#
18,23,24 INT_PIRQD#
18,22,23 INT_PIRQE#
18,22,23 INT_PIRQF#
18,22,23 INT_PIRQG#
18,22,23,37 INT_PIRQH#
22,23 PCI_REQ64#
22,23 PCI_ACK64#
19,22,23,24,32,34,37 PM_CLKRUN#
3
5,15,19,20,22,23,27,28,29,32,36,37,38,39,44,48
+VDC
R5P7
V5A_BG_D
3
2
1
RP8H6C
RP8H7B
2
19,35,37 PM_RI#
18,37 SMB_ALERT#
E
20,22,23,27,36,37,43,44
1
ICH4 Pullups
D
+V5
2
A
1
100K
100K
R5C5
750_1%
20,37 +V3.3ALWAYS_ICH
18,22,23,24,47 SMB_CLK
R8J1
2
2.2k
1
18,22,23,24,47 SMB_DATA
R8J3
2
2.2k
1
2
FAB REVISION
2
R6F20
NO_STUFF_10K
C5C10
R7F8
R6F19
10K
20,22,23,27,36,37,43,44 +VDC
+V5
19,20,22,24,37 +V3.3S_ICH
C5P3
100pF
10%
0.1UF
NO_STUFF_10K
15,16,44
+V5_ALWAYS
C5C3
20,28,29
2
C4C7
C4C6
150UF
22UF
0.1UF
19 ICH_FAB_REV0
19 ICH_FAB_REV1
19 ICH_FAB_REV2
R6F24
10K
R6F23
NO_STUFF_10K
Please place
C5C10 near
U5C3 Pin 9
R7F5
10K
Please place
C5P3 and
C5C3 near
U5C3.
Please place
C4C6 and
C4P7 near
R5C5.
R5P8
GND_V5A
FAB ID Strapping Table
ICH_FAB_REV
0
2
1
1
0
0
0
0
1
1
1
1
A
B
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
BOARD FAB
1
2
3
4
5
6
7
8
1
Title
Size
A
Date:
C
ICH4-M Pullups and Testpoints
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
21
E
46
A
B
23
23,44
C
+V12S_PCI
23,44
23
+V3.3S_PCI
4
18,21,23 INT_PIRQG#
18,21,23 INT_PIRQE#
C7B10
0.01UF
SLT1_PRSNT1#
C7C1
0.01UF
SLT1_PRSNT2#
18,23,24,32,34,37 INT_SERIRQ
6 CLK_PCI_SLOT1
18,21 PCI_REQ1#
18,23,24 PCI_AD31
18,23,24 PCI_AD29
18,23,24 PCI_AD27
18,23,24 PCI_AD25
3
18,23,24 PCI_C/BE3#
18,23,24 PCI_AD23
18,23,24 PCI_AD21
18,23,24 PCI_AD19
18,23,24 PCI_AD17
18,23,24 PCI_C/BE2#
18,21,23,24 PCI_IRDY#
18,21,23,24 PCI_DEVSEL#
18,21,23,24 PCI_LOCK#
18,21,23 PCI_PERR#
18,21,23,24 PCI_SERR#
18,23,24 PCI_C/BE1#
18,23,24 PCI_AD14
18,23,24 PCI_AD12
18,23,24 PCI_AD10
2
18,23,24 PCI_AD8
18,23,24 PCI_AD7
18,23,24 PCI_AD5
18,23,24 PCI_AD3
18,23,24 PCI_AD1
21,23 PCI_ACK64#
-V12S
+V12S_PCI
23
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
TRST#
TCK
+12V
GND1
TMS
TDO
TDI
+5V (1)
+5V (7)
+5V (2)
INTA#
INTB#
INTC#
INTD#
+5V (8)
PRSNT1#
RSV3
RSV1
+5V (9)
PRSNT2#
RSV4
GND2
GND14
GND3
GND15
RSV2
RSV5
GND4
RST#
CLK
+5V (10)
GND5
GNT#
REQ#
GND16
+5V (3)
PME#
AD31
AD30
AD29
+3.3V (7)
GND6
AD28
AD27
AD26
AD25
GND17
+3.3V (1)
AD24
C/BE3#
IDSEL
AD23
+3.3V (8)
GND8
AD22
AD21
AD20
AD19
GND18
+3.3V (2)
AD18
AD17
AD16
C/BE2#
+3.3V (9)
GND9
FRAME#
IRDY#
GND19
+3.3V (3)
TRDY#
DEVSEL#
GND20
GND10
STOP#
LOCK#
+3.3V (10)
PERR#
SDONE
+3.3V (4)
SBO#
SERR#
GND21
+3.3V (5)
PAR
C/BE1#
AD15
AD14
+3.3V (11)
GND11
AD13
AD12
AD11
AD10
GND22
GND12
AD09
KEY
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD08
C/BE0#
AD07
+3.3V (12)
+3.3V (6)
AD06
AD05
AD04
AD03
GND23
GND13
AD02
AD01
AD00
+5V (4)
+5V (11)
ACK64#
REQ64#
+5V (5)
+5V (12)
+5V (6)
+5V (13)
J7B2
+V5_PCI
+V3.3ALWAYS
+V5S_PCI
23
23
+V5S_PCI
A1
+V3.3S_PCI
23
A2
23
+V3.3S_PCI
A3
A4
A5
18,21,23 INT_PIRQF#
A6
INT_PIRQF# 18,21,23
18,21,23,37 INT_PIRQH#
A7
INT_PIRQH# 18,21,23,37
A8
SLT2_PRSNT1#
C8N1
A9
PM_CLKRUN# 19,21,23,24,32,34,37
A10
C8C1 SLT2_PRSNT2#
0.01UF
A11
PCI_GATED_RST# 15,23,32,37
A12
0.01UF
A13
A14
18,23,24,32,34,37 INT_SERIRQ
A15
BUF_PCI_RST# 18,23,24,26,31,32,34,37
A16
6 CLK_PCI_SLOT2
A17
PCI_GNT1# 18
A18
18,21 PCI_REQ2#
A19
PCI_PME# 15,18,23,37
A20
PCI_AD30 18,23,24
18,23,24 PCI_AD31
A21
18,23,24 PCI_AD29
A22
PCI_AD28 18,23,24
A23
PCI_AD26 18,23,24
18,23,24 PCI_AD27
A24
18,23,24 PCI_AD25
A25
PCI_AD24 18,23,24
A26 SLT1_IDSEL
PCI_AD16 18,23,24 18,23,24 PCI_C/BE3#
A27
R7C5 680
18,23,24 PCI_AD23
A28
PCI_AD22 18,23,24
A29
PCI_AD20 18,23,24
18,23,24 PCI_AD21
A30
18,23,24 PCI_AD19
A31
PCI_AD18 18,23,24
A32
PCI_AD16 18,23,24
18,23,24 PCI_AD17
A33
18,23,24 PCI_C/BE2#
A34
PCI_FRAME# 18,21,23,24
A35
18,21,23,24 PCI_IRDY#
A36
PCI_TRDY# 18,21,23,24
A37
18,21,23,24 PCI_DEVSEL#
A38
PCI_STOP# 18,21,23,24
A39
18,21,23,24 PCI_LOCK#
A40
18,21,23 PCI_PERR#
SMB_CLK 18,21,23,24,47
A41
SMB_DATA 18,21,23,24,47
A42
18,21,23,24 PCI_SERR#
A43
PCI_PAR 18,23,24
A44
PCI_AD15 18,23,24
18,23,24 PCI_C/BE1#
A45
18,23,24 PCI_AD14
A46
PCI_AD13 18,23,24
A47
PCI_AD11 18,23,24
18,23,24 PCI_AD12
A48
18,23,24 PCI_AD10
A49
PCI_AD9 18,23,24
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
TRST#
TCK
+12V
GND1
TMS
TDO
TDI
+5V (1)
+5V (7)
+5V (2)
INTA#
INTB#
INTC#
INTD#
+5V (8)
PRSNT1#
RSV3
RSV1
+5V (9)
PRSNT2#
RSV4
GND2
GND14
GND3
GND15
RSV2
RSV5
GND4
RST#
CLK
+5V (10)
GND5
GNT#
REQ#
GND16
+5V (3)
PME#
AD31
AD30
AD29
+3.3V (7)
GND6
AD28
AD27
AD26
AD25
GND17
+3.3V (1)
AD24
C/BE3#
IDSEL
AD23
+3.3V (8)
GND8
AD22
AD21
AD20
AD19
GND18
+3.3V (2)
AD18
AD17
AD16
C/BE2#
+3.3V (9)
GND9
FRAME#
IRDY#
GND19
+3.3V (3)
TRDY#
DEVSEL#
GND20
GND10
STOP#
LOCK#
+3.3V (10)
PERR#
SDONE
+3.3V (4)
SBO#
SERR#
GND21
+3.3V (5)
PAR
C/BE1#
AD15
AD14
+3.3V (11)
GND11
AD13
AD12
AD11
AD10
GND22
GND12
AD09
KEY
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD08
C/BE0#
AD07
+3.3V (12)
+3.3V (6)
AD06
AD05
AD04
AD03
GND23
GND13
AD02
AD01
AD00
+5V (4)
+5V (11)
ACK64#
REQ64#
+5V (5)
+5V (12)
+5V (6)
+5V (13)
PCI_C/BE0# 18,23,24
PCI_AD6 18,23,24
PCI_AD4 18,23,24
PCI_AD2 18,23,24
PCI_AD0 18,23,24
PCI_REQ64# 21,23
18,23,24 PCI_AD8
18,23,24 PCI_AD7
18,23,24 PCI_AD5
18,23,24 PCI_AD3
18,23,24 PCI_AD1
21,23 PCI_ACK64#
CON120_PCI
J8B3
SLOT1
1
18,19,23 PCI_GNTA#
R7V1
8.2K
5
2
4
6
PCI_C/BE0# 18,23,24
PCI_AD6 18,23,24
PCI_AD4 18,23,24
PCI_AD2 18,23,24
PCI_AD0 18,23,24
PCI_REQ64# 21,23
CON120_PCI
20,21,23,27,36,37,43,44
+V5
23
+V5_PCI
R8N1
NO_STUFF_0
PCI_REQA# 18,23
INT_SERIRQ 18,23,24,32,34,37
1
5Pin_Keyed-HDR
R7U2
8.2K
19,20,21,24,37
Title
+V3.3S_ICH
Size
A
Date:
A
2
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
+V3.3S_ICH
J7G1
LEGACY HEADER
FOR ADD-IN
AUDIO CARD
TESTING
VIA SLOT1 ONLY
5,15,19,20,21,23,27,28,29,32,36,37,38,39,44
+V5S_PCI
23
A1
A2
23
+V3.3S_PCI
A3
A4
4
A5
A6
INT_PIRQG# 18,21,23
A7
INT_PIRQE# 18,21,23
A8
A9
PM_CLKRUN# 19,21,23,24,32,34,37
A10
A11
PCI_GATED_RST# 15,23,32,37
A12
A13
A14
A15
BUF_PCI_RST# 18,23,24,26,31,32,34,37
A16
A17
PCI_GNT2# 18
A18
A19
PCI_PME# 15,18,23,37
A20
PCI_AD30 18,23,24
A21
A22
PCI_AD28 18,23,24
A23
PCI_AD26 18,23,24
A24
A25
PCI_AD24 18,23,24
A26 SLT2_IDSEL
PCI_AD17 18,23,24
A27
R8C1 680
3
A28
PCI_AD22 18,23,24
A29
PCI_AD20 18,23,24
A30
A31
PCI_AD18 18,23,24
A32
PCI_AD16 18,23,24
A33
A34
PCI_FRAME# 18,21,23,24
A35
A36
PCI_TRDY# 18,21,23,24
A37
A38
PCI_STOP# 18,21,23,24
A39
A40
SMB_CLK 18,21,23,24,47
A41
SMB_DATA 18,21,23,24,47
A42
A43
PCI_PAR 18,23,24
A44
PCI_AD15 18,23,24
A45
A46
PCI_AD13 18,23,24
A47
PCI_AD11 18,23,24
A48
A49
PCI_AD9 18,23,24
SLOT2
19,20,21,24,37
1
23
5,15,19,20,21,23,27,28,29,32,36,37,38,39,44,48
+V5S_PCI
23
+V5_PCI
E
-V12S
+V3.3ALWAYS
23
D
B
C
PCI Slot 1 & 2
Project:
Document Number
Friday, May 21, 2004
D
Sheet
22
Rev
of
E
46
A
B
C
D
5,15,19,20,21,22,27,28,29,32,36,37,38,39,44,48
+V5_PCI
15,17,27,37,38,44 +V12S
Moon ISA support
+V12S_PCI
Default: 1-2
19
15,18,19,20,27,30,32,35,37,38,39,43,44
4
+V3.3S_PCI
3
18,22 PCI_REQA#
22,44
+V3.3PCISLT3
3
PCI_NOGO
22
+V3.3
1
2
1
2
R7B2 0.01_1%
J9E4
Default: 1-2
-V12S
1 RP7B1A 8
0
PCI_RSV5
22
Moon ISA support
22
J9E2
E
+V3.3ALWAYS
CON3_HDR
CON3_HDR
1
RP7F4A8
NO_STUFF_0
+V5PCISLT3
+V5PCISLT3
C7B4
C8B2
C7B5
10UF
0.1UF
0.1UF
R7C6
PCI_RSV1
0
22
3 RP7B1C 6
0
18,21,24 INT_PIRQD#
4 RP7F4D 5
NO_STUFF_0
18,21,22,37 INT_PIRQH#
22
+V5
C8C3
C8E5
C8B4
C8E6
C8B5
22UF
0.1UF
0.1UF
0.1UF
0.1UF
0
18,21 PCI_REQ3#
C8D3
C8C6
C8E2
C8C8
C8D9
C8D5
22UF
22UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
18,22,24 PCI_AD27
18,22,24 PCI_AD25
18,22,24 PCI_C/BE3#
18,22,24 PCI_AD23
8,15,16,17,18,20,24,25,27,34,35,39,40,44,47
Layout Note:
Place half of these caps by PCI slot 1, the other
half by PCI slot2
0.01_1%
22
C8C2 SLT3_PRSNT2#
18,22,24 PCI_AD31
18,22,24 PCI_AD29
C8D7
R7E3
SLT3_PRSNT1#
18,22,24,32,34,37 INT_SERIRQ
R8B6
NO_STUFF_0
6 CLK_PCI_SLOT3
Place close to slot 3
+V5S
C8N2
0.01UF
R8B7
Place close to slot 3
+V3.3PCISLT3
0.01UF
+V5S_PCI
20,21,22,27,36,37,43,44
3
PCI_SLT3INTD#
4 RP7B1D 5
0
15,18,21,24 INT_PIRQA#
+V5PCISLT3
PCI_SLT3INTB#
3 RP7F4C 6
NO_STUFF_0
18,21,22 INT_PIRQF#
18,22,24 PCI_AD21
18,22,24 PCI_AD19
18,22,24 PCI_AD17
18,22,24 PCI_C/BE2#
18,21,22,24 PCI_IRDY#
+V5S_PCI
18,21,22,24 PCI_DEVSEL#
C8E3
C8B7
C7B8
C7E2
C7B6
C8E7
22UF
22UF
22UF
22UF
0.1UF
0.1UF
C8C4 C7C3
0.1UF
0.1UF
C7C2
0.1UF
18,21,22,24 PCI_LOCK#
18,21,22 PCI_PERR#
C8B3
C7B7
C7E4
C7B11
C8C5
C8B6
C7E3
C8E4
C7B9
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
18,22,24 PCI_C/BE1#
18,22,24 PCI_AD14
18,22,24 PCI_AD12
18,22,24 PCI_AD10
18,22,24 PCI_AD8
18,22,24 PCI_AD7
18,22,24 PCI_AD5
18,22,24 PCI_AD3
18,22,24 PCI_AD1
+V3.3S
21,22 PCI_ACK64#
5,6,8,9,11,16,18,20,21,26,31,33,34,35,36,38,39,40,41,44,48
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
-12V
TRST#
TCK
+12V
GND1
TMS
TDO
TDI
+5V (1)
+5V (7)
+5V (2)
INTA#
INTB#
INTC#
INTD#
+5V (8)
PRSNT1#
RSV3
RSV1
+5V (9)
PRSNT2#
RSV4
GND2
GND14
GND3
GND15
RSV2
RSV5
GND4
RST#
CLK
+5V (10)
GND5
GNT#
REQ#
GND16
+5V (3)
PME#
AD31
AD30
AD29
+3.3V (7)
GND6
AD28
AD27
AD26
AD25
GND17
+3.3V (1)
AD24
C/BE3#
IDSEL
AD23
+3.3V (8)
GND8
AD22
AD21
AD20
AD19
GND18
+3.3V (2)
AD18
AD17
AD16
C/BE2#
+3.3V (9)
GND9
FRAME#
IRDY#
GND19
+3.3V (3)
TRDY#
DEVSEL#
GND20
GND10
STOP#
LOCK#
+3.3V (10)
PERR#
SDONE
+3.3V (4)
SBO#
SERR#
GND21
+3.3V (5)
PAR
C/BE1#
AD15
AD14
+3.3V (11)
GND11
AD13
AD12
AD11
AD10
GND22
GND12
AD09
KEY
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26 SLT3_IDSEL
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
AD08
C/BE0#
AD07
+3.3V (12)
+3.3V (6)
AD06
AD05
AD04
AD03
GND23
GND13
AD02
AD01
AD00
+5V (4)
+5V (11)
ACK64#
REQ64#
+5V (5)
+5V (12)
+5V (6)
+5V (13)
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
J8B2
R8E1
0.01_1%
22
C7D6
C7D2
C8D6
C8C9
C8D4
C8D2
C8D1 C8C7
C7C5
C7D1
C7E1
C7D7
C8E1
22UF
22UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF 0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
Default: 2-3
J9E5
PM_CLKRUN# 19,21,22,24,32,34,37
1
PCI_GNTA# 18,19,22
2
3
PCI_GATED_RST# 15,22,32,37
R8P1
CON3_HDR
NO_STUFF_0
R8P2
0
BUF_PCI_RST# 18,22,24,26,31,32,34,37
S3_PCI_GNT3#
PCI_RSV4
PCIRST#
PCI_PME# 15,18,22,37
PCI_AD30 18,22,24
R8C2
PCI_AD24 18,22,24
PCI_AD18 18,22,24
680
PCI_AD22 18,22,24
PCI_AD20 18,22,24
PCI_AD18 18,22,24
PCI_AD16 18,22,24
22
C
+V3.3S_PCI
PCI_FRAME# 18,21,22,24
+V3.3PCISLT3
PCI_TRDY# 18,21,22,24
R8E2
1K
PCI_STOP# 18,21,22,24
SMB_CLK 18,21,22,24,47
SMB_DATA 18,21,22,24,47
PCI_PAR 18,22,24
PCI_AD15 18,22,24
PCI_AD13 18,22,24
PCI_AD11 18,22,24
R8E3
10K
2
3
Q8E1
2N3904
1
PCI_AD9 18,22,24
2
PCI_C/BE0# 18,22,24
PCI_GNT3# 18
PCI_AD6 18,22,24
PCI_AD4 18,22,24
PCI_AD2 18,22,24
PCI_AD0 18,22,24
PCI_REQ64# 21,22
Note: To Power PCI Slot3 in
suspend Stuff R8B6, R7C3, R8P1
and Unstuff R8B7, R7C6, R8P2
Title
Size
A
Date:
B
3
PCI_AD28 18,22,24
PCI_AD26 18,22,24
CON120_PCI
PCI Slot3 is farthest
from processor
A
INT_PIRQG# 18,21,22
PCI_SLT3INTA#
PCI_SLT3INTC#
1
C8D8
2 RP7F4B 7
NO_STUFF_0
4
Moon ISA support
SLOT3
+V3.3S_PCI
INT_PIRQB# 15,18,21,24
V3.3S_PCI_D
18,21,22,24 PCI_SERR#
2
INT_PIRQE# 18,21,22
2 RP7B1B 7
0
+V12S_PCI
+V3.3PCISLT3
R7C3
NO_STUFF_0
INT_PIRQC# 18,21,24
1
PCI Slot 3/Moon-ISA support & Decoupling
Document Number
Project:
Friday, May 21, 2004
D
Sheet
23
Rev
of
E
46
A
B
Qbuffers used for isolation during suspend
as well as 5V->3.3V translation
U9D2
1
18,22,23 PCI_AD[31:0]
PCI_AD22
PCI_AD23
PCI_AD26
PCI_AD27
PCI_AD30
PCI_AD31
PCI_AD29
PCI_AD28
PCI_AD25
PCI_AD24
PCI_AD12
PCI_AD14
PCI_AD15
PCI_AD18
PCI_AD19
PCI_AD21
PCI_AD20
PCI_AD17
PCI_AD16
PCI_AD13
4
C
8,15,16,17,18,20,23,25,27,34,35,39,40,44,47
2
3
4
5
6
7
9
10
11
12
13
14
16
18
19
20
21
22
23
24
48
47
17,25 DOCK_QPCIEN#
R9D3
100K
+V5S_QSPWR
NC
VCC
15
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
46
45
44
43
42
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
1OE#
2OE#
DOCK_AD22
DOCK_AD23
DOCK_AD26
DOCK_AD27
DOCK_AD30
DOCK_AD31
DOCK_AD29
DOCK_AD28
DOCK_AD25
DOCK_AD24
DOCK_AD12
DOCK_AD14
DOCK_AD15
DOCK_AD18
DOCK_AD19
DOCK_AD21
DOCK_AD20
DOCK_AD17
DOCK_AD16
DOCK_AD13
C9P1
22UF
0.1UF
3
18
18
18,22,23,32,34,37
15,18,21,23
15,18,21,23
18,21,23
18,21,23
18,21,22,23
18,22,23
18,21,22,23
18,21,22,23
18,21,22,23
18,21,22,23
18,21,22,23
18,21,22,23
18,22,23
18,22,23
18,22,23
18,22,23
25
+V5S_QSPWR
18,21,22,23,47 SMB_DATA
PCI_AD1
PCI_AD0
18,21,22,23,47 SMB_CLK
2
7,17 DAC_DDCADATA
7,17 DAC_DDCACLK
48
47
DOCK_QPCIEN#
NC
VCC
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
46
45
44
43
42
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
GND1
GND2
GND3
GND4
8
17
32
41
1OE#
2OE#
DOCK_AD2
DOCK_AD3
DOCK_AD6
DOCK_AD7
DOCK_AD10
DOCK_AD11
DOCK_AD9
DOCK_AD8
DOCK_AD5
DOCK_AD4
DOCK_AD1
DOCK_AD0
+V3.3S_ICH
+V5S_QSPWR
U9E1
1
U9D1
2
3
4
5
6
7
9
10
11
12
13
14
16
18
19
20
21
22
23
24
4
0.1UF
R7G2
8.2K
3
PCI_AD2
PCI_AD3
PCI_AD6
PCI_AD7
PCI_AD10
PCI_AD11
PCI_AD9
PCI_AD8
PCI_AD5
PCI_AD4
C9D1
19,20,21,22,37
DOCK_AD[31:0]
15
DOCK_QDEN# 25
1
Q9D1
BSS84
8
17
32
41
GND1
GND2
GND3
GND4
E
2
C9C1
74CBTD16210
1
D
+V5S
C9R1
0.1UF
PCI_GNTB#
PCI_REQB#
INT_SERIRQ
INT_PIRQA#
INT_PIRQB#
INT_PIRQC#
INT_PIRQD#
PCI_SERR#
PCI_PAR
PCI_IRDY#
PCI_DEVSEL#
PCI_STOP#
PCI_TRDY#
PCI_LOCK#
PCI_FRAME#
PCI_C/BE3#
PCI_C/BE2#
PCI_C/BE1#
PCI_C/BE0#
DOCK_QPCIEN#
NC
VCC
15
2
3
4
5
6
7
9
10
11
12
13
14
16
18
19
20
21
22
23
24
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
46
45
44
43
42
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
48
47
1OE#
2OE#
GND1
GND2
GND3
GND4
8
17
32
41
DOCK_SMBDATA 25
C9C2
DOCK_GNTB# 25
DOCK_REQB# 25
DOCK_SERIRQ 25
DOCK_PIRQA# 25
DOCK_PIRQB# 25
DOCK_PIRQC# 25
DOCK_PIRQD# 25
DOCK_SERR# 25
DOCK_PAR 25
DOCK_IRDY# 25
DOCK_DEVSEL# 25
DOCK_STOP# 25
DOCK_TRDY# 25
DOCK_LOCK# 25
DOCK_FRAME# 25
DOCK_C/BE3# 25
DOCK_C/BE2# 25
DOCK_C/BE1# 25
DOCK_C/BE0# 25
0.1UF
3
74CBTD16210
DOCK_SMBCLK 25
DOCK_DDCDAT 25
DOCK_DDCCLK 25
2
74CBTD16210
+V5S_QSPWR
U9C1
18,22,23,26,31,32,34,37
19,21,22,23,32,34,37
1
3
4
7
8
11
BUF_PCI_RST#
18
18,21
6
32,36,37
PM_CLKRUN#
14
17
18
21
22
PCI_GNT4#
PCI_REQ4#
CLK_DOCKPCI
DOCK_INTR#
OE#
R9C1
100
A
1
13
1A1
1A2
1A3
1A4
1A5
2A1
2A2
2A3
2A4
2A5
1OE#
2OE#
VCC
24
1B1
1B2
1B3
1B4
1B5
2
5
6
9
10
2B1
2B2
2B3
2B4
2B5
15
16
19
20
23
GND
12
C9R2
DOCK_RESET# 25
DOCK_CLKRUN#
0.1UF
25
DOCK_GNT4# 25
DOCK_REQ4# 25
CLK_DOCKCONNPCI 25
DOCK_DOCKINTR# 25
1
Title
SN74CBTD3384
QUIET DOCK
QSWITCH
B
Size
A
Date:
C
Docking Q-Switches
Document Number
Project:
Friday, May 21, 2004
D
Sheet
24
Rev
of
E
46
A
B
C
D
J9E3A
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
4
17 DOCK_RED
17 DOCK_VSYNC
17 DOCK_HSYNC
24 DOCK_SMBDATA
24 DOCK_CLKRUN#
24 DOCK_REQB#
24 DOCK_PIRQC#
24 DOCK_PIRQB#
24 DOCK_GNT4#
GND0
V_DC0
V_DC1
GND1
GND2
RED_RTN
RED
VSYNC
HSYNC
GND3
GND4
NC0
SM_DATA
SYSACT#
CLKRUN#
PC_REQ#
GND5
CD2
NC1
NC2
CD3#/GND
INTD#
INTC#
GND6
GNT#
E
J9E3C
REQ#
GND7
PERR#
SERR#
GND8
STOP#
TRDY#
GND9
LOCK#
FRAME#
GND10
C/BE1#
C/BE0#
GND11
AD29
AD28
GND12
AD25
AD24
GND13
AD21
AD20
GND14
V_ACDC0
V_ACDC1
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
DOCK_REQ4# 24
DOCK_SERR# 24
DOCK_AD17
DOCK_AD16
DOCK_STOP# 24
DOCK_TRDY# 24
DOCK_AD13
DOCK_AD12
DOCK_LOCK# 24
DOCK_FRAME# 24
DOCK_AD9
DOCK_AD8
DOCK_C/BE1# 24
DOCK_C/BE0# 24
DOCK_AD5
DOCK_AD4
DOCK_AD29
DOCK_AD28
DOCK_AD1
DOCK_AD0
DOCK_AD25
DOCK_AD24
24 CLK_DOCKCONNPCI
DOCK_AD21
DOCK_AD20
200Pin_Docking-Plug
3V
GND30
NC7
GND31
AD17
AD16
GND32
AD13
AD12
GND33
AD9
AD8
GND34
AD5
AD4
GND35
AD1
AD0
GND36
PCI_CLK
GND37
SLCTIN#
PLT_AFD#
PLT_PE
GND38
LPT_BUSY
LPT_D5
LPT_D4
GND39
ERROR#
LPT_D1
LPT_D0
GND40
SER_OUT
SER_RTS
SER_CTS
SER_DTR
MS_DATA
MS_CLK
GND41
L_LININ
LIN_GND
R_LININ
NC8
MIDI_SRX
MIDI_STX
USB+
USBGND42
DCKINTR#
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
4
DOCK_DOCKINTR#
24
200Pin_Docking-Plug
3
3
24 DOCK_AD[31:0]
J9E3B
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
17 DOCK_GREEN
17 DOCK_BLUE
24 DOCK_DDCDAT
24 DOCK_DDCCLK
24 DOCK_SMBCLK
24 DOCK_SERIRQ
2
24 DOCK_GNTB#
24 DOCK_PIRQA#
24 DOCK_PIRQD#
V_DC2
V_DC3
GND15
GND16
GRN_RTN
GREEN
BLU_RTN
BLUE
DDC_DAT
DDC_CLK
GND17
GND18
SM_CLK
SERINT
NC3
PC_GNT#
GND19
NC4
NC5
NC6
GND20
INTB#
INTA#
GND21
UNDKRQ#
J9E3D
UNDKGT#
GND22
PAR
PCI_RST#
GND23
IRDY#
DEVSEL#
GND24
C/BE3#
C/BE2#
GND25
AD31
AD30
GND26
AD27
AD26
GND27
AD23
AD22
GND28
AD19
AD18
GND29
V_ACDC2
V_ACDC3
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
DOCK_PAR 24
DOCK_RESET# 24
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
DOCK_AD15
DOCK_AD14
DOCK_IRDY# 24
DOCK_DEVSEL# 24
DOCK_AD11
DOCK_AD10
DOCK_C/BE3# 24
DOCK_C/BE2# 24
DOCK_AD7
DOCK_AD6
DOCK_AD31
DOCK_AD30
DOCK_AD3
DOCK_AD2
DOCK_AD27
DOCK_AD26
DOCK_AD23
DOCK_AD22
24 DOCK_QDEN#
19,21,32,37,39 PM_PWROK
DOCK_AD19
DOCK_AD18
200Pin_Docking-Plug
5V0
5V1
NC9
GND43
AD15
AD14
GND44
AD11
AD10
GND45
AD7
AD6
GND46
AD3
AD2
GND47
SRBTN#
QDEN#
QPCIEN#
NBPWROK
DPWRSW
NC10
LPT_SLCT
LPT_STB#
CD4#/GND
LPT_ACK#
LPT_D7
LPT_D6
GND48
LPT_INIT#
LPT_D3
LPT_D2
GND49
SER_RD
SER_DSR
SER_RI
SER_DCD
KB_DATA
KB_CLK
NC11
L_INOUT
L_O_GND
R_INOUT
NC12
MICIN
MIC_GND
5V_USB
GND_USB
SUSTAT#
CD1#
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
2
200Pin_Docking-Plug
CR9C1
8,15,16,17,18,20,23,24,27,34,35,39,40,44,47
15,19,32,37,38,43,44
+V5S
1 DOCK_SUSTAT#
3
PM_SLP_S3#
200
199
150
149
BAR43
There is pull-up on
docking station.
R9E1
33K
<NO_STUFF>
17,24 DOCK_QPCIEN#
1
152
151
102
101
1
100 5049
Title
Size
A
Date:
52512 1
A
B
C
Docking Connector
Project:
Document Number
Friday, May 21, 2004
D
Sheet
25
Rev
of
E
46
A
B
C
R4Y2
BUF_PCI_RST#
19 IDE_PDD[15:0]
4
5,6,8,9,11,16,18,20,21,23,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
RP2J1C
3
E
47
IDE_D_PRST#
18,22,23,24,31,32,34,37
D
PRIMARY HDD CONN
J4J2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
IDE_PDD7
IDE_PDD6
IDE_PDD5
IDE_PDD4
IDE_PDD3
IDE_PDD2
IDE_PDD1
IDE_PDD0
6
19 IDE_PDDREQ
19 IDE_PDIOW#
19 IDE_PDIOR#
19 IDE_PIORDY
19 IDE_PDDACK#
18,21,37 INT_IRQ14
19 IDE_PDA1
19 IDE_PDA0
19 IDE_PDCS1#
27,44 IDE_PDACTIVE#
4.7K
2
4
6
8
10
12
14
16
18
22
24
26
28
30
32
34
36
38
40
IDE_PDD[15:0]
19
4
IDE_PDD8
IDE_PDD9
IDE_PDD10
IDE_PDD11
IDE_PDD12
IDE_PDD13
IDE_PDD14
IDE_PDD15
R2J2
IDE_PD_CSEL
470
IDE_PATADET 19,37
R4Y1
10K
20x2-HDR
19 IDE_PDCS3#
19 IDE_PDA2
3
SECONDARY HDD CONN
27 IDE_D_SRST#
J4J1
19 IDE_SDD[15:0]
5,6,8,9,11,16,18,20,21,23,31,33,34,35,36,38,39,40,41,44,48
+V3.3S
RP2J1D
4
IDE_SDD7
IDE_SDD6
IDE_SDD5
IDE_SDD4
IDE_SDD3
IDE_SDD2
IDE_SDD1
IDE_SDD0
5
19 IDE_SDDREQ
19 IDE_SDIOW#
19 IDE_SDIOR#
19 IDE_SIORDY
19 IDE_SDDACK#
18,21,37 INT_IRQ15
19 IDE_SDA1
19 IDE_SDA0
19 IDE_SDCS1#
27 IDE_SDACTIVE#
4.7K
2
3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
22
24
26
28
30
32
34
36
38
40
IDE_SDD[15:0]
IDE_SDD8
IDE_SDD9
IDE_SDD10
IDE_SDD11
IDE_SDD12
IDE_SDD13
IDE_SDD14
IDE_SDD15
19
R3J1
IDE_SD_CSEL
2
470
IDE_SATADET 19,37
R2J1
10K
20x2-HDR
19 IDE_SDCS3#
19 IDE_SDA2
1
1
Title
Size
A
Date:
A
B
C
IDE 1 of 2
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
26
E
46
A
B
C
D
Secondary IDE Power
8,15,16,17,18,20,23,24,25,34,35,39,40,44,47
E
8,15,16,17,18,20,23,24,25,34,35,39,40,44,47
+V5S
+V5S
C2H1
14
U3H1A
0.1UF
2
4
IDE_SPWR_EN
74HC14
U3H1E
74HC14
10 IDE_SPWR2_D
11
C2H2
R2H6 390K
IDE_SPWR2
2
Note: Primary IDE
Power on Turner
DC/DC Module
7
8,15,16,17,18,20,23,24,25,34,35,39,40,44,47
+V5S
U3H1D
SHMIDT4
9
C2H4
SHMIDT2
8
3
IDE_SRST#
4
7
8
5
6
+V5S_IDE_S
R3H2
R2H7
0.01_1%
IDE_D_SRST# 26
47
74HC14
0.1UF
R2H1
NO_STUFF_0
4
V5S_IDE_PD
+V12S_IDE_S
J2H1
C2H5
C2J1
0.1UF
22UF 0.1UF 100uF
C2H6 + C2H3
1
2
3
4
3
4Pin_PwrConn
7
7
74HC14
Q3H1
BSS138
15,17,23,37,38,44 +V12S
8,15,16,17,18,20,23,24,25,34,35,39,40,44,47
IDE_SPWR_EN_Q#
SPARE GATE
+V12S_IDE_S
14
U3H1C
C2G14
SHMIDT3 5
R2G12
1M
1
2N7002
100K
1000PF
IDE_SPWR_EN_D#
1
Q2G4
6
3
TP_SHMIDT_C
R3H1
SI2307DS
74HC14
7
Q3G1
0
3
2
IDE_SPWR_EN
2
2
R2G13
For
Secondary
IDE Drive
Only
+V5S
IDE_SPWR_EN# 1
3
3
U2H1B
SI4925DY
4
U3H1B
14
14
100K
1M
3
U2H1A
SI4925DY
R2H8
R2H9
1
1000PF
7
+V5S_IDE_S
R2H5
1M
14
1
34,37 IDE_SPWR_EN#
8,15,16,17,18,20,23,24,25,34,35,39,40,44,47
+V5S
IDE Activity LEDs
MDC Interposer Header
5,15,19,20,21,22,23,28,29,32,36,37,38,39,44,48
R2J6
15,18,19,20,23,30,32,35,37,38,39,43,44
470
20,21,22,23,36,37,43,44
+V3.3ALWAYS
+V3.3
+V5
J9F4
IDE_PLED
2
2
19 AUDIO_PWRDN
19
AC_SYNC
DS2J2
GREEN
1
19 AC_SDATAIN1
19 AC_SDATAIN0
26,44 IDE_PDACTIVE#
19
AC_BITCLK
R9F3
R9F7
R9G2
SDATAIN1_D
SDATAIN0_D
33
33
AC_BITCLK_D
33
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
2
AC_SPKR 19
AC_SDATAOUT_D
R9F5 33
SDATAIN2_D
R9F6 33
AC_SDATAOUT 19
AC_SDATAIN2 19
AC_RST# 19
2x10-SHD-HDR
R9F2
10K
+V5S_IDE_S
Layout Note:
Place MDC series resistors
0.1 to 0.4 inches from MDC
header based on topology
R2J3
1
470
26 IDE_SDACTIVE#
2 IDE_SDACTIVE#_Q
1
DS2J1
GREEN
Title
Size
A
Date:
A
1
B
C
IDE 2 of 2 / MDC Interposer
Document Number
Project:
Friday, May 21, 2004
D
Sheet
27
Rev
of
E
46
A
B
+V5_ALWAYS
C
D
E
20,21,29
R4N2
+V5_USB1
0.01_1%
C4B1
5,15,19,20,21,22,23,27,29,32,36,37,38,39,44,48
+V3.3ALWAYS
0.1UF
+V5_ALWAYS
20,21,29
1
2
4
RP5B1B
10K
USB_OC0# 19
U4B2
1
2
3
4
EN_U16
GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#
8
7
6
5
7
R4B1
1K
RP5B1A
10K
FB4B1
50OHM
1
2
8
4
USBPWR_CONNC
USBPWR_CONND
FB4B2
50OHM
2
1
C4A1
USB_OC1# 19
TPS2052
C4A6
C4A5
470PF
150UF
470PF
C4A2
150UF
L4N1
4
USB_PP0
2
3
USBC_VCC
USBCUSBC+
90@100MHz
CR4M5
CR4N1
2
3
1
1
1
19
USB_PN0
3
Triple
USB
Connector
2
19
Clamping-Diode
Clamping-Diode
J4A2
1
2
3
4
VCC1
P#0
P0
GND1
TOP
PORT
USBD_VCC
USBDUSBD+
5
6
7
8
VCC2
P#1
P1
GND2
MIDDLE
PORT
USBE_VCC
9
10
11
12
VCC3
P#2
P2
GND3
BOTTOM
PORT
1
4
USB_PP1
2
3
1
90@100MHz
CR4M4
2
CR4M2
2
19
USB_PN1
1
L4M2
19
4
USBE-
19
USB_PP2
2
3
USBE+
CR4M1
Clamping-Diode
Clamping-Diode
4
3
20,21,29
RP5B1C
10K
1
RP5B1D
10K
GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#
8
7
6
5
5
1
2
3
4
6
U5B1
EN_U10
USBPWR_CONNE
USB_OC2# 19
1
FB4B3
50OHM
1
2
USBE_VCC
OC2#
470PF
B
Title
C4A7
TPS2052
A
2
+V3.3ALWAYS
0.1UF
R5N1
1K
CR4M3
2
5,15,19,20,21,22,23,27,29,32,36,37,38,39,44,48
1
L4M1
1
1
USB_PN2
+V5_USB1
C5B2
+V5_ALWAYS
2
19
90@100MHz
13
14
15
16
3_stack_USB
Clamping-Diode
Clamping-Diode
2
GND4
GND5
GND6
GND7
C
C4A8
150UF
Size
A
Date:
USB (1 of 2)
Document Number
Project:
Friday, May 21, 2004
D
Sheet
Rev
of
28
E
46
A
B
C
D
E
4
4
5,15,19,20,21,22,23,27,28,32,36,37,38,39,44,48
+V5_ALWAYS
+V3.3ALWAYS
20,21,28
R6B2
10K
R6N2
0.01_1%
R6A7
10K
USB_OC3# 19
U6B1
+V5_USB2
C6A12
3
R6B3
1K
EN_U2
0.1UF
1
2
3
4
GND
IN
EN1
EN2
OC1#
OUT1
OUT2
OC2#
8
7
6
5
USBPWR_CONNA
USBPWR_CONNB
1
FB5B1 50OHM
2
3
USB_OC4# 19
TPS2052
C5B3
C5B1
470PF
150UF
J5A1B
L5M2
USB_PN3
1
4
19
USB_PP3
2
3
1
90@100MHz
1
19
USBA_VCC
USBAUSBA+
CR5M3
1
FB5B2 50OHM
2
2
2
CR5M4
VCC2
C5B4
C5B5
470PF
150UF
1
2
3
4
VCC1
P#0
TOP
P0
PORT
GND10
5
6
7
8
VCC2 BOTTOM
P#1
PORT
P1
GND11
STACKED_RJ45_USB
Clamping-Diode
Clamping-Diode
L5M1
USB_PN4
1
4
19
USB_PP4
2
3
USBBUSBB+
2
1
90@100MHz
1
2
19
CR5M2
2
2
CR5M1
Clamping-Diode
Clamping-Diode
5,15,19,20,21,22,23,27,28,32,36,37,38,39,44,48
+V3.3ALWAYS
R7V9
10K
19
USB_OC5#
1
1
Title
Size
A
Date:
A
B
C
USB Connector (2 of 2)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
29
E
46
A
B
C
+V3.3
D
15,18,19,20,23,27,32,35,37,38,39,43,44
4
4
+V3.3_LAN
R6A1
0.01_1%
Bulk caps should be 4.7uF or higher.
Layout note:
Place 100 Ohm resistor
close to 82562EM
L6A1
1
C6A5
C6A7
C6A10 C6A11 C6A3 C6A2
4.7UF
4.7UF
0.1UF 0.1UF 0.1UF 0.1UF
2
+V3.3_L_LAN
+V3.3_LAN
3
R6A6
10K
If LAN is enabled,
PM_LANPWROK waits for
PM_PWROK to go high and
stays high in S3.
LAN_RST
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_RXD2
LAN_RXD1
LAN_RXD0
LAN_ADV
3
LAN_TCK
Q6A1
BSS138
1
ADV10
ISOL_TCK
ISOL_TI
ISOL_EX
TOUT
TESTEN
R6M1
100
82562EM
2
18,32 PM_LANPWROK
LAN_TOUT
LAN_TESTEN
41
30
28
29
26
21
JCLK
JRSTSYNC
JTXD2
JTXD1
JTXD0
JRXD2
JRXD1
JRXD0
Platform LAN
Connect
C6A4
0.1UF
4.7UF
TDP
TDN
10
11
RDP
RDN
15
16
X2
X1
J5A1A
LAN_TDP
LAN_TDN
C6A1
TDC
100_1%
NO_STUFF_10PF
R6A4
121_1%
LAN_RDP
5 LAN_RB100
4 LAN_RB10
LAN_RDN
R6A2
619_1%
R6A3 549_1%
32
31
27
LAN_ACTLED#
LAN_SPDLED#
LAN_LILED#
47
46
LAN_X2
LAN_X1
TDP
TDN
13
12
TDC1
TDC2
11
14
RDP
RDN
17
18
19
20
LED_PWR
SPEED LED
ACT_LED
LINK_LED
GRN
YLW
RXC
15
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
28
27
26
25
24
23
22
21
16
3
Magnetics and LED resistors
are integrated into RJ-45
Chassis GND
(should cover part
of magnetics)
Y5A1
C6A9
4
25MHZ
C6A8
22PF
2
9
10
STACKED_RJ45_USB
1
J6A1
1
+V3.3_LAN
No Stuff
R6A5
ACTLED
SPDLED
LILED
Layout note:
Transmit/Receive pairs
need to be 50 ohms
Optional cap: C1 value
6pF - 12pF if needed for
magnetics
U6A1
RBIAS100
RBIAS10
VSS2
VSS3
VSS4
VSS5
VSS1
VSSP_2
VSSP_1
VSSA_2
VSSA2
VSSR1
VSSR2
18
18
18
18
18
18
18
39
42
45
44
43
37
35
34
C6A6
8
13
18
24
48
33
38
3
6
20
22
LAN_JCLK
VCC1
VCC2
VCCP_2
VCCP_1
VCCA_1
VCCA2
VCCT_1
VCCT_2
VCCT_3
VCCT_4
VCCR1
VCCR2
1
25
36
40
2
7
9
12
14
17
19
23
4.7UH
18
E
22PF
NO_STUFF
82562EM Testpoint Header
2
2
1
1
Title
Size
A
Date:
A
B
C
LAN Interface (82562EM)
Document Number
Project:
Friday, May 21, 2004
D
Sheet
30
Rev
of
E
46
A
B
C
D
E
4
4
5,6,8,9,11,16,18,20,21,23,26,33,34,35,36,38,39,40,41,44,48
+V3.3S
+V3.3S_FWH
R8H5
U8H1
R8W2
PCI_RST#_D
100
37
12
9
6 CLK_FWHPCI
R8W1
R8W7
R8W3
R8W4
R8W5
100
100
100
100
100
INIT#
RST#
CLK
FGPIO4
FGPIO3
FGPIO2
FGPIO1
FGPIO0
7
15
16
17
18
TP_FWH_ID3
TP_FWH_ID2
TP_FWH_ID1
TP_FWH_ID0
21
22
23
24
ID3
ID2
ID1
ID0
TP_FWH_RSVD2
TP_FWH_RSVD1
TP_FWH_RSVD5
TP_FWH_RSVD4
TP_FWH_RSVD3
32
33
34
35
36
RSVD2
RSVD1
RSVD5
RSVD4
RSVD3
29
30
40
GND2
GND1
GNDA
3
FGPI4
FGPI3
FGPI2
FGPI1
FGPI0
FWH
VPP
VCC2
VCC1
VCCA
11
10
31
39
TBL#
WP#
20
19
FWH4
FWH3
FWH2
FWH1
FWH0
38
28
27
26
25
IC
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
0.01_1%
C8W2
0.1UF
TBL# R8W8
WP# R8W6
C8W1
0.1UF
FWH_TBL# 19,37
FWH_WP# 19,37
LPC_FRAME# 19,32,33,34,37
LPC_AD3 19,32,33,34,37
LPC_AD2 19,32,33,34,37
LPC_AD1 19,32,33,34,37
LPC_AD0 19,32,33,34,37
IC
2
1
3
4
5
6
8
13
14
100
100
C8G4
10UF
3
TP_FWH_NC1
TP_FWH_NC2
TP_FWH_NC3
TP_FWH_NC4
TP_FWH_NC5
TP_FWH_NC6
TP_FWH_NC7
TP_FWH_NC8
2
18 FWH_INIT#
BUF_PCI_RST#
RP9B1B
10K
7
18,22,23,24,26,32,34,37
FWH SKT
2
2
1
1
FWH sits in the
FWH_TSOP_Socket,
Not on the board
A
B
C
Title
Size
A
Date:
Firmware Hub
Document Number
Project:
Friday, May 21, 2004
D
Sheet
31
Rev
of
E
46
+V3.3ALWAYS_KBC 33
SMC_XTAL
SMC_EXTAL
+V3.3ALWAYS
NO_STUFF_10K
SMC_RES#
SMC_STBY#
R8B4
39 VR_SHUT_DOWN#
3
33 SMC_INITCLK
R9A3
19,21,25,37,39 PM_PWROK
,44,48
0
Stuff R9A4 only for in-ckt
programming
+V3.3ALWAYS
36,37,44 SMB_SB_CLK
36,37,44 SMB_SB_DATA
37 SMB_SC_INT#
36,37,44 SMB_SB_ALRT#
P91/IRQ1#
R9A4
NO_STUFF_10K
7 LIDON
10K
2
RP9A1B
SMC_LID
VIRTUAL_BATTERY
2
3
SPDT_SLIDE
LID
SWITCH
37,44 SMC_ONOFF#
SW9A1
2
1
R8B5 VR_SHUTDOWN_R
NMI_GATE#
0
19,20,37,38,43,44 PM_SLP_S4#
37,44 AC_PRESENT#
J9A3
24,36,37 DOCK_INTR#
1
J9A3
Default Open
BT_WAKE
KSC_P76
KBC_DISABLE#
BT_ON
38,39,44,48
2
+V3.3ALWAYS
R8A210K
18,30
19,37
37,39,40,42
37
19,21,25,37,39
19,21,37
5,19,21,37
48
18,37
37
VBATTON 1
SW8A1
2
3
SPDT_SLIDE
2
VIRTUAL
BATTERY
J9A1
4
RP9A1D
5
10K
1
33 +V3.3ALWAYS_KBC
5,37
5,37
19,36,37
19,34,36,37
19,36,37
36,37
PM_LANPWROK
PM_PWRBTN#
VR_ON
FAN_ON
PM_PWROK
PM_RSMRST#
PM_THRM#
SMC_SHUTDOWN
H_RCIN#
SMC_RSTGATE#
SMB_THRM_CLK
SMB_THRM_DATA
SMC_RUNTIME_SCI#
SMC_EXTSMI#
SMC_WAKE_SCI#
KBC_A20GATE
37 BAT_SUSPEND
19,36,37 PM_BATLOW#
BT_DETACH
SMC_PROG_RST#
SMC_MD
KSC_RES0
PA3/CIN11/KIN11#/PS2AD
PA2/CIN10/KIN10#/PS2AC
30
31
KBC_MOUSE_DATA 36
KBC_MOUSE_CLK 36
5
6
MD1
MD0
2
3
XTAL
EXTAL
PA5/CIN13/KIN13#/PS2BD
PA4/CIN12/KIN12#/PS2BC
P95/CS1#
P94/IOW#
P93/IOR#
20
21
18
19
22
KBC_CAPSLOCK
KBC_SCROLLOCK
KBC_NUMLOCK
1
8
7
RES#
STBY#
NMI
P60/FTCI/CIN0/KIN0#
P61/FTOA/CIN1/KIN1#
P62/FTIA/CIN2/KIN2#/TMIY
P63/FTIB/CIN3/KIN3#
P64/FTIC/CIN4/KIN4#
P65/FTID/CIN5/KIN5#
P66/FTOB/CIN6/KIN6#/IRQ6#
P67/CIN7/KIN7#/IRQ7#
26
27
28
29
32
33
34
35
KBC_SCANIN0
KBC_SCANIN1
KBC_SCANIN2
KBC_SCANIN3
KBC_SCANIN4
KBC_SCANIN5
KBC_SCANIN6
KBC_SCANIN7
P27/PW15
P26/PW14
P25/PW13
P24/PW12
P23/PW11
P22/PW10
P21/PW9
P20/PW8
P17/PW7
P16/PW6
P15/PW5
P14/PW4
P13/PW3
P12/PW2
P11/PW1
P10/PW0
60
61
62
63
64
65
66
67
72
73
74
75
76
77
78
79
KBC_SCANOUT15
KBC_SCANOUT14
KBC_SCANOUT13
KBC_SCANOUT12
KBC_SCANOUT11
KBC_SCANOUT10
KBC_SCANOUT9
KBC_SCANOUT8
KBC_SCANOUT7
KBC_SCANOUT6
KBC_SCANOUT5
KBC_SCANOUT4
KBC_SCANOUT3
KBC_SCANOUT2
KBC_SCANOUT1
KBC_SCANOUT0
P30/HDB0/LAD0
P31/HDB1/LAD1
P32/HDB2/LAD2
P33/HDB3/LAD3
P34/HDB4/LFRAME#
P35/HDB5/LRESET#
P36/HDB6/LCLK
P37/HDB7/SERIRQ
P82/CLKRUN#
P83/LPCPD#
82
83
84
85
86
87
88
89
95
96
P85/IRQ4#
P86/IRQ5#/SCL1
P42/TMRI0/SDA1
98
99
51
VSS1
VSS2
VSS3
VSS4
AVSS
15
70
71
92
46
P51/RxD0
P50/TxD0
P52/SCK0/SCL0
P97/SDA0
P96/0/EXCL
P92/IRQ0#
P91/IRQ1#
P90/IRQ2#/ADTRG#
38
39
40
41
42
43
44
45
47
48
49
50
52
53
54
55
56
68
69
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6/DA0
P77/AN7/DA1
PA1/CIN9/KIN9#
PA0/CIN8/KIN8#
P40/TMCI0
P41/TMO0
P43/TMCI1/HIRQ11
P44/TMO1/HIRQ1
P45/TMR11/HIRQ12
P46/PWX0
P47/PWX1
PB5/WUE5#
PB4/WUE4#
80
81
90
91
93
94
PB3/CS4#/WUE3#
PB2/CS3#/WUE2#
PB1/HIRQ4/WUE1#/LSCI
PB0/HIRQ3/WUE0#/LSMI#
P80/HA0/PME#
P81/CS2#/GA20
57
58
PB7/WUE7#
PB6/WUE6#
97
P84/IRQ3#
100
H8S/2149F-Z
RESO#
KBC_KB_DATA 36
KBC_KB_CLK 36
1
KBC_SCANIN[7:0]
3
Q9A1
BSS138
36
Bluetooth Sideband
+V3.3ALWAYS
5,15,19,20,21,22,23,27,28,29,3
J9B2
BT_WAKE
BT_ON
BT_DETACH
SMB_SB_CLK
SMB_SB_DATA
C9M1
C9M2
0.1UF
10UF
1
2
3
4
5
6
7
8
8Pin_HDR
15,18,19,20,23,27,30,35,37,38,39,43,44
+V3.3
J9A4
Measurement Point
RP8C1D
10K
3
2
BUF_PCI_RST#
Q9B3
BSS138
SMC_RSTGATE#
1
GATE OFF PCIRST# during S3
Testpoint Header
J8B1
SMB_SC_INT#
VR_SHUTDOWN_R 2
KBC_A20GATE
Note: for flash progamming, must use
TX1 and RX1, which are pin97 and
pin98.
B
J9A2
1
KSC_RES0
1
NMI_GATE#
3
2 KSC_P76
CON3_HDR
C
Title
Size
A
Date:
2
PM_SLP_S3# 15,19,25,37,38,43,44
SCL1
SDA1
15,22,23,37 PCI_GATED_RST#
KSC Testpoint Header
CON14_RECEPT
A
Q9B1
BSS138
1
KBC_SCANOUT[15:0] 36
LPC_AD0 19,31,33,34,37
LPC_AD1 19,31,33,34,37
LPC_AD2 19,31,33,34,37
LPC_AD3 19,31,33,34,37
LPC_FRAME# 19,31,33,34,37
BUF_PCI_RST# 18,22,23,24,26,31,34,37
CLK_SMCPCI 6
INT_SERIRQ 18,22,23,24,34,37
PM_CLKRUN# 19,21,22,23,24,34,37
PM_SUS_STAT# 15,19,34,37
RP8C1C
10K
2
4
6
8
10
12
14
Q9B2
BSS138
1
3
RP8C1B
10K
J8C1
1
3
5
7
9
11
13
6
BT_DETACH
7
RP8C1A
10K
8
1
2
1
+V3.3ALWAYS
5,15,19,20,21,22,23,27,28,29,36,37,38,39,44,48
Hardware
+V3.3ALWAYS_KBC 33
Programming
Interface
KBC_GP_DATA 36
KBC_GP_CLK 36
13
14
12
16
17
23
24
25
4
2
3
,44,48
SMC_MD
CON3_HDR
10
11
2
2
3
PA7/CIN15/KIN15#/PS2CD
PA6/CIN14/KIN14/PS2CC
3 LED_CAPS
1
5
74AHC1G08
R8A3
240
2
2
VCC
VCL
VCCB
AVREF
AVCC
4
SMC_PROG_RST#
RST_HDR 1
4
5
1
5
SMC_RST#
59
9
4
36
37
R8B1
240
P90-P92 needs to be at VCC for boot mode programming. They are
already pulled up in the design. MD0, MD1 needs to be at Vss.
Jumper for J9B1 needs to be populated. System needs to supply
DS8B1
DS8A2
DS8A1
GREEN
GREEN
GREEN
+V3ALWAYS to flash connector.
U9B1
J8A2
6
33
0.1UF
2
Shunt to program only
if using hardware
programmer
+V3.3ALWAYS_KBC 33
RP9B1C RP9B1D
10K
10K
+V3.3ALWAYS_KBC
R8B3
240
2
C8A7
U8A2
4
3
+V3.3ALWAYS_KBC 33
33
Boot Mode Programming Straps
J9B1
1
J9A1
No Shunt (Default)
Shunt
2 LEDD3
C9B1
18PF
Decode KBC Addresses
Enable 60h & 64h
Disable
1
0.1UF
LED_NUM
C9N1
0.1UF
3
C9N4
0.1UF
1
C9N3
0.1UF
2
10MHZ
C9B2
18PF
4
C9N2
22UF
1
1
C9A1
J8A2
1-2 (Default)
2-3
LED_SCROLL
0.01_1%
Y9B1
E
KSC
Enable
Disable
3
R9A1
D
+V3.3ALWAYS_KBC
2 LEDD2
C
33
1
B
+V3.3ALWAYS
5,15,19,20,21,22,23,27,28,29,36,37,38,39,44,48
2 LEDD1
A
Keyboard and System Management Controller (KSC)
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
32
E
46
A
B
C
D
E
KSC SUSPEND TIMER
32
32
+V3.3ALWAYS_SMCRST
R7A1
32
+V3.3ALWAYS_KBC
0
R8A4
1M
R7A2
7
7
U7A4C
74HC04
8
C8B1
7
4.7uF
SMC_INITCLK 32
4
U7A4D
74HC04
SMC_INIT_CLK4
U7A4A
74HC04
2
4.7K
J8A1
1
1
19 KSC_VPPEN#
2
SMC_RST# 32
R8B2
100K
NMI Jumper: Shunt J8A1
for KSC Hardware or
Software Programming
Q8A1
BSS138
1
MAX809
Q8B1
BSS138
SMC_RST 1
2
SMC_INIT_CLK3 9
6
U7A4B
74HC04
3
1
2
SMC_RST#_D
2
7
14
SMC_INIT_CLK2 5
4
14
RST#
14
SMC_INIT_CLK1 3
3
0.1UF
3
GND
14
C8A5
U7A2
VCC
4
+V3.3ALWAYS_KBC
+V3.3ALWAYS_KBC
Circuitry provides an interrupt to the KSC every
1s while in suspend (this allows the KSC to
complete housekeeping functions while
suspended)
32
1Hz Clock
Disable
Enable
J8A1
Shunt (Default)
No Shunt
R7B1
+V3.3ALWAYS_KBC
14
0 INVD1
11
10
32
TP_INVD1
R7A3
+V3.3ALWAYS_KBC
14
0 INVD2
13
12
U7A4E
74HC04
7
3
7
TP_INVD2
U7A4F
74HC04
3
Spare gates
PORT 80-83 DISPLAY
5,6,8,9,11,16,18,20,21,23,26,31,34,35,36,38,39,40,41,44,48
5,6,8,9,11,16,18,20,21,23,26,31,34,35,36,38,39,40,41,44,48
+V3.3S
Port
82-83
80-81
+V3.3S
CR9G1
CR9G2
CT_COM
LED_SEGA
LED_SEGB
LED_SEGC
LED_SEGD
LED_SEGE
LED_SEGF
LED_SEGG
7
9
7-SEG-LED-DISPLAY
High Nibble (Left)
1
10
8
5
4
2
3
A
B
C
D
E
F
G
1
10
8
5
4
2
3
A
B
C
D
E
F
G
LED_SEGDP
CT_DP
7
7SEG_LED_CT2
CT_COM
9
Low Nibble (Right)
AN_DP
6
CT_DP
7
CT_COM
9
7-SEG-LED-DISPLAY
High Nibble (Left)
RP8H5D 4
RP8H5C 3
RP8H5B 2
RP8H4D 4
RP8H4B 2
RP8H4C 3
RP8H4A 1
RP8H5A 1
150
150
150
150
150
150
150
150
5LED_SEGA
6LED_SEGB
7LED_SEGC
5LED_SEGD
7LED_SEGE
6LED_SEGF
8LED_SEGG
8LED_SEGDP
LED_SEGA 1
LED_SEGB 10
LED_SEGC 8
LED_SEGD 5
LED_SEGE 4
LED_SEGF 2
LED_SEGG 3
6 CLK_PCI_PORT80
7,8,10,18 PCI_RST#
PORT 81, 83
CR9H1
LED_SEGDP
OE#_PORT80
LED_SEGDP
AN_DP 6
5,6,8,9,11,16,18,20,21,23,26,31,34,35,36,38,39,40,41,44,48
A
B
C
D
E
F
G
U9H1
9
17
29
41
CT_DP
7
CT_COM
9
37
39
38
40
+V3.3S
R9W1
100
R8J13
7SEG_LED_CT3
LED_SEGA
LED_SEGB
LED_SEGC
LED_SEGD
LED_SEGE
LED_SEGF
LED_SEGG
6
7-SEG-LED-DISPLAY
CR9H2
2
AN_DP
1K
SUS_CLK_Q
7-SEG-LED-DISPLAY
Low Nibble (Right)
7SEG_LED_CT4
19,37
5,6,8,9,11,16,18,20,21,23,26,31,34,35,36,38,39,40,41,44,48
SUS_CLK
Q8J4
BSS138
1
+V3.3S
4
16
24
36
IO32
IO31
IO30
IO29
IO28
IO27
TDO/IO26
IO25
IO24
IO23
GCLK1
IO22
GCLR#
TCK/IO21
IO20
IO19
OE1
OE2/GCLK2 IO18
IO17
IO16
IO15
IO14
IO13
IO12
IO11
IO10
IO9
IO8
IO7
TMS/IO6
IO5
GND1
IO4
GND2
IO3
GND3
IO2
GND4 TDI/IO1
VCC1
VCC2
VCC3
VCC4
44
43
42
35
34
33
32
31
30
28
27
26
25
23
22
21
20
19
18
15
14
13
12
11
10
8
7
6
5
3
2
1
LPC_FRAME# 19,31,32,34,37
PORT82_EN#
2
CT_DP
PORT 80, 82
LED_SEGDP
6
J9H1
R9W2
PLD_PD
1
AN_DP
3
A
B
C
D
E
F
G
2
1
10
8
5
4
2
3
7SEG_LED_CT1
LED_SEGA
LED_SEGB
LED_SEGC
LED_SEGD
LED_SEGE
LED_SEGF
LED_SEGG
J9H1
Shunt
No Shunt (Default)
10K
LED_MUX_HI81
LED_MUX_LO81
LED_MUX_HI80
LED_MUX_LO80
2
LED_SEGA
LED_SEGB
LED_SEGC
LED_SEGD
LED_SEGE
LED_SEGF
LED_SEGG
LED_SEGDP
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
19,31,32,34,37
19,31,32,34,37
19,31,32,34,37
19,31,32,34,37
EPM7064STC
3
1
1
3
Q9H1
2N3904
2
LED_MUX_HI81
LED_MUX_HI80
LED_MUX_LO81
LED_MUX_LO80
RP9H1A 1
RP9H1B 2
RP9H1C 3
RP9H1D 4
A
150
150
150
150
8
7
6
5
1
Q8H3
2N3904
2
3
1
Q8H4
2N3904
3
Q8J1
2N3904
1
2
C9W1
0.1UF
C9W3
0.1UF
C9W4
0.1UF
C9W2
0.1UF
C9H1
10UF
1
2
Title
LED_MUX_HI81_D
LED_MUX_HI80_D
LED_MUX_LO81_D
LED_MUX_LO80_D
Size
A
Date:
B
C9Y1
0.1UF
C
KSC Suspend Timer and Port 80 LEDs
Document Number
Project:
Friday, May 21, 2004
D
Sheet
33
Rev
of
E
46
A
B
C
D
E
BUF_PCI_RST# 18,22,23,24,26,31,32,37
2 SIO_RST#
SIO
Enable
Disable
3
CON3_HDR
+V3.3S_SIO
J9G2
1-2 (Default)
2-3
1
+V3.3S_SIO
RP8G1A 1
8 10K
2
3
2
1
100
99
98
97
96
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO20
GPIO21
GPIO22
GPIO23
GPIO24
95
94
93
92
91
81
80
79
78
77
76
75
74
GPIO26
GPIO27
87
86
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO30
GPIO31
GPIO32
GPIO33
GPIO34
85
84
83
82
5
NC
65
GPIOs
SER_DCDA# 35
SER_DSRA# 35
SER_SINA 35
SER_RTSA# 35
SER_SOUTA 35
SER_CTSA# 35
SER_DTRA# 35
SER_RIA# 35
XCNF1/XWR# RP8G1C 6
R8F1
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0
2 RP7F5B
3 RP7F5C
4 RP7F5D
1 RP7F7A
4
90
RP7F6C
RP7F6B
RP7F6A
RP7F3D
4
1
C8F4
1
C8F5
PPT_SLCT 35
PPT_PE 35
330PF
PPT_BUSY/WAIT# 35 2
PPT_ACK# 35
100
100
7
6
5
8
XCNF1/XWR#
XCNF2
FDC
EV_GPIO_0
EV_GPIO_1
33
33
1K
1K
1K
1K
Straps
Parallel
Port
IR
35 FLP_DSKCHG#
35 FLP_HDSEL#
35 FLP_RDATA#
35
FLP_WP#
35
FLP_TRK0#
35 FLP_WGATE#
35 FLP_WDATA#
35 FLP_STEP#
35
FLP_DIR#
35
FLP_DR0#
35 FLP_MTR0#
35 FLP_INDEX#
35 FLP_DENSEL#
35 FLP_DRATE0
R7F7
R7F6
BUSY/WAIT#
ACK#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
2 RP7F7B
3 RP7F7C
4 RP7F7D
1 RP7F5A
55
56
57
58
59
60
61
62
PWR &
GND
DCD1#
DSR1#
SIN1
RTS1#
SOUT1/XCNF0
CTS1#
DTR1#
RI1#
3
R8F3
R8F2
AFD#/DSTRB#
STB#/WRITE#
PPT_SLIN#/ASTRB# 35
PPT_INIT# 35
PPT_ERR# 35
PPT_AFD#/DSTRB# 35
PPT_STB#/WRITE# 35
7
6
5
8
DSKCHG#
HDSEL#
RDATA#
WP#
TRK0#
WGATE#
WDATA#
STEP#
DIR#
DR0#
MTR0#
INDEX#
DENSEL
DRATE0
DR1#
MTR1#
35
36
37
40
41
42
43
44
45
46
48
50
52
7
21
22
23
24
25
26
27
28
29
30
31
32
33
34
72
73
PNF
SLCT
PE
BUSY/WAIT#
ACK#
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
2 RP7F1B
4.7K
IR_TXD
IRRX1
IRRX2_IRSL0
IRSL1
IRSL2A/DR1B/XIORDB
IRSL3/PWUREQ
IRTX
8
35
69
68
67
71
66
70
1 RP7F1A
4.7K
IR_RXD
IR_SEL
IR_MD0
IR_MD1
R8F4
4.7K
35
35
35
35
Clock
3 RP7F1C 6
4.7K
CLKIN
4 RP7F1D 5
4.7K
20
3 RP7F8C 6
4.7K
CLK_SIO14
47
49
51
53
54
4 RP7F8D 5
4.7K
6
SLIN#/ASTRB#
INIT#
ERR#
AFD#/DSTRB#
STB#/WRITE#
7
SERIRQ
SMI#
LPCPD#
CLKRUN#
14
39
63
88
13
38
64
89
8
10
19
7
6
VDD1
VDD2
VDD3
VDD4
VSS5
VSS6
VSS7
VSS8
1 RP7F8A
4.7K
2 RP7F8B
4.7K
18,22,23,24,32,37 INT_SERIRQ
19,32,36,37 SMC_EXTSMI#
15,19,32,37 PM_SUS_STAT#
19,21,22,23,24,32,37 PM_CLKRUN#
Bus
Interface
LAD0
LAD1
LAD2
LAD3
LCLK
LDRQ#
LFRAME#
LRESET#
Serial
Port
+V5S_DIODE
15
16
17
18
8
11
12
9
19,31,32,33,37 LPC_AD0
19,31,32,33,37 LPC_AD1
19,31,32,33,37 LPC_AD2
19,31,32,33,37 LPC_AD3
6
CLK_SIOPCI
19 SIO_DRQ#0
19,31,32,33,37 LPC_FRAME#
3
CR7G1
BAR43
U8F1
4
8,15,16,17,18,20,23,24,25,27,35,39,40,44,47
1K
1K
1K
1K
1
+V5S
PPT_PNF# 35
J9G2
330PF
2
3
2
1
4
33
33
33
33
6
7
8
5
PPT_PD7
PPT_PD6
PPT_PD5
PPT_PD4
35
35
35
35
RP7F3C 3
RP7F3B 2
RP7F3A 1
R8U1
33
33
33
6
7
8
33
PPT_PD3
PPT_PD2
PPT_PD1
PPT_PD0
35
35
35
35
3
1
1
C7F5 C7F4 C8F6 C8U1
1
680PF 680PF 330PF 330PF C8U2
2
2
330PF
2
10K
3
10K
1
1
1
1
1
C8U3 C7F1 C7F2 C8U4 C7F3
330PF 330PF 330PF 330PF 330PF
2
2
2
2
2
39,40
39,40
39,40
39,40
39,40
2
DET_1.2V#
IDE_SPWR_EN# 27,37
LVDS_BKLTSEL0 16
LVDS_BKLTSEL1 16
5,6,8,9,11,16,18,20,21,23,26,31,33,35,36,38,39,40,41,44,48
+V3.3S
+V3.3S_SIO
PC87393
+V3.3S_SIO
+V3.3S_SIO
R8G7
+V3.3S_SIO
EV GPIO Strapping options
0.01_1%
R8G4
NO_STUFF_4.7K
R8U3
NO_STUFF_10K_1%
R8G3
NO_STUFF_4.7K
C8U6
C8U5
C8F2
0.1UF
0.1UF
22UF
1
1
DET_1.2V#
EV_GPIO_1
1
1
EV_GPIO_0
R8G1
NO_STUFF_470
A
R8U2
10K_1%
Title
GMCH core
voltage detection
Default: Pulled to GND
2
<NO_STUFF>
2
R8G2
NO_STUFF_470
B
C
Size
A
Date:
Super I/O Controller
Project:
Document Number
Friday, May 21, 2004
D
Sheet
34
Rev
of
E
56
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
7
9
11
13
15
17
19
21
23
25
27
29
31
33
C
D
PARALLEL PORT
J2A1A
7
5
8
7
60OHM@100MHZ
PPT_L_PE
FB2A2B
PPT_L_BUSY/WAIT#
FB2A2D
FB2A1A
PPT_L_ACK#
FB2A1B
PPT_L_PD7
3
4
1
2
6
5
8
7
60OHM@100MHZ
FB2A1C
FB2A1D
FB3A4A
FB3A4B
3
4
1
2
6
5
8
7
60OHM@100MHZ
FB3A4C PPT_L_SLIN#
FB3A4D PPT_L_PD2
FB3A6A PPT_L_INIT#
FB3A6B PPT_L_PD1
6
5
8
5
60OHM@100MHZ
FB3A6C PPT_L_ERR#
FB3A6D PPT_L_PD0
FB3A5A PPT_L_AFD#/DSTRB#
FB3A5D PPT_L_STB#/WRITE#
2
4
1
2
34 PPT_PE
34 PPT_BUSY/WAIT#
34 PPT_ACK#
34 PPT_PD7
E
60OHM@100MHZ
PPT_L_PNF#
6 FB2A2C
PPT_L_SLCT
8 FB2A2A
3
1
34 PPT_PNF#
34 PPT_SLCT
6 RP3H1C
1K
1
3
8 RP3H1A 1
1K
J4H1
4
6 RP3H2C
1K
FLOPPY CONNECTOR
7 RP3H1B 2
1K
+V5S
3
8,15,16,17,18,20,23,24,25,27,34,39,40,44,47
3
B
8 RP3H2A 1
1K
A
13
25
12
24
11
23
10
22
9
21
8
20
7
19
6
18
5
17
4
16
3
15
2
14
1
FLP_DENSEL# 34
FLP_DRATE0 34
FLP_INDEX# 34
FLP_MTR0# 34
PPT_L_PD6
FLP_DR0# 34
34
34
34
34
FLP_DIR# 34
FLP_STEP# 34
FLP_WDATA# 34
FLP_WGATE# 34
FLP_TRK0# 34
FLP_WP# 34
FLP_RDATA# 34
FLP_HDSEL# 34
FLP_DSKCHG# 34
PPT_PD6
PPT_PD5
PPT_PD4
PPT_PD3
34 PPT_SLIN#/ASTRB#
34 PPT_PD2
34 PPT_INIT#
34 PPT_PD1
17x2_HDR
PPT_L_PD5
PPT_L_PD4
PPT_L_PD3
4
CONN,MISC,49P,D-SUB,3-IN-1
3
3
4
1
4
34 PPT_ERR#
34 PPT_PD0
34 PPT_AFD#/DSTRB#
34 PPT_STB#/WRITE#
5,6,8,9,11,16,18,20,21,23,26,31,33,34,36,38,39,40,41,44,48
3
INFRARED PORT
+V3.3S
+V3.3S_IR
19,21,37
PM_RI#
3
2
Q8H2
BSS138
2
1
,48
C8A3
0.1UF
C8M1
22UF
0.1UF
U8A1
SERBUF_C1+ 28
SER_EN
V+
27
34
34
IR_TXD
IR_RXD
34
34
34
IR_MD1
IR_MD0
IR_SEL
SERBUF_C1- 24
C8A4
SERBUF_C2-
2
SER_RIA
34 SER_CTSA#
34
SER_RIA#
34 SER_SINA
34 SER_DSRA#
34 SER_DCDA#
20
19
18
17
16
15
34 SER_DTRA#
34 SER_SOUTA
34 SER_RTSA#
14
13
12
T1IN
T2IN
T3IN
23
22
21
FORCEON
FORCEOFF#
INVALID#
C7A3
0.1UF
SER_ON
C7M2
LEDA
TXD
RXD
GND
NC
MOD1
MOD0
FIR_SEL
AGND
VDD
MNT
11
2
NO_STUFF_HSDL-3600#017
0.1UF
C1-
1
U7A1
10
9
8
7
6
5
4
3
2
1
SERBUF_V+
C7M1
SERBUF_C2+
R8A1 1K
19
C1+
26
C8A1
+V3.3S
1
R7M1
NO_STUFF_2.2
15,18,19,20,23,27,30,32,37,38,39,43,44
VCC
+V3.3
NO_STUFF_0.1UF NO_STUFF_10UF
C2+
V-
SERBUF_V-
3
C7A1
Caps must be placed
as close as possible to
pins 1,2
0.1UF
C2R2OUTB
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
R1IN
R2IN
R3IN
R4IN
R5IN
T1OUT
T2OUT
T3OUT
GND
4
5
6
7
8
SERIAL PORT
SERBUF_CTSA
SERBUF_RIA
SERBUF_SINA#
SERBUF_DSRA
SERBUF_DCDA
1
4
3
4
9 SERBUF_DTRA
10 SERBUF_SOUTA#
11 SERBUF_RTSA
25
3
1
2
2
8
5
6
5
6
8
7
7
60OHM@100MHZ
SERPRT_DCDA
FB1A1A
SERPRT_DSRA
FB1A3D
SERPRT_SINA#
FB1A3C
SERPRT_RTSA
FB1A1D
60OHM@100MHZ
FB1A1C SERPRT_SOUTA#
FB1A3A SERPRT_CTSA
FB1A1B SERPRT_DTRA
FB1A3B SERPRT_RIA
J2A1B
26
31
27
32
28
33
29
34
30
50
51
52
53
54
55
1
CONN,MISC,49P,D-SUB,3-IN-1
MAX3243
R2OUTB is enabled even in suspend.
SER_RIA# is routed to allow the system to
wake up in Suspend To RAM.
R8M1
1K
Size
A
Date:
Note: FORCEOFF# overrides FORCEON.
A
B
Title
C
Floppy, Parallel, Serial, and IR Ports
Document Number
Project:
Friday, May 21, 2004
D
Sheet
35
Rev
of
E
46
A
B
C
D
E
+V5_PS2
KBC_SCANOUT[15:0]
32
CBTD has integrated
diode for 5V to 3.3V
voltage translation
J9D1
4
KBC_SCANOUT0
KBC_SCANOUT2
KBC_SCANOUT4
KBC_SCANOUT6
KBC_SCANOUT8
KBC_SCANOUT10
KBC_SCANOUT12
KBC_SCANOUT14
KBC_SCANIN0
KBC_SCANIN2
KBC_SCANIN4
KBC_SCANIN6
1
3
5
7
9
11
13
15
2
4
6
8
10
12
14
16
17
19
21
23
18
20
22
24
KBC_SCANOUT1
KBC_SCANOUT3
KBC_SCANOUT5
KBC_SCANOUT7
KBC_SCANOUT9
KBC_SCANOUT11
KBC_SCANOUT13
KBC_SCANOUT15
U8A3
32
32
32
32
32
KBC_SCANIN1
KBC_SCANIN3
KBC_SCANIN5
KBC_SCANIN7
KBC_GP_DATA
KBC_GP_CLK
KBC_MOUSE_DATA
KBC_MOUSE_CLK
KBC_KB_DATA
32 KBC_KB_CLK
18 H_A20GATE
NO_STUFF_24Pin_ZIF-HDR
OE#_PS2
Scan Matrix Key Board
KBC_SCANIN[7:0]
+V5_PS2
C8A6
0.1UF
3
4
7
8
11
1A1
1A2
1A3
1A4
1A5
14
17
18
21
22
2A1
2A2
2A3
2A4
2A5
1
13
1OE#
2OE#
32
4
VCC
24
1B1
1B2
1B3
1B4
1B5
2
5
6
9
10
GP_DATA
GP_CLK
MOUSE_DATA
MOUSE_CLK
KBD_DATA
2B1
2B2
2B3
2B4
2B5
15
16
19
20
23
KBD_CLK
GND
12
KBC_A20GATE 32,37
+V3.3S
SN74CBTD3384
3 RP8G2C 6
8.2K
R8A5
100
+V5_PS2
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,38,39,40,41,44,48
RP1A1A
4.7K
RP8G1D
RP8H6A
RP8H6B
RP8H6D
RP8H7A
RP9G1B
RP9G1C
F1A1
1.1A
4
5
+V5_PS2
CP1A1D
47PF
1
PS2_PWR_L +1
FB1M4
60ohm@100MHz
1
2
8
GP_CLK
+V3.3ALWAYS
RP1B1A
4.7K
4
1
2
4
1
2
3
10K
10K
10K
10K
10K
10K
10K
R9A2
FB1M3
60ohm@100MHz
1
2
1
FB1A2
31Ohm@100MHz
L_GPDATA
5
8
7
5
8
7
6
3
SMC_EXTSMI# 19,32,34,37
SMC_RUNTIME_SCI# 19,32,37
SMC_WAKE_SCI# 19,32,37
PM_BATLOW# 19,32,37
SMB_SB_DATA 32,37,44
SMB_SB_CLK 32,37,44
SMB_SB_ALRT# 32,37,44
10K
DOCK_INTR# 24,32,37
8
3
2
1
5,15,19,20,21,22,23,27,28,29,32,37,38,39,44,48
GP_DATA
2
+V5_PS2
+V5_PS2
C1A3
2
L_PS2_PWR
47pF
4
KBD_CLK
5
2
7
RP1B1B
4.7K
+V5_PS2
+V5
6 4 2
L_KBD_CLK
1
5
47PF
R1B3
C1A4
47pF
16
17
12
+V5_PS2
8
11
2
FB1M1
60ohm@100MHz
2
3
8
6
B
C
0.1UF
1
MOUSE_DATA
1
CP1A1C
47PF
Title
Size
A
Date:
A
C1A2
22UF
If a PS/2 "breakout" connector is used,the keyboard PS/2
connector can be used for both a PS/2 keyboard and a
second PS/2 mouse. Otherwise, the keyboard PS/2
connector will only support a PS/2 keyboard.
RP1A1B
4.7K
1
C1A1
7
6
FB1M6
60ohm@100MHz
1
2
MOUSE_CLK
CP1A1A
47PF
DUAL_PS2
L_MOUSE_DATA
3
RP1B1C
4.7K
+V5_PS2
7
9
L_MOUSE_CLK
+V5_PS2
2
0.01_1%
KBD_DATA
3
13
14
15
CP1A1B
FB1M2
60ohm@100MHz
L_KBD_DATA 1
2
10
1
20,21,22,23,27,37,43,44
J1A1
L_GPCLK
7
2
RP1B1D
4.7K
FB1M5
60ohm@100MHz
1
2
Keyboard and Mouse Connectors
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
36
E
46
A
B
15,17,23,27,38,44 +V12S
C
D
J3H2
LPC POWERED ON SUSPEND RAIL FOR ADD-IN H8 CARD
LPC Debug Slot
15,17,23,27,38,44 +V12S
J8F1
19,33
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
SUS_CLK
0,21,22,23,27,28,29,32,36,38,39,44,48
+V3.3ALWAYS
18,32 H_RCIN#
32,36 KBC_A20GATE
19,32,34,36 SMC_EXTSMI#
12V1
12V2 A1
SUSCLK
NEG_12V A2
GND1
GND2 A3
LREQ
BP_CLK A4
VCC3_1
VCC3_2 A5
LCNTL0
LCNTL1 A6
GND3
GND5 A7
LDC
LD6 A8
LD5
LD4 A9
GND4
GND7 A10
+V5_LPCSLOT
LD3
LD2 A11
LD0 A12
LD1
A13
VCC5_2
GND6
SCLK A14
3V_STBY
GND10 A15
LPS
INT_SERIRQ 18,22,23,24,32,34
SERIRQ A16
KBRESTE#
PM_CLKRUN# 19,21,22,23,24,32,34
CLKRUN# A17
A20GATE#
A18
GND8
GND12
5,15,19,20,21,22,23,27,28,29,32,36,38,39,44,48
+V3.3ALWAYS
LSMI#
LINK_ON A19
+V5_LPCSLOT
3
KEY
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
19 LPC_DRQ#1
19,31,32,33,34 LPC_FRAME#
19,31,32,33,34 LPC_AD2
19,31,32,33,34 LPC_AD0
6 CLK_LPC14
1
3
5
7
9
11
13
15
4,18 H_PWRGD
18,21 SM_INTRUDER#
19,21,35 PM_RI#
3,7,18 H_DPSLP#
18,21 SMB_ALERT#
3,18
H_NMI
3,18
H_SMI#
+V3.3_LPCSLOT
+V3.3_LPCSLOT
4
E
20,21,
R4169_D
R3H3
H_STPCLK# 3,18
1K
H_CPUSLP# 3,18
4
20,21
+V3.3ALWAYS_ICH
19,20,21,22,24 +V3.3S_ICH
R7J3
R7J4
10K
4.7K
J7J1
19
1
3
5
7
9
ICH_GPIO7
18,21,22,23 INT_PIRQH#
19 ICH_MFG_MODE
15,18,22,23 PCI_PME#
2
4
6
8
10
IDE_PATADET 19,26
IDE_SATADET 19,26
2X5-Header
ICH4-M Testpoint Header
10K
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
VCC5_3
LDRQ0#
GND14
LAD3
LAD1
GND15
PCICLK
LPCPD#
GND16
PME#
VCC3_4
H_INIT#
3,18
+V5
H_INTR
3,18
BUF_PCI_RST# 18,22,23,24,26,31,32,34
2X8_HDR
R8G6
VCC5_1
LDRQ1#
LFRAME1#
GND9
LAD2
LAD0
GND11
PCIRST#
GND13
OSC
VCC3_3
2
4
6
8
10
12
14
16
J9J1
LPC_DRQ#0 19
6,19,39,40
6,19,38,44
15,19
3,19
39
LPC_AD3 19,31,32,33,34
LPC_AD1 19,31,32,33,34
CLK_LPCPCI 6
PM_SUS_STAT# 15,19,32,34
1
3
5
7
9
11
13
15
PM_STPCPU#
PM_SLP_S1#
PM_C3_STAT#
PM_CPUPERF#
VR_PWRGD
PCI_PME# 15,18,22,23
2
4
6
8
10
12
14
16
PM_STPPCI# 6,19
INT_IRQ14 18,21,26
INT_IRQ15 18,21,26
AGP_SUSPEND# 19
3
PM_CLKRUN# 19,21,22,23,24,32,34
PM_SLP_S4# 19,20,32,38,43,44
2X8_HDR
60Pin_CardCon
LPC_RST#
R9G3
NO_STUFF_0
15,22,23,32 PCI_GATED_RST#
J2J2
Layout Note:
Line up LPC slot
with PCI Slot 3
R9G4
0
1
3
5
7
27,34 IDE_SPWR_EN#
2
4
6
8
FWH_WP# 19,31
FWH_TBL# 19,31
8Pin HDR
SIO Sidebands
BUF_PCI_RST# 18,22,23,24,26,31,32,34
5,15,19,20,21,22,23,27,28,29,32,36,38,39,44,48
+V3.3ALWAYS
TEST HEADER
J9D2
2
5,19,21,32
19,32
32,44
32,39,40,42
19,21,25,32,39
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
PM_THRM#
PM_PWRBTN#
SMC_ONOFF#
VR_ON
PM_PWROK
19,21,32 PM_RSMRST#
32,44 AC_PRESENT#
15,19,25,32,38,43,44
PM_SLP_S3#
44,48 GATED_SMC_SHUTDOWN
32 BAT_SUSPEND
32 SMC_RSTGATE#
24,32,36 DOCK_INTR#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
SMC_RUNTIME_SCI# 19,32,36
SMC_WAKE_SCI# 19,32,36
R9D1
NO_STUFF_10K
J2J1
FAN_ON
32
1
3
5
7
19,32,34,36 SMC_EXTSMI#
19,38 PM_SLP_S5#
19,39,40 PM_DPRSLPVR
SMB_THRM_CLK 5,32
SMB_THRM_DATA 5,32
2
4
6
8
DELAYED_VR_PWRGD
PM_SUS_CLK 15,19
PM_GMUXSEL 19
2
19,41
8Pin HDR
R9D2
10K
SMB_SB_CLK 32,36,44
SMB_SB_DATA 32,36,44
SMB_SB_ALRT# 32,36,44
PM_BATLOW# 19,32,36
NO STUFF
GROUND
HEADERS
SMB_SC_INT# 32
15x2_HDR
J9J4
1
SMC Sidebands for LPC Power Management
J7E1
2
1
J7F3
2
1
2
1
J9J3
1
J1H7
2
1
2
1
J7A1
J2A2
2
1
2
1
J9E1
2
J1E2
2
1
1
20,21,22,23,27,36,43,44
+V5
+V5_LPCSLOT
R9G1
A
+V3.3
0.01_1%
15,18,19,20,23,27,30,32,35,38,39,43,44
+V3.3_LPCSLOT
R9G5
0.01_1%
C9G2
C9G1
C9G4
C8F1
C8F3
C9G3
Title
22UF
0.1UF
22UF
0.1UF
0.1UF
0.1UF
Size
A
Date:
B
C
LPC Slot & Debug Headers
Document Number
Project:
Friday, May 21, 2004
D
Sheet
37
Rev
of
E
46
A
B
C
D
E
Processor Fan Header
Test Caps
15,17,23,27,37,44 +V12S
TP_220pf1
4
TP_220pf2
4
1
2
3
C8J7
220PF
TP_330pf1
TP_330pf2
2
C9J4
330PF
1
2
3
1
J1E1
CON3_HDR
TP_0.1uf1
Test Caps backside
TP_BS_100pf1
TP_0.1uf2
C8J6
0.1UF
TP_BS_100pf2
TP_0.082uf2
TP_0.082uf1
C8J4
0.082uF
C9Y2 100pF
TP_BS_0.01uf1
TP_BS_0.01uf2
TP_0.47uf1
C9Y5
0.01UF
TP_BS_0.1uf2
C9Y3
0.1UF
TP_BS_0.1uf1
TP_0.47uf2
2
0.47uF
TP_0.01uf2
TP_0.01uf1
C9J2
0.01UF
TP_BS_220pf2
TP_BS_220pf1
3
1
C8J5
3
C9J1
220PF
C9J3
TP_BS_1000pF2
TP_BS_1000pF1
TP_0.1uf2
TP_0.1uf1
C9Y4
1000PF
0.1UF
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,39,40,41,44,48
+V3.3S
+V3.3S
2
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,39,40,41,44,48
15,18,19,20,23,27,30,32,35,37,39,43,44
1S4_LED_C 3
1
LED for S4
SO_LED_A2
2
DS1H1
LED for S0
DS1H3
LED for S1
GREEN
1
Q1G1
BSS138
1
6,19,37,44 PM_SLP_S1#
DS1H2
LED for S3
GREEN
2
2 S5_LED_A
2
DS2H2
DS2H1
2
GREEN
R2H2
68
R2H4
68
2 S4_LED_A
2
R2H3
68
R1H2
68
2 S1_LED_A 2
SI2307DS
1
1S5_LED_C 3
19,20,32,37,43,44 PM_SLP_S4#
LED for S5
1PM_SUSLEDPWR 3
Q2G2
SI2307DS
1
SI2307DS
1
2
2
Q2G6
19,37 PM_SLP_S5#
PM_SLP_S3#
1S1_LED_C 3
Q2G5
15,19,25,32,37,43,44
R1H1
68
SI2307DS
1
3 SO_LED_C 1
+V3.3ALWAYS
2
Q1G2
2 PM_SUSLED
2
23,27,28,29,32,36,37,39,44,48
+V3.3
6,19,37,44 PM_SLP_S1#
+V3.3ALWAYS
2
5,15,19,20,21,22,23,27,28,29,32,36,37,39,44,48
1
System State LEDs
GREEN
1
1
1
13
GREEN
Q2G3
BSS138
1
Title
Size
A
Date:
2
19,37 PM_SLP_S5#
A
B
C
Fan Circuit, Test Capacitors and System State LEDs
Document Number
Project:
Friday, May 21, 2004
D
Sheet
Rev
of
38
E
46
B
+V3.3ALWAYS
MAIN_PWROK
4
74AHC1G08
Step 2 - VR ON
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
0.1UF
1
4
C5B10
PM_PWROK 19,21,25,32,37
74AHC1G08
R5N9
2.2k
0.1UF
U5B3
1
VR_ON
2
DELAYED_VIDPWRGD
32,37,40,42
40
3
C5N3
0.1UF
14
U4B3A
1
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
C5B8
0.1uF 10%
74AHC1G08
Step 3 - Power Good
INTERPOSER_PRES#
ON_BOARD_VR_ON 40
3
+V3.3ALWAYS
+V3.3S
4
40 ON_BOARD_VR_PWRGD
4
4
74AHC1G08
3
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
20,21,23,26,31,33,34,35,36,38,40,41,44,48 +V3.3S
R4B7
10K
2
OFF_BOARD_VR_ON
74AHC1G08
5
21 V5A_PWRGD
2
4
74AHC1G08
2
32 VR_SHUT_DOWN#
U7B1
4
VR_VID_ON
1
0.1UF
1
1
3
43 DDR_VR_PWRGD
INTERPOSER_PRES#
2
U5B4
5
+V3.3ALWAYS
3
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
C7B2
0.1UF
5
4
C5C1
U5C1
3
MAIN2_PWROK 2
+V3.3S
1
2
C7A4
U7A6
E
5
20 V1.5_PWRGD
D
Step 1 - Power OK
5
44 PWR_PWROK
U7A3
1
C
5
A
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
C7A2
0.1UF
14
U4B3B
74HC00
3
PWRGD1
4
2
74HC00
6
3
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
VR_PWRGD 37
5
7
15,18,19,20,23,27,30,32,35,37,38,43,44
7
5,15,19,20,21,22,23,27,28,29,32,36,37,38,44,48
+V3.3S
3
+V3.3
R3G10
10K
+V3.3ALWAYS
C7B1
74HC00
14
U4B3D
INTERPOSER_PRES
13
8
74HC00
9
11
0.1UF
1
40,42 GMCH_VCORE_PWRGD
PWRGD2
2
4
74AHC1G08
VID Settings
B
1
3
1
3
8.2K
8.2K
R1G1
4
3
5 RP1G1D
8.2K
6 RP1G1C
8.2K
1
3
J1G2
2
1
0
2
1
1
1
1
1
2
C
3
1K
H_VID0
H_VID1
H_VID2
H_VID3
H_VID4
STRAP_VID0
STRAP_VID1
STRAP_VID2
STRAP_VID3
STRAP_VID4
2
2
2
2
2
2
2
1
A
4
1K
J1G3
J1G4
J1H1
J1G1
R1F1
BX_PU
+V3.3S
STRAP0
1
2
4
6
8
PM_STPCPU# 6,19,37,40
10
PM_DPRSLPVR 19,37,40
12 SMB_DATA_VR
14 SMB_CLK_VR
SMB_DATA_S 6,8,11,12,16,18
16
NO_STUFF_0 R4C17
18
20
SMB_CLK_S 6,8,11,12,16,18
22
NO_STUFF_0 R4C18
24
26
28
30
IMVP-V_NET7 40
32
(Bootselect_5V)
34
36
38
40
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
+V5S
8,15,16,17,18,20,23,24,25,27,34,35,40,44,47
20x2_Header
STRAP1
3,40 H_PROCHOT#
INTERPOSER_PRES#
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VR_VID2
VR_VID1
VR_VID0
J1H2
1-2 (Default)
2-3
1-X
STRAP2
J4C1
VR_VID5
VR_VID4
VR_VID3
OFF_BOARD_VR_ON
OFF_BOARD_VR_PWRGD
VID5 Setting
Processor Control
Logic "0"
Logic "1"
STRAP3
VID2_LED VID1_LED VID0_LED
DS1J2
DS1J3
DS1J4
GREEN
GREEN
GREEN
VR_VID5
STRAP4
VID5_LED VID4_LED VID3_LED
DS1J1
DS2J3
DS2J4
GREEN
GREEN
GREEN
8.2K
RP1G1B
J1H2
7
CON3_HDR
1
R1Y1
330
Note: J1F1 enables
Manual VID strapping
2
R1Y2
330
BE#
CON3_HDR
47
47
47
47
47
+V3.3S
H_VID[4:0]
3
R1Y3
330
4
R1H4
1K
3
R1Y4
330
2
R2Y1
330
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
40
R1H3
3
VR_VID5
2
+V3.3S
2
+V3.3S
H_VID5
1
3
1
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
R1J1
330
2
7
VR Interposer
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,40,41,44,48
Q2G1
2N3904
IMVP_PWRGD 7,41
3
R5N7
100K
2
7
OFF_BOARD_VR_PWRGD
IMVP_PWRGD_D
1
10K
12
VR_PWRGD_CK408# 6
3
R2G11
5
4
6 RP1E1D 3
7 RP1E1C 2
8 RP1E1B 1
RP1E1A
10
U7A5
5
14
U4B3C
1 BX
2
R1F7
8.2K
Title
With pin 13 high, B input goes to C
output. With pin 13 low, A input goes
to C output.
U1F1
3
7
11
17
21
4
8
14
18
22
1
13
A0
A1
A2
A3
A4
B0
B1
B2
B3
B4
BE#
BX
C0
C1
C2
C3
C4
D0
D1
D2
D3
D4
VCC
GND
2
6
10
16
20
5
9
15
19
23
24
12
VR_VID0
VR_VID1
VR_VID2
VR_VID3
VR_VID4
+V5S
R1E1
1K
34,40
34,40
34,40
34,40
34,40
8,15,16,17,18,20,
C1F2
0.01UF
Bus_Switch_74CBT3383
J1F1
STRAP_VID4
STRAP_VID3
STRAP_VID2
STRAP_VID1
STRAP_VID0
R1F3
1K
2
For EVMC use, J1F1 is to be jumpered and J1G1,
J1G2, J1G3, J1G4, J1H1 need to be jumpered 1-2
1
Processor VR Interposer Support & Power Circuitry
Size Project:
A
Date:
Friday, May 21, 2004
D
Document Number
Sheet
39
Rev
of
E
46
A
4
39
34,39
34,39
34,39
34,39
34,39
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0
B
C
D
E
Temperature Monitor
VR_VID5
VR_VID4
VR_VID3
VR_VID2
VR_VID1
VR_VID0
ON_BOARD_VR_PWRGD
ON_BOARD_VR_PWRGD 39
4
GMCH_VCORE_PWRGD
GMCH_VCORE_PWRGD 39,42
3,4,5,9,10,18,20,41,47,48
19,37,39 PM_DPRSLPVR
IMVP-V_NET7
PM_DPRSLPVR
6,19,37,39 PM_STPCPU#
39 ON_BOARD_VR_ON
PM_STPCPU#
ON_BOARD_VR_ON
+VIN
R3N2
100K_1%
IMVP-V
VCC_IMVP
+VIN
4 BOOTSELECT
Thermal
Alarm
+VCC_IMVP 3,4,5,9,10,18,20,41,47,48
8,15,16,17,18,20,23,24,25,27,34,35,39,44,47
+V5S
R2N1
1K_1%
CORE_VSSSENSE
4 CORE_VCCSENSE
CORE_VCCSENSE
H_PROCHOT# 3,39
Q3B2
BOOTSELECT
4 CORE_VSSSENSE
+VCC_IMVP
IMVP-V_NET7 39
1
2
3
GND1 TOVER#
GND2
HYST
VCC
5
4
MAX6501
THERMAL_SENSOR_VCC
C3N1
2.2uF
10%
C3N2
0.1uF
10%
3
3
Mobile Intel Pentium 4 Processor VID table
+VCC_IMVP
J1H2 J1H1 J1G4 J1G3 J1G2 J1G1
0
0
1
1
1
0
1
1
0
0
1
1
0
1
1
0
0
1
0
1
1
0
0
1
0
1
1
0
0
0
0
1
1
1
1
1
0
1
1
1
1
0
1
1
1
0
0
1
0
1
1
1
0
0
0
1
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
1
1
1
0
0
1
1
1
0
0
0
1
0
1
0
1
0
0
0
1
1
0
1
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
1
1
1
1
0
1
0
1
1
1
1
0
1
1
0
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
0
1
0
1
0
1
1
1
0
0
1
0
1
0
0
0
0
1
1
0
1
1
1
0
0
1
1
0
1
0
1
0
1
0
1.2125 V
1.2250 V
1.2375 V
1.2500 V
1.2625 V
1.2750 V
1.2875 V
1.3000 V
1.3125 V
1.3250 V
1.3375 V
1.3500 V
1.3625 V
1.3750 V
1.3875 V
1.4000 V
1.4125 V
1.4250 V
1.4375 V
1.4500 V
1.4625 V
1.4750 V
1.4875 V
1.5000 V
1.5125 V
1.5250 V
1.5375 V
1.5500 V
1.5625 V
1.5750 V
1.5875 V
1.6000 V
DELAY POWERGOOD CIRCUIT
2
39 DELAYED_VIDPWRGD
C4P3
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,41,44,48
1
0.1uF
CR4C1
10%
R4P7
BAT54
49.9K
1%
3
1
+V3.3S
2
2
Jumper Settings
0 = LOW, 1 = HIGH
See page 39 for info.
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,41,44,48
1
4
R4P5
+V3.3S
3
H_VIDPWRGD 3
2IMVP-V_NET11
R4P6
2.43K_1%
1M
U2R1
R2P1
CM3102_IN
0
R4P3
R4P4
2
9.76k_1% 2.21K_1%
8
+
U4C1A
LM358
1
Jumper Settings
0 = LOW, 1 = HIGH
See page 39 for info.
+VCC_IMVP
J1H2 J1H1 J1G4 J1G3 J1G2 J1G1
1
1
0
0
0
0
0.8375 V
0.8500 V
1
1
0
0
0
1
0
0.8625 V
1
0
0
0
1
1
1
0
0
0
0
0.8750 V
0
0
1
0.8875 V
0
0
0
1
0
0
1
1
1
0.9000V
0
0
1
1
1
0.9125 V
0
1
0
1
0
1
0
0.9250 V
0
0
1
0
0.9375 V
1
0
1
0
0
1
0
0.9500 V
1
0.9625 V
0
0
1
0
1
0
0
1
0
1
0
0.9750V
0
0
1
0
0
0.9875 V
0
0
0
1.0000 V
0
0
1
1
1
0
1
0
0
1
0
1.0125 V
1
1
0
0
0
1.0250 V
0
1
0
0
0
0
0
1.0375 V
0
1
0
0
0
1
1.0500 V
1.0625 V
0
0
0
0
0
1
1
0
0
0
1.0750 V
0
0
0
0
0
0
0
1.0875 V
0
1
1
1
1
1
1
OFF
0
1
1
1
1
OFF
1
1
1
1
1
0
1.1000 V
1
1.1125V
1
0
1
1
0
1
1
1
1
1
0
1
1.1250V
0
1
0
1
1
1
1.1375V
1
0
1
1
1
0
1.1500V
0
1
1
0
0
1
1.1625V
1
1
1
0
1
1
1.1750V
0
1
1
1
1
0
1.1875V
1
0
1
1
1
0
1.2000V
5%
C2R3
0.1uF
10%
1
2
3
IN
GND
EN
OUT
3,4
C2R4
PG
+VCC_VID
5
4
0.1uF 10%
C2R5
1uF
20%
MIC5258
VR_ON
32,37,39,42
1
1
Title
Processor Core VR (IMVP-V)
Size Project:
A
Date:
Friday, May 21, 2004
A
B
C
D
Document Number
Sheet
40
Rev
of
E
46
A
3,4,5,9,10,18,20,40,47,48
B
C
D
E
Processor Decoupling
+VCC_IMVP
Do Not Stuff
+ C3P1
+ C3P3
+ C3P4
+ C3P2
NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF NO_STUFF_680uF
20%
20%
20%
20%
+ C3P5
NO_STUFF_680uF
20%
+ C2P2
NO_STUFF_680uF
20%
+ C2P1
NO_STUFF_680uF
20%
+ C2P3
NO_STUFF_680uF
20%
4
4
C3C12
22uF
20%
C2D2
22uF
20%
C2C5
22uF
20%
C2D1
22uF
20%
C2P4
22uF
20%
C2R2
22uF
20%
C3P7
22uF
20%
C3R3
22uF
20%
C3P6
20%
C3R2
20%
C3P8
20%
C3R1
20%
NO_STUFF_22uF
C3D3
22uF
20%
NO_STUFF_22uF
C3C11
22uF
20%
NO_STUFF_22uF
C3C10
22uF
20%
NO_STUFF_22uF
C3D2
22uF
20%
NO_STUFF_22uF
C3D1
22uF
20%
NO_STUFF_22uF
C3C9
22uF
20%
C3R5
20%
C2R7
20%
Do Not Stuff
20%
C3T5
20%
C3T6
20%
C3E1
20%
C3E2
20%
C3E3
20%
C3E4
20%
C3E5
20%
C3E6
20%
NO_STUFF_22uF
C3T4
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3T2
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3T1
NO_STUFF_22uF
20%
NO_STUFF_22uF
C2T1
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3R7
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3R9
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3T3
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3R8
NO_STUFF_22uF
20%
NO_STUFF_22uF
C3R6
NO_STUFF_22uF
20%
NO_STUFF_22uF
NO_STUFF_22uF
C3R4
C2E1
20%
C2E2
20%
Do Not Stuff
3
3
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,44,48
+V3.3S
C6C4
0.1UF
1
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,44,48
+V3.3S
R6C13
10K
R6C7
1.58K_1%
VDD+
10
R6C12
10K
2
2
OPAMP_N
2
OPAMP_P
3
TLV2463
2
Q6C3
BSS84
1
7,39 IMVP_PWRGD
C6C5
1uF
2
U6C2A
1
5
OPAMP_EN
DELAYED_VR_PWRGD
19,37
+
GND
4
R6C9
2K_1%
3
1
1
Title
Size
A
Date:
A
B
C
Processor Decoupling
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
41
E
46
A
B
C
D
E
4
4
3
3
44,47 1.5V_EV
1.5V_EV
2
+V1.5S_GMCH 9,47
+V1.5S_GMCH
2
852GME/PM VR CONTROLLER
32,37,39,40 VR_ON
VR_ON
GMCH_VCORE_PWRGD 39,40
GMCH_VCORE_PWRGD
1
1
Title
GMCH VR and VCCP
Size Project:
A
Date:
Friday, May 21, 2004
A
B
C
D
Document Number
Sheet
42
Rev
of
E
46
A
B
20,21,22,23,27,36,37,44
C
D
E
+V5
BOOT_1
C3G9
C3G8
C3G10
150uF
150uF
0.1UF
4
24
23
22
21
20
VSENSE_1
2
COMP_1
C3G5
47pF
C3V2
R3V4
COMP_1_D 1
RT_1
R3U4
2
NO_STUFF_10K_1%
SS/ENA_1
J3G2
R3F22
3
R4G1 5.49k_1%
V2.5_DDR_D
VBIAS_1
C3G1
1
CON3_HDR
0.01UF
NO_STUFF_10K
VIN0
VIN1
VIN2
VIN3 TPS54610
VIN4
NC/Comp
4
PWRGD
5
BOOT
28
RT
27
FSEL
6
7
8
9
10
11
12
13
14
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
VSENSE
3
2
5600pF
25.5k_1%
0.022uF
U3G1
9,11,12
+V2.5
Single point
sense
near load
L4G1
PH_1 1
4.7uH
2
AGND
4
C4F1
PwrPad
C3G7
0.1UF
1
PGND0 19
PGND1 18
26 SS/ENA
PGND2 17
PGND3 16
25 VBAIS
PGND4 15
Note for layout: This part has
special pad on it's underside
20,21,22,23,27,36,37,44
C3F6
11,12,47,48 +V2.5_DDR
R3V1 10K_1%
20,21,22,23,27,36,37,44
+V5
+V5
0.1UF
VSENSE_1_D
1
R3V2 221_1%
9,10,48 +V2.5_GMCH_SM
2
C3V1
8200pF
R3V8
10K
C3G11
0.1UF
R3F21
43.2_1%
R2G7
VDD+
R3V3
5.49k_1%
10
10K_1%
3
GND_DDR R3G5
8
SM_VREF_DIMM_EV 47
Default: J3G1 No shunt
2.5V_DDR_EV 47
0
-
U3G2B
TLV2463
J3G1
1
9,10,48 +V2.5_GMCH_SM
2
R3G9
7
0
9
6
SM_VREF_DIMM 11,12
OPAMP1_EN
3
+
GND
4
R3G6
R3V5
NO_STUFF_10K
10K_1%
15,18,19,20,23,27,30,32,35,37,38,39,44
R3V11
10K_1%
+V3.3
R3G8
10K
20,21,22,23,27,36,37,44
+V5
DDR_VR_PWRGD 39
R3W3
10K_1%
C3V3
0.01UF
9,10,48 +V2.5_GMCH_SM
SM_VREF_MCH_EV 47
20,21,22,23,27,36,37,44
+V5
REFIN_2
VDD+
R3V6
NO_STUFF_10K
10
R3G2
2
-
3
+
U3G2A
TLV2463
1
5
10K_1%
R3G4
0
OPAMP2_EN
SM_VREF_MCH 7
2
C3H3
C3H4
R3W2
150uF
150uF
U3G3
0.1UF
24
23
22
21
20
NO_STUFF_0
VSENSE_2
2
COMP_2
C3G13
220PF
R3W1
C3V5
COMP_2_D
BOOT_2
4.99k_1%
FSEL
100K
VBIAS_2
R3G12
R3V12
VIN0
VIN1
VIN2
VIN3 TPS54672
VIN4
VSENSE
3
NC/Comp
4
STATUS
5
RT_2
0.082uF
BOOT
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
6
7
8
9
10
11
12
13
14
10K_1%
R3V9
VSENSE_2_D
1.25V_DDR_EV 47
Vtt Sense
R4G3
L4H1
PH_2
1
4.7uH
43.2_1%
14,47,48
R4H1
RT
27
ENA
C6J1
C4J1
C6J2
C4H1
C4H5
26
REFIN
150uF
150uF
150uF
150uF
0.1UF
AGND
1
C3V4
1
2
PGND0 19
PGND1 18
PGND2 17
PGND3 16
25 VBAIS
PGND4 15
Note for layout: This part has
special pad on it's underside
R3G11
15,19,25,32,37,38,44 PM_SLP_S3#
0
No Stuff
R3V10
19,20,32,37,38,44 PM_SLP_S4#
Vtt Sense
C
R3V6
R3G4
R3V7
R3G9
R3V6
1
DDR VR
Size Project:
A
Date:
Friday, May 21, 2004
B
EV Support
EV Support Resistor Options
NO_STUFF_0
Title
Vtt Sense
R3G4
R3V7
R3G9
FSEL
C3H1
0.022uF
A
Non-EV Support
Stuff
8200pF
R3V13
NO_STUFF_4.99k_1%
+V1.25S
0.01_1%
0.1UF
267_1%
Single point
sense
near load
+VDDR
2
28
C3G12
3.92k_1%
1
2
R3V7
10K
GND
4
R3G1
PwrPad
C3H2
D
Document Number
Sheet
43
Rev
of
E
46
A
B
C
D
J1B1
15,16,21
15,17,23,27,37,38 +V12S
5,6,8,9,11,16,18,20,21,23,26,31,33,34,35,36,38,39,40,41,48
F1
F2
F3
F4
8,15,16,17,18,20,23,24,25,27,34,35,39,40,47
CON3,RCPTL,TH,700000-667.Normal
9,15,19,20,47,48
+V1.5S
+V3.3S_TURNER
-V12S_TURNER
R1C4
8
+V3.3ALWAYS
0.01_1%
R1D2
+V3.3A_TURNER
2
0.002_1%
C1D1
22UF
2
IN
OUT
3
3
R6J2
330
+V5S_TURNER
R1D1
0.01_1%
15,17,23,27,37,38 +V12S
+V5
FRONT1
R1C5
0.01_1%
26,27
IDE_PDACTIVE#
+V2.5_TURNER
C6J4
C6J6
C6J8
470PF 470PF 470PF
1
3
5
7
9
11
13
15
R6J4
330
POWER
FRONT2
2
4
6
8
10
12
SW3_CONN_D 3
SW8J1
3
1
4
2
Push button
1
CR6J1
BAT54
C6J7
C6J5
470PF
470PF
PS_ON_SW#
16
5,15,19,20,21,22,23,27,28,29,32,36,37,38,39,48
MASTER_RESET#
1.5V_EV
42,47
+V3.3ALWAYS
U1E1
C1E2
1
2
3,5,47 ITP_DBRESET#
74AHC1G08
4
PM_SYSRST# 19
2
0.1UF
+V12DC
J5B1
3
4
1
2
C4N2
470pF
5%
C5N2
470pF
5%
+V5
ATX POWER SUPPLY +12V CONNECTOR
+V5_TURNER
R1D3
0.01_1%
F1
F2
F3
F4
1
Title
Size
A
Date:
3Pin_RECEPTICLE
CON3,RCPTL,TH,700000-667.Normal
A
3
HDR_2x8
20,21,22,23,27,36,37,43
1
+V3.3_TURNER
+V5S
Front Panel Connector
D1
D2
D3
D4
0.01_1%
C1E1
20,21,22,23,27,36,37,43
J1D1
R1D4
+V5
J6J1
+V12S_TURNER
A1
A2
A3
A4
+V3.3
20,21,22,23,27,36,37,43
8,15,16,17,18,20,23,24,25,27,34,35,39,40,47
CON72,RCPTL,TH,700000-668.Normal
35,37,38,39,43
MASTER_RESET#
5
-V12S
4
3
,23
PS_ON_SW#
72Pin_RECEPTICLE(male)
19,20,32,37,38,43 PM_SLP_S4#
15,19,25,32,37,38,43 PM_SLP_S3#
6,19,37,38 PM_SLP_S1#
39 PWR_PWROK
F12
F11
F10
F9
F8
F7
F6
F5
F4
F3
F2
F1
E12
E11
E10
E9
E8
E7
E6
E5
E4
E3
E2
E1
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
VCC
CR6J2
BAT54
+V5S
+V5S
J1C1
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
GND
MAX6816
RST_PUSH#_D
8,15,16,17,18,20,23,24,25,27,34,35,39,40,47
CON3,RCPTL,TH,700000-667.Normal
32,37 AC_PRESENT#
37,48 GATED_SMC_SHUTDOWN
32,37 SMC_ONOFF#
32,36,37 SMB_SB_CLK
32,36,37 SMB_SB_DATA
32,36,37 SMB_SB_ALRT#
22UF
1
22UF
8,15,16,17,18,20,23,24,25,27,34,35,39,40,47
3Pin_RECEPTICLE
3
RST_PUSH#
C7E7
1
F1
F2
F3
F4
0.002_1%
1
2
Push button
RESET
D1
D2
D3
D4
R1C2
C1C1
22UF
3
4
4
+V5S
C6J3
0.1UF
U6J1
SW7J1
J1B2
A1
A2
A3
A4
+V3.3S
C3A11
22UF
35V
+V3.3S
R6J5
10K
3Pin_RECEPTICLE
35,36,38,39,40,41,48
C8A2
22UF
35V
+VDC
D1
D2
D3
D4
+V1.8S
-V12S
HDM conn. is a modulized conn. design in 2 parts. 3 pin power
recepticle and a 72 pin recepticle. The 2 parts will be arranged as
shown on this schematic page.
A1
A2
A3
A4
4
E
22,23
HDM Connector Assembly (base board)
B
C
DC/DC Connector
Project:
Document Number
Friday, May 21, 2004
D
Sheet
Rev
of
44
E
46
A
B
C
D
E
Power On Sequence
PM_SLP_S4#
4
+V3.3
5
PM_SLP_S3#
4
+V3.3S
5
+V5S
5
+V5
5
3
2
+V3A
PG 20
+V1.5A
MAIN2_PWROK
PG 39
U7A6
8
PM_PWROK
19
PG 39
CPU
PG 41
SMC
10
H_VIDPWRGD
2
VR_PWRGD_CK408#
9
SMC_PROG_RST#
U8A2
SMC_RST#
RST_HDR
VR_ON
2
PG 3
PG 32
+V3A
+V2.5
+V1.25S
3
21
3 3
MAX809
PG 33
+V5A VR
PG 21
PG 7
PG 39
U7B1
SMC_ONOFF#
DDR VR
PG 43
GMCH
PG 32
CK-408
PG 6
IMVP_PWRGD
PG 44
MAIN_PWROK
PM_RSMRST#
5
7
U7A3
6
PM_PWRBTN#
5
V5A_PWRGD
-V12S
PG 44
PWR_PWROK
4
PG 19
PS_ON_SW#
DDR_VR_PWRGD
+V12S
1
POWER
20
ICH4
H_CPURST#
5
H_PWRGD
+V1.5S
PCI_RST#
DELAYED_VR_PWRGD
5
V1.5_PWRGD
4
20
DC/DC
+VDC
+V5_ALWAYS
2
PG 39
VR_SHUTDOWN
14
ON_BOARD_VR_ON
Core VR
U5C1
13
PG 39
PG 40
U5B4
12
VR_VID_ON
11
U5B3
DELAYED_VIDPWRGD
INTERPOSER_PRES#
H_VIDPWRGD
VCCVID
VR
GMCH
VR
10 PG 40
PG 42
GMCH_VCORE_PWRGD
15
ON_BOARD_VR_PWRGD
1
U4B3A
PG 39
INTERPOSER_PRES
OFF_BOARD_VR_PWRGD
U4B3D
16
10
U7A5
U4B3B 17
18
PG 39
Title
Power On Check-list
Size Project:
A
Date:
Friday, May 21, 2004
A
B
1
PG 39
C
D
Document Number
Sheet
45
Rev
of
E
46
A
B
C
D
E
PS_ON_SW#
DC/DC
Turner
4
Reset Map
PG 44
SMC_SHUTDOWN
PCI_RST#
PCI
SLOTS
BUF_PCI_RST#
PWR_PWROK
PG 44
U7A3
MASTER_RESET#
ICH4
PM_PWROK
PG 39
PG22
PG 18
PM_RSMRST#
PG 40
Core VR
PG 39
Q9B3
PCI_GATED_RST#
PG32
R=0
ITP
AGP
SLOT
PG 15
U7A4
PG 33
PG 33
3
PG 22
PG 5
MAX809
LPC
SLOT
PG 37
R=0
DOCKING
3
2
4
SMC
SMC_RST#
U8A2
PG 32
2
SMC_RES#
FWH
PG 31
PG 32
SMC_PROG_RST#
H_CPURST#
SIO
PG 34
MCH
H_PWRGD
CPU
PG 7
1
1
PG 3
Title
Reset Map
Size Project:
A
Date:
Friday, May 21, 2004
A
B
C
D
Document Number
Sheet
46
Rev
of
E
46
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