Topic E
Under the Hood of Low-Voltage
DC/DC Converters
Brian Lynch
Kurt Hesse
1
Outline
‹ Synchronous Buck Review
‹ Design a converter
„
„
„
„
„
Inductor
FETs
Controller
Capacitors
Feedback Design
‹ Results
‹ Conclusion
2
1
Synchronous Buck
Synchronous
Rectifier
DC Input
SW Node
Averaging Circuit
Switch
Output
Z
VCC
SR
Z
COMP
+
PWM
Z
GND
Control Circuit
3
Synchronous Buck Waveforms
Continuous Conduction Mode
PWM Switch
Synchronous
Rectifier
Switch
Current
GND
Synchronous
Rectifier
Current
GND
Vin
Switch
Node
Average Vout
GND
Average Iout
Inductor
Current
GND
t2
t6
t3 t5
t4
t1
t0
Ts
t7
t8
4
2
Synchronous Rectifier FET Current
PWM Switch
Synchronous
Rectifier
Total
Synchronous
Rectifier
Current
GND
Diode
Current
GND
Channel
Current
GND
Vin
Switch
Node
Average Vout
GND
t2
t6
t3 t5
t4
t1
t0
t7
t8
Ts
5
Synchronous Buck Waveforms
Discontinuous Conduction Mode
PWM
Synchronous
Rectifier
Switch
Current
GND
Synchronous
Rectifier
Current
GND
Swtch
Node
Average Vout
GND
Inductor
Current
GND
t0
t1
t2
t6
t4
t3
t5
6
3
Basic Relationships
Continuous Conduction Mode (CCM)
t on
V
= out
Ts
V in
(V in − V out ) ⋅ D ⋅ Ts
∆I out =
L
D =
Discontinuous Conduction Mode (DCM)
D =
2L ⋅ I O
V out
⋅
Ts
V in 2 − V in ⋅ V out
7
Under The Hood
Design Example
8
4
Design Goals
‹ Input Voltage: 3.3V
‹ Output Voltage: 1.2V
‹ Output Current: 10A
‹ Optimize for power density
„
„
Low power dissipation
Small size
9
Controller Selection
‹ TPS40003
„
„
„
„
600kHz
Predictive Gate DriveTM
Small size: 10-pin MSOP
2 Amp peak on-board drivers
10
5
Predictive Gate DriveTM
SW Node
GND
Channel Conduction
Body Diode Conduction
Monitor
Level
Fixed Delay
Adaptive Delay
Predictive Delay
11
Inductor Considerations
‹ Benefits of low L values
„
„
„
Lower DCR
Higher Isat
Higher di/dt
Š Transient response improves
Š Less output capacitance required for given transient
performance
‹ Benefits of high L values
„
Lower ripple current
Š
Š
Š
Š
Š
Lower AC losses (skin effect, hysteresis)
Lower RMS current in FETs
Lower RMS capacitor current (mainly output)
Continuous inductor current over broader load range
Less C required for equivalent output ripple
12
6
General Inductor Guidelines
‹ Size for ∆IL to be 10% to 30% of full load current
‹ Winding losses usually dominate
PLAVG = ILRMS2 ⋅ RL
2
where ILRMS = Iout +
∆ILpp2
12
13
Inductor and FETs
Normalized Switch and SR Power Loss (W)
1.25
1.20
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0
10
20
30
40
50
60
70
80
90
100
IRIPPLE/ILOAD (%)
‹ Increasing ripple increases losses
‹ Similar effect for capacitor ESR loss
14
7
Inductor and Total Efficiency
93
Inductor
91
0.68 µH 3 mΩ
0.47 µH 3.5 mΩ
90
Efficiency (%)
ESR
1.0 µH
2 mΩ
0.82 µH 2.5 mΩ
92
89
88
87
86
85
0
2
4
6
8
10
IOUT - Output Current - A
‹ Vishay IHLP5050CE
‹ Converter similar to final design
15
Inductor Selection
‹ IHLP5050CE, 680nH
‹ Good efficiency over broadest range
‹ Ripple current is about 20% of full load
16
8
MOSFETs
‹ Both main switch and synchronous rectifier are N-type
(from controller selection)
‹ Many interrelated issues
„
„
„
Output capacitance vs. switching loss
Gate capacitance vs. switching speed
Gate capacitance vs. driver power loss
‹ Primary Tradeoffs
„
„
„
Package
Power loss
Cost
17
Switch FET
Losses vs. Frequency
0.35
Losses
Switch Losses (W)
0.30
Conduction
0.25
Gate
Switching
0.20
Output
0.15
0.10
0.05
0.00
100 k
10 M
fSW - Switching Frequency - Hz
‹ Frequency already chosen by controller selection
‹ Data for Si4866DY switch, Si4836DY rectifier, 2A ripple
current and 10A load
18
9
Rectifier FET
Losses vs. Frequency
0.35
Losses
0.30
Channel Conduction
Gate
Switch Losses (W)
0.25
Diode Conduction
0.20
0.15
0.10
0.05
0.00
100 k
10 M
fSW - Switching Frequency - Hz
‹ Note rise in diode conduction loss as Fs rises.
‹ Data assumes 20-ns of diode conduction time per SW edge
19
FET Effect on Driver Dissipation
Driver
equivalent
switch and
resistance
Vgtdrv ⋅ Qg ⋅ Fs
⋅
2
⎛
⎞
Rghi
Rglo
⎜⎜
⎟⎟
+
⎝ Rghi + Rg + Rgi Rglo + Rg + Rgi ⎠
Pdrvr =
Gate Drive
Voltage
Rghi
Switch or
Synchronous
Rectifier
Rg
Rglo
PWM
Gate
Drive
‹ Higher Qg gives higher
driver dissipation
Rgi
MOSFET
‹ Addition of external
resistor reduces driver
dissipation
20
10
FET Selection
‹Compare different FETs in both positions
‹In general higher F and higher input voltage
mean lower Qg switch FET to cut switching
losses
‹For rectifier FET, low RDS(on) is most important,
but don’t ignore gate power
‹Changing FET RDS(on) changes D, which
effects RMS currents and losses elsewhere
21
Some FET Comparisons
(at rated load)
Switch FET
Si4836DY
FDS6574A
IRF7459
Si4866DY
Rect. FET
Si4836DY
FDS6574A
IRF7459
Si4836DY
SW FET
Losses
566mW
817mW
1231mW
503mW
Rect. FET
Losses
392mW
675mW
1057mW
391mW
Other Losses
0.949W
1.000W
0.959W
0.944W
Total Losses
1.91W
2.49W
3.25W
1.84W
Efficiency
86.3%
82.8%
78.7%
86.7%
22
11
SW Node Ringing
Bottom Gate (1 V/div)
SW (1 V/div)
‹Can affect converter
operation
‹Worst on rising edge of SW
(highest di/dt transition)
‹Caused by parasitic L and C
„
dV/dt Bump
„
t - Time - 50 ns/div
„
L in the FET from the SW node
to Vin or GND
C from SW node to GND
High layout dependence
23
Parasitic Rectifier Turn-On
Main Switch
Vin
Synchronous
Rectifier
MOSFET
Vout
Ld
Cdg
Driver
Cds
Lg
Rgi
Cgs
Ls
‹ Rectifier FET can be briefly forced on when SW rises
‹ Cdg (Miller) capacitance causes displacement current
in gate circuit
24
12
SW Node Ringing Remedies
‹ Improve layout
„
„
„
Minimize loop areas
Minimize trace inductance
Keep SW node area low (secondary effect, conflicts
with cooling rectifier FET)
‹ Slow down SW node edge transitions
„
Series gate resistor in switch FET gate lead
‹ Add a snubber
25
Power Capacitors
Selection Considerations
‹ Power Dissipation
„
ESR
‹ Ripple Performance
„
ESR
‹ Transient Performance
„
„
„
ESR
Capacitance
ESL
‹ Cost
‹ Size
‹ Reliability
26
13
Relative Capacitors Characteristics
‹ Standard Al Electrolytic
„
„
„
„
High ESR
Low cost
Low current capability
Not really suited to DC/DC converters
‹ OSCON
„
„
„
Low ESR
Medium cost
High current capability
27
Relative Capacitors Characteristics
‹ Solid Polymer
„
„
„
Low ESR
Very high cost
Medium current capability
‹ POSCAP
„
„
„
Low ESR
High cost
Medium current capability
28
14
Relative Capacitors Characteristics
‹ Tantalum
„
„
„
Medium ESR
Medium cost
Medium low current capability
‹ Ceramic
„
„
„
Very low ESR
Very high cost
High current capability in bulk
29
Capacitor Impedance
10 µF Ceramic
180 µF Solid Polymer
470 µF Tantalum
1000 µF OSCON
10
RCAP - Impedance - Ω
1
0.1
0.01
0.001
0.1
1
10
100
1000
10000
f - Frequency - kHz
30
15
Choosing Capacitor Size
‹ Input Filter
„
Sized for AC current handling
‹ Output Filter
„
„
Transient events on load
Output voltage ripple
31
Input Capacitor Current
Ic
(sw OFF)
Isw = Ic + Iin
Ic
(sw ON)
Iin
SW1
Lout
+
Io
∆ISWpp
Cin
Io
Iload
SW2
Cout
2
Pcap = I cap RMS ⋅ ESR cap
2
⎡
∆ISW pp ⎤
2
I cap RMS = ⎢(ISW pk − I in avg ) 2 +
⎥ ⋅ D + I in avg ⋅ (1 − D )
12 ⎥
⎢⎣
⎦
32
16
Input Capacitors Selection
‹ Use two 180µF solid polymer (SP)
„
„
2 required to handle current (~5A)
Smallest volume = best power density
Š 220µF POSCAP is smaller but has same footprint
Š SP will dissipate heat better due to slightly larger surface area
Š Either would work in application
‹ 40µF of ceramic capacitor added to reduce high frequency
current in supply feed
33
Input Ripple Voltage
Switch current
Cin current
Cin Ripple Voltage
ESR Voltage
C
ESL Voltage
‹ Usually a secondary consideration
‹ Contribution from ESR, ESL and capacitance value
34
17
Output Capacitor Criteria
Selection Considerations
‹ Transient performance
„
„
„
Bulk capacitance
ESR
ESL
‹ Output Ripple
„
„
„
ESR
Bulk value
ESL has minor effect
35
Transient Performance
Iload
Iinductor
Output
Currents
0A
ESR
Vout
AC
Coupled
ESL
ESL
ESR
Cout &
ESR
Cout &
ESR
36
18
Output Capacitor Calculations
Vunder =
Vover =
2
L ⋅ Istep
2 ⋅ Cout ⋅ Dmax ⋅ (Vin − Vout )
2
L ⋅ Istep
2 ⋅ Cout ⋅ Vout
di
dt
∆IL
Vripple = ∆IL ⋅ R ESR +
8 ⋅ Fs ⋅ Cout
Vspike = Istep ⋅ R ESR + LESL
37
Output Capacitor
Selection Considerations
‹ 2A to 10A load step @ 15A/µs
‹ Use 470µF SP: 15mΩ, 3nH
‹ To help reduce spikes, add two 10µF ceramics
‹ Yields
„
„
„
„
24.5mV undershoot
39mV overshoot
8mV spikes
21mV of ripple
38
19
Feedback Design
‹ Voltage mode buck
„
Use “Type 3” compensator
‹ Design for high loop bandwidth
„
Possible caviates
Š Shifting output capacitor ESR zero
Š Error amplifier GBWP
39
AC Model for Buck Converter
Filter Circuit
Vout
Vin
+
+
Bulk
Capacitance
w/ESR
* Ceramic helps at high frequency
PWM
Gain
(%/V)
Compensation
Σ
+
Reference Voltage
40
20
Start with Line Bode Plot
60
5 MHz
GBWP
Error
Amplifier
Limit
Compensation
Response
50
40
21.5 dB @ 100 kHz
Gain - dB
30
FDP = 8.9 kHz
20
A
KPWM = 11 dB
C
10
Fp1 = 100 kHz
Fp2 = 200 kHz
0
Filter and
PWM Response
-10
-20
B
-21.5 dB @ 100 kHz
Fz1 = Fz2 = 8.9 kHz
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-30
-40
10
100
1k
10 k
Frequency - Hz
100 k
1M
41
Plot PWM and Filter Response
60
50
40
FDP =
Vramp
3.6
=
= 11db
1
1
= 8.9kHz
2π ⋅ L f ⋅ C f
FESR =
1
2π ⋅ R ESR ⋅ C f
30
Gain - dB
K PWM =
Vin(MAX)
KPWM = 11 dB
ESR Zero: 34kHz
10
0
-10
= 34kHz
FDP = 8.9 kHz
20
Filter and
PWM Response
-20
-30
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-40
10
100
1k
10 k
Frequency
100 k
1M
42
21
Plan Compensation Response
‹ Minimize DC error
„
Place pole at DC (no DC path from COMP to FB)
‹ Needs positive phase around FDP
„
Place 2 zeros at FDP
‹ Should have a +1 slope in the vicinity of 0db open
loop gain
„
„
Plan for maximum loop cross of 20% Fs (example uses
100kHz)
+1 slope of compensation should extend to at least this
point
‹ Take into account variable ESR zero of output cap
„
Set compensation gain to limit FCO in maximum ESR case
‹ Pay attention to error amplifier GBWP limit
43
Plan Compensation Response
60
5 MHz
GBWP
Error
Amplifier
Limit
50
40
21.5 dB @ 100 kHz
Gain - dB
30
FDP = 8.9 kHz
20
A
KPWM = 11 dB
10
0
Filter and
PWM Response
-10
-21.5 dB @ 100 kHz
-20
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-30
-40
10
100
1k
10 k
100 k
1M
‹ FCO max: place a corner so that the sum of
compensation gain and PWM/filter gain is 0db (point A)
„
„
In this example 21.5dB @100kHz
Draw in GBWP limit line – assume dominant pole amplifier
44
22
Plan Compensation Response
60
5 MHz
GBWP
Error
Amplifier
Limit
Compensation
Response
50
40
21.5 dB @ 100 kHz
30
FDP = 8.9 kHz
Gain - dB
20
A
KPWM = 11 dB
10
0
Filter and
PWM Response
-10
-20
B
-21.5 dB @ 100 kHz
Fz1 = Fz2 = 8.9 kHz
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-30
-40
10
100
1k
10 k
100 k
1M
‹ From A, go lower in frequency at +1 slope to FDP (point B)
~ 0dB @ 8.9kHz
„
45
Plan Compensation Response
60
5 MHz
GBWP
Error
Amplifier
Limit
50
40
21.5 dB @ 100 kHz
Gain - dB
30
FDP = 8.9 kHz
20
A
KPWM = 11 dB
10
0
Filter and
PWM Response
-10
-20
B
-21.5 dB @ 100 kHz
Fz1 = Fz2 = 8.9 kHz
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-30
-40
10
100
1k
10 k
100 k
1M
‹ Below point B the response is –1 slope
„
From the DC pole
46
23
Plan Compensation Response
60
5 MHz
GBWP
Error
Amplifier
Limit
50
40
21.5 dB @ 100 kHz
30
FDP = 8.9 kHz
Gain - dB
20
A
KPWM = 11 dB
C
10
Fp1 = 100 kHz
Fp2 = 200 kHz
0
B
Filter and
PWM Response
-10
-21.5 dB @ 100 kHz
Fz1 = Fz2 = 8.9 kHz
-20
w/ ESR = 0 mΩ
w/ ESR = 10 mΩ
-30
-40
10
100
1k
10 k
100 k
1M
‹ From A go higher in frequency at 0 slope for about an
octave, place the high frequency pole (point C)
„
21.5dB @ 200kHz
47
Implement Compensation
Vout
C3
C1
C2
R4
R1
Vref
2
Pick R
2
=
0.7
V out
= 10k
⇒ R 1 = 7 . 15 k,
R3
R2
R2
R1 + R
F Z1 = 8.9kHz
+
Vcmp
=
1
2π ⋅ R 1 ⋅ C1
⇒ C 1 = 2 . 5 nF (use 2.7nF)
F P1 = 100kHz
⇒ R
3
=
1
2π ⋅ R 3 ⋅ C 1
= 589 (use 590)
48
24
Implement Compensation
Vout
G P1 = 21.5dB = 12 = R 4 ⋅
C3
C1
C2
⇒ R 4 = 6.5k (Use 6.49k)
R4
FZ2 = 8.9kHz =
R1
R3
Vref
R2
R1 + R 3
R1 ⋅ R 3
1
2π ⋅ R 4 ⋅ C 2
⇒ C 2 = 2.76nF (Use 2.7nF)
+
Vcmp
FP2 = 200kHz =
1
2π ⋅ R 4 ⋅ C 3
⇒ C 3 = 123pF (Use 120pF)
49
AC Open Loop Response
180
135
30
135
90
20
90
10
45
0
0
180
30
20
10
45
0
0
-10
-45
Gain - dB
40
40
-10
-45
-90
-135
-20
-90
-20
-30
-135
-30
-40
100
1k
10 k
100 k
f - Frequency - Hz
-180
1M
Phase - Degrees
Whole Converter
Phase - Degrees
Gain - dB
Compensation
-40
100
1k
10 k
100 k
f - Frequency - Hz
GAIN
High ESR
Low ESR
-180
1M
PHASE MARGIN
High ESR
Low ESR
50
25
The Final Schematic
3.3 Vin
180 µF
x2
10 µF
x4
20 kΩ
TPS40003
2.7 nF
1
ILIM
BOOT
10
2
FB
HDRV
9
3
COMP
SW
8
4
SS/SD
VDD
7
6.49 kΩ
Si4866DY
IHLP5050CE-01
0.68 µH
1.2 Vout
100 nF
1.5 Ω
120 pF
4.7 nF
GND
LDRV
6
Si4836DY
5.6 nF
10 µF
x2
7.15 kΩ
2.7 nF
10.0 k
51
Lab Results
~20mV peak-to-peak Ripple
.015
.01
VOUT - Output Voltage - mV
5
374590
470 µF
.005
0
-.005
-.010
-.015
-.020
t- Time - 2 µs/div
52
26
Lab Results
Gate Drive Waveforms
SW Node
4.0
5
3.5
4
VGATE - Voltage - V
2.5
2.0
1.5
1.0
3
2
1
0.5
0
0.0
-0.5
-1
SR Gate
t- Time - 1 µs/div
Top Gate
53
Lab Results
fCO = 45kHz with 90º Phase Margin
Gain
Phase Margin
40
180
135
30
45
10
0
-45
0
Phase - Degrees
90
20
Gain - dB
VGATE - Voltage - V
3.0
-90
-10
-135
-20
100
1k
10 k
-180
100 k
f - Frequency - Hz
54
27
Lab Results
Efficiency
95
90
Actual
Efficiency - %
85
Predicted
80
75
70
65
60
0
1
2
3
4
5
6
7
8
9
10
11
12
ILOAD - Load Current - A
55
Conclusion
‹ Synchronous Buck converters appear simple at first
glance
„
„
“Anybody can build one”
Building a good one requires more thought
‹ Many interrelated factors combine to determine overall
converter effectiveness. Some are:
„
„
„
Relative FET sizes for main switch & SR
Frequency of operation vs. power density vs. efficiency
Others in paper: Capacitors, inductors, layout…
‹ Shown some of the major effects of choices in
converter design – others in paper
56
28
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