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CXA2581N
RF Signal Processor for CD Players
Description
The CXA2581N is an RF signal processing IC for
compact disc players.
30 pin SSOP (Plastic)
Features
• Wide band RF signal processing
• RF system VCA circuit
• RF system equalizer (supports CAV mode)
• Supports pickups with built-in RF summing
amplifier
• Low current consumption mode (EQ Pass mode)
• RW/ROM switching mode
• Center error amplifier
• Output DC level shift circuit
• TE balance adjustment function
Absolute Maximum Ratings
• Supply voltage
VCC
7
• Storage temperature
Tstg –65 to +150
• Allowable power dissipation
PD
620
Functions
• RF AC summing amplifier, equalizer, VCA
• RF DC summing amplifier
• Focus error amplifier
• Tracking error amplifier
• Center error amplifier
• Automatic power control
• VC buffer amplifier (analog block, digital block)
V
°C
mW
Operating Conditions
• Operating supply voltage range
VCC – GND 3.4 to 5.5
V
(0V ≤ Vcc – DVcc < 2V)
Note) Care should be taken for the operating voltage.
See page 18.
• Operating temperature
Topr –30 to +85
°C
DC_OFST
RFDCI
RFDCO
VC
RFC
VFC
BST
RFG
VCC
CEI
CE
TE_BAL
TE
FEI
FE
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LD
PD
EQ_IN
AC_SUM
GND
A
B
C
D
E
F
SW
DVCC
DVC
RFAC
Pin Configuration
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E98739A97-PS
CXA2581N
RFG
BST
3
23
24 26 25
AC
SUM
AC
VCA
EQ
VFC
EQ_IN
4
RFC
AC_SUM
Block Diagram
15 RFAC
EQ_ON/OFF
RW/ROM
30 DC_OFST
DVCC
VC
29 RFDCI
28 RFDCO
RW/ROM
DVC
A
6
B
7
C
8
D
DVCC
17 FEI
16 FE
VOFST
RW/ROM
VC
9
DVC
19 TE_BAL
RW/ROM
VC
F 10
gm
E 11
gm
VOFST
RW/ROM
DVCC
18 TE
VOFST
VC
RW/ROM
B
DVC
C
A
D
SW 12
APC
20 CE
VC
RW/ROM
APC-OFF (Hi-Z)
DVC
RW/ROM
VC
(H/L)
VCC
VOFST
VC
VC
1
DVC
22
5
27
14
VC
DVC
VCC
GND
LD
2
21 CEI
DVC
VCC
PD
DVCC
–2–
13 DVCC
CXA2581N
Pin Description
Pin
No.
Symbol
I/O
Description
1
LD
O
APC amplifier output.
2
PD
I
APC amplifier input.
3
EQ_IN
I
RFAC system VCA block and EQ block input.
4
AC_SUM
O
RFAC system RF SUM output.
5
GND
I
GND.
6
A
I
A signal input.
7
B
I
B signal input.
8
C
I
C signal input.
9
D
I
D signal input.
10
E
I
E signal input.
11
F
I
F signal input.
12
SW
I
Mode switching signal input.
13
DVCC
I
DVCC.
14
DVC
O
DVC output.
15
RFAC
O
RFAC signal output.
16
FE
O
Focus error signal output.
17
FEI
I
FE amplifier virtual ground.
18
TE
O
Tracking error signal output.
19
TE_BAL
I
TE balance adjustment.
20
CE
O
Center error signal output.
21
CEI
I
CE amplifier virtual ground.
22
VCC
I
VCC.
23
RFG
I
RFAC system VCA block low frequency gain adjustment.
24
BST
I
EQ boost level adjustment.
25
VFC
I
EQ cut-off frequency adjustment.
26
RFC
I
EQ cut-off frequency adjustment.
27
VC
O
VC voltage output.
28
RFDCO
O
RFDC signal output.
29
RFDCI
I
RFDC amplifier virtual ground.
30
DC_OFST
I
RFDC signal output offset adjustment.
–3–
CXA2581N
Pin Description
Pin
No.
Symbol
I/O
Equivalent circuit
Description
10k
1
LD
O
2
PD
I
1
APC amplifier output.
1k
55k
APC amplifier input.
20k
2
20k
1.1k
3
EQ_IN
I
3
1.1k
Equalizer circuit input.
1.2k
5k
5k
VC
VC
1.6k 1.6k
4
AC_SUM
O
4
5
GND
—
—
–4–
RFAC summing amplifier
output.
GND.
CXA2581N
Pin
No.
6
Symbol
A
I/O
Equivalent circuit
Description
I
15k
6
100µA
7
B
I
7
100µA
RF summing amplifier and
focus error amplifier input.
30k
8
C
I
8
47k
100µA
47k
9
9
D
VC
I
100µA
10
E
I
10
Tracking error amplifier input.
11
11
F
VC
I
200k
12
SW
I
CD-ROM/RW switching input.
RW when connected to VCC,
ROM when connected to GND.
200k
12
200k
VC
13
DVCC
—
14
DVC
O
—
Digital power supply.
150k
14
150k
25
–5–
(DVCC + GND)/2 voltage
output.
CXA2581N
Pin
No.
15
Symbol
RFAC
I/O
Equivalent circuit
O
FE
RFAC amplifier output.
15
2mA
16
Description
100
O
Focus error amplifier output.
50k
124
16
VC
124
17
17
FEI
I
18
TE
O
18
Focus error amplifier gain
adjustment. The gain is
adjusted by the external
resistance value connected
between this pin and Pin 16.
Tracking error amplifier output.
20k
19
20k
19
TE_BAL
I
Tracking error E and F gain
balance adjustment.
20k
VC
20
CE
O
Center error amplifier output.
50k
124
20
VC
124
21
21
CEI
I
–6–
Center error amplifier gain
adjustment.
The gain is adjusted by the
external resistance value
connected between this pin
and Pin 20.
CXA2581N
Pin
No.
Symbol
I/O
Equivalent circuit
—
22
VCC
—
23
RFG
I
Description
VCC. (AVCC)
20k
Sets the RFAC low frequency
gain.
23
VC
100µA
50µA
24
BST
I
20k
24
VC
Input for adjusting the
equalizer circuit boost
frequency with the control
voltage.
20k
25
VFC
I
25
VC
100µA
1.0V
124
26
RFC
I
27
VC
O
26
150k
27
150k 25
–7–
Input for adjusting the
equalizer circuit boost level.
Input for adjusting the
equalizer circuit boost
frequency with external
resistance.
(VCC + GND)/2 voltage
output.
CXA2581N
Pin
No.
28
Symbol
RFDC
I/O
Equivalent circuit
Description
RFDC amplifier output.
O
1mA
2k
124
28
VC
RFDC amplifier gain
adjustment.
The gain is adjusted by the
external resistance value
connected between this pin
and Pin 28.
124
29
RFDCI
I
29
30
124
30
DC_OFST
24k
I
RFDC amplifier offset control.
VC
10k
15k
–8–
CXA2581N
Description of Functions
• RFAC
The RF signal input by connecting capacitance to the EQ_IN pin is equalized, arithmetically amplified and then
output from the RFAC pin.
A
6
B
7
C
8
D
9
AC_SUM
VCC
AC
SUM
BST VFC
24 25 26 RFC
4
3
RF
0.1µ
5.1k
EQ
Amp
EQ_IN
15 RFAC
RFG 23
RW/ROM
BST = VCC
Low frequency gain
AC_SUM:
13dB (both ROM/RW)
VCA to RFAC ROM: 0dB
RW: 12dB
The EQ can be bypassed by connecting the BST control pin (Pin 24) to VCC.
In this case only the EQ block enters sleep mode and low power consumption mode (slim mode) is activated.
The low frequency gain is the same value as for EQ ON mode.
If RF (summing signal) is present at the pickup output pin, input the addition output signal to EQ_IN (Pin 3)
coupled by capacitance.
When using a pickup without a summing output function, perform addition with the AC SUM block and then
input the signal to EQ_IN (Pin 3) coupled by capacitance.
RW/ROM switching is done by the VCA block, so either input method can be used without problem.
The RW gain is 12dB higher than the ROM gain.
Gain [dB]
The VCA low frequency gain can be adjusted by the RFG
(Pin 23) voltage.
The control voltage vs. low frequency gain characteristics
are shown in the graph to the right.
VCA variable range
8
0
–8
VC – 1
VC
VC + 1
Vcnt
[V]
The RFAC pin (Pin 15) is an NPN transistor emitter follower output.
The maximum drive current is approximately 2mA.
If the load capacitance distorts the output waveform, connect resistance between Pin 15 and GND to increase
the drive current.
–9–
CXA2581N
• EQ
HPF
In
The diagram to the left shows the EQ internal block
diagram.
The EQ consists of a combination of HPF and LPF.
The HPF and LPF transmittance is the Bessel function.
The boost gain can be adjusted by adjusting the HPF
gain.
The boost frequency is adjusted by the RFC external
resistance value and the VFC control voltage value.
Amp
LPF
LPF
fc
Out
Boost
EQ CNT
RFC 26
VCC
VFC 25
BST 24
VC
VC
RFC resistance value: The cut-off frequency fo of each
filter is adjusted by the Pin 26
external resistance value.
The VFC voltage can be varied
using this fo as the reference.
VFC voltage: fo can be changed by the voltage applied
to Pin 25.
The boost gain can be adjusted by the BST pin control
voltage.
The control characteristics are shown in the graph below.
The cut-off frequency control characteristics are
shown in the graph below.
Boost Gain [dB]
fc [Hz]
8dB
1.5fo
fo
0dB
0.5fo
VC – 1.0
VC
VC + 1.0
Pin 24 (BST) voltage
Vcnt
[V]
VC – 1.0
VC
VC + 1.0
Pin 25 (VFC) voltage
Vcnt
[V]
• APC (Automatic Power Control)
When the laser diode is driven by a constant current, the optical power output has extremely large negative
temperature characteristics. Therefore, the current must be controlled to maintain the monitor photo diode
output at a constant level. This control is performed by the APC function.
VCC
56k
PD 2
1 LD
10k
55k
10k
10k
1.25V
– 10 –
1k
56k
CXA2581N
• Focus Error
The signals input to the A and C pins and the B and D pins are arithmetically amplified and the focus error
signal is output.
This circuit has RW/ROM switching and offset addition functions.
VC
ROM
100k
RW
FEI 17
23.5k
124
A 6
30k
C 8
16 FE
100k
124
50k
30k
30k
B 7
ROM
D 9
ROM
VOFST
RW
30k
47k
47k
200k
DVC
RW
200k
FE = Gain { (B + D) – (A + C) }
Low frequency gain ROM: 16dB
RW: 28dB
Cut-off frequency fc (typ.) ROM: 300kHz
RW: 300kHz
• Tracking Error
The signals input to the E and F pins are arithmetically amplified and the tracking error signal is output.
This circuit has RW/ROM switching and offset addition functions.
TE_BAL 19
TE = Gain (F – E)
ROM
63k
63k ROM
251k
10k
251k RW
DVCC
Low frequency gain
VOFST
20k
10
20k
11
F
E
VC
gm
RW
20k
18 TE
20k
gm
VC
TE balance adjustment
F – E low frequency gain = ±6dB
10k
31.5k
125.5k
ROM
RW
DVC
External resistance value vs. Low frequency gain
Low frequency
gain [dB]
22
16
12.5
10k
20k
– 11 –
30k
ROM: 16dB
RW: 28dB
Resistance value [Ω]
CXA2581N
• VC Buffer
• DVC Buffer
This outputs the VC ((1/2) VCC) voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the analog block VC voltage.
This outputs the 1/2 DVCC voltage.
The maximum output current is approximately ±3mA.
Use this voltage as the digital block VC voltage.
The output DC voltage of each block is level shifted
using the DVC voltage as the reference.
VCC
DVCC
40k
VC 27
40k
25
40k
DVC 14
25
40k
• RFDC
The signals input to the A, B, C and D pins are added, amplified and the RFDC signal is output. RW/ROM
switching and low frequency gain adjustment are possible.
VC
30
A 6
B 7
C 8
D 9
ROM
VC
RW
ROM
RW
24k
96k
15k
10k
RFDCI 29
28 RFDCO
ROM
15k
15k
5.1k
40k
RW
124
124
2k
15k
2.4k
DVC
3.3k
RFDC = Gain (A + B + C + D)
Low frequency gain ROM: 17.5dB
RW: 29.5dB
fc (Typ)
ROM: 20MHz
RW: 5MHz
The gain can be adjusted by the external resistance connected between Pins 28 and 29.
The output voltage offset can be adjusted by controlling the Pin 30 voltage.
– 12 –
CXA2581N
• Center Error
The signals input to the A and D pins and the B and C pins are arithmetically amplified and the center error
signal is output.
RW/ROM switching, low frequency gain adjustment and offset adjustment are possible.
VC
A 6
D 9
B 7
C 8
ROM
VOFST
RW
ROM
RW
12k
48k
200k
CEI 21
30k
20 CE
50k
30k
30k
ROM
30k
24k
24k
96k
DVC
RW
96k
The (B + C) – (A + D) signal is arithmetically amplified.
Low frequency gain ROM: 16dB
RW: 28dB
Cut-off frequency fc (typ.)
ROM: 200kHz
RW: 200kHz
• Output Offset Shift
The RFDC, FE, TE and CE output DC voltages are level shifted to the digital VC voltage (DVC).
The reference voltage of this IC is the VC voltage, and only the output reference voltage changes.
The maximum output voltage of each output signal should be kept to the digital VCC voltage (DVCC) or less in
order to protect the DSP_IC.
40k
40k
DVC
VC
VOFST
40k
40k
The VC and DVC voltages are arithmetically amplified and
output as the VOFST voltage.
The VOFST voltage serves as the level shift reference
voltage, and is distributed to each block.
VC
• SW
This controls the laser (APC) on/off, active/sleep mode, and RW/ROM mode switching.
Switching is controlled by the voltage applied to the SW pin.
SW high/low condition
High: VC + 1V to Vcc
Low: VC – 1V to GND
Active/Sleep
SW 12
SW
RW/ROM
APC_ON/OFF
The VC buffer is always in active mode even if it enters sleep mode.
In the function block, MODE_SW is always set to active mode.
Item
APC
Active/Sleep
RW/ROM
VCC
ON
Active
RW
VC or Hi-Z
OFF
Sleep
—
GND
ON
Active
ROM
Control
voltage
– 13 –
Symbol
O
Offset voltage ROM
10
– 14 –
O
Gac_ROM2
Low frequency gain ROM_cnt
Low frequency gain ROM_max Gac_ROM3
Low frequency gain RW_min
O
O
O
O
O O
Gac_EQoff
Fac_MinL
Frequency response EQ_OFF Fac_EQoff
Vac_L
Frequency response Min_L
Frequency response Min_H Fac_MinH
Vac_H
Low frequency gain EQ_off
Maximum output voltage H
Maximum output voltage L
18
19
20
21
22
23
O O
O
Low frequency gain RW_max Gac_RW3
17
16
O
Low frequency gain RW_cnt
O
Gac_ROM1
Low frequency gain ROM_min
Gac_RW1
O
AC_OfstRW
Offset voltage RW
Gac_RW2
15
14
13
12
11
AC_OfstROM
O O O O
SUM maximum output voltage L Vsum_L
9
O
O
O
O
50kHz
0.3Vp-p
0.3Vp-p
0.3Vp-p
20MHz
30MHz
10MHz
0.8Vp-p 100kHz
75mVp-p 50kHz
0.2Vp-p
0.35Vp-p 50kHz
0.3Vp-p 100kHz
0.8Vp-p 100kHz
1.4Vp-p 100kHz
–1.2V
1.2V
0V
–0.4V
0.4V
0V
E5
0V
1.7V 0V
1.0V
0V –1.0V
0V 1.7V
1.0V
0V
–1.0V
1.0V
0V
–1.0V
Fsum
SUM frequency response
10MHz 70mV
Gsum
SUM low frequency gain
0.1Vp-p
ACSUM_Ofst
SUM offset voltage
O O O O
Icc_Slp
Current consumption (Sleep)
0.1Vp-p 100kHz 70mV
0V
Icc_Dvcc
0V
E4
Current consumption (DVCC)
0V
E3
1.7V
O O O O
0V
0V
Hi-Z
E2
Bias conditions
V1
V1
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude
frequency E1
Switch conditions
O O O O
8
RFAC EQ
0V
E6
0V
15
15
15
15
15
15
15
15
15
15
15
15
15
15
4
4
4
4
4
22
13
22
22
MeasureE7 ment pin
45 mA
70 mA
5
8
mA
0.5 0.8 mA
30
50
11
13
15 dB
–1.2 –0.7 –0.2 V
3
0.2
15
30
Min. Typ. Max. Unit
1.4
1.6 1.7
V
5
–3
9
5
5
0
8
12
–8
8
0
dB
8
8
2
dB
dB
dB
11 dB
15 dB
–5 dB
11 dB
3
–5 dB
V
V
1.2
V
Pin voltage – AC_OfstROM –1.1 –0.9 –0.7 V
1
–0.5 2.5 5.5 dB
2
2
–2
Pin voltage – AC_OfstROM 0.8
20 log (Vout/Vin) – EQoff
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin)
20 log (Vout/Vin) – Gac_RW2– Gac_ROM2 5
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin) – Gac_RW2– Gac_ROM2 –11
20 log (Vout/Vin) – Gac_ROM2
20 log (Vout/Vin)
–8
–0.8 –0.3 0.2
–0.8 –0.3 0.2
20 log (Vout/Vin) – Gac_ROM2 –11
Pin voltage
Pin voltage
Pin voltage –ACSUM_Ofst –0.5 –0.3 –0.1 V
Pin voltage –ACSUM_Ofst
20 log (Vout/Vin) – Gsum –2.5 –0.5 0.5 dB
20 log (Vout/Vin)
Pin voltage
Pin current
Pin current
Pin current
Pin current
Measurement
conditions
(VCC = 1.7V, VEE = –1.7V, DVCC = 1.7V, DVEE = –1.7V)
Current consumption (Active, EQ Off) Icc_Aeqoff
Current consumption (Active, EQ On) Icc_Aeqon
Measurement item
SUM maximum output voltage H Vsum_H
7
6
5
4
3
2
1
RFAC SUM
Measure- Funcment No. tion
Electrical Characteristics
CXA2581N
– 15 –
Frequency response RW1
Frequency response RW2
Maximum output voltage H
Maximum output voltage L
41
42
43
44
Vfe_L
Vfe_H
Ffe_RW2
Ffe_RW1
Frequency response ROM2 Ffe_ROM2
40
Gfe_RW2
Low frequency gain RW2
Frequency response ROM1 Ffe_ROM1
Gfe_RW1
39
38
37
36
FE_OfstRW
Low frequency gain RW1
Offset voltage RW
34
FE_OfstROM
Gfe_ROM2
Offset voltage ROM
33
DC_Ofst1
Low frequency gain ROM2
Offset voltage 1
32
Vdc_L
Gfe_ROM1
Maximum output voltage L
31
Vdc_H
Fdc_RW
Fdc_ROM
Low frequency gain ROM1
Maximum output voltage H
30
35
Frequency response RW
Frequency response ROM
12.5mVp-p 100kHz
O O O O
Gdc_RW
Low frequency gain RW
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
0.3V
16
16
16
16
16
16
0V
28
28
28
28
28
0.3V
16
25mVp-p 300kHz
16
16
16
25mVp-p 300kHz
0
0
150 mV
150 mV
10
12
14 dB
14.5 17.5 20.5 dB
–150
–150
Min. Typ. Max. Unit
0.8
1
V
0
0
150 mV
150 mV
10
10
12
12
14 dB
14 dB
12.5 15.5 18.5 dB
12.5 15.5 18.5 dB
–150
–150
–0.7 –0.6 –0.5 V
–1.7 –1.5 –1.3 V
0.6
Pin voltage
Pin voltage
1.5 1.7
V
–1.7 –1.5 –1.3 V
1.3
20 log (Vout/Vin) – Gfe_RW2– Gfe_ROM2 –5.5 –2.5 0.5 dB
20 log (Vout/Vin) – Gfe_RW1– Gfe_ROM1 –5.5 –2.5 0.5 dB
20 log (Vout/Vin) – Gfe_ROM2 –5.5 –2.5 0.5 dB
20 log (Vout/Vin) – Gfe_ROM1 –5.5 –2.5 0.5 dB
20 log (Vout/Vin) – Gfe_ROM2
20 log (Vout/Vin) – Gfe_ROM1
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
20 log (Vout/Vin) – Gdc_RW – Gdc_ROM –4.5 –1.5 –0.5 dB
20 log (Vout/Vin) – Gdc_ROM –3.5 –0.5 0.5 dB
20 log (Vout/Vin) – Gdc_ROM
20 log (Vout/Vin)
Pin voltage
28
28
Pin voltage
Measurement
conditions
28
28
0V
–0.5V
0V
16
0V
E6
0.1Vp-p 300kHz
0V
E5
16
1kHz
25mVp-p
0V
0V
E4
MeasureE7 ment pin
0.1Vp-p 300kHz
1kHz
1kHz
0.1Vp-p
25mVp-p
1kHz
0.1Vp-p
–0.3V
O O O O
0V
0.3V
O O O O
O
12.5mVp-p
O O O O
5MHz
50mVp-p 20MHz
O O O O
O
O
50mVp-p 100kHz
O O O O
Gdc_ROM
Low frequency gain ROM
O
DC_OfstRW
Offset voltage RW
0V
E3
E2
Bias conditions
V1
V1
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude
frequency E1
Switch conditions
DC_OfstROM
Symbol
Offset voltage ROM
Measurement item
29
28
27
26
25
FE
24
RFDC
Measure- Funcment No. tion
CXA2581N
TE_OfstRW
Gte_ROM1
Gte_ROM2
Gte_RW1
Gte_RW2
Offset voltage RW
Low frequency gain ROM1
Low frequency gain ROM2
Low frequency gain RW1
Low frequency gain RW2
– 16 –
Frequency response RW1
Frequency response RW2
Maximum output voltage H
Maximum output voltage L
68
69
70
Vce_L
O
O O
Vce_H
O O
O O
O
O
Fce_RW2
Fce_RW1
Frequency response ROM2 Fce_ROM2
Frequency response ROM1 Fce_ROM1
O O
Gce_RW2
O
O
O
O
Low frequency gain RW2
O
Gce_RW1
Low frequency gain RW1
O O
Gce_ROM2
Low frequency gain ROM2
25mVp-p
O
1kHz
1kHz
1kHz
1kHz
1kHz
25mVp-p 200kHz
25mVp-p 200kHz
O
O
0.1Vp-p 200kHz
0.1Vp-p 200kHz
25mVp-p
O
0.1Vp-p
0.1Vp-p
Gce_ROM1
Low frequency gain ROM1
O
CE_OfstRW
Offset voltage RW
O
CE_OfstROM
Offset voltage ROM
O
Vte_L
Maximum output voltage L
O
O
Vte_H
Maximum output voltage H
67
66
65
64
63
62
61
60
59
58
57
0.1Vp-p
O O
Gte2
25mVp-p 100kHz
O O
1kHz
25mVp-p 100kHz
O
Balance gain 2
56
1kHz
0.1Vp-p 100kHz
0.1Vp-p
Balance gain 1
55
Fte_RW2
O
O
25mVp-p
O O
1kHz
1kHz
1kHz
0.1Vp-p 100kHz
25mVp-p
0.1Vp-p
O
O
0.1Vp-p
O O
Frequency response RW2
54
Fte_RW1
O
O
O
0V
E6
Measure-
0V
–1.0V
1.0V
0V
18
18
18
18
18
18
18
18
18
18
18
18
18
E7 ment pin
0.5V
0.5V
20
20
20
20
20
20
20
20
20
20
20
20
0V
E5
0V
0V
E4
18
0V
E3
0.6V
0.6V
0V
0V
O
E2
Bias conditions
V1
V1
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude
frequency E1
Switch conditions
Gte1
Frequency response RW1
Frequency response ROM2 Fte_ROM2
Frequency response ROM1 Fte_ROM1
TE_OfstROM
Symbol
Offset voltage ROM
Measurement item
53
52
51
50
49
48
47
46
CE
45
TE
Measure- Funcment No. tion
10
10
13
13
–500
–200
12
12
16
16
0
0
14 dB
14 dB
19 dB
19 dB
500 mV
200 mV
Min. Typ. Max. Unit
dB
V
–4 dB
8
1.5 1.7
–6
6
0
0
150 mV
150 mV
12
14 dB
14 dB
Pin voltage
Pin voltage
–1.7 –1.5 –1.3 V
1.15 1.35 1.55 V
20 log (Vout/Vin) – Gce_RW2– Gce_ROM2 –3.8 –2.3 –0.8 dB
20 log (Vout/Vin) – Gce_RW1– Gce_ROM1 –3.8 –2.3 –0.8 dB
20 log (Vout/Vin) – Gce_ROM2 –3.8 –2.3 –0.8 dB
20 log (Vout/Vin) – Gce_ROM1 –3.8 –2.3 –0.8 dB
20 log (Vout/Vin) – Gce_ROM2 10
12
12.5 15.5 18.5 dB
12.5 15.5 18.5 dB
–150
–150
–1.7 –1.5 –1.3 V
1.3
–8
4
20 log (Vout/Vin) – Gce_ROM1 10
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
Pin voltage
Pin voltage
E, F gain difference
E, F gain difference
20 log (Vout/Vin) – Gte_RW2– Gte_ROM2 –3.5 –1.5 0.5 dB
20 log (Vout/Vin) – Gte_RW1– Gte_ROM1 –3.5 –1.5 0.5 dB
20 log (Vout/Vin) – Gte_ROM2 –3.2 –1.2 0.8 dB
20 log (Vout/Vin) – Gte_ROM1 –3.2 –1.2 0.8 dB
20 log (Vout/Vin) – Gte_ROM2
20 log (Vout/Vin) – Gte_ROM1
20 log (Vout/Vin)
20 log (Vout/Vin)
Pin voltage
Pin voltage
Measurement
conditions
CXA2581N
77
76
75
74
73
72
DVC AVC
71
APC
Measure- Funcment No. tion
Vapc_off
Iapc_max O O
APC OFF voltage
Maximum output current
Output voltage
Vdvc
Vavc
Vapc3
Output voltage 3
O
O
O
Vapc2
O
Output voltage 2
Output voltage
Switch conditions
Hi-Z
O
0V
0V
Vapc1 +
20mV
Vapc1 –
20mV
0V
E2
0V
E3
Bias conditions
V1
V1
S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 amplitude
frequency E1
Vapc1
Symbol
Output voltage 1
Measurement item
0V
E4
0V
E5
0V
E6
0V
14
27
1
1
1
1
1, 2
MeasureE7 ment pin
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Pin voltage
Input at which output voltage = 0V
Measurement
conditions
V
V
–100 0
–100 0
100 mV
100 mV
–0.55 –0.15 0.25 V
1.4 1.6 1.7
–1 –0.75 –0.5 V
1
150 300 mV
0.5 0.75
0
Min. Typ. Max. Unit
CXA2581N
– 17 –
CXA2581N
Notes on Supply Voltage
6.5
Vcc (Pin 22) [V]
6
5.5
5
4.5
4
2
2.5
3.5
3
DVcc (Pin 13) [V]
VCC voltage value at which the waveform is clipped when DVCC is fixed
The voltage difference between VCC (Pin 22) and DVCC (Pin 13) should be kept to the value shown in the graph
above or less.
Example) When DVCC = 2.5V
From the graph, VCC = 4.5V
Therefore, VCC should be from 3.4 to 4.5V.
(3.4V is the minimum operating voltage for the IC.)
Electrical Characteristics Measurement Circuit
VCC
VCC
10k
5.1k
E6
DVCC
DVC
RFAC
5
6
7
8
9
10
11
12
13
14
15
S1
S2
S3
S4
10k
VEE S5
S6
S7
S8
20k
S9
S10
TE_BAL
CEI
20k
S11
10k
DVCC
E2
0.8mA
0.1µ
VEE VCC
VCC
VEE
V1
E1
– 18 –
FE
SW
4
FEI
F
3
TE
E
2
CE
VCC
D
1
VC
RFG
16
C
17
BST
18
B
19
VFC
20
A
21
RFC
22
GND
23
AC_SUM
24
RFDCO
25
EQ_IN
26
10k
RFDCI
27
E7
E3
PD
28
E4
DC_OFST
29
E5
10k 100k
10k
200k
5.1k
LD
30
S12
CXA2581N
RFDC
OUT VC
0.1µ
Application Circuits
DVCC
DVC
RFAC
5
6
7
8
9
10
11
12
13
14
15
F
TE
CE
0.1µ
LD
PD IN
A
B
C
D
E
Drive
RF SUM RF SUM inputs the signal when A, B, C
and D are added by the front and PD.
FE
SW
4
FEI
F
3
TE_BAL
E
2
CEI
VCC
D
1
VC
RFG
16
C
17
BST
18
B
19
VFC
20
A
21
RFC
22
GND
23
AC_SUM
24
RFDCO
25
EQ_IN
26
RFDCI
27
PD
28
FE
OUT
DC_OFST
29
TE
OUT
LD
30
CE
OUT
VCC
DVCC DVC
MODE
RFAC
Control
OUT
<CXA2581N>
VCC
4
3
AC
SUM
A
VC
A
B
C
D
VFC
BST
RFC
RFG
AC_SUM
<OP>
0.1µ
EQ_IN
0.1µ
VCC
23
24 26 25
AC
VCA
EQ
<DSP>
15
RW/ROM
VC
30
DVCC
B
D
A
A
B
B
C
C
D
D
29
28
RW/ROM
VC
VC
VC
RFAC
EQ_ON/OFF
RF
C
RFAC
DC_OFST
RFDCI
RFDCO
RFDC
DVC
6
DVCC
7
17
16
8
VC
FE
FE
DVC
VOFST
9
FEI
VC
19 TE_BAL
RW/ROM
VOFST
F
F
F
E
E
RW/ROM
VC
10
gm
11
gm
DVCC
VC
E
18
TE
TE
VC
VOFST
RW/ROM
VC
B
DVC
C
A
D
SW 12
PD
LD
2
APC
DVCC
21
20
VC
RW/ROM
APC-OFF (Hi-Z)
DVC
RW/ROM
VC
(H/L)
VCC
DVC
1
CE
CE
VOFST
VC
VC
CEI
13
DVCC
VCC
DVC
VC GND VCC
VC
22
VCC
5
27
GND
14
VC
DVC
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
– 19 –
CXA2581N
Characteristics Graphs
EQ boost voltage vs. Frequency response
EQ Rfc resistance value vs. Frequency response
12
8
Vfc = VC
Vbst = VC, Vfc = VC
Rfc = 100kΩ
Vboost = 1.0V
Rfc = 20kΩ Rfc = 5.1kΩ
8
Rfc = 100kΩ
5
6
4
4
[dB]
[dB]
6
3
0
1
–2
0
–4
–1
–6
10
1
100
Rfc = 100kΩ
Vboost = 0V
2
2
–2
0.1
Rfc = 5.1kΩ
Vboost = 1.0V
10
7
Rfc = 5.1kΩ
Vboost = 0V
Rfc = 100kΩ
Vboost = –1.0V
–8
0.1
10
1
100
[MHz]
[MHz]
EQ Vfc vs. frequency response
RF AC frequency response
24
8
Vbst = VC
Rfc = 20kΩ
Vfc = 0V
7
6
21
Rfc = 20kΩ
Vfc = 1V
EQ_Pass
RW mode
18
Rfc = 20kΩ
Vfc = –1V
5
15
AC SUM
12
[dB]
4
[dB]
Rfc = 5.1kΩ
Vboost = –1.0V
3
9
2
6
1
3
0
0
–1
–3
–2
EQ_Pass
ROM mode
–6
0.1
1
10
100
0.1
1
[MHz]
10
100
[MHz]
FE frequency response
RF DC frequency response
38
34
35
31
32
28
RW
25
26
22
[dB]
[dB]
RW
29
23
20
19
16
ROM
17
13
14
10
11
7
8
0.1
1
10
100
4
0.01
ROM
0.1
1
[MHz]
[MHz]
– 20 –
10
CXA2581N
TE frequency response
APC I/O characteristics
35
5.5
32
5.0
RW
4.5
VLD – Output voltage [V]
29
26
[dB]
23
20
17
16
ROM
Vcc = 5.5V
4.0
3.5
3.0
2.5
Vcc = 3.4V
2.0
13
1.5
10
1.0
7
0.01
0.1
1
10
[MHz]
0.5
0.05
0.1
0.15
VPD – Input voltage [V]
CE frequency response
34
31
28
RW
25
[dB]
22
19
16
ROM
13
10
7
4
0.01
1
0.1
10
[MHz]
– 21 –
0.2
0.25
CXA2581N
Package Outline
Unit: mm
30PIN SSOP (PLASTIC)
+ 0.2
1.25 – 0.1
∗9.7 ± 0.1
1
+ 0.1
0.22 – 0.05
7.6 ± 0.2
16
∗5.6 ± 0.1
30
0.10
A
15
+ 0.05
0.15 – 0.02
0.65
0.13 M
0.5 ± 0.2
0.1 ± 0.1
0° to 10°
NOTE: Dimension “∗” does not include mold protrusion.
DETAIL A
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
SSOP-30P-L01
LEAD TREATMENT
SOLDER/PALLADIUM
PLATING
EIAJ CODE
SSOP030-P-0056
LEAD MATERIAL
42/COPPER ALLOY
PACKAGE MASS
0.1g
JEDEC CODE
NOTE : PALLADIUM PLATING
This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
– 22 –
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