Mobile Intel® 965 Express
Chipset Family
External Design Specification (EDS) - Volume 1 of 2
This document is the first of the two volumes. Refer to doc
ref# 644937 for the second volume.
Revision 2.0
February 2007
Intel Confidential
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Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The Mobile Intel® 965 Express Chipset Family may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
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Copyright © 2005 - 2007, Intel Corporation. All rights reserved.
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External Design Specification
Contents
1
Introduction ............................................................................................................ 19
1.1
Overview ......................................................................................................... 19
1.2
Mobile Intel® PM965 Express Chipset Feature Support ........................................... 20
1.2.1 Processor Support .................................................................................. 20
1.2.2 System Memory Support ......................................................................... 20
1.2.3 Discrete Graphics using PCI Express* Graphics Attach Port .......................... 21
1.2.4 DMI...................................................................................................... 21
1.2.5 Power Management ................................................................................ 21
1.2.6 Security and Manageability (Intel® Active Management Technology)............. 21
1.2.7 Package ................................................................................................ 22
1.3
Mobile Intel® GM965 Express Chipset Feature Support .......................................... 22
1.3.1 PCI Express Graphics Attach Port.............................................................. 22
1.3.2 Internal Graphics ................................................................................... 22
1.3.3 Power Management ................................................................................ 23
1.4
Mobile Intel® GL960 Express Chipset Feature Support ........................................... 24
1.4.1 Processor Support .................................................................................. 24
1.4.2 System Memory Support ......................................................................... 24
1.4.3 Internal Graphics ................................................................................... 24
1.4.4 ICH Support .......................................................................................... 24
1.4.5 Power Management ................................................................................ 24
1.4.6 Intel® AMT ........................................................................................... 24
1.5
Terminology ..................................................................................................... 25
1.6
Reference Documents ........................................................................................ 26
2
Signal Description ................................................................................................... 29
2.1
Host Interface................................................................................................... 29
2.1.1 Host Interface Signals............................................................................. 30
2.2
DDR2 Memory Interface ..................................................................................... 33
2.2.1 DDR2 Memory Channel A Interface ........................................................... 33
2.2.2 DDR2 Memory Channel B Interface ........................................................... 34
2.2.3 DDR2 Memory Common Signals ............................................................... 35
2.2.4 DDR2 Memory Reference and Compensation .............................................. 36
2.3
PCI Express* Based Graphics Interface Signals...................................................... 36
2.3.1 Serial DVO and PCI Express Based Graphics Signal Mapping......................... 36
2.4
DMI – (G)MCH to ICH Serial Interface .................................................................. 37
2.5
Integrated Graphics Interface Signals .................................................................. 38
2.5.1 CRT DAC SIGNALS ................................................................................. 38
2.5.2 Analog TV-out Signals............................................................................. 39
2.5.3 LVDS Signals ......................................................................................... 40
2.5.4 Serial DVO Interface ............................................................................... 41
2.5.5 Display Data Channel (DDC) and GMBUS Support ....................................... 42
2.6
Intel® Management Engine Interface Signals ........................................................ 43
2.7
PLL Signals....................................................................................................... 43
2.8
Reset and Miscellaneous Signals.......................................................................... 44
2.9
Non-Critical to Function (NCTF) ........................................................................... 45
2.10 Power and Ground............................................................................................. 45
3
Host
3.1
3.2
3.3
3.4
Interface ......................................................................................................... 49
FSB Source Synchronous Transfers ...................................................................... 49
FSB IOQ Depth ................................................................................................. 49
FSB OOQ Depth ................................................................................................ 49
FSB AGTL+ Termination ..................................................................................... 49
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3.5
3.6
3.7
FSB Dynamic Bus Inversion.................................................................................49
FSB Interrupt Overview ......................................................................................50
APIC Cluster Mode support..................................................................................50
4
System Address Map ................................................................................................51
4.1
Legacy Address Range........................................................................................53
4.1.1 DOS Range (0000_0000h – 0009_FFFFh)...................................................55
4.1.2 Legacy Video Area (000A_0000h to 000B_FFFFh)........................................55
4.1.3 Expansion Area (000C_0000h to 000D_FFFFh) ...........................................55
4.1.4 Extended System BIOS Area (000E_0000h to 000E_FFFFh) ..........................56
4.1.5 System BIOS Area (000F_0000h to 000F_FFFFh) ........................................56
4.1.6 Programmable Attribute Map (PAM) Memory Area Details .............................57
4.2
Main Memory Address Range (1 MB to TOLUD) ......................................................57
4.2.1 ISA Hole (15 MB to 16 MB) ......................................................................58
4.2.2 TSEG ....................................................................................................59
4.2.3 Pre-allocated Memory..............................................................................59
4.3
PCI Memory Address Range (TOLUD to 4 GB) ........................................................60
4.3.1 APIC Configuration Space (FEC0_0000h to FECF_FFFFh) ..............................62
4.3.2 HSEG (FEDA_0000h to FEDB_FFFFh) .........................................................62
4.3.3 FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF) .............................62
4.3.4 High BIOS Area ......................................................................................62
4.4
Main Memory Address Space (4 GB to TOUUD) ......................................................63
4.4.1 Memory Re-Map Background ....................................................................63
4.4.2 Memory Remapping (or Reclaiming) ..........................................................64
4.5
PCI Express Configuration Address Space..............................................................64
4.5.1 PCI Express Graphics Attach ....................................................................64
4.5.2 Graphics Aperture...................................................................................64
4.6
Graphics Memory Address Ranges........................................................................65
4.6.1 Graphics Register Ranges ........................................................................65
4.6.2 I/O Mapped Access to Device 2 MMIO Space ..............................................65
4.7
System Management Mode (SMM) .......................................................................67
4.7.1 SMM Space Definition ..............................................................................67
4.8
SMM Space Restrictions ......................................................................................68
4.8.1 SMM Space Combinations ........................................................................68
4.8.2 SMM Control Combinations.......................................................................68
4.8.3 SMM Space Decode and Transaction Handling.............................................69
4.8.4 Processor WB Transaction to an Enabled SMM Address Space .......................69
4.9
Memory Shadowing............................................................................................69
4.10 I/O Address Space .............................................................................................69
4.10.1 PCI Express I/O Address Mapping .............................................................70
4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping .......................................71
4.11.1 Legacy VGA and I/O Range Decode Rules ..................................................71
5
System Memory Controller .......................................................................................73
5.1
Functional Overview ...........................................................................................73
5.2
Memory Channel Access Modes............................................................................73
5.2.1 Dual Channel Interleaved Mode ................................................................74
5.2.2 Dual Channel Non-Interleaved Mode..........................................................75
5.3
DRAM Technologies and Organization ...................................................................75
5.3.1 Rules for Populating SO-DIMM Slots ..........................................................76
5.3.2 Pin Connectivity for Dual Channel Modes....................................................76
5.4
DRAM Clock Generation ......................................................................................76
5.5
DDR2 On Die Termination ...................................................................................77
5.6
DRAM Power Management ..................................................................................77
5.6.1 Self Refresh Entry and Exit operation ........................................................77
5.6.2 Dynamic Power Down Operation ...............................................................77
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5.7
5.6.3 DRAM I/O Power Management ................................................................. 78
System Memory Throttling.................................................................................. 78
6
PCI Express Based External Graphics ...................................................................... 79
6.1
PCI Express Architecture .................................................................................... 79
6.1.1 Layering Overview.................................................................................. 79
6.1.2 Transaction Layer................................................................................... 79
6.1.3 Data Link Layer...................................................................................... 79
6.1.4 Physical Layer........................................................................................ 80
6.2
PCI Express Configuration Mechanism .................................................................. 80
6.3
Serial Digital Video Output (SDVO) ...................................................................... 81
6.3.1 SDVO Capabilities................................................................................... 81
6.3.2 Concurrent SDVO/PCI Express* Operation ................................................. 82
6.4
SDVO Modes..................................................................................................... 84
7
Integrated Graphics Controller ................................................................................ 87
7.1
Graphics Processing........................................................................................... 88
7.1.1 3D Graphics Pipeline ............................................................................... 88
7.1.2 3D Engine ............................................................................................. 88
7.1.3 2D Engine ............................................................................................. 93
7.1.4 Video Engine ......................................................................................... 94
8
Display Interfaces ................................................................................................... 99
8.1
Display Overview .............................................................................................. 99
8.2
Planes ............................................................................................................. 99
8.2.1 DDC (Display Data Channel) .................................................................. 100
8.3
Display Pipes .................................................................................................. 100
8.3.1 Clock Generator Units (DPLL)................................................................. 100
8.4
Display Ports .................................................................................................. 101
8.4.1 Analog Display Port Characteristics ......................................................... 102
8.4.2 Dedicated LFP LVDS Port ....................................................................... 102
8.4.3 SDVO Digital Display Port ...................................................................... 106
8.5
Multiple Display Configurations.......................................................................... 107
9
Power Management ............................................................................................... 109
9.1
Overview ....................................................................................................... 109
9.2
ACPI States Supported..................................................................................... 109
9.2.1 System ............................................................................................... 109
9.2.2 Processor ............................................................................................ 110
9.2.3 Internal Graphics Display Device Control ................................................. 110
9.2.4 Internal Graphics Adapter...................................................................... 110
9.3
Interface Power States Supported ..................................................................... 110
9.3.1 PCI Express Link States......................................................................... 110
9.3.2 Main Memory States ............................................................................. 111
9.4
Power Management Features ............................................................................ 111
9.4.1 Dynamic Power Management on I/O ....................................................... 111
9.4.2 System Memory Power Management....................................................... 112
9.5
Chipset State Combinations .............................................................................. 113
9.5.1 CPU Sleep (H_SLPCPU#) Signal Definition ............................................... 114
9.6
CLKREQ# - Mode of Operation .......................................................................... 114
9.7
Intel® Display Power Saving Technology (Intel® DPST) 3.0.................................. 114
9.8
Intel® Smart 2D Display Technology (Intel® S2DDT) .......................................... 115
9.9
Dynamic Display Power Optimization* (D2PO) Panel Support ................................ 115
9.10 Intel® Automatic Display Brightness.................................................................. 115
9.11 Intel® Display Refresh Rate Switching ............................................................... 115
9.12 Intel® Dynamic Front Side Bus Frequency Switching............................................ 115
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9.13
9.14
Graphics Render Standby.................................................................................. 115
PWROK Timing Requirements for Power-up, Resume from S3 ................................ 116
10
Absolute Maximum Ratings .................................................................................... 117
10.1 Power Characteristics ....................................................................................... 119
10.2 Thermal Characteristics .................................................................................... 122
11
Thermal Management ............................................................................................ 123
11.1 Internal Thermal Sensor ................................................................................... 123
11.1.1 Internal Thermal Sensor Operation.......................................................... 123
11.1.2 Sample Programming Model ................................................................... 125
11.1.3 Hysteresis Operation ............................................................................. 125
11.2 Thermal Throttling Options................................................................................ 126
11.3 External Thermal Sensor Interface Overview ....................................................... 126
11.4 THERMTRIP# Operation .................................................................................... 127
12
DC Characteristics.................................................................................................. 129
12.1 I/O Buffer Supply Voltages................................................................................ 129
12.2 Signal Groups ................................................................................................. 129
12.3 General DC Characteristics................................................................................ 133
12.4 CRT DAC DC Characteristics .............................................................................. 139
12.5 TV DAC DC Characteristics ................................................................................ 139
13
AC Characteristics .................................................................................................. 141
13.1 Input Clock AC Characteristics ........................................................................... 141
13.2 Host Interface Timing ....................................................................................... 143
13.3 System Memory Interface Timing....................................................................... 145
13.3.1 DDR2 Interface Timings......................................................................... 145
13.4 PCI Express Timing .......................................................................................... 150
13.5 LVDS Interface Timing...................................................................................... 151
13.6 CRT DAC Interface Timing................................................................................. 153
13.7 TV DAC Interface Timing................................................................................... 153
13.8 Controller Link Interface Timing ......................................................................... 154
13.9 Display Data Channel (DDC) and GMBUS Interface Timing..................................... 155
14
Signal Quality Specifications/Parameters .............................................................. 157
15
AC Timing Diagrams............................................................................................... 163
15.1 Input Clocks.................................................................................................... 163
15.2 Host Interface ................................................................................................. 164
15.3 PCI Express Interface ....................................................................................... 166
15.4 System Memory Interface ................................................................................. 167
15.4.1 DDR2 Interface .................................................................................... 167
15.5 LVDS Interface ................................................................................................ 172
15.6 Miscellaneous .................................................................................................. 173
15.7 Chipset Family Power Sequencing ...................................................................... 174
15.7.1 TV DAC ............................................................................................... 174
15.7.2 Mobile Intel 965 Express Chipset General Power Sequencing Rules .............. 177
16
Clocking ................................................................................................................. 179
16.1 Overview ........................................................................................................ 179
16.2 (G)MCH Reference Clocks ................................................................................. 179
16.3 Host/Memory/Graphics Core Clock Frequency Support .......................................... 179
17
Testability.............................................................................................................. 181
17.1 Test Mode Entry .............................................................................................. 181
17.2 Voltage Rail Information ................................................................................... 183
17.2.1 XOR Chain Differential Pairs ................................................................... 183
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17.3
17.4
17.2.2 XOR Chain Exclusion List ....................................................................... 183
XOR Chain Test Mode for Different Product Configurations .................................... 187
17.3.1 DRAM Channel Configurations ................................................................ 187
17.3.2 Various PCI Express Graphics/DMI Lane Configurations ............................. 187
17.3.3 PCI Express Graphics/SDVO Configurations.............................................. 187
17.3.4 LVDS Channel Configurations ................................................................. 188
17.3.5 I2C and Other HVCMOS Configurations.................................................... 188
XOR Chain Connectivity/Ordering ...................................................................... 188
18
Chipset Strapping Configuration ............................................................................ 205
19
Ballout and Package Information........................................................................... 207
19.1 Chipset Ballout Diagrams ................................................................................. 207
19.2 Chipset Ball List (Listed by Interface) ................................................................. 211
19.2.1 Analog TV-out...................................................................................... 211
19.2.2 CRT DAC ............................................................................................. 211
19.2.3 DDC & GMBus...................................................................................... 211
19.2.4 DMI.................................................................................................... 211
19.2.5 Host Interface...................................................................................... 212
19.2.6 LVDS .................................................................................................. 213
19.2.7 Intel Management Engine Interface ........................................................ 213
19.2.8 Memory Interface ................................................................................. 213
19.2.9 No Connects ........................................................................................ 216
19.2.10PCI Express Based Graphics................................................................... 216
19.2.11PLL..................................................................................................... 217
19.2.12Power and Ground................................................................................ 217
19.2.13Reserved and Test................................................................................ 223
19.2.14Strappings .......................................................................................... 223
19.2.15Reset and Miscellaneous........................................................................ 224
19.3 Chipset Ball List (Listed by Ball) ........................................................................ 224
19.4 Chipset Package Information ............................................................................ 236
20
I/O Buffer and IBIS Model Documentation ............................................................ 239
Figures
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Santa Rosa Platform with Mobile Intel® 965 Express Chipset Family (G)MCH ................... 19
System Address Ranges............................................................................................ 53
DOS Legacy Address Range....................................................................................... 54
Main Memory Address Range (0 to 4 GB) .................................................................... 58
PCI Memory Address Range....................................................................................... 61
Graphics Register Memory and I/O Map ...................................................................... 66
Intel Flex Memory Technology Operation ..................................................................... 74
System Memory Styles ............................................................................................. 75
PCI Express Related Register Structures in (G)MCH ...................................................... 80
SDVO Conceptual Block Diagram................................................................................ 81
SDVO/PCI Express Non-Reversed Configurations .......................................................... 83
SDVO/PCI Express* Reversed Configurations ............................................................... 83
(G)MCH Graphics Controller Block Diagram.................................................................. 87
MPEG-2 Decode Stage .............................................................................................. 95
WMV9 Decode Stage ................................................................................................ 96
Mobile Intel GM965/GL960 Chipset Display Block Diagram ............................................. 99
LVDS signals and Swing Voltage .............................................................................. 104
LVDS Clock and Data Relationship ............................................................................ 104
Panel Power Sequencing ......................................................................................... 105
Upon Power-up and Resume from S3/S4/S5 .............................................................. 116
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Platform External Sensor ......................................................................................... 127
Measurement Points for Differential Clocks................................................................. 163
Single-Ended Clock Waveform .................................................................................. 164
System Bus Test Fixture.......................................................................................... 164
System Bus Common Clock Waveform ...................................................................... 165
System Bus Source Synchronous Strobe Waveform for Address .................................... 165
System Bus Source Synchronous Strobe Waveform for Data ........................................ 166
PCI Express Transmitter Eye .................................................................................... 166
SDQ Setup/Hold Relationship to/from SDQS/SDQS# (Read Operation) .......................... 167
PCI Express Receiver Eye ........................................................................................ 167
SDQ and SDM Valid before and after SDQS/SDQS# (Write Operation) ........................... 168
Write Preamble Duration ......................................................................................... 168
Write Postamble Duration ........................................................................................ 168
Command Signals Valid before and after SCK Rising Edge ............................................ 168
SCKE Valid before and after SCK Rising Edge ............................................................. 169
SCS# Valid before and after SCK Rising Edge ............................................................. 169
SODT Valid before SCK Rising Edge .......................................................................... 169
Clock Cycle Time .................................................................................................... 170
Skew between any System Memory Differential Clock Pair (SCK/SCK#) ......................... 170
SCK High Time ....................................................................................................... 170
SCK Low Time........................................................................................................ 171
SDQS Falling Edge Output Access Time to SCK Rising Edge .......................................... 171
SDQS Falling Edge Output Access Time from SCK Rising Edge ...................................... 171
SCK Rising Edge Output Access Time to the First SDQS Rising Edge .............................. 172
SCK Rising Edge Output Access Time to the SDQS Preamble Falling Edge....................... 172
LVDS Load and Transition Times............................................................................... 172
Transmitting Position (Data to Strobe) ...................................................................... 173
Overshoot and Undershoot Diagram and Ringback Illustration ...................................... 173
Receiver Window Under System Load for Simulations Only........................................... 174
Receiver Margins Under System Load for Validation Only ............................................. 174
GPIO Power-Up Sequencing ..................................................................................... 175
GPIO Power-Down Sequencing ................................................................................. 176
HVSYNC Power-Up Sequencing................................................................................. 176
HVSYNC Power-Down Sequencing............................................................................. 177
XOR Chain Test Mode Entry Events Diagram .............................................................. 181
ALLZ Test Mode Entry Events Diagram ...................................................................... 182
XOR Test Mode Initialization Cycle ............................................................................ 183
Chipset Ballout Diagram (Top View) Upper Left Quadrant............................................. 207
Chipset Ballout Diagram (Top View) Upper Right Quadrant........................................... 208
Chipset Ballout Diagram (Top View) Lower Left Quadrant............................................. 209
Chipset Ballout Diagram (Top View) Lower Right Quadrant........................................... 210
Chipset Drawing ..................................................................................................... 237
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Tables
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SDVO and PCI Express* Based Graphics Port Signal Mapping ......................................... 36
Expansion Area Memory Segments ............................................................................. 56
Extended System BIOS Area Memory Segments........................................................... 56
System BIOS Area Memory Segments......................................................................... 57
Pre-allocated Memory Example for 512-MB DRAM, 64-MB VGA, and 1-MB TSEG ............... 59
SMM Space Definition Summary................................................................................. 67
SMM Space Table ..................................................................................................... 68
SMM Control Table ................................................................................................... 69
System Memory Organization Support for DDR2........................................................... 73
DDR2 Dual Channel Pin Connectivity........................................................................... 76
DDR2 Single Channel Pin Connectivity ........................................................................ 76
Concurrent SDVO / PCI Express* Configuration Strap Controls ....................................... 82
Configuration-wise Mapping of SDVO Signals on the PCI Express Interface ...................... 84
Display Port Characteristics ..................................................................................... 101
Analog Port Characteristics ...................................................................................... 102
Panel Power Sequencing Timing Parameters .............................................................. 106
Targeted Memory State Conditions ........................................................................... 113
G, S and C State Combinations ................................................................................ 113
D, S, and C State Combinations ............................................................................... 113
Absolute Maximum Ratings1.................................................................................... 117
DDR2 (533 MTs/667 MTs) Power Characteristics ........................................................ 121
VCC Auxiliary Rail Power Characteristics.................................................................... 122
Mobile Intel 965 Express Chipset Family Package Thermal Resistance ........................... 122
Signal Groups........................................................................................................ 130
DC Characteristics.................................................................................................. 133
CRT DAC DC Characteristics: Functional Operating Range
(VCCADAC = 3.3 V ±5%)........................................................................................ 139
TV DAC DC Characteristics: Functional Operating Range
(VCCATVDAC [A,B,C] = 3.3 V +/- 5%) ..................................................................... 139
Host Interface AC Characteristics for 533MHz............................................................ 143
Host Interface AC Characteristics for 667 MHz........................................................... 144
Host Interface AC Characteristics for 800 MHz............................................................ 144
DDR2 Interface AC Characteristics at 533 MTs, VCCSM = 1.8 V ± 5% ........................... 145
(G)MCH DDR2 533-MTs Write Latency Values ............................................................ 147
DDR2 533-MTs tSUmch and tHDmch Derating ........................................................... 147
DDR2 Interface AC Characteristics at 677 MTs, VCCSM = 1.8 V±5% ............................ 147
(G)MCH DDR2 667-MTs Write Latency Values ............................................................ 149
DDR2-667-MTs tSUmch and tHDmch Derating ........................................................... 150
PCI Express interface (Discrete Graphics or SDVO Port) .............................................. 150
SDVO Interface Timings .......................................................................................... 150
LVDS Interface AC Characteristics at Various Frequencies............................................ 151
CRT DAC AC Characteristics..................................................................................... 153
TV DAC AC Characteristics....................................................................................... 154
Controller Link AC Characteristics ............................................................................. 154
DDC and GMBUS Characteristics ............................................................................. 155
Signal Quality Parameters ....................................................................................... 157
Signal Quality Specifications for AGTL+Signal Groups ................................................. 160
FSB Source Synch AC Specifications AGTL+ Signal Group
(533-MHz, 667-MHz and 800-MHz FSB) - Simulation Specification ................................ 161
FSB Source Synch AC Specifications AGTL+ Signal Group (667-MHz and 800-MHz FSB) Validation Specification ........................................................................................... 161
Host/Memory/Graphics Clock Frequency Support for 1.05-V Core Voltage for the Mobile Intel
GM965 and GL960 Express Chipsets ......................................................................... 179
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Host/Memory/Graphics Clock Frequency Support for 1.05-V Core Voltage for the Mobile Intel
GM965/GM965 (mini-note)/GM965(sub-note), GL960 and PM965 Express Chipsets ......... 180
Mobile Intel GM965/PM965/GL960 Express Chipset Strap Information for Testability ....... 182
XOR Chain Exclusion List ......................................................................................... 183
Mobile Intel GM965/PM965 Chipset PCI Express Graphics Lanes Active for SDVO Configuration
for Testability......................................................................................................... 187
XOR Chain Connectivity/Ordering FSB1 ..................................................................... 188
XOR Chain Connectivity/Ordering FSB2 ..................................................................... 190
XOR Chain Connectivity/Ordering FSB3 ..................................................................... 191
XOR Chain Connectivity/Ordering FSB4 ..................................................................... 192
XOR Chain Connectivity/Ordering GPIO1.................................................................... 192
XOR Chain Connectivity/Ordering GPIO2.................................................................... 193
XOR Chain Connectivity/Ordering LVDS ..................................................................... 193
XOR Chain Connectivity/Ordering DMI ....................................................................... 194
XOR Chain Connectivity/Ordering PCI Express Graphics ............................................... 195
XOR Chain Connectivity/Ordering DDR1..................................................................... 197
XOR Chain Connectivity/Ordering DDR1..................................................................... 198
XOR Chain Connectivity/Ordering DDR3..................................................................... 198
XOR Chain Connectivity/Ordering DDR4..................................................................... 201
XOR Chain Connectivity/Ordering DDR5..................................................................... 201
XOR Chain Connectivity/Ordering DDR6..................................................................... 202
Chipset Strapping Signals and Configuration .............................................................. 205
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Revision History
Revision
Date
Document
Number
Revision
Number
18790
0.5
• Initial Release
June 2005
0.7
• Updated Feature Support Sections in Chapter 1with SKU specific
features
• Sorted signals alphabetically where appropriate in Signal
Description chapter
— Updated signal names and descriptions for H_AVREF,
H_DVREF, H_CPUSLP#, H_SCOMP, H_SCOMP#,
SM_CKE[1:0], SM_CKE[4:3], SM_VREF, DMI_RXN[3:0],
DMI_RXP[3:0], DMI_TXN[3:0], DMI_TXP[3:0],
CRT_TVO_IREF, TVA_RTN, TVB_RTN, TVC_RTN,
LVDSA_CLK, LVDSA_CLK#, LVDSA_DATA[2:0],
LVDSA_DATA#[2:0], LVDSB_CLK, LVDSB_CLK#,
LVDSB_DATA[2:0], LVDSB_DATA#[2:0], CL_PWROK,
GFX_VID[3:0], GFX_VR_EN, ICH_SYNC#, PM_DPRSTP#,
TEST1, TEST2, NC, VCCD_QDAC, VTTLF, VCC_SM_LF,
VCC_AXM, and VSS_SCB
• Updated System Address Map chapter with Memory Remapping
or Reclaiming
• Updated PCI Express* Based External Graphics chapter with
Concurrent SDVO/PCI Express* Operation.
• Added Integrated Graphics Controller chapter
• Added Clocking chapter
• Updated Crestline Chipset Strapping Configuration chapter.
November
2005
1.0
• General:
— Added 24bpp support for LVDS single channel
— Updated RAMDAC frequency to 300MHz
• Chapter 2
— Updated Pull-down resistor value for L_IBG
— Removed SDVOB_ALPHA signal information
— Added SA_MA_14 and SB_MA_14
— Corrected VCCR_RX_DMI to VCC_RXR_DMI in Section 2-10
• Chapter 4
— Updated Fig 4-1 to show remapping with 4GB physical
memory populated
— Added Device 3 (ME) BAR information
— Added information on Intel® Flex Memory Technology
support
• Chapter 6
— Removed note under Table 6-2
— Removed Alpha support on SDVO
• Chapter 7
— Updated 3D Engine information to reflect Gen4 Core
Internal Graphics Capabilities
— Updated Fig 7-1
• Chapter 8
— Updated Fig 8-1
— Added Display Pipe and Display Plane information
• Chapter 9
— Added CLKREQ# info
— Added PWROK sequencing info
• Chapter 11
— Updated Trip points support
May 2006
19857
20954
External Design Specification
Description
Intel Confidential
11
Document
Number
20954
21749
12
Revision
Number
Description
Revision
Date
1.0
• The following chapters have been incorporated from the Crestline
EDS Addendum (Change Bars indicate the updates over the
previous revision of the Crestline EDS addendum)
— Chapter 10 - Absolute Maximum Ratings
— Chapter 12 - DC Characteristics
— Chapter 13 - AC Characteristics
— Chapter 14 - Signal Quality Specifications
— Chapter 15 - AC Timing Diagrams
— Chapter 20 - IO Buffer Documentation
• Chapter 12
— Updated TBD in Section 12.2
• Chapter 17
— Added Testability information
• Chapter 18
— Changed CFG8 strapping definition to RSVD
• Chapter 19
— Added ball list and ballout diagrams
— Added Package information and diagrams
May 2006
1.1
• Updated all ‘Crestline’ references with appropriate Intel® 965
Express Chipset family brand name.
• Updated all relevant sections to indicate support for DualChannel 24bpp LVDS Panel support.
• Chapter 1
— Changed TBD value for Render Standby Voltage in Section
1.3.3 to 0.75 V.
• Chapter 2
— Section 2.8 - changed PM_DPRSTP# Voltage CMOS buffer
type from HVCMOS (3.3 V) to LVCMOS (1.05 V).
• Chapter 10
— Section 10.1 - Updated TDP numbers and few Iccmax
numbers based on Post Silicon validation.
• Chapter 11
— Section 11.1.1 - corrected Aux2 trip point programming and
added values for trip point temperatures, Tjmaxand Taccuracy.
• Chapter 12
— Updated Section 12.2 and Section 12.3.
• Chapter 13
— Section 13.1 - Removed Display PLLA, PLLB Differential
Clock at Frequency of 96 MHz (w/SSC) and updated values
for 100 MHz (w/SSC).
— Updated Sections 13.2, 13.3, 13.6 and 13.7.
• Chapter 14
— Added Table 45, 46 and 47.
• Chapter 15
— Added Figure 47 and 48.
— Added general and specific power sequencing requirements
for (G)MCH, TVDAC, GPIO and HVSYNC.
• Chapter 16
— Corrected error in the DPLL_REF_SSCLK row.
August 2006
Intel Confidential
External Design Specification
Document
Number
22244
Revision
Number
Description
Revision
Date
1.5
• Chapter 1
— Added FSB 533MHz to Section 1.2.1 (965GM)
— Added “DMI x2 lanes reversed is not supported” to Section
1.2.4
— Added the following to the PM SKU Power Management to
Section 1.2.5
— Dynamic FSB Frequency Switching
— Replaced “Analog Monitor Support up to QXGA (2048x1536
@ 60 Hz)” with “For supported resolutions, Refer to the OMP
tool” in Section 1.3.2.1
— Replaced “4:3 Aspect Ratio Panel support up to UXGA
(1600x1200 @75Hz) Widescreen Panel support up to
WUXGA (1920x1200 @ 65Hz)” with “For supported
resolutions, refer to the OMP tool” Section 1.3.2.2
— Removed “support up to WUXGA (1920x1200)” in Section
1.3.2.2
— Added the following to the GM SKU Power Management
Section to Section 1.3.3
— DPST3.0
— Intel® S2DDT
— Dynamic Display Power Optimization* (D2PO) Panel Support
— Intel® Automatic Display Brightness
— LCD Refresh Rate
— Dynamic FSB Frequency Switching
— Graphics Render Standby
— Removed Intel® RMPM from Section 1.3.3 as it's redundant
— Added FSB 533 MHz, and removed FSB 667 to Section 1.4.1
(965GL)
— Updated 965GL render clock frequency 250 MHz 320 MHz in
Section 1.4.3
— Removed “Display panel capabilities - TBD (information will
be provided in revision 1.5)” from Section 1.4.3
— Added “All Power Management features supported by Intel
PM965 Express Choppiest shall be supported by Intel GL960
Express Choppiest unless otherwise noted below.” Section
1.4.5
— Removed “Power Management support - TBD (information
will be provided in revision 1.5)” from Section 1.4.5
— Added “Intel® RMPM is not supported” for Section 1.4.5
— Added “Dynamic FSB Frequency Switching is not supported”
for Section 1.4.5
— Added HDMI terminology to 1.5
— Added TMDS terminology to 1.5
— Replaced “PCI Express Specification 1.0a“with “PCI Express
Specification 1.1“in Section 1.6
— Replaced “PCI Express Specification 1.0a Mobile Graphics
Low Power Addendum to the PCI Express Base Specification
Revision 1.0” with “PCI Express™ Architecture Mobile
Graphics Low Power Addendum to the PCI Express Base
Specification Revision 1.0”
— Replaced “PCI Local Bus Specification 2.3” with “PCI Local
Bus Specification 3.0”
• Chapter 2
— Updated Intel Management Engine interface signal types in
Section 2.6
— Renamed PM_BM_BUSY# (PMSYNC#), and changed
description in Section 2.8
— Removed a duplicate of “VCCD_CRT, and VCCD_QDAC,
VCC_SYNC, VCCA_CRT_DAC)” from Section 2.10
• Chapter 6
— Added HDMI to 6.3.1
October 2006
External Design Specification
Intel Confidential
13
Document
Number
22244
14
Revision
Number
Description
Revision
Date
1.5
• Chapter 8
— Removed “(G)MCH's integrated 300 MHz RAMDAC supports
resolutions up to 2048 x 1536 @ 60 Hz” with “For (G)MCH
supported resolutions, refer to the OMP tool” in Section
8.4.1.1
— Added HDMI to 8.4.3.1
— Modified TMDS to DVI on 8.4.3.2
— Added HDMI info to 8.4.3.5
— Added TMDS info to 8.4.3.6
• Reformatted units for Add On, and LVDS Active in Table 16
• Chapter 9
— Added the following to the overview Section (9.1)
— Intel® S2DDT
— Dynamic Display Power Optimization* (D2PO) Panel Support
— Intel® Automatic Display Brightness
— LCD Refresh Rate
— Dynamic FSB Frequency Switching
— Graphics Render Standby
— Removed “Enhanced Intel SpeedStep® Technology” from
the overview Section (9.1)
— Added Intel® RMPM description to 9.4.2.1
— Changed DPST3.0 description in Section 9.7
— Added Intel® S2DDT in Section 9.8
— Added Dynamic Display Power Optimization* (D2PO) Panel
Support in Section 9.9
— Added Intel® Automatic Display Brightness in Section 9.10
— Added LCD Refresh Rate in Section 9.11
— Added Dynamic FSB Frequency Switching in Section 9.12
— Added Graphics Render Standby in Section 9.13
• Chapter 10
— Added TDP for GM(sub-note) in Section 10.1
— Changed IVCCD_QTVDAC Max value from 5 to 0.5 in section
10.1
• Chapter 12
— Renamed PM_BM_BUSY# with PMSYNC#, and changed I/O
to I in Table 25
— Replaced PCI Express Interface 1.0a with PCI Express
Interface 1.1 in Table 26
• Chapter 13
— Replaced PCI Express Specification 1.0a with PCI Express
Specification 1.1 in Table 38
• Chapter 15
— Replaced VCC_GIO with VCC_HV in Section 15.7.1.2
— Replaced the following signal names (Sections 15.7.1,
15.7.1.1, 15.7.3)
— VCCA_A_TVO with VCCA_TVA_DAC
— VCCA_B_TVO with VCCA_TVB_DAC
— VCCA_C_TVO with VCCA_TVC_DAC
— VCCABG_DAC_BG with VCCA_DAC_BG
— VCCD_TVO with VCCD_TVDAC
— VCCDQ_DAC with VCCD_QDAC
— VCCA_CRT with VCCA_CRT_DAC
— VCCSYNC_CRT WITH VCC_SYNC
• Chapter 16
— Added Section 16.3
— Added Table 48
— Added Table 49
• Chapter 17
— Renamed PM_BM_BUSY# (PMSYNC#), and changed I/O to I
in Table 54
— Replaced VCC_GIO with VCC_HV
— Corrected PM_DPRSTP# signal type in Table 55
October 2006
Intel Confidential
External Design Specification
Document
Number
22244
643728
Revision
Number
Description
Revision
Date
1.5
• Chapter 18
— Added FSB 533 to Table 68
— Added CFG7 strap (Intel® Management Engine Crypto
strap) information to Table 68
— Added notes to Table 68
• Chapter 19
— Renamed PM_BM_BUSY# (PMSYNC#) in Sections 19.2 and
19.3
— Updated Figure 60 for clarity
October 2006
1.6
• Chapter 1
— Secttion 1.1 - Updated Figure 1 to reflect FSB-533 MHz
support
— Secttion 1.2.1 - Updated Intel® Dynamic Front Side Bus
Frequency Switching naming
— Section 1.2.4 – Updated DMI support
— Secttion 1.2.5 - Updated Intel® Dynamic Front Side Bus
Frequency Switching naming
— Section 1.3.1 -Updated PCI Express Graphics support
— Section 1.3.2 - Updated CRCLK information for GM965
— Section 1.3.2 - Updated Mobile Intel® Graphics Media
Accelerator X3100 (Mobile Intel® GMA X3100) naming
— Section 1.3.2 - Added Intel® Clear Video Technology
— section 1.3.2 - Added Not available at TTM Launch”note
— Section 1.3.3 – Updated RS2 information
— Section 1.3.3 - Updated Intel® Display Refresh Rate
Switching naming
— Section 1.4.3 - Replaced Gen 4 with Mobile Intel® Graphics
Media Accelerator X3100 (Mobile Intel® GMA X3100)
— Section 1.4.3 - Updated CRCLK informationfor GL960
information
— Secttion 1.4.5 - Updated Intel® Dynamic Front Side Bus
Frequency Switching naming
— Section 1.6 – Added DVI info
• Chapter 2
— Updated PCI Express Specification support
— Section 2.6 – Updated CL_PWROK buffer type
— Section 2.8 – Corrected a typo with PM_BM_BUSY# signal
— Section 2.10 - Updated VCC_AXG information
• Chapter 3
— Section 3.6 - Updated PCI Express Specification support
• Chapter 6
— Section 6.2 - Updated PCI Express and PCI Specification
support
• Chapter 7
— Section 7.1.2.1.6 - Replaced Gen 4 with Mobile Intel® GMA
X3100 Section 7.1.2.3 - Replaced Gen 4 with Mobile Intel®
GMA X3100 Section 7.1.4.7 - Replaced Gen 4 with Mobile
Intel® GMA X3100
• Chapter 9
— Section 9.1 - Updated Intel® Dynamic Front Side Bus
Frequency Switching naming
— Section 9.1 - Updated Intel® Display Refresh Rate
Switching naming
— Section 9.11- Updated Intel® Display Refresh Rate
Switching naming
— Section 9.12 - Updated Intel® Dynamic Front Side Bus
Frequency Switching naming
— Section 9.4.2.1 - Updated Conditional Self refresh
information
— Section 9.4.2.4 - Updated Conditional Self refresh
information (as well as Table 17)
— notes
January 2007
External Design Specification
Intel Confidential
15
Document
Number
643728
Revision
Number
1.6
Revision
Date
Description
• Chapter 10
— Updated Table 20WRT VCC_AXG, VCC_AXD, and VCC_AXM
— Section 10.1 - Updated TDP numbers
— Section 10.1 – Updated IVCC_AXM
— Section 10.1 – Updated IVTT for FSB 533
— Section 10.1 – Updated IVCC_PEG
— Section 10.1 – Updated CRT DAC Interface section
— Section 10.1 - Updated PLL Analog Power Supplies section
— Section 10.1 - Updated Notes
— Updated Table 21 WRT IVCCA_SM (and replaced
IVCCSM_CK(667 MT/s) with IVCCA_SM)
— Updated Table 22 WRT IVCC_AXD
• Chapter 12
— Section 12.3 – Updated Table 26 WRT VCC_AXG
— Section 12.3 – Updated Table 26 WRT VIH of group (v)
• Chapter 13
— Section 13.1 - Added FSB 533 information
— Section 13.2 - Added Table 29 for Host Interface AC
Characteristics for 533 MHz
— Section 13.2 - Updated Notes of Table 30
— Section 13.2 - Updated Notes of Table 31
— Section 13.4 – Updated Table 38 WRT TTX_EYE
• Section 13.4 – Updated Table 39 WRT TTX_EYE as well as the
January 2007
• Chapter 14
— Updated Table 45
— Updated Table 47
• Chapter 15
— Updated Figure 26
• Chapter 16
— Updated Table 49
— Updated Table 50
• Chapter 20
• I/O Buffer and IBIS models are no longer password protected
643728
16
2.0
• Chapter 1
— Section 1.1 - Removed 667-MHz from Figure 1
— Section 1.2.1 - Removed 667-MHz processor support
— Section 1.2.2 - Removed “2Gb memory technology”
— Section 1.2.5 - Replaced C5 with “Intel® Enhanced Deeper
Sleep (aka Deep C4 or C5)”
— Section 1.3.2 - Updated Internal Graphics section
— Section 1.3.3 - Update RS information
— Section 1.6 - Added “RS - Mobile Intel® GM965/PM965/
GL960 Express Chipset Family BIOS Specification“
• Chapter 2
— Section 2.5.1 - Corrected CRT_TVO_IREF resistor value
— Section 2.5.3 - Updated LVDS_IBG resistor accuracy
— Section 2.8 - Updated PWROK signal description
• Chapter 3
— Section 3.1 - Added 533-MHz information
• Chapter 5
— Section 5.1 - Updated table 9
• Chapter 7
— Replaced GMA x3000 with GMA x3100
— Section 7.1.2 - Replaced DirectX* 10 with DirectX* 9
— Section 7.1.2 - Removed OpenGL* 2.0
— Section 7.1.2.4 - Removed “Pixel shader 4.0 (for DirectX*
10 applications)”
— Added Section 7.1.2.4.7 - “Intermediate Z“
— Added Section 7.1.3.3 “Hardware Rotation”
— Reconstructed section 7.1.4
Intel Confidential
February
2007
External Design Specification
Document
Number
643728
Revision
Number
Description
Revision
Date
2.0
• Chapter 8
— Section 8.3 - Added DPLL_REF_SSCLK/DPLL_REF_SSCLK#
— Section 8.4.2.1 - Updated text WRT ANSI/TIA/EIA 644
• Chapter 9
— Section 9.1 - Added Intel® Enhanced Deeper Sleep state
— Section 9.12 - Corrected typo WRT Intel® Dynamic Front
Side Bus Frequency Switching
— Section 9.14 - Updated Figure 20
— Section 9.14 - Updated Figure 20
• Chapter 10
— Updated Table 20 WRT IVCC_AXM
• Chapter 11
— Section 11.1.1.1 - Updated Thermal sensor information and
removed table 24
— Section 11.1.1.2 - Updated Thermal sensor information
• Chapter 12
— Section 12.3 - Added note to Table 25 WRT LVDS
termination
• Chapter 13
— Replaced “Crestline” with “Intel 965 Express Chipset family
— Section 13.1 – Removed inaccurate text WRT performing
test
— Section 13.1 - Updated parameters and notes
— Section 13.2 - Added table 28 (was supposed to be added
as table 29 for FSB533 in rev 1.6, but it wasn’t, although it
was mentioned in the revision history of doc #643728;
therefore all incorrect table numbers in the revision history
of rev 1.6 were strike through and corrected accordingly)
— Section 13.2 - Updated Table 29
— Section 13.2 - Updated Table 30
— Section 13.3.1 - Updated Table 31 and Table 34 WRT TSUMCH
— Section 13.5 - Added note to table 39 WRT LVDS
termination
• Chapter 15
— section 15.1 - Updated Figure 22 title description
• Chapter 16
— Section 16.3 - Updated Table 48
• Chapter 19
— Section 19.4 - Added notes Figure 62
February
2007
Revision Number Descriptions
Revision
Associated Life Cycle Milestone
Release Information
0.5
Design Win Phase
Required Release
0.6–0.7
When Needed
Project Dependent
0.7
Simulations Complete
Required Release
0.8–0.9
When Needed
Project Dependent
1.0
First Silicon Samples
Required Release
1.1–1.4
When Needed
Project Dependent
1.5
Qualification Silicon Samples
Project Dependent
1.6–1.9
When Needed
Project Dependent
NDA - 2.0
Public - XXXXXX-001
First SKU Launch
2.1 and up
When Needed
External Design Specification
Required Release
Product Launch
Project Dependent
Intel Confidential
17
§
18
Intel Confidential
External Design Specification
Introduction
1
Introduction
1.1
Overview
The Mobile Intel® 965 Express Chipset family is designed for use in Intel’s next
generation mobile platform, code named Santa Rosa.
The (G)MCH manages the flow of information between various components through
four primary interfaces:
• Front Side Bus (FSB)
• System Memory Interface (DDR2)
• Graphics Interfaces (LVDS, CRT, TV-Out, SDVO, and PCI Express* Graphics)
• Direct Media Interface (DMI)
Figure 1.
Santa Rosa Platform with Mobile Intel® 965 Express Chipset Family (G)MCH
Intel
Core™2
Duo Mobile
Processor
FSB
(533/800 MHz)
DDR2 533/667 MHz
LVDS
Memory
Memory
Intel 965
(G)MCH
CRT
2 SDVO Ports
SDVO
TV-OUT
DMI
10 USB 2.0 Ports
(x2/x4)
PCI Express
Graphics
Controller
Link 0
USB
6 PCI Express x1 Ports
1 Parallel ATA Channel
PATA
ICH8M
3 Serial ATA Ports
SATA
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
PCI Express
Intel® High
Definition Audio
SIO/EC
WLAN
GLCI
LPC
LAN
10/100 LCI
Controller Link 1
TPM
FWH
PCI Bus
External Design Specification
Intel Confidential
19
Introduction
The (G)MCH can be enabled to support either integrated graphics or external graphics.
When external graphics is enabled, the x16 PCI Express Graphics attach port is utilized,
and the internal graphics ports are disabled.
1.2
Mobile Intel® PM965 Express Chipset Feature
Support
1.2.1
Processor Support
• Intel® Core™2 Duo mobile processor for Santa Rosa
• 533-MHz, and 800-MHz FSB support
• Source synchronous double-pumped (2x) address
• Source synchronous quad-pumped (4x) data
• Intel® Dynamic Front Side Bus Frequency Switching
• Other key features are:
— Support for DBI (Data Bus Inversion)
— Support for MSI (Message Signaled Interrupt)
— 36-bit interface to addressing, allowing the CPU to access the entire 64 GB of
the (G)MCH’s memory address space
— 12-deep in-order queue to pipeline FSB commands
— AGTL+ bus driver with integrated AGTL termination resistors
1.2.2
System Memory Support
• Supports Dual Channel DDR2 SDRAM
• One SO-DIMM connector (or memory module) per channel
• Two Memory Channel Configurations supported
— Dual Channel Interleaved
— Dual Channel Asymmetric
• Maximum memory supported: 4 GB
• Intel(R) Flex Memory Technology support
• 64-bit wide per channel
• Support for DDR2 at 667 MHz and 533 MHz
• 256-Mb, 512-Mb, and 1-Gb memory technologies supported
• Support for x8 and x16 devices
• Support for DDR2 On-Die Termination (ODT)
• Supports partial writes to memory using data mask signals (DM)
• Dynamic rank power-down
• No support for Fast Chip Select mode
• No support for ECC
20
Intel Confidential
External Design Specification
Introduction
1.2.3
Discrete Graphics using PCI Express* Graphics Attach Port
• One 16-lane (x16) PCI Express port for external PCI Express based graphics card
— May also be configured as a PCI Express x1 port
1.2.4
DMI
• Chip-to-chip interface between (G)MCH and ICH8M
• Configurable as x2 or x4 DMI lanes
• DMI x2 lanes reversed is not supported
• DMI polarity inversion is supported
• 2-GB/s (1 GB/s each direction) point-to-point interface to ICH8M
• 32-bit downstream address
• DMI asynchronously coupled to core
• APIC and MSI interrupt messaging support
• Supports SMI, SCI and SERR error indication
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
1.2.5
Power Management
• Supports ACPI 3.0
• S States: S0, S3, S4, S5
• C States: C0, C1, C1E, C2, C2E, C3, C4, C4E and Intel® Enhanced Deeper Sleep
(aka Deep C4 or C5) states
• M States: M0, M1, M-off
• PCI Express Link States: L0, L0s, L1, L2/L3 ready, L3
• H_SLPCPU# output
• H_DPWR# support
• Intel® Rapid Memory Power Management (Intel® RMPM)
• Intel® Dynamic Front Side Bus Frequency Switching
1.2.6
Security and Manageability (Intel® Active Management
Technology)
The (G)MCH provides an integrated Intel® Active Management Technology (Intel®
AMT) engine that combines hardware and software solutions to provide:
• Remote Asset Management
• Remote Diagnosis & Repair
• Remote Agent Presence
• Wireless OOB Management
• System Defense Network Isolation
• Mobile Power Management Policies
• 3rd Party Non-Volatile Storage
• Intel® AMT 2.5 with both wired and wireless LAN support
External Design Specification
Intel Confidential
21
Introduction
• Controller Link interface to ICH8M for extended manageability functionality
1.2.7
Package
• FCBGA
• Ball Count: 1299 balls
• Package Size: 35 mm x 35 mm
• Ball pitch: Variable pitch; 31.5-mil minimum pitch
1.3
Mobile Intel® GM965 Express Chipset Feature
Support
All features supported by Intel PM965 Express Chipset shall be supported by Intel
GM965 Chipset unless otherwise noted below. Additional features are also listed below.
1.3.1
PCI Express Graphics Attach Port
• One 16-lane (x16) PCI Express port for external PCI Express Based graphics card
— May also be configured as a PCI Express x1 port for video capture
• Lane reversal is supported
• Polarity Inversion is supported
1.3.2
Internal Graphics
• Mobile Intel Graphics Media Accelerator X3100 (Mobile Intel GMA X3100)
• Estimated 500-MHz core render clock at 1.05 V core voltage
• Supports TV-Out, LVDS, CRT and SDVO
• Intel® Smart 2D Display Technology (Intel® S2DDT)
• Video Capture via x1 concurrent PCI Express port
• Dynamic Video Memory Technology (DVMT 4.0)
• Intel® Clear Video Technology
— MPEG-2 Hardware Acceleration
— WMV9 Hardware Acceleration
— ProcAmp
— Advanced Pixel Adaptive De-interlacing
— Sharpness Enhancement
— De-noise Filter
— High Quality Scaling
— Film Mode Detection and Correction
— Intel® TV Wizard
• Microsoft DirectX* 9
• Intermediate Z
• OpenGL* 1.5
• HW Pixel Shader 3.0
22
Intel Confidential
External Design Specification
Introduction
• HW rotation
1.3.2.1
Analog CRT
• Integrated 300-MHz RAMDAC
• For supported resolutions, refer to the OMP tool
• Support for CRT hot plug
1.3.2.2
Dual Channel LVDS
• For supported resolutions, refer to the OMP tool
• 25-112 MHz single/dual channel
— Single channel LVDS interface support: 1 x 18-bpp OR 1 x 24-bpp (Type 1
only), compatible with VESA LVDS color mapping)
— Dual channel LVDS interface support: 2 x 18-bpp panel support or 2 x 24-bpp
panel (Type 1 only)
— TFT panel type supported
• Pixel dithering for 18-bit TFT panel to emulate 24-bpp true color displays
• Panel Fitting. Panning, and Center mode supported
• Standard Panel Working Group (SPWG) v.3.5 specification compliant
• Spread spectrum clocking supported
• Panel power sequencing support
• Integrated PWM interface for LCD backlight inverter control
1.3.2.3
TV-Out
• Three integrated 10-bit DACs
• MacroVision support
• Overscaling
• NTSC/PAL
• Component, S-Video and Composite Output Interfaces
• HDTV graphics mode support
1.3.2.4
SDVO Ports
• Two SDVO ports supported
— SDVO pins are muxed onto the PCI Express Graphics attach port pins
— DVI 1.0 support for External Digital Monitor
— Downstream HDCP Support but no upstream HDCP support
— Display Hot Plug support
• Supports appropriate external SDVO components (HDMI, DVI, LVDS, TV-Out)
• I2C channel provided for control
1.3.3
Power Management
• Graphics Display Adapter States: D0, D3
• Intel® Display Power Saving Technology (Intel® DPST) 3.0
• Intel® S2DDT
External Design Specification
Intel Confidential
23
Introduction
• Dynamic Display Power Optimization* (D2PO) Panel Support
• Intel® Automatic Display Brightness
• Intel® Display Refresh Rate Switching
• Graphics Render Standby Mode †
— Render Standby Voltage: 0.55 V (Render frequency drops to zero)
† Not available at TTM Launch
1.4
Mobile Intel® GL960 Express Chipset Feature
Support
All features supported by Intel GM965 Express Chipset shall be supported by Intel
GL960 Express Chipset unless otherwise noted below. Additional features are also listed
below.
1.4.1
Processor Support
• Intel Celeron processor based on the Intel Core 2 Duo Mobile Processor for Santa
Rosa
• 533-MHz FSB support
1.4.2
System Memory Support
• Support for DDR2 at 533 MHz only
• Maximum memory supported: 2 GB
1.4.3
Internal Graphics
• Mobile Intel® Graphics Media Accelerator X3100 (Mobile Intel GMA X3100)
• Estimated 400-MHz core render clock at 1.05-V core voltage
1.4.4
ICH Support
• Support for ICH8M (base variant) only
1.4.5
Power Management
All Power Management features supported by Intel PM965 Express Chipset are
supported by Intel GL960 Express Chipset unless otherwise noted below.
• Intel® RMPM is not supported
• Intel® Dynamic Front Side Bus Frequency Switching is not supported
1.4.6
Intel® AMT
• No support for Intel® AMT
24
Intel Confidential
External Design Specification
Introduction
1.5
Terminology
(Sheet 1 of 2)
Term
Description
(G)MCH
Graphics Memory Controller Hub
CPU
Central Processing Unit or processor
CRT
Cathode Ray Tube
DBI
Dynamic Bus inversion
DDR2
Second generation Double Data Rate SDRAM memory technology
DMI
Direct Media Interface. The chip-to-chip interconnect between the Mobile Intel
GM965/PM965/GL960 Express Chipset and the ICH8M. It is an Intel
Proprietary interface
DVI*
Digital Visual Interface is the interface specified by the DDWG (Digital Display
Working Group) DVI Spec. Rev. 1.0
HDMI
High Definition Multimedia Interface - HDMI supports standard, enhanced, or
high-definition video, plus multi-channel digital audio on a single cable. It
transmits all ATSC HDTV standards and supports 8-channel digital audio,
(additional details available through http://www.hdmi.org)
Front Side Bus
FSB
Connection between Mobile Intel GM965/PM965/GL960 Express Chipset and
the CPU. Also known as the Host interface
Host
This term is used synonymously with processor
I2C
Inter-IC (a two wire serial bus created by Philips)
ICH8M
The I/O Controller Hub component that contains the primary PCI interface, LPC
interface, USB2, Serial ATA, and other I/O functions. It communicates with the
(G)MCH over a proprietary interconnect called DMI.
iDCT
Inverse Discrete Cosine Transform
INTx
An interrupt request signal where X stands for interrupts A,B,C and D
LCD
Liquid Crystal Display
LFP
Local Flat Panel
Low Voltage Differential Signaling
LVDS
A high speed, low power data transmission standard used for display
connections to LCD panels.
NCTF
Non-Critical to Function
NTSC
National Television Standards Committee
PAL
Phase Alternate Line
PWM
Pulse Width Modulation
Rank
A unit of DRAM corresponding 4 to 8 devices in parallel, ignoring ECC. These
devices are usually, but not always, mounted on a single side of a SO-DIMM.
TMDS
Transition Minimized Differential Signaling.
SCI
System Control Interrupt. Used in ACPI protocol
External Design Specification
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25
Introduction
(Sheet 2 of 2)
Term
Description
Serial Digital Video Out (SDVO)
SDVO
SDVO Device
1.6
Digital display channel that serially transmits digital display data to an external
SDVO device. The SDVO device accepts this serialized format and then
translates the data into the appropriate display format (i.e., TMDS, LVDS, TVOut). This interface is not electrically compatible with the previous digital
display channel - DVO. For the Mobile Intel 965 Express Chipset family, it will
be multiplexed on a portion of the x16 graphics PCI Express interface.
Third party codec that utilizes SDVO as an input. May have a variety of output
formats, including HDMI, DVI, LVDS, TV-out, etc.
VLD
Variable Length Decoding
VTT
Front Side Bus Power Supply (VCCP)
x1
Refers to a Link or Port with one Physical Lane
x16
Refers to a Link or Port with sixteen Physical Lanes
Reference Documents
Document
No./Location
Document
26
Advanced Configuration and Power Interface
Specification 3.0
http://www.acpi.info/
PCI Local Bus Specification 3.0
http://www.pcisig.com/specifications
PCI Express Specification 1.1
http://www.pcisig.com
Santa Rosa Platform ME-EC Interaction Specification
See Note
Standard Panel Working Group (SPWG) v.3.5
Specification
http://www.spwg.org/
Crestline IBIS Models (DDR2, FSB, PCI Express* etc.)
See Note
Intel(R) Core(TM) 2 Duo Processor for Santa Rosa
Platform Electrical, Mechanical, and Thermal
Specification (EMTS)
See Note
CK505 Clock Synthesizer/Driver Specification
See Note
JEDEC Double Data Rate 2 (DDR2) SDRAM
Specification
http://www.jedec.com
DDR2 JEDEC Specification Addendum
See Note
PCI Express™ Architecture Mobile Graphics Low Power
Addendum to the PCI Express Base Specification
Revision 1.0
http://www.pcisig.org
ICH8/ICH8-M External Design Specification (EDS)
See Note
ICH8/ICH8M IBIS Models
See Note
VESA Specification
http://www.vesa.org
Intel Confidential
External Design Specification
Introduction
Document
No./Location
Document
TIA/EIA-644 Standard
http://www.tiaonline.org
Digital Visual Interface (DVI) Specification revision 1.0
http://www.ddwg.org/downloads.asp
RS - Mobile Intel® GM965/PM965/GL960 Express
Chipset Family BIOS Specification
See Note
NOTE: Contact your Intel representative for a latest version of this document.
§
External Design Specification
Intel Confidential
27
Introduction
28
Intel Confidential
External Design Specification
Signal Description
2
Signal Description
This section describes the (G)MCH signals. These signals are arranged in functional
groups according to their associated interface. The following notations are used to
describe the signal type:
Notations
I
Signal Type
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
The signal description also includes the type of buffer used for the particular signal:
Signal
Description
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The (G)MCH integrates AGTL+ termination resistors, and
supports Vtt from 0.83 V to 1.65 V (including guardbanding).
PCI Express
PCI Express interface signals. These signals are compatible with PCI Express
1.1 Signaling Environment AC Specifications. The buffers are not 3.3-V
tolerant. Refer to the PCI Express specification.
CMOS
CMOS buffers.
HVCMOS
High Voltage CMOS buffers. 3.3-V tolerant
LVCMOS
Low Voltage CMOS buffers. Vtt tolerant
COD
CMOS Open Drain buffers. 3.3-V tolerant
SSTL-1.8
Stub Series Termination Logic: These are 1.8-V capable buffers. 1.8-V tolerant
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
LVDS
Low Voltage Differential signal interface
Ref
Voltage reference signal
1.5-V tolerant
Note:
1. System Address and Data Bus signals are logically inverted signals. The actual
values are inverted of what appears on the system bus. This must be considered
and the addresses and data bus signals must be inverted inside the (G)MCH. All
processor control signals follow normal convention: A 0 indicates an active level
(low voltage), and a 1 indicates an active level (high voltage).
2. All pins marked RSVD should be left NC.
2.1
Host Interface
Unless otherwise noted, the voltage level for all signals in this interface is tied to the
termination voltage of the host bus (VCCP).
External Design Specification
Intel Confidential
29
Signal Description
2.1.1
Host Interface Signals
Signal Name
Type
Description
Host Address Bus:
H_A#[35:3]
I/O
AGTL+
2X
HA#[35:3] connects to the processor address bus. During
processor cycles the HA#[35:3] are inputs. The (G)MCH
drives HA#[35:3] during snoop cycles on behalf of PCI
Express/Internal Graphics or ICH8M. HA#[35:3] are
transferred at 2x rate.
Note that the address is inverted on the processor bus.
Host Address Strobe:
H_ADS#
I/O
AGTL+
The system bus owner asserts H_ADS# to indicate the first of
two cycles of a request phase. The (G)MCH can also assert
this signal for snoop cycles and interrupt messages.
Host Address Strobe:
H_ADSTB#[1:0]
I/O
AGTL+
2X
HA#[31:3] connects to the processor address bus. During
processor cycles, the source synchronous strobes are used to
transfer HA#[35:3] and HREQ#[4:0] at the 2x transfer rate.
Strobe
Address Bits
HADSTB#0
HA#[15:3], HREQ#[4:0]
HADSTB#1
HA#[35:16
H_AVREF
I
Host Reference Voltage:
H_DVREF
A
Reference voltage input for the Data, Address, and Common
clock signals of the Host AGTL+ interface
H_BNR#
I/O
AGTL+
Host Block Next Request:
Used to block the current request bus owner from issuing a
new request. This signal is used to dynamically control the
processor bus pipeline depth.
Host Bus Priority Request:
H_BPRI#
O
AGTL+
The (G)MCH is the only Priority Agent on the system bus. It
asserts this signal to obtain the ownership of the address bus.
This signal has priority over symmetric bus requests and will
cause the current symmetric owner to stop issuing new
transactions unless the H_LOCK# signal was asserted.
Host Bus Request:
H_BREQ#
I/O
AGTL+
The (G)MCH pulls the processor bus H_BREQ# signal low
during H_CPURST#. The signal is sampled by the processor
on the active-to-inactive transition of H_CPURST#.
H_BREQ# should be tri-stated after the hold time
requirement has been satisfied.
Host CPU Reset:
H_CPURST#
O
AGTL+
The H_CPURST# pin is an output from the (G)MCH. The
(G)MCH asserts H_CPURST# while RSTIN# is asserted and
for approximately 1 ms after RSTIN# is deasserted.
H_CPURST# allows the processor to begin execution in a
known state.
30
Intel Confidential
External Design Specification
Signal Description
Signal Name
Type
Description
Host CPU Sleep:
H_CPUSLP#
O
LVCMOS
When asserted in the Stop-Grant state, causes the processor
to enter the Sleep state. During Sleep state, the processor
stops providing internal clock signals to all units, leaving only
the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or
interrupts. (This is a CMOS type buffer with Vtt - NOT 3.3
volts)
Host Data:
H_D#[63:0]
I/O
AGTL+
4X
H_DBSY#
I/O
AGTL+
H_DEFER#
O
AGTL+
These signals are connected to the processor data bus.
HD#[63:0] are transferred at 4x rate.
Note that the data signals are inverted on the processor bus
depending on the HDINV#[3:0] signals.
Host Data Bus Busy:
Used by the data bus owner to hold the data bus for transfers
requiring more than one cycle.
Host Defer:
Signals that the (G)MCH will terminate the transaction
currently being snooped with either a deferred response or
with a retry response.
Host Dynamic Bus Inversion:
H_DINV#[3:0]
I/O
AGTL+
Driven along with the HD[63:0]# signals. Indicates if the
associated signals are inverted or not. HDINV[3:0]# are
asserted such that the number of data bits driven electrically
low (low voltage) within the corresponding 16-bit group never
exceeds 8.
H_DINV#
Data Bits
H_DINV#3 H_D#[63:48]
H_DINV#2 H_D#[47:32]
H_DINV#1 H_D#[31:16]
H_DINV#0 H_D#[15:0]
Host Data Power:
H_DPWR#
H_DRDY#
I/O
AGTL+
I/O
AGTL+
Used by (G)MCH to indicate that a data return cycle is
pending within 2 H_CLK cycles or more. Processor uses this
signal during a read-cycle to activate the data input buffers in
preparation for H_DRDY# and the related data.
Host Data Ready:
Asserted for each cycle that data is transferred.
Host Differential Host Data Strobes:
H_DSTBP#[3:0]
H_DSTBN#[3:0]
I/O
AGTL+
4X
The differential source synchronous strobes are used to
transfer HD#[63:0] and HDINV#[3:0] at the 4x transfer rate.
Strobe
Data Bits
H_DSTBP#3, H_DSTBN#3 H_D#[63:48], H_DINV#[3]
H_DSTBP#2, H_DSTBN#2 H_D#[47:32], H_DINV#[2]
H_DSTBP#1, H_DSTBN#1 H_D#[31:16], H_DINV#[1]
H_DSTBP#0, H_DSTBN#9 H_D#[15:0], H_DINV#[0]
External Design Specification
Intel Confidential
31
Signal Description
Signal Name
Type
Description
Host Hit:
H_HIT#
I/O
AGTL+
Indicates that a caching agent holds an unmodified version of
the requested line.
Also, driven in conjunction with H_HITM# by the target to
extend the snoop window.
Host Hit Modified:
H_HITM#
I/O
AGTL+
Indicates that a caching agent holds a modified version of the
requested line and that this agent assumes responsibility for
providing the line.
Also, driven in conjunction with H_HIT# to extend the snoop
window.
Host Lock:
H_LOCK#
I
AGTL+
H_RCOMP
I/O
A
All processor bus cycles sampled with the assertion of
H_LOCK# and H_ADS#, until the negation of H_LOCK# must
be atomic.
Host RCOMP:
Used to calibrate the Host AGTL+ I/O buffers. .
Host Request Command:
H_REQ#[4:0]
I/O
AGTL+
2X
Defines the attributes of the request. H_REQ#[4:0] are
transferred at 2x rate. Asserted by the requesting agent
during both halves of the Request Phase. In the first half the
signals define the transaction type to a level of detail that is
sufficient to begin a snoop request. In the second half the
signals carry additional information to define the complete
transaction type
Host Response Status:
Indicates the type of response according to the following the
table:
H_RS#[2:0]Response type
H_RS#[2:0]
32
O
AGTL+
H_SCOMP
I/O
H_SCOMP#
A
000
Idle state
001
Retry response
010
Deferred response
011
Reserved (not driven by (G)MCH)
100
Hard Failure (not driven by (G)MCH)
101
No data response
110
Implicit Write back
111
Normal data response
Host SCOMP:
Slew Rate Compensation for the Host Interface
Intel Confidential
External Design Specification
Signal Description
Signal Name
H_SWING
H_TRDY#
THERMTRIP#
Type
Description
I
Host Voltage Swing:
A
These signals provide reference voltages used by the
H_RCOMP circuits.
Host Target Ready:
O
AGTL+
Indicates that the target of the processor transaction is able
to enter the data transfer phase.
Connects between the Processor and the Intel ICH8M.
Assertion of THERMTRIP# (Thermal Trip) indicates the
(G)MCH junction temperature has reached a level beyond
which damage may occur. Upon assertion of THERMTRIP#,
the (G)MCH will shut off its internal clocks (thus halting
program execution) in an attempt to reduce the (G)MCH core
junction temperature. To protect (G)MCH, its core voltage
(Vcc) must be removed following the assertion of
THERMTRIP#. Once activated, THERMTRIP# remains latched
until RSTIN# is asserted. While the assertion of the RSTIN#
signal will de-assert THERMTRIP#, if the (G)MCH’s junction
temperature remains at or above the trip level, THERMTRIP#
will again be asserted.
O
AGTL+
2.2
DDR2 Memory Interface
2.2.1
DDR2 Memory Channel A Interface
Signal Name
SA_BS[2:0]
SA_CAS#
Type
Description
Bank Select:
O
SSTL-1.8
These signals define which banks are selected within each
SDRAM rank.
CAS Control Signal:
O
SSTL-1.8
Used with SA_RAS# and SA_WE# (along with SA_CS#)
to define the SDRAM commands.
Data Mask:
O
SA_DM[7:0]
SSTL-1.8
2x
I/O
SA_DQ[63:0]
I/O
SSTL-1.8
2x
External Design Specification
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SA_DM[7:0] for every data byte lane.
Data Bus:
SSTL-1.8
2x
SA_DQS#[7:0]
These signals are used to mask individual bytes of data in
the case of a partial write, and to interrupt burst writes.
DDR2 Channel A data signal interface to the SDRAM data
bus.
Data Strobe Complements
These are the complementary strobe signals.
Intel Confidential
33
Signal Description
Signal Name
Type
Data Strobes:
I/O
SA_DQS[7:0]
SSTL-1.8
2x
SA_MA[14:0]
SA_RAS#
SA_RCVEN#
SA_WE#
2.2.2
Description
SA_DQS[7:0] and its complement signal group make up
a differential strobe pair. The data is captured at the
crossing point of SA_DQS[7:0] and its SA_DQS[7:0]#
during read and write transactions.
Memory Address:
O
SSTL-1.8
These signals are used to provide the multiplexed row
and column address to the SDRAM.
RAS Control Signal:
O
SSTL-1.8
Used with SA_CAS# and SA_WE# (along with SA_CS#)
to define the SDRAM commands.
Clock Input:
I
SSTL-1.8
Used to emulate source-synch clocking for reads.
Leave as No Connect.
Write Enable Control Signal:
O
SSTL-1.8
Used with SA_RAS# and SA_CAS# (along with SA_CS#)
to define the SDRAM commands.
DDR2 Memory Channel B Interface
Signal Name
SB_BS[2:0]
SB_CAS#
Type
Description
Bank Select:
O
SSTL-1.8
These signals define which banks are selected within each
SDRAM rank.
CAS Control signal:
O
SSTL-1.8
Used with SB_RAS# and SB_WE# (along with SB_CS#)
to define the SDRAM commands.
Data Mask:
O
SB_DM[7:0]
SSTL-1.8
2x
I/O
SB_DQ[63:0]
I/O
SSTL-1.8
2x
SSTL-1.8
2x
34
DDR2 Channel B data signal interface to the SDRAM data
bus.
Data Strobe Complements:
These are the complementary strobe signals.
Data Strobes:
I/O
SB_DQS[7:0]
When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one
SB_DM[7:0] for every data byte lane.
Data Bus:
SSTL-1.8
2x
SB_DQS#[7:0]
These signals are used to mask individual bytes of data in
the case of a partial write, and to interrupt burst writes.
SB_DQS[7:0] and its complement signal group make up a
differential strobe pair. The data is captured at the
crossing point of SB_DQS[7:0] and its SB_DQS[7:0]#
during read and write transactions.
Intel Confidential
External Design Specification
Signal Description
Signal Name
SB_MA[14:0]
SB_RAS#
SB_RCVEN#
SB_WE#
2.2.3
Type
Description
Memory Address:
O
SSTL-1.8
These signals are used to provide the multiplexed row
and column address to the SDRAM.
RAS Control Signal:
O
SSTL-1.8
Used with SB_CAS# and SB_WE# (along with SB_CS#)
to define the SDRAM commands.
Clock Input:
I
SSTL-1.8
Used to emulate source-synch clocking for reads.
Leave as No Connect.
Write Enable Control Signal:
O
SSTL-1.8
Used with SB_RAS# and SB_CAS# (along with SB_CS#)
to define the SDRAM commands.
DDR2 Memory Common Signals
Signal Name
Type
Description
SM_CK#[1:0]
O
SDRAM Inverted Differential Clock: (2 per SO-DIMM)
SM_CK#[4:3]
SSTL-1.8
These are the SDRAM Inverted Differential Clock signals.
SDRAM Differential Clock: (2 per SO-DIMM)
These are the SDRAM Differential Clock signals
SM_CK[1:0]
O
SM_CK[4:3]
SSTL-1.8
The crossing of the positive edge of SM_CKx and the
negative edge of its complement SM_CKx# are used to
sample the command and control signals on the SDRAM.
Clock Enable: (1 per Rank):
SM_CKE[4:3] and SM_CKE[1:0] is used:
SM_CKE[1:0]
O
SM_CKE[4:3]
SSTL-1.8
• to initialize the SDRAMs during power-up,
• to power-down SDRAM ranks,
• to place all SDRAM ranks into and out of self-refresh
during STR.
Chip Select: (1 per Rank):
SM_CS#[3:0]
SM_ODT[3:0]
External Design Specification
O
SSTL-1.8
O
SSTL-1.8
These signals select particular SDRAM components during
the active state. There is one Chip Select for each SDRAM
rank.
On Die Termination: Active Termination Control.
Intel Confidential
35
Signal Description
2.2.4
DDR2 Memory Reference and Compensation
Signal Name
Type
SM_RCOMP
SM_RCOMP#
System Memory Impedance Compensation:
Requires pull up resistor.
I
System Memory Impedance Compensation:
A
Requires pull down resistor.
Swing voltage for pull up impedance compensation
A
I
SM_RCOMP_VOL
Swing voltage for pull down impedance compensation
A
I
SM_VREF
2.3
I
A
I
SM_RCOMP_VOH
Description
System Memory Reference Voltage for all data and
data strobe signals. (2 Signals).
A
PCI Express* Based Graphics Interface Signals
Unless otherwise specified, these signals are AC coupled.
Signal Name
Type
I
PEG_COMPI
I
I
PCI Express
PEG_TX[15:0]
PEG_TX#[15:0]
2.3.1
PCI Express Graphics Output Current and Resistance
Compensation.
A
PEG_RX[15:0]
PEG_RX#[15:0]
PCI Express Graphics Input Current Compensation
A
PEG_COMPO
Description
O
PCI Express
PCI Express Graphics Receive Differential Pair.
PCI Express Graphics Transmit Differential Pair.
Serial DVO and PCI Express Based Graphics Signal
Mapping
SDVO and PCI Express Interface for graphics architecture are muxed together. Table 1
shows the signal mapping.
Table 1.
SDVO and PCI Express* Based Graphics Port Signal Mapping (Sheet 1 of 2)
SDVO Mode
36
PCI Express MODE
SDVOB_RED
PEG_TXP0
SDVOB_RED#
PEG_TXN0
SDVOB_GREEN
PEG_TXP1
SDVOB_GREEN#
PEG_TXN1
SDVOB_BLUE
PEG_TXP2
SDVOB_BLUE#
PEG_TXN2
SDVOB_CLK
PEG_TXP3
Intel Confidential
External Design Specification
Signal Description
Table 1.
SDVO and PCI Express* Based Graphics Port Signal Mapping (Sheet 2 of 2)
SDVO Mode
2.4
PCI Express MODE
SDVOB_CLK#
PEG_TXN3
SDVOC_RED
PEG_TXP4
SDVOC_RED#
PEG_TXN4
SDVOC_GREEN
PEG_TXP5
SDVOC_GREEN#
PEG_TXN5
SDVOC_BLUE
PEG_TXP6
SDVOC_BLUE#
PEG_TXN6
SDVOC_CLK
PEG_TXP7
SDVOC_CLK#
PEG_TXN7
SDVO_TV_CLKIN
PEG_RXP0
SDVO_TV_CLKIN#
PEG_RXN0
SDVO_INT
PEG_RXP1
SDVO_INT#
PEG_RXN1
SDVO_FLD_STALL
PEG_RXP2
SDVO_FLD_STALL#
PEG_RXN2
DMI – (G)MCH to ICH Serial Interface
Signal Name
DMI_RXN[3:0]
DMI_RXP[3:0]
DMI_TXN[3:0]
DMI_TXP[3:0]
External Design Specification
Type
I
PCI
Express
O
PCI
Express
Description
DMI input from ICH:
Direct Media Interface receive differential pair
DMI output to ICH:
Direct Media Interface transmit differential pair
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37
Signal Description
2.5
Integrated Graphics Interface Signals
2.5.1
CRT DAC SIGNALS
Signal Name
CRT_BLUE
CRT_BLUE#
CRT_GREEN
CRT_GREEN#
CRT_HSYNC
CRT_RED
CRT_RED#
Type
O
A
O
A
O
A
O
A
O
HVCMOS
O
A
O
A
Description
BLUE Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
BLUE# Analog Output:
This signal is an analog video output from the internal color
palette DAC. This signal is used to provide noise immunity.
GREEN Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
GREEN# Analog Output:
This signal is an analog video output from the internal color
palette DAC. This signal is used to provide noise immunity.
CRT Horizontal Synchronization:
This signal is used as the horizontal sync (polarity is
programmable) or “sync interval”.
RED Analog Video Output:
This signal is a CRT Analog video output from the internal color
palette DAC.
RED# Analog Output:
This signal is an analog video output from the internal color
palette DAC. This signal is used to provide noise immunity.
Resistor Set and TV Reference Current:
CRT_TVO_IREF
CRT_VSYNC
38
O
A
O
HVCMOS
Set point resistor for the internal color palette DAC and TV
reference current. A 1.3 ΚΩ±0.5% resistor is required between
CRT_TVO_IREF and motherboard ground.
CRT Vertical Synchronization:
This signal is used as the vertical sync (polarity is
programmable).
Intel Confidential
External Design Specification
Signal Description
2.5.2
Analog TV-out Signals
Signal Name
Type
TV_DCONSEL[1:
0]
O
HVCMOS
Description
TV D-connector Select:
Selects appropriate full-voltage discernment signals for TV-out
D-connector
TVDAC Channel A Output:
TVA_DAC
O
A
Can map to any one of the following:
• Composite Video, Blank, and Sync (CVBS)
• Component Pb
TVA_RTN
O
Current Return for TV DAC Channel A:
A
Connect to ground on board
TVDAC Channel B Output:
TVB_DAC
O
A
Can map to any one of the following:
Svideo - Y
Component Y
TVB_RTN
O
Current Return for TV DAC Channel B:
A
Connect to ground on board
TVDAC Channel C Output:
TVC_DAC
O
A
Can map to any one of the following:
Svideo - C
Component Pr
TVC_RTN
External Design Specification
O
Current Return for TV DAC Channel C:
A
Connect to ground on board
Intel Confidential
39
Signal Description
2.5.3
LVDS Signals
Signal Name
Type
Description
LDVS Channel A
LVDSA_CLK
LVDSA_CLK#
LVDSA_DATA#[3:0]
LVDSA_DATA[3:0]
O
LVDS Channel A differential clock output – positive
LVDS
O
LVDS Channel A differential clock output – negative
LVDS
O
LVDS Channel A differential data output – negative
LVDS
O
LVDS Channel A differential data output – positive
LVDS
LDVS Channel B
LVDSB_CLK
LVDSB_CLK#
LVDSB_DATA#[3:0]
LVDSB_DATA[3:0]
O
LVDS Channel B differential clock output – positive
LVDS
O
LVDS Channel B differential clock output – negative
LVDS
O
LVDS Channel B differential data output – negative
LVDS
O
LVDS Channel B differential data output – positive
LVDS
Lfp Panel Power and Backlight Control
L_BKLT_CTRL
L_BKLT_EN
L_VDD_EN
O
Panel backlight brightness control
HVCMOS
Panel brightness control.
O
LVDS backlight enable
HVCMOS
O
Panel backlight enable control.
LVDS panel power enable
HVCMOS
Panel power control enable control.
LVDS Reference Signals
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
I/O
LVDS Reference Current.
Ref
A pull down resistor of 2.4 KΩ±1% is needed
O
Reserved
A
No connect
I
Reserved
Ref
I
Ref
40
Must be connected to ground.
Reserved
Must be connected to ground.
Intel Confidential
External Design Specification
Signal Description
2.5.4
Serial DVO Interface
All of the pins in this section are multiplexed with the upper eight lanes of the PCI
Express interface.
Signal Name
Type
Description
SDVO B Interface
SDVOB_BLUE
SDVOB_BLUE#
SDVOB_GREEN
SDVOB_GREEN#
SDVOB_RED
SDVOB_RED#
SDVOB_CLK
SDVOB_CLK#
O
Serial Digital Video B Blue Data:
PCI Express
O
Multiplexed with PEG_TXP2
Serial Digital Video B Blue Data Complement:
PCI Express
O
Multiplexed with PEG_TXN2
Serial Digital Video B Green Data:
PCI Express
O
Multiplexed with PEG_TXP1
Serial Digital Video B Green Data Complement:
PCI Express
O
Multiplexed with PEG_TXN1
Serial Digital Video B Red Data:
PCI Express
O
Multiplexed with PEG_TXP0
Serial Digital Video B Red Data Complement:
PCI Express
O
Multiplexed with PEG_TXN0
Serial Digital Video B Clock:
PCI Express
O
Multiplexed with PEG_TXP3
Serial Digital Video B Clock Complement:
PCI Express
Multiplexed with PEG_TXN3
SDVO C Interface
SDVOC_BLUE
SDVOC_BLUE#
SDVOC_GREEN
SDVOC_GREEN#
SDVOC_RED
SDVOC_RED#
SDVOC_CLK
SDVOC_CLK#
O
Serial Digital Video Channel C Blue:
PCI Express
O
Serial Digital Video C Blue Complement:
PCI Express
O
Multiplexed with PEG_TXN6
Serial Digital Video C Green:
PCI Express
O
Multiplexed with PEG_TXP5
Serial Digital Video C Green Complement:
PCI Express
O
Multiplexed with PEG_TXN5
Serial Digital Video C Red Data:
PCI Express
O
Multiplexed with PEG_TXP4
Serial Digital Video C Red Complement:
PCI Express
O
Multiplexed with PEG_TXN4
Serial Digital Video C Clock:
PCI Express
O
Multiplexed with PEG_TXP7
Serial Digital Video C Clock Complement:
PCI Express
External Design Specification
Multiplexed with PEG_TXP6
Multiplexed with PEG_TXN7
Intel Confidential
41
Signal Description
Signal Name
Type
Description
SDVO Common Signals
SDVO_FLDSTALL
SDVO_FLDSTALL#
SDVO_INT
SDVO_INT#
SDVO_TV_CLKIN
SDVO_TV_CLKIN#
2.5.5
Serial Digital Video Field Stall:
I
Multiplexed with PEG_RXP2
Serial Digital Video Field Stall Complement:
PCI Express
I
Multiplexed with PEG_RXN2
Serial Digital Video Input Interrupt:
PCI Express
I
Multiplexed with PEG_RXP1
Serial Digital Video Input Interrupt Complement:
PCI Express
I
Multiplexed with PEG_RXN1
Serial Digital Video TVOUT Synchronization Clock:
PCI Express
I
PCI Express
Multiplexed with PEG_RXP0
Serial Digital Video TVOUT Synchronization Clock
Complement:
Multiplexed with PEG_RXN0
Display Data Channel (DDC) and GMBUS Support
Signal Name
CRT_DDC_CLK
CRT_DDC_DATA
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
SDVO_CTRL_CLK
SDVO_CTRL_DATA
42
I
PCI Express
Type
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
COD
I/O
COD
Description
CRT DDC clock monitor control support
CRT DDC Data monitor control support
Control signal (clock) for External SSC clock chip control –
optional
Control signal (data) for External SSC clock chip control –
optional
EDID support for flat panel display
EDID support for flat panel display
Control signal (clock) for SDVO device
Control signal (data) for SDVO device
Intel Confidential
External Design Specification
Signal Description
2.6
Intel® Management Engine Interface Signals
Note:
The signals below are used as the Intel® Management Engine Interface between the
(G)MCH and the ICH. For details on implementing Intel Management Engine on the
Santa Rosa platform, refer to Santa Rosa Platform ME-EC Interaction Specification.
Signal Name
Type
CL_CLK
Supply
Independent
CMOS
Controller Link Bi Directional Clock
CL_DATA
Supply
Independent
CMOS
Controller Link Bi Directional Data
CL_PWROK
CL_RST#
I
HVCMOS
I
CMOS
I
CL_VREF
2.7
Description
Controller Link Power OK
Controller Link reset
External reference voltage for Controller Link input buffers
A
PLL Signals
Signal Name
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
Type
Description
I
Diff Clk
Display PLLA Differential Clock In Complement:
I
Diff Clk
Display PLL Differential Clock In Complement - no SSC
support.
Display PLLB Differential Clock In: 100-MHz Optional
Display PLL Differential Clock In for SSC support –
I
Diff Clk
DPLL_REF_SSCLK#
Display PLLA Differential Clock In: 96-MHz Display PLL
Differential Clock In, no SSC support
NOTE: Differential Clock input for optional SSC support for
LVDS display.
Display PLLB Differential Clock In Complement:
I
Diff Clk
Optional Display PLL Differential Clock In Complement for
SSC support.
NOTE: Differential Clock input for optional SSC support for
LVDS display.
Differential Host Clock In:
HPLL_CLK
External Design Specification
I
Diff Clk
Differential clock input for the Host PLL. Used for phase
cancellation for FSB transactions. This clock is used by all of
the (G)MCH logic that is in the Host clock domain. Also used
to generate core and system memory internal clocks. This is a
low voltage differential signal and runs at ¼ the FSB data
rate.
Intel Confidential
43
Signal Description
Signal Name
HPLL_CLK#
Type
Description
I
Diff Clk
Differential Host Clock Input Complement:
Differential PCI Express Based Graphics/DMI Clock In:
PEG_CLK
PEG_CLK#
2.8
I
Diff Clk
I
Diff Clk
These pins receive a differential 100-MHZ Serial Reference
clock from the external clock synthesizer. This clock is used to
generate the clocks necessary for the support of PCI Express.
Differential PCI Express based Graphics / DMI Clock In
complement
Reset and Miscellaneous Signals
Signal Name
CLKREQ#
GFX_VID[3:0]
GFX_VR_EN
ICH_SYNC#
PMSYNC#
(PM_BM_BUSY#)
DPRSLPVR
PM_DPRSTP#
Type
O
HVCMOS
O
A
O
A
O
HVCMOS
Description
External Clock Request:
(G)MCH drives CLK_REQ# to control the PCI Express*
differential clock input to itself.
Voltage ID to support Graphics Render Standby
Mode
VR Enable Signal to support Graphics Render
Standby Mode
ICH Synchronization:
Asserted to synchronize with ICH on faults. ICH_SYNC#
must be connected to ICH8M’s MCH_SYNC# signal.
(G)MCH Power Management Sync:
I
HVCMOS
I/O
HVCMOS
I
PMSYNC# is used to indicate some Cx state transition
information between ICH and (G)MCH.
Deeper Sleep - Voltage Regulator:
Deeper Sleep Voltage signal from ICH8M
Deeper Sleep State:
LVCMOS
Deeper Sleep State signal coming from ICH8M
External Thermal Sensor Input:
PM_EXT_TS#[1:0]
I
HVCMOS
If the system temperature reaches a dangerously high
value then this signal can be used to trigger the start of
system memory throttling.
Power OK:
PWROK
I
HVCMOS
When asserted, PWROK is an indication to the (G)MCH
that (G)MCH clocks have been stable for at least 1 us, and
that (G)MCH power supplies have been stable for at least
1 ms.
This input buffer is 3.3-V tolerant.
Reset In:
RSTIN#
I
HVCMOS
When asserted this signal will asynchronously reset the
(G)MCH logic. This signal is connected to the PCIRST#
output of the ICH8M.
This input has a Schmitt trigger to avoid spurious resets.
This input buffer is 3.3-V tolerant.
44
Intel Confidential
External Design Specification
Signal Description
Signal Name
Type
I
TEST1
I
This signal should be tied to ground.
Test 2:
HVCMOS
NC
2.9
Test 1:
HVCMOS
TEST2
Description
NC
This signal should be tied to ground.
No Connects:
This signals should be left as no connects.
Non-Critical to Function (NCTF)
As a function of Intel's continuous improvement goals, we have identified package level
modifications that add to the overall solder joint strength and reliability of our
component. Through our research and development, we have concluded that adding
non-critical to function (NCTF) solder balls to our packages can improve the overall
package-to-board solder joint strength and reliability.
Ball locations/signal ID's followed with the suffix of NCTF have been designed into the
package footprint to enhance the package to board solder joint strength/reliability of
this product by absorbing some of the stress introduced by the Characteristic Thermal
Expansion (CTE) mismatch of the Die to package interface.
It is expected that in some cases, where board stresses are excessive, these balls may
crack partially or completely, however, cracks in the NCTF balls will have no impact to
our product performance or reliability. Intel has added these balls primarily to serve as
stress absorbers.
2.10
Power and Ground
Voltage
Ball Name
Description
Host
1.05
VTT
Host Interface I/O Voltage
1.05
VTTLF
These balls are internally connected to power and
require a decoupling capacitor.
System Memory
1.8
1.8
1.8
VCC_SM
I/O Voltage
VCC_SM_LF
These balls are internally connected to power and
require a decoupling capacitor.
VCC_SM_CK
Clock I/O Voltage
1.25
VCCA_SM
I/O Logic and DLL voltage
1.25
VCCA_SM_CK
Clock logic voltage
PCI Express* Based Graphics / DMI
VCC_PEG
Analog, I/O Logic, and Term Voltage for PCI Express
Based Graphics
3.3
VCCA_PEG_BG
Band Gap Voltage for PCI Express Based Graphics
Ground
VSSA_PEG_BG
Band Gap Ground for PCI Express Based Graphics
1.05
External Design Specification
Intel Confidential
45
Signal Description
Voltage
Ball Name
Description
1.25
VCCA_PEG_PLL
Analog PLL Voltage for PCI Express Based Graphics
1.25
VCCD_PEG_PLL
Digital PLL Voltage for PCI Express Based Graphics
1.25
VCC_DMI
TX Analog and Term Voltage for DMI
1.05
VCC_RXR_DMI
Rx and I/O Logic for DMI
PLL
1.25
VCCA_HPLL
Host PLL Analog Supply
1.25
VCCD_HPLL
Host PLL Digital Supply
1.25
VCCA_MPLL
MPLL Analog circuits
1.25
VCCA_DPLLA
Display A PLL power supply
1.25
VCCA_DPLLB
Display B PLL power supply
High Voltage
3.3
VCC_HV
HV buffer power supply
CRT
3.3
VCC_SYNC
HSYNC/VSYNC power supply
3.3
VCCA_CRT_DAC
Analog power supply
1.5
VCCD_QDAC
Quiet digital power supply (same as VCCD_QDAC for
TV)
1.5
VCCD_CRT
Level shifter voltage
3.3
VCC_SYNC
HSYNC/VSYNC power supply
3.3
VCCA_CRT_DAC
Analog power supply
1.5
VCCD_QDAC
Quiet digital power supply (same as VCCD_QDAC for
TV)
1.5
VCCD_CRT
Level shifter voltage
LVDS
1.8
VCCD_LVDS
Digital power supply
1.8
VCC_TX_LVDS
I/O power supply
1.8
VCCA_LVDS
Analog power supply
Ground
VSSA_LVDS
Analog ground
TV
1.5
VCCD_TVDAC
TV DAC power supply
3.3
VCCA_TVA_DAC
TV Out Channel A power supply
3.3
VCCA_TVB_DAC
TV Out Channel Bpower supply
3.3
VCCA_TVC_DAC
TV Out Channel Cpower supply
1.5
VCCD_QDAC
Quiet Digital TV DAC Power Supply (same as
VCCDQ_DAC for CRT)
3.3
VCCA_DAC_BG
TV DAC Band Gap Power (3.3 V)
Ground
VSSA_DAC_BG
TV DAC Band Gap Ground
Intel Management Engine
46
Intel Confidential
External Design Specification
Signal Description
Voltage
1.05
Ball Name
VCC_AXM
Description
Controller Link / ME voltage supply
Graphics Core
1.05
VCC
Core chipset voltage supply
1.05
VCC_AXG
Graphics voltage supply
1.25
VCC_AXD
Memory voltage supply
1.25
VCC_AXF
I/O voltage supply
Ground
VSS
Ground
Ground
VSS_SCB
Sacrificial Corner Balls for improved package
reliability
§
External Design Specification
Intel Confidential
47
Signal Description
48
Intel Confidential
External Design Specification
Host Interface
3
Host Interface
3.1
FSB Source Synchronous Transfers
The chipset supports the Intel Core 2 Duo Mobile Processor (for Santa Rosa platform)
subset of the Enhanced Mode Scaleable bus. The cache line size is 64 bytes. Source
synchronous transfer is used for the address and data signals. The address signals are
double pumped and a new address can be generated every other bus clock. At bus
clock speeds of 133-MHz, 166-MHz and 200-MHz, address signals run at 266MT/s, 333MT/s and 400-MT/s which amounts to a maximum address queue rate of 64, 83 and
100 Mega-addresses/sec, respectively. Data signals are quad pumped and an entire
64B cache line can be transferred in two bus clocks. At 133-MHz, 166-MHz and 200MHz bus clock, data signals run at 533-MHz, 667-MT/s and 800-MT/s for a maximum
bandwidth of 4.3-GB/s, 5.3-GB/s and 6.4-GB/s, respectively.
3.2
FSB IOQ Depth
The scalable bus supports up to 12 simultaneous outstanding transactions. The chipset
has a 12-deep IOQ.
3.3
FSB OOQ Depth
The (G)MCH supports only one outstanding deferred transaction on the FSB.
3.4
FSB AGTL+ Termination
The (G)MCH integrates AGTL+ termination resistors on die.
3.5
FSB Dynamic Bus Inversion
The (G)MCH supports dynamic bus inversion (DBI) when driving and when receiving
data from the processor. DBI limits the number of data signals that are driven to a low
voltage on each quad pumped data phase. This decreases the worst-case power
consumption of the (G)MCH. H_DINV[3:0]# indicate if the corresponding 16 bits of
data are inverted on the bus for each quad pumped data phase:
H_DINV#[3:0]
Data Bits
H_DINV#0
H_D#[15:0]
H_DINV#1
H_D#[31:16]
H_DINV#2
H_D#[47:32]
H_DINV#3
H_D#[63:48]
Whenever the processor or the (G)MCH drives data, each 16-bit segment is analyzed.
If there are more than eight (out of sixteen) signals driven low on the H_D# bus, a
corresponding H_DINV# signal is asserted. As a result, the data is inverted prior to
being driven on the bus. Whenever the processor or the (G)MCH receives data, it
monitors H_DINV#[3:0] to determine if the corresponding data segment should be
inverted.
External Design Specification
Intel Confidential
49
Host Interface
3.6
FSB Interrupt Overview
The Intel Core 2 Duo Mobile Processor for Santa Rosa platform supports FSB interrupt
delivery. It does not support the APIC serial bus interrupt delivery mechanism.
Interrupt related messages are encoded on the FSB as Interrupt Message Transactions.
FSB interrupts may originate from the CPU(s) on the FSB, or from a downstream device
on the DMI or PCI Express Graphics Attach. In the latter case, the (G)MCH drives the
“Interrupt Message Transaction” on the FSB.
In the IOxAPIC environment, an interrupt is generated from the IOxAPIC to a processor
in the form of an upstream memory write. The ICH contains IOxAPICs, and its
interrupts are generated as upstream DMI Memory Writes. Furthermore, the PCI
specification and PCI Express Specification define Message Signaled Interrupts (MSI’s)
that are also in the form of Memory Writes. A PCI device may generate an interrupt as
an MSI cycle on its PCI bus instead of asserting a hardware signal to the IOxAPIC. The
MSI may be directed to the IOxAPIC. The IOxAPIC in turn generates an interrupt as an
upstream DMI Memory Write. Alternatively, the MSI may directly route to the FSB. The
target of an MSI is dependent on the address of the interrupt Memory Write. The
(G)MCH forwards upstream DMI and PCI Express Graphics Attach low priority Memory
Writes to address 0FEEx_xxxxh to the FSB as Interrupt Message Transactions.
The (G)MCH also broadcasts EOI cycles generated by a processor downstream to the
PCI Express Port and DMI interfaces.
3.7
APIC Cluster Mode support
APIC Cluster mode support is required is required for backwards compatibility with
existing software, including various operating systems. For example, beginning with
Microsoft Windows* 2000 operating system, there is a mode (boot.ini) that allows an
end user to enable the use of cluster addressing support of the APIC.
§
50
Intel Confidential
External Design Specification
System Address Map
4
System Address Map
The Mobile Intel 965 Express Chipset supports up to 64 GB of addressable memory
space and 64 kB+3 B of addressable I/O space. There is a programmable memory
address space under the 1-MB region which is divided into regions which can be
individually controlled with programmable attributes such as Disable, Read/Write, Write
Only, or Read Only.This section focuses on how the memory space is partitioned and
what the separate memory regions are used for. I/O address space has simpler
mapping and is explained near the end of this section.
The (G)MCH does not support the PCI dual address cycle (DAC) mechanism, PCI
Express 64-bit prefetchable memory transactions, or any other addressing mechanism
that allows addressing of greater than 4 GB on either the DMI or PCI Express interface.
The (G)MCH does not limit DRAM space in hardware. There is no hardware lock to stop
someone from inserting more memory than is addressable.
In the following sections, it is assumed that all of the compatibility memory ranges
reside on the DMI. The exception to this rule is VGA ranges, which may be mapped to
PCI Express, DMI, or to the internal graphics device (IGD). In the absence of more
specific references, cycle descriptions referencing PCI should be interpreted as the
DMI/PCI, while cycle descriptions referencing PCI Express or IGD are related to the PCI
Express bus or the internal graphics device respectively. The (G)MCH does not remap
APIC or any other memory spaces above TOLUD (Top of Low Usable DRAM). The TOLUD
register is set to the appropriate value by BIOS.
The Address Map includes a number of programmable ranges:
• Device 0
— EPBAR – Egress port registers. Necessary for setting up VC1 as an isochronous
channel using time based weighted round robin arbitration. (4-kB window)
— MCHBAR – Memory mapped range for internal (G)MCH registers.
— PCIEXBAR – Flat memory-mapped address spaced to access device
configuration registers. This mechanism can be used to access PCI
configuration space (0-FFh) and extended configuration space (100h-FFFh) for
PCI Express devices. This enhanced configuration access mechanism is defined
in the PCI Express specification. (64-MB, 128-MB, or 256-MB window).
— DMIBAR –This window is used to access registers associated with .. in the MCH/
ICH (DMI) register memory range. (4-kB window)
— GGC – (G)MCH graphics control register. Used to select the amount of main
memory that is pre-allocated to support the internal graphics device in VGA
(non-linear) and Native (linear) modes. (0 to 64-MB options).
• Device 1, Function 0:
— MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window.
— PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window.
(PMUBASE/PMULIMIT) - are applicable for 36-bit SKUs
— IOBASE1/IOLIMIT1 – PCI Express port IO access window.
External Design Specification
Intel Confidential
51
System Address Map
• Device 2, Function 0:
— MMADR – IGD registers and internal graphics instruction port. (512-kB window)
— IOBAR – I/O access window for internal graphics. Through this window
address/data register pair, using I/O semantics, the IGD and internal graphics
instruction port registers can be accessed. Note this allows accessing the same
registers as MMADR. In addition, the IOBAR can be used to issue writes to the
GTTADR table.
— GMADR – Internal graphics translation window. (256-MB window)
— GTTADR – Internal graphics translation table location. (256-kB window).
• Device 2, Function 1:
— MMADR – Function 1 IGD registers and internal graphics instruction port. (512kB window)
• Device 3, Function 0:
— EPHECIBAR - Function 0 HECI memory mapped registers (16-B window)
• Device 3, Function 1:
— EPHECI2BAR - Function 0 HECI memory mapped registers (16-B window)
• Device 3, Function 3:
— EPKTBAR - Function 3 Keyboard and Text IO space (8-B window)
The rules for the above programmable ranges are:
1. ALL of these ranges MUST be unique and NON-OVERLAPPING. It is the BIOS or
system designers responsibility to limit memory population so that
adequate PCI, PCI Express, High BIOS, PCI Express Memory Mapped
space, and APIC memory space can be allocated.
2. In the case of overlapping ranges with memory, the memory decode will be given
priority.
3. There are NO Hardware Interlocks to prevent problems in the case of overlapping
ranges.
4. Accesses to overlapped ranges may produce indeterminate results.
5. The only peer-to-peer cycles allowed below the top of memory (register TOLUD)
are DMI to PCI Express VGA range writes. Note that peer to peer cycles to the
Internal Graphics VGA range are not supported.
Figure 2 represents system memory address map in a simplified form.
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Intel Confidential
External Design Specification
System Address Map
Figure 2.
System Address Ranges
M a x L im it 6 4 G B
P C I M e m o ry
A d d re s s
Range
D e v ic e 0
BARS
(E P B A R ,
MCHBAR,
P C IE X B A R ,
D M IB A R )
M a in M e m o ry
A d d re s s
Range
R E M A P B A S E /L IM IT
D e v ic e 1
(P M B A S E U /
P M L IM IT U )
D e v ic e 2
(M M A D R ,
GMADR,
G TTADR)
D e v ic e 3
(E P H E C IB A R ,
E P H E C I2 B A R )
R E M A P L IM IT
REM APBASE=TO UUD
4 GB
P C I M e m o ry
A d d re s s
Range
D e v ic e 1
(M B A S E 1 /
M L IM IT 1 )
In d e p e n d e n tly P ro g ra m m a b le
N o n -O v e rla p p in g W in d o w s
D e v ic e 3
(E P K T B A R )
TO LUD
M a in M e m o ry
A d d re s s
Range
D e v ic e 0
GGC
(G ra p h ic s
S to le n
M e m o ry )
In d e p e n d e n tly P ro g ra m m a b le
N o n -O v e rla p p in g W in d o w s
1 MB
Legacy
A d d re s s
Range
0
NOTES:
1.
BARs mapped to the REMAPLIMIT-64 GB space can also be mapped to the TOLUD-4 GB
space. (G)MCH variants not supporting 36-bit addressing will require these BARs to be
mapped to the TOLUD-4 GB space.
4.1
Legacy Address Range
This area is divided into the following address regions:
• 0 - 640 kB – DOS Area
• 640 - 768-kB – Legacy Video Buffer Area
• 768 - 896 kB in 16-kB sections (total of eight sections) – Expansion Area
• 896 -960 kB in 16-kB sections (total of four sections) – Extended System BIOS
Area
• 960-kB - 1-MB Memory – System BIOS Area
External Design Specification
Intel Confidential
53
System Address Map
Figure 3.
DOS Legacy Address Range
1 MB
System BIOS (Upper)
64 kB
960 kB
Extended System BIOS (Lower)
64 kB (4 x 16 kB)
896 kB
000F_FFFFh
000F_0000h
000E_FFFFh
000E_0000h
000D_FFFFh
Expansion Area
128 kB (8 x 16 kB)
000C_0000h
000B_FFFFh
768 kB
Legacy Video Area (SMM Memory)
128 kB
000A_0000h
0009_FFFFh
640 kB
DOS Area
640 kB
0000_0000h
0
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Intel Confidential
External Design Specification
System Address Map
4.1.1
DOS Range (0000_0000h – 0009_FFFFh)
The DOS area is 640 kB (0000_0000h to 0009_FFFFh) in size and is always mapped to
the main memory controlled by the (G)MCH.
4.1.2
Legacy Video Area (000A_0000h to 000B_FFFFh)
The legacy 128-kB VGA memory range, frame buffer, (000A_0000h to 000B_FFFFh)
can be mapped to IGD (Device #2), to PCI Express (Device #1), and/or to the DMI.
The appropriate mapping depends on which devices are enabled and the programming
of the VGA steering bits. Based on the VGA steering bits, priority for VGA mapping is
constant. The (G)MCH always decodes internally mapped devices first. Internal to the
(G)MCH, decode precedence is always given to IGD. The (G)MCH always positively
decodes internally mapped devices, namely the IGD and PCI Express. Subsequent
decoding of regions mapped to PCI Express or the DMI depends on the Legacy VGA
configuration bits (VGA Enable and MDAP). This region is also the default for SMM
space.
4.1.2.1
Compatible SMRAM Address Range (000A_0000h to 000B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range
are routed to physical system DRAM at 000A 0000h to 000B FFFFh. Non-SMM-mode
processor accesses to this range are considered to be to the Video Buffer Area as
described above. PCI Express and DMI originated cycles to enabled SMM space are not
allowed and are considered to be to the Video Buffer Area if IGD is not enabled as the
VGA device. PCI Express and DMI initiated cycles are attempted as Peer cycles, and will
master abort on PCI if no external VGA device claims them.
4.1.2.2
Monochrome Adapter (MDA) Range (000B_0000h to 000B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,
or the DMI (depending on configuration bits). Since the monochrome adapter may be
mapped to any one of these devices, the (G)MCH must decode cycles in the MDA range
(000B_0000h to 000B_7FFFh) and forward either to IGD, PCI Express, or the DMI. This
capability is controlled by a VGA steering bits and the legacy configuration bit (MDAP
bit). In addition to the memory range B0000h to B7FFFh, the (G)MCH decodes IO
cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards them to the either
IGD, PCI Express, and/or the DMI.
4.1.3
Expansion Area (000C_0000h to 000D_FFFFh)
This 128-kB ISA Expansion region (000C_0000h – 000D_FFFFh) is divided into eight 16
kB segments. Each segment can be assigned one of four Read/Write states: read-only,
write-only, read/write, or disabled. Typically, these blocks are mapped through (G)MCH
and are subtractively decoded to ISA space. Memory that is disabled is not remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
External Design Specification
Intel Confidential
55
System Address Map
Table 2.
4.1.4
Expansion Area Memory Segments
Memory Segments
Attributes
Comments
000C_0000h to
000C_3FFFh
W/R
Add-on BIOS
000C_4000h to
000C_7FFFh
W/R
Add-on BIOS
000C_8000h to
000C_BFFFh
W/R
Add-on BIOS
000C_C000h to
000C_FFFFh
W/R
Add-on BIOS
000D_0000h to
000D_3FFFh
W/R
Add-on BIOS
000D_4000h to
000D_7FFFh
W/R
Add-on BIOS
000D_8000h to
000D_BFFFh
W/R
Add-on BIOS
000D_C000h to
000D_FFFFh
W/R
Add-on BIOS
Extended System BIOS Area (000E_0000h to 000E_FFFFh)
This 64-kB area (000E_0000h to 000E_FFFFh) is divided into four, 16-kB segments.
Each segment can be assigned independent read and write attributes so it can be
mapped either to main DRAM or to DMI. Typically, this area is used for RAM or ROM.
Memory segments that are disabled are not remapped elsewhere.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
Table 3.
4.1.5
Extended System BIOS Area Memory Segments
Memory Segments
Attributes
Comments
000E_0000h to 000E_3FFFh
W/R
BIOS Extension
000E_4000h to 000E_7FFFh
W/R
BIOS Extension
000E_8000h to 000E_BFFFh
W/R
BIOS Extension
000E_C000h to 000E_FFFFh
W/R
BIOS Extension
System BIOS Area (000F_0000h to 000F_FFFFh)
This area is a single 64-kB segment (000F_0000h – 000F_FFFFh). This segment can be
assigned read and write attributes. It is by default (after reset) Read/Write disabled
and cycles are forwarded to DMI. By manipulating the Read/Write attributes, the
(G)MCH can “shadow” BIOS into the main DRAM. When disabled, this segment is not
remapped.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
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Table 4.
System BIOS Area Memory Segments
Memory Segments
000F_0000h to
000F_FFFFh
4.1.6
Attributes
WE
RE
Comments
BIOS Area
Programmable Attribute Map (PAM) Memory Area Details
The 13 sections from 768 kB to 1 MB comprise what is also known as the PAM Memory
Area.
The (G)MCH does not handle IWB (Implicit Write-Back) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there normally will not be
IWB cycles targeting DMI.
However, DMI becomes the default target for processor and DMI originated accesses to
disabled segments of the PAM region. If the MTRRs covering the PAM regions are set to
WB or RD it is possible to get IWB cycles targeting DMI. This may occur for DMI
originated cycles to disabled PAM regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. A snoop is generated on the FSB and the result is an IWB.
Since the PAM region is “Read Disabled” the default target for the Memory Read
becomes DMI. The IWB associated with this cycle will cause the (G)MCH to hang.
4.2
Main Memory Address Range (1 MB to TOLUD)
This address range extends from 1 MB to the top of physical memory that is permitted
to be accessible by the (G)MCH (as programmed in the TOLUD register). All accesses to
addresses within this range will be forwarded by the (G)MCH to the DRAM unless they
fall into the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
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System Address Map
Figure 4.
Main Memory Address Range (0 to 4 GB)
4 GB
FFFF_FFFFh
F la sh
A P IC
C onta ins: D e vice 0, 1 , 2 ,
B A R s & IC H /P C I ranges
P C I M e m o ry R a n g e
TO LUD
In te rn a l G ra p h ic s (o p tio n a l)
T S E G (o p tio n a l)
M a in M e m o ry
16 M B
15 M B
0100_0000h
IS A H o le (o p tio n a l)
00F0_0000h
M a in M e m o ry
1 MB
0
4.2.1
0010_0000h
D O S C o m p a tib ility M e m o ry
0000_0000h
ISA Hole (15 MB to 16 MB)
A hole can be created at 15 MB to 16 MB as controlled by the fixed hole enable in
Device 0 space. Accesses within this hole are forwarded to the DMI. The range of
physical DRAM memory disabled by opening the hole is not remapped to the top of the
memory – that physical DRAM space is not accessible. This 15-MB to 16-MB hole is an
optionally enabled ISA hole.
Video accelerators originally used this hole. It is also used for validation by customer
teams for some of their test cards. That is why it is being supported. There is no
inherent BIOS request for the 15-MB to 16-MB window.
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4.2.2
TSEG
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory,
which is at the top of physical memory. System management software may partition
this region of memory so it is accessible only by system management software. SMMmode processor accesses to enabled TSEG access the physical DRAM at the same
address. Non-processor originated accesses are not allowed to SMM space. PCI
Express, DMI, and Internal Graphics originated cycles to enabled SMM space are
handled as invalid cycle type with reads and writes to location 0 and byte enables
turned off for writes. When the extended SMRAM space is enabled, processor accesses
to the TSEG range without SMM attribute or without WB attribute are also forwarded to
memory as invalid accesses (see Table 6). Non-SMM-mode Write Back cycles that
target TSEG space are completed to DRAM for cache coherency. When SMM is enabled
the maximum amount of memory available to the system is equal to the amount of
physical DRAM minus the value in the TSEG register which is fixed at 1 MB, 2 MB or
8 MB.
4.2.3
Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and
reside within system memory address range (< TOLUD) are created for SMM-mode and
legacy VGA graphics compatibility. It is the responsibility of BIOS to properly
initialize these regions. Table 5 details the location and attributes of the regions.
How to enable and disable these ranges are described in the (G)MCH Control Register
Device #0 (GGC).
Table 5.
Pre-allocated Memory Example for 512-MB DRAM, 64-MB VGA, and 1-MB TSEG
Memory Segments
Attributes
0000_0000h to
1BEF_FFFFh
R/W
1BF0_0000h to
1BFF_FFFFh
SMM Mode Only Processor Reads
1C00_0000h t 1FFF_FFFFh
External Design Specification
R/W
Comments
Available System Memory 447 MB
TSEG Address Range & Pre-allocated Memory
Pre-allocated Graphics VGA memory.
64 MB when IGD is enabled.
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System Address Map
4.3
PCI Memory Address Range (TOLUD to 4 GB)
This address range, from the top of physical memory to 4 GB (top of addressable
memory space supported by the (G)MCH) is normally mapped to the DMI Interface.
Exceptions to this mapping include the BAR memory mapped regions, which include:
EPBAR, MCHBAR, and DMIBAR.
In the PCI Express port, there are two exceptions to this rule:
• Addresses decoded to the PCI Express memory window defined by the MBASE1,
MLIMIT1, PMBASE1, and PMLIMIT1 registers are mapped to PCI Express.
• Addresses decoded to PCI Express configuration space are mapped based on Bus,
Device, and Function number. (PCIEXBAR range)
Note:
AGP Aperture no longer exists with PCI Express.
In an internal graphics configuration, there are three exceptions to this rule:
1. Addresses decoded to the Graphics Memory Range. (GMADR range)
2. Addresses decoded to the Graphics Translation Table range (GTTADR range).
3. Addresses decoded to the Memory Mapped Range of the Internal Graphics Device
(MMADR range). There is a MMADR range for device 2 function 0 and a MMADR
range for device 2 function 1. Both ranges are forwarded to the internal graphics
device.
In an Intel Management Engine configuration, there are exceptions to this rule.
1. Addresses decoded to the Intel Management Engine keyboard and Text MMIO
range (EPKTBAR)
The exceptions listed above for internal graphics and the PCI Express ports MUST NOT
overlap with APIC Configuration Space, FSB Interrupt Space and High BIOS
Address Range.
Note:
60
With the exception of certain BARs, all the above mentioned BARs can be mapped in
the TOUUD to 64-GB range in the case of chipset variants supporting 36-bit addressing.
See Figure 2 for details.
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External Design Specification
System Address Map
Figure 5.
PCI Memory Address Range
4 GB
High BIOS
4 GB minus 2 MB
FFFF_FFFFh
FFE0_0000h
DMI Interface
(subtractive decode)
FEF0_0000h
4 GB minus 17 MB
FSB Interrupts
4 GB minus 18 MB
4 GB minus 19 MB
4 GB minus 20 MB
FED0_0000h
Local (CPU) APIC
FEC8_0000h
I/O APIC
FEC0_0000h
DMI Interface
(subtractive decode)
PCI Express Configuration
Space
E000_0000h
4 GB minus 512 MB
Internal Graphics
ranges
PCI Express Port
Optional HSEG
FEDA_0000h to
FEDB_FFFFh
F000_0000h
4 GB minus 256 MB
Possible address
range
FEE0_0000h
DMI Interface
(subtractive decode)
DMI Interface
(subtractive decode)
TOLUD
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System Address Map
4.3.1
APIC Configuration Space (FEC0_0000h to FECF_FFFFh)
This range is reserved for APIC configuration space which includes the default I/O APIC
configuration space from FEC0_0000h to FEC7_0FFFh. The default Local (Processor)
APIC configuration space goes from FEC8_0000h to FECF_FFFFh.
Processor accesses to the Local APIC configuration space do not result in external bus
activity since the Local APIC configuration space is internal to the processor. However,
an MTRR must be programmed to make the Local APIC range uncacheable (UC). The
Local APIC base address in each processor should be relocated to the FEC0_0000h (4
GB minus 20 MB) to FECF_FFFFh range so that one MTRR can be programmed to 64 kB
for the Local and I/O APICs. The I/O APIC(s) usually reside in the ICH portion of the
chip set or as a stand-alone component(s).
I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/
O APIC will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h
where x is I/O APIC unit number 0 through F (hex). This address range will normally be
mapped to DMI.
Note:
There is no provision to support an I/O APIC device on PCI Express.
4.3.2
HSEG (FEDA_0000h to FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping window
to SMM memory. It is sometimes called the High SMM memory space. SMM-mode
processor accesses to the optionally enabled HSEG are remapped to 000A_0000h to
000B_FFFFh. Non-SMM mode processor accesses to enabled HSEG are considered
invalid and are terminated immediately on the FSB. The exceptions to this rule are
Non-SMM mode Write Back cycles which are remapped to SMM space to maintain cache
coherency. PCI Express and DMI originated cycles to enabled SMM space are not
allowed. Physical DRAM behind the HSEG transaction address is not remapped and is
not accessible. All Cacheline writes with WB attribute or implicit write backs to the
HSEG range are completed to DRAM like an SMM cycle.
4.3.3
FSB Interrupt Memory Space (FEE0_0000 to FEEF_FFFF)
The FSB Interrupt space is the address used to deliver interrupts to the FSB. Any
device on PCI Express, internal graphics, or DMI may issue a Memory Write to
0FEEx_xxxxh. The (G)MCH will forward this Memory Write along with the data to the
FSB as an Interrupt Message Transaction. The (G)MCH terminates the FSB transaction
by providing the response and asserting H_TRDY#. This Memory Write cycle does not
go to DRAM.
4.3.4
High BIOS Area
The top 2 MB (FFE0_0000h to FFFF_FFFFh) of the PCI Memory Address Range is
reserved for system BIOS (High BIOS), extended BIOS for PCI devices, and the A20
alias of the system BIOS. The processor begins execution from the High BIOS after
reset. This region is mapped to DMI so that the upper subset of this region aliases to
the 16-MB minus 256-kB range. The actual address space required for the BIOS is less
than 2 MB, but the minimum processor MTRR range for this region is 2 MB so a full 2
MB must be considered.
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4.4
Main Memory Address Space (4 GB to TOUUD)
Earlier chipsets supported a maximum main memory size of 4-GB total memory. This
would result in a hole between TOLUD (Top of Low Usable DRAM) and 4 GB when main
memory size approached 4 GB, resulting in a certain amount of physical memory being
inaccessible to the system.
The new reclaim configuration registers (TOUUD, REMAPBASE, REMAPLIMIT) exist to
reclaim lost main memory space. The greater than 32-bit reclaim handling will be
handled similar to other MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by PCI Express Graphics and DMI.
The Top of Memory (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist in
main memory address map due to addresses allocated for memory mapped IO above
TOM). TOM is used to allocate the Intel Management Engine stolen memory. The Intel
Management Engine stolen size register reflects the total amount of physical memory it
has stolen. The Intel Management Engine stolen memory is located at the top of
physical memory, and the memory base is calculated by subtracting the amount of
memory stolen by the Intel Management Engine from TOM.
The Top of Upper Usable DRAM (TOUUD) register reflects the total amount of
addressable memory. If reclaim is disabled, TOUUD will reflect TOM minus Intel
Management Engine’s stolen size. If reclaim is enabled, then it will reflect the reclaim
limit. Also, the reclaim base will be the same as TOM minus Intel Management Engine
stolen memory size to the nearest 64-MB alignment.
4.4.1
Memory Re-Map Background
The following examples of Memory Mapped I/O devices are typically located below 4
GB:
• High BIOS
• H-Seg
• T-Seg
• Graphics Stolen Memory
• XAPIC
• Local APIC
• FSB Interrupts
• Mbase / Mlimit
• Memory Mapped I/O space that supports only 32-bit addressing
The (G)MCH provides the capability to remap or reclaim the physical memory
overlapped by the Memory Mapped I/O logical address space. The (G)MCH re-maps
physical memory from the Top of Low Usable DRAM (TOLUD) boundary up to the 4-GB
boundary to an equivalent sized logical address range located just below the Intel
Management Engine’s stolen memory.
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System Address Map
4.4.2
Memory Remapping (or Reclaiming)
An incoming address (referred to as a logical address) is checked to see if it falls in the
memory re-map window. The bottom of the re-map window is defined by the value in
the REMAPBASE register. The top of the re-map window is defined by the value in the
REMAPLIMIT register. An address that falls within this window is remapped to the
physical memory starting at the address defined by the TOLUD register. The TOLUD
register must by 64-MB aligned when remapping is enabled, but can be 1-MB aligned
when remapping is disabled.
4.5
PCI Express Configuration Address Space
The device 0 register (PCIEXBAR), defines the base address for the configuration space
associated with all devices and functions that are potentially a part of the PCI Express
root complex hierarchy. This is a 256-MB block of addresses below top of addressable
memory (currently 4 GB) and is aligned to a 256-MB boundary. BIOS must assign this
address range such that it will not conflict with any other address ranges.
4.5.1
PCI Express Graphics Attach
The (G)MCH can be programmed to direct memory accesses to the PCI Express
interface when addresses are within either of two ranges specified via registers in
(G)MCH’s Device #1 configuration space.
• The first range is controlled via the Memory Base Register (MBASE) and Memory
Limit Register (MLIMIT) registers.
• The second range is controlled via the Prefetchable Memory Base (PMBASE/
PMBASEU) and Prefetchable Memory Limit (PMLIMIT/PMLIMITU) registers.
The (G)MCH positively decodes memory accesses to PCI Express memory address
space as defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
It is essential to support a separate Prefetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
Note that the (G)MCH Device #1 memory range registers described above are used to
allocate memory address space for any PCI Express devices sitting on PCI Express that
require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set in the device 1 PCICMD1
register to enable the memory base/limit and prefetchable base/limit windows.
4.5.2
Graphics Aperture
Unlike AGP, PCI Express has no concept of aperture for PCI Express devices. As a
result, there is no need to translate addresses from PCI Express. Therefore, the
(G)MCH has no APBASE and APSIZE registers.
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4.6
Graphics Memory Address Ranges
The (G)MCH can be programmed to direct memory accesses to IGD when addresses
are within any of three ranges specified via registers in (G)MCH’s Device #2
configuration space.
• The Memory Map Base Register (MMADR) is used to access graphics control
registers.
• The Graphics Memory Aperture Base Register (GMADR) is used to access graphics
memory allocated via the graphics translation table.
• The Graphics Translation Table Base Register (GTTADR) is used to access the
translation table.
Normally these ranges will reside above the Top-of-Main-DRAM and below high BIOS
and APIC address ranges. They normally reside above the top of memory (TOLUD) so
they do not steal any physical DRAM memory space.
GMADR is a Prefetchable range in order to apply USWC attribute (from the processor
point of view) to that range. The USWC attribute is used by the processor for write
combining.
4.6.1
Graphics Register Ranges
This section provides a high-level register map (register groupings per function) for the
integrated graphics. The memory and I/O maps for the graphics registers are shown in
Figure 6, except PCI Configuration registers, which are described in Volume 2 of this
document. The VGA and Extended VGA registers can be accessed via standard VGA I/O
locations as well as via memory-mapped locations. In addition, the memory map
contains allocation ranges for various functions. The memory space address listed for
each register is an offset from the base memory address programmed into the MMADR
register (PCI configuration offset 14h). The same memory space can be accessed via
dword accesses to I/OBAR. Through the IOBAR, I/O registers MMIO_index and
MMIO_data are written.
VGA and Extended VGA Control Registers (0000_0000h to 0000_0FFFh):
These registers are located in both I/O space and memory space. The VGA and
Extended VGA registers contain the following register sets: General Control/Status,
Sequencer (SRxx), Graphics Controller (GRxx), Attribute Controller (ARxx), VGA Color
Palette, and CRT Controller (CRxx) registers.
Instruction, Memory, and Interrupt Control Registers (0000_1000h to
0000_2FFFh):
The Instruction and Interrupt Control registers are located in space and contain the
types of registers listed in the following sections.
4.6.2
I/O Mapped Access to Device 2 MMIO Space
If Device 2 is enabled, and Function 0 within device 2 is enabled, then IGD registers
can be accessed using the IOBAR.
MMIO_Index: MMIO_INDEX is a 32-bit register. An I/O write to this port loads the
address of the MMIO register that needs to be accessed. I/O Reads returns the current
value of this register.
MMIO_Data: MMIO_DATA is a 32-bit register. An I/O write to this port is re-directed to
the MMIO register pointed to by the MMIO-index register. An I/O read to this port is redirected to the MMIO register pointed to by the MMIO-index register.
External Design Specification
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System Address Map
Figure 6.
Graphics Register Memory and I/O Map
Memory Space Map
(512 kB allocation)
Cursor Registers
Display Registers
Pixel Pipe Registers
TV Out Registers
Misc. Multimedia Registers
Offset From
Base_Reg
0007_FFFFh
0007_0000h
0006_FFFFh
0006_0000h
0005_FFFFh
Host Port Registers
Note:
Some Overlay registers are
double-buffered with an
additional address range in
graphics memory
Bit Engine Control Status
(RO)
0005_0000h
0004_FFFFh
0004_0000h
0003_FFFFh
Overlay Registers
0003_0000h
0002_FFFFh
0001_0000h
0000_FFFFh
Reserved
0000_B000h
0000_AFFFh
Display Palette Registers
0000_A000h
0000_9FFFh
Reserved
0000_7000h
0000_6FFFh
Clock Control Registers
0000_6000h
0000_5FFFh
Misc I/O Control Registers
0000_5000h
0000_4FFFh
Reserved
Local Memory Interface
Control Registers
I/O Space Map
(Standard graphics locations)
Instruction Control Registers
Interrupt Control
VGA and Ext. VGA Registers
VGA and Ext. VGA Registers
0000_4000h
0000_3FFFh
0000_3000h
0000_2FFFh
0000_1000h
0000_0FFFh
0000_0000h
31
19
MMADR Register (Base Address)
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4.7
System Management Mode (SMM)
System Management Mode uses main memory for System Management RAM (SM
RAM). The (G)MCH supports: Compatible SMRAM (C_SMRAM), High Segment (HSEG),
and Top of Memory Segment (TSEG). System Management RAM space provides a
memory area that is available for the SMI handlers and code and data storage. This
memory resource is normally hidden from the system OS so that the processor has
immediate access to this memory space upon entry to SMM. (G)MCH provides three
SMRAM options:
• Below 1-MB option that supports compatible SMI handlers.
• Above 1-MB option that allows new SMI handlers to execute with write-back
cacheable SMRAM.
• Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD
stolen memory.
The above 1 MB solutions require changes to compatible SMRAM handlers code to
properly execute above 1 MB.
Note:
DMI and PCI Express masters are not allowed to access the SMM space.
4.7.1
SMM Space Definition
SMM space is defined by its addressed SMM space and its DRAM SMM space. The
addressed SMM space is defined as the range of bus addresses used by the processor
to access SMM space. DRAM SMM space is defined as the range of physical DRAM
memory locations containing the SMM code. SMM space can be accessed at one of
three transaction address ranges: Compatible, High and TSEG. The Compatible and
TSEG SMM space is not remapped and therefore the addressed and DRAM SMM space
is the same address range. Since the High SMM space is remapped the addressed and
DRAM SMM space are different address ranges. Note that the High DRAM space is the
same as the Compatible Transaction Address space. Table 6 describes three unique
address ranges:
• Compatible Transaction Address (Adr C)
• High Transaction Address (Adr H)
• TSEG Transaction Address (Adr T)
These abbreviations are used later in the table describing SMM Space Transaction
Handling.
Table 6.
SMM Space Definition Summary
SMM Space
Enabled
Transaction Address Space
DRAM Space (DRAM)
Compatible (C)
000A_0000h to 000B_FFFFh
000A_0000h to 000B_FFFFh
High (H)
FEDA_0000h to FEDB_FFFFh
000A_0000h to 000B_FFFFh
TSEG (T)
(TOLUD minus STOLEN minus
TSEG) to (TOLUD minus STOLEN)
(TOLUD minus STOLEN minus
TSEG) to (TOLUD minus STOLEN)
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System Address Map
4.8
SMM Space Restrictions
If any of the following conditions are violated, the results of SMM accesses are
unpredictable and may cause the system to hang:
• The Compatible SMM space must not be set-up as cacheable.
• High or TSEG SMM transaction address space must not overlap address space
assigned to system DRAM, or to any “PCI” devices (including DMI, PCI Express, and
graphics devices). This is a BIOS responsibility.
• Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
• When TSEG SMM space is enabled, the TSEG space must not be reported to the
OS as available DRAM. This is a BIOS responsibility.
• Any address translated through the GMADR must not target DRAM from A_0000F_FFFF.
4.8.1
SMM Space Combinations
When High SMM is enabled (G_SMRAME=1 and H_SMRAM_EN=1) the Compatible SMM
space is effectively disabled. Processor originated accesses to the Compatible SMM
space are forwarded to PCI Express if VGAEN=1 (also depends on MDAP), otherwise
they are forwarded to the DMI. PCI Express and DMI originated accesses are never
allowed to access SMM space.
Table 7.
4.8.2
SMM Space Table
Global Enable
G_SMRAME
High Enable
H_SMRAM_EN
TSEG Enable
TSEG_EN
Compatible
(C) Range
High (H)
Range
TSEG (T)
Range
0
X
X
Disable
Disable
Disable
1
0
0
Enable
Disable
Disable
1
0
1
Enable
Disable
Enable
1
1
0
Disabled
Enable
Disable
1
1
1
Disabled
Enable
Enable
SMM Control Combinations
The G_SMRAME bit provides a global enable for all SMM memory. The D_OPEN bit
allows software to write to the SMM ranges without being in SMM mode. BIOS software
can use this bit to initialize SMM code at power up. The D_LCK bit limits the SMM range
access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be
forwarded to the DMI or PCI Express. The SMM software can use this bit to write to
video memory while running SMM code out of DRAM.
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Table 8.
4.8.3
SMM Control Table
G_SMRAME
D_LCK
D_CLS
D_OPEN
Processor
in SMM
Mode
SMM Code
Access
SMM Data
Access
0
X
X
X
X
Disable
Disable
1
0
X
0
0
Disable
Disable
1
0
0
0
1
Enable
Enable
1
0
0
1
X
Enable
Enable
1
0
1
0
1
Enable
Disable
1
0
1
1
X
Invalid
Invalid
1
1
X
X
0
Disable
Disable
1
1
0
X
1
Enable
Enable
1
1
1
X
1
Enable
Disable
SMM Space Decode and Transaction Handling
Only the processor is allowed to access SMM space. PCI Express and DMI originated
transactions are not allowed to SMM space.
4.8.4
Processor WB Transaction to an Enabled SMM Address
Space
Processor Writeback transactions (REQ[1]# = 0) to enabled SMM address space must
be written to the associated SMM DRAM even though D_OPEN=0 and the transaction is
not performed in SMM mode. This ensures SMM space cache coherency when cacheable
extended SMM space is used.
4.9
Memory Shadowing
Any block of memory that can be designated as read-only or write-only can be
“shadowed” into (G)MCH DRAM memory. Typically this is done to allow ROM code to
execute more rapidly out of main DRAM. ROM is used as read-only during the copy
process while DRAM at the same time is designated write-only. After copying, the
DRAM is designated read-only so that ROM is shadowed. Processor bus transactions are
routed accordingly.
4.10
I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on
the processor bus. The (G)MCH generates either DMI or PCI Express bus cycles for all
processor I/O accesses that it does not claim. Within the host bridge the (G)MCH
contains two internal registers in the processor I/O space, Configuration Address
Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA).
These locations are used to implement a configuration space access mechanism.
The processor allows 64 kB plus 3 B to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination bus
and therefore provides addressability for 64 kB plus 3 B locations. Note that the upper
three locations can be accessed only during I/O address wrap-around when processor
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System Address Map
bus H_A#16 address signal is asserted. H_A#16 is asserted on the processor bus
whenever an I/O access is made to 4 bytes from address 0000_FFFDh, 0000_FFFEh, or
0000_FFFFh. H_A#16 is also asserted when an I/O access is made to 2 bytes from
address 0000_FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are
consumed by the internal graphics device if it is enabled. The mechanisms for internal
graphics I/O decode and the associated control is explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded
normally to the DMI bus unless they fall within the PCI Express I/O address range as
defined by the mechanisms explained below. I/O writes are NOT posted. Memory
writes to ICH or PCI Express are posted. The PCICMD1 register can disable the routing
of I/O cycles to PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status.
Upstream I/O cycles and configuration cycles should never occur. If one does occur, the
request will route as a read to memory address 0h so a completion is naturally
generated (whether the original request was a read or write). The transaction will
complete with a UR completion status.
For Intel Core™2 Duo Mobile Processor for Santa Rosa, I/O reads that lie within 8-byte
boundaries but cross 4-byte boundaries are issued from the processor as 1 transaction.
The (G)MCH will break this into two separate transactions. This was not done on
chipsets prior to the Intel® 915 Express chipset family. I/O writes that lie within 8-byte
boundaries but cross 4-byte boundaries are assumed to be split into two transactions
by the processor.
4.10.1
PCI Express I/O Address Mapping
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI
Express bus interface when processor initiated I/O cycle addresses are within the PCI
Express I/O address range. This range is controlled via the I/O Base Address (IOBASE)
and I/O Limit Address (IOLIMIT) registers in (G)MCH Device #1 configuration space.
The (G)MCH positively decodes I/O accesses to PCI Express I/O address space as
defined by the following equation:
I/O_Base_Address ≤ Processor I/O Cycle Address ≤ I/O_Limit_Address
The effective size of the range is programmed by the plug-and-play configuration
software and it depends on the size of I/O space claimed by the PCI Express device.
The (G)MCH also forwards accesses to the Legacy VGA I/O ranges according to the
settings in the Device #1 configuration registers BCTRL (VGA Enable) and PCICMD1
(IOAE1), unless a second adapter (monochrome) is present on the DMI Interface/PCI.
The presence of a second graphics adapter is determined by the MDAP configuration
bit. When MDAP is set, the (G)MCH will decode legacy monochrome IO ranges and
forward them to the DMI Interface. The IO ranges decoded for the monochrome
adapter are 3B4h, 3B5h, 3B8h, 3B9h, 3Bah and 3BFh.
Note that the (G)MCH Device #1 I/O address range registers defined above are used
for all I/O space allocation for any devices requiring such a window on PCI Express.
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System Address Map
4.11
(G)MCH Decode Rules and Cross-Bridge Address
Mapping
VGAA = 000A_0000 to 000A_FFFF
MDA = 000B_0000 to 000B_7FFF
VGAB = 000B_8000 to 000B_FFFF
MAINMEM = 0100_0000 to TOLUD
4.11.1
Legacy VGA and I/O Range Decode Rules
The legacy 128-kB VGA memory range 000A_0000h to 000B_FFFFh can be mapped to
IGD (Device #2), to PCI Express (Device #1), and/or to the DMI depending on the
programming of the VGA steering bits. Priority for VGA mapping is constant in that the
(G)MCH always decodes internally mapped devices first. Internal to the (G)MCH,
decode precedence is always given to IGD. The (G)MCH always positively decodes
internally mapped devices, namely the IGD and PCI Express. Subsequent decoding of
regions mapped to PCI Express or the DMI depends on the Legacy VGA configurations
bits (VGA Enable and MDAP).
§
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System Address Map
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External Design Specification
System Memory Controller
5
System Memory Controller
5.1
Functional Overview
The chipset system memory controller supports DDR2 SDRAMs.
Two memory channel organizations are supported:
• Dual channel Interleaved (Single SO-DIMM per channel)
• Dual channel Asymmetric (Single SO-DIMM per channel)
Each channel has a 64-bit data interface and the frequencies supported are 533 MHz
and 667 MHz.
Note:
The chipset supports only one SO-DIMM connector per channel.
Each channel can have one or two ranks populated. There can be a maximum of 4
ranks (2 double sided SO-DIMMs) populated.
Table 9.
System Memory Organization Support for DDR2
DDR2
Tech
5.2
SDRAM
Org
SO-DIMM
size
SO-DIMM
Org
Banks
Ranks
Page
Size
(dev/
module)
Max
Capacity
(2 SODIMMs)
Freq
256 Mb
x8
256 MB
32Mx64
4
1
1K/8K
512 MB
533/667
256 Mb
x16
128 MB
16Mx64
4
1
1K/4K
256 MB
533/667
256 Mb
x16
256 MB
32Mx64
4
2
1K/4K
512 MB
533/667
512 Mb
x8
512 MB
64Mx64
4
1
1K/8K
1 GB
533/667
512 Mb
x8
1 GB
128Mx64
4
2
1K/8K
2 GB
533/667
512 Mb
x16
256 MB
32Mx64
4
1
1K/8K
512 MB
533/667
512 Mb
x16
512 MB
64Mx64
4
2
2K/8K
1 GB
533/667
1 Gb
x8
1 GB
128Mx64
8
1
2K/8K
2 GB
533/667
1 Gb
x8
2 GB
256Mx64
8
2
1K/8K
4 GB
533/667
Memory Channel Access Modes
The system memory controller supports two styles of memory access (dual channel
Interleaved and dual channel Asymmetric). Rules for populating SO-DIMM slots are
included in this chapter.
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System Memory Controller
5.2.1
Dual Channel Interleaved Mode
This mode provides maximum performance on real applications. Addresses alternate
between the channels after each cache line (64-byte boundary). The channel selection
address bit is controlled by DCC[10:9]. If a second request sits behind the first, and
that request is to an address on the second channel, that request can be sent before
data from the first request has returned. Due to this feature, some progress is made
even during page conflict scenarios. If two consecutive cache lines are requested, both
may be retrieved simultaneously, since they are guaranteed to be on opposite
channels. The drawback of conventional Interleaved mode is that the system designer
must populate both channels of memory so that they have equal capacity, however the
technology and device width may vary from one channel to the other.
5.2.1.1
Intel® Flex Memory Technology (Dual Channel Interleaved Mode with
Unequal Memory Population)
The (G)MCH supports interleaved addressing in dual-channel memory configurations
even when the two channels have unequal amounts of memory populated. This is
called Intel® Flex Memory Technology.
Flex memory provides higher performance with different sized channel populations
than “Asymmetric” mode (where no interleaving is used) by allowing some
interleaving.
The memory addresses up to the twice the size of the smaller SO-DIMM are interleaved
on a 64-B boundary using address bit 6 (including any XOR-ing already used in
interleaved mode). Above this, the rest of the address space is assigned to the
remaining memory in the larger channel. Figure 7 shows various configurations of
memory populations.
Figure 7.
Intel Flex Memory Technology Operation
NOTES:
1.
B: Smaller of the two physical memory amounts: (Accessed in Dual-Channel Interleaved
mode)
2.
C: Extra memory populated over B: (Accessed in non-interleaved mode)
Note:
1. To enable Intel Flex Memory Technology, BIOS should program both channels’ DRBs
(DRAM Rank Boundaries) to the size of memory in that channel, as if for fully
interleaved memory (Should not add the top of one channel to the other as in
Asymmetric mode). Interleaved mode operation should also be enabled.
2. To disable Intel Flex Memory Technology, BIOS should program as usual for the
Asymmetric mode.
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System Memory Controller
5.2.2
Dual Channel Non-Interleaved Mode
This mode trades performance for system design flexibility, by allowing unequal
amounts of memory to be populated in the two channels. Unlike the previous mode,
addresses start in channel A and stay there until the end of the highest rank in channel
A, then addresses continue from the bottom of channel B to the top. Real world
applications are unlikely to make requests that alternate between addresses that sit on
opposite channels with this memory organization, so in most cases, bandwidth will be
limited The system designer is free to populate or not to populate any rank on either
channel, including either degenerate single channel case. Because channel A is
addressed first, when using only one channel, channel A should be the channel used.
Figure 8.
System Memory Styles
Dual Channel Interleaved
(Symmetric Population)
Dual Channel Non-interleaved
(Asymmetric Population)
CL
CH1
CL
Top of
Memory
CH1
Top of
Memory
CH0
CH0-top
DRB
CH0
CH1
CH0
CH1
CH0
0
0
Channel selector
controlled by DCC[10:9]
5.3
DRAM Technologies and Organization
All standard 256-Mb, 512-Mb, 1-Gb, and 2-Gb technologies and addressing are
supported for x16 and x8 devices.
The (G)MCH supports various page sizes. Page size is individually selected for every
rank; 4 k and 8 k for Interleaved and Asymmetric dual channel modes.
The DRAM sub-system supports only dual channel with 64-bit width per channel.
The number of ranks each channel can have populated is one or two.
Mixed mode Double-Sided SO-DIMMs (x8 and x16 on the same SO-DIMM) are not
supported.
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System Memory Controller
5.3.1
Rules for Populating SO-DIMM Slots
In all modes, the frequency of system memory will be the lowest frequency of all SODIMMs in the system, as determined through the SPD registers on the SO-DIMMs. The
Mobile Intel 965 Express Chipset family supports only one SO-DIMM connector per
channel.
• In dual channel Interleaved mode, both SO-DIMM slots must be populated, and the
total amount of memory in each channel must be the same. The device
technologies may differ.
• In dual channel Asymmetric mode, the total memory in the two channels need not
be equal (one slot could even be unpopulated). When populating only one
channel, channel A should be populated.
5.3.2
Pin Connectivity for Dual Channel Modes
Table 10.
DDR2 Dual Channel Pin Connectivity
Dual Channel
JEDEC Pin
Mapping
5.4
Channel A
Channel B
CK[1:0]
SM_CK[1:0]
SM_CK[4:3]
CKB[1:0]
SM_CK#[1:0]
SM_CK#[4:3]
CSB[1:0]
SM_CS#[1:0]
SM_CS#[3:2]
CKE[1:0]
SM_CKE[1:0]
SM_CKE[4:3]
ODT[1:0]
SM_ODT[1:0]
SM_ODT[3:2]
BS[2:0]
SA_BS[2:0]
SB_BS[2:0]
MA[14:0]
SA_MA[14:0]
SB_MA[14:0]
RAS#
SA_RAS#
SB_RAS#
CAS#
SA_CAS#
SB_CAS#
WE#
SA_WE#
SB_WE#
DQ[63:0]
SA_DQ[63:0]
SB_DQ[63:0]
DQS[7:0]
SA_DQS[7:0]
SB_DQS[7:0]
DQS[7:0]#
SA_DQS#[7:0]
SB_DQS#[7:0]
DM[7:0]
SA_DM[7:0]
SB_DM[7:0]
DRAM Clock Generation
The chipset generates two differential clock pairs for every supported SO-DIMM. There
are total of four clock pairs driven directly by the (G)MCH to two SO-DIMMs.
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System Memory Controller
5.5
DDR2 On Die Termination
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal
termination resistance for each DQ, DQS/DQS# and DM signal for x8 configurations via
the ODT control pin. The ODT feature is designed to improve signal integrity of the
memory channel by allowing the DRAM controller to independently turn on/off
termination resistance for any or all DRAM devices.
The ODT feature is designed to improve signal integrity of the memory channel by
allowing the termination resistance for the DQ, DM, DQS, and DQS# signals to be
located inside the DRAM devices themselves instead of on the motherboard. The
(G)MCH drives out the required ODT signals, based on memory configuration and which
rank is being written to or read from, to the DRAM devices on a targeted SO-DIMM rank
to enable or disable their termination resistance.
ODT operation follows these general rules:
WRITE
• Chipset: ODT off
• DRAM:
— If one slot populated but has two ranks, turn on termination in the written
rank.
— If one slot/one rank, turn on that rank’s termination.
READ
• Chipset: ODT on
• DRAM: ODT off
5.6
DRAM Power Management
The chipset implements extensive support for power management on the SDRAM
interface.
5.6.1
Self Refresh Entry and Exit operation
When entering the Suspend-To-RAM (STR) state, (G)MCH will flush pending cycles and
then enter all SDRAM ranks into self refresh. In STR, the CKE signals remain LOW so
the SDRAM devices will perform self-refresh.
5.6.2
Dynamic Power Down Operation
The chipset implements aggressive CKE control to dynamically put the DRAM devices in
a power down state. The (G)MCH controller can be configured to put the devices in
active power down (CKE de-assertion with open pages) or precharge power down (CKE
de-assertion with all pages closed). Precharge power down provides greater power
savings but has a bigger performance impact, since all pages are needed to be closed
before putting the devices in power down mode.
If dynamic power down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
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System Memory Controller
5.6.3
DRAM I/O Power Management
(G)MCH implements several power saving features where different groups of IO buffers
are disabled when safe to do so in a dynamic fashion thereby saving IO power. These
features are listed below.
• SO-DIMM clock gating disable – The chipset has 2 clock pairs per SO-DIMM. If only
one SO-DIMM is populated, it allows the other 2 clock pairs to be disabled.
• Unused CKE pins can be tri-stated.
• Address and control tri-state enable – If CKE for any given rank is deasserted, the
CS# to that rank is disabled. If all CKEs are deasserted (such as in S3), All address
and control buffers (excluding CKEs) are disabled.
• Self refresh master/slave DLL disable - When all the SDRAMs ranks have been put
in a self refresh state, all DLLs are disabled.
• Data sense amp disable (self refresh, dynamic) - When all the SDRAM ranks have
been put in a self refresh state, or during normal operation, if no memory accesses
are pending, the sense amplifiers for all data buffers are turned off.
• Output only sense amp disable – Sense amplifiers of all IO buffers which are
functionally outputs only (everything except DQ and DQS) are turned off.
• RCVEN DLL disable - The (G)MCH has DLLs for timing the RCVEN signal. If only one
SO-DIMM is populated, the unused DLLs are turned off.
5.7
System Memory Throttling
The chipset has two independent mechanisms, (G)MCH thermal management and
DRAM thermal management, that causes system memory bandwidth throttling. For
more information on system memory throttling, see Section 11.3.
§
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External Design Specification
PCI Express Based External Graphics
6
PCI Express Based External
Graphics
See the PCI Express Specification for specification details of PCI Express.
This (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in Device #1 configuration space and two root complex
register blocks (RCRBs).
6.1
PCI Express Architecture
The PCI Express architecture is specified in layers. Compatibility with the PCI
addressing model (a load - store architecture with a flat address space) is maintained
to ensure that all existing applications and drivers operate unchanged. The PCI Express
configuration uses standard mechanisms as defined in the PCI plug-and-play
specification. The initial speed of 2.5-GHz (250 MHz internally) results in 2.5 GB/s
direction which provides a 250-MB/s communications channel in each direction
(500 MB/s total) that is close to twice the data rate of classic PCI per lane.
6.1.1
Layering Overview
The representation of layers in the PCI Express architecture (transaction layer, Data
Link Layer, and physical layer) is to simplify the understanding of the high-level
functionality.
PCI Express uses packets to communicate information between components. Packets
are formed in the Transaction and data link layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side the reverse process occurs and
packets get transformed from their physical layer representation to the data link layer
representation and finally (for transaction layer packets) to the form that can be
processed by the transaction layer of the receiving device.
6.1.2
Transaction Layer
The upper layer of the PCI Express architecture is the transaction layer. The transaction
layer’s primary responsibility is the assembly and disassembly of transaction layer
Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as
well as certain types of events. The transaction layer also manages flow control of TLPs.
6.1.3
Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an
intermediate stage between the transaction layer and the physical layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
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PCI Express Based External Graphics
6.1.4
Physical Layer
The physical layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance
matching circuitry.
6.2
PCI Express Configuration Mechanism
The PCI Express (external graphics) link is mapped through a PCI-PCI bridge structure.
Figure 9.
PCI Express Related Register Structures in (G)MCH
GMCH
PCI Express
Graphics
Device
PCI Express Link
x16 down to x1
PCI-PCI
Bridge
representing
root PCI
Express Port
(Device 1)
PCI
Compatible
Host Bridge
Device
(Device 0)
RCRB for
Egress Port
(access to
Main Memory)
RCRB for DMI
(ICH attach)
ICH
PCI Express extends the configuration space to 4096 bytes per device/function as
compared to 256 bytes allowed by PCI Specification. PCI Express configuration space is
divided into a PCI compatible region, which consists of the first 256 bytes of a logical
device’s configuration space and an extended PCI Express region which consists of the
remaining configuration space. The PCI compatible region can be accessed using either
the mechanisms defined in the PCI specification or using the enhanced PCI Express
configuration access mechanism described in the PCI Express Enhanced Configuration
Mechanism section.
The PCI Express host bridge is required to translate the memory-mapped PCI Express
configuration space accesses from the host processor to PCI Express configuration
cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is
recommended that system software access the enhanced configuration space using 32bit operations (32-bit aligned) only.
See the PCI Express specification for details of both the PCI compatible and PCI
Express enhanced configuration mechanisms and transaction rules.
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PCI Express Based External Graphics
6.3
Serial Digital Video Output (SDVO)
The SDVO description is located here because it is muxed onto the PCI Express x16
port pins. The AC/DC specifications are identical to the PCI Express Graphics interface.
SDVO electrical interface is based on the PCI Express interface, though the protocol
and timings are completely unique. Whereas PCI Express runs at a fixed frequency, the
frequency of the SDVO interface is dependant upon the active display resolution and
timing. The port can be dynamically configured in several modes to support display
configurations.
Essentially, an SDVO port will transmit display data in a high-speed, serial format
across differential AC coupled signals. An SDVO port consists of a sideband differential
clock pair and a number of differential data pairs.
6.3.1
SDVO Capabilities
SDVO ports can support a variety of display types including LVDS, DVI, HDMI, cTV-Out,
and external CE type devices. The Mobile Intel GM965/GL960 Chipset utilizes an
external SDVO device to translate from SDVO protocol and timings to the desired
display format and timings. The internal graphics controller can have one or two SDVO
ports multiplexed on the x16 PCI Express interface.
The SDVO port defines a two-wire point-to-point communication path between the
SDVO device and (G)MCH. The SDVO Control Clock (SDVO_CTRL_CLK) and Data
(SDVO_CTRL_DATA) provide similar functionality to I2C. However unlike I2C, this
interface is intended to be point-to-point (from the (G)MCH to the SDVO device) and
will require the SDVO device to act as a switch and direct traffic from the SDVO Control
bus to the appropriate receiver. Additionally, the SDVO Control bus will be able to run at
faster speeds (up to 1 MHz) than a traditional I2C interface would.
Figure 10.
SDVO Conceptual Block Diagram
Monitor
Analog RGB
TV Clock In
Stall
Interrupt
GMCH
External Design Specification
SDVO Port C
PCI
Express
Logic
Control Data
SDVO Port B
PCI Express x16 Port Pins
Control Clock
Internal
Graphics
Intel Confidential
ClockC
RedC
GreenC
BlueC
rd
3 Party
SDVO
External
Device(s)
Digital
Display
Device(s)
or TV
ClockB
RedB
GreenB
BlueB
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PCI Express Based External Graphics
6.3.2
Concurrent SDVO/PCI Express* Operation
The GM965 chipset supports concurrent operation of the SDVO port with video capture
via x1 PCI Express interface. Note that the only type of data supported over the x1 PCI
Express link is video capture.
SDVO slot reversal is also supported on the GM965 chipset. The (G)MCH will allow
SDVO and x1 PCI Express to operate concurrently on the PCI Express-based Graphics
link.
The PCI Express lanes comprise a standard PCI Express link and must always originate
with lane 0 on the PCI Express connector. The only supported PCI Express width when
SDVO is present is x1.
This concurrency is supported in reversed and non-reversed configurations. Mirroring /
Reversing are always about the axis between lanes 7 and 8. When SDVO is reversed,
SDVO lane 0 corresponds to what would be PCI Express pin/connector lane 15 (mirrored to higher lane numbers).
Hardware reset straps are used to determine which of the 6 configurations below is
desired.
Table 12.
Concurrent SDVO / PCI Express* Configuration Strap Controls
Configuration
Number
Description
Slot Reversed
Strap (CFG9)
SDVO Present Strap
(SDVO_CTRLDATA)
SDVO/PCI
Express
Concurrent Strap
(CFG20)
1
PCI Express*-only not
reversed
High
Low
Low
2
PCI Express-only Reversed
Low
Low
Low
3
SDVO-only not reversed
High
High
Low
4
SDVO-only Reversed
Low
High
Low
5
SDVO and PCI Express not
reversed
High
High
High
6
SDVO and PCI Express
Reversed
Low
High
High
NOTE: Details of the implementations corresponding to the configuration number are shown below.
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PCI Express Based External Graphics
Figure 11.
SDVO/PCI Express Non-Reversed Configurations
( G ) M C H P C Ie
L a ne N u m be ring
0
1
0
3
0
5
0
0
0
P C Ie La n e 0
x8
sD V O
s D VO La n e 7
PCI Express x16 Connector
PCI Express x16 Connector
x 16
P C Ie
C ard
x4
sDVO
PCI Express x16 Connector
Not Reversed
P C Ie
V id e o In
V id e o O u t
sD V O
15
Figure 12.
15
15
s D VO La n e 0
15
15
SDVO/PCI Express* Reversed Configurations
(G)MCH PCIe
Lane Numbering
15
2
4
6
15
0
15
sDVO Lane 0
15
x4
sDVO
sDVO Lane 7
PCI Expres s x16 Connector
x8
sDVO
PCI Expres s x16 Connector
Reversed
x16
PCIe
Card
PCI Expres s x16 Connector
sDVO
Video Out
Video In
PCIe
0
6.3.2.1
15
0
0
PCIe Lane 0
0
0
SDVO Signal Mapping
The table below shows the mapping of SDVO signals to the PCI Express lanes in the
various possible configurations as determined by the strapping configuration. Note that
slot-reversed configurations do not apply to the Integrated-graphics only variants.
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PCI Express Based External Graphics
Table 13.
Configuration-wise Mapping of SDVO Signals on the PCI Express Interface
Configuration-wise Mapping
SDVO Signal
SDVOB_RED#
SDVO Only – Normal
(3)
SDVO Only –
Reversed (4)
Concurrent
SDVO and PCI
Express –
Normal (5)
Concurrent SDVO
and PCI Express
– Reversed (6)
EXP_TXN0
EXP_TXN15
EXP_TXN15
EXP_TXN0
SDVOB_RED
EXP_TXP0
EXP_TXP15
EXP_TXP15
EXP_TXP0
SDVOB_GREEN#
EXP_TXN1
EXP_TXN14
EXP_TXN14
EXP_TXN1
SDVOB_GREEN
EXP_TXP1
EXP_TXP14
EXP_TXP14
EXP_TXP1
SDVOB_BLUE#
EXP_TXN2
EXP_TXN13
EXP_TXN13
EXP_TXN2
SDVOB_BLUE
EXP_TXP2
EXP_TXP13
EXP_TXP13
EXP_TXP2
SDVOB_CLKN
EXP_TXN3
EXP_TXN12
EXP_TXN12
EXP_TXN3
SDVOB_CLKP
EXP_TXP3
EXP_TXP12
EXP_TXP12
EXP_TXP3
SDVOC_RED#
EXP_TXN4
EXP_TXN11
EXP_TXN11
EXP_TXN4
SDVOC_RED
EXP_TXP4
EXP_TXP11
EXP_TXP11
EXP_TXP4
SDVOC_GREEN#
EXP_TXN5
EXP_TXN10
EXP_TXN10
EXP_TXN5
SDVOC_GREEN
EXP_TXP5
EXP_TXP10
EXP_TXP10
EXP_TXP5
SDVOC_BLUE#
EXP_TXN6
EXP_TXN9
EXP_TXN9
EXP_TXN6
SDVOC_BLUE
EXP_TXP6
EXP_TXP9
EXP_TXP9
EXP_TXP6
SDVOC_CLKN
EXP_TXN7
EXP_TXN8
EXP_TXN8
EXP_TXN7
SDVOC_CLKP
EXP_TXP7
EXP_TXP8
EXP_TXP8
EXP_TXP7
SDVO_TVCLKIN#
EXP_RXN0
EXP_RXN15
EXP_RXN15
EXP_RXN0
SDVO_TVCLKIN
EXP_RXP0
EXP_RXP15
EXP_RXP15
EXP_RXP0
SDVOB_INT#
EXP_RXN1
EXP_RXN14
EXP_RXN14
EXP_RXN1
SDVOB_INT
EXP_RXP1
EXP_RXP14
EXP_RXP14
EXP_RXP1
SDVO_FLDSTALL#
EXP_RXN2
EXP_RXN13
EXP_RXN13
EXP_RXN2
SDVO_FLDSTALL
EXP_RXP2
EXP_RXP13
EXP_RXP13
EXP_RXP2
SDVOC_INT#
EXP_RXN5
EXP_RXN10
EXP_RXN10
EXP_RXN5
SDVOC_INT
EXP_RXP5
EXP_RXP10
EXP_RXP10
EXP_RXP5
6.4
SDVO Modes
The port can be dynamically configured in several modes:
• Standard – Baseline SDVO functionality. Supports Pixel Rates between 25 and 200
MP/s. Utilizes three data pairs to transfer RGB data.
• Dual Standard – Utilizes Standard data streams across both SDVO B and SDVO C.
Both channels can only run in Standard mode (3 data pairs) and each channel
supports Pixel Rates between 25 and 200 MP/s. There are two types of dual
standard modes:
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— Dual Independent Standard - In Dual Independent Standard mode, each SDVO
channel will see a different pixel stream. The data stream across SDVO B will
not be the same as the data stream across SDVO C.
— Dual Simultaneous Standard - In Dual Simultaneous Standard mode, both
SDVO channels will see the same pixel stream. The data stream across SDVO B
will be the same as the data stream across SDVO C. The display timings will be
identical, but the transfer timings may not be - that is, SDVO B Clocks and Data
may not be perfectly aligned with SDVO C Clock and Data as seen at the SDVO
device(s). Since this utilizes just a single data stream, it utilizes a single pixel
pipeline within the (G)MCH.
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7
Integrated Graphics Controller
The (G)MCH graphics is powered by the Mobile Intel GMA X3100, bringing new levels of
richness and realism to DirectX* 9 enabled applications. It supports eight fully
programmable Execution cores, enabling greater performance than previous generation
chipsets.
The Mobile Intel GMA X3100 support full precision floating point operations to enhance
the visual experience of compute-intensive applications.
The Mobile Intel GMA X3100 contain several types of components. The major
components in the Mobile Intel GMA X3100 are the engines, planes, pipes and ports.
The Mobile Intel GMA X3100 has a 3D/2D Instruction Processing unit to control the 3D
and 2D engines. The Mobile Intel GMA X3100’s 3D and 2D engines are fed with data
through the memory controller. The outputs of the engines are surfaces sent to
memory, which are then retrieved and processed by the Mobile Intel GMA X3100
planes.
Figure 13.
(G)MCH Graphics Controller Block Diagram
Plane A
Video Engine
Overlay
2D Engine
BUFFERS
Cursor A
VGA
3D Engine
Plane B
Setup/Transform
Rasterizer
Texture Engine
Pixel Shader
Plane C/
Sprite
CRT
Alpha
Blend/
Gamma
/Panel
Fitter
Pipe A
M
U
X
Pipe B
LVDS
TVOUT
SDVO
B/C
Cursor B
The Mobile Intel GMA X3100 contains a variety of planes, such as display, overlay,
cursor and VGA. A plane consists of rectangular shaped image that has characteristics
such as source, size, position, method, and format. These planes get attached to
source surfaces, which are rectangular memory surfaces with a similar set of
characteristics. They are also associated with a particular destination pipe.
A pipe consists of a set of combined planes and a timing generator. The Mobile Intel
GMA X3100 has two independent display pipes, allowing for support of two
independent display streams. A port is the destination for the result of the pipe.
The entire Mobile Intel GMA X3100 is fed with data from its memory controller. The
Mobile Intel GMA X3100 performance is directly related to the amount of bandwidth
available. If the engines are not receiving data fast enough from the memory controller
(e.g., single-channel DDR2 533), the rest of the Mobile Intel GMA X3100 will also be
affected.
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7.1
Graphics Processing
7.1.1
3D Graphics Pipeline
Mobile Intel GMA X3100 is the next step in the evolution of integrated graphics.
Additional processing capability has been added to the Geometry stage with a vertex
shader, geometry shader, and clipper.
The 3D graphics pipeline for the Mobile Intel GMA X3100 has a deep pipelined
architecture in which each stage can simultaneously operate on different primitives or
on different portions of the same primitive.
The Mobile Intel GMA X3100 is optimized by using current and future Intel processor
family for advance software based transform and lighting (geometry processing) as
defined by Microsoft DirectX* API. Within the Mobile Intel GMA X3100, the rasterization
engine converts vertices to pixels and the texture engine applies textures to pixels. The
rasterization engine takes textured pixels and applies lighting and other environmental
affects to produce the final pixel value. From the rasterization stage the final pixel value
is written to the frame buffer in memory so that it can be displayed.
7.1.2
3D Engine
The 3D engine of the Mobile Intel GMA X3100 has been designed with a deep pipelined
architecture, where performance is maximized by allowing each stage of the pipeline to
simultaneously operate on different primitives or portions of the same primitive.
Mobile Intel GMA X3100 supports 32-bit full precision floating point operations, as
against 24-bit in previous chipsets, thus enabling richer and more realistic images.
They also support up to 8 Multiple Render Targets (MRTs), further optimizing
performance in execution of instructions.
The Mobile Intel GMA X3100 supports acceleration for all Microsoft DirectX* 9 and SGI
OpenGL* 1.5 required features as well as other additional features. Some of the key
features supported are:
The 3D pipeline subsystem performs the 3D rendering acceleration. The main blocks of
the pipeline are the Setup Engine, Rasterizer, Texture Pipeline, and Raster Pipeline. A
typical programming sequence would be to send instructions to set the state of the
pipeline followed by rending instructions containing 3D primitive vertex data.
The engines’ performance is dependent on the memory bandwidth available. Systems
that have more bandwidth available will outperform systems with less bandwidth. The
engines’ performance is also dependent on the core clock frequency. The higher the
frequency, the more data is processed.
7.1.2.1
Setup Engine
The setup stage of the pipeline takes the input data associated with each vertex of 3D
primitive and computes the various parameters required for scan conversion. In
formatting this data, the Mobile Intel GMA X3100 maintains sub-pixel accuracy.
7.1.2.1.1
3D Primitives and Data Formats Support
The 3D primitives rendered by the Mobile Intel GMA X3100 are points, lines, discrete
triangles, line strips, triangle strips, triangle fans and polygons. In addition to this, The
Mobile Intel GMA X3100 Mobile Intel GMA X3100 Mobile Intel GMA X3100 supports the
Microsoft DirectX* Flexible Vertex Format (FVF), which enables the application to
specify a variable length of parameter list obviating the need for sending unused
information to the hardware. Strips, Fans and Indexed Vertices as well as FVF, improve
the vertex rate delivered to the setup engine significantly.
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7.1.2.1.2
Pixel Accurate “Fast” Scissoring and Clipping Operation
The Mobile Intel GMA X3100 supports 2D clipping to the scissor rectangle, avoiding
processing pixels that fall outside the rectangle. The Mobile Intel GMA X3100’s clipping
and scissoring in hardware reduce the need for software to clip objects, and thus
improve performance. During the setup stage, The Mobile Intel GMA X3100 clips
objects to the scissor window.
7.1.2.1.3
Depth Bias
The Mobile Intel GMA X3100 supports source Depth Biasing in the Setup Engine. Depth
Bias value is specified in the vertex command packet on a per primitive basis. The
value ranges from -1 to 1. The Depth Bias value is added to the z value of the vertices.
By using Depth Bias, it is possible to offset the destination z value (compare value)
before comparing with the new z value.
7.1.2.1.4
Backface Culling
As part of the setup, the Mobile Intel GMA X3100 discards polygons from further
processing, if they are facing away from or towards the user’s viewpoint, thus
optimizing all further steps.
7.1.2.1.5
Color Shading Modes
The Raster engine supports the Flat and Gouraud shading modes. These shading
modes are programmed by the appropriate state variables issued through the
command stream.
Flat shading is performed by smoothly interpolating the vertex intrinsic color
components (Red, Green, Blue), Specular Highlights (R,G,B), Fog, and Alpha to the
pixel, where each vertex color has the same value. The setup engine substitutes one of
the vertex’s attribute values for the other two vertices attribute values thereby creating
the correct flat shading terms. This condition is set up by the appropriate state
variables issued prior to rendering the primitive.
Gouraud shading is performed by smoothly interpolating the vertex intrinsic color
components (Red, Green, Blue). Specular Highlights (R,G,B), Fog, and Alpha to the
pixel, where each vertex color has a different value.
7.1.2.1.6
Occlusion Query
Occlusion query is a new addition on the Mobile Intel GMA X3100. It optimizes
application performance by minimizing overhead on the depth buffer. It also enables
support for new features and effects such as Lens Flare.
7.1.2.2
Rasterizer
Working on a per-polygon basis, the rasterizer uses the vertex and edge information is
used to identify all pixels affected by features being rendered.
7.1.2.2.1
Pixel Rasterization Rules
The Mobile Intel GMA X3100 supports both SGI OpenGL* and D3D* pixel rasterization
rules to determine whether a pixel is filled by the triangle or line. For both D3D and
OpenGL* modes, a top-left filling convention for filling geometry will be used. Pixel
rasterization rule on rectangle primitive is also supported using the top-left fill
convention.
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7.1.2.2.2
Pixel Pipeline
The pixel pipeline function combines, for each pixel, the interpolated vertex
components from the scan conversion function, texel values from the texture samplers,
and the pixel’s current values from the color and/or depth buffers. This combination is
performed via a programmable pixel shader engine, followed by a pipeline for optional
pixel operations performed in a specific order. The result of these operations can be
written to the color and depth buffers.
7.1.2.3
Texture Engine
The Mobile Intel GMA X3100 allows an image, pattern, or video to be placed on the
surface of a 3D polygon.
The texture processor receives the texture coordinate information from the setup
engine and the texture blend information from the rasterizer. The texture processor
performs texture color or ChromaKey matching, texture filtering (anisotropic, trilinear
and bilinear interpolation), and YUV to RGB conversions. Mobile Intel GMA X3100
enhancements to the Texture engine include dynamic filtering of upto 16 samples in
Anistropic filtering, as compared to a maximum of 4 samples in on previous chipsets.
7.1.2.3.1
Perspective Correct Texture Support
A textured polygon is generated by mapping a 2D texture pattern onto each pixel of the
polygon. A texture map is like wallpaper pasted onto the polygon. Since polygons are
rendered in perspective, it is important that texture be mapped in perspective as well.
Without perspective correction, texture is distorted when an object recedes into the
distance.
7.1.2.3.2
Texture Formats and Storage
The Mobile Intel GMA X3100 supports up to 128 bits of color for textures, including
support for textures with floating point components.
7.1.2.3.3
Texture Decompression
DirectX* supports Texture Compression to reduce the bandwidth required to deliver
textures. As the textures’ average size gets larger with higher color depth and multiple
textures become the norm, it becomes increasingly important to provide a mechanism
for compressing textures. Texture decompression formats supported include DXT1,
DXT2, DXT3, DXT4, DXT5, FXT1, BC4 and BC5.
7.1.2.3.4
Texture ChromaKey
ChromaKey describes a method of removing a specific color or range of colors from a
texture map before it is applied to an object. For “nearest” texture filter modes,
removing a color simply makes those portions of the object transparent (the previous
contents of the back buffer show through). For “linear” texture filtering modes, the
texture filter is modified if only the non-nearest neighbor texels match the key (range).
7.1.2.3.5
Texture Map Filtering
The Mobile Intel GMA X3100 supports many texture mapping modes. Perspective
correct mapping is always performed. As the map is fitted across the polygon, the map
can be tiled, mirrored in either the U or V directions, or mapped up to the end of the
texture and no longer placed on the object (this is known as clamp mode). The way a
texture is combined with other object attributes is also definable.
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The Mobile Intel GMA X3100 supports up to 14 Levels-of-Detail (LODs) ranging in size
from 8192X8192 to 1x1 texels. Textures need not be square. Included in the texture
processor is a texture cache, which provides efficient MIP-mapping.
7.1.2.3.6
Multiple Texture Composition
The Mobile Intel GMA X3100 also performs multiple texture composition. This allows
the combination of two or greater MIP Maps to produce a new one with new LODs and
texture attributes in a single or iterated pass. Flexible vertex format support allows
multitexturing because it makes it possible to pass more than one texture in the vertex
structure.
7.1.2.3.7
Cubic Environment Mapping
Environment maps allow applications to render scenes with complex lighting and
reflections while significantly decreasing CPU load. There are several methods to
generate environment maps such as spherical, circular and cubic. The Mobile Intel GMA
X3100 supports cubic reflection mapping over spherical and circular since it is the best
choice to provide real-time environment mapping for complex lighting and reflections.
Cubic Mapping requires a texture map for each of the 6 cube faces. These can be
generated by pointing a camera with a 90-degree field-of-view in the appropriate
direction. Per-vertex vectors (normal, reflection or refraction) are interpolated across
the polygon and the intersection of these vectors with the cube texture faces is
calculated. Texel values are then read from the intersection point on the appropriate
face and filtered accordingly.
Multiple texture map surfaces arranged into a cubic environment map is supported.
Supports CLAMP and CUBE texture address mode for Cube maps.
A new format is supported for Compressed Cube maps that allow each mip/face to exist
in its own compression block.
7.1.2.4
Pixel Shader
The Mobile Intel GMA X3100 supports a Pixel shader 3.0 (for DirectX* 9 applications)
enabling life-like effects by use of realistic shading, lighting, and textures. The higher
range and precision color allows for high-dynamic range lighting and motion blur.
7.1.2.4.1
Color Dithering
Color Dithering helps to hide color quantization errors. Color Dithering takes advantage
of the human eye’s propensity to “average” the colors in a small area. Input color,
alpha, and fog components are converted from 5 or 6-bit component to 8-bit
components by dithering. Dithering is performed on blended textured pixels with
random lower bits to avoid visible boundaries between the relatively discrete 5/6-bit
colors. Dithering is not performed on components containing 8 bits or more.
7.1.2.4.2
Vertex and Per Pixel Fogging
Fogging is used to create atmospheric effects such as low visibility conditions in flight
simulator- type games. It adds another level of realism to computer-generated scenes.
Fog can be used for depth cueing or hiding distant objects. With fog, distant objects
can be rendered with fewer details (fewer polygons), thereby improving the rendering
speed or frame rate. Fog is simulated by attenuating the color of an object with the fog
color as a function of distance. The higher the density (lower visibility for distant
objects). There are two ways to implement the fogging technique: per-vertex (linear)
fogging and per-pixel (non-linear) fogging. The per-vertex method interpolates the fog
value at the vertices of a polygon to determine the fog factor at each pixel within the
polygon. This method provides realistic fogging as long as the polygons are small. With
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large polygons (such as a ground plane depicting an airport runway), the per-vertex
technique results in unnatural fogging. The Mobile Intel GMA X3100 supports both
types of fog operations, vertex and per pixel or table fog.
7.1.2.4.3
Alpha Blending (Frame Buffer)
Alpha Blending adds the property of transparency or opacity to an object. Alpha
blending combines a source pixel color (RSGSBS) and alpha (AS) component with a
destination pixel color (RDGDBD) and alpha (AD) component. For example, this is so
that a glass surface on top (source) of a red surface (destination) would allow much of
the red base color to show through.
Blending allows the source and destination color values to be multiplied by
programmable factors and then combined via a programmable blend function. The
combined and independent selection of factors and blend functions for color and alpha
are supported.
7.1.2.4.4
Color Buffer Formats: 8, 16, 32, 64 or 128 Bits Per Pixel (Destination Alpha)
The raster engine will support 8-, 16-, 32-, 64- and 128-bit color buffer formats. The 8bit format is used to support planar YUV420 format, which used only in Motion
Compensation and Arithmetic Stretch format. The bit format of Color and Z will be
allowed to mix.
The Mobile Intel GMA X3100 supports both double and triple buffering, where one
buffer is the primary buffer used for display and one or two are the back buffer(s) used
for rendering.
The frame buffer of the Mobile Intel GMA X3100 contains at least two hardware buffers:
the Front Buffer (display buffer) and the Back Buffer (rendering buffer). While the back
buffer may actually coincide with (or be part of) the visible display surface, a separate
(screen or window-sized) back buffer is used to permit double-buffered drawing. That
is, the image being drawn is not visible until the scene is complete and the back buffer
made visible (via an instruction) or copied to the front buffer (via a 2D BLT operation).
Rendering to one and displaying from the other remove the possibility of image tearing.
This also speeds up the display process over a single buffer. Additionally, triple back
buffering is also supported. The instruction set of the Mobile Intel GMA X3100 provides
a variety of controls for the buffers (e.g., initializing, flip, clear, etc.).
7.1.2.4.5
Depth Buffer
The raster engine will be able to read and write from this buffer and use the data in per
fragment operations that determine whether resultant color and depth value of the
pixel for the fragment are to be updated or not.
7.1.2.4.6
Stencil Buffer
The Raster engine will provide 8-bit stencil buffer storage in 32 and 64-bit mode and
the ability to perform stencil testing. Stencil testing controls 3D drawing on a per pixel
basis, conditionally eliminating a pixel on the outcome of a comparison between a
stencil reference value and the value in the stencil buffer at the location of the source
pixel being processed. They are typically used in multipass algorithms to achieve
special effects, such as decals, outlining, shadows and constructive solid geometry
rendering.
7.1.2.4.7
Intermediate Z
The Mobile Intel GMA X3100 supports intermediate Z test, which avoids pixel
processing on occluded polygons for enhanced 3D graphics performance
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7.1.3
2D Engine
The Mobile Intel GMA X3100 contains BLT functionality, and an extensive set of 2D
instructions. To take advantage of the 3D drawing engine’s functionality, some BLT
functions such as Alpha BLTs, arithmetic (bilinear) stretch BLTs, rotations, transposing
pixel maps, limited color space conversion, and DIBs make use of the 3D renderer.
7.1.3.1
The Mobile Intel GMA X3100 VGA Registers
The 2D registers are a combination of registers for the original Video Graphics Array
(VGA) and others that Intel has added to support graphics modes that have color
depths, resolutions, and hardware acceleration features that go beyond the original
VGA standard.
7.1.3.2
Logical 128-Bit Fixed BLT and 256 Fill Engine
Use of this BLT engine accelerates the Graphical User Interface (GUI) of Microsoft
Windows* operating systems. The 128-bit Mobile Intel GMA X3100 BLT Engine provides
hardware acceleration of block transfers of pixel data for many common Windows
operations. The term BLT refers to a block transfer of pixel data between memory
locations. The BLT engine can be used for the following:
• Move rectangular blocks of data between memory locations
• Data alignment
• Perform logical operations (raster ops)
The rectangular block of data does not change as it is transferred between memory
locations. The allowable memory transfers are between: cacheable system memory
and frame buffer memory, frame buffer memory and frame buffer memory, and within
system memory. Data to be transferred can consist of regions of memory, patterns, or
solid color fills. A pattern will always be 8x8 pixels wide and may be 8, 16, or 32 bits
per pixel.
The Mobile Intel GMA X3100 BLT engine has the ability to expand monochrome data
into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent.
Opaque transfers move the data specified to the destination. Transparent transfers
compare destination color to source color and write according to the mode of
transparency selected.
Data is horizontally and vertically aligned at the destination. If the destination for the
BLT overlaps with the source memory location, the Mobile Intel GMA X3100 can specify
which area in memory to begin the BLT transfer. Hardware is included for all 256 raster
operations (Source, Pattern, and Destination) defined by Microsoft, including
transparent BLT.
The Mobile Intel GMA X3100 has instructions to invoke BLT and stretch BLT operations,
permitting software to set up instruction buffers and use batch processing. The Mobile
Intel GMA X3100 can perform hardware clipping during BLTs.
7.1.3.3
HW Rotation
The Mobile Intel GMA X3100 has made it possible for the primary display of a Dual
Display Clone configuration to be independently rotated at 180º when secondary
display is in normal mode (0°) or vice versa. This is achieved by hardware accelerated
rotation.
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7.1.4
Video Engine
7.1.4.1
Dynamic Video Memory Technology (DVMT 4.0)
DVMT is an enhancement of the Unified Memory Architecture (UMA) concept, wherein
the optimum amount of memory is allocated for balanced graphics and system
performance. DVMT ensures the most efficient use of available memory – regardless of
frame buffer or main memory size – for balanced 2D/3D graphics performance and
system performance. DVMT dynamically responds to system requirements and
applications’ demands, by allocating the proper amount of display, texturing and buffer
memory after the operating system has booted. For example, a 3D application when
launched may require more vertex buffer memory to enhance the complexity of objects
or more texture memory to enhance the richness of the 3D environment. The operating
system views the Intel Graphics Driver as an application, which uses Direct AGP to
request allocation of additional memory for 3D applications, and returns the memory to
the operating system when no longer required.
7.1.4.2
Intel® Clear Video Technology
Intel® Clear Video Technology enables new features such as: MPEG-2 Hardware
Acceleration; WMV9 Hardware Acceleration; ProcAmp; Advanced Pixel Adaptive Deinterlacing; Sharpness Enhancement; De-Noise Filter; High Quality scaling; Film mode
detection and correction; Intel® TV Wizard to deliver an outstanding media experience
on the Mobile Intel GMA X3100
Note:
For additional information on any of the Intel® Clear Video Technology features, refer
to Intel® Graphics Media Accelerator-Video Software Product Specification (SPS).
7.1.4.2.1
MPEG-2 Hardware Acceleration
MPEG-2 content format is one of the most prevalent formats for video content. Since
introduction in 1994, it has become extensively utilized in DVD, HDTV, digital satellite
broadcasts, and also become a prevalent standard for PC based video. Partitioning the
MPEG-2 workload between the integrated graphics device and the CPU allows for
reduced workload when performing simultaneous support of up to two streams of
video.
Figure 14 illustrates the hardware acceleration provided by the Mobile Intel GMA X3100
for the MPEG-2 decode pipeline.
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Figure 14.
MPEG-2 Decode Stage
D ecode
V a r ia b le L e n g th
D ecode
In v e r s e
Q u a n tiz a tio n
In v e r s e
D is c re te C o s in e
T ra n s fo rm
CPU
GM CH
7.1.4.2.2
M o tio n
C o m p e n s a tio n
WMV9 Hardware Acceleration
WMV9 is Microsoft’s* implementation of the VC-1 CODEC standard. It is bitstream
compatible with VC-1 however it is optimized for progressive content only and thus has
different software entry points than standard VC-1. The Mobile Intel GMA X3100 core
provides hardware acceleration for the WMV9 stages indicated in the diagram below. It
should be noted that the various decode stages of WMV9 are typically referred to by
letter. The Mobile Intel GMA X3100 core provides hardware acceleration for the WMV9b
stage of the decode pipeline; specifically, this accelerates the motion compensation and
in-loop deblocking stages for progressive content.
Figure 15 illustrates the hardware acceleration provided by the Mobile Intel GMA X3100
for the WMV9 decode pipeline.
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Figure 15.
WMV9 Decode Stage
D ecode
V a r ia b le L e n g th
D ecode
In v e r s e
Q u a n tiz a tio n
In v e r s e
T ra n s fo rm
M o tio n
C o m p e n s a tio n
CPU
In -L o o p
D e b lo c k in g
G M CH
7.1.4.2.3
ProcAmp
ProcAmp is the short name for “Processing Amplifier”. It is an amplifier to adjust video
visual attributes, such as brightness, contrast, hue and saturation. These adjustments
are typically controlled by users through the video player application. However when
using Microsoft’s DXVA driver interface, the ProcAmp calls to the Mobile Intel GMA
X3100 core are utilized to perform image enhancements on a frame by frame basis.
7.1.4.2.4
Advanced Pixel Adaptive De-interlacing
Interlaced data that originates from a video camera creates two fields that are
temporally offset by 1/60 of a second. These fields have alternating lines of data and
thus must be adapted for use on progressive PC displays. There are several basic
schemes to deinterlace the video stream: line replication, vertical filtering, field
merging and vertical temporal filtering. All of these create varying degrees of visual
artifacts.
The Mobile Intel GMA X3100 core brings with it enhanced hardware integration allowing
de-interlacing of video content for a high quality experience with interlaced formats. It
also reduces static and motion artifacts with an edge adaptive spatial, temporal filter
and motion detector. A pixel adaptive de-interlacing algorithm provides enhanced
picture clarity for interlaced content. Hardware acceleration off loads post-processing
from CPU to chipset to reduce CPU utilization, further improving performance.
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7.1.4.2.5
Film Mode Detection and Correction
A special case of deinterlacing deals with pulled down content. For example, when
broadcasting a typical Hollywood movie over NTSC TV, 3:2 pull down converts 24
progressive frames/sec into 60 interlaced fields/sec. This is accomplished by splitting
the progressive source content into fields, and then replicating the fields every other
frame. Furthermore, because 24 fps does not directly translate to the 60Hz refresh rate
of NTSC television, the resulting fields need to be replicated in an odd cadence thus
creating a 3,2,3,2... pattern in the fields.
Playing back such an encoded stream using typical deinterlacing methods, misses an
opportunity to achieve significantly enhanced visual quality. By detecting the repetitive
3:2 cadence, Intel® Clear Video Technology is capable of recreating the original
progressive frames. By working with the original progressive content artifacts are
minimized.
Making use of Intel® Clear Video Technology’s Film Mode Cadence Detection and
Correction features is fully transparent to video playback software. Playback software
need only request the highest level of deinterlacing be utilized. Intel® Clear Video
Technology will automatically apply the necessary algorithms for perfect deinterlacing if
a recognized cadence is observed. Otherwise, the highest level of deinterlacing
supported shall be utilized.
7.1.4.2.6
Sharpness Enhancement
With the proliferation of televisions capable of presenting content in high definition
resolutions, there is a need to routinely scale standard definition content to HD
resolutions. While high quality scalars are vital to performing this task, large scale
ratios can still lead to edge artifacts such as blurring, haloing, and ringing.
Intel’s sharpness enhancement filters reduce the appearance of these artifacts by
identifying and operating on the edges within an image. By applying noise reduction
algorithms specifically on shape edges and improving contrast ratios in these specific
regions, Intel® Clear Video Technology helps mitigate artifacts that typically
accompany high scale ratios.
7.1.4.2.7
De-noise Filter
When working with analog video streams, capturing, converting, and duplicating the
content will inevitably inject analog noise into the stream; thus degrading the overall
video quality. Digital video streams can also exhibit similar artifacts as a result of their
original capture or their subsequent compression. Noise artifacts are most noticeable in
regions of the image that contain large areas of solid colors.
Traditional de-noise algorithms often suppress fine detail within an image by mistaking
the detail for noise. However, Intel® Clear Video Technology leverages its motion
detection algorithms to dramatically reduce the appearance of randomized noise in
video streams while accurately preserving fine detail. By realizing that noise artifacts
are nondeterministic in their motion, Intel’s de-noise filters are able to differentiate
between noise and valid video data.
7.1.4.2.8
High Quality Scaling
Intel® Clear Video Technology’s high quality scaling utilizes advanced filtering
techniques allowing video to be up-scaled or down-scaled to fit any playback window.
This includes non-square scaling. In addition to the obvious benefits of traditional video
playback, this also allows for the accurate and efficient mixing of differently sized video
streams.
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Integrated Graphics Controller
The Mobile Intel GMA X3100 core utilizes a 4x4 (polyphase) filter, a 4x4 (bicubic) filter,
as well as a 2x2 (bilinear) filter. This allows for playback applications to strike a balance
between video quality and performance overhead in specific scenarios.
7.1.4.2.9
Intel® TV Wizard
Intel® TV Wizard is a new, independent graphical user interface (GUI) application that
comes packaged along with the Intel Graphics driver. Currently PC to TV interaction is
not user friendly and it needs lot of adjustments to get a good quality picture on TV.
The application is used by end-users to configure their TV display outputs in a predefined sequence.
7.1.4.3
Sub-Picture Support
Sub-picture is used for two purposes, one is Subtitles for movie captions, etc. (which
are superimposed on a main picture), and Menus used to provide some visual operation
environments the user of a content player.
The Mobile Intel GMA X3100 supports sub-picture by mixing the two video streams via
alpha blending. Unlike color keying, alpha blending provides a softer effect and each
pixel that is displayed is a composite between the two video stream pixels. The Mobile
Intel GMA X3100 can utilize multiple methods when dealing with sub-pictures. The
flexibility enables the Mobile Intel GMA X3100 to work with all sub- picture formats.
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8
Display Interfaces
The display is the defining portion of a graphics controller. The display converts a set of
source images or surfaces, combines them and sends them out at the proper timing to
an output interface connected to a display device. Along the way, the data can be
converted from one format to another, stretched or shrunk, and color corrected or
gamma converted.
Figure 16.
Mobile Intel GM965/GL960 Chipset Display Block Diagram
Plane A
Overlay
CRT
Cursor A
Pipe A
LVDS
VGA
Alpha Blend/
Gamma/
Panel Fitter
MUX
TVOUT
Plane B
Plane C/
Sprite
Pipe B
SDVO
B/C
Cursor B
8.1
Display Overview
Integrated graphics display on the (G)MCH can be broken down into three components:
• Display Planes
• Display Pipes
• Display Ports
8.2
Planes
The (G)MCH contains a variety of planes, such as Plane A and Plane B, Cursor, Overlay,
Sprite, A plane consists of rectangular shaped image that has characteristics such as
source, size, position, method, and format. These planes get attached to source
surfaces, which are rectangular areas in memory with a similar set of characteristics.
They are also associated with a particular destination pipe.
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8.2.1
DDC (Display Data Channel)
DDC is a standard defined by VESA. Its purpose is to allow communication between the
host system and display. Both configuration and control information can be exchanged
allowing Plug and Play systems to be realized. Support for DDC 1 and 2 is
implemented. The chipset uses the CRTDDCCLK and CRTDDCDATA signals to
communicate with the analog monitor.
8.2.1.1
Source/Destination Color Keying/ChromaKeying
Overlay source/destination ChromaKeying enables blending of the overlay with the
underlying graphics background. Destination color keying/ChromaKeying can be used
to handle occluded portions of the overlay window on a pixel by pixel basis that is
actually an underlay. Destination ChromaKeying would only be used for YUV pass
through to TV. Destination color keying supports a specific color as well as alpha
blending.
8.2.1.2
Gamma Correction
To compensate for overlay color intensity loss due to the non-linear response between
display devices, the overlay engine supports independent gamma correction. This
allows the overlay data to be converted to linear data or corrected for the display
device when not blending.
8.3
Display Pipes
The display consists of two pipes:
• Display Pipe A
• Display Pipe B
A pipe consists of a set of combined planes and a timing generator. The timing
generators provide the basic timing information for each of the display pipes. The
(G)MCH has two independent display pipes, allowing for support of two independent
display streams. A port is the destination for the result of the pipe.
The Mobile Intel GM965/GL960 Chipset has flexibility to support all display types from
both display pipes with enhanced 3x3 panel fitter. It also enables support for 7x5
scaling for external TV monitors with over scan control for HDTV displays.
8.3.1
Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It
operates by converting an input reference frequency into an output frequency. The
timing generators take their input from internal DPLL devices that are programmable to
generate pixel clocks in the range of 25-350 MHz. Accuracy for VESA timing modes is
required to be within ± 0.5%.
The DPLL can take a reference frequency from the external reference input
(DPLL_REF_CLK / DPLL_REF_CLK#, DPLL_REF_SSCLK / DPLL_REF_SSCLK#), or the TV
clock input (TVCLKIN).
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8.4
Display Ports
Display ports is the destination for the display pipe. These are the places where the
data finally appears to devices outside the graphics device. The (G)MCH has one
dedicated CRT display port (analog), one TV out port (analog), one LVDS port (digital),
and two SDVO ports (digital).
• CRT
• LVDS
• TV out
• SDVO (B&C)
Table 14.
Display Port Characteristics
Interface Protocol
S
I
G
N
A
L
S
(Analog)
LVDS
RGB DAC
LVDS
Port C
(Digital)
Port B
(Digital)
SDVO 1.0
SDVO 1.0
HSYNC
Yes Enable/
Polarity
Encoded during blanking codes
VSYNC
Yes Enable/
Polarity
Encoded during blanking codes
BLANK
No
No
Encoded
Encoded
STALL
No
No
Yes
Yes
Field
No
No
No
No
Display_Enable
No
Yes*
Encoded
Encoded
Image Aspect Ratio
Programmable and typically 1.33:1 or 1.78:1
Pixel Aspect Ratio
Square*
Square
Voltage
RGB 0.7V p-p
1.2 VDC
300 mV p-p
Scalable 1.x V
7x Differential
(dual channel)
Clock
3.5x
Differential
(Single
channel)
NA
224 MPixel
(dual channel)
Max Rate
300 Mpixel
112 Mpixel
(Single
Channel)
Format
Analog RGB
Multiple
18bpp or
24bpp Type
1(single
channel only)
Control Bus
DDC1
Optional DDC
External Device
No
No
Connector
VGA/DVI-I
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200 Mpixel
RGB 8:8:8 YUV 4:4:4
GMBUS
TMDS/LVDS Transmitter /TV Encoder
DVI/CVBS/S-Video/Component/
SCART
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8.4.1
Analog Display Port Characteristics
The analog display port provides a RGB signal output along with a HSYNC and VSYNC
signal. There is an associated DDC signal pair that is implemented using GPIO pins
dedicated to the analog port. The intended target device is for a CRT based monitor
with a VGA connector. Display devices such as LCD panels with analog inputs may work
satisfactory but no functionality has been added to the signals to enhance that
capability.
Table 15.
Analog Port Characteristics
Signal
RGB
HSYNC
VSYNC
Port Characteristic
Support
Voltage Range
0.7 V p-p only
Monitor Sense
Analog Compare
Analog Copy Protection
No
Sync on Green
No
Voltage
2.5 V
Enable/Disable
Port control
Polarity adjust
VGA or port control
Composite Sync Support
No
Special Flat Panel Sync
No
Stereo Sync
DDC
8.4.1.1
No
Voltage
Externally buffered to 5 V
Control
Through GPIO interface
Integrated RAMDAC
The display function contains a RAM-based Digital-to-Analog Converter (RAMDAC) that
transforms the digital data from the graphics and video subsystems to analog data for
the CRT monitor. For (G)MCH supported resolutions, refer to the OMP tool. Three 8-bit
DACs provide the R, G, and B signals to the monitor.
8.4.1.2
Sync Signals
HSYNC and VSYNC signals are digital and conform to TTL signal levels at the connector.
Since these levels cannot be generated internally, external level shifting buffers are
required. These signals can be polarity adjusted and individually disabled in one of the
two possible states. The sync signals should power up disabled in the high state. No
composite sync or special flat panel sync support will be included.
8.4.2
Dedicated LFP LVDS Port
The display pipe selected by the LVDS display port is programmed with the panel timing
parameters that are determined by installed panel specifications or read from an
onboard EDID ROM. The programmed timing values are then “locked” into the registers
to prevent unwanted corruption of the values. From that point on, the display modes
are changed by selecting a different source size for that pipe, programming the VGA
registers, or selecting a source size and enabling the VGA. The timing signals will
remain stable and active through mode changes. These mode changes include VGA to
VGA, VGA to HiRes, HiRes to VGA, and HiRes to HiRes.
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The transmitter can operate in a variety of modes and supports several data formats.
The serializer supports 6-bit or 8-bit color and single or dual channel operating modes.
The display stream from the display pipe is sent to the LVDS transmitter port at the dot
clock frequency, which is determined by the panel timing requirements. The output of
LVDS is running at a fixed multiple of the dot clock frequency, which is determined by
the mode of operation; single or dual channel.
Depending on configuration and mode, a single channel can take 18 bits of RGB pixel
data plus 3 bits of timing control (HSYNC/VSYNC/DE) and output them on three
differential data pair outputs; or 24 bits of RGB plus 3 bits of timing control output on
four differential data pair outputs. A dual channel interface converts 36 or 48 bits of
color information plus the 3 bits of timing control and outputs it on six or eight sets of
differential data outputs respectively.
This display port is normally used in conjunction with the pipe functions of panel scaling
and 6- to 8-bit dither. This display port is also used in conjunction with the panel power
sequencing and additional associated functions.
When enabled, the LVDS constant current drivers consume significant power. Individual
pairs or sets of pairs can be selected to be powered down when not being used. When
disabled, individual or sets of pairs will enter a low power state. When the port is
disabled all pairs enter a low power mode. The panel power sequencing can be set to
override the selected power state of the drivers during power sequencing.
8.4.2.1
LVDS Interface Signals
There are two LVDS transmitter channels (channel A and channel B) in the LVDS
interface. Channel A and Channel B consist of 4-data pairs and a clock pair each. The
phase locked transmit clock is transmitted in parallel with the data being sent out over
the data pairs and over the LVDS clock pair. There are two LVDS transmitter channels
(channel A and channel B) in the LVDS interface. Channel A and Channel B consist of 4data pairs and a clock pair each. The phase locked transmit clock is transmitted in
parallel with the data being sent out over the data pairs and over the LVDS clock pair.
Each channel supports transmit clock frequency ranges from 25 MHz to 112 MHz, which
provides a throughput of up to 784 Mbps on each data output and up to 112 MP/s on
the input. When using both channels, they each operate at the same frequency each
carrying a portion of the data. The maximum pixel rate is increased to 224 MP/s but
may be limited to less than that due to restrictions elsewhere in the circuit.
The LVDS Port enable bit enables or disables the entire LVDS interface. When the port
is disabled, it will be in a low power state. Once the port is enabled, individual driver
pairs will be disabled based on the operating mode. Disabled drivers can be powered
down for reduced power consumption or optionally fixed to forced 0’s output.
8.4.2.2
LVDS Data Pairs and Clock Pairs
The LVDS data and clock pairs are identical buffers and differ only in the use defined for
that pair. The LVDS data pair is used to transfer pixel data as well as the LCD timing
control signals. The pixel bus data to serial data mapping options are specified
elsewhere. A single or dual clock pair is used to transfer clocking information to the
LVDS receiver. A serial pattern of 1100011 represents one cycle of the clock.
Figure 17 shows a pair of LVDS signals and swing voltage.
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Figure 17.
LVDS signals and Swing Voltage
1’s and 0’s are represented the differential voltage between the pair of signals.
Figure 18.
LVDS Clock and Data Relationship
8.4.2.3
LVDS Pair States
The LVDS pairs can be put into one of five states, powered down tri-state, powered
down 0 V, common mode, send zeros, or active. When in the active state, several data
formats are supported. When in powered down state, the circuit enters a low power
state and drives out 0 V or tri-states on both the output pins for the entire channel. The
common mode tri-state is both pins of the pair set to the common mode voltage. When
in the send zeros state, the circuit is powered up but sends only zero for the pixel color
data regardless what the actual data is with the clock lines and timing signals sending
the normal clock and timing data.
8.4.2.4
Single Channel versus Dual Channel Mode
In the single channel mode, only Channel-A is used. Channel-B cannot be used for
single channel mode. In the dual channel mode, both Channel-A and Channel-B pins
are used concurrently to drive one LVDS display.
In Single Channel mode, Channel A is capable of supporting 24bpp display panels of
Type 1 only (compatible with VESA LVDS color mapping). In Dual Channel mode,
Channel A and B are capable of supporting 24 bpp panels of Type 1.
Dual channel mode uses twice the number of LVDS pairs and transfers the pixel data at
twice the rate of the single channel. In general, one channel will be used for even pixels
and the other for odd pixel data. The first pixel of the line is determined by the display
enable going active and that pixel will be sent out Channel-A. All horizontal timings for
active, sync, and blank will be limited to be on two pixel boundaries in the two channel
modes.
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8.4.2.5
LVDS Channel Skew
When in dual channel mode, the two channels must meet the panel requirements with
respect to the inter channel skew.
8.4.2.6
LVDS PLL
The Display PLL is used to synthesize the clocks that control transmission of the data
across the LVDS interface. The three operations that are controlled are the pixel rate,
the load rate, and the IO shift rate. These are synchronized to each other and have
specific ratios based on single channel or dual channel mode. If the pixel clock is
considered the 1x rate, a 7x or 3.5x speeds IO_shift clock needed for the high speed
serial outputs setting the data rate of the transmitters. The load clock will have either a
1x or 0.5x ratio to the pixel clock.
8.4.2.7
Panel Power Sequencing
This section provides details for the power sequence timing relationship of the panel
power, the backlight enable and the LVDS data timing delivery. In order to meet the
panel power timing specification requirements, two signals, LFP_VDD_EN and
LFP_BKLT_EN are provided to control the timing sequencing function of the panel and
the backlight power supplies.
8.4.2.7.1
Panel Power Sequence States
A defined power sequence is recommended when enabling the panel or disabling the
panel. The set of timing parameters can vary from panel to panel vendor, provided that
they stay within a predefined range of values. The panel VDD power, the backlight on/
off state and the LVDS clock and data lines are all managed by an internal power
sequencer.
A requested power-up sequence is only allowed to begin after the power cycle delay
time requirement T4 is met.
Figure 19.
Panel Power Sequencing
T4
T1+T2
TX
T5
T3
T4
Panel
On
Panel VDD
Enable
Panel
BackLight
Enable
Off
Off
Valid
Clock/Data Lines
Power On Sequence from off state and
Power Off Sequence after full On
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Table 16.
Panel Power Sequencing Timing Parameters
Panel Power Sequence Timing Parameters
Spec Name
From
Min
Max
Name
Units
To
Vdd On
0.1 Vdd
0.9 Vdd
0
10
T1
ms
LVDS Active
Vdd Stable On
LVDS Active
0
50
T2
ms
Backlight
LVDS Active
Backlight on
200
T5
ms
Backlight State
Backlight Off
LVDS off
X
X
TX
ms
LVDS State
LVDS Off
Start power off
0
50
T3
ms
Power cycle Delay
Power Off
Power On
Sequence Start
0
400
T4
ms
8.4.3
SDVO Digital Display Port
8.4.3.1
SDVO
Intel SDVO ports can support a variety of display types – LVDS, DVI, HDMI, TV-Out,
etc, and external CE type devices. The (G)MCH utilizes an external SDVO device to
translate from SDVO protocol and timings to the desired display format and timings.
8.4.3.2
SDVO DVI
DVI, a 3.3-V flat panel interface standard, is a prime candidate for SDVO. Mobile Intel
GM965/GL960 Chipset provides unscaled mode where the display is centered on the
panel.
Monitor Hot Plug functionality is supported for DVI devices.
8.4.3.3
SDVO LVDS
The (G)MCH may use the SDVO port to drive an LVDS transmitter. Flat Panel is a fixed
resolution display. The (G)MCH supports panel fitting in the transmitter, receiver or an
external device, but has no native panel fitting capabilities. The (G)MCH will however,
provide unscaled mode where the display is centered on the panel. Scaling in the LVDS
transmitter through the SDVO stall input pair is also supported.
8.4.3.4
SDVO TV-Out
The SDVO port supports both standard and high-definition TV displays in a variety of
formats. The SDVO port generates the proper blank and sync timing, but the external
encoder is responsible for generation of the proper format signal and output timings.
(G)MCH will support NTSC/PAL/SECAM standard definition formats. The (G)MCH will
generate the proper timing for the external encoder. The external encoder is
responsible for generation of the proper format signal.
The TV-out interface on (G)MCH is addressable as a master device. This allows an
external TV encoder device to drive a pixel clock signal on SDVO_TVCLKIN[+/-] that
the (G)MCH uses as a reference frequency. The frequency of this clock is dependent on
the output resolution required.
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8.4.3.5
SDVO HDMI
HDMI is a 3.3-V interface that uses TMDS encoding, and requires an active level shifter
to get 3.3-V DC coupling. The (G)MCH supports the mandatory features of HDMI
Specification 1.3. When combined with a HDMI compliant external device and
connector, the external HDMI device can support standard, enhanced, or high-definition
video, plus multi-channel digital audio on a single cable. The (G)MCH has a high speed
interface to a digital display (e.g., flat panel or digital TV).
8.4.3.6
TMDS
The (G)MCH is compliant with DVI Specification 1.0. DVI requires an SDVO device. The
(G)MCH supports panel fitting in the transmitter, receiver or an external device.
8.4.3.7
Flicker Filter and Overscan Compensation
The overscan compensation scaling and the flicker filter is done in the external TV
encoder chip. Care must be taken to allow for support of TV sets with high performance
de-interlacers and progressive scan displays connected to by way of a non-interlaced
signal. Timing will be generated with pixel granularity to allow more overscan ratios to
be supported.
8.4.3.8
Direct YUV from Overlay
When source material is in the YUV format and is destined for a device that can take
YUV format data in, it is desired to send the data without converting it to RGB. This
avoids the truncation errors associated with multiple color conversion steps. The
common situation will be that the overlay source data is in the YUV format and will
bypass the conversion to RBG as it is sent to the TV port directly.
8.4.3.9
Analog Content Protection
Analog content protection may be provided through the external encoder.
8.4.3.10
Connectors
Target TV connector support includes the CVBS, S-Video, Analog Component (YPbPr),
and SCART connectors. The external TV encoder will determine the method of support.
8.4.3.11
Control Bus
The SDVO port defines a two-wire communication path between the SDVO device(s)
and (G)MCH. Traffic destined for the PROM or DDC will travel across the Control bus,
and will then require the SDVO device to act as a switch and direct traffic from the
Control bus to the appropriate receiver. Additionally, the Control bus is able to operate
at up to 1 MHz.
8.5
Multiple Display Configurations
Since the (G)MCH has several display ports available for its two pipes, it can support up
to two different images on different display devices. Timings and resolutions for these
two images may be different. The (G)MCH is incapable of operating in parallel with an
external PCI Express graphics device. The (G)MCH can, however, work in conjunction
with a PCI graphics adapter.
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Power Management
9
Power Management
9.1
Overview
• Supports ACPI 3.0
• S States: S0, S3Cold, S4, S5
• C states: C0, C1, C1E, C2, C2E, C3, C4, C4E, and Intel® Enhanced Deeper Sleep
states
• Internal Graphics Display Device states: D0, D1, D2, D3
• Graphics Display Adapter states: D0, D3
• PCI Express Link states: L0, L0s, L1(including ASPM), L2/ L3 ready, L3
• H_SLPCPU# output
• Intel Rapid Memory Power Management (Intel RMPM)
• Dynamic I/O power reduction
• Intel Display Power Saving Technology (Intel DPST) 3.0
• Intel® S2DDT
• Dynamic Display Power Optimization* (D2PO) Panel Support
• Intel® Automatic Display Brightness
• Intel® Display Refresh Rate Switching
• Intel® Dynamic Front Side Bus Frequency Switching is not supported
• Graphics Render Standby
9.2
ACPI States Supported
(G)MCH supports the following ACPI states:
9.2.1
System
State
Description
G0/S0
Full On
G1/S1
Not supported
G1/S1
Not supported
G1/S2
Not supported
G1/S3-Cold
Suspend to RAM (STR). Context saved to memory (S3-Hot is not
supported by Mobile Intel GM965/PM965/GL960 Express
Chipset)
G1/S4
Suspend to Disk (STD). All power lost (except wakeup on ICH)
G2/S5
Soft off. All power lost (except wakeup on ICH). Total reboot
G3
Mechanical off. All power (AC and battery) removed from system
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9.2.2
Processor
State
9.2.3
Description
C0
Full On
C1/C1E
Auto Halt
C2/C2E
Stop Grant. Clock stopped to processor core
C3
Deep Sleep. Clock to processor stopped
C4/C4E
Deeper Sleep. Same as C3 with reduced voltage on the processor
Internal Graphics Display Device Control
State
9.2.4
Description
D0
Display Active
D1
Low power state, low latency recovery, Standby display
D2
Suspend display
D3
Power off display
Internal Graphics Adapter
State
Description
D0
Full on, display active
D3 Cold
Power off
9.3
Interface Power States Supported
9.3.1
PCI Express Link States
State
110
Description
L0
Full on – Active transfer state
L0s
First Active Power Management low power state – Low exit
latency
L1
Lowest Active Power Management - Longer exit latency
L2/L3 Ready
Lower link state with power applied – Long exit latency
L3
Lowest power state (power off) – Longest exit latency
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9.3.2
Main Memory States
State
9.4
Description
Power up
CKE asserted. Active mode
Pre-charge Power down
CKE deasserted (not self-refresh) with all banks closed
Active Power down
CKE deasserted (not self-refresh) with min. one bank
active
Self-Refresh
CKE deasserted using device self-refresh
Power Management Features
Refer to the ACPI Specification Revision 3.0 for an overview of the system power
states.
9.4.1
Dynamic Power Management on I/O
(G)MCH provides several features to reduce I/O power dynamically.
9.4.1.1
System Memory
• Dynamic Power Down of unused ranks of memory.
• Intel Rapid Memory Power Management conditionally places memory into selfrefresh based on C state, PCI Express link states, and graphics/display activity.
9.4.1.2
PCI Express
• Active power management support using L0, L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
9.4.1.3
DMI
• Active power management support using L0s/L1 state.
• All inputs and outputs disabled in L2/L3 Ready state.
9.4.1.4
Intel Management Engine
• Active power management support using M0, M1 and M-off states.
• Only (G)MCH Clocks enabled in M1-state; All ME rails powered down.
9.4.1.5
SDVO
• Disabling of SDVO places all SDVO logic and I/O in minimum power state.
9.4.1.6
H_DPWR#
• H_DPWR# signal disables processor sense amps when no read return data is
pending.
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9.4.2
System Memory Power Management
The main memory is power managed during normal operation and in low power ACPI
Cx states.
9.4.2.1
Intel® Rapid Memory Power Management (Intel® RMPM)
This technique is to allow all rows of memory to be self refresh with all on chip DLLs off
and all DIMM clocks off as long as possible during C3 and above to reduce power
consumption. This is accomplished by adding a mechanism in the memory controller to
allow for self-refresh entry and exit during C3 and above, and allow for single row self
refresh exit during C3 and above.
9.4.2.2
Disabling Unused System Memory Outputs
Any System Memory (SM) interface signal that goes to a SO-DIMM connector in which
it is not connected to any actual memory devices (such as SO-DIMM connector is
unpopulated, or is single-sided) will be tri-stated.
The benefits of disabling unused SM signals are:
• Reduce power consumption.
• Reduce possible overshoot/undershoot signal quality issues seen by the (G)MCH
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated (as determined by the DRAM Rank Boundary
Register values) then the corresponding chip select and SCKE signals will not be driven.
SCKE tri-state should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
9.4.2.3
Dynamic Power Management of Memory
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. If the pages for a rank have
all been closed at the time of power down, then the device will enter the precharge
power-down state. If pages remain open at the time of power-down the devices will
enter the active power-down state.
9.4.2.4
Conditional Self-Refresh
The chipset supports Intel Rapid Memory Power Management which a conditionally
places memory into self-refresh in the C3, C4 and Intel® Enhanced Deeper Sleep
states, based on memory traffic.
The target behavior is to enter self-refresh for C3/C4/Intel® Enhanced Deeper Sleep
states as long as there is no memory requests to service.
Though the dependencies on this behavior are configurable, the target usage is shown
in the table below.
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Power Management
Table 17.
Targeted Memory State Conditions
Memory State with Internal
Graphics
Memory State with External
Graphics
Dynamic memory rank power down
based on idle conditions
Dynamic memory rank power down
based on idle conditions
Mode
C0, C1, C2
C3, C4,
Intel®
Enhanced
Deeper
Sleep
9.5
Dynamic memory rank power down
based on idle conditions
If graphics engine is idle, no display
requests, and permitted display
configuration, then enter self-refresh.
Otherwise use dynamic memory rank
power down based on idle conditions
Dynamic memory rank power down
based on idle conditions
If there are no memory requests, then
enter self-refresh. Otherwise use
dynamic memory rank power down
based on idle conditions
S3
Self Refresh Mode
Self Refresh Mode
S4
Memory power down (contents lost)
Memory power down (contents lost)
Chipset State Combinations
(G)MCH supports the state combinations listed in the Table 18 and Table 19.
Table 18.
Table 19.
G, S and C State Combinations
Global
(G) State
Sleep
(S) State
CPU
(C) State
G0
S0
C0
Full On
On
Full On
G0
S0
C1
Auto-Halt
On
Auto Halt
G0
S0
C2
Stop Grant
On
Stop Grant
G0
S0
C3
Deep Sleep
On
Deep Sleep
G0
S0
C4
Deeper Sleep
On
Deep Sleep with
processor
voltage lowered.
G1
S3
power off
Off, except RTC
Suspend to RAM
G1
S4
power off
Off, except RTC
Suspend to Disk
G2
S5
power off
Off, except RTC
Soft Off
G3
NA
power off
Power Off
Hard Off
Processor State
System Clocks
Description
D, S, and C State Combinations (Sheet 1 of 2)
Graphics Adapter
(D) State
Sleep (S)
State
CPU (C)
State
Description
D0
S0
C0
Full On, Displaying
D0
S0
C1
Auto-Halt, Displaying
D0
S0
C2
Stop Grant, Displaying
D0
S0
C3
Deep Sleep, Displaying
D0
S0
C4
Deeper Sleep, Displaying
D1
S0
C0-2
Not Displaying
D1
S0
C3
Not Displaying
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Power Management
Table 19.
D, S, and C State Combinations (Sheet 2 of 2)
Graphics Adapter
(D) State
9.5.1
Sleep (S)
State
CPU (C)
State
D3
S0
C0-2/ C3/C4
D3
S3
---
D3
S4
---
Description
Not Displaying
Not Displaying
(G)MCH may power off
Not Displaying
Suspend to disk
CPU Sleep (H_SLPCPU#) Signal Definition
The processor’s sleep signal (SLP#) reduces power in the processor by gating off
unused clocks. This signal can be driven only by the (G)MCH’s H_SLPCPU# signal.
The (G)MCH host interface controller will ensure that no transactions will be initiated on
the FSB without having first met the required timing from the SLP# deassertion to the
assertion of BPRI#.
(G)MCH will control H_SLPCPU# and enforce the configured timing rules associated
with this. This allows the (G)MCH to enforce the timing of the SLP# deassertion to
BPRI# assertion during C3 to C2 or C3 to C0 transitions.
9.6
CLKREQ# - Mode of Operation
The CLKREQ# signal is driven by the (G)MCH to control the PCI Express clock to the
external graphics and the DMI clock. When both the DMI and PCI Express links (if supported) are in L1, with CPU in C3/C4/C4e state, the (G)MCH deasserts CLKREQ# to the
clock chip, allowing it to gate the GCLK differential clock pair to the (G)MCH, in turn
disabling the PCI Express and DMI clocks inside the (G)MCH. For the (G)MCH to support CLKREQ# functionality, ASPM must enabled on the platform.
9.7
Intel® Display Power Saving Technology (Intel®
DPST) 3.0
When enabled, the Intel Display Power Saving Technology (Intel DPST) feature
dynamically reduces the power (up to 25% reduction) of the panel backlight based on
the brightness distribution in each video frame being displayed. Users should be
comfortable with the changes in image and screen quality resulting from this
technology as well as initialization of Intel DPST. For example, in the case where the
user policy scheme allows Intel DPST to be enabled or disabled on the fly (e.g., when
changing from AC to DC), it must not disturb the work of the user (e.g., using colorpicker or doing image/photo/video editing).
Intel DPST 3.0 provides enhanced image quality over previous version of Intel DPST.
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External Design Specification
Power Management
9.8
Intel® Smart 2D Display Technology (Intel®
S2DDT)
Intel® Smart 2D Display Technology (Intel® S2DDT)) is a technique to reduce memory
reads and, hence, reduce read data power consumption and improve most CPU
benchmarks due to reduced CPU to memory read latency. Intel® S2DDT helps save
power in mobile systems. The Intel S2DDT (aka Frame Buffer Compression) engine
periodically compresses the front frame-buffer data and stores it in a compressed
frame buffer. In the upcoming frames, the display engine reads the compressed lines
from the compressed frame buffer instead of reading uncompressed lines from the
original frame buffer. Lines that were not compressed or lines that were modified since
the last compression are displayed from the uncompressed (original) frame buffer.
9.9
Dynamic Display Power Optimization* (D2PO)
Panel Support
D²PO* is a liquid crystal drive technology developed by Toshiba Matsushita Display
Technology Co., Ltd.* (TMD) that reduces the power consumption of the LCD for
notebook PCs. Intel’s D²PO* Panel Support feature employs this LCD technology
dynamically to achieve significant power savings while maintaining a high quality visual
experience.
9.10
Intel® Automatic Display Brightness
The Intel® Automatic Display Brightness feature dynamically adjusts the backlight
brightness based upon the current ambient light environment. This technique provides
both potential power savings and usability benefit by automatically decreasing the
backlight in dark environments and increasing the backlight in bright environments.
9.11
Intel® Display Refresh Rate Switching
Intel® Display Refresh Rate Switching is a method of saving power by automatically
switching the LCD refresh rate. This method switches between two display timings
stored in either the LCD EDID Detailed Timing Descriptors or in the Video BIOS Table.
The refresh rate switching will occur during AC/DC event or when the system boots or
resumes from S3/S4 in either AC or battery mode.
9.12
Intel® Dynamic Front Side Bus Frequency
Switching
Intel® Dynamic Front Side Bus Frequency Switching is a feature where the processor
and chipset work together in order to allow a virtual change in the bus clock frequency,
thereby reducing frequency by up to half. Reduced frequency allows the processor core
voltage to be lowered, thereby consuming less power while still active. This state is
exposed as a processor performance state (P-state) and is also known as super LFM.
9.13
Graphics Render Standby
Graphics Render Standby is a technique designed to optimize the average power to the
(G)MCH. (This technique requires a separate Graphics VRM.) (G)MCH will put the
Graphics Render engine to sleep, or Render Standby (RS), during times of inactivity or
basic video modes. While in Render Standby state, the (G)MCH will place the VR into a
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Power Management
low voltage state or shut it off through VID signals. To indicate a condition where
(G)MCH Render core is in a very low-power state, the (G)MCH will place the render
engine into a RS state and will change the VID code to the Render core VR to a lower
voltage state.
9.14
PWROK Timing Requirements for Power-up,
Resume from S3
Figure 20 highlights the timing requirements for the (G)MCH PWROK signal for Powerup and resume from S-states.
Figure 20.
Upon Power-up and Resume from S3/S4/S5
t0>0
t1>=1ms t2>=1us
PLL Vcc
GMCH VCC
e
HCLK/GCLK
Running and Stable
GMCH PWROK
NOTES:
1.
Timings t1, t2 apply for both Power-up and Resume from S3-Cold events
2.
t1: All (G)MCH power supplies should be valid at least 1ms before PWROK assertion
3.
t2: (G)MCH clocks should be running and stable at least 1us before PWROK assertion
§
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External Design Specification
Absolute Maximum Ratings
10
Absolute Maximum Ratings
Table 20 specifies the Mobile Intel 965 Express Chipset family chipset’s absolute
maximum and minimum ratings. Within functional operation limits, functionality and
long-term reliability can be expected.
Caution:
At conditions outside functional operation condition limits, but within absolute
maximum and minimum ratings, neither functionality nor long-term reliability can be
expected. At conditions exceeding absolute maximum and minimum ratings, neither
functionality nor long-term reliability can be expected. If a device is returned to
conditions within functional operation limits after having been subjected to conditions
outside these limits, but within the absolute maximum and minimum ratings, the
device may be functional, but with its lifetime degraded.
Caution:
Although the (G)MCH contains protective circuitry to resist damage from static electric
discharge, precautions should always be taken to avoid high static voltages or electric
fields.
Table 20.
Absolute Maximum Ratings1 (Sheet 1 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
Tdie
Die Temperature under Bias
0
105
°C
1
Tstorage
Storage Temperature
-55
150
°C
2,3
VCC
1.05 V Core Supply Voltage with respect
to VSS
-0.3
1.155
V
VCC_AXG
1.05 V Graphics Voltage with respect to
VSS
-0.3
1.375
V
VCC_AXD
1.25 V DDR2 IO Voltage with Respect to
VSS
-0.3
1.375
V
VCC_AXM
1.05 Manageability engine Voltage with
respect to VSS
-0.3
1.155
V
(G)MCH
4
Host Interface
VTT (FSB Vccp)
1.05 V AGTL+ buffer DC Input Voltage
with respect to VSS
-0.3
1.32
V
VCC_AXF
1.25 V DC Input Voltage for AGTL+
buffer logic with respect to VSS
-0.3
1.375
V
DDR2 Interface (533 MTs/ /667 MTs)
VCC_SM
1.8 V DDR2 Supply Voltage with Respect
to Vss.
-0.3
2.1
V
VCC_SM_CK
1.8 V DDR2 Clock IO Voltage with
Respect to Vss.
-0.3
2.1
V
VCCA_SM
1.25 V DDR2 Voltage connects to IO logic
and DLLs with Respect to Vss.
-0.3
1.375
V
VCCA_SM_CK
1.25 V DDR2 Voltage for clock module to
avoid noise with Respect to Vss.
-0.3
1.375
V
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Absolute Maximum Ratings
Table 20.
Absolute Maximum Ratings1 (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
Notes
DMI /PCI Express Graphics/SDVO Interface
VCC_PEG
1.05 V PCI-Express Supply Voltage with
respect to VSS
-0.3
1.375
V
VCC_DMI
1.25 V DMI Terminal Supply Voltage with
respect to VSS
-0.3
1.375
V
VCCR_RX_DMI
1.05 V RX and IO Logic voltage for DMI
-0.3
1.375
V
VCCA_PEG_BG
3.3V Analog Band Gap Voltage with
respect to VSSA_PEG_BG
-0.3
3.63
V
Controller LINK
5
CRT DAC Interface (8 bit DAC)
VCCA_CRT_DAC
3.3 V DAC IO Supply Voltage
-0.3
3.63
V
VCC_SYNC
3.3 V CRT Sync Supply Voltage
-0.3
3.63
V
VCCD_QCRT
1.5 V CRT Quiet Digital Voltage
-0.3
1.65
V
VCCD_CRT
1.5 V CRT Level Shifter Supply
-0.3
1.65
V
-0.3
3.63
V
1.5 V TV Supply
-0.3
1.65
V
3.3 V TV Analog Supply
-0.3
3.63
V
HV CMOS Interface
VCC_HV
3.3 V Supply Voltage with respect to VSS
TV OUT Interface (10 bit DAC)
VCCD_TVDAC
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_DAC_BG
3.3 V TV DAC Band Gap voltage
-0.3
3.63
V
VCCD_QTVDAC
1.5 V Quiet Supply
-0.3
1.65
V
VCCD_LVDS
1.8 V LVDS Digital Power Supply
-0.3
1.98
V
VCC_TX_LVDS
1.8 V LVDS Data/Clock Transmitter
Supply Voltage with respect to VSS
-0.3
1.98
V
VCCA_LVDS
1.8 V LVDS Analog Supply voltage with
respect to VSS
-0.3
1.98
V
-0.3
1.375
V
LVDS Interface
PLL Analog Power Supplies
VCCA_HPLL,
VCCD_HPLL,
VCCA_MPLL,
VCCA_PEG_PLL,
1.25 V Power Supply for various PLL
VCCD_PEG_PLL
VCCA_DPLLA,
VCCA_DPLLB
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External Design Specification
Absolute Maximum Ratings
NOTES:
1.
Functionality is not guaranteed for parts that exceed Tdie temperature above 105 ºC. Tdie
is measured at top center of the package. Full performance may be affected if the on-die
thermal sensor is enabled.
2.
Possible damage to the (G)MCH may occur if the (G)MCH storage temperature exceeds
150 ºC. Intel does not guarantee functionality for parts that have exceeded temperatures
above 150 ºC due to spec violation.
3.
Storage temperature is applicable to storage conditions only. In this scenario, the device
must not receive a clock, and no pins can be connected to a voltage bias. Storage within
these limits will not affect the long-term reliability of the device. This rating applies to the
silicon and does not include any tray or packaging.
4.
Relevant for Controller Link as well.
5.
See VCC_AXD
10.1
Power Characteristics
Symbol
SKU
Core Voltage
TDP
Unit
Notes
Intel GM965 Express Chipset
(Render clock 400 MHz)
1.05 V
13.5
1.05 V
12
Intel GM965 Express Chipset
(Mini-note)
1.05 V
10.5
1.05 V
9.5
W
1
Intel GM965 Express Chipset
(sub-note)
1.05 V
8
1.05 V
<13.5
Max
Unit
Notes
0
105
°C
1
-55
150
°C
2,3
Intel GM965 Express Chipset
(Render clock 500 MHz)
TDP
Intel PM965 Express Chipset
Intel GL960 Express Chipset
(Sheet 1 of 3)
Symbol
Parameter
Tdie
Die Temperature under Bias
Tstorage
Storage Temperature
Signal Names
Min
Typ
(G)MCH
IVCC
1.05-V Core Supply Current
(External GFX)
1310.
mA
4, 6
IVCC
1.05-V Core Supply Current
(Integrated GFX)
1572.62
mA
4, 6
IVCC_AXG
1.05-V Graphics Core Supply
Current
7700
mA
4, 6
IVCC_AXM
1.05-V Manageability engine
Supply Current
540
mA
Host Interface
IVTT FSB at
533 MHz
VTT Supply Current (1.05 V)
700
mA
IVTT FSB at
667 MHz
VTT Supply Current (1.05 V)
770
mA
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Absolute Maximum Ratings
(Sheet 2 of 3)
Symbol
IVTT FSB at
800 MHz
Parameter
Signal Names
VTT Supply Current (1.05 V)
Min
Typ
Max
Unit
850
mA
1310
mA
Notes
DMI /PCI Express Graphics/SDVO Interface
IVCC_PEG
1.05-V PCI-Express Supply
Voltage with respect to VSS
IVCC_DMI
1.25-V DMI termination Supply
Voltage with respect to VSS
100
mA
IVCCR_RX_DMI
1.05-V IO Logic voltage for DMI
260
mA
IVCCA_PEG_BG
3.3-V Analog Band Gap Voltage
with respect to VSSA_PEG_BG
400
uA
4, 5, 9
Controller Link
IVCC_AXM
10
CRT DAC Interface (8 bit DAC)
IVCCA_CRT_DAC
3.3-V DAC IO Supply Voltage
70
mA
4, 9
IVCC_SYNC
3.3-V CRT Sync Supply Voltage
10
mA
4, 9
IVCCD_QCRT
1.5-V CRT Quiet Digital Voltage
0.5
mA
IVCCD_CRT
1.5-V CRT Digital Power Supply
60
mA
100
mA
4
60
mA
4, 9
mA
4, 9
5
mA
4
0.5
mA
HV CMOS Interface
IVCC_HV
3.3-V Supply Voltage with
respect to VSS
TV OUT Interface (10 bit DAC)
IVCCD_TVDAC
1.5-V TV Supply
IVCCA_TVA_DAC
IVCCA_TVB_DAC
IVCCA_TVC_DA
40
3.3-V TV Analog Supply
40
40
C
IVCCA_DAC_BG
3.3-V TV Analog Supply
IVCCD_QTVDAC
1.5-V Quiet Supply
LVDS Interface
IVCCD_LVDS
1.8-V LVDS Digital Power Supply
150
mA
IVCC_TX_LVDS
1.8-V LVDS Data/Clock
Transmitter Supply Voltage with
respect to VSS
100
mA
IVCCA_LVDS
1.8-V LVDS Analog Supply
voltage with respect to VSS
10
mA
50
mA
4
4
PLL Analog Power Supplies
IVCCA_HPLL
120
Host PLL Supply Current
VCCA_HPLL
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External Design Specification
Absolute Maximum Ratings
(Sheet 3 of 3)
Symbol
IVCCD_HPLL
IVCCA_DPLLA
Parameter
HPLL Supply Current for Digital
Interface
IVCCA_DPLLB
Display PLLA Supply Current
Display PLLB Supply Current
IVCCA_MPLL
Memory PLL Supply Current
IVCCA_PEG_PLL
IVCCD_PEG_PLL
Signal Names
Min
Typ
VCCD_HPLL
Max
Unit
Notes
250
mA
4
100
mA
4
150
mA
4
90
mA
4
VCCA_DPLLA
VCCA_DPLLB
VCCA_MPLL
VCCA_PEG_PLL
PEG PLL Supply current
VCCD_PEG_PLL
NOTES:
1.
This specification is the thermal design power and is the estimated maximum possible expected power
generated in a component by a realistic application. It is based on extrapolations in both hardware and
software technology over the life of the component. It does not represent the expected power generated
by a power virus. Studies by Intel indicate that no application will cause thermally significant power
dissipation exceeding this specification, although it is possible to concoct higher power synthetic workloads
that write but never read. Under realistic read/write conditions, this higher power workload can only be
transient and is accounted in the Icc (max) spec. Tdie is measured at the top center of the package.
2.
These current levels can happen simultaneously, and can be summed into one supply.
3.
These are pre-silicon estimates, subject to change without notice.
4.
Estimate is only for max current coming through the chipset’s supply balls.
5.
Rail includes PLL current.
6.
Includes Worst case Leakage.
7.
Calculated for highest stretch goal frequencies.
8.
Iccmax is determined on a per-interface basis, and all can not happen simultaneously.
9.
Iccmax number includes max current for all signal names listed in the table.
10.
See IVCC_AXDl
Table 21.
DDR2 (533 MTs/667 MTs) Power Characteristics
Symbol
Parameter
Min
Type
Max
Unit
IVCCSM
DDR2 System Memory Interface
(1.8 V, 533 MTs) Supply Current
1 Channel
1395
2 Channel
2700
IVCCSM
DDR2 System Memory Interface
(1.8 V, 667 MTs) Supply Current
1 Channel
1700
2 Channel
3300
IVCCSM_CK
DDR2 System Memory Interface Clock Supply
Current
200
mA
IVCCA_SM
(533MT/s)
1.25-V DDR2 IO logic and DLLs supply current
550
mA
1.25-V DDR2 IO logic and DLLs supply current
735
mA
IVCCA_SM_CK
1.25-V DDR2 supply current for clock module.
35
mA
ISUS_VCCSM
DDR2 System Memory interface (1.8V) Standby
supply current
5
mA
ISMVREF
DDR2 System Memory Interface Reference
Voltage (0.90-V) Supply Current
20
uA
IVCCA_SM
(667MT/s)
External Design Specification
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Notes
mA
mA
1
121
Absolute Maximum Ratings
Table 21.
DDR2 (533 MTs/667 MTs) Power Characteristics
Symbol
Parameter
Min
Type
Max
Unit
ISUS_SMVREF
DDR2 System Memory Interface Reference
Voltage (0.90-V) Standby Supply Current
10
uA
ITTRC
DDR2 System Memory Interface Resister
Compensation Voltage
(1.8-V) Supply Current
30
mA
ISUS_TTRC
DDR2 System Memory Interface Resister
Compensation Voltage
(1.8-V) Standby Supply Current
0
mA
Max
Unit
Notes
1
NOTES:
1.
Standby in Table 21 refers to system memory in Self Refresh during S3 (STR).
Table 22.
VCC Auxiliary Rail Power Characteristics
Symbol
Parameter
Min
Type
Notes
IVCC_AXD
Supply current for HSIO
515
mA
1,2
IVCC_AXF
Supply current FSB IO
495
mA
1
NOTES:
1.
Calculated for highest frequency of operation.
2.
Relevant for Controller Link as well.
10.2
Thermal Characteristics
The chipset is designed for operation at die temperatures between 0 °C and 105 °C. The
thermal resistance of the package is given in the following table.
Table 23.
Mobile Intel 965 Express Chipset Family Package Thermal Resistance
Parameter
Ψjt (°C/Watt)1
Θja
(°C/Watt)1
Airflow Velocity in Meters/Second
0 m/s (0 LFM)
1 m/s (200 LFM)
23.5 C/W
18.3 C/W
0.5 C/W
0.9 C/W
NOTES:
1.
Estimate
§
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Thermal Management
11
Thermal Management
System level thermal management requires comprehending thermal solutions for two
domains of operation:
1. Robust Thermal Solution Design: Proper system design should include
implementation of a robust thermal solution. The system’s thermal solution should
be capable of dissipating the platform’s TDP power while keeping all components
(particularly (G)MCH, for the purposes of this discussion) below the relevant
Tdie_max under the intended usage conditions. Such conditions include ambient air
temperature and available airflow inside the laptop.
2. Thermal Failsafe Protection Assistance: As a backup to the implemented thermal
solution, the system design should provide a method to provide additional thermal
protection for the components of concern (particularly (G)MCH, for purposes of this
discussion). The failsafe assistance mechanism is to help manage components from
being damaged by excessive thermal stress under situations in which the
implemented thermal solution is inadequate or has failed.
The (G)MCH provides two internal thermal sensors, plus hooks for an external thermal
sensor mechanism. These can be used for detecting the component temperature and
for triggering thermal control within the (G)MCH. The (G)MCH has implemented several
silicon level thermal management features that can lower both (G)MCH and DDR power
during periods of high activity. These features can help control temperature of the
(G)MCH and DDR and thus help prevent thermally induced component failures. These
features include:
• Memory throttling triggered by memory heating
• Memory throttling triggered by (G)MCH heating
• THRMTRIP# support
11.1
Internal Thermal Sensor
The (G)MCH incorporates two on-die thermal sensors for thermal management.
The thermal sensors may be programmed to cause hardware throttling and/or software
interrupts. Hardware throttling includes render and main memory programmable
throttling thresholds. Sensor trip points may also be programmed to generate various
interrupts including SCI, SMI, SERR, or an internal graphics interrupt.
11.1.1
Internal Thermal Sensor Operation
The internal thermal sensor reports five trip points: Aux0, Aux1, Aux2, Aux3, Hot and
Catastrophic trip points in the order of increasing temperature.
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Thermal Management
11.1.1.1
Trip Points
Aux0, 1, 2, 3 Temperature Trip Points
These trip points may be set dynamically if desired and provides an interrupt to ACPI
(or other software) when it is crossed in either direction. These auxiliary temperature
trip points do not automatically cause any hardware throttling but may be used by
software to trigger interrupts.
Hot Temperature Trip Point
This trip point is set at the temperature at which the MCH must start throttling. It may
optionally enable (G)MCH throttling when the temperature is exceeded. This trip point
may provide an interrupt to ACPI (or other software) when it is crossed in either
direction. Software could optionally set this as an "Interrupt when the temperature
exceeds this level" setting.
Catastrophic Trip Point
This trip point is set at the temperature at which the (G)MCH must be shut down
immediately without any software support. The Catastrophic trip point may be
programmed to generate an interrupt, enable throttling, or immediately shut down the
system (via Halt, or via THERMTRIP# assertion).
Crossing a trip point in either direction may generate several types of interrupts. Each
trip point has a register to select what type of interrupt is generated. Crossing a trip
point is implemented as edge detection, used to trigger the interrupts. Either edge
(i.e., crossing the trip point in either direction) generates the interrupt.
Recommended Programming for Available Trip Points
See BIOS SPEC for recommended Trip Point programming. Thermal Sensors are not
located in hotspot of (G)MCH. Thermal Sensors may be up to 4°C lower than maximum
Tj of (G)MCH. Trip Points should be set to account for temperature offset between
Thermal Sensors and maximum Tj hotspot and Thermal Sensor accuracy.
Aux Trip Points (0, 1, 2, 3) should be programmed for software and firmware
control via interrupts
HOT Trip Point should be set to throttle (G)MCH to avoid maximum Tj of 110°C.
Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of
130°C.
11.1.1.2
Thermal Sensor Accuracy
Thermal sensor accuracy for (G)MCH is ±8°C from approximately +80°C to Tj-max of
110°C. Temperature reading accuracy from Thermal sensor will degrade further with
junction temperatures below +80°C. Temperature readings from Thermal Sensor may
not be available below +40°C. (G)MCH may not operate above Tj-max of +110°C.
Software has the ability to program the Tcat, Thot, and Taux trip points, but these trip
points should be selected with consideration for the thermal sensor accuracy and the
quality of the platform thermal solution. Overly conservative (unnecessarily low) temperature settings may unnecessarily degrade performance due to frequent throttling,
while overly aggressive (dangerously high) temperature settings may fail to protect the
part against permanent thermal damage.
124
Intel Confidential
External Design Specification
Thermal Management
11.1.2
Sample Programming Model
Intel reference and driver code do not use the thermal sensor interrupts.
11.1.2.1
Setting Trip Point for Hot Temperature and Generating an SERR
Interrupt
• Program the Thermal Hot Temperature Setting Register (TSTTPA1.HTPS or
TSTTPA2.HTPS).
• In Thermal Sensor Control Register (TSC1 or TSC2), set thermal sensor enable bit
(TSE), and the hysteresis value (if applicable).
• In Thermal Error Command Register (TERRCMD), set the SERR on Hot Thermal
Sensor Event (bit 4).
• Program the global thermal interrupt enabling registers.
11.1.2.2
Temperature Rising above the Hot Trip Point
• The TIS[Hot Thermal Sensor Interrupt Event] is set when SERR interrupt is
generated.
• Clear this bit of the TIS register to allow subsequent interrupts of this type to get
registered.
• Clear the global thermal sensor event bit in the Error Status Register.
• In thermal sensor status register (TSS), the Hot Trip indicator (HTI) bit is set if this
condition is still valid by the time the software gets to read the register.
11.1.2.3
Determining the Current Temperature as Indicated by the
Thermometer
• In Thermal Sensor Control Register (TSC1), set thermal sensor enable bit (TSE),
and the hysteresis value (if applicable).
• Read the value in the Thermometer Reading Register (TR). Allow enough time for
the entire thermometer sequence to complete (less than 1.3msec= 512*256/100
MHz for hraw clock of 100 MHz) in 512 clock mode. Reading is not valid unless TSS
[Thermometer Output Valid] = 1.
11.1.3
Hysteresis Operation
• Hysteresis provides a small amount of positive feedback to the thermal sensor
circuit to prevent a trip point from flipping back and forth rapidly when the
temperature is right at the trip point.
• The digital hysteresis offset is programmable to be 0,1, 2…15, which corresponds
to an offset in the range of approximately 0 to 7°C.
External Design Specification
Intel Confidential
125
Thermal Management
11.2
Thermal Throttling Options
The (G)MCH have two independent mechanisms that cause system memory throttling.
• (G)MCH Thermal Management: This is to ensure that the chipset is operating within
thermal limits. The mechanism can be initiated by a thermal sensor (internal ) trip
or by virtual thermal sensor bandwidth measurement exceeding a programmed
threshold via a weighted input averaging filter.
• DRAM Thermal Management: This is to ensure that the dram chips are operating
within thermal limits. The (G)MCH can control the amount of (G)MCH - initiated
bandwidth per rank to a programmable limit via a weighted input averaging filter.
11.3
External Thermal Sensor Interface Overview
While it is possible for Intel to set throttling values which will minimally impact typical
application performance in a typical environment, due to the possibility that a bad
thermal platform solution can cause overheating of box skin temperature, and that
such a bad platform is unlikely to include external thermal sensors for its SO-DIMMS, it
become necessary for the customers to have a means to determine the settings for
their platforms throttling. This is further complicated by the fact that different
memory vendors will have varying thermal performance.
An external thermal sensor with a serial interface such as the National Semi LM77,
LM87 - or other - may be placed next to a SO- DIMM (or any other appropriate platform
location), or a remote Thermal Diode (see Maxim 6685) may be placed next to the SODIMM (or any other appropriate platform location) and connected to the external
Thermal Sensor.
The External Sensor can be connected to the ICH via the SMBus Interface to allow
programming and setup by BIOS software over the serial interface. The External
Sensor’s output should include at least one Active-Low Open-Drain signal indicating an
Over-Temp condition (e.g., LM77 T_CRIT# or INT# in comparator mode), which
remains asserted for as long as the Over-Temp Condition exists, and de-asserts when
Temperature has returned to within normal operating range. This External Sensor
output will be connected to the (G)MCH input (PM_EXT_TS#0) and will trigger a preset
Interrupt and/or Throttle on a level-sensitive basis. If the External Sensor has two trip
point outputs, the other can be connected to the (G)MCH PM_EXT_TS#1 input to
trigger a preset interrupt or throttle action.
Additional external Thermal Sensor’s outputs, for multiple sensors, can be wire-OR’d
together allow signaling from multiple sensors that are physically located separately.
Software can, if necessary, distinguish which SO-DIMM(s) is the source of the overtemp through the serial interface. However, since the SO-DIMM’s will be located on the
same Memory Bus Data lines, any (G)MCH-based Read Throttle will apply equally.
Note:
126
The use of external sensors that include an internal pull-up resistor on the open-drain
thermal trip output is discouraged; however it may be possible, depending on the size
of the pull-up and the voltage of the sensor.
Intel Confidential
External Design Specification
Thermal Management
Figure 21.
Platform External Sensor
External Pull-up R
is associated with
the voltage rail of
the MCH Input
CPU
V
R
PM_EXT_TS
(G)MCH
THERM#
SO-DIMMs
TS
TS
ICH
SMBdata
SMBclock
11.4
THERMTRIP# Operation
Assertion of the (G)MCH’s THERMTRIP# (Thermal Trip) indicates that its junction
temperature has reached a level beyond which damage may occur. Upon assertion of
THERMTRIP#, the (G)MCH will shut off its internal clocks (thus halting program
execution) in an attempt to reduce the core junction temperature. Once activated,
THERMTRIP# remains latched until RSTIN# is asserted.
§
External Design Specification
Intel Confidential
127
Thermal Management
128
Intel Confidential
External Design Specification
DC Characteristics
12
DC Characteristics
12.1
I/O Buffer Supply Voltages
The I/O buffer supply voltage is measured at the (G)MCH package pins. The tolerances
shown in Table 25 are inclusive of all noise from DC up to 20 MHz. In the lab, the
voltage rails should be measured with a bandwidth limited oscilloscope with a roll off of
3 dB/decade above 20 MHz under all operating conditions. Table 25 indicates which
supplies are connected directly to a voltage regulator or to a filtered voltage rail.
For voltages that are connected to a filter, they should me measured at the input of the
filter. If the recommended platform decoupling guidelines cannot be met, the system
designer will have to make tradeoffs between the voltage regulator output DC tolerance
and the decoupling performance of the capacitor network to stay within the voltage
tolerances listed below.
12.2
Signal Groups
The following notations are used to describe the signal types:
Notations
I
Signal Type
Input pin
O
Output pin
I/O
Bi-directional Input/Output pin
The signal description includes the type of buffer used for the particular signal.
Signal
Description
AGTL+
Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for
complete details. The (G)MCH integrates AGTL+ termination resistors, and
supports Vtt from 0.83 V to 1.65 V (including guardbanding)
PCI Express*
PCI Express interface signals. These signals are compatible with PCI Express
1.0. Signaling Environment AC Specifications. The buffers are not 3.3 V
tolerant. Refer to the PCI Express specification.
CMOS
CMOS buffers. 1.5 V tolerant.
HVCMOS
High Voltage CMOS buffers. 3.3 V tolerant.
LVCMOS
Low Voltage CMOS buffers. Vtt tolerant
COD
CMOS Open Drain buffers. 3.3 V tolerant
SSTL-1.8
Stub Series Termination Logic: These are 1.8 V capable buffers. 1.8 V tolerant
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
LVDS
Low Voltage Differential signal interface
Ref
Voltage reference signal
External Design Specification
Intel Confidential
129
DC Characteristics
Table 24.
Signal
Group
Signal Groups (Sheet 1 of 4)
Signal Type
Signals
Notes
Host Interface Signal Groups
(a)
(b)
(c)
(d)
(e)
I/O
AGTL+
O
AGTL+
O
LVCMOS
I
AGTL+
I
A
I/O
A
H_ADS#, H_BNR#, H_BREQ#,H_DBSY#, H_DRDY#,
H_DINV#[3:0], H_A#[35:3], H_ADSTB#[1:0],
H_D#[63:0],H_DSTBP#[3:0], H_DPWR#,
H_DSTBN#[3:0], H_HIT#, H_HITM#, H_REQ#[4:0]
H_BPRI#, H_CPURST#, H_DEFER#, H_TRDY#,
H_RS#[2:0], THERMTRIP#
H_CPUSLP
H_LOCK#
H_AVREF, H_DVREF, H_SWING
H_RCOMP, H_SCOMP, H_SCOMP#
Serial DVO or PCI-Express Graphics Interface Signal Groups
PCI-E GFX Interface: PEG_RX[15:0], PEG_RX#[15:0]
(f)
I
PCI Express
SDVO Interface: SDVO_TVCLKIN#, SDVO_TVCLKIN, ,
SDVO_INT, SDVO_INT#, SDVO_FLD_STALL#,
SDVO_FLD_STALL
Refer to EDS for
SDVO & PCI
Express GFX Pin
Mapping
PCI-E GFX Interface: PEG_TX[15:0], PEG_TX#[15:0]
(g)
(h)
O
PCI Express
SDVO Interface: SDVOB_RED#, SDVOB_RED,
SDVOB_GREEN#, SDVOB_GREEN, SDVOB_BLUE#,
SDVOB_BLUE, SDVOB_CLK, SDVOB_CLK#,
SDVOC_RED#/SDVOB_ALPHA#, SDVOC_RED/
SDVOB_ALPHA, SDVOC_GREEN#, SDVOC_GREEN,
SDVOC_BLUE#, SDVOC_BLUE, SDVOC_CLK,
SDVOC_CLK#
I
PEG_COMPO
A
PEG_COMPI
Refer to EDS for
SDVO & PCI
Express GFX Pins
Mapping
Analog
PCI-E GFX/SDVO
I/F Compensation
Signals
DDR2 Interface Signal Groups
(l)
130
I/O
SSTL-1.8
SA_DQ[63:0], SB_DQ[63:0]
SA_DQS[7:0], SB_DQS[7:0], SA_DQS[7:0]#,
SB_DQS#[7:0]
Intel Confidential
External Design Specification
DC Characteristics
Table 24.
Signal
Group
(j)
Signal Groups (Sheet 2 of 4)
Signal Type
Signals
O
SA_DM[7:0], SB_DM[7:0], SA_MA[14:0], SB_MA[14:0],
SA_BS[2:0], SB_BS[2:0], SA_RAS#, SB_RAS#,
SA_CAS#, SB_CAS#, SA_WE#, SB_WE#, SM_ODT[3:0],
SM_CKE[3:0], M_CS#[3:0],
SSTL-1.8
Notes
SM_CK[1:0], SM_CK#[1:0], SM_CK[4:3], SM_CK#[4:3]
I
SSTL-1.8
(k)
I
A
SA_RCVEN#, SB_RCVEN#
SM_VREF
LVDS Signal Groups
(l)
(m)
O
LVDS
I/O
Ref
I
Ref
LVDSA_DATA[3:0], LVDSA_DATA#[3:0], LVDSA_CLK,
LVDSA_CLK#, LVDSB_DATA[3:0], LVDSB_DATA#[3:0],
LVDSB_CLK, LVDSB_CLK#
LVDS_IBG
LVDS_VBG, LVDS_VREFH, LVDS_VREFL
CRT DAC Signal Groups
(n)
(o)
(p)
O
A
O
A
O
HVCMOS
CRT_RED, CRT_RED#, CRT_GREEN, CRT_GREEN#,
CRT_BLUE, CRT_BLUE#
Refer to CRT/
Analog VESA spec
& EDS
CRT_TVO_IREF
Current Mode
Reference pin. DC
Spec. not required
CRT_HSYNC, CRT_VSYNC
Refer to CRT/
Analog VESA spec
& EDS
TV DAC Signal Groups
(q)
O
A
O
HVCMOS
(ae)
TV DAC Band Gap
and Channel Supply
TVA_DAC, TVB_DAC, TVC_DAC, TVA_RTN, TVB_RTN,
TVC_RTN
TV_DCONSEL[1:0]
VCCA_TVA_DAC,VCCA_TVB_DAC, VCCA_TVC_DAC,
VCCA_DAC_BG
Clocks, Reset, and Miscellaneous Signal Groups
(s)
(t)
(u)
HVCMOS Input
Low Voltage Diff.
Clock Input
O
HVCMOS
External Design Specification
PM_EXT_TS[1:0]#,
HCLKP(BCLK0/BCLK), HCLKN(BCLK1/BCLK#),
DREF_CLKP, DREF_CLKN, DREF_SSCLKP, DREF_SSCLKN,
GCLKP, GCLKN
L_VDD_EN, L_BKLT_EN, L_BKLT_CRTL, CLK_REQ#,
ICH_SYNC#
Intel Confidential
131
DC Characteristics
Table 24.
Signal
Group
(ua)
(v)
(va)
Signal Groups (Sheet 3 of 4)
Signal Type
O
A
I
HVCMOS
I/O
COD
I
Diff Clk
(w)
(x)
(xa)
AGTL+ input/output
I
HVCMOS
I
LVCMOS
Signals
Notes
GFX_VID[3:0], GFX_VR_EN
PMSYNC# (PM_BM_BUSY#)
CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK,
L_DDC_DATA, SDVO_CTRL_CLK, SDVO_CTRL_DATA,
L_CRTL_CLK, L_CRTL_DATA
DDC and GMBUS
support signals
DPLL_REF_CLK, DPLL_REF_CLK#, DPLL_REF_SSCLK,
DPLL_REF_SSCLK#, HPLL_CLK, HPLL_CLK#, PEG_CLK,
PEG_CLK#
PLL Signals
CFG[17:3]
RSTIN#, PWROK, CFG[20:18], H_BSEL[2:0] / CFG[2:0],
PM_EXT_TS#[1:0, TEST1, TEST2
PM_DPRSTP#
I/O Buffer Supply Voltages
(y)
AGTL+ Termination
Voltage
VTT (Vccp)
(z)
SDVO, DMI, PCI
Express GFX
Voltages
VCC3G, VCCA_3GBG
(aa)
1.8V DDR2 Supply
Voltage
VCCSM
(ab)
(G)MCH Core
VCC
(ac)
HV Supply Voltage
VCCHV
(ad)
TV DAC Supply
Voltage
VCCD_TVDAC, VCCDQ_TVDAC
(ae)
TV DAC Band Gap
and Channel Supply
VCCA_TVDACA,VCCA_TVDACB, VCCA_TVDACC
(af)
CRT DAC Supply
Voltage
VCCA_CRTDAC, VCCDQ_CRT, VCCD_CRT, VCC_SYNC
(ag)
PLL Supply Voltages
VCCA_HPLL, VCCA_MPLL, VCCD_HMPLL VCCA_3GPLL,
VCCA_DPLLA, VCCA_DPLLB
(ah)
1.8 V LVDS Digital
Supply
VCCD_LVDS
(ai)
1.8 V LVDS Data/
clock Transmitter
Supply
VCCTX_LVDS
(aj)
1.8 V LVDS Analog
Supply
VCCA_LVDS
(ak)
1.25V Power Supply
for DDR2 DLL,
DDR2 IO and FSB
IO
VCC_AXD and VCC_AXF
132
Intel Confidential
External Design Specification
DC Characteristics
Table 24.
Signal Groups (Sheet 4 of 4)
Signal
Group
Signal Type
Signals
Notes
Controller Link signals
(al)
VCC-independent
CMOS I/O
(al)
HVCMOS Input
CL_PWROK
(al)
CMOS Input
CL_RST#,
(al)
Analog Input
CL_VREF
CL_DATA, CL_CLK,
12.3
General DC Characteristics
Table 25.
DC Characteristics (Sheet 1 of 6)
Signal
Group
Min
Nom
Max
Unit
1.05-V Host AGTL+
Termination Voltage
0.9975
1.05
1.1025
V
1.25-V DC Input Voltage
for AGTL+ IO Logic
1.1875
1.25
1.3125
V
1.05-V (G)MCH Core
Supply Voltage
0.9975
1.05
1.1025
V
VCC_AXG
1.05-V Graphics Voltage
0.9975
1.05
1.1025
V
VCC_AXM
1.05-V Intel
Management Engine
Voltage
0.9975
1.05
1.1025
V
DDR2 I/O Supply
Voltage
1.7
1.8
1.9
V
1.8-V DDR2 Clock IO
Voltage
1.7
1.8
1.9
V
Symbol
Parameter
Notes
I/O Buffer Supply Voltage
VTT
(y)
VCC_AXF
VCC
VCC_SM
(ab)
(aa)
VCC_SM_CK
VCCA_SM
1.25-V DDR2 Voltage
connects to IO logic and
DLLs
1.1875
1.25
1.3125
V
VCC_AXD
1.25-V DDR2 High
speed IO Logic Voltage
and Controller Link IO
1.1875
1.25
1.3125
V
1.25-V DDR2 IO logic
Voltage for SM clocks
1.1875
1.25
1.3125
V
1.05-V PCI-Express
Supply Voltage
0.9975
1.05
1.1025
V
VCC_DMI
1.25-V TX Analog and
Term Voltage for DMI
1.1875
1.25
1.3125
V
VCCR_RX_DMI
1.05-V Rx and I/O Logic
for DMI
0.9975
1.05
1.1025
V
VCCA_SM_CK
VCC_PEG
(z)
External Design Specification
Intel Confidential
16
1
133
DC Characteristics
Table 25.
DC Characteristics (Sheet 2 of 6)
Symbol
Signal
Group
VCCA_PEG_BG
Parameter
Min
Nom
Max
Unit
Notes
3.3-V Analog Band Gap
Voltage
3.135
3.3
3.465
V
1
VCCHV
(ac)
HV CMOS Supply
Voltage
3.135
3.3
3.465
V
VCCD_TVDAC
(ad)
TV DAC Supply Voltage
1.425
1.5
1.575
V
VCCD_QTVDAC
(ad)
TV DAC Quiet Supply
Voltage
1.425
1.5
1.575
V
1
VCCA_TVA_DAC
VCCA_TVB_DAC
VCCA_TVC_DAC
VCCA_DAC_BG
(ae)
TV DAC Analog & Band
Gap Supply Voltage
3.135
3.3
3.465
V
1
VCCA_CRT_DAC
(af)
CRT DAC Supply Voltage
3.135
3.3
3.465
V
1
(af)
CRT DAC SYNC Supply
Voltage
3.135
3.3
3.465
V
VCCD_QCRT
1.5-V CRT Quiet Digital
Voltage
1.425
1.5
1.575
VCCD_CRT
1.5-V CRT Digital Power
Supply
1.425
1.5
1.575
VCC_SYNC
1
VCCA_HPLL,
VCCA_MPLL,
VCCD_HPLL,
(ag)
Various PLLS Analog
Supply Voltages
1.1875
1.25
1.3125
V
VCCD_LVDS
(ah)
Digital LVDS Supply
Voltage
1.7
1.8
1.9
V
VCC_TX_LVDS
(ai)
Data/Clock Transmitter
LVDS Supply Voltage
1.7
1.8
1.9
V
1
VCCA_LVDS
(aj)
Analog LVDS Supply
Voltage
1.7
1.8
1.9
V
1
H_VREF
(e)
Host Address and Data
Reference Voltage
2/3 x VTT
– 1%
2/3 x
VTT
2/3 x VTT
+ 1%
V
H_SWING
(e)
Host Compensation
Reference Voltage
0.3125x
VTT – 1%
0.3125
x VTT
0.3125x
VTT + 1%
V
SM_VREF
(k)
DDR2 Reference Voltage
0.49 x
VCCSM
0.50 x
VCCSM
0.51 x
VCCSM
V
VCCA_PEG_PLL
VCCD_PEG_PLL
1
VCCA_DPLLA,
VCCA_DPLLB
Reference Voltages
Host Interface
VIL_H
(a,d,w)
Host AGTL+ Input Low
Voltage
-0.10
0
(2/3 x VTT)
– 0.1
V
VIH_H
(a,d,w)
Host AGTL+ Input High
Voltage
(2/3 x VTT)
+ 0.1
VTT
(1.05)
VTT + 0.1
V
134
Intel Confidential
External Design Specification
DC Characteristics
Table 25.
DC Characteristics (Sheet 3 of 6)
Signal
Group
Parameter
VOL_H
(a,b,w)
Host AGTL+ Output Low
Voltage
VOH_H
(a,b,w)
Host AGTL+ Output
High Voltage
IOL_H
(a,b,w)
Host AGTL+ Output Low
Current
ILEAK_H
(a,d,w)
Host AGTL+ Input
Leakage Current
CPAD
(a,d,w)
Host AGTL+ Input
Capacitance
VOL_H
(c)
CMOS Output Low
Voltage
VOH_H
(c)
CMOS Output High
Voltage
VIL(DC)
(l)
DDR2 Input Low Voltage
VIH(DC)
(l)
DDR2 Input High
Voltage
VIL(AC)
(i)
DDR2 Input Low Voltage
VIH(AC)
(i)
DDR2 Input High
Voltage
VOL
(i, j)
DDR2 Output Low
Voltage
VOH
(i, j)
DDR2 Output High
Voltage
ILeak
(i)
Input Leakage Current
CI/O
(i, j)
DDR2 Input/Output Pin
Capacitance
Symbol
Min
Nom
VTT-0.1
1.2
0.9VTT
Max
Unit
Notes
0.3125 x
VTT) + 0.1
V
VTT
V
VTTmax /
(Rtermmin
- Rpdmin)
mA
±10
uA
2.5
pF
0.1 VTT
V
IOL =
1 mA
VTT
V
IOH =
1 mA
SM_VREF –
0.125
V
5
DDR2 Interface
SM_VREF
+ 0.125
V
SM_VREF –
0.250
SM_VREF
+ 0.250
V
V
0.3
1.5
1.0
V
2
V
2
±10
uA
4.0
pF
1.2
V
3, 4
20
mV
3
V
3, 4
1.05 V PCI Express Interface 1.1 (includes PCI Express GFX and SDVO)
VTX-DIFF P-P
(f, g)
Differential Peak to Peak
Output Voltage
VTX_CM-ACp
(f, g)
AC Peak Common Mode
Output Voltage
ZTX-DIFF-DC
(f, g)
DC Differential TX
Impedance
VRX-DIFF p-p
(f, g)
Differential Input Peak
to Peak Voltage
External Design Specification
0.400
80
0.175
Intel Confidential
100
120
1.2
135
DC Characteristics
Table 25.
Symbol
VRX_CM-ACp
DC Characteristics (Sheet 4 of 6)
Signal
Group
(f, g)
Parameter
Min
Nom
AC peak Common Mode
Input Voltage
Max
Unit
150
mV
0.8
V
±10
μA
6.0
pF
Notes
Clocks, Reset, and Miscellaneous Signals
VIL
(s)
Input Low Voltage
VIH
(s)
Input High Voltage
ILEAK
(s)
Input Leakage Current
CIN
(s)
Input Capacitance
3.0
VIL
(t)
Input Low Voltage
-0.3
VIH
(t)
Input High Voltage
VCROSS
(t)
Crossing Voltage
ΔVCROSS
(t)
Range of Crossing Points
VSWING
(t)
Differential Output
Swing
ILEAK
(t)
Input Leakage current
CPAD
(t)
pad Capacitance
VOL
(u)
Output Low Voltage
(CMOS Outputs)
VOH
(u)
Output High Voltage
(CMOS Outputs)
IOL
(u)
Output Low Current
(CMOS Outputs)
IOH
(u)
Output High Current
(CMOS Outputs)
2.0
V
0.300
NA
NA
V
5, 13,
14
1.15
V
5, 12,
13
0.550
V
6, 11,
15
0.140
V
6, 11,
9
V
5, 10
+5
μA
5, 7
1.45
pF
5, 8
0.4
V
0.300
-5
0.95
1.2
2.8
V
1
-1
mA
mA
VIL
(v)
Input Low Voltage (DC)
VIH
(v)
Input High Voltage (DC)
ILEAK
(v)
Input Leakage Current
±10
uA
CIN
(v)
Input Capacitance
10
pF
0.8
1.55
@VOL_
max
HI
@VOH_
HI min
V
V
VIL
(x)
Input Low Voltage
VIH
(x)
Input High Voltage
ILEAK
(x)
Input Leakage Current
±10
CIN
(x)
Input Capacitance
10
pF
450
mV
0.8
2.0
V
V
μA
LVDS Interface: Functional Operating Range (VCC=1.8 V±5%)
VOD
136
(l)
Differential Output
Voltage
250
Intel Confidential
350
17
External Design Specification
DC Characteristics
Table 25.
DC Characteristics (Sheet 5 of 6)
Symbol
Signal
Group
Parameter
ΔVOD
(l)
Change in VOD between
Complementary Output
States
VOS
(l)
Offset Voltage
ΔVOS
(l)
Change in VOS between
Complementary Output
States
IOs
(l)
Output Short Circuit
Current
IOZ
(l)
Output TRI-STATE
Current
Min
1.125
Nom
Max
Unit
Notes
50
mV
17
1.375
V
17
50
mV
17
-3.5
-10
mA
17
±1
±10
μA
17
0.277
V
1.25
Controller Link
VIL
(al)
Input Low Voltage
VIH
(al)
Input High Voltage
ILEAK
(al)
Input Leakage Current
± 20
μA
CIN
(al)
Input Capacitance
2.0
pF
IOL
(al)
Output Low Current
(CMOS Outputs)
1.0
mA
IOH
(al)
Output High Current
(CMOS Outputs)
VOL
(al)
Output Low Voltage
(CMOS Outputs)
VOH
(al)
Output High Voltage
(CMOS Outputs)
0.427
V
6
mA
0.06
0.6
@VOL_
max
HI
@VOH_
HI min
V
V
SDVO_CTRLDATA, SDVO_CTRLCLK
VIL
Input Low Voltage
VIH
Input High Voltage
0.75
ILEAK
Input Leakage Current
± 10
μA
CIN
Input Capacitance
10.0
pF
VOL
Output Low Voltage
0.4
V
1.75
V
V
CRT_DDC_DATA, CRT_DDC_CLK, L_DDC_CLK, L_DDC_DATA, L_CRTL_CLK, L_CTRL_DATA,
TV_DCONSEL_0, TV_DCONSEL_1, CLKREQ#
VIL
Input Low Voltage
VIH
Input High Voltage
ILEAK
Input Leakage Current
± 10
μA
CIN
Input Capacitance
10.0
pF
VOL
Output Low Voltage
0.4
V
External Design Specification
0.9
2.1
Intel Confidential
V
V
137
DC Characteristics
Table 25.
DC Characteristics (Sheet 6 of 6)
Symbol
Signal
Group
Parameter
Min
Nom
Max
Unit
Notes
L_VDDEN, L_BKLTEN, L_BKLTCTL, DFGT_VID[3:0], DFGT_VR_EN
VIL
Input Low Voltage
VIH
Input High Voltage
0.9
ILEAK
Input Leakage Current
± 10
μA
CIN
Input Capacitance
10.0
pF
VOL
Output Low Voltage
(CMOS Outputs)
0.4
V
VOH
Output High Voltage
(CMOS Outputs)
2.1
V
V
2.7
V
CFG_RSVD[2:0], DPRSLPVR, PM_EXTTS#[1:0]
VIL
Input Low Voltage
0.9
V
VIH
Input High Voltage
ILEAK
Input Leakage Current
± 10
μA
CIN
Input Capacitance
10.0
pF
0.3VCC
V
2.1
V
PM_DPRSTP# VCC = 1.05V
VIL
Input Low Voltage
VIH
Input High Voltage
ILEAK
Input Leakage Current
± 10
μA
CIN
Input Capacitance
10.0
pF
0.7VCC
V
NOTES:
1.
Refer to the platform design guidelines filter recommendations for these rails.
2.
Determined with 2x (G)MCH DDR2 buffer strength settings into a 50 Ω to 0.5xVCCSM (DDR2) test load.
3.
Specified at the measurement point into a timing and voltage compliance test load as shown in Transmitter
compliance eye diagram of PCI Express specification and measured over any 250 consecutive TX Ul's.
Specified at the measurement point and measured over any 250 consecutive ULS. The test load shown in
receiver compliance eye diagram of PCI Express specification. Should be used as the RX device when taking
measurements.
4.
For low voltage PCI Express (PCI Express Graphics/SDVO) interface:
Symbol
5.
6.
7.
8.
9.
10.
11.
12.
138
Parameter
Min
Typ
Max
Unit
RTT
Termination
Resistance
50
55
61
Ω
RCN
Buffer On
Resistance
22
25
28
Ω
Unless otherwise noted, all specifications in this table apply to all FSB frequencies.
Crossing Voltage is defined as absolute voltage where rising edge of BCLK0 is equal to the falling edge of
BCLK1.
For Vin between 0 V and VH.
Cpad includes die capacitance only. No package parasitics are included.
ΔVCROSS is defined as the total variation of all crossing voltages as defined in note 6.
Measurement taken from differential waveform.
Measurement taken from single-ended waveform.
“Steady state” voltage, not including Overshoots or Undershoots.
Intel Confidential
External Design Specification
DC Characteristics
13.
14.
15.
16.
17.
The max voltage including overshoot.
The min voltage including undershoot.
Only applies to the differential rising edge (Clock rising and Clock# falling).I
If a variable VRM is used the VCC_AXG should be ±5% of the nominal setting (the setting shown is of
1.05 V).
All LVDS active lanes must be terminated with 100-Ω resistors for correct Vos performance and
measurement.
12.4
CRT DAC DC Characteristics
Table 26.
CRT DAC DC Characteristics: Functional Operating Range
(VCCADAC = 3.3 V ±5%)
Parameter
Min
Typical
DAC Resolution
Max Luminance (full-scale)
Max
8
0.665
0.700
Min Luminance
LSB Current
Units
Notes
Bits
0.770
(1) Measured at Low Frequency
V
(2, 4, 5) white video level voltage
0.000
V
(3) Measured at DC. Black video level
voltage
73.2
uA
(4, 5)
Integral Linearity (INL)
-1.0
+1.0
LSB
(6)
Differential Linearity (DNL)
-1.0
+1.0
LSB
(6)
6
%
(7)
Video channel-channel voltage
amplitude mismatch
Monotonicity
Guaranteed
NOTES:
1.
Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of Analog Display
Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2.
Max steady-state amplitude
3.
Min steady-state amplitude
4.
Defined for a double 75-Ω termination.
5.
Set by external reference resistor value.
6.
INL and DNL measured and calculated according to VESA video signal standards.
7.
Max full-scale voltage difference among R,G,B outputs (percentage of steady-state full-scale voltage).
12.5
TV DAC DC Characteristics
Table 27.
TV DAC DC Characteristics: Functional Operating Range
(VCCATVDAC [A,B,C] = 3.3 V +/- 5%) (Sheet 1 of 2)
Parameter
Min
DAC Resolution
Typi
cal
Max
10
Units
Bits
Measured at low-frequency
Bits
@ NTSC/PAL Video BW
ENOB (Effective Number of Bits)
7.5
Max Luminance (full-scale)
1.235
1.3
1.365
V
Max Luminance (full-scale)
1.045
1.1
1.155
V
External Design Specification
Intel Confidential
Notes
For composite video signal
Note: 1,3,4
For S-Video signal
Note: 1,3,4
139
DC Characteristics
Table 27.
TV DAC DC Characteristics: Functional Operating Range
(VCCATVDAC [A,B,C] = 3.3 V +/- 5%) (Sheet 2 of 2)
Parameter
Min
Typi
cal
Max
Units
Notes
For component video signal
Max Luminance (full-scale)
0.665
0.7
0.735
V
Min Luminance
-0.1
0
+0.1
mV
Measured at DC, Note: 2
Integral Linearity (INL)
-2.5
+2.5
LSB
Note: 5
Differential Linearity (DNL)
-0.5
+0.5
LSB
Note: 5
SNR
48
dB
RMS @ NTSC/PAL Video BW
Video channel-channel voltage
amplitude mismatch
-3
%
Note: 6
Monotonicity
Guaranteed
+3
Note: 1,3,4
NOTES:
1.
Max steady-state amplitude
2.
Min steady-state amplitude
3.
Defined for a double 75-Ω termination.
4.
Set by external reference resistor value.
5.
INL and DNL measured and calculated based on the method given in VESA video signal standards.
6.
Max full-scale voltage difference among the outputs (percentage of steady-state full-scale voltage).
§
140
Intel Confidential
External Design Specification
AC Characteristics
13
AC Characteristics
This section documents the (G)MCH AC characteristics.
• Clocks
• Host interface
• DDR2 interface
• PCI Express interface (PCI Express Graphics, SDVO)
• LVDS interface
• CRT DAC interface
• TV DAC interface
• Controller Link
The subsequent sections will document the AC characteristics for these interfaces.
These specifications should be used in conjunction with the Intel® 965 Express Chipset
family I/O buffer models provided by Intel. Layout guidelines are also available in the
platform design guide.
13.1
Input Clock AC Characteristics
The specifications below are taken from the CK505 Clock Synthesizer / Driver
Specification document. These specifications are valid at the pad of the (G)MCH.
Ledges on the clock signals will be observed if measuring the clocks at the pins of the
(G)MCH, since the clocks rely on reflective switching. Refer to Figure 22 or
measurement points on the waveform.
Parameter
Min
Nom
Max
Unit
MHz
Figures
Notes
Figure 22
1,5,6
Differential Host Clock at frequency of 133 MHz
BCLK[1:0] Frequency
132.64
133.33
133.45
BCLK[1:0] Period
7.4993
7.500
7.5384
ns
150
ps
BCLK[1:0] Period Stability
2,3
BCLK[1:0] Duty Cycle
40
60
%
Figure 22
6
BCLK[1:0] Rise and Fall Slew
Rate
2.5
8
V/ns
Figure 22
6,8
20
%
Slew Rate Matching
9,10
Differential Host Clock at frequency of 166 MHz
BCLK[1:0] Frequency
165.82
166.66
166.68
MHz
BCLK[1:0] Period
5.9994
6
6.0307
ns
150
ps
BCLK[1:0] Period Stability
Figure 22
1,5,6
2,3
BCLK[1:0] Duty Cycle
40
60
%
Figure 22
6
BCLK[1:0] Rise and Fall Slew
Rate
2.5
8
V/ns
Figure 22
6,8
External Design Specification
Intel Confidential
141
AC Characteristics
Parameter
Min
Nom
Slew Rate Matching
Max
Unit
20
%
Figures
Notes
9,10
Differential Host Clock at frequency of 200 MHz
BCLK[1:0] Frequency
199.98
200
200.19
MHz
BCLK[1:0] Period
4.9995
5
5.0256
ns
150
ps
BCLK[1:0] Period Stability
Figure 22
1,5,6
2,3
BCLK[1:0] Duty Cycle
40
60
%
Figure 22
6
BCLK[1:0] Rise and Fall Slew
Rate
2.5
8
V/ns
Figure 22
6,8
20
%
Slew Rate Matching
9,10
Differential PCI Express* Clock at frequency of 100 MHz
GCLK[P:N] Frequency
GCLK[P:N] Period
99.49
100
100.09
MHz
9.9991
10
10.0512
ns
150
ps
8
V/ns
GCLK[P:N] Period Stability
GCLK[P:N] Rise and Fall Slew
Rate
2.5
Figure 22
1,5,6
2,3
Figure 22
6, 8
Figure 22
1,5,6
Display PLLA, PLLB Differential Clock at frequency of 96 MHz
DREF_CLK[P:N] Frequency
DREF_CLK[P:N] Period
95.99
96
96.009
MHz
10.4156
10.4167
10.4177
ns
250
ps
8
V/ns
DREF_CLK[P:N] Period
Stability
DREF_CLK[P:N] Rise and Fall
Slew Rate
2.5
2,3
Figure 22
6, 8
Figure 22
1,5,6
Display PLLA, PLLB Differential Clock at frequency of 100 MHz (w/ SSC)
DREF_CLK[P:N] Frequency
DREF_CLK[P:N] Period
95.238
100
102.564
MHz
9.75
10
10.5
ns
250
ps
8
V/ns
DREF_CLK[P:N] Period
Stability
DREF_CLK[P:N] Rise and Fall
Slew Rate
2.5
2,3
Figure 22
6, 8
NOTES:
1.
The period specified here is the average period. A given period may vary from this specification as
governed by the period stability specification. Min period specification is based on –300-ppm deviation
from the ideal period. Max period specification is based on the summation of +300-ppm deviation from
the ideal period and a +5% max variance due to spread spectrum clocking. Ideal periods for the various
clocks are derived using 96 MHz, 100 MHz, 200 MHz and 266.6 MHz respectively.
2.
For the clock jitter specification, refer to the CK505 Clock Synthesizer/Driver Specification.
3.
In this context, period stability is defined as the worst-case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
4.
Rise and fall times are measured single-ended between 300 mV and 550 mV on the rising and falling edges
of the clock.
142
Intel Confidential
External Design Specification
AC Characteristics
5.
The average period over any 1 us period of time must be greater than the minimum and less than the
maximum specified period.
Measurement taken from differential waveform.
DOT100 SSC calculations assume maximum down-spread SSC of 2.5%.
Slew rate is measured through the VSWING voltage range centered about differential zero.
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a ±75mV window centered on the average cross point where Clock rising meets Clock# falling. The median cross
point is used to calculate the voltage thresholds
Measurement taken from single-ended waveform.
6.
7.
8.
9.
10.
13.2
Host Interface Timing
The clock to output valid delays for the host interface are specified into a 55-W load
and measured at the die pad, unless otherwise specified. The reference point for all
system bus AC timing measurements is 2/3xVTT.
Table 28.
Host Interface AC Characteristics for 533MHz
Symbol
Parameter
Min
Nom
Max
Unit
Figures
Notes
Common Clock
TCO
Output Valid Delay
0.075
ns
Figure 24
1
TSU
Input Setup Time
0.469
0.975
ns
Figure 24
1
TH
Input Hold Time
0.277
ns
Figure 24
1
Transmitter Address Timing
BCLK Rising to Valid Address Delay
0.075
TAvb
TAco
Address Output Valid before
1.711
0.975
ns
ns
Figure 26
Figure 26
TAva
Address Output Valid after
1.706
ns
Figure 26
Transmitter Data Timing
TDco
BCLK Rising to Valid Data Delay
0.075
ns
Figure 28
TDvb
Data Output Valid before
0.773
ns
Figure 28
TDva
Data Output Valid after
0.767
ns
Figure 28
0.975
Receiver Address Timing
TAsu
Address Input Setup Time
0.180
ns
Figure 28
TAh
Address Hold Time
0.180
ns
Figure 28
Receiver Data Timing
TDsu
Data Input Setup Time
0.180
ns
TDh
Data Hold Time
0.180
ns
NOTES:
1.
Common Clock AGTL+ signals are referenced to the rising edge of BCLK0.
2.
Since the (G)MCH chipset core is running at 133 MHz, the I/O buffer receives the data at the rate of
533 MHz from the processor and is latched by the corresponding strobes. In addition, because the (G)MCH
chipset core is running at 166 MHz, data transfer from I/O to core takes place at the 133-MHz clock. This
requires that all the data and the strobes arrive at the Intel (G)MCH before the 133-MHz clock edge (when
data is transferred to core).
External Design Specification
Intel Confidential
143
AC Characteristics
Table 29.
Host Interface AC Characteristics for 667 MHz
Symbol
Parameter
Min
Nom
Max
Unit
Figures
Notes
Common Clock
TCO
Output Valid Delay
0.075
TSU
Input Setup Time
TH
Input Hold Time
0.975
ns
Figure 24
1
0.469
ns
Figure 24
1
0.277
ns
Figure 24
1
Transmitter Address Timing
TAco
BCLK Rising to Valid Address Delay
0.075
0.975
ns
Figure 26
TAvb
Address Output Valid before
1.334
ns
Figure 26
TAva
Address Output Valid after
1.329
ns
Figure 26
ns
Figure 28
Transmitter Data Timing
TDco
BCLK Rising to Valid Data Delay
0.075
0.975
TDvb
Data Output Valid before
0.584
ns
Figure 28
TDva
Data Output Valid after
0.579
ns
Figure 28
Receiver Address Timing
TAsu
Address Input Setup Time
0.180
ns
Figure 28
TAh
Address Hold Time
0.180
ns
Figure 28
Receiver Data Timing
TDsu
Data Input Setup Time
0.180
ns
TDh
Data Hold Time
0.180
ns
NOTES:
1.
Common Clock AGTL+ signals are referenced to the rising edge of BCLK0.
2.
Since the (G)MCH chipset core is running at 166 MHz, the I/O buffer receives the data at the rate of
667 MHz from the processor and is latched by the corresponding strobes. In addition, because the (G)MCH
chipset core is running at 166 MHz, data transfer from I/O to core takes place at the 166-MHz clock. This
requires that all the data and the strobes arrive at the Intel (G)MCH before the 166-MHz clock edge (when
data is transferred to core).
Table 30.
Host Interface AC Characteristics for 800 MHz (Sheet 1 of 2)
Symbol
Parameter
Min
Nom
Max
Unit
Figures
Notes
Common Clock
TCO
Output Valid Delay
0.075
TSU
Input Setup Time
TH
Input Hold Time
0.975
ns
Figure 24
1
0.469
ns
Figure 24
1
0.277
ns
Figure 24
1
Transmitter Address Timing
TAco
BCLK Rising to Valid Address Delay
0.075
TAvb
Address Output Valid before
1.084
ns
Figure 26
TAva
Address Output Valid after
1.079
ns
Figure 26
144
Intel Confidential
0.975
ns
Figure 26
External Design Specification
AC Characteristics
Table 30.
Host Interface AC Characteristics for 800 MHz (Sheet 2 of 2)
Transmitter Data Timing
TDco
BCLK Rising to Valid Data Delay
0.075
TDvb
Data Output Valid before
TDva
Data Output Valid after
0.975
ns
Figure 28
0.425
ns
Figure 28
0.425
ns
Figure 28
Receiver Address Timing
TAsu
Address Input Setup Time
0.180
ns
Figure 26
TAh
Address Hold Time
0.180
ns
Figure 26
Receiver Data Timing
TDsu
Data Input Setup Time
0.180
ns
TDh
Data Hold Time
0.180
ns
NOTES:
1.
Common Clock AGTL+ signals are referenced to the rising edge of BCLK0.
2.
Since the (G)MCH chipset core is running at 200MHz, the I/O buffer receives the data at the rate of
800 MHz from the processor and is latched by the corresponding strobes. In addition, because the (G)MCH
chipset core is running at 133-MHz, data transfer from I/O to core takes place at the 200-MHz clock. This
requires that all the data and the strobes arrive at the Intel (G)MCH before the 200-MHz clock edge (when
data is transferred to core).
13.3
System Memory Interface Timing
13.3.1
DDR2 Interface Timings
The clock to output valid delays for the DDR2 interface are specified at 50 to
0.5xVCCSM load, measured at the die pad, unless otherwise specified. The delay of the
signal traveling in the package per unit distance (velocity) is specified as 5.8862e-9s/m
(~180 ps/in)). The reference point for all DDR2 AC timing measurements is
0.5xVCCSM.
Table 31.
DDR2 Interface AC Characteristics at 533 MTs, VCCSM = 1.8 V ± 5%
Symbol
Parameter
Min
SDQ[63:0], SDQS[7:0], SDQS#[7:0] Input
Slew Rate
1.0
Max
Unit
Figures
Notes
Electrical Characteristics
TSLR_D
V/ns
6
System Memory Clock Timings
TCK
SCK Period
TCH
SCK High Time
TCL
SCK Low Time
TjIT
SCK Cycle to Cycle Jitter
3.750
ns
Figure 38
1.71
ns
Figure 40
1.71
ns
Figure 41
400
ps
System Memory Command Signal Timings
TCMD_VB
SRAS#, SCAS#, SWE#, SMA[13:0],
SBS[1:0] Valid before SCK Rising Edge
External Design Specification
6.0
Intel Confidential
ns
Figure 34
2, 4
145
AC Characteristics
Table 31.
Symbol
TCMD_VA
DDR2 Interface AC Characteristics at 533 MTs, VCCSM = 1.8 V ± 5%
Parameter
Min
SRAS#, SCAS#, SWE#, SMA[13:0],
SBS[1:0] Valid after SCK Rising Edge
Max
1.0
Unit
Figures
Notes
ns
Figure 34
4
System Memory Control Signal Timings
TCTRL_VB
SCS#[3:0], SCKE[3:0], SODT[3:0] Valid
before SCK Rising Edge
TCTRL_VA
SCS#[3:0], SCKE[3:0] Valid after SCK
Rising Edge
2.169
ns
Figure 35
Figure 36
Figure 35
4
1.1
ns
0.65
ns
Figure 31
5
0.85
ns
Figure 31
5
Figure 36
4
System Memory Data and Strobe Signal Timings
TDVB
SDQ[63:0], SDM[7:0] Valid before
SDQS[7:0] Rising or Falling Edge
TDVA
SDQ[63:0], SDM[7:0] Valid after
SDQS[7:0] Rising or Falling Edge
TSumch
SDQ and SDM Input Setup Time to SDQS
Rising or Falling Edge
- 0.55
ns
Figure 30
1, 5, 6, 7
THDmch
SDQ and SDM Input Hold Time after SDQS
Rising or Falling Edge
1.3
ns
Figure 30
1, 5, 6
TDSSmch
SDQS Falling Edge Output Access Time to
SCK Rising Edge
1.685
ns
Figure 42
4, 5
TDSHmch
SDQS Falling Edge Output Access Time From
SCK Rising Edge
ns
Figure 43
4, 5
ns
Figure 32
ns
Figure 33
ns
Figure 44
3, 4, 5
ns
Figure 44
4, 5, 6
TWPRE_mc
h
TWPST_mc
h
TDQSS_mc
h
TPOE
SDQS/SDQS# Write Preamble Duration (1/2
TCK before fall clock edge + 1/2 TCK)
SDQS/SDQS# Write Postamble Duration
SCK Rising Edge Output Access Time, Where
a Write Command Is Referenced, to the First
SDQS Rising Edge
1.725
3.553
1.678
2.073
(WL ± 0.25)x
TCK
SCK Rising Edge Output Access Time, Where
a Write Command Is Referenced, to the
SDQS Preamble Falling Edge
0.207
NOTES:
1.
Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the (G)MCH
pad are determined with the minimum Read SDQS/SDQS# Delay and also applies to TDSSmch and
TDSHmch parameter.
2.
Command Timings are based off 2n Command Assertion Rule where the MA, RAS#, CAS#, WE#, and BS
signals are driven approximately one clock cycle prior to the assertion of CS#.
3.
WL (Write Latency) is the delay, in clock cycles, between the rising edge of SCK where a write command is
referenced and the first rising strobe edge where the first byte of write data is present. The WL value is
determined by the value of the CL (CAS Latency) setting Table 32 specifies the WL value based off the CL
setting.
4.
The system memory clock outputs are differential (SCK and SCK#), the SCK rising edge is referenced at
the crossing point where SCK is rising and SCK# is falling.
5.
The system memory strobe outputs are differential (SDQS and SDQS#), the SDQS rising edge is
referenced at the crossing point where SDQS is rising and SDQS# is falling, and the SDQS falling edge is
referenced at the crossing point where SDQS is falling and SDQS# is rising.
6.
When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0 V/
nS the tSUmch and tHDmch specifications must be increased by a derating factor. The input single ended
146
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External Design Specification
AC Characteristics
slew rate is measured from DC to AC levels; VIL_DC to VIH_AC for rising edges, and VIH_DC to VIL_AC for
falling edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte
group, to determine the required derating value. Table 33 specifies the derating values that must be added
to the tSUmch and tHDmch specifications if the input single ended data or strobe slew rate is less than 1.0
V/ns. No derating is required for single ended slew rates equal to or greater than 1.0 V/ns.
TSUMCH is measured from the crossing of SDQS and SDQS# until SDQ reaches Vref.
7.
Table 32.
Table 33.
(G)MCH DDR2 533-MTs Write Latency Values
CAS Latency (CL)
Write Latency (WL)
3
2
4
3
5
4
DDR2 533-MTs tSUmch and tHDmch Derating
Minimum SDQ/
SDQS/SDQS#
Input Slew Rate
(V/ns)
tSUmch, tHDmch
Derating Factor
(ps)
4.0 – 1.0
0
0.90
3
0.80
7
0.70
11
NOTE: This derating table can be used in a linear interpolation manner to determine the derating
factor for slew rates that are in between those specified in the minimum SDQ/SDQS/
SDQS# slew rate column. Refer to JEDEC specification for derating definition.
Table 34.
Symbol
DDR2 Interface AC Characteristics at 677 MTs, VCCSM = 1.8 V±5%
(Sheet 1 of 3)
Parameter
Min
Max
Unit
1.0
no max val
V/ns
Figures
Notes
Electrical Characteristics
TSLR_D
SDQ[63:0], SDQS[7:0],
SDQS#[7:0] Input Slew Rate
6
System Memory Clock Timings
TCK
SCK Period
ns
Figure 38
TCH
SCK High Time
1.263
ns
Figure 40
TCL
SCK Low Time
1.263
ns
Figure 41
TjIT
SCK Cycle to Cycle Jitter
125
ps
TJIT(c2c)
SCK/SCK# Cycle to Cycle Clock
Period Jitter
250
ps
TJIT(duty)
SCK/SCK# Clock Half Period
Jitter
125
ps
External Design Specification
3.000
Intel Confidential
147
AC Characteristics
Table 34.
Symbol
DDR2 Interface AC Characteristics at 677 MTs, VCCSM = 1.8 V±5%
(Sheet 2 of 3)
Parameter
Min
Max
Unit
TERR(2period)
SCK/SCK# Clock Cumulative
Error Across Two Consecutive
Cycles
175
ps
TERR(3period)
SCK/SCK# Clock Cumulative
Error Across Three Consecutive
Cycles
225
ps
TERR(4period)
SCK/SCK# Clock Cumulative
Error Across Four Consecutive
Cycles
250
ps
TERR(5period)
SCK/SCK# Clock Cumulative
Error Across Five Consecutive
Cycles
250
ps
Figures
Notes
System Memory Command Signal Timings
TCMD_VB
SRAS#, SCAS#, SWE#,
SMA[13:0], SBS[1:0] Valid
before SCK Rising Edge
4.66
ns
Figure 34
2, 4
TCMD_VA
SRAS#, SCAS#, SWE#,
SMA[13:0], SBS[1:0] Valid after
SCK Rising Edge
0.76
ns
Figure 34
4
System Memory Control Signal Timings
TCTRL_VB
SCS#[3:0], SCKE[3:0],
SODT[3:0] Valid before SCK
Rising Edge
1.76
ns
Figure 35
Figure 37
4
TCTRL_VA
SCS#[3:0], SCKE[3:0] Valid
after SCK Rising Edge
0.72
ns
Figure 35
Figure 36
4
System Memory Data and Strobe Signal Timings
TDVB
SDQ[63:0], SDM[7:0] Valid
before SDQS[7:0] Rising or
Falling Edge
0.45
ns
Figure 31
5
TDVA
SDQ[63:0], SDM[7:0] Valid
after SDQS[7:0] Rising or
Falling Edge
0.65
ns
Figure 31
5
TSumch
SDQ and SDM Input Setup Time
to SDQS Rising or Falling Edge
-0.5
ns
Figure 30
1, 5, 6, 7
THDmch
SDQ and SDM Input Hold Time
after SDQS Rising or Falling
Edge
1.05
ns
Figure 30
1, 5
TDSSmch
SDQS Falling Edge Output
Access Time to SCK Rising Edge
1.35
ns
Figure 42
4, 5
TDSHmch
SDQS Falling Edge Output
Access Time From SCK Rising
Edge
1.35
ns
Figure 43
4, 5
148
Intel Confidential
External Design Specification
AC Characteristics
Table 34.
Symbol
DDR2 Interface AC Characteristics at 677 MTs, VCCSM = 1.8 V±5%
(Sheet 3 of 3)
Parameter
Min
SDQS/SDQS# Write Preamble
Duration (1/2 TCK before fall
clock edge + 1/2 TCK)
2.763
TWPST_mch
SDQS/SDQS# Write Postamble
Duration
1.263
TDQSS_mch
SCK Rising Edge Output Access
Time, Where a Write Command
Is Referenced, to the First SDQS
Rising Edge
TPOE
SCK Rising Edge Output Access
Time, Where a Write Command
Is Referenced, to the SDQS
Preamble Falling Edge
TWPRE_mch
Max
1.738
Unit
Figures
Notes
ns
Figure 32
6
ns
Figure 33
ns
Figure 44
3, 4, 5
ns
Figure 45
4, 5, 6
(WL ± 0.25) X TCK
0.380
NOTES:
1.
Data to Strobe read setup and Data from Strobe read hold minimum requirements specified at the MCH
pad are determined with the minimum Read SDQS/SDQS# Delay and also applies to TDSSmch and
TDSHmch parameter.
2.
Command Timings are based off 2n Command Assertion Rule where the MA, RAS#, CAS#, WE#, and BS
signals are driven approximately one clock cycle prior to the assertion of CS#.
3.
WL (Write Latency) is the delay, in clock cycles, between the rising edge of SCK where a write command is
referenced and the first rising strobe edge where the first byte of write data is present. The WL value is
determined by the value of the CL (CAS Latency) setting Table 35 specifies the WL value based off the CL
setting.
4.
The system memory clock outputs are differential (SCK and SCK#), the SCK rising edge is referenced at
the crossing point where SCK is rising and SCK# is falling.
5.
The system memory strobe outputs are differential (SDQS and SDQS#), the SDQS rising edge is
referenced at the crossing point where SDQS is rising and SDQS# is falling, and the SDQS falling edge is
referenced at the crossing point where SDQS is falling and SDQS# is rising.
6.
When the single ended slew rate of the input Data or Strobe signals, within a byte group, are below 1.0 V/
nS the tSUmch and tHDmch specifications must be increased by a derating factor. The input single ended
slew rate is measured from DC to AC levels; VIL_DC to VIH_AC for rising edges, and VIH_DC to VIL_AC for
falling edges. Use the worse case minimum slew rate measured between Data and Strobe, within a byte
group, to determine the required derating value. Table 36 specifies the derating values that must be added
to the tSUmch and tHDmch specifications if the input single ended data or strobe slew rate is less than
1.0V/ns. No derating is required for single ended slew rates equal to or greater than 1.0V/ns.
7.
TSUMCH is measured from the crossing of SDQS and SDQS# until SDQ reaches Verve
Table 35.
(G)MCH DDR2 667-MTs Write Latency Values
CAS Latency (CL)
Write Latency (WL)
3
2
4
3
5
4
External Design Specification
Intel Confidential
149
AC Characteristics
Table 36.
DDR2-667-MTs tSUmch and tHDmch Derating
Minimum SDQ/SDQS/SDQS#
Input Slew Rate (V/ns)
tSUmch, tHDmch
Derating Factor (ps)
4.0 – 1.0
0
0.90
3
0.80
7
0.70
11
NOTE: This derating table can be used in a linear interpolation manner to determine the derating
factor for slew rates that are in between those specified in the minimum SDQ/SDQS/
SDQS# slew rate column. Refer to JEDEC specification for derating definition.
13.4
PCI Express Timing
Table 37.
PCI Express interface (Discrete Graphics or SDVO Port)
Symbol
Parameter
Min
Max
Unit
Figures
Notes
Transmitter and Receiver Timings
Table 38.
UI
Unit Interval
399.88
400.12
ps
TTX-EYE
Minimum Transmission Eye Width
0.75
UI
TTX-RISE/Fall
D+/D- TX Out put Rise/Fall time
.125
UI
TRX-EYE
Minimum Receiver Eye Width
.4
UI
5
Figure 28
1,2
1,2
Figure 29
3, 4
SDVO Interface Timings
Symbol
Parameter
Min
Max
Unit
Figures
Notes
Transmitter and Receiver Timings
UI
Unit Interval
369.89
TTX-EYE
Minimum Transmission Eye
Width
1000
ps
0.75
UI
TTX-RISE/Fall
D+/D- TX Out put Rise/Fall
time
.125
UI
TRX-EYE
Minimum Receiver Eye Width
.4
UI
6
Figure 28
1,2
1,2
Figure 29
3,4
NOTES:
1.
Specified at the measurement point into a timing and voltage compliance test load and
measured over any 250 consecutive TX UIs. (Also refer to the transmitter compliance eye
diagram shown in Figure 28).
2.
A TTX-EYE = 0.75 UI provides for a total sum of deterministic and random jitter budget of
TTX-JITTER-MAX = 0.25 UI for the Transmitter collected over any 250 consecutive TX UIs.
The TTX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the
median and the maximum deviation from the median is less than half of the total TX jitter
budget collected over any 250 consecutive TX UIs. It should be noted that the median is
not the same as the mean. The jitter median describes the point in time where the number
150
Intel Confidential
External Design Specification
AC Characteristics
3.
4.
5.
6.
13.5
of jitter points on either side is approximately equal as opposed to the averaged time
value.
Specified at the measurement point and measured over any 250 consecutive UIs. The test
load in Figure 4-25 of PCI Express Specification should be used as the RX device when
taking measurements (also refer to the receiver compliance eye diagram shown in
Figure 28). If the clocks to the RX and TX are not derived from the same reference clock,
the TX UI recovered from 3500 consecutive UI must be used as a reference for the eye
diagram.
A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter
budget for the Transmitter and interconnect collected any 250 consecutive UIs. The TRXEYE-MEDIAN-to-MAX-JITTER specification ensures a jitter distribution in which the median
and the maximum deviation from the median is less than half of the total.6 UI jitter budget
collected over any 250 consecutive TX UIs. It should be noted that the median is not the
same as the mean. The jitter median describes the point in time where the number of jitter
points on either side is approximately equal as opposed to the averaged time value. If the
clocks to the RX and TX are not derived from the same reference clock, the TX UI
recovered from 3500 consecutive UI must be used as the reference for the eye diagram.
Nominal UI Interval is 400 ps.
Nominal UI Interval for highest Intel SDVO speed is 370 ps. However, depending on the
resolution on the interface, the UI may be less than 370 ps.
LVDS Interface Timing
LVDS interface timing is specified below.
Table 39.
LVDS Interface AC Characteristics at Various Frequencies (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Figures
Notes
LLHT
LVDS Low-to-High Transition Time
0.25
0.5
0.75
ns
Figure 46
1, Across
receiver
termination
LHLT
LVDS High-to-Low Transition Time
0.25
0.5
0.75
ns
Figure 46
1, Across
receiver
termination
Frequency = 40-MHz
TPPos0
Transmitter Output Pulse for Bit 0
-0.25
0
0.25
ns
Figure 47
TPPos1
Transmitter Output Pulse for Bit 1
3.32
3.57
3.82
ns
Figure 47
TPPos2
Transmitter Output Pulse for Bit 2
6.89
7.14
7.39
ns
Figure 47
TPPos3
Transmitter Output Pulse for Bit 3
10.46
10.71
10.96
ns
Figure 47
TPPos4
Transmitter Output Pulse for Bit 4
14.04
14.29
14.54
ns
Figure 47
TPPos5
Transmitter Output Pulse for Bit 5
17.61
17.86
18.11
ns
Figure 47
TPPos6
Transmitter Output Pulse for Bit 6
21.18
21.43
21.68
ns
Figure 47
TJCC
Transmitter Jitter Cycle-to-Cycle
350
370
ps
Figure 47
Frequency = 65- MHz
TPPos0
Transmitter Output Pulse for Bit 0
-0.20
0
0.20
ns
Figure 47
TPPos1
Transmitter Output Pulse for Bit 1
2.00
2.20
2.40
ns
Figure 47
TPPos2
Transmitter Output Pulse for Bit 2
4.20
4.40
4.60
ns
Figure 47
TPPos3
Transmitter Output Pulse for Bit 3
6.39
6.59
6.79
ns
Figure 47
TPPos4
Transmitter Output Pulse for Bit 4
8.59
8.79
8.99
ns
Figure 47
External Design Specification
Intel Confidential
151
AC Characteristics
Table 39.
LVDS Interface AC Characteristics at Various Frequencies (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Unit
Figures
TPPos5
Transmitter Output Pulse for Bit 5
10.79
10.99
11.19
ns
Figure 47
TPPos6
Transmitter Output Pulse for Bit 6
12.99
13.19
13.39
ns
Figure 47
TJCC
Transmitter Jitter Cycle-to-Cycle
250
ps
Notes
Frequency = 85 – MHz
TPPos0
Transmitter Output Pulse for Bit 0
-0.20
0
0.20
ns
Figure 47
TPPos1
Transmitter Output Pulse for Bit 1
1.48
1.68
1.88
ns
Figure 47
TPPos2
Transmitter Output Pulse for Bit 2
3.16
3.36
3.56
ns
Figure 47
TPPos3
Transmitter Output Pulse for Bit 3
4.84
5.04
5.24
ns
Figure 47
TPPos4
Transmitter Output Pulse for Bit 4
6.52
6.72
6.92
ns
Figure 47
TPPos5
Transmitter Output Pulse for Bit 5
8.20
8.40
8.60
ns
Figure 47
TPPos6
Transmitter Output Pulse for Bit 6
9.88
10.08
10.28
ns
Figure 47
TJCC
Transmitter Jitter Cycle-to-Cycle
250
ps
Frequency = 108 –MHz
TPPos0
Transmitter Output Pulse for Bit 0
-0.20
0
0.20
ns
Figure 47
TPPos1
Transmitter Output Pulse for Bit 1
1.12
1.32
1.52
ns
Figure 47
TPPos2
Transmitter Output Pulse for Bit 2
2.46
2.66
2.86
ns
Figure 47
TPPos3
Transmitter Output Pulse for Bit 3
3.76
3.96
4.16
ns
Figure 47
TPPos4
Transmitter Output Pulse for Bit 4
5.09
5.29
5.49
ns
Figure 47
TPPos5
Transmitter Output Pulse for Bit 5
6.41
6.61
6.81
ns
Figure 47
TPPos6
Transmitter Output Pulse for Bit 6
7.74
7.94
8.14
ns
Figure 47
TJCC
Transmitter Jitter Cycle-to-Cycle
250
ps
0.20
ns
Figure 47
Frequency = 112 –MHz
TPPos0
Transmitter Output Pulse for Bit 0
-0.20
0
TPPos1
Transmitter Output Pulse for Bit 1
1.08
1.28
1.48
ns
Figure 47
TPPos2
Transmitter Output Pulse for Bit 2
2.35
2.55
2.75
ns
Figure 47
TPPos3
Transmitter Output Pulse for Bit 3
3.63
3.83
4.03
ns
Figure 47
TPPos4
Transmitter Output Pulse for Bit 4
4.90
5.10
5.30
ns
Figure 47
TPPos5
Transmitter Output Pulse for Bit 5
6.18
6.38
6.58
ns
Figure 47
TPPos6
Transmitter Output Pulse for Bit 6
7.46
7.66
7.86
ns
Figure 47
TJCC
Transmitter Jitter Cycle-to-Cycle
250
ps
Note:
152
All LVDS active lanes must be terminated by 100-Ω resistors for correct AC timing and
measurement
Intel Confidential
External Design Specification
AC Characteristics
13.6
CRT DAC Interface Timing
The DAC (digital-to-analog converter) consists of three identical 8-bit DACs to provide
red, green, and blue color components. Each DAC can output a current from 0 to 255
units of current, where one unit of current (LSB) is defined based on the VESA video
signal standard.
Table 40.
CRT DAC AC Characteristics
Parameter
Min
Pixel Clock Frequency
Typ
Max
300
Units
Notes
MHz
R,G,B Video Rise Time
0.25
3.4
ns
(1, 2, 8) (10-90% of black-towhite transition, @ 300-MHz
pixel clock)
R,G,B Video Fall Time
0.25
3.4
ns
(1, 3, 8) (90-10% of white-toblack transition, @ 300-MHz
pixel clock)
5
ns
(1, 4, 8) @ 300-MHz pixel clock
0.1
ns
(1, 5, 8) @ 300-MHz pixel clock
%
(1, 6, 8) Full-scale voltage step
of 0.7 V
%
(1, 7, 8)
Settling Time
Video channel-tochannel output skew
Overshoot/ Undershoot
Noise Injection Ratio
--10.0
+10.0
6.50
NOTES:
1.
Measured at each R, G, B termination according to the VESA Test Procedure – Evaluation of
Analog Display Graphics Subsystems Proposal (Version 1, Draft 4, December 1, 2000).
2.
R, G, B Max Video Rise/Fall Time: 50% of minimum pixel clock period.
3.
R, G, B Min Video Rise/Fall Time: 10% of minimum pixel clock period.
4.
Max settling time: 30% of minimum pixel clock period.
5.
Video channel-channel output skew: 50% of minimum pixel clock period.
6.
Overshoot/undershoot: ± 12% of black-white video level (full-scale) step function.
7.
Noise injection ratio: 2.5% of maximum luminance voltage (dc to max. pixel frequency).
8.
R, G, B AC parameters are strongly dependent on the board implementation
13.7
TV DAC Interface Timing
The DAC (digital-to-analog converter) consists of three identical 10-bit DAC channels.
Each DAC can output a current from 0 to 1023 units of current, where one unit of
current (LSB) is defined based on the TV signal standard.
TVDAC timing parameters are strongly dependent on the board implementation.
External Design Specification
Intel Confidential
153
AC Characteristics
Table 41.
TV DAC AC Characteristics
Parameter
Min
Typ
Max
Units
Comments
Rise/Fall Time
10
ns
@ TC Connector
Channel-to-Channel Skew
5
ns
D/A Clock rising edge to output
transition
Overshoot/Undershoot (Glitch)
10
%
% of steady-state full-scale voltage
step function voltage, min-to-fullscale output transition
5
ns
30% of minimum clock period
averaged over 100 video waveforms
to +/- 5% of steady-state full-scale
voltage after overshoot
148.5
MHz
Settling Time
Clock Frequency
13.8
54
108
Controller Link Interface Timing
The Controller Link interface consists of a data and clock signal line and is used to
communicate between the (G)MCH and ICH8. The physical link is a 2 wire, half duplex
interface. There is one clock, CL_CLK, and one data pin, CL_DATA, with the clock being
provided by the transmitter of the data in a source synchronous manner that is
sampled by the receiver on the rising and falling edges of the clock.
CL_CLK is driven at ½ the frequency of device’s transmit clock that is used to strobe
CL_DATA. CL_DATA is sampled at the receiver using both the rising and the falling edge
of CL_CLK.
Table 42.
Controller Link AC Characteristics
Symbol
Parameter
Min
Nom
Max
Unit
Figures
Notes
Transmitter Data Timing
Tvb
Data Output Valid Before
4.5
ns
Tva
Data Output Valid After
4.5
ns
Receiver Data Timing
154
Tsu
Data Input Setup Time
0.9
ns
Th
Data Hold Time
0.9
ns
Intel Confidential
External Design Specification
AC Characteristics
13.9
Display Data Channel (DDC) and GMBUS Interface
Timing
DDC and GMBUS signals are CRT_DDC_CLK, CRT_DDC_DATA, L_DDC_CLK,
L_DDC_DATA, SDVO_CTRL_CLK, SDVO_CTRL_DATA, L_CRTL_CLK, L_CRTL_DATA.
Table 43.
DDC and GMBUS Characteristics
Parameter
Min
Max
Units
Slew Rate
0.05
2
V/ns
CIO
3
6
pF
Remark
§
External Design Specification
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155
AC Characteristics
156
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External Design Specification
Signal Quality Specifications/Parameters
14
Signal Quality Specifications/
Parameters
Table 44 specifies the signal quality parameters for the chipset’s different signal
groups. All data is preliminary.
Table 44.
Signal Quality Parameters (Sheet 1 of 4)
Symbol
Parameter
Max (V)
Time
Duration
Note
1.1025
N/A
1
FSB Signals – 533 MHz
Vccx
FSB Supply Max Voltage
VOS
Absolute Maximum Overshoot
1.50
<251 ps
3, 4
VUS
Absolute Maximum Undershoot
-0.40
<251 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.47
<439 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.37
<439 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.45
<626 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.35
<626 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.42
<1.08 ns
3, 4
VUS
Undershoot Voltage Magnitude
-0.32
<1.08 ns
3, 4
VOS
Overshoot Voltage Magnitude
1.40
<1.55 ns
3, 4
VUS
Undershoot Voltage Magnitude
-0.30
<1.55 ns
3, 4
1.1025
N/A
1
FSB Signals – 667 MHz
Vccx
FSB Supply Max Voltage
VOS
Absolute Maximum Overshoot
1.50
<201 ps
3, 4
VUS
Absolute Maximum Undershoot
-0.40
<201 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.47
<351 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.37
<351 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.45
<501 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.35
<501 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.42
<861 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.32
<861 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.40
<1.24 ns
3, 4
VUS
Undershoot Voltage Magnitude
-0.30
<1.24 ns
3, 4
1.1025
N/A
1
FSB Signals – 800 MHz
Vccx
FSB Supply Max Voltage
VOS
Absolute Maximum Overshoot
1.50
<167 ps
3, 4
VUS
Absolute Maximum Undershoot
-0.40
<167 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.47
<292 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.37
<292 ps
3, 4
External Design Specification
Intel Confidential
157
Signal Quality Specifications/Parameters
Table 44.
Signal Quality Parameters (Sheet 2 of 4)
Max (V)
Time
Duration
Note
Overshoot Voltage Magnitude
1.45
<417 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.35
<417 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.42
<718 ps
3, 4
VUS
Undershoot Voltage Magnitude
-0.32
<718 ps
3, 4
VOS
Overshoot Voltage Magnitude
1.40
<1.03 ns
3, 4
VUS
Undershoot Voltage Magnitude
-0.30
<1.03 ns
3, 4
1.1025
N/A
Symbol
VOS
Parameter
PCI Express Graphics/SDVO Signals (Frequency = 2.5 GHz)
Vccx
PCI Express/SDVO Supply Max Voltage
VOS_MAX
Absolute Maximum Overshoot
1.57
<68.80 ps
VUS_MAX
Absolute Maximum Undershoot
-0.47
<68.80 ps
VOS
Overshoot Voltage Magnitude
1.55
<99.5 ps
VUS
Undershoot Voltage Magnitude
-0.45
<99.5 ps
VOS
Overshoot Voltage Magnitude
1.52
<173 ps
VUS
Undershoot Voltage Magnitude
-0.42
<173 ps
VOS
Overshoot Voltage Magnitude
1.5
<249 ps
VUS
Undershoot Voltage Magnitude
-0.40
<249 ps
VOS
Overshoot Voltage Magnitude
1.48
<357 ps
VUS
Undershoot Voltage Magnitude
-0.38
<357 ps
DDR2 533 MTs SDRAM Signals
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.1
<213 ps
4
VUS
Undershoot Voltage Magnitude
-1.21
<213 ps
4
VOS
Overshoot Voltage Magnitude
3
<444 ps
4
VUS
Undershoot Voltage Magnitude
-1.11
<444 ps
4
VOS
Overshoot Voltage Magnitude
2.95
<643 ps
4
VUS
Undershoot Voltage Magnitude
-1.06
<643 ps
4
VOS
Overshoot Voltage Magnitude
2.9
<928 ps
4
VUS
Undershoot Voltage Magnitude
-1.01
<928 ps
4
VOS
Overshoot Voltage Magnitude
2.85
<1.34 ns
4
VUS
Undershoot Voltage Magnitude
-0.96
<1.34 ns
4
DDR2 667 MTs SDRAM Signals
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.1
<170 ps
4
VUS
Undershoot Voltage Magnitude
-1.21
<170 ps
4
VOS
Overshoot Voltage Magnitude
3
<355 ps
4
VUS
Undershoot Voltage Magnitude
-1.11
<355 ps
4
158
Intel Confidential
External Design Specification
Signal Quality Specifications/Parameters
Table 44.
Signal Quality Parameters (Sheet 3 of 4)
Symbol
Parameter
Max (V)
Time
Duration
Note
VOS
Overshoot Voltage Magnitude
2.95
<514 ps
4
VUS
Undershoot Voltage Magnitude
-1.06
<514 ps
4
VOS
Overshoot Voltage Magnitude
2.9
<742 ps
4
VUS
Undershoot Voltage Magnitude
-1.01
<742 ps
4
VOS
Overshoot Voltage Magnitude
2.85
<1.07 ns
4
VUS
Undershoot Voltage Magnitude
-0.96
<1.07 ns
4
LVDS Signals: Frequency = 40 MHz (Thick Gate)
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.5
<4.67 ns
4
VUS
Undershoot Voltage Magnitude
-1.61
<4.67 ns
4
VOS
Overshoot Voltage Magnitude
3.4
<9.56 ns
4
VUS
Undershoot Voltage Magnitude
-1.51
<9.56 ns
4
VOS
Overshoot Voltage Magnitude
3.35
<13.6 ns
4
VUS
Undershoot Voltage Magnitude
-1.46
<13.6 ns
4
VOS
Overshoot Voltage Magnitude
3.3
<19.30 ns
4
VUS
Undershoot Voltage Magnitude
-1.41
<19.30 ns
4
VOS
Overshoot Voltage Magnitude
3.28
<22.20 ns
4
VUS
Undershoot Voltage Magnitude
-1.39
<22.20 ns
4
LVDS Signals: Frequency = 65 MHz (Thick Gate)
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.5
<2.87 ns
4
VUS
Undershoot Voltage Magnitude
-1.61
<2.87 ns
4
VOS
Overshoot Voltage Magnitude
3.4
<5.88 ns
4
VUS
Undershoot Voltage Magnitude
-1.51
<5.88 ns
4
VOS
Overshoot Voltage Magnitude
3.35
<8.37 ns
4
VUS
Undershoot Voltage Magnitude
-1.46
<8.37 ns
4
VOS
Overshoot Voltage Magnitude
3.3
<11.90 ns
4
VUS
Undershoot Voltage Magnitude
-1.41
<11.90 ns
4
VOS
Overshoot Voltage Magnitude
3.28
<13.70 ns
4
VUS
Undershoot Voltage Magnitude
-1.39
<13.70 ns
4
LVDS Signals: Frequency = 85 MHz (Thick Gate)
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.5
<2.20 ns
4
VUS
Undershoot Voltage Magnitude
-1.61
<2.20 ns
4
VOS
Overshoot Voltage Magnitude
3.4
<4.50 ns
4
VUS
Undershoot Voltage Magnitude
-1.51
<4.50 ns
4
External Design Specification
Intel Confidential
159
Signal Quality Specifications/Parameters
Table 44.
Signal Quality Parameters (Sheet 4 of 4)
Symbol
Parameter
Max (V)
Time
Duration
Note
<6.40 ns
4
VOS
Overshoot Voltage Magnitude
3.35
VUS
Undershoot Voltage Magnitude
-1.46
<6.40 ns
4
VOS
Overshoot Voltage Magnitude
3.3
<9.09 ns
4
VUS
Undershoot Voltage Magnitude
-1.41
<9.09 ns
4
VOS
Overshoot Voltage Magnitude
3.28
<10.40 ns
4
VUS
Undershoot Voltage Magnitude
-1.39
<10.40 ns
4
LVDS Signals: Frequency = 108 MHz (Thick Gate)
Vccx
DDR2 533 MTs SDRAM Supply Max Voltage
1.9
N/A
1
VOS
Overshoot Voltage Magnitude
3.5
<1.73 ns
4
VUS
Undershoot Voltage Magnitude
VOS
Overshoot Voltage Magnitude
VUS
-1.61
<1.73 ns
4
3.4
<3.54 ns
4
Undershoot Voltage Magnitude
-1.51
<3.54 ns
4
VOS
Overshoot Voltage Magnitude
3.35
<5.04 ns
4
VUS
Undershoot Voltage Magnitude
-1.46
<5.04 ns
4
VOS
Overshoot Voltage Magnitude
3.3
<7.15 ns
4
VUS
Undershoot Voltage Magnitude
-1.41
<7.15 ns
4
VOS
Overshoot Voltage Magnitude
3.28
<8.22 ns
4
VUS
Undershoot Voltage Magnitude
-1.39
<8.22 ns
4
CRT DAC Signals
Refer to Section 13.6 for overshoot/undershoot spec
TV DAC Signals
Refer to Section 13.7 for overshoot/undershoot spec
NOTES:
1.
Vccx is the voltage at which the time duration for the overshoot voltage is measured.
2.
The signal voltage must not exceed the absolute maximum overshoot/undershoot voltage at any time.
3.
Signals driven on the system bus should meet signal quality specifications to ensure components read data
properly and incoming signals do not affect long reliability of the component. See appropriate
microprocessor specification.
4.
Activity Factor = 0.25.
Table 45.
Signal Quality Specifications for AGTL+Signal Groups
Signal Group and Parameter
160
Maximum
Unit
Figure
AGTL+ Rising Edge Ringback
GTLREF +63
V
48
AGTL+ Falling Edge Ringback
GTLREF -63
V
48
Intel Confidential
Notes
External Design Specification
Signal Quality Specifications/Parameters
Table 46.
FSB Source Synch AC Specifications AGTL+ Signal Group
(533-MHz, 667-MHz and 800-MHz FSB) - Simulation Specification
T# Parameter
Min
Typ
Max
Unit
Figure
Notes
ps
49
1,2,3
ps
49
1,2,3
ps
49
1,2,3
ps
49
1,2,3
Unit
Figure
Notes
Data Eye Timing Margins:
T1
134
T2
138
T3
134
Data Eye Total Timing Margins
T1+T2+T3
Address Eye Timings Margins
T1
134
T2
190
T3
134
Address Eye Total Timing
Margins
T1+T2+T3
V# Parameter
Min
Typ
Max
Data Eye VREF Margins:
VREFD_H_sim
GTLREF+63
VREFD_L_sim
GTLREF-63
mV
49
1,2,3
Address Eye VREF Margins:
VREFA_H_sim
GTLREF+63
VREFA_L_sim
GTLREF-63
mV
49
1,2,3
NOTES:
1.
All timing and voltage parameters are relative to functional eye. Refer Figure 49 for more
information.
2.
This specification is defined for minimum eye margin values required for robust FSB
operation.
3.
This specification is defined for FSB simulations only.
Table 47.
FSB Source Synch AC Specifications AGTL+ Signal Group (667-MHz and 800MHz FSB) - Validation Specification
V# parameter
Min
Typ
Max
Unit
Figure
Notes
Data Eye VREF Margins:
VREFD_H_sim
GTLREF+85
VREFD_L_sim
GTLREF-85
mV
25
1,2,3
mV
25
1,2,3
Address Eye VREF Margins:
VREFA_H_sim
GTLREF+85
VREFA_L_sim
GTLREF-85
NOTES:
1.
This specification is defined for minimum values required for robust FSB operation.
2.
This specification is defined for FSB validation only.
3.
Refer to Figure 50 for more information.
§
External Design Specification
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Signal Quality Specifications/Parameters
162
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External Design Specification
AC Timing Diagrams
15
AC Timing Diagrams
15.1
Input Clocks
Figure 22.
Measurement Points for Differential Clocks
External Design Specification
Intel Confidential
163
AC Timing Diagrams
Figure 23.
Single-Ended Clock Waveform
15.2
Host Interface
Figure 24.
System Bus Test Fixture
VTT
1.475 nH
FSB Buffer
50 O
50 O
160 ps / in.
.8" length
164
Intel Confidential
0.85 pF
External Design Specification
AC Timing Diagrams
Figure 25.
System Bus Common Clock Waveform
s
Figure 26.
System Bus Source Synchronous Strobe Waveform for Address
External Design Specification
Intel Confidential
165
AC Timing Diagrams
Figure 27.
System Bus Source Synchronous Strobe Waveform for Data
15.3
PCI Express Interface
Figure 28.
PCI Express Transmitter Eye
166
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External Design Specification
AC Timing Diagrams
Figure 29.
PCI Express Receiver Eye
VTS-Diff = 0mV
D+/D- Crossing point
VRS-Diffp-p-Min>175mV
.4 UI =TRX-EYE min
15.4
System Memory Interface
15.4.1
DDR2 Interface
Figure 30.
SDQ Setup/Hold Relationship to/from SDQS/SDQS# (Read Operation)
SDQS#
(MCH)
0.5xVCCSM
SDQS
(MCH)
tHDmch
tSUmch
SDQ
(MCH)
tSUmch
Valid Data
Valid Data
Valid Data
Valid Data
tHDmch
External Design Specification
Intel Confidential
167
AC Timing Diagrams
Figure 31.
SDQ and SDM Valid before and after SDQS/SDQS# (Write Operation)
SDQS#
(MCH)
0.5xVCCSM
SDQS
(MCH)
tDVB
SDQ, SDM
(MCH)
Figure 32.
tDVA
tDVB
Valid Data
tDVA
Valid Data
Valid Data
Valid Data
Write Preamble Duration
tWPREmch
SDQS# (MCH)
SDQS
SDQS#
(MCH)
0.5xVCCSM
SDQS (MCH)
SDQS/SDQS# Write Preamble
Figure 33.
SDQS/SDQS# Toggle
Write Postamble Duration
tWPSTmch
SDQS#
(MCH)
0.5xVCCSM
SDQS
(MCH)
SDQS/SDQS# Toggle
Figure 34.
SDQS/SDQS# Write Posamble
Command Signals Valid before and after SCK Rising Edge
SCK# (MCH)
SCK (MCH)
tCVA
tCVB
SMA, SBS,
SRAS#,
SCAS#,
SWE# (MCH)
Valid CMD
SCS# (MCH)
168
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External Design Specification
AC Timing Diagrams
Figure 35.
SCKE Valid before and after SCK Rising Edge
SCK (MCH)
SCK# (MCH)
tCTRL_VB
SCKE (MCH)
Figure 36.
tCTRL_VA
Valid
SCS# Valid before and after SCK Rising Edge
SCK (MCH)
SCK# (MCH)
tCTRL_VB
tCTRL_VA
SCS# (MCH)
0.5xVCCSM
Figure 37.
SODT Valid before SCK Rising Edge
SCK (MCH)
SCK# (MCH)
tCTRL_VB
tCTRL_VB
0.5xVCCSM
SODT (MCH)
External Design Specification
Intel Confidential
169
AC Timing Diagrams
Figure 38.
Clock Cycle Time
tCK
SCK# (MCH)
SCK (MCH)
Figure 39.
Skew between any System Memory Differential Clock Pair (SCK/SCK#)
SCK#x (MCH)
SCKx (MCH)
tSKEW
SCK#y (MCH)
SCKy (MCH)
NOTE: represents one differential clock pair, and y represents another differential clock pair.
Figure 40.
SCK High Time
tCH
SCK# (MCH)
SCK (MCH)
170
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External Design Specification
AC Timing Diagrams
Figure 41.
SCK Low Time
tCL
SCK# (MCH)
SCK (MCH)
Figure 42.
SDQS Falling Edge Output Access Time to SCK Rising Edge
SCK# (MCH)
SCK (MCH)
tDSSmch
SDQS (MCH)
SDQS
SDQS#
(MCH)
0.5xVCCSM
SDQS# (MCH)
SDQS/SDQS# Write Preamble
Figure 43.
SDQS/SDQS# Toggle
SDQS Falling Edge Output Access Time from SCK Rising Edge
SCK# (MCH)
SCK (MCH)
tDSHmch
SDQS# (MCH)
SDQS
SDQS#
(MCH)
0.5xVCCSM
SDQS (MCH)
SDQS/SDQS# Write Preamble
External Design Specification
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SDQS/SDQS# Toggle
171
AC Timing Diagrams
Figure 44.
SCK Rising Edge Output Access Time to the First SDQS Rising Edge
SCK# (MCH)
SCK (MCH)
SMA, SBS,
SRAS#,
SCAS#,
SWE# (MCH)
Write
CMD
tDQSSmch
SDQS (MCH)
SDQS
SDQS#
(MCH)
0.5xVCCSM
SDQS# (MCH)
SDQS/SDQS# Write Preamble
Figure 45.
SDQS/SDQS# Toggle
SCK Rising Edge Output Access Time to the SDQS Preamble Falling Edge
SCK# (MCH)
SCK (MCH)
SMA, SBS,
SRAS#,
SCAS#,
SWE# (MCH)
Write
CMD
tPOE
SDQS (MCH)
SDQS
SDQS#
(MCH)
0.5xVCCSM
SDQS# (MCH)
SDQS/SDQS# Write Preamble
15.5
LVDS Interface
Figure 46.
LVDS Load and Transition Times
172
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SDQS/SDQS# Toggle
External Design Specification
AC Timing Diagrams
Figure 47.
Transmitting Position (Data to Strobe)
CLKA/
CLKB
Tppos0
YA/YB
Tppos1
Tppos2
Tppos3
Tppos4
Tppos5
Tppos6
15.6
Miscellaneous
Figure 48.
Overshoot and Undershoot Diagram and Ringback Illustration
Voltage
Overshoot
Tos1
Tos2
VOSREF
VCCP
Rising Edge
Ringback
Tus1
VSS
Falling Edge
Ringback
Undershoot
External Design Specification
Tus2
Intel Confidential
Time
173
AC Timing Diagrams
Figure 49.
Receiver Window Under System Load for Simulations Only
Figure 50.
Receiver Margins Under System Load for Validation Only
15.7
Chipset Family Power Sequencing
15.7.1
TV DAC
Power-Up Sequencing: There are no power sequencing requirements. There is a
preference to have 3.3-V ramp up before 1.5 V.
Power-Down Sequencing: There are no power sequencing requirements. There is a
preference to have 3.3-V ramp down after 1.5 V.
• 1.5-V rail include the following rails: VCCD_TVDAC, VCCD_QDAC.
• 3.3-V rail include the following rails: VCCA_TVA_DAC, VCCA_TVB_DAC,
VCCA_TVC_DAC, VCCA_DAC_BG.
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External Design Specification
AC Timing Diagrams
15.7.1.1
TV DAC with Respect to CRTDAC
Power-Up/Down Sequencing: Both TVDAC and CRTDAC 3.3 V should ramp up/down
together (supply them from same regulator). If TVDAC is not used: Tie all the 3.3 V for
TVDAC to CRTDAC 3.3-V supply.
• Relevant 3.3-V CRTDAC rail: VCCA_CRT_DAC.
• 3.3-V TVDAC rail include the following rails: VCCA_TVA_DAC, VCCA_TVB_DAC,
VCCA_TVC_DAC, VCCA_DAC_BG.
15.7.1.2
GPIO
Power-Up Sequencing: 3.3 V should ramp up before 1.05 V (VCC). If VCC ramps up
before 3.3 V, the maximum voltage difference between VCC and 3.3 V should be 0.7 V.
Power-Down Sequencing: 3.3 V should ramp down after 1.05 V (VCC). If 3.3 V
ramps down before VCC the maximum voltage difference between 3.3 V and VCC
during power-down should be less than 0.7 V.
• Relevant 3.3-V rail: VCC_HV.
Figure 51.
GPIO Power-Up Sequencing
External Design Specification
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175
AC Timing Diagrams
Figure 52.
GPIO Power-Down Sequencing
15.7.1.3
HVSYNC
Power-Up Sequencing: 3.3 V should ramp up before VCC (1.05 V). If 3.3-V ramps up
after VCC the max voltage difference between 3.3 V and VCC during power-up must be
less than 0.7 V.
Power-Down Sequencing: VCC should ramp down before 3.3 V. If 3.3-V ramps down
before VCC the max voltage difference between 3.3 V and VCC during power-down
must be less than 0.7 V.
• Relevant 3.3-V rail: VCC_SYNC
Figure 53.
176
HVSYNC Power-Up Sequencing
Intel Confidential
External Design Specification
AC Timing Diagrams
Figure 54.
HVSYNC Power-Down Sequencing
15.7.2
Mobile Intel 965 Express Chipset General Power
Sequencing Rules
• VCC_AXM and VCC_AXD must be stable for at least 1 ms before CL_PWROK
assertion to the MCH.
• VCC_AXF, VCC, and VTT must be stable for at least 1 ms before PWROK assertion
to the MCH.
• CL_PWROK assertion must be prior or at the same time as PWROK assertion.
For a system that does not support Intel AMT, VCC_AXM and VCC_AXD must still be
powered (VCC_AXM may be driven by the same supply as VCC, and VCC_AXD the
same supply as VCC_AXF).
§
External Design Specification
Intel Confidential
177
AC Timing Diagrams
178
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External Design Specification
Clocking
16
Clocking
16.1
Overview
The (G)MCH has a total of 4 PLLs which is used for many internal clocks. The PLLs are:
• Host PLL – Generates the main core clocks in the host clock domain. Can also be
used to generate memory and internal graphics core clocks. Uses the Host clock
(HPLL_CLK /HPLL_CLK#) as a reference.
• PCI Express PLL – Generates all PCI Express related clocks, including the DMI that
connects to the ICH. This PLL uses the 100 MHz (PEG_CLK / PEG_CLK#) as a
reference.
• Display PLL A – Generates the internal clocks for Display A or Display B. Uses the
low voltage 96-MHz differential clock, DPLL_REF_CLK / DPLL_REF_CLK#, as a
reference.
• Display PLL B – Generates the internal clocks for Display A or Display B. Uses the
low voltage 96-MHz differential clock, DPLL_REF_CLK / DPLL_REF_CLK#, as a
reference. Also may optionally use DPLL_REF_SSCLK / DPLL_REF_SSCLK#as a
reference for SSC support for LVDS display.
16.2
(G)MCH Reference Clocks
Reference Input Clocks
Input Frequency
Associated PLL
HPLL_CLK / HPLL_CLK#
133, 167, 200
Host / Memory / Graphics Core
PEG_CLK / PEG_CLK#
100 MHz
PCI Express / DMI PLL
DPLL_REF_CLK / DPLL_REF_CLK#
96 MHz
Display PLL A or B
DPLL_REF_SSCLK / DPLL_REF_SSCLK#
96 MHz (Non-SSC)
100 MHz (SSC)
Display PLL B
16.3
Host/Memory/Graphics Core Clock Frequency
Support
Table 48.
Host/Memory/Graphics Clock Frequency Support for 1.05-V Core Voltage for
the Mobile Intel GM965 and GL960 Express Chipsets (Sheet 1 of 2)
Host
(MHz)
Memory
(MHz)
Display Clock (MHz)
Render Clock (MHz)
533
DDR2 533
320
267(GM965/GL960)/320(GM965/
GL960)/400 (GM965/GL960)
667
DDR2 533
333
267(GM965)/333(GM965)
667
DDR2 667
333
250(GM965)/333(GM965)/
400(GM965)/500(GM965)
800
DDR2 533
320
267(GM965)/320(GM965)/
400(GM965)
External Design Specification
Intel Confidential
179
Clocking
Table 48.
Table 49.
Host/Memory/Graphics Clock Frequency Support for 1.05-V Core Voltage for
the Mobile Intel GM965 and GL960 Express Chipsets (Sheet 2 of 2)
Host
(MHz)
Memory
(MHz)
Display Clock (MHz)
Render Clock (MHz)
800
DDR2 667
333
250(GM965)/333(GM965)/
400(GM965)/500(GM965)
Host/Memory/Graphics Clock Frequency Support for 1.05-V Core Voltage for
the Mobile Intel GM965/GM965 (mini-note)/GM965(sub-note), GL960 and
PM965 Express Chipsets
SKU
GM965
GM965
(mini-note)
GM965
(sub-note)
GL960
PM965
Max FSB (MHz)
800
800
533
533
800
Max Memory
(MHz)
DDR2 667
DDR2 533
DDR2 533
DDR2 533
DDR2 667
Max Display
Clock (MHz)
333
320
320
320
N/A
Recommended
Max Render
Clock (MHz)
500
320
267
400
N/A
§
180
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External Design Specification
Testability
17
Testability
17.1
Test Mode Entry
This Section is used to provide instructions to the product and board test teams on how
to activate the XOR chain/ALLZ test mode.
Figure 55.
XOR Chain Test Mode Entry Events Diagram
PWROK
C L_PW ROK
DON’T C ARE
CFG[13]
(XOR setting)
DON’T C ARE
CFG[12]
(XOR setting)
R STIN#
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Testability
Figure 56.
ALLZ Test Mode Entry Events Diagram
PWROK
CL_PWROK
DON’T CARE
CFG[13]
(ALLZ setting)
DON’T CARE
CFG[12]
(ALLZ setting)
RSTIN#
Table 50.
Mobile Intel GM965/PM965/GL960 Express Chipset Strap Information for
Testability
Pin Name
Strap
Description
Configuration
00 = Reserved
CFG13:12
XOR/ALLZ
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal operation (default)
SDVO_CTRL_DATA
SDVO present
CFG20
SDVO/PCI
Express
Concurrent
CFG9
PCI Express
Graphics Lane
0 = No SDVO Card Present (default)
1 = SDVO Card Present
0 = Only SDVO or PCI Express* is operational
(default)
1 = SDVO and PCI Express operate simultaneously
through the PCI Express Graphics attach port
0 = Lane Reversed
1 = Normal mode (default; lanes numbered in order)
The chipsets latches the strap values at PWROK assertion. XOR chain test mode and
ALLZ activation occur at RSTIN#. All XOR chain inputs (except 3GIO/PCI-E buffers) tristate after RSTIN# assertion. All XOR chain outputs enable after RSTIN# assertion.
A minimum of 50-ns PWROK assertion prior to RSTIN# assertion is recommended.
A minimum of 10-ns CFG straps assertion prior to PWROK assertion is recommended.
A minimum of 32 3GIO clocks are required after RSTIN# assertion to tri-state the
3GIO/PCI-E buffers. Refer to Figure 57 for details.
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External Design Specification
Testability
A minimum of 32-HPLL clocks are required after RSTIN# assertion to properly enable
test mode.
Figure 57.
HPLL_CLK
HPLL_CLK#
G_CLKINP
G_CLKINN
XOR Test Mode Initialization Cycle
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
DON’T
CARE
PWROK
RSTINB
3GIO/PCIE Buffers
17.2
1
Z
Voltage Rail Information
Section 2.10 contains a full list of the chipset voltage rail information.
17.2.1
XOR Chain Differential Pairs
In XOR mode the differential pairs in DDR interface do not have to be treated as pairs
in XOR mode. There is XOR specific circuitry that allows the pins to be driven
independently.
17.2.2
XOR Chain Exclusion List
The following table contains the list of pins that are not included in the XOR chains.
Note:
Voltage column indicates what level represents a logical 1. To enable the XOR chain test
mode some of the exclusion pins should be driven with certain specific voltages. These
are indicated in the Connectivity column.
Table 51.
XOR Chain Exclusion List (Sheet 1 of 4)
Ball Name
Interface
Ball
CRT_BLUE
CRT DAC
H32
CRT_BLUE#
CRT DAC
G32
CRT_GREEN
CRT DAC
K29
CRT_GREEN#
CRT DAC
J29
CRT_HSYNC
CRT DAC
F33
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Testability
Table 51.
XOR Chain Exclusion List (Sheet 2 of 4)
Ball Name
Interface
Ball
CRT_TVO_IREF
CRT DAC
C32
CRT_RED
CRT DAC
F29
CRT_RED#
CRT DAC
E29
CRT_VSYNC
CRT DAC
E33
SA_RCVEN#
Memory Interface
AY20
RSVD
Reserved & Test
BJ20
RSVD
Reserved & Test
BK22
SB_RCVEN#
Memory Interface
AY18
RSVD
Reserved & Test
BH39
RSVD
Reserved & Test
BF19
RSVD
Reserved & Test
BH20
SM_RCOMP#
Memory Interface
BK14
SM_RCOMP
Memory Interface
BL15
SM_RCOMP_VOH
Memory Interface
BK31
SM_RCOMP_VOL
Memory Interface
BL31
RSVD
Reserved & Test
BK18
RSVD
Reserved & Test
BJ18
RSVD
Reserved & Test
AW20
RSVD
Reserved & Test
BK20
SM_VREF
Memory Interface
AW4
SM_VREF
Memory Interface
AR49
RSVD
Reserved & Test
P36
RSVD
Reserved & Test
P37
RSVD
Reserved & Test
R35
RSVD
Reserved & Test
N35
DPLL_REF_CLK#
PLL
C42
DPLL_REF_CLK
PLL
B42
DPLL_REF_SSCLK#
PLL
H47
DPLL_REF_SSCLK
PLL
H48
PCI Express Based Graphics
M43
PLL
K45
PEG_COMPO
PEG_CLK#
PEG_CLK
PLL
K44
PCI Express Based Graphics
N43
H_SCOMP
Host Interface
W1
H_SCOMP#
Host Interface
W2
H_SWING
PEG_COMPI
184
Host Interface
B3
HPLL_CLK#
PLL
AM7
HPLL_CLK
PLL
AM5
Intel Confidential
External Design Specification
Testability
Table 51.
XOR Chain Exclusion List (Sheet 3 of 4)
Ball Name
Interface
Ball
RSVD
Reserved & Test
AR12
RSVD
Reserved & Test
AR13
RSVD
Reserved & Test
AM12
RSVD
Reserved & Test
AN13
RSVD
Reserved & Test
AR37
RSVD
Reserved & Test
AM36
RSVD
Reserved & Test
AL36
RSVD
Reserved & Test
AM37
LVDS_IBG
LVDS
L41
LVDS_VBG
LVDS
L43
LVDS_VREFH
LVDS
N41
LVDS_VREFL
LVDS
N40
CL_PWROK
Intel ME Interface
AT43
CL_CLK
Intel ME Interface
AM49
CL_DATA
Intel ME Interface
AK50
CL_RST#
Intel ME Interface
AN49
CL_VREF
Intel ME Interface
AM50
NC
No Connects
BJ51
NC
No Connects
BK2
NC
No Connects
E1
NC
No Connects
A5
NC
No Connects
C51
NC
No Connects
B50
NC
No Connects
A50
NC
No Connects
A49
NC
No Connects
BK51
NC
No Connects
BK50
NC
No Connects
BL50
NC
No Connects
BL49
NC
No Connects
BL3
NC
No Connects
BL2
NC
No Connects
BK1
NC
No Connects
BJ1
CFG0
Strappings
P27
CFG1
Strappings
N27
CFG10
Strappings
R24
CFG11
Strappings
L23
CFG12
Strappings
J23
External Design Specification
Intel Confidential
185
Testability
Table 51.
XOR Chain Exclusion List (Sheet 4 of 4)
Ball Name
186
Interface
Ball
CFG13
Strappings
E23
CFG14
Strappings
E20
CFG15
Strappings
K23
CFG16
Strappings
M20
CFG17
Strappings
M24
CFG2
Strappings
N24
CFG3
Strappings
C21
CFG4
Strappings
C23
CFG5
Strappings
F23
CFG6
Strappings
N23
CFG7
Strappings
G23
CFG8
Strappings
J20
CFG9
Strappings
C20
PWROK
Reset & Miscellaneous
AW49
RSTIN#
Reset & Miscellaneous
AV20
VSS
Power & Ground
T33
VSS
Power & Ground
R28
VSS
Power & Ground
T31
VSS
Power & Ground
T29
RSVD
Reserved & Test
D20
TVA_DAC
Analog TV-out
E27
TVB_DAC
Analog TV-out
G27
TVC_DAC
Analog TV-out
K27
TV_DCONSEL0
Analog TV-out
M35
TV_DCONSEL1
Analog TV-out
P33
TVA_RTN
Analog TV-out
F27
TVB_RTN
Analog TV-out
J27
TVC_RTN
Analog TV-out
L27
Intel Confidential
External Design Specification
Testability
17.3
XOR Chain Test Mode for Different Product
Configurations
The chipset supports XOR chain test mode with different product configurations. Some
of the ball(s) may not route to the board based on the following product configurations.
• DRAM channel configurations
• Various PCI Express Graphics/DMI lane configurations
• PCI Express Graphics/SDVO configurations
• LVDS channel configurations
• I2C and other HVCMOS configurations
17.3.1
DRAM Channel Configurations
All DDR XOR chains are composed of pins from the same DDR channel. DDR chains
1,2, and 3 are composed of DDR channel A pins, and chains 4, 5, and 6 are composed
of DDR channel B pins.
17.3.2
Various PCI Express Graphics/DMI Lane Configurations
PCI Express Graphics and DMI XOR chains require having all un-driven XOR inputs to
be routed to the board for all lane configurations. These XOR chains are NOT
supported for the Mobile Intel GM965/PM965 Chipset if this requirement is not
met.
Note:
If implementing DMI x4 interface then this requirement is met. If implementing DMI x2
interface then all the undriven DMI ports will need to be routed to test points.
17.3.3
PCI Express Graphics/SDVO Configurations
PCI Express Graphics XOR chain requires having all active PCI Express Graphics lanes
to be routed to the board for the SDVO configurations listed below. This XOR chain is
NOT supported for Mobile Intel GM965/PM965 Chipset if this requirement is not met.
Table 52.
Mobile Intel GM965/PM965 Chipset PCI Express Graphics Lanes Active for
SDVO Configuration for Testability
Active PCI Express
Graphics Lanes for XOR
Configuration
SDVO Enable
SDVO/PCI
Express
coexistence
detected
PCI Express
Static Lane
Reversal
0
0
0
[15:8] & [7:0]
0
0
1
[7:0] & [15:8]
1
0
0
[7:0]
1
0
1
[15:8]
1
1
0
[15:8] & [7:0]
1
1
1
[7:0] & [15:8]
External Design Specification
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MCH PCI Express
Graphics Pins
187
Testability
17.3.4
LVDS Channel Configurations
LVDS XOR chain requires having all un-driven XOR inputs to be routed to the board for
all LVDS channel configurations. These XOR chains are NOT supported for Mobile Intel
GM965/GL960 Chipset if this requirement is not met.
17.3.5
I2C and Other HVCMOS Configurations
For HVCMOS XOR chains, it is recommended to have all un-driven XOR inputs be
routed to the board for different I2C and HVCMOS configurations.
17.4
XOR Chain Connectivity/Ordering
The following tables contain the ordering for all of the XOR chains and pin to ball mapping information.
Note:
The voltage column indicates what level needs to be driven for the XOR input.
Table 53.
XOR Chain Connectivity/Ordering FSB1 (Sheet 1 of 3)
XOR CHAIN FSB1
188
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG3
O
LV CMOS
VTT
C21
1
H_D#58
IO
AGTL+
VTT
AJ7
2
H_D#62
IO
AGTL+
VTT
AH2
3
H_D#60
IO
AGTL+
VTT
AE5
4
H_D#59
IO
AGTL+
VTT
AJ2
5
H_D#61
IO
AGTL+
VTT
AJ3
6
H_D#56
IO
AGTL+
VTT
AJ6
7
H_D#55
IO
AGTL+
VTT
AH5
8
H_D#54
IO
AGTL+
VTT
AJ5
9
H_D#49
IO
AGTL+
VTT
AH8
10
H_D#48
IO
AGTL+
VTT
AJ9
11
H_D#50
IO
AGTL+
VTT
AJ14
12
H_D#52
IO
AGTL+
VTT
AE11
13
H_D#63
IO
AGTL+
VTT
AH13
14
H_D#53
IO
AGTL+
VTT
AH12
15
H_D#51
IO
AGTL+
VTT
AE9
16
H_D#57
IO
AGTL+
VTT
AE7
17
H_D#45
IO
AGTL+
VTT
AE2
18
H_D#47
IO
AGTL+
VTT
AG3
19
H_D#33
IO
AGTL+
VTT
AE3
20
H_D#32
IO
AGTL+
VTT
AD12
21
H_D#38
IO
AGTL+
VTT
AD11
22
H_D#39
IO
AGTL+
VTT
AC11
Intel Confidential
External Design Specification
Testability
Table 53.
XOR Chain Connectivity/Ordering FSB1 (Sheet 2 of 3)
XOR CHAIN FSB1
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
23
H_D#44
IO
AGTL+
VTT
AC6
24
H_D#46
IO
AGTL+
VTT
AC5
25
H_D#41
IO
AGTL+
VTT
AD7
26
H_D#43
IO
AGTL+
VTT
Y3
27
H_D#42
IO
AGTL+
VTT
AB1
28
H_D#37
IO
AGTL+
VTT
AC14
29
H_D#36
IO
AGTL+
VTT
AC7
30
H_D#40
IO
AGTL+
VTT
AB2
31
H_D#34
IO
AGTL+
VTT
AD9
32
H_D#35
IO
AGTL+
VTT
AC9
33
H_D#25
IO
AGTL+
VTT
W9
34
H_D#18
IO
AGTL+
VTT
Y8
35
H_D#17
IO
AGTL+
VTT
W10
36
H_D#24
IO
AGTL+
VTT
W6
37
H_D#27
IO
AGTL+
VTT
Y7
38
H_D#21
IO
AGTL+
VTT
J1
39
H_D#19
IO
AGTL+
VTT
V4
40
H_D#28
IO
AGTL+
VTT
Y9
41
H_D#26
IO
AGTL+
VTT
N2
42
H_D#31
IO
AGTL+
VTT
N1
43
H_D#16
IO
AGTL+
VTT
M2
44
H_D#20
IO
AGTL+
VTT
M3
45
H_D#23
IO
AGTL+
VTT
N3
46
H_D#22
IO
AGTL+
VTT
N5
47
H_D#30
IO
AGTL+
VTT
W3
48
H_D#29
IO
AGTL+
VTT
P4
49
H_D#5
IO
AGTL+
VTT
H3
50
H_D#6
IO
AGTL+
VTT
G4
51
H_D#4
IO
AGTL+
VTT
H7
52
H_D#13
IO
AGTL+
VTT
H5
53
H_D#1
IO
AGTL+
VTT
G2
54
H_D#2
IO
AGTL+
VTT
G7
55
H_D#3
IO
AGTL+
VTT
M6
56
H_D#7
IO
AGTL+
VTT
F3
57
H_D#8
IO
AGTL+
VTT
N8
58
H_D#14
IO
AGTL+
VTT
P13
External Design Specification
Intel Confidential
189
Testability
Table 53.
XOR Chain Connectivity/Ordering FSB1 (Sheet 3 of 3)
XOR CHAIN FSB1
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
59
H_D#12
IO
AGTL+
VTT
N9
60
H_D#15
IO
AGTL+
VTT
K9
61
H_D#11
IO
AGTL+
VTT
N12
62
H_D#9
IO
AGTL+
VTT
H2
63
H_D#0
IO
AGTL+
VTT
E2
64
H_D#10
IO
AGTL+
VTT
M10
Table 54.
XOR Chain Connectivity/Ordering FSB2 (Sheet 1 of 2)
XOR CHAIN FSB2
190
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG4
O
LV CMOS
VTT
C23
1
H_A#5
IO
AGTL+
VTT
C11
2
H_A#4
IO
AGTL+
VTT
B11
3
H_REQ#1
IO
AGTL+
VTT
E13
4
H_A#6
IO
AGTL+
VTT
M11
5
H_A#3
IO
AGTL+
VTT
J13
6
H_REQ#4
IO
AGTL+
VTT
B12
7
H_REQ#3
IO
AGTL+
VTT
H13
8
H_A#13
IO
AGTL+
VTT
B13
9
H_A#9
IO
AGTL+
VTT
L13
10
H_A#11
IO
AGTL+
VTT
C14
11
H_A#8
IO
AGTL+
VTT
F16
12
H_A#10
IO
AGTL+
VTT
G17
13
H_REQ#2
IO
AGTL+
VTT
A11
14
H_ADSTB#
IO
AGTL+
VTT
H17
15
H_REQ#0
IO
AGTL+
VTT
M14
16
H_A#16
IO
AGTL+
VTT
B14
17
H_A#7
IO
AGTL+
VTT
C15
18
H_A#14
IO
AGTL+
VTT
L16
19
H_A#12
IO
AGTL+
VTT
K16
20
H_A#15
IO
AGTL+
VTT
J17
21
H_A#20
IO
AGTL+
VTT
B16
22
H_A#29
IO
AGTL+
VTT
B17
23
H_A#18
IO
AGTL+
VTT
P15
24
H_A#24
IO
AGTL+
VTT
M17
25
H_A#25
IO
AGTL+
VTT
N16
Intel Confidential
External Design Specification
Testability
Table 54.
XOR Chain Connectivity/Ordering FSB2 (Sheet 2 of 2)
XOR CHAIN FSB2
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
26
H_A#35
IO
AGTL+
VTT
N19
27
H_A#30
IO
AGTL+
VTT
B15
28
H_A#23
IO
AGTL+
VTT
D17
29
H_A#17
IO
AGTL+
VTT
K19
30
H_A#27
IO
AGTL+
VTT
B18
31
H_A#34
IO
AGTL+
VTT
B19
32
H_A#19
IO
AGTL+
VTT
R17
33
H_A#31
IO
AGTL+
VTT
E17
34
H_ADSTB#
IO
AGTL+
35
H_A#26
IO
AGTL+
VTT
J19
36
H_A#21
IO
AGTL+
VTT
H20
37
H_A#33
IO
AGTL+
VTT
A19
38
H_A#22
IO
AGTL+
VTT
L19
39
H_A#32
IO
AGTL+
VTT
C18
40
H_A#28
IO
AGTL+
VTT
E19
Table 55.
VTT
G20
XOR Chain Connectivity/Ordering FSB3 (Sheet 1 of 2)
XOR CHAIN FSB3
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
ICH_SYNC#
O
HVCMOS
VCC_HV
BJ1
1
H_DSTBP#2
IO
AGTL+
VTT
AC2
2
H_DSTBN#2
IO
AGTL+
VTT
AD2
3
H_RS#1
O
AGTL+
VTT
D7
4
H_HITM#
IO
AGTL+
VTT
C6
5
H_TRDY#
O
AGTL+
VTT
B7
6
H_HIT#
IO
AGTL+
VTT
E4
7
H_DSTBP#1
IO
AGTL+
VTT
K2
8
H_DSTBN#1
IO
AGTL+
VTT
K3
9
H_DSTBP#0
IO
AGTL+
VTT
L7
10
H_DSTBN#0
IO
AGTL+
VTT
M7
11
H_DPWR#
O
AGTL+
VTT
H8
12
RSVD20
O
AGTL+
VTT
B51
13
H_BNR#
IO
AGTL+
VTT
C8
14
H_LOCK#
I
AGTL+
VTT
G10
External Design Specification
Intel Confidential
191
Testability
Table 55.
XOR Chain Connectivity/Ordering FSB3 (Sheet 2 of 2)
XOR CHAIN FSB3
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
15
H_BPRI#
O
AGTL+
VTT
E8
16
H_CPURST#
O
AGTL+
VTT
B6
17
THERMTRIP#
O
AGTL+
VTT
N20
Table 56.
XOR Chain Connectivity/Ordering FSB4
XOR CHAIN FSB4
XOROUT
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
1
PMSYNC#
(PM_BM_BUSY#)
I
HVCMOS
VCC_HV
G41
2
H_DSTBP#3
IO
AGTL+
VTT
AJ10
3
H_DSTBN#3
IO
AGTL+
VTT
AH11
4
H_DINV#3
IO
AGTL+
VTT
AE13
5
H_DINV#2
IO
AGTL+
VTT
AD13
6
H_RS#2
O
AGTL+
VTT
D8
7
H_DEFER#
O
AGTL+
VTT
D6
8
H_RS#0
O
AGTL+
VTT
E12
9
H_DRDY#
IO
AGTL+
VTT
K7
10
H_DBSY#
IO
AGTL+
VTT
C10
11
H_DINV#1
IO
AGTL+
VTT
L2
12
H_DINV#0
IO
AGTL+
VTT
K5
13
RSVD9
O
AGTL+
VTT
B51
14
H_ADS#
IO
AGTL+
VTT
G12
15
H_CPUSLP#
O
CMOS
VTT
E5
16
H_BREQ#
IO
AGTL+
VTT
F12
Table 57.
XOR Chain Connectivity/Ordering GPIO1
XOR CHAIN GPIO1
192
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG5
O
LV CMOS
VTT
F23
1
DPRSLPVR
I
HVCMOS
VCC_HV
G36
2
GFX_VR_EN
O
HVCMOS
VCC_HV
E36
3
GFX_VID2
O
HVCMOS
VCC_HV
C38
4
CRT_DDC_CLK
IO
Open Drain
VCC_HV
K33
5
GFX_VID0
O
HVCMOS
VCC_HV
E35
6
CLKREQ#
O
Open Drain
VCC_HV
G39
Intel Confidential
External Design Specification
Testability
Table 57.
XOR Chain Connectivity/Ordering GPIO1
XOR CHAIN GPIO1
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
7
CFG19
I
HVCMOS
VCC_HV
N33
8
SDVO_CTRL_DATA
IO
Open Drain
VCC_HV
K36
9
L_CTRL_DATA
O
Open Drain
VCC_HV
E40
10
CFG20
I
HVCMOS
VCC_HV
L35
11
PM_DPRSTP#
I
LVCMOS
Vtt
L39
12
TEST2
I
HVCMOS
VCC_HV
R32
13
PM_EXT_TS#0
I
HVCMOS
VCC_HV
L36
14
TV_DCONSEL0
O
Open Drain
VCC_HV
M35
Table 58.
XOR Chain Connectivity/Ordering GPIO2
XOR CHAIN GPIO2
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG9
O
LVCMOS
VTT
C20
1
CFG18
I
HVCMOS
VCC_HV
L32
2
L_DDC_CLK
IO
Open Drain
VCC_HV
C37
3
CRT_DDC_DATA
IO
Open Drain
VCC_HV
G35
4
L_BKLT_CTRL
O
HVCMOS
VCC_HV
J40
5
GFX_VID1
O
HVCMOS
VCC_HV
A39
6
SDVO_CTRL_CLK
IO
Open Drain
VCC_HV
H35
7
TV_DCONSEL1
O
Open Drain
VCC_HV
P33
8
L_CTRL_CLK
O
Open Drain
VCC_HV
E39
9
GFX_VID3
O
HVCMOS
VCC_HV
B39
10
PM_EXT_TS#1
I
HVCMOS
VCC_HV
J36
11
L_VDD_EN
O
HVCMOS
VCC_HV
K40
12
L_DDC_DATA
IO
Open Drain
VCC_HV
D35
Table 59.
XOR Chain Connectivity/Ordering LVDS
XOR CHAIN LVDS
BALL NAME
XOROUT
DIR
I/O TYPE
VOLTAGE (V)
BALL
L_BKLT_EN
O
HVCMOS
VCC_HV
H39
1
LVDSA_CLK#
IO
LVDS
Current Drive
D46
2
LVDSB_CLK#
IO
LVDS
Current Drive
D44
3
LVDSA_CLK
IO
LVDS
Current Drive
C45
4
LVDSB_CLK
IO
LVDS
Current Drive
E42
External Design Specification
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Testability
Table 59.
XOR Chain Connectivity/Ordering LVDS
XOR CHAIN LVDS
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
5
LVDSA_DATA#0
IO
LVDS
Current Drive
G51
6
LVDSB_DATA#0
IO
LVDS
Current Drive
G44
7
LVDSA_DATA#1
IO
LVDS
Current Drive
E51
8
LVDSB_DATA#1
IO
LVDS
Current Drive
B47
9
LVDSA_DATA#2
IO
LVDS
Current Drive
F49
10
LVDSB_DATA#2
IO
LVDS
Current Drive
B45
11
LVDSA_DATA#3
IO
LVDS
Current Drive
C48
12
LVDSB_DATA#3
O
LVDS
Current Drive
B44
13
LVDSA_DATA0
IO
LVDS
Current Drive
G50
14
LVDSB_DATA0
IO
LVDS
Current Drive
E44
15
LVDSA_DATA1
IO
LVDS
Current Drive
E50
16
LVDSB_DATA1
IO
LVDS
Current Drive
A47
17
LVDSA_DATA2
IO
LVDS
Current Drive
F48
18
LVDSB_DATA2
IO
LVDS
Current Drive
A45
19
LVDSA_DATA3
IO
LVDS
Current Drive
D47
20
LVDSB_DATA3
O
LVDS
Current Drive
C44
Table 60.
XOR Chain Connectivity/Ordering DMI (Sheet 1 of 2)
XOR CHAIN DMI
194
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG0
O
LVCMOS
VTT
P27
1
DMI_TXN0
O
3GIO
Current Drive
AJ46
2
DMI_TXP0
O
3GIO
Current Drive
AJ47
3
DMI_RXN0
I
3GIO
Current Drive
AN47
4
DMI_RXP0
I
3GIO
Current Drive
AM47
5
DMI_RXN1
I
3GIO
Current Drive
AJ38
6
DMI_RXP1
I
3GIO
Current Drive
AJ39
7
DMI_TXN1
O
3GIO
Current Drive
AJ41
8
DMI_TXP1
O
3GIO
Current Drive
AJ42
9
DMI_TXN2
O
3GIO
Current Drive
AM40
10
DMI_TXP2
O
3GIO
Current Drive
AM39
11
DMI_RXN2
I
3GIO
Current Drive
AN42
12
DMI_RXP2
I
3GIO
Current Drive
AN41
13
DMI_RXN3
I
3GIO
Current Drive
AN46
Intel Confidential
External Design Specification
Testability
Table 60.
XOR Chain Connectivity/Ordering DMI (Sheet 2 of 2)
XOR CHAIN DMI
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
14
DMI_RXP3
I
3GIO
Current Drive
AN45
15
DMI_TXN3
O
3GIO
Current Drive
AM44
16
DMI_TXP3
O
3GIO
Current Drive
AM43
Table 61.
XOR Chain Connectivity/Ordering PCI Express Graphics (Sheet 1 of 3)
XOR CHAIN PCI Express Graphics
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG5
O
LVCMOS
VTT
F23
1
PEG_TX0
O
3GIO
Current Drive
M45
2
PEG_TX#0
O
3GIO
Current Drive
N45
3
PEG_RX0
I
3GIO
Current Drive
J50
4
PEG_RX#0
I
3GIO
Current Drive
J51
5
PEG_RX1
I
3GIO
Current Drive
L50
6
PEG_RX#1
I
3GIO
Current Drive
L51
7
PEG_TX1
O
3GIO
Current Drive
T38
8
PEG_TX#1
O
3GIO
Current Drive
U39
9
PEG_RX2
I
3GIO
Current Drive
M47
10
PEG_TX#2
O
3GIO
Current Drive
U47
11
PEG_TX2
O
3GIO
Current Drive
T46
12
PEG_RX#2
I
3GIO
Current Drive
N47
13
PEG_RX3
I
3GIO
Current Drive
U44
14
PEG_RX#3
I
3GIO
Current Drive
T45
15
PEG_TX3
O
3GIO
Current Drive
N50
16
PEG_TX#3
O
3GIO
Current Drive
N51
17
PEG_TX4
O
3GIO
Current Drive
R51
18
PEG_TX#4
O
3GIO
Current Drive
R50
19
PEG_RX4
I
3GIO
Current Drive
T49
20
PEG_RX#4
I
3GIO
Current Drive
T50
21
PEG_RX5
I
3GIO
Current Drive
T41
22
PEG_RX#5
I
3GIO
Current Drive
U40
23
PEG_TX5
O
3GIO
Current Drive
U43
24
PEG_TX#5
O
3GIO
Current Drive
T42
25
PEG_TX6
O
3GIO
Current Drive
W42
26
PEG_TX#6
O
3GIO
Current Drive
Y43
27
PEG_RX6
I
3GIO
Current Drive
W45
External Design Specification
Intel Confidential
195
Testability
Table 61.
XOR Chain Connectivity/Ordering PCI Express Graphics (Sheet 2 of 3)
XOR CHAIN PCI Express Graphics
196
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
28
PEG_RX#6
I
3GIO
Current Drive
Y44
29
PEG_RX7
I
3GIO
Current Drive
W41
30
PEG_RX#7
I
3GIO
Current Drive
Y40
31
PEG_TX7
O
3GIO
Current Drive
Y47
32
PEG_TX#7
O
3GIO
Current Drive
W46
33
PEG_RX8
I
3GIO
Current Drive
AB50
34
PEG_TX#8
O
3GIO
Current Drive
W38
35
PEG_TX8
O
3GIO
Current Drive
Y39
36
PEG_RX#8
I
3GIO
Current Drive
AB51
37
PEG_RX9
I
3GIO
Current Drive
Y48
38
PEG_RX#9
I
3GIO
Current Drive
W49
39
PEG_TX9
O
3GIO
Current Drive
AC38
40
PEG_TX#9
O
3GIO
Current Drive
AD39
41
PEG_TX10
O
3GIO
Current Drive
AD47
42
PEG_TX#10
O
3GIO
Current Drive
AC46
43
PEG_RX10
I
3GIO
Current Drive
AC45
44
PEG_RX#10
I
3GIO
Current Drive
AD44
45
PEG_RX11
I
3GIO
Current Drive
AC41
46
PEG_RX#11
I
3GIO
Current Drive
AD40
47
PEG_TX11
O
3GIO
Current Drive
AC50
48
PEG_TX#11
O
3GIO
Current Drive
AC49
49
PEG_RX12
I
3GIO
Current Drive
AH47
50
PEG_TX#12
O
3GIO
Current Drive
AC42
51
PEG_TX12
O
3GIO
Current Drive
AD43
52
PEG_RX#12
I
3GIO
Current Drive
AG46
53
PEG_RX13
I
3GIO
Current Drive
AG49
54
PEG_RX#13
I
3GIO
Current Drive
AH49
55
PEG_TX13
O
3GIO
Current Drive
AG39
56
PEG_TX#13
O
3GIO
Current Drive
AH39
57
PEG_RX14
I
3GIO
Current Drive
AH45
58
PEG_TX#14
O
3GIO
Current Drive
AE49
59
PEG_TX14
O
3GIO
Current Drive
AE50
60
PEG_RX#14
I
3GIO
Current Drive
AG45
61
PEG_RX15
I
3GIO
Current Drive
AG42
Intel Confidential
External Design Specification
Testability
Table 61.
XOR Chain Connectivity/Ordering PCI Express Graphics (Sheet 3 of 3)
XOR CHAIN PCI Express Graphics
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
62
PEG_RX#15
I
3GIO
Current Drive
AG41
63
PEG_TX15
O
3GIO
Current Drive
AH43
64
PEG_TX#15
O
3GIO
Current Drive
AH44
VOLTAGE (V)
BALL
Table 62.
XOR Chain Connectivity/Ordering DDR1
XOR CHAIN DDR1
BALL NAME
DIR
I/O TYPE
XOROUT
RSVD12
O
1.25
1
SA_DQS#0
IO
SSTL-1.8
VCCSM
AT47
2
SA_DM0
O
SSTL-1.8
VCCSM
AT45
3
SA_DM1
O
SSTL-1.8
VCCSM
BD44
4
SA_DQS#2
IO
SSTL-1.8
VCCSM
BC41
5
SA_DM2
O
SSTL-1.8
VCCSM
BD42
6
SA_DM3
O
SSTL-1.8
VCCSM
AW38
8
SA_MA6
O
SSTL-1.8
VCCSM
BJ27
AL36
9
SM_CKE0
O
SSTL-1.8
VCCSM
BE29
10
SM_CKE1
O
SSTL-1.8
VCCSM
AY32
11
SA_MA9
O
SSTL-1.8
VCCSM
BA28
12
SA_MA5
O
SSTL-1.8
VCCSM
BK28
13
SA_MA2
O
SSTL-1.8
VCCSM
BK27
14
SA_MA3
O
SSTL-1.8
VCCSM
BH28
15
SA_MA4
O
SSTL-1.8
VCCSM
BL24
16
SA_MA7
O
SSTL-1.8
VCCSM
BJ25
17
SA_MA8
O
SSTL-1.8
VCCSM
BL28
18
SM_CK#0
O
SSTL-1.8
VCCSM
AW30
20
SM_CK0
O
SSTL-1.8
VCCSM
AV29
22
SA_MA1
O
SSTL-1.8
VCCSM
BD20
23
SM_ODT1
O
SSTL-1.8
VCCSM
BJ15
24
SM_CS#0
O
SSTL-1.8
VCCSM
BG20
25
SM_ODT0
O
SSTL-1.8
VCCSM
BH18
26
SA_MA10
O
SSTL-1.8
VCCSM
BC19
27
SM_CS#1
O
SSTL-1.8
VCCSM
BK16
External Design Specification
Intel Confidential
197
Testability
Table 63.
XOR Chain Connectivity/Ordering DDR1
XOR CHAIN DDR2/MLINK
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
RSVD11
O
GTL
VCCA_SM
AM36
1
CL_CLK
I/O
GTL
VCCA_SM
AM49
2
CL_DATA
I/O
GTL
VCCA_SM
AK50
3
SA_DQS#5
IO
SSTL-1.8
VCCSM
BH7
4
SA_DM5
O
SSTL-1.8
VCCSM
BG8
5
SA_DQS#6
IO
SSTL-1.8
VCCSM
BC1
6
SA_DM6
O
SSTL-1.8
VCCSM
AY5
7
SA_DQS#7
IO
SSTL-1.8
VCCSM
AP2
8
SA_DM7
O
SSTL-1.8
VCCSM
AN6
9
SA_DQS#1
IO
SSTL-1.8
VCCSM
BD47
10
SA_DQS#3
IO
SSTL-1.8
VCCSM
BA37
11
SA_MA14
O
SSTL-1.8
VCCSM
BJ29
12
SA_MA12
O
SSTL-1.8
VCCSM
BG30
13
SA_MA11
O
SSTL-1.8
VCCSM
BE28
14
SA_BS2
O
SSTL-1.8
VCCSM
BF29
15
SM_CK#1
O
SSTL-1.8
VCCSM
BA23
16
SM_CK1
O
SSTL-1.8
VCCSM
BB23
17
SA_CAS#
O
SSTL-1.8
VCCSM
BL17
18
SA_WE#
O
SSTL-1.8
VCCSM
BA19
19
SA_BS0
O
SSTL-1.8
VCCSM
BB19
20
SA_BS1
O
SSTL-1.8
VCCSM
BK19
21
SA_MA13
O
SSTL-1.8
VCCSM
BJ16
22
SA_MA0
O
SSTL-1.8
VCCSM
BJ19
23
SA_RAS#
O
SSTL-1.8
VCCSM
BE18
24
SA_DQS#4
IO
SSTL-1.8
VCCSM
BA16
25
SA_DM4
O
SSTL-1.8
VCCSM
AW13
Table 64.
XOR Chain Connectivity/Ordering DDR3 (Sheet 1 of 3)
XOR CHAIN DDR3
198
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG1
O
LVCMOS
VTT
N27
1
SA_DQS5
IO
SSTL-1.8
VCCSM
BH6
2
SA_DQ42
IO
SSTL-1.8
VCCSM
BD8
3
SA_DQ43
IO
SSTL-1.8
VCCSM
AY9
Intel Confidential
External Design Specification
Testability
Table 64.
XOR Chain Connectivity/Ordering DDR3 (Sheet 2 of 3)
XOR CHAIN DDR3
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
4
SA_DQ47
IO
SSTL-1.8
VCCSM
BB9
5
SA_DQ45
IO
SSTL-1.8
VCCSM
AW9
6
SA_DQ44
IO
SSTL-1.8
VCCSM
BG10
7
SA_DQ46
IO
SSTL-1.8
VCCSM
BD7
8
SA_DQ40
IO
SSTL-1.8
VCCSM
BE10
9
SA_DQ41
IO
SSTL-1.8
VCCSM
BD10
10
SA_DQS6
IO
SSTL-1.8
VCCSM
BB2
11
SA_DQ55
IO
SSTL-1.8
VCCSM
AR8
12
SA_DQ53
IO
SSTL-1.8
VCCSM
BB7
13
SA_DQ54
IO
SSTL-1.8
VCCSM
AR5
14
SA_DQ51
IO
SSTL-1.8
VCCSM
AT7
15
SA_DQ49
IO
SSTL-1.8
VCCSM
AY7
16
SA_DQ52
IO
SSTL-1.8
VCCSM
AY6
17
SA_DQ50
IO
SSTL-1.8
VCCSM
AT5
18
SA_DQ48
IO
SSTL-1.8
VCCSM
BB5
19
SA_DQS7
IO
SSTL-1.8
VCCSM
AP3
20
SA_DQ56
IO
SSTL-1.8
VCCSM
AR9
21
SA_DQ58
IO
SSTL-1.8
VCCSM
AM8
22
SA_DQ59
IO
SSTL-1.8
VCCSM
AN10
23
SA_DQ60
IO
SSTL-1.8
VCCSM
AT9
24
SA_DQ57
IO
SSTL-1.8
VCCSM
AN3
25
SA_DQ63
IO
SSTL-1.8
VCCSM
AN11
26
SA_DQ61
IO
SSTL-1.8
VCCSM
AN9
27
SA_DQ62
IO
SSTL-1.8
VCCSM
AM9
28
SA_DQS0
IO
SSTL-1.8
VCCSM
AT46
29
SA_DQ2
IO
SSTL-1.8
VCCSM
BA45
30
SA_DQ5
IO
SSTL-1.8
VCCSM
AR45
31
SA_DQ7
IO
SSTL-1.8
VCCSM
AW47
32
SA_DQ3
IO
SSTL-1.8
VCCSM
AY46
33
SA_DQ0
IO
SSTL-1.8
VCCSM
AR43
34
SA_DQ6
IO
SSTL-1.8
VCCSM
AT42
35
SA_DQ4
IO
SSTL-1.8
VCCSM
AR41
36
SA_DQ1
IO
SSTL-1.8
VCCSM
AW44
37
SA_DQS1
IO
SSTL-1.8
VCCSM
BE48
38
SA_DQ12
IO
SSTL-1.8
VCCSM
BB47
39
SA_DQ13
IO
SSTL-1.8
VCCSM
BG50
External Design Specification
Intel Confidential
199
Testability
Table 64.
XOR Chain Connectivity/Ordering DDR3 (Sheet 3 of 3)
XOR CHAIN DDR3
200
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
40
SA_DQ8
IO
SSTL-1.8
VCCSM
BB45
41
SA_DQ9
IO
SSTL-1.8
VCCSM
BF48
42
SA_DQ10
IO
SSTL-1.8
VCCSM
BG47
43
SA_DQ11
IO
SSTL-1.8
VCCSM
BJ45
44
SA_DQ14
IO
SSTL-1.8
VCCSM
BH49
45
SA_DQ15
IO
SSTL-1.8
VCCSM
BE45
46
SA_DQS2
IO
SSTL-1.8
VCCSM
BB43
47
SA_DQ17
IO
SSTL-1.8
VCCSM
BE44
48
SA_DQ22
IO
SSTL-1.8
VCCSM
BG40
49
SA_DQ16
IO
SSTL-1.8
VCCSM
AW43
50
SA_DQ21
IO
SSTL-1.8
VCCSM
BH45
51
SA_DQ20
IO
SSTL-1.8
VCCSM
BF44
52
SA_DQ19
IO
SSTL-1.8
VCCSM
BE40
53
SA_DQ23
IO
SSTL-1.8
VCCSM
BF40
54
SA_DQ18
IO
SSTL-1.8
VCCSM
BG42
55
SA_DQS3
IO
SSTL-1.8
VCCSM
BC37
56
SA_DQ28
IO
SSTL-1.8
VCCSM
AW41
57
SA_DQ25
IO
SSTL-1.8
VCCSM
AW40
58
SA_DQ29
IO
SSTL-1.8
VCCSM
AY41
59
SA_DQ24
IO
SSTL-1.8
VCCSM
AR40
60
SA_DQ26
IO
SSTL-1.8
VCCSM
AT39
61
SA_DQ30
IO
SSTL-1.8
VCCSM
AV38
62
SA_DQ31
IO
SSTL-1.8
VCCSM
AT38
63
SA_DQ27
IO
SSTL-1.8
VCCSM
AW36
64
SA_DQS4
IO
SSTL-1.8
VCCSM
BB16
65
SA_DQ34
IO
SSTL-1.8
VCCSM
AW11
66
SA_DQ37
IO
SSTL-1.8
VCCSM
AT11
67
SA_DQ32
IO
SSTL-1.8
VCCSM
AV13
68
SA_DQ33
IO
SSTL-1.8
VCCSM
AT13
69
SA_DQ39
IO
SSTL-1.8
VCCSM
BA11
70
SA_DQ38
IO
SSTL-1.8
VCCSM
BA13
71
SA_DQ36
IO
SSTL-1.8
VCCSM
AU15
72
SA_DQ35
IO
SSTL-1.8
VCCSM
AV11
Intel Confidential
External Design Specification
Testability
Table 65.
XOR Chain Connectivity/Ordering DDR4
XOR CHAIN DDR4
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
CFG_7
O
LV CMOS
VTT
G23
1
SB_DQS#_0
IO
SSTL-1.8
VCCSM
AU50
2
SB_DM_0
O
SSTL-1.8
VCCSM
AR50
3
SB_DM_1
O
SSTL-1.8
VCCSM
BD49
4
SB_DQS#_2
IO
SSTL-1.8
VCCSM
BL45
5
SB_DM_2
O
SSTL-1.8
VCCSM
BK45
6
SB_DM_3
O
SSTL-1.8
VCCSM
BL39
7
SB_MA_5
O
SSTL-1.8
VCCSM
BE25
8
SM_CKE_3
O
SSTL-1.8
VCCSM
BD39
9
SM_CKE_4
O
SSTL-1.8
VCCSM
BG37
10
SB_MA_4
O
SSTL-1.8
VCCSM
BF25
11
SB_MA_2
O
SSTL-1.8
VCCSM
BG25
12
SB_MA_1
O
SSTL-1.8
VCCSM
BG28
13
SB_MA_6
O
SSTL-1.8
VCCSM
BA29
14
SB_MA_7
O
SSTL-1.8
VCCSM
BC28
15
SB_MA_9
O
SSTL-1.8
VCCSM
BD37
16
SB_MA_8
O
SSTL-1.8
VCCSM
AY28
17
SM_CK#_3
O
SSTL-1.8
VCCSM
AW25
18
SM_CK_3
O
SSTL-1.8
VCCSM
BA25
19
SB_MA_3
O
SSTL-1.8
VCCSM
AW17
20
SB_MA_0
O
SSTL-1.8
VCCSM
BC18
21
SM_CS#_2
O
SSTL-1.8
VCCSM
BG16
22
SM_ODT_2
O
SSTL-1.8
VCCSM
BJ14
23
SM_CS#_3
O
SSTL-1.8
VCCSM
BE13
24
SM_ODT_3
O
SSTL-1.8
VCCSM
BE16
25
SB_MA_10
O
SSTL-1.8
VCCSM
BG17
T
Table 66.
XOR Chain Connectivity/Ordering DDR5 (Sheet 1 of 2)
XOR CHAIN DDR5
BALL NAME
DIR
I/O TYPE
XOROUT
RSVD10
O
1.25
1
SB_DQS#5
IO
SSTL-1.8
VCCSM
BK7
2
SB_DM5
O
SSTL-1.8
VCCSM
BJ7
3
SB_DQS#6
IO
SSTL-1.8
VCCSM
BF2
External Design Specification
Intel Confidential
VOLTAGE (V)
BALL
AR37
201
Testability
Table 66.
XOR Chain Connectivity/Ordering DDR5 (Sheet 2 of 2)
XOR CHAIN DDR5
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
4
SB_DM6
O
SSTL-1.8
VCCSM
BF3
5
SB_DQS#7
IO
SSTL-1.8
VCCSM
AV3
6
SB_DM7
O
SSTL-1.8
VCCSM
AW2
7
SB_DQS#1
IO
SSTL-1.8
VCCSM
BC50
8
SB_DQS#3
IO
SSTL-1.8
VCCSM
BK38
9
SB_BS2
O
SSTL-1.8
VCCSM
BG36
10
SB_MA12
O
SSTL-1.8
VCCSM
BA39
11
SB_MA14
O
SSTL-1.8
VCCSM
BE24
12
SB_MA11
O
SSTL-1.8
VCCSM
BE37
13
SM_CK#4
O
SSTL-1.8
VCCSM
AW23
14
SM_CK4
O
SSTL-1.8
VCCSM
AV23
15
SB_RAS#
O
SSTL-1.8
VCCSM
AV16
16
SB_MA13
O
SSTL-1.8
VCCSM
BG13
17
SB_BS1
O
SSTL-1.8
VCCSM
BG18
18
SB_CAS#
O
SSTL-1.8
VCCSM
BE17
19
SB_BS0
O
SSTL-1.8
VCCSM
AY17
20
SB_WE#
O
SSTL-1.8
VCCSM
BC17
21
SB_DQS#4
IO
SSTL-1.8
VCCSM
BK12
22
SB_DM4
O
SSTL-1.8
VCCSM
BH12
Table 67.
XOR Chain Connectivity/Ordering DDR6 (Sheet 1 of 3)
XOR CHAIN DDR6
BALL NAME
202
DIR
I/O TYPE
VOLTAGE (V)
BALL
XOROUT
RSVD13
O
1.25
1
SB_DQS5
IO
SSTL-1.8
VCCSM
BL7
2
SB_DQ46
IO
SSTL-1.8
VCCSM
BJ8
3
SB_DQ45
IO
SSTL-1.8
VCCSM
BK10
4
SB_DQ41
IO
SSTL-1.8
VCCSM
BL9
5
SB_DQ43
IO
SSTL-1.8
VCCSM
BL5
6
SB_DQ44
IO
SSTL-1.8
VCCSM
BK9
7
SB_DQ40
IO
SSTL-1.8
VCCSM
BJ10
8
SB_DQ47
IO
SSTL-1.8
VCCSM
BJ6
9
SB_DQ42
IO
SSTL-1.8
VCCSM
BK5
10
SB_DQS6
IO
SSTL-1.8
VCCSM
BE2
11
SB_DQ52
IO
SSTL-1.8
VCCSM
BK3
12
SB_DQ50
IO
SSTL-1.8
VCCSM
BG1
Intel Confidential
AM37
External Design Specification
Testability
Table 67.
XOR Chain Connectivity/Ordering DDR6 (Sheet 2 of 3)
XOR CHAIN DDR6
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
13
SB_DQ48
IO
SSTL-1.8
VCCSM
BF4
14
SB_DQ55
IO
SSTL-1.8
VCCSM
BJ2
15
SB_DQ49
IO
SSTL-1.8
VCCSM
BH5
16
SB_DQ54
IO
SSTL-1.8
VCCSM
BD3
17
SB_DQ53
IO
SSTL-1.8
VCCSM
BE4
18
SB_DQ51
IO
SSTL-1.8
VCCSM
BC2
19
SB_DQS7
IO
SSTL-1.8
VCCSM
AV2
20
SB_DQ57
IO
SSTL-1.8
VCCSM
BB3
21
SB_DQ56
IO
SSTL-1.8
VCCSM
BA3
22
SB_DQ61
IO
SSTL-1.8
VCCSM
AY3
23
SB_DQ60
IO
SSTL-1.8
VCCSM
AY2
24
SB_DQ62
IO
SSTL-1.8
VCCSM
AU2
25
SB_DQ58
IO
SSTL-1.8
VCCSM
AR1
26
SB_DQ59
IO
SSTL-1.8
VCCSM
AT3
27
SB_DQ63
IO
SSTL-1.8
VCCSM
AT2
28
SB_DQS0
IO
SSTL-1.8
VCCSM
AT50
29
SB_DQ7
IO
SSTL-1.8
VCCSM
AV49
30
SB_DQ0
IO
SSTL-1.8
VCCSM
AP49
31
SB_DQ4
IO
SSTL-1.8
VCCSM
AN51
32
SB_DQ5
IO
SSTL-1.8
VCCSM
AN50
33
SB_DQ6
IO
SSTL-1.8
VCCSM
AV50
34
SB_DQ2
IO
SSTL-1.8
VCCSM
AW50
35
SB_DQ3
IO
SSTL-1.8
VCCSM
AW51
36
SB_DQ1
IO
SSTL-1.8
VCCSM
AR51
37
SB_DQS1
IO
SSTL-1.8
VCCSM
BD50
38
SB_DQ10
IO
SSTL-1.8
VCCSM
BA49
39
SB_DQ15
IO
SSTL-1.8
VCCSM
BF49
40
SB_DQ8
IO
SSTL-1.8
VCCSM
BA50
41
SB_DQ13
IO
SSTL-1.8
VCCSM
AY49
42
SB_DQ11
IO
SSTL-1.8
VCCSM
BE50
43
SB_DQ9
IO
SSTL-1.8
VCCSM
BB50
44
SB_DQ14
IO
SSTL-1.8
VCCSM
BF50
45
SB_DQ12
IO
SSTL-1.8
VCCSM
BA51
46
SB_DQS2
IO
SSTL-1.8
VCCSM
BK46
47
SB_DQ17
IO
SSTL-1.8
VCCSM
BJ44
48
SB_DQ21
IO
SSTL-1.8
VCCSM
BK49
External Design Specification
Intel Confidential
203
Testability
Table 67.
XOR Chain Connectivity/Ordering DDR6 (Sheet 3 of 3)
XOR CHAIN DDR6
BALL NAME
DIR
I/O TYPE
VOLTAGE (V)
BALL
49
SB_DQ23
IO
SSTL-1.8
VCCSM
BK42
50
SB_DQ18
IO
SSTL-1.8
VCCSM
BJ43
51
SB_DQ19
IO
SSTL-1.8
VCCSM
BL43
52
SB_DQ22
IO
SSTL-1.8
VCCSM
BK43
53
SB_DQ20
IO
SSTL-1.8
VCCSM
BK47
54
SB_DQ16
IO
SSTL-1.8
VCCSM
BJ50
55
SB_DQS3
IO
SSTL-1.8
VCCSM
BK39
56
SB_DQ28
IO
SSTL-1.8
VCCSM
BK41
57
SB_DQ25
IO
SSTL-1.8
VCCSM
BL41
58
SB_DQ24
IO
SSTL-1.8
VCCSM
BJ41
59
SB_DQ27
IO
SSTL-1.8
VCCSM
BJ36
60
SB_DQ30
IO
SSTL-1.8
VCCSM
BL35
61
SB_DQ26
IO
SSTL-1.8
VCCSM
BJ37
62
SB_DQ31
IO
SSTL-1.8
VCCSM
BK37
63
SB_DQ29
IO
SSTL-1.8
VCCSM
BJ40
64
SB_DQS4
IO
SSTL-1.8
VCCSM
BJ12
65
SB_DQ39
IO
SSTL-1.8
VCCSM
BG12
66
SB_DQ34
IO
SSTL-1.8
VCCSM
BK11
67
SB_DQ32
IO
SSTL-1.8
VCCSM
BK13
68
SB_DQ37
IO
SSTL-1.8
VCCSM
BE12
69
SB_DQ36
IO
SSTL-1.8
VCCSM
BC13
70
SB_DQ33
IO
SSTL-1.8
VCCSM
BE11
71
SB_DQ35
IO
SSTL-1.8
VCCSM
BC11
72
SB_DQ38
IO
SSTL-1.8
VCCSM
BC12
§
204
Intel Confidential
External Design Specification
Chipset Strapping Configuration
18
Chipset Strapping Configuration
Table 68.
Chipset Strapping Signals and Configuration
Pin Name
Strap Description
Configuration
010 = FSB 800 MHz
011 = FSB 667 MHz
CFG[2:0]
FSB Frequency Select
CFG[4:3]
Reserved
CFG5
DMI x2 Select
CFG6
Reserved
CFG7
Intel® Management
Engine Crypto strap
CFG8
Reserved
CFG9
PCI Express Graphics Lane
Reversal
CFG[11:10]
Reserved
001 = FSB 533 MHz
Others: Reserved
0 = DMI x2
1 = DMI x4 (default)
0 = Intel Management Engine Crypto Transport Layer
Security (TLS) cipher suite with no confidentiality
1= Intel Management Engine Crypto TLS cipher suite with
confidentiality (default)
0 = Lane Reversed
1 = Normal mode (default; lanes numbered in order)
00 = Reserved
CFG[13:12]
XOR/ALL-Z
CFG[15:14]
Reserved
CFG16
FSB Dynamic ODT
CFG[18:17]
Reserved
CFG19
DMI Lane Reversal
CFG20
Concurrent SDVO / PCI
Express
SDVO_CTRL_DATA
SDVO Present
01 = XOR Mode Enabled
10 = All-Z Mode Enabled
11 = Normal operation (default)
0 = Dynamic ODT disabled
1 = Dynamic ODT enabled (default)
0 = Normal mode (default; lanes numbered in order)
1 = Lane reversed
0 = Only SDVO or PCI Express is operational (default)
1 = SDVO and PCI Express operate simultaneously through
the PCI Express Graphics attach port
0 = No SDVO Card Present (default)
1 = SDVO Card Present
NOTES:
1.
All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK
(PWROK) signal.
2.
Default values do not require pull-up/pull-down resistors.
3.
Pull-up/Pull-down resistor value should be 4-KΩ ±5%.
4.
Pull-up rail for CFG[17:0] is 1.05S V.
5.
Pull-up rail for CFG[20:18] is 3.3S V.
§
External Design Specification
Intel Confidential
205
Chipset Strapping Configuration
206
Intel Confidential
External Design Specification
Ballout and Package Information
19
Ballout and Package
Information
19.1
Chipset Ballout Diagrams
Figure 58.
Chipset Ballout Diagram (Top View) Upper Left Quadrant
BL
BK
BJ
51
50
49
VSS_SC
B5
NC
NC
NC
NC
SB_DQ2
1
NC
SB_DQ1
6
VSS
SA_DQ1
3
VSS
SB_DQ1
1
BC
SB_DQ
S#1
VSS
SB_DQ9
BB
AY
VSS
SB_DQ1
3
AW
SB_DQ3 SB_DQ2 PWROK
SB_DQ6 SB_DQ7
SB_DQ
S0
AT
SB_DQ1
SB_DQ4 SB_DQ5
41
SB_DQ2 SB_DQ2 SB_DQ2
2
3
8
VSS
SA_DQ2
1
VSS
VSS
SA_DQ3
SA_DQ2
2
VSS
SA_DM
1
SB_DQ SB_DQ SB_DQ3
S3
S#3
1
VSS
SA_DQ
S2
VSS
SB_DQ0
CL_RST
#
SA_DQ5
VSS
SA_DQ0
DMI_RX
P0
VSS
DMI_TX DMI_TX
N3
P3
AK
AJ
AH
VCC_R VCC_R PEG_R
XR_DMI XR_DMI X#13
AG
VSS
VSS
PEG_R
X13
DMI_TX DMI_TX
P0
N0
PEG_R
X12
VSS
VSS
VSS
PEG_R PEG_TX PEG_TX
X14
#15
15
PEG_R PEG_R
X#12
X#14
VSS
SB_MA1
VCC_S
M
VCC_S VCC_S
M
M
VCCA_
SB_MA7
SM_CK
VCC_S
M
VCCA_
SM_CK
VSS
VSS
SA_DQ
S#3
VCC_S
M
VCC_S VCC_S
M
M
VSS
VCC_S
M
SM_CK
E1
SA_DM
3
SA_DQ2 VCC_S
7
M
SA_DQ2
4
VSS
VSS
VCC_S
M
VCC
VSS
SB_MA6 SA_MA9
SB_MA8
SM_CK
#0
VSS
VCC_A
XM
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VSS
SM_CK
0
VCC_S VCC_S
M
M
VCC
SM_CK SA_MA1
E0
1
VCC_S
M
VSS
VCC_A
XD
VCC_A VCC_A VCC_A
XM
XD
XD
VCC_A
XG_NC
TF
VCC_A VCC_A VCC_A
XM_NC XM_NC XM_NC
TF
TF
TF
VCC_A VCC_A
VCC_N
XM_NC XM_NC
CTF
TF
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_N VCC_N VCC_N
CTF
CTF
CTF
VCC_N
CTF
VCC_A
XM
VSS
VSS
VCC_N VCC_N
CTF
CTF
VCC_N
CTF
VSS
VCC
VSS
VCC
VCC_A
XM
VCC_N VCC_N VCC_N
CTF
CTF
CTF
VCC_N
CTF
VCC
VCC
VCC
VCC
VCC_A
XG
VCC_N VSS_N
CTF
CTF
VCC_N
CTF
VCC
VSS
VSS
VSS
VCC_A
XG
VCC_N VCC_N
CTF
CTF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VCC_A
XM_NC
TF
VSS
VCC_A
VSS_N
XD_NC
CTF
TF
VCC_A
VSS_N
XM_NC
CTF
TF
VSS_N
CTF
VSS
RSVD
DMI_RX DMI_RX
P1
N1
PEG_TX
#13
PEG_TX
13
VSS
VCC_S
M
RSVD
DMI_TX DMI_TX
N2
P2
VSS
VCC_S
M
SA_DQ3
0
SA_DQ2 SA_DQ3
6
1
DMI_TX DMI_TX
P1
N1
PEG_R PEG_R
X15
X#15
VSS
SA_BS2
SA_DQ
S3
DMI_RX DMI_RX
N2
P2
VSS
SA_MA1
2
SA_MA6
VCC_S
M_LF2
RSVD
VCC_N
CTF
RSVD
VCC_N
CTF
VCC
VSS
VSS
AF
External Design Specification
VCC_S VCC_S
M
M
26
SA_MA3
VCC_S
M
CL_DAT
A
VCC_D
MI
VSS
VCC_S VCC_S
M
M
VSS
VSS
VCC_S
M
27
SA_MA5 SA_MA2
VCC_S
M
VCC_N VCC_N
CTF
CTF
VSS
VSS
SA_MA1
4
VCC_S
M
VSS
DMI_RX DMI_RX DMI_RX
N0
N3
P3
28
SA_MA8
SB_MA1
1
SA_DQ2
9
SA_DQ4
29
SB_MA9
VSS
VSS
30
VCC_S VCC_S
M
M
VSS
SA_DQ2 SA_DQ2
8
5
CL_PW
SA_DQ6
ROK
31
VCC_S VCC_S VCC_S
M
M
M
VSS
VSS
32
VCC_S
M
SM_CK
VCC_S
SB_BS2
E4
M
VSS
AL
VSS
VSS
33
SM_RC
OMP_V
OL
SM_RC
VCC_S VCC_S VCC_S VCC_S
OMP_V
M
M
M
M
OH
SB_DQ2 SB_DQ2
6
7
VSS
VSS
34
SM_CK
E3
VSS
SA_DQ SA_DQ SA_DM
S#0
S0
0
35
SB_DQ3
0
VCC_S VCC_S
M
M
SB_MA1
2
VSS
36
SA_DQ1 VCC_S
9
M_LF3
SA_DM
2
VCC_S
SA_DQ1
SA_DQ1
M_LF1
6
SA_DQ7
37
VSS
SA_DQ2
3
SA_DQ1 SA_DQ1
5
7
VSS
38
RSVD
SA_DQ1
8
SA_DQ8
VSS
SB_DQ2 SB_DQ2
4
9
SA_DQ2
0
VSS
39
SB_DM
3
VSS
SA_DQ1
0
SA_DQ
S#1
40
SB_DQ2
5
VSS
CL_VRE
CL_CLK
F
AM
42
SA_DQ2
SB_DM SM_VR
0
EF
VSS
AP
AN
SB_DQ
S#0
VSS
VSS
SA_DQ1
2
VSS
SB_DQ1
SB_DQ1
SB_DQ8
2
0
VSS
43
SB_DQ1
9
SA_DQ
S#2
BA
AV
VSS
44
SA_DQ1 SB_DQ1 SB_DQ1
1
7
8
SA_DQ
S1
BD
AR
45
SB_DQ
S#2
SB_DQ2 SB_DQ SB_DM
0
S2
2
VSS
SB_DQ SB_DM
S1
1
AU
46
SB_DQ1 SB_DQ1
SA_DQ9
4
5
BF
BE
47
VSS
SA_DQ1
4
BH
BG
48
Intel Confidential
207
Ballout and Package Information
Figure 59.
25
24
Chipset Ballout Diagram (Top View) Upper Right Quadrant
23
SA_MA4
22
21
20
VSS
VSS
VCC_S VCC_S
M_CK M_CK
SA_MA7
VCC_S VCC_S
M_CK M_CK
19
RSVD
RSVD
SA_BS1
VSS
SB_MA4
SB_MA5
SB_MA1
4
SM_CS
#0
RSVD
VSS
VSS
SM_CK
3
VSS
VSS
VSS
VCC_A
XD
VCC_A
XD
VSS
VSS
SB_BS1
VSS
SA_BS0
SM_CK
#1
SA_WE
#
SM_CS
#1
VSS
SM_CK
#4
RSVD
VCCA_
SB_MA3
SM
SM_CK
4
RSTIN#
VCCA_
SM
VCC_A VCC_A
XM
XM
VSS
VCC_A
XM
VCC_A VCC_A
XG
XG
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
VSS
VSS
XG_NC
TF
VCC_A
VCC_A
VSS
XG_NC
XG
TF
VCC_A
VCC_A VCC_A
XG_NC
XG
XG
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
10
9
VSS
8
SB_DQ4
1
SB_DQ4
0
7
6
SB_DQ
S5
VSS
SB_DQ
S#5
VSS
3
2
1
SB_DQ4
3
5
NC
NC
VSS_SC
B4
SB_DQ4
2
SB_DQ5
2
NC
NC
BK
SB_DQ5
5
NC
BJ
VSS
SB_DQ5
0
SB_DQ4 SB_DM SB_DQ4
6
5
7
VSS
SA_DQ4
4
SA_DQ SA_DQ SB_DQ4
S#5
S5
9
SA_DM
5
SA_DQ4
1
VSS
SB_DQ3 SB_DQ3 SB_DQ3
6
8
5
SA_DQ
S4
VSS
SA_DQ3
8
SA_DM
4
SB_RAS
#
SA_DQ3
2
SA_DQ4 SA_DQ4
2
6
VSS
VCC_S SB_DQ5
M_LF5
4
SA_DQ4
7
VSS
SA_DQ5
3
SA_DQ4
8
SB_DQ5
6
SA_DQ3
4
SA_DQ4
3
SA_DQ4 SA_DQ5 SA_DM
9
2
6
SA_DQ4 VCC_S
5
M_LF6
VSS
VSS
SM_VR
EF
SA_DQ3
5
SA_DQ3
3
RSVD
SA_DQ3
7
RSVD
VSS
SA_DQ6
0
SA_DQ5 VCC_S SA_DQ5
1
M_LF7
0
SA_DQ5 SA_DQ5
6
5
VSS
VSS
VSS
VCC_A
XG_NC
TF
SA_DQ6 SA_DQ5 SA_DQ6
3
9
1
RSVD
VSS
RSVD
VSS
SA_DQ6 SA_DQ5 HPLL_C
2
8
LK#
VSS
SA_DM
7
HPLL_C
LK
VSS
VSS
208
VSS
VCC_A
XG
VSS
VCC_A
XG_NC
TF
AR
AP
VSS
AN
AM
VSS
AL
AK
H_D#50
VCC_A
XG_NC
TF
VSS
H_D#63 H_D#53
VSS
H_DSTB
H_D#48
P#3
H_DSTB
N#3
VSS
H_D#58 H_D#56 H_D#54
H_D#49
VSS
H_D#55
H_D#61 H_D#59
VSS
H_D#47
VSS
AU
AT
SB_DQ5
8
VCCA_
MPLL
VCCA_
HPLL
AW
AV
VSS
SA_DQ SA_DQ
S7
S#7
SA_DQ5 VCCD_
7
HPLL
VSS
BA
AY
VSS
SB_DQ5 SB_DQ6
9
3
SA_DQ5
4
VSS
SB_DQ6
2
BC
BB
VSS
SB_DQ SB_DQ
S#7
S7
VSS
VCCA_
VSS_N
SM_NC
CTF
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
VCC_A
VSS_N
XG_NC
CTF
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
VCC_A
VSS_N
XG_NC
CTF
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
SB_DM
7
BE
BD
SB_DQ6 SB_DQ6
1
0
SA_DQ3
6
VSS
VSS
VSS
BG
BF
VSS
SB_DQ5 SA_DQ
7
S6
SA_DQ3
9
VSS
SB_DQ
S6
SB_DQ5 SA_DQ
1
S#6
VSS
VSS
SB_DQ5
3
VSS
BL
BH
VSS
SB_DQ4 SB_DM SB_DQ
8
6
S#6
SM_CS SB_DQ3 SB_DQ3 SA_DQ4
#3
7
3
0
SA_DQ
S#4
4
VSS
VSS
VCCA_ VCCA_ VCCA_
SM
SM
SM
VCCA_
SM_NC
TF
VCC_A
XG_NC
TF
SB_DQ
S4
SB_MA1 SB_DQ3
3
9
VCC_A
XG
VCC_A
VSS_N
XG_NC
CTF
TF
VCC_A VCC_A
XM_NC XG_NC
TF
TF
VSS
VSS
VCCA_ VCCA_ VCCA_
SM
SM
SM
VCC_A
VSS_N
XG_NC
CTF
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
11
VSS
SB_DM
4
SA_RAS SB_CAS SM_OD
#
#
T3
VSS
12
SM_RC SB_DQ3 SB_DQ SB_DQ3 SB_DQ4 SB_DQ4
OMP#
2
S#4
4
5
4
SB_MA1 SM_CS
0
#2
SB_RC
SB_BS0
VEN#
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VSS
13
VSS
VSS
SA_RC
VEN#
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
14
VCC_S
M_LF4
SM_CK
1
VSS
15
SM_RC
OMP
SA_MA1 SM_OD SM_OD
3
T1
T2
SA_MA1
SB_WE
SB_MA0
0
#
RSVD
16
VSS
SA_MA1
VCC_A VCCA_ VCCA_
XD
SM
SM
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VSS
RSVD
VSS
SM_CK
#3
RSVD
SM_OD
T0
RSVD
RSVD
VSS
17
SA_CAS
#
RSVD SA_MA0 RSVD
RSVD
SB_MA2
18
VSS
VCC_A
VSS_N
XG_NC
CTF
TF
H_D#62 VTTLF3
VSS
AJ
AH
AG
AF
Intel Confidential
External Design Specification
Ballout and Package Information
Figure 60.
PEG_TX PEG_TX
14
#14
AE
AD
VCC_PE
G
VSS
PEG_TX
10
VSS
PEG_TX PEG_TX
11
#11
AC
AB
Chipset Ballout Diagram (Top View) Lower Left Quadrant
VSS
VSS
PEG_R PEG_TX
X#10
12
PEG_TX PEG_R
#10
X10
VSS
VSS
PEG_R PEG_TX
X#11
#9
PEG_TX PEG_R
#12
X11
VSS
VCC_N
CTF
VSS
VCC_AX
G
VCC_N VCC_N
CTF
CTF
VCC_N
CTF
VCC
VCC
VCC_AX VCC_AX
G
G
VCC_N
CTF
VSS
VSS
VCC_AX
G
VSS
VSS
VSS
VCC_AX
G
VSS
VCC_AX
G
VCC_AX
G
PEG_TX
9
PEG_R PEG_R
X#8
X8
VCC_N VCC_N VSS_NC
CTF
CTF
TF
VCC_N VCC_N
CTF
CTF
AA
VSS
Y
W
VCCA_P
EG_PLL
PEG_TX PEG_TX
#3
3
VSS
PEG_R PEG_R
X#1
X1
VSS
B
A
VSS
VSS
PEG_R PEG_TX
X3
5
PEG_TX PEG_R
2
X#3
VSS
VSS
VSS
VSS
PEG_R
X#2
PEG_TX
#0
VSS
PEG_R
X2
PEG_TX
0
VSS
VSS
PEG_C
OMPI
PEG_C
OMPO
LVDS_V LVDS_V
REFH
REFL
VCC_AX VCC_AX
G_NCTF G_NCTF
VCC_AX
G_NCTF
VCC_N VCC_N VSS_NC
CTF
CTF
TF
VCC_N VCC_N VSS_NC
CTF
CTF
TF
VCC_AX VCC_AX
G_NCTF G_NCTF
VCC_AX
G_NCTF
VCC_N VCC_N
CTF
CTF
PEG_TX VSS_NC
1
TF
VSS
VSS
VSS
LVDS_I
BG
VSS
LVDSA_ LVDSA_
DATA3 CLK#
LVDSA_
DATA#3
RSVD
NC
NC
NC
51
50
49
48
LVDSB_
DATA#1
LVDSB_
DATA1
47
VSS
L_VDD_
EN
VCCD_L L_BKLT
VDS
_CTRL
PM_EXT
_TS#1
VSS
PM_BM ICH_SY CLKRE
_BUSY# NC#
Q#
LVDSB_
CLK
VSS
LVDSA_ LVDSB_
CLK
DATA3
DPLL_R
EF_CLK
#
VSS
LVDSB_ LVDSB_
DATA#2 DATA#3
DPLL_R VSSA_L VCC_H GFX_VI
EF_CLK VDS
V
D3
46
External Design Specification
45
VSS
44
43
VSS
VCC_H
V
VCCA_L
VDS
42
CFG19
41
VSS
VSS
39
RSVD
VSS
RSVD
TEST1
VSS
38
37
Intel Confidential
VSS
36
35
CFG0
VSS
VCCD_
QDAC
VCCD_T
VDAC
VSS
CFG1
VSS
CFG18
CRT_G
REEN
VCC_SY
NC
CRT_G
REEN#
CRT_BL
UE
TVC_RT
N
TVC_DA
C
VSS
TVB_RT
N
VSS
VSS
TVB_DA
C
CRT_HS
YNC
CRT_RE
D
TVA_RT
N
CRT_VS
YNC
CRT_RE
D#
VSS
TVA_DA
C
VSS
VCCA_T
VB_DAC
VSS
CRT_BL
UE#
VSS
VSS
VSS
RSVD
RSVD
VSS
VSS
VSS
VCC_AX
G_NCTF
VSS_NC
TF
VSS
VCC
CRT_D
DC_CLK
L_DDC_
DATA
GFX_VI
D1
40
VSS
GFX_VR GFX_VI
_EN
D0
GFX_VI L_DDC_
D2
CLK
VCC_N VSS_NC
CTF
TF
VCC_N
CTF
VCCD_
CRT
VSS
L_CTRL L_CTRL
_DATA _CLK
VSS
VCC_TX
_LVDS
RSVD
SDVO_
CTRL_C
LK
CRT_D
DPRSLP
DC_DAT
VR
A
L_BKLT
_EN
LVDSB_
CLK#
LVDSB_
DATA2
TEST2
PM_EXT
CFG20
_TS#0
VSS
LVDSB_
DATA0
VSS
VSS_SC
B6
VSS
PM_DP
RSTP#
VCCD_L
VDS
LVDSB_
DATA#0
VSS
VSS
TV_DC
ONSEL1
RSVD
SDVO_
CTRL_D
ATA
LVDSA_ LVDSA_
DATA#2 DATA2
VCCA_
DPLLA
VSS
TV_DC
ONSEL0
PEG_CL PEG_CL
K#
K
VSS
DPLL_R DPLL_R
VCCA_
EF_SSC EF_SSC
DPLLB
LK
LK#
VSS
VCC_N VCC_N VCC_N
CTF
CTF
CTF
VCC_N VCC_N
CTF
CTF
VSS
LVDS_V
BG
VSS
VSS
NC
VCC_N VCC_N VCC_AX
CTF
CTF G_NCTF
RSVD
VSS
VSS
VCC_AX
G
VCC_N VCC_N VCC_N
CTF
CTF
CTF
PEG_R PEG_TX
X#5
#1
PEG_TX PEG_R
#5
X5
VCC_N
CTF
VSS
PEG_TX
#8
RSVD
LVDSA_ LVDSA_
DATA#1 DATA1
D
C
PEG_R PEG_TX
X#7
8
VSS
LVDSA_ LVDSA_
DATA#0 DATA0
F
E
VSS
VSS
PEG_TX PEG_R
6
X7
PEG_R PEG_R
X#0
X0
H
G
VSS
VCCA_P VSSA_P
EG_BG EG_BG
K
J
PEG_R PEG_TX
X#6
#6
VSS
M
L
VSS
PEG_TX PEG_R
#7
X6
VCCD_
PEG_TX
PEG_PL
#2
L
VSS
PEG_TX PEG_TX
4
#4
P
N
VSS
PEG_R PEG_R
X#4
X4
T
R
PEG_R PEG_TX
X9
7
VCC_PE VCC_PE
G
G
V
U
VSS
VCC_PE VCC_PE PEG_R
G
G
X#9
VCC_AX
G
VSS_NC VCC_N VCC_N
TF
CTF
CTF
VSS
CRT_TV
O_IREF
VSS
VCCA_
VSSA_D
RSVD CRT_DA
AC_BG
C
VCCA_
CRT_DA
C
34
33
32
VSS
VSS
VCCA_
DAC_B
G
31
30
29
VCCA_T
VCCA_T
VC_DA
VB_DAC
C
VCCA_T
VC_DA
C
28
27
26
209
Ballout and Package Information
Figure 61.
Chipset Ballout Diagram (Top View) Lower Right Quadrant
VSS
VCC_A VCC_A
XG
XG
VSS
VCC_A
VCC_A VCC_A
XG_NC
XG
XG
TF
VCC_A
VCC_A
VSS
XG_NC
XG
TF
VCC_A VCC_A
XG
XG
VCC_A
XG
VSS
VSS
VCC_A
XG
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A VSS_N
XG
CTF
VSS
VCC_A VCC_A
XG_NC XG_NC
TF
TF
VSS_N
CTF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A VSS_N
XG
CTF
VCC_A VCC_A VCC_A
XG_NC XG_NC XG_NC
TF
TF
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
H_DINV
#3
H_D#52
H_D#37
VSS
H_D#39
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A
XG
CFG10
VSS
CFG2
VSS
VSS
CFG15
VSS
CFG8
VSS
VSS
H_ADST
B#1
CFG7
VSS
VCCA_T
VA_DA
C
VCCA_T
VA_DA
C
VSS
210
24
VSS
VCC_A
XG
H_A#26
H_A#15
H_A#10
VCC_A
XF
VSS
VCC_A
XF
22
21
VSS
H_A#32
VSS
VTT
H_D#36 H_D#44 H_D#46
H_D#28 H_D#18 H_D#27
H_D#17 H_D#25
VTT
VTT
H_REQ
#0
H_A#14
VSS
VTT
VTT
VTT
VTT
H_D#24
VTT
VTT
19
17
H_D#12 H_D#8
H_A#6 H_D#10
VSS
H_A#3
VSS
VSS
VSS
H_DSTB
P#2
VSS
H_D#30
AE
VSS
AD
AC
AB
VTT
VSS
RSVD
H_D#15
VSS
VTT
VTT
VTT
VTT
VTT
VTT
VTT
VSS
VSS
P
H_D#23 H_D#26 H_D#31
N
H_D#20 H_D#16
M
VSS
H_DINV
#0
VSS
H_DPW
H_D#4
R#
H_LOC
K#
H_ADS#
VSS
H_D#13
H_D#2
VSS
15
VSS
H_A#5
H_DBS
Y#
H_REQ
#4
H_A#4
VSS
H_REQ
#2
VSS
14
13
12
11
H_AVR
EF
H_DEFE
R#
H_BNR#
H_HITM
#
H_DVR
EF
10
Intel Confidential
9
8
VSS
VTTLF1
NC
VSS_SC
B1
4
3
J
G
F
NC
E
D
H_SWIN VSS_SC
G
B2
5
L
H
VSS
H_RCO VSS_SC
MP
B3
VSS
6
R
K
H_D#21
VSS
H_TRD H_CPU
Y#
RST#
7
VSS
H_D#7 VTTLF2
H_D#0
U
T
VTT
H_D#9
H_D#1
H_CPU
H_HIT#
SLP#
H_RS#2 H_RS#1
VSS
H_D#5
H_D#6
H_BPRI
#
VSS
VSS
H_A#7 H_A#11
VSS
VSS
H_REQ
H_RS#0
#1
H_DINV
#1
V
VTT
H_DSTB H_DSTB
N#1
P#1
VSS
RSVD
W
VTT
VSS
H_DRD
Y#
Y
H_SCO H_SCO
MP#
MP
VSS
H_D#22
H_DSTB
H_D#3
N#0
VSS
VSS
VSS
H_BRE
Q#
VSS
16
H_DSTB
N#2
H_D#43
H_DSTB
P#0
H_REQ
#3
VSS
18
VSS
H_A#9
VSS
VSS
VSS
VSS
H_D#29
H_D#11
H_A#34 H_A#27 H_A#29 H_A#20 H_A#30 H_A#16 H_A#13
H_A#33
20
H_A#25
H_A#8
H_A#23
VCC_A
XF
23
VSS
RSVD
CFG9
H_D#33 H_D#45
VSS
H_D#14
H_ADST
B#0
H_A#31
CFG3
VSS
VSS
VTT
H_A#12
CFG14 H_A#28
CFG4
VSS
25
H_A#22
VSS
CFG13
VTT
VCC_A
XG
H_A#24
H_A#21
CFG5
VSS
VSS
H_A#17
CFG12
H_D#60
H_D#19
H_A#18
CFG16
CFG11
H_D#35
VSS
H_D#41
H_A#19
THERM
H_A#35
TRIP#
CFG6
VSS
H_D#57
VSS
AA
VCC_A
XG_NC
TF
VCC_A
XG_NC
TF
VCC_A VCC_A
XG_NC XG_NC
TF
TF
VSS
CFG17
VSS
VCC_A
VCC_A
XG_NC
XG_NC
TF
TF
VCC_A
VCC_A
XG_NC
XG_NC
TF
TF
VCC_A VCC_A VCC_A
XG_NC XG_NC XG_NC
TF
TF
TF
H_D#51
H_D#34
H_D#40 H_D#42
VCC_A VCC_A
XG
XG
VCC_A VCC_A
VCC_A
XG_NC XG_NC
XG_NC
TF
TF
TF
VCC_A
VCC_A
VSS_N
XG_NC
XG_NC
CTF
TF
TF
VCC_A
VCC_A VCC_A VCC_A
XG_NC
XG_NC XG_NC XG_NC
TF
TF
TF
TF
VSS
H_DINV
H_D#32 H_D#38
#2
C
B
A
2
1
External Design Specification
Ballout and Package Information
19.2
Chipset Ball List (Listed by Interface)
19.2.1
Analog TV-out
Signal
TV_DCONSEL0
19.2.2
Ball
Signal
Ball
TVA_RTN
F27
TVC_DAC
K27
TV_DCONSEL1
P33
TVB_DAC
G27
TVC_RTN
L27
TVA_DAC
E27
TVB_RTN
J27
CRT DAC
Ball
Signal
Ball
Signal
Ball
CRT_BLUE
H32
CRT_GREEN#
J29
CRT_RED#
E29
CRT_BLUE#
G32
CRT_HSYNC
F33
CRT_TVO_IREF
C32
CRT_GREEN
K29
CRT_RED
F29
CRT_VSYNC
E33
DDC & GMBus
Signal
19.2.4
Signal
M35
Signal
19.2.3
Ball
Ball
Signal
Ball
Signal
Ball
CRT_DDC_CLK
K33
L_CTRL_DATA
E40
SDVO_CTRL_CLK
H35
CRT_DDC_DATA
G35
L_DDC_CLK
C37
SDVO_CTRL_DATA
K36
L_CTRL_CLK
E39
L_DDC_DATA
D35
DMI
Signal
Ball
Signal
Ball
Signal
Ball
DMI_RXN0
AN47
DMI_RXP2
AN41
DMI_TXN3
AM44
DMI_RXN1
AJ38
DMI_RXP3
AN45
DMI_TXP0
AJ47
DMI_RXN2
AN42
DMI_TXN0
AJ46
DMI_TXP1
AJ42
DMI_RXN3
AN46
DMI_TXN1
AJ41
DMI_TXP2
AM39
DMI_RXP0
AM47
DMI_TXN2
AM40
DMI_TXP3
AM43
DMI_RXP1
AJ39
External Design Specification
Intel Confidential
211
Ballout and Package Information
19.2.5
Host Interface
Signal
212
Ball
Signal
Ball
Signal
Ball
H_A#10
G17
H_D#13
H5
H_D#56
AJ6
H_A#11
C14
H_D#14
P13
H_D#57
AE7
H_A#12
K16
H_D#15
K9
H_D#58
AJ7
H_A#13
B13
H_D#16
M2
H_D#59
AJ2
H_A#14
L16
H_D#17
W10
H_D#6
G4
H_A#15
J17
H_D#18
Y8
H_D#60
AE5
H_A#16
B14
H_D#19
V4
H_D#61
AJ3
H_A#17
K19
H_D#2
G7
H_D#62
AH2
H_A#18
P15
H_D#20
M3
H_D#63
AH13
H_A#19
R17
H_D#21
J1
H_D#7
F3
H_A#20
B16
H_D#22
N5
H_D#8
N8
H_A#21
H20
H_D#23
N3
H_D#9
H2
H_A#22
L19
H_D#24
W6
H_DBSY#
C10
H_A#23
D17
H_D#25
W9
H_DEFER#
D6
H_A#24
M17
H_D#26
N2
H_DINV#0
K5
H_A#25
N16
H_D#27
Y7
H_DINV#1
L2
H_A#26
J19
H_D#28
Y9
H_DINV#2
AD13
H_A#27
B18
H_D#29
P4
H_DINV#3
AE13
H_A#28
E19
H_D#3
M6
H_DPWR#
H8
H_A#29
B17
H_D#30
W3
H_DRDY#
K7
H_A#3
J13
H_D#31
N1
H_DSTBN#0
M7
H_A#30
B15
H_D#32
AD12
H_DSTBN#1
K3
H_A#31
E17
H_D#33
AE3
H_DSTBN#2
AD2
H_A#32
C18
H_D#34
AD9
H_DSTBN#3
AH11
H_A#33
A19
H_D#35
AC9
H_DSTBP#0
L7
H_A#34
B19
H_D#36
AC7
H_DSTBP#1
K2
H_A#35
N19
H_D#37
AC14
H_DSTBP#2
AC2
H_A#4
B11
H_D#38
AD11
H_DSTBP#3
AJ10
H_A#5
C11
H_D#39
AC11
H_DVREF
A9
H_A#6
M11
H_D#4
H7
H_HIT#
E4
H_A#7
C15
H_D#40
AB2
H_HITM#
C6
H_A#8
F16
H_D#41
AD7
H_LOCK#
G10
H_A#9
L13
H_D#42
AB1
H_RCOMP
C2
H_ADS#
G12
H_D#43
Y3
H_REQ#0
M14
H_ADSTB#0
H17
H_D#44
AC6
H_REQ#1
E13
H_ADSTB#1
G20
H_D#45
AE2
H_REQ#2
A11
Intel Confidential
External Design Specification
Ballout and Package Information
Signal
19.2.6
Ball
Signal
Ball
B9
H_D#46
AC5
H_REQ#3
H13
H_BNR#
C8
H_D#47
AG3
H_REQ#4
B12
H_BPRI#
E8
H_D#48
AJ9
H_RS#0
E12
H_BREQ#
F12
H_D#49
AH8
H_RS#1
D7
H_CPURST#
B6
H_D#5
H3
H_RS#2
D8
H_CPUSLP#
E5
H_D#50
AJ14
H_SCOMP
W1
H_D#0
E2
H_D#51
AE9
H_SCOMP#
W2
H_D#1
G2
H_D#52
AE11
H_SWING
B3
H_D#10
M10
H_D#53
AH12
H_TRDY#
B7
H_D#11
N12
H_D#54
AJ5
THERMTRIP#
N20
H_D#12
N9
H_D#55
AH5
LVDS
Ball
Signal
Ball
Signal
Ball
L_BKLT_CTRL
J40
LVDSA_DATA#0
G51
LVDSB_CLK#
D44
L_BKLT_EN
H39
LVDSA_DATA#1
E51
LVDSB_DATA#0
G44
L_VDD_EN
K40
LVDSA_DATA#2
F49
LVDSB_DATA#1
B47
LVDS_IBG
L41
LVDSA_DATA#3
C48
LVDSB_DATA#2
B45
LVDS_VBG
L43
LVDSA_DATA0
G50
LVDSB_DATA#3
B44
LVDS_VREFH
N41
LVDSA_DATA1
E50
LVDSB_DATA0
E44
LVDS_VREFL
N40
LVDSA_DATA2
F48
LVDSB_DATA1
A47
LVDSA_CLK
C45
LVDSA_DATA3
D47
LVDSB_DATA2
A45
LVDSA_CLK#
D46
LVDSB_CLK
E42
LVDSB_DATA3
C44
Intel Management Engine Interface
Signal
19.2.8
Ball
H_AVREF
Signal
19.2.7
Signal
Ball
Signal
Ball
CL_CLK
AM49
CL_PWROK
AT43
CL_DATA
AK50
CL_RST#
AN49
Signal
CL_VREF
Ball
AM50
Memory Interface
Signal
SA_BS0
Ball
BB19
Signal
SA_DQS#6
Ball
BC1
Signal
SB_DQ47
Ball
BJ6
SA_BS1
BK19
SA_DQS#7
AP2
SB_DQ48
BF4
SA_BS2
BF29
SA_DQS0
AT46
SB_DQ49
BH5
External Design Specification
Intel Confidential
213
Ballout and Package Information
Signal
214
Ball
Signal
Ball
Signal
Ball
SA_CAS#
BL17
SA_DQS1
BE48
SB_DQ5
AN50
SA_DM0
AT45
SA_DQS2
BB43
SB_DQ50
BG1
SA_DM1
BD44
SA_DQS3
BC37
SB_DQ51
BC2
SA_DM2
BD42
SA_DQS4
BB16
SB_DQ52
BK3
SA_DM3
AW38
SA_DQS5
BH6
SB_DQ53
BE4
SA_DM4
AW13
SA_DQS6
BB2
SB_DQ54
BD3
SA_DM5
BG8
SA_DQS7
AP3
SB_DQ55
BJ2
SA_DM6
AY5
SA_MA0
BJ19
SB_DQ56
BA3
SA_DM7
AN6
SA_MA1
BD20
SB_DQ57
BB3
SA_DQ0
AR43
SA_MA10
BC19
SB_DQ58
AR1
SA_DQ1
AW44
SA_MA11
BE28
SB_DQ59
AT3
SA_DQ10
BG47
SA_MA12
BG30
SB_DQ6
AV50
SA_DQ11
BJ45
SA_MA13
BJ16
SB_DQ60
AY2
SA_DQ12
BB47
SA_MA14
BJ29
SB_DQ61
AY3
SA_DQ13
BG50
SA_MA2
BK27
SB_DQ62
AU2
SA_DQ14
BH49
SA_MA3
BH28
SB_DQ63
AT2
SA_DQ15
BE45
SA_MA4
BL24
SB_DQ7
AV49
SA_DQ16
AW43
SA_MA5
BK28
SB_DQ8
BA50
SA_DQ17
BE44
SA_MA6
BJ27
SB_DQ9
BB50
SA_DQ18
BG42
SA_MA7
BJ25
SB_DQS#0
AU50
SA_DQ19
BE40
SA_MA8
BL28
SB_DQS#1
BC50
SA_DQ2
BA45
SA_MA9
BA28
SB_DQS#2
BL45
SA_DQ20
BF44
SA_RAS#
BE18
SB_DQS#3
BK38
SA_DQ21
BH45
SA_RCVEN#
AY20
SB_DQS#4
BK12
SA_DQ22
BG40
SA_WE#
BA19
SB_DQS#5
BK7
SA_DQ23
BF40
SB_BS0
AY17
SB_DQS#6
BF2
SA_DQ24
AR40
SB_BS1
BG18
SB_DQS#7
AV3
SA_DQ25
AW40
SB_BS2
BG36
SB_DQS0
AT50
SA_DQ26
AT39
SB_CAS#
BE17
SB_DQS1
BD50
SA_DQ27
AW36
SB_DM0
AR50
SB_DQS2
BK46
SA_DQ28
AW41
SB_DM1
BD49
SB_DQS3
BK39
SA_DQ29
AY41
SB_DM2
BK45
SB_DQS4
BJ12
SA_DQ3
AY46
SB_DM3
BL39
SB_DQS5
BL7
SA_DQ30
AV38
SB_DM4
BH12
SB_DQS6
BE2
SA_DQ31
AT38
SB_DM5
BJ7
SB_DQS7
AV2
SA_DQ32
AV13
SB_DM6
BF3
SB_MA0
BC18
SA_DQ33
AT13
SB_DM7
AW2
SB_MA1
BG28
SA_DQ34
AW11
SB_DQ0
AP49
SB_MA10
BG17
SA_DQ35
AV11
SB_DQ1
AR51
SB_MA11
BE37
Intel Confidential
External Design Specification
Ballout and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
SA_DQ36
AU15
SB_DQ10
BA49
SB_MA12
BA39
SA_DQ37
AT11
SB_DQ11
BE50
SB_MA13
BG13
SA_DQ38
BA13
SB_DQ12
BA51
SB_MA14
BE24
SA_DQ39
BA11
SB_DQ13
AY49
SB_MA2
BG25
SA_DQ4
AR41
SB_DQ14
BF50
SB_MA3
AW17
SA_DQ40
BE10
SB_DQ15
BF49
SB_MA4
BF25
SA_DQ41
BD10
SB_DQ16
BJ50
SB_MA5
BE25
SA_DQ42
BD8
SB_DQ17
BJ44
SB_MA6
BA29
SA_DQ43
AY9
SB_DQ18
BJ43
SB_MA7
BC28
SA_DQ44
BG10
SB_DQ19
BL43
SB_MA8
AY28
SA_DQ45
AW9
SB_DQ2
AW50
SB_MA9
BD37
SA_DQ46
BD7
SB_DQ20
BK47
SB_RAS#
AV16
SA_DQ47
BB9
SB_DQ21
BK49
SB_RCVEN#
AY18
SA_DQ48
BB5
SB_DQ22
BK43
SB_WE#
BC17
SA_DQ49
AY7
SB_DQ23
BK42
SM_CK#0
AW30
SA_DQ5
AR45
SB_DQ24
BJ41
SM_CK#1
BA23
SA_DQ50
AT5
SB_DQ25
BL41
SM_CK#3
AW25
SA_DQ51
AT7
SB_DQ26
BJ37
SM_CK#4
AW23
SA_DQ52
AY6
SB_DQ27
BJ36
SM_CK0
AV29
SA_DQ53
BB7
SB_DQ28
BK41
SM_CK1
BB23
SA_DQ54
AR5
SB_DQ29
BJ40
SM_CK3
BA25
SA_DQ55
AR8
SB_DQ3
AW51
SM_CK4
AV23
SA_DQ56
AR9
SB_DQ30
BL35
SM_CKE0
BE29
SA_DQ57
AN3
SB_DQ31
BK37
SM_CKE1
AY32
SA_DQ58
AM8
SB_DQ32
BK13
SM_CKE3
BD39
SA_DQ59
AN10
SB_DQ33
BE11
SM_CKE4
BG37
SA_DQ6
AT42
SB_DQ34
BK11
SM_CS#0
BG20
SA_DQ60
AT9
SB_DQ35
BC11
SM_CS#1
BK16
SA_DQ61
AN9
SB_DQ36
BC13
SM_CS#2
BG16
SA_DQ62
AM9
SB_DQ37
BE12
SM_CS#3
BE13
SA_DQ63
AN11
SB_DQ38
BC12
SM_ODT0
BH18
SA_DQ7
AW47
SB_DQ39
BG12
SM_ODT1
BJ15
SA_DQ8
BB45
SB_DQ4
AN51
SM_ODT2
BJ14
SA_DQ9
BF48
SB_DQ40
BJ10
SM_ODT3
BE16
SA_DQS#0
AT47
SB_DQ41
BL9
SM_RCOMP
BL15
SA_DQS#1
BD47
SB_DQ42
BK5
SM_RCOMP#
BK14
SA_DQS#2
BC41
SB_DQ43
BL5
SM_RCOMP_VOH
BK31
External Design Specification
Intel Confidential
215
Ballout and Package Information
Signal
19.2.9
Ball
Signal
Ball
BA37
SB_DQ44
BK9
SM_RCOMP_VOL
BL31
SA_DQS#4
BA16
SB_DQ45
BK10
SM_VREF
AW4
SA_DQS#5
BH7
SB_DQ46
BJ8
SM_VREF
AR49
No Connects
Ball
Signal
Ball
Signal
Ball
NC
BJ51
NC
A50
NC
BL49
NC
BK2
NC
A49
NC
BL3
NC
E1
NC
BK51
NC
BL2
NC
A5
NC
BK50
NC
BK1
NC
C51
NC
BL50
NC
BJ1
NC
B50
PCI Express Based Graphics
Signal
216
Ball
SA_DQS#3
Signal
19.2.10
Signal
Ball
Signal
Ball
Signal
Ball
PEG_COMPI
N43
PEG_RX12
AH47
PEG_TX#4
PEG_COMPO
M43
PEG_RX13
AG49
PEG_TX#5
T42
PEG_RX#0
J51
PEG_RX14
AH45
PEG_TX#6
Y43
PEG_RX#1
L51
PEG_RX15
AG42
PEG_TX#7
W46
PEG_RX#10
AD44
PEG_RX2
M47
PEG_TX#8
W38
PEG_RX#11
AD40
PEG_RX3
U44
PEG_TX#9
AD39
PEG_RX#12
AG46
PEG_RX4
T49
PEG_TX0
M45
PEG_RX#13
AH49
PEG_RX5
T41
PEG_TX1
T38
PEG_RX#14
AG45
PEG_RX6
W45
PEG_TX10
AD47
PEG_RX#15
AG41
PEG_RX7
W41
PEG_TX11
AC50
PEG_RX#2
N47
PEG_RX8
AB50
PEG_TX12
AD43
PEG_RX#3
T45
PEG_RX9
Y48
PEG_TX13
AG39
PEG_RX#4
T50
PEG_TX#0
N45
PEG_TX14
AE50
PEG_RX#5
U40
PEG_TX#1
U39
PEG_TX15
AH43
PEG_RX#6
Y44
PEG_TX#10
AC46
PEG_TX2
T46
PEG_RX#7
Y40
PEG_TX#11
AC49
PEG_TX3
N50
PEG_RX#8
AB51
PEG_TX#12
AC42
PEG_TX4
R51
PEG_RX#9
W49
PEG_TX#13
AH39
PEG_TX5
U43
PEG_RX0
J50
PEG_TX#14
AE49
PEG_TX6
W42
Intel Confidential
R50
External Design Specification
Ballout and Package Information
Signal
19.2.11
Signal
Ball
Signal
Ball
PEG_RX1
L50
PEG_TX#15
AH44
PEG_TX7
Y47
PEG_RX10
AC45
PEG_TX#2
U47
PEG_TX8
Y39
PEG_RX11
AC41
PEG_TX#3
N51
PEG_TX9
AC38
PLL
Signal
19.2.12
Ball
Ball
Signal
Ball
Signal
Ball
DPLL_REF_CLK
B42
DPLL_REF_SSCLK#
H47
PEG_CLK
K44
DPLL_REF_CLK#
C42
HPLL_CLK
AM5
PEG_CLK#
K45
DPLL_REF_SSCLK
H48
HPLL_CLK#
AM7
Power and Ground
Signal
Ball
Signal
Ball
Signal
Ball
VCC
AT35
VCC_SM
BK35
VSS
AH9
VCC
AT34
VCC_SM
BK34
VSS
AH7
VCC
AK32
VCC_SM
BK33
VSS
AH3
VCC
AJ31
VCC_SM
BK32
VSS
AG50
VCC
AJ28
VCC_SM
BJ34
VSS
AG47
VCC
AH32
VCC_SM
BJ33
VSS
AG43
VCC
AH31
VCC_SM
BJ32
VSS
AG38
VCC
AH29
VCC_SM
BH35
VSS
AG2
VCC
AH28
VCC_SM
BH34
VSS
AF31
VCC
AF32
VCC_SM
BH32
VSS
AF29
VCC
AC32
VCC_SM
BG35
VSS
AF28
VCC
AC31
VCC_SM
BG33
VSS
AF24
VCC
R30
VCC_SM
BG32
VSS
AF23
VCC_AXD
AU28
VCC_SM
BF34
VSS
AF20
VCC_AXD
AU24
VCC_SM
BF33
VSS
AE14
VCC_AXD
AT30
VCC_SM
BE35
VSS
AE10
VCC_AXD
AT29
VCC_SM
BE33
VSS
AE6
VCC_AXD
AT25
VCC_SM
BE32
VSS
AD50
VCC_AXD
AT23
VCC_SM
BD35
VSS
AD49
VCC_AXD_NCTF
AR29
VCC_SM
BD32
VSS
AD45
VCC_AXF
B23
VCC_SM
BC35
VSS
AD41
VCC_AXF
B21
VCC_SM
BC33
VSS
AD32
VCC_AXF
A21
VCC_SM
BC32
VSS
AD29
VCC_AXG
AN14
VCC_SM
BB33
VSS
AD26
External Design Specification
Intel Confidential
217
Ballout and Package Information
Signal
218
Ball
Signal
Ball
Signal
Ball
VCC_AXG
AJ20
VCC_SM
BA35
VSS
AD21
VCC_AXG
AH26
VCC_SM
BA33
VSS
AD8
VCC_AXG
AH24
VCC_SM
BA32
VSS
AD5
VCC_AXG
AH23
VCC_SM
AY35
VSS
AD3
VCC_AXG
AH21
VCC_SM
AW35
VSS
AD1
VCC_AXG
AH20
VCC_SM
AW33
VSS
AC47
VCC_AXG
AF26
VCC_SM
AV33
VSS
AC43
VCC_AXG
AF21
VCC_SM
AU35
VSS
AC39
VCC_AXG
AD31
VCC_SM
AU33
VSS
AC13
VCC_AXG
AD28
VCC_SM
AU32
VSS
AC10
VCC_AXG
AD24
VCC_SM
AU30
VSS
AC3
VCC_AXG
AD23
VCC_SM_CK
BK24
VSS
AB32
VCC_AXG
AD20
VCC_SM_CK
BK23
VSS
AB31
VCC_AXG
AC29
VCC_SM_CK
BJ24
VSS
AB28
VCC_AXG
AC28
VCC_SM_CK
BJ23
VSS
AB26
VCC_AXG
AC26
VCC_SM_LF1
AW45
VSS
AB23
VCC_AXG
AC24
VCC_SM_LF2
BC39
VSS
AB20
VCC_AXG
AC23
VCC_SM_LF3
BE39
VSS
AA32
VCC_AXG
AC21
VCC_SM_LF4
BD17
VSS
AA29
VCC_AXG
AC20
VCC_SM_LF5
BD4
VSS
AA24
VCC_AXG
AB29
VCC_SM_LF6
AW8
VSS
AA21
VCC_AXG
AB24
VCC_SM_LF7
AT6
VSS
Y50
VCC_AXG
AB21
VCC_SYNC
J32
VSS
Y49
VCC_AXG
AA31
VCC_TX_LVDS
A43
VSS
Y45
VCC_AXG
AA28
VCCA_CRT_DAC
B33
VSS
Y41
VCC_AXG
AA26
VCCA_CRT_DAC
A33
VSS
Y13
VCC_AXG
AA23
VCCA_DAC_BG
A30
VSS
Y11
VCC_AXG
AA20
VCCA_DPLLA
B49
VSS
Y5
VCC_AXG
Y12
VCCA_DPLLB
H49
VSS
Y2
VCC_AXG
W14
VCCA_HPLL
AL2
VSS
W47
VCC_AXG
W13
VCCA_LVDS
A41
VSS
W43
VCC_AXG
T14
VCCA_MPLL
AM2
VSS
W39
VCC_AXG
R20
VCCA_PEG_BG
K50
VSS
W11
VCC_AXG_NCTF
AR26
VCCA_PEG_PLL
U51
VSS
W7
VCC_AXG_NCTF
AR24
VCCA_SM
AW18
VSS
W5
VCC_AXG_NCTF
AR23
VCCA_SM
AV19
VSS
V3
VCC_AXG_NCTF
AR21
VCCA_SM
AU19
VSS
V2
VCC_AXG_NCTF
AR20
VCCA_SM
AU18
VSS
U50
VCC_AXG_NCTF
AP24
VCCA_SM
AU17
VSS
U45
Intel Confidential
External Design Specification
Ballout and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
VCC_AXG_NCTF
AP23
VCCA_SM
AT22
VSS
U41
VCC_AXG_NCTF
AP21
VCCA_SM
AT21
VSS
T47
VCC_AXG_NCTF
AP20
VCCA_SM
AT19
VSS
T43
VCC_AXG_NCTF
AP19
VCCA_SM
AT18
VSS
T39
VCC_AXG_NCTF
AP17
VCCA_SM
AT17
VSS
R49
VCC_AXG_NCTF
AP16
VCCA_SM_CK
BC29
VSS
P50
VCC_AXG_NCTF
AP15
VCCA_SM_CK
BB29
VSS
P29
VCC_AXG_NCTF
AM23
VCCA_SM_NCTF
AR17
VSS
P23
VCC_AXG_NCTF
AM21
VCCA_SM_NCTF
AR16
VSS
P19
VCC_AXG_NCTF
AM20
VCCA_TVA_DAC
C25
VSS
P3
VCC_AXG_NCTF
AM19
VCCA_TVA_DAC
B25
VSS
P2
VCC_AXG_NCTF
AM16
VCCA_TVB_DAC
C27
VSS
N49
VCC_AXG_NCTF
AM15
VCCA_TVB_DAC
B27
VSS
N44
VCC_AXG_NCTF
AL23
VCCA_TVC_DAC
B28
VSS
N39
VCC_AXG_NCTF
AL21
VCCA_TVC_DAC
A28
VSS
N36
VCC_AXG_NCTF
AL20
VCCD_CRT
M32
VSS
N32
VCC_AXG_NCTF
AL19
VCCD_HPLL
AN2
VSS
N29
VCC_AXG_NCTF
AL17
VCCD_LVDS
J41
VSS
N17
VCC_AXG_NCTF
AL16
VCCD_LVDS
H42
VSS
N14
VCC_AXG_NCTF
AK19
VCCD_PEG_PLL
U48
VSS
N11
VCC_AXG_NCTF
AK16
VCCD_TVDAC
L29
VSS
N7
VCC_AXG_NCTF
AJ19
VCCD_QDAC
N28
VSS
M50
VCC_AXG_NCTF
AJ17
VSS
T33
VSS
M49
VCC_AXG_NCTF
AJ16
VSS
R28
VSS
M46
VCC_AXG_NCTF
AH19
VSS
T31
VSS
M42
VCC_AXG_NCTF
AH17
VSS
T29
VSS
M28
VCC_AXG_NCTF
AH16
VSS
BL47
VSS
M9
VCC_AXG_NCTF
AH15
VSS
BL37
VSS
M5
VCC_AXG_NCTF
AF19
VSS
BL22
VSS
L49
VCC_AXG_NCTF
AF16
VSS
BL19
VSS
L33
VCC_AXG_NCTF
AD17
VSS
BL13
VSS
L28
VCC_AXG_NCTF
AD16
VSS
BL11
VSS
L24
VCC_AXG_NCTF
AD15
VSS
BK44
VSS
L20
VCC_AXG_NCTF
AC19
VSS
BK40
VSS
L17
VCC_AXG_NCTF
AC17
VSS
BK36
VSS
L3
VCC_AXG_NCTF
AC16
VSS
BK29
VSS
L1
VCC_AXG_NCTF
AB19
VSS
BK25
VSS
K47
VCC_AXG_NCTF
AB16
VSS
BK17
VSS
K12
VCC_AXG_NCTF
AA17
VSS
BK15
VSS
K8
External Design Specification
Intel Confidential
219
Ballout and Package Information
Signal
220
Ball
Signal
Ball
Signal
Ball
VCC_AXG_NCTF
AA16
VSS
BK8
VSS
J39
VCC_AXG_NCTF
Y31
VSS
BK6
VSS
J35
VCC_AXG_NCTF
Y29
VSS
BJ46
VSS
J33
VCC_AXG_NCTF
Y28
VSS
BJ42
VSS
J28
VCC_AXG_NCTF
Y26
VSS
BJ38
VSS
J24
VCC_AXG_NCTF
Y24
VSS
BJ13
VSS
J16
VCC_AXG_NCTF
Y23
VSS
BJ11
VSS
J11
VCC_AXG_NCTF
Y21
VSS
BJ4
VSS
J2
VCC_AXG_NCTF
Y20
VSS
BH46
VSS
H50
VCC_AXG_NCTF
Y19
VSS
BH44
VSS
H45
VCC_AXG_NCTF
Y17
VSS
BH30
VSS
H28
VCC_AXG_NCTF
Y16
VSS
BH17
VSS
H24
VCC_AXG_NCTF
Y15
VSS
BH8
VSS
H4
VCC_AXG_NCTF
V29
VSS
BG51
VSS
G48
VCC_AXG_NCTF
V28
VSS
BG48
VSS
G45
VCC_AXG_NCTF
V26
VSS
BG39
VSS
G42
VCC_AXG_NCTF
V24
VSS
BG29
VSS
G33
VCC_AXG_NCTF
V23
VSS
BG24
VSS
G29
VCC_AXG_NCTF
V21
VSS
BG19
VSS
G28
VCC_AXG_NCTF
V20
VSS
BG5
VSS
G24
VCC_AXG_NCTF
V19
VSS
BG2
VSS
G19
VCC_AXG_NCTF
V17
VSS
BF36
VSS
G16
VCC_AXG_NCTF
V16
VSS
BF16
VSS
G13
VCC_AXG_NCTF
U26
VSS
BF12
VSS
G8
VCC_AXG_NCTF
U23
VSS
BE51
VSS
G1
VCC_AXG_NCTF
U21
VSS
BE42
VSS
F50
VCC_AXG_NCTF
U20
VSS
BE30
VSS
F40
VCC_AXG_NCTF
U19
VSS
BE23
VSS
F36
VCC_AXG_NCTF
U17
VSS
BE19
VSS
F19
VCC_AXG_NCTF
U16
VSS
BE8
VSS
F4
VCC_AXG_NCTF
U15
VSS
BE1
VSS
E47
VCC_AXG_NCTF
T25
VSS
BD48
VSS
E32
VCC_AXG_NCTF
T23
VSS
BD45
VSS
E28
VCC_AXG_NCTF
T22
VSS
BD28
VSS
E24
VCC_AXG_NCTF
T21
VSS
BD13
VSS
E16
VCC_AXG_NCTF
T19
VSS
BD5
VSS
E10
VCC_AXG_NCTF
T18
VSS
BD2
VSS
D49
VCC_AXG_NCTF
T17
VSS
BC51
VSS
D45
VCC_AXM
AT33
VSS
BC40
VSS
D39
Intel Confidential
External Design Specification
Ballout and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
VCC_AXM
AT31
VSS
BC36
VSS
D32
VCC_AXM
AK29
VSS
BC25
VSS
D24
VCC_AXM
AK24
VSS
BC24
VSS
D13
VCC_AXM
AK23
VSS
BC16
VSS
D3
VCC_AXM
AJ26
VSS
BB49
VSS
C50
VCC_AXM
AJ23
VSS
BB44
VSS
C46
VCC_AXM_NCTF
AR33
VSS
BB40
VSS
C41
VCC_AXM_NCTF
AR32
VSS
BB25
VSS
C36
VCC_AXM_NCTF
AR31
VSS
BB12
VSS
C33
VCC_AXM_NCTF
AP33
VSS
BB8
VSS
C29
VCC_AXM_NCTF
AP32
VSS
BA24
VSS
C28
VCC_AXM_NCTF
AP31
VSS
BA18
VSS
C19
VCC_AXM_NCTF
AP29
VSS
BA17
VSS
C16
VCC_AXM_NCTF
AM33
VSS
BA2
VSS
C12
VCC_AXM_NCTF
AM32
VSS
BA1
VSS
C7
VCC_AXM_NCTF
AM31
VSS
AY50
VSS
B46
VCC_AXM_NCTF
AM29
VSS
AY47
VSS
B43
VCC_AXM_NCTF
AM28
VSS
AY45
VSS
B38
VCC_AXM_NCTF
AM26
VSS
AY43
VSS
B35
VCC_AXM_NCTF
AL32
VSS
AY42
VSS
B30
VCC_AXM_NCTF
AL31
VSS
AY37
VSS
B29
VCC_AXM_NCTF
AL29
VSS
AY24
VSS
B24
VCC_AXM_NCTF
AL28
VSS
AY10
VSS
B20
VCC_AXM_NCTF
AL26
VSS
AW32
VSS
B10
VCC_AXM_NCTF
AL24
VSS
AW29
VSS
B8
VCC_DMI
AJ50
VSS
AW24
VSS
B5
VCC_HV
C40
VSS
AW16
VSS
A24
VCC_HV
B40
VSS
AW12
VSS
A17
VCC_NCTF
AR36
VSS
AW7
VSS
A15
VCC_NCTF
AR35
VSS
AW5
VSS
A13
VCC_NCTF
AP36
VSS
AW1
VSS_NCTF
AR28
VCC_NCTF
AP35
VSS
AV48
VSS_NCTF
AR19
VCC_NCTF
AM35
VSS
AV39
VSS_NCTF
AR15
VCC_NCTF
AL35
VSS
AV25
VSS_NCTF
AP28
VCC_NCTF
AL33
VSS
AU51
VSS_NCTF
AP26
VCC_NCTF
AK37
VSS
AU49
VSS_NCTF
AM24
VCC_NCTF
AK36
VSS
AU36
VSS_NCTF
AM17
VCC_NCTF
AK35
VSS
AU29
VSS_NCTF
AK17
VCC_NCTF
AK33
VSS
AU23
VSS_NCTF
AF35
External Design Specification
Intel Confidential
221
Ballout and Package Information
Signal
222
Ball
Signal
Ball
Signal
Ball
VCC_NCTF
AJ36
VSS
AU3
VSS_NCTF
AF17
VCC_NCTF
AJ35
VSS
AU1
VSS_NCTF
AD37
VCC_NCTF
AJ33
VSS
AT49
VSS_NCTF
AD19
VCC_NCTF
AH37
VSS
AT41
VSS_NCTF
AB35
VCC_NCTF
AH36
VSS
AT27
VSS_NCTF
AB17
VCC_NCTF
AH35
VSS
AT14
VSS_NCTF
AA19
VCC_NCTF
AH33
VSS
AT10
VSS_NCTF
V35
VCC_NCTF
AF36
VSS
AR47
VSS_NCTF
V31
VCC_NCTF
AF33
VSS
AR44
VSS_NCTF
U28
VCC_NCTF
AD36
VSS
AR39
VSS_NCTF
U24
VCC_NCTF
AD35
VSS
AR11
VSS_NCTF
T37
VCC_NCTF
AD33
VSS
AR7
VSS_NCTF
T27
VCC_NCTF
AC36
VSS
AR2
VSS_SCB1
A3
VCC_NCTF
AC35
VSS
AP50
VSS_SCB2
B2
VCC_NCTF
AC33
VSS
AP48
VSS_SCB3
C1
VCC_NCTF
AB37
VSS
AP4
VSS_SCB4
BL1
VCC_NCTF
AB36
VSS
AN43
VSS_SCB5
BL51
VCC_NCTF
AB33
VSS
AN39
VSS_SCB6
A51
VCC_NCTF
AA36
VSS
AN38
VSSA_DAC_BG
B32
VCC_NCTF
AA35
VSS
AN7
VSSA_LVDS
B41
VCC_NCTF
AA33
VSS
AN5
VSSA_PEG_BG
K49
VCC_NCTF
Y37
VSS
AN1
VTT
U13
VCC_NCTF
Y36
VSS
AM45
VTT
U12
VCC_NCTF
Y35
VSS
AM41
VTT
U11
VCC_NCTF
Y33
VSS
AM13
VTT
U9
VCC_NCTF
Y32
VSS
AM11
VTT
U8
VCC_NCTF
V37
VSS
AM4
VTT
U7
VCC_NCTF
V36
VSS
AM3
VTT
U5
VCC_NCTF
V33
VSS
AL1
VTT
U3
VCC_NCTF
V32
VSS
AK51
VTT
U2
VCC_NCTF
U36
VSS
AK31
VTT
U1
VCC_NCTF
U35
VSS
AK28
VTT
T13
VCC_NCTF
U33
VSS
AK26
VTT
T11
VCC_NCTF
U32
VSS
AK21
VTT
T10
VCC_NCTF
U31
VSS
AK20
VTT
T9
VCC_NCTF
U29
VSS
AJ49
VTT
T7
VCC_NCTF
T35
VSS
AJ45
VTT
T6
VCC_NCTF
T34
VSS
AJ43
VTT
T5
VCC_NCTF
T30
VSS
AJ32
VTT
T3
Intel Confidential
External Design Specification
Ballout and Package Information
Signal
19.2.13
19.2.14
Ball
Signal
Ball
Signal
Ball
VCC_PEG
AD51
VSS
AJ29
VTT
T2
VCC_PEG
W51
VSS
AJ24
VTT
R3
VCC_PEG
W50
VSS
AJ21
VTT
R2
VCC_PEG
V50
VSS
AJ13
VTT
R1
VCC_PEG
V49
VSS
AJ11
VTTLF1
A7
VCC_RXR_DMI
AH51
VSS
AH41
VTTLF2
F2
VCC_RXR_DMI
AH50
VSS
AH40
VTTLF3
AH1
VCC_SM
BL33
Reserved and Test
Signal
Ball
Signal
Ball
Signal
Ball
RSVD
A35
RSVD
BF19
RSVD
AM12
RSVD
B37
RSVD
BH20
RSVD
AN13
RSVD
B36
RSVD
BK18
RSVD
AR37
RSVD
B34
RSVD
BJ18
RSVD
AM36
RSVD
C34
RSVD
AW20
RSVD
AL36
RSVD
BF23
RSVD
BK20
RSVD
AM37
RSVD
BG23
RSVD
P36
RSVD
D20
RSVD
BJ20
RSVD
P37
RSVD
B51
RSVD
BK22
RSVD
R35
TEST1
A37
TEST2
R32
RSVD
BC23
RSVD
N35
RSVD
BD24
RSVD
J12
RSVD
BH39
RSVD
H10
RSVD
AR12
RSVD
AR13
Strappings
Signal
CFG0
Ball
P27
Signal
CFG8
Ball
J20
Signal
CFG15
Ball
K23
CFG1
N27
CFG9
C20
CFG16
M20
CFG3
C21
CFG10
R24
CFG17
M24
CFG4
C23
CFG11
L23
CFG18
L32
CFG5
F23
CFG12
J23
CFG19
N33
CFG6
N23
CFG13
E23
CFG2
N24
CFG7
G23
CFG14
E20
CFG20
L35
External Design Specification
Intel Confidential
223
Ballout and Package Information
19.2.15
Reset and Miscellaneous
Signal
19.3
Signal
Ball
Signal
Ball
CLKREQ#
G39
GFX_VID3
B39
PM_EXT_TS#0
L36
DPRSLPVR
G36
GFX_VR_EN
E36
PM_EXT_TS#1
J36
GFX_VID0
E35
ICH_SYNC#
G40
PWROK
AW49
GFX_VID1
A39
PMSYNC#
(PM_BM_BUSY#)
G41
RSTIN#
AV20
GFX_VID2
C38
PM_DPRSTP#
L39
Chipset Ball List (Listed by Ball)
Ball
224
Ball
Signal
Ball
Signal
Ball
Signal
A11
H_REQ#2
V16
VCC_AXG_NCTF
AR37
RSVD
A13
VSS
V17
VCC_AXG_NCTF
AR39
VSS
A15
VSS
V19
VCC_AXG_NCTF
AR40
SA_DQ24
A17
VSS
V2
VSS
AR41
SA_DQ4
A19
H_A#33
V20
VCC_AXG_NCTF
AR43
SA_DQ0
A21
VCC_AXF
V21
VCC_AXG_NCTF
AR44
VSS
A24
VSS
V23
VCC_AXG_NCTF
AR45
SA_DQ5
A28
VCCA_TVC_DAC
V24
VCC_AXG_NCTF
AR47
VSS
A3
VSS_SCB1
V26
VCC_AXG_NCTF
AR49
SM_VREF
A30
VCCA_DAC_BG
V28
VCC_AXG_NCTF
AR5
SA_DQ54
A33
VCCA_CRT_DAC
V29
VCC_AXG_NCTF
AR50
SB_DM0
A35
RSVD
V3
VSS
AR51
SB_DQ1
A37
TEST1
V31
VSS_NCTF
AR7
VSS
A39
GFX_VID1
V32
VCC_NCTF
AR8
SA_DQ55
A41
VCCA_LVDS
V33
VCC_NCTF
AR9
SA_DQ56
A43
VCC_TX_LVDS
V35
VSS_NCTF
AT10
VSS
A45
LVDSB_DATA2
V36
VCC_NCTF
AT11
SA_DQ37
A47
LVDSB_DATA1
V37
VCC_NCTF
AT13
SA_DQ33
A49
NC
V4
H_D#19
AT14
VSS
A5
NC
V49
VCC_PEG
AT17
VCCA_SM
A50
NC
V50
VCC_PEG
AT18
VCCA_SM
A51
VSS_SCB6
W1
H_SCOMP
AT19
VCCA_SM
A7
VTTLF1
W10
H_D#17
AT2
SB_DQ63
A9
H_DVREF
W11
VSS
AT21
VCCA_SM
B10
VSS
W13
VCC_AXG
AT22
VCCA_SM
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
B11
H_A#4
W14
VCC_AXG
AT23
VCC_AXD
B12
H_REQ#4
W2
H_SCOMP#
AT25
VCC_AXD
B13
H_A#13
W3
H_D#30
AT27
VSS
B14
H_A#16
W38
PEG_TX#8
AT29
VCC_AXD
B15
H_A#30
W39
VSS
AT3
SB_DQ59
B16
H_A#20
W41
PEG_RX7
AT30
VCC_AXD
B17
H_A#29
W42
PEG_TX6
AT31
VCC_AXM
B18
H_A#27
W43
VSS
AT33
VCC_AXM
B19
H_A#34
W45
PEG_RX6
AT34
VCC
B2
VSS_SCB2
W46
PEG_TX#7
AT35
VCC
B20
VSS
W47
VSS
AT38
SA_DQ31
B21
VCC_AXF
W49
PEG_RX#9
AT39
SA_DQ26
B23
VCC_AXF
W5
VSS
AT41
VSS
B24
VSS
W50
VCC_PEG
AT42
SA_DQ6
B25
VCCA_TVA_DAC
W51
VCC_PEG
AT43
CL_PWROK
B27
VCCA_TVB_DAC
W6
H_D#24
AT45
SA_DM0
B28
VCCA_TVC_DAC
W7
VSS
AT46
SA_DQS0
B29
VSS
W9
H_D#25
AT47
SA_DQS#0
B3
H_SWING
Y11
VSS
AT49
VSS
B30
VSS
Y12
VCC_AXG
AT5
SA_DQ50
B32
VSSA_DAC_BG
Y13
VSS
AT50
SB_DQS0
B33
VCCA_CRT_DAC
Y15
VCC_AXG_NCTF
AT6
VCC_SM_LF7
B34
RSVD
Y16
VCC_AXG_NCTF
AT7
SA_DQ51
B35
VSS
Y17
VCC_AXG_NCTF
AT9
SA_DQ60
B36
RSVD
Y19
VCC_AXG_NCTF
AU1
VSS
B37
RSVD
Y2
VSS
AU15
SA_DQ36
B38
VSS
Y20
VCC_AXG_NCTF
AU17
VCCA_SM
B39
GFX_VID3
Y21
VCC_AXG_NCTF
AU18
VCCA_SM
B40
VCC_HV
Y23
VCC_AXG_NCTF
AU19
VCCA_SM
B41
VSSA_LVDS
Y24
VCC_AXG_NCTF
AU2
SB_DQ62
B42
DPLL_REF_CLK
Y26
VCC_AXG_NCTF
AU23
VSS
B43
VSS
Y28
VCC_AXG_NCTF
AU24
VCC_AXD
B44
LVDSB_DATA#3
Y29
VCC_AXG_NCTF
AU28
VCC_AXD
B45
LVDSB_DATA#2
Y3
H_D#43
AU29
VSS
B46
VSS
Y31
VCC_AXG_NCTF
AU3
VSS
B47
LVDSB_DATA#1
Y32
VCC_NCTF
AU30
VCC_SM
B49
VCCA_DPLLA
Y33
VCC_NCTF
AU32
VCC_SM
B5
VSS
Y35
VCC_NCTF
AU33
VCC_SM
B50
NC
Y36
VCC_NCTF
AU35
VCC_SM
External Design Specification
Intel Confidential
225
Ballout and Package Information
Ball
226
Signal
Ball
Signal
Ball
Signal
B51
RSVD
Y37
VCC_NCTF
AU36
VSS
B6
H_CPURST#
Y39
PEG_TX8
AU49
VSS
B7
H_TRDY#
Y40
PEG_RX#7
AU50
SB_DQS#0
B8
VSS
Y41
VSS
AU51
VSS
B9
H_AVREF
Y43
PEG_TX#6
AV11
SA_DQ35
C1
VSS_SCB3
Y44
PEG_RX#6
AV13
SA_DQ32
C10
H_DBSY#
Y45
VSS
AV16
SB_RAS#
C11
H_A#5
Y47
PEG_TX7
AV19
VCCA_SM
C12
VSS
Y48
PEG_RX9
AV2
SB_DQS7
C14
H_A#11
Y49
VSS
AV20
RSTIN#
C15
H_A#7
Y5
VSS
AV23
SM_CK4
C16
VSS
Y50
VSS
AV25
VSS
C18
H_A#32
Y7
H_D#27
AV29
SM_CK0
C19
VSS
Y8
H_D#18
AV3
SB_DQS#7
C2
H_RCOMP
Y9
H_D#28
AV33
VCC_SM
C20
CFG9
AA16
VCC_AXG_NCTF
AV38
SA_DQ30
C21
CFG3
AA17
VCC_AXG_NCTF
AV39
VSS
C23
CFG4
AA19
VSS_NCTF
AV48
VSS
C25
VCCA_TVA_DAC
AA20
VCC_AXG
AV49
SB_DQ7
C27
VCCA_TVB_DAC
AA21
VSS
AV50
SB_DQ6
C28
VSS
AA23
VCC_AXG
AW1
VSS
C29
VSS
AA24
VSS
AW11
SA_DQ34
C32
CRT_TVO_IREF
AA26
VCC_AXG
AW12
VSS
C33
VSS
AA28
VCC_AXG
AW13
SA_DM4
C34
RSVD
AA29
VSS
AW16
VSS
C36
VSS
AA31
VCC_AXG
AW17
SB_MA3
C37
L_DDC_CLK
AA32
VSS
AW18
VCCA_SM
C38
GFX_VID2
AA33
VCC_NCTF
AW2
SB_DM7
C40
VCC_HV
AA35
VCC_NCTF
AW20
RSVD
C41
VSS
AA36
VCC_NCTF
AW23
SM_CK#4
C42
DPLL_REF_CLK#
AB1
H_D#42
AW24
VSS
C44
LVDSB_DATA3
AB16
VCC_AXG_NCTF
AW25
SM_CK#3
C45
LVDSA_CLK
AB17
VSS_NCTF
AW29
VSS
C46
VSS
AB19
VCC_AXG_NCTF
AW30
SM_CK#0
C48
LVDSA_DATA#3
AB2
H_D#40
AW32
VSS
C50
VSS
AB20
VSS
AW33
VCC_SM
C51
NC
AB21
VCC_AXG
AW35
VCC_SM
C6
H_HITM#
AB23
VSS
AW36
SA_DQ27
C7
VSS
AB24
VCC_AXG
AW38
SA_DM3
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
C8
H_BNR#
AB26
VSS
AW4
SM_VREF
D13
VSS
AB28
VSS
AW40
SA_DQ25
D17
H_A#23
AB29
VCC_AXG
AW41
SA_DQ28
D20
RSVD
AB31
VSS
AW43
SA_DQ16
D24
VSS
AB32
VSS
AW44
SA_DQ1
D3
VSS
AB33
VCC_NCTF
AW45
VCC_SM_LF1
D32
VSS
AB35
VSS_NCTF
AW47
SA_DQ7
D35
L_DDC_DATA
AB36
VCC_NCTF
AW49
PWROK
D39
VSS
AB37
VCC_NCTF
AW5
VSS
D44
LVDSB_CLK#
AB50
PEG_RX8
AW50
SB_DQ2
D45
VSS
AB51
PEG_RX#8
AW51
SB_DQ3
D46
LVDSA_CLK#
AC10
VSS
AW7
VSS
D47
LVDSA_DATA3
AC11
H_D#39
AW8
VCC_SM_LF6
D49
VSS
AC13
VSS
AW9
SA_DQ45
D6
H_DEFER#
AC14
H_D#37
AY10
VSS
D7
H_RS#1
AC16
VCC_AXG_NCTF
AY17
SB_BS0
D8
H_RS#2
AC17
VCC_AXG_NCTF
AY18
SB_RCVEN#
E1
NC
AC19
VCC_AXG_NCTF
AY2
SB_DQ60
E10
VSS
AC2
H_DSTBP#2
AY20
SA_RCVEN#
E12
H_RS#0
AC20
VCC_AXG
AY24
VSS
E13
H_REQ#1
AC21
VCC_AXG
AY28
SB_MA8
E16
VSS
AC23
VCC_AXG
AY3
SB_DQ61
E17
H_A#31
AC24
VCC_AXG
AY32
SM_CKE1
E19
H_A#28
AC26
VCC_AXG
AY35
VCC_SM
E2
H_D#0
AC28
VCC_AXG
AY37
VSS
E20
CFG14
AC29
VCC_AXG
AY41
SA_DQ29
E23
CFG13
AC3
VSS
AY42
VSS
E24
VSS
AC31
VCC
AY43
VSS
E27
TVA_DAC
AC32
VCC
AY45
VSS
E28
VSS
AC33
VCC_NCTF
AY46
SA_DQ3
E29
CRT_RED#
AC35
VCC_NCTF
AY47
VSS
E32
VSS
AC36
VCC_NCTF
AY49
SB_DQ13
E33
CRT_VSYNC
AC38
PEG_TX9
AY5
SA_DM6
E35
GFX_VID0
AC39
VSS
AY50
VSS
E36
GFX_VR_EN
AC41
PEG_RX11
AY6
SA_DQ52
E39
L_CTRL_CLK
AC42
PEG_TX#12
AY7
SA_DQ49
E4
H_HIT#
AC43
VSS
AY9
SA_DQ43
E40
L_CTRL_DATA
AC45
PEG_RX10
BA1
VSS
E42
LVDSB_CLK
AC46
PEG_TX#10
BA11
SA_DQ39
External Design Specification
Intel Confidential
227
Ballout and Package Information
Ball
228
Signal
Ball
Signal
Ball
Signal
E44
LVDSB_DATA0
AC47
VSS
BA13
SA_DQ38
E47
VSS
AC49
PEG_TX#11
BA16
SA_DQS#4
E5
H_CPUSLP#
AC5
H_D#46
BA17
VSS
E50
LVDSA_DATA1
AC50
PEG_TX11
BA18
VSS
E51
LVDSA_DATA#1
AC6
H_D#44
BA19
SA_WE#
E8
H_BPRI#
AC7
H_D#36
BA2
VSS
F12
H_BREQ#
AC9
H_D#35
BA23
SM_CK#1
F16
H_A#8
AD1
VSS
BA24
VSS
F19
VSS
AD11
H_D#38
BA25
SM_CK3
F2
VTTLF2
AD12
H_D#32
BA28
SA_MA9
F23
CFG5
AD13
H_DINV#2
BA29
SB_MA6
F27
TVA_RTN
AD15
VCC_AXG_NCTF
BA3
SB_DQ56
F29
CRT_RED
AD16
VCC_AXG_NCTF
BA32
VCC_SM
F3
H_D#7
AD17
VCC_AXG_NCTF
BA33
VCC_SM
F33
CRT_HSYNC
AD19
VSS_NCTF
BA35
VCC_SM
F36
VSS
AD2
H_DSTBN#2
BA37
SA_DQS#3
F4
VSS
AD20
VCC_AXG
BA39
SB_MA12
F40
VSS
AD21
VSS
BA45
SA_DQ2
F48
LVDSA_DATA2
AD23
VCC_AXG
BA49
SB_DQ10
F49
LVDSA_DATA#2
AD24
VCC_AXG
BA50
SB_DQ8
F50
VSS
AD26
VSS
BA51
SB_DQ12
G1
VSS
AD28
VCC_AXG
BB12
VSS
G10
H_LOCK#
AD29
VSS
BB16
SA_DQS4
G12
H_ADS#
AD3
VSS
BB19
SA_BS0
G13
VSS
AD31
VCC_AXG
BB2
SA_DQS6
G16
VSS
AD32
VSS
BB23
SM_CK1
G17
H_A#10
AD33
VCC_NCTF
BB25
VSS
G19
VSS
AD35
VCC_NCTF
BB29
VCCA_SM_CK
G2
H_D#1
AD36
VCC_NCTF
BB3
SB_DQ57
G20
H_ADSTB#1
AD37
VSS_NCTF
BB33
VCC_SM
G23
CFG7
AD39
PEG_TX#9
BB40
VSS
G24
VSS
AD40
PEG_RX#11
BB43
SA_DQS2
G27
TVB_DAC
AD41
VSS
BB44
VSS
G28
VSS
AD43
PEG_TX12
BB45
SA_DQ8
G29
VSS
AD44
PEG_RX#10
BB47
SA_DQ12
G32
CRT_BLUE#
AD45
VSS
BB49
VSS
G33
VSS
AD47
PEG_TX10
BB5
SA_DQ48
G35
CRT_DDC_DATA
AD49
VSS
BB50
SB_DQ9
G36
DPRSLPVR
AD5
VSS
BB7
SA_DQ53
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
G39
CLKREQ#
AD50
VSS
BB8
VSS
G4
H_D#6
AD51
VCC_PEG
BB9
SA_DQ47
G40
ICH_SYNC#
AD7
H_D#41
BC1
SA_DQS#6
G41
PMSYNC#
(PM_BM_BUSY#)
AD8
VSS
BC11
SB_DQ35
G42
VSS
AD9
H_D#34
BC12
SB_DQ38
G44
LVDSB_DATA#0
AE10
VSS
BC13
SB_DQ36
G45
VSS
AE11
H_D#52
BC16
VSS
G48
VSS
AE13
H_DINV#3
BC17
SB_WE#
G50
LVDSA_DATA0
AE14
VSS
BC18
SB_MA0
G51
LVDSA_DATA#0
AE2
H_D#45
BC19
SA_MA10
G7
H_D#2
AE3
H_D#33
BC2
SB_DQ51
G8
VSS
AE49
PEG_TX#14
BC23
RSVD
H10
RSVD
AE5
H_D#60
BC24
VSS
H13
H_REQ#3
AE50
PEG_TX14
BC25
VSS
H17
H_ADSTB#0
AE6
VSS
BC28
SB_MA7
H2
H_D#9
AE7
H_D#57
BC29
VCCA_SM_CK
H20
H_A#21
AE9
H_D#51
BC32
VCC_SM
H24
VSS
AF16
VCC_AXG_NCTF
BC33
VCC_SM
H28
VSS
AF17
VSS_NCTF
BC35
VCC_SM
H3
H_D#5
AF19
VCC_AXG_NCTF
BC36
VSS
H32
CRT_BLUE
AF20
VSS
BC37
SA_DQS3
H35
SDVO_CTRL_CLK
AF21
VCC_AXG
BC39
VCC_SM_LF2
H39
L_BKLT_EN
AF23
VSS
BC40
VSS
H4
VSS
AF24
VSS
BC41
SA_DQS#2
H42
VCCD_LVDS
AF26
VCC_AXG
BC50
SB_DQS#1
H45
VSS
AF28
VSS
BC51
VSS
H47
DPLL_REF_SSCLK
#
AF29
VSS
BD10
SA_DQ41
H48
DPLL_REF_SSCLK
AF31
VSS
BD13
VSS
H49
VCCA_DPLLB
AF32
VCC
BD17
VCC_SM_LF4
H5
H_D#13
AF33
VCC_NCTF
BD2
VSS
H50
VSS
AF35
VSS_NCTF
BD20
SA_MA1
H7
H_D#4
AF36
VCC_NCTF
BD24
RSVD
H8
H_DPWR#
AG2
VSS
BD28
VSS
J1
H_D#21
AG3
H_D#47
BD3
SB_DQ54
J11
VSS
AG38
VSS
BD32
VCC_SM
J12
RSVD
AG39
PEG_TX13
BD35
VCC_SM
J13
H_A#3
AG41
PEG_RX#15
BD37
SB_MA9
External Design Specification
Intel Confidential
229
Ballout and Package Information
Ball
230
Signal
Ball
Signal
Ball
Signal
J16
VSS
AG42
PEG_RX15
BD39
SM_CKE3
J17
H_A#15
AG43
VSS
BD4
VCC_SM_LF5
J19
H_A#26
AG45
PEG_RX#14
BD42
SA_DM2
J2
VSS
AG46
PEG_RX#12
BD44
SA_DM1
J20
CFG8
AG47
VSS
BD45
VSS
J23
CFG12
AG49
PEG_RX13
BD47
SA_DQS#1
J24
VSS
AG50
VSS
BD48
VSS
J27
TVB_RTN
AH1
VTTLF3
BD49
SB_DM1
J28
VSS
AH11
H_DSTBN#3
BD5
VSS
J29
CRT_GREEN#
AH12
H_D#53
BD50
SB_DQS1
J32
VCC_SYNC
AH13
H_D#63
BD7
SA_DQ46
J33
VSS
AH15
VCC_AXG_NCTF
BD8
SA_DQ42
J35
VSS
AH16
VCC_AXG_NCTF
BE1
VSS
J36
PM_EXT_TS#1
AH17
VCC_AXG_NCTF
BE10
SA_DQ40
J39
VSS
AH19
VCC_AXG_NCTF
BE11
SB_DQ33
J40
L_BKLT_CTRL
AH2
H_D#62
BE12
SB_DQ37
J41
VCCD_LVDS
AH20
VCC_AXG
BE13
SM_CS#3
J50
PEG_RX0
AH21
VCC_AXG
BE16
SM_ODT3
J51
PEG_RX#0
AH23
VCC_AXG
BE17
SB_CAS#
K12
VSS
AH24
VCC_AXG
BE18
SA_RAS#
K16
H_A#12
AH26
VCC_AXG
BE19
VSS
K19
H_A#17
AH28
VCC
BE2
SB_DQS6
K2
H_DSTBP#1
AH29
VCC
BE23
VSS
K23
CFG15
AH3
VSS
BE24
SB_MA_14
K27
TVC_DAC
AH31
VCC
BE25
SB_MA5
K29
CRT_GREEN
AH32
VCC
BE28
SA_MA11
K3
H_DSTBN#1
AH33
VCC_NCTF
BE29
SM_CKE0
K33
CRT_DDC_CLK
AH35
VCC_NCTF
BE30
VSS
K36
SDVO_CTRL_DATA
AH36
VCC_NCTF
BE32
VCC_SM
K40
L_VDD_EN
AH37
VCC_NCTF
BE33
VCC_SM
K44
PEG_CLK
AH39
PEG_TX#13
BE35
VCC_SM
K45
PEG_CLK#
AH40
VSS
BE37
SB_MA11
K47
VSS
AH41
VSS
BE39
VCC_SM_LF3
K49
VSSA_PEG_BG
AH43
PEG_TX15
BE4
SB_DQ53
K5
H_DINV#0
AH44
PEG_TX#15
BE40
SA_DQ19
K50
VCCA_PEG_BG
AH45
PEG_RX14
BE42
VSS
K7
H_DRDY#
AH47
PEG_RX12
BE44
SA_DQ17
K8
VSS
AH49
PEG_RX#13
BE45
SA_DQ15
K9
H_D#15
AH5
H_D#55
BE48
SA_DQS1
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
L1
VSS
AH50
VCC_RXR_DMI
BE50
SB_DQ11
L13
H_A#9
AH51
VCC_RXR_DMI
BE51
VSS
L16
H_A#14
AH7
VSS
BE8
VSS
L17
VSS
AH8
H_D#49
BF12
VSS
L19
H_A#22
AH9
VSS
BF16
VSS
L2
H_DINV#1
AJ10
H_DSTBP#3
BF19
RSVD
L20
VSS
AJ11
VSS
BF2
SB_DQS#6
L23
CFG11
AJ13
VSS
BF23
RSVD
L24
VSS
AJ14
H_D#50
BF25
SB_MA4
L27
TVC_RTN
AJ16
VCC_AXG_NCTF
BF29
SA_BS2
L28
VSS
AJ17
VCC_AXG_NCTF
BF3
SB_DM6
L29
VCCD_TVDAC
AJ19
VCC_AXG_NCTF
BF33
VCC_SM
L3
VSS
AJ2
H_D#59
BF34
VCC_SM
L32
CFG18
AJ20
VCC_AXG
BF36
VSS
L33
VSS
AJ21
VSS
BF4
SB_DQ48
L35
CFG20
AJ23
VCC_AXM
BF40
SA_DQ23
L36
PM_EXT_TS#0
AJ24
VSS
BF44
SA_DQ20
L39
PM_DPRSTP#
AJ26
VCC_AXM
BF48
SA_DQ9
L41
LVDS_IBG
AJ28
VCC
BF49
SB_DQ15
L43
LVDS_VBG
AJ29
VSS
BF50
SB_DQ14
L49
VSS
AJ3
H_D#61
BG1
SB_DQ50
L50
PEG_RX1
AJ31
VCC
BG10
SA_DQ44
L51
PEG_RX#1
AJ32
VSS
BG12
SB_DQ39
L7
H_DSTBP#0
AJ33
VCC_NCTF
BG13
SB_MA13
M10
H_D#10
AJ35
VCC_NCTF
BG16
SM_CS#2
M11
H_A#6
AJ36
VCC_NCTF
BG17
SB_MA10
M14
H_REQ#0
AJ38
DMI_RXN1
BG18
SB_BS1
M17
H_A#24
AJ39
DMI_RXP1
BG19
VSS
M2
H_D#16
AJ41
DMI_TXN1
BG2
VSS
M20
CFG16
AJ42
DMI_TXP1
BG20
SM_CS#0
M24
CFG17
AJ43
VSS
BG23
RSVD
M28
VSS
AJ45
VSS
BG24
VSS
M3
H_D#20
AJ46
DMI_TXN0
BG25
SB_MA2
M32
VCCD_CRT
AJ47
DMI_TXP0
BG28
SB_MA1
M35
TV_DCONSEL0
AJ49
VSS
BG29
VSS
M42
VSS
AJ5
H_D#54
BG30
SA_MA12
M43
PEG_COMPO
AJ50
VCC_DMI
BG32
VCC_SM
M45
PEG_TX0
AJ6
H_D#56
BG33
VCC_SM
M46
VSS
AJ7
H_D#58
BG35
VCC_SM
External Design Specification
Intel Confidential
231
Ballout and Package Information
Ball
232
Signal
Ball
Signal
Ball
Signal
M47
PEG_RX2
AJ9
H_D#48
BG36
SB_BS2
M49
VSS
AK16
VCC_AXG_NCTF
BG37
SM_CKE4
M5
VSS
AK17
VSS_NCTF
BG39
VSS
M50
VSS
AK19
VCC_AXG_NCTF
BG40
SA_DQ22
M6
H_D#3
AK20
VSS
BG42
SA_DQ18
M7
H_DSTBN#0
AK21
VSS
BG47
SA_DQ10
M9
VSS
AK23
VCC_AXM
BG48
VSS
N1
H_D#31
AK24
VCC_AXM
BG5
VSS
N11
VSS
AK26
VSS
BG50
SA_DQ13
N12
H_D#11
AK28
VSS
BG51
VSS
N14
VSS
AK29
VCC_AXM
BG8
SA_DM5
N16
H_A#25
AK31
VSS
BH12
SB_DM4
N17
VSS
AK32
VCC
BH17
VSS
N19
H_A#35
AK33
VCC_NCTF
BH18
SM_ODT0
N2
H_D#26
AK35
VCC_NCTF
BH20
RSVD
N20
THERMTRIP#
AK36
VCC_NCTF
BH28
SA_MA3
N23
CFG6
AK37
VCC_NCTF
BH30
VSS
N24
CFG2
AK50
CL_DATA
BH32
VCC_SM
N27
CFG1
AK51
VSS
BH34
VCC_SM
N28
VCCD_QDAC
AL1
VSS
BH35
VCC_SM
N29
VSS
AL16
VCC_AXG_NCTF
BH39
RSVD
N3
H_D#23
AL17
VCC_AXG_NCTF
BH44
VSS
N32
VSS
AL19
VCC_AXG_NCTF
BH45
SA_DQ21
N33
CFG19
AL2
VCCA_HPLL
BH46
VSS
N35
RSVD
AL20
VCC_AXG_NCTF
BH49
SA_DQ14
N36
VSS
AL21
VCC_AXG_NCTF
BH5
SB_DQ49
N39
VSS
AL23
VCC_AXG_NCTF
BH6
SA_DQS5
N40
LVDS_VREFL
AL24
VCC_AXM_NCTF
BH7
SA_DQS#5
N41
LVDS_VREFH
AL26
VCC_AXM_NCTF
BH8
VSS
N43
PEG_COMPI
AL28
VCC_AXM_NCTF
BJ1
NC
N44
VSS
AL29
VCC_AXM_NCTF
BJ10
SB_DQ40
N45
PEG_TX#0
AL31
VCC_AXM_NCTF
BJ11
VSS
N47
PEG_RX#2
AL32
VCC_AXM_NCTF
BJ12
SB_DQS4
N49
VSS
AL33
VCC_NCTF
BJ13
VSS
N5
H_D#22
AL35
VCC_NCTF
BJ14
SM_ODT2
N50
PEG_TX3
AL36
RSVD
BJ15
SM_ODT1
N51
PEG_TX#3
AM11
VSS
BJ16
SA_MA13
N7
VSS
AM12
RSVD
BJ18
RSVD
N8
H_D#8
AM13
VSS
BJ19
SA_MA0
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
N9
H_D#12
AM15
VCC_AXG_NCTF
BJ2
SB_DQ55
P13
H_D#14
AM16
VCC_AXG_NCTF
BJ20
RSVD
P15
H_A#18
AM17
VSS_NCTF
BJ23
VCC_SM_CK
P19
VSS
AM19
VCC_AXG_NCTF
BJ24
VCC_SM_CK
P2
VSS
AM2
VCCA_MPLL
BJ25
SA_MA7
P23
VSS
AM20
VCC_AXG_NCTF
BJ27
SA_MA6
P27
CFG0
AM21
VCC_AXG_NCTF
BJ29
SA_MA_14
P29
VSS
AM23
VCC_AXG_NCTF
BJ32
VCC_SM
P3
VSS
AM24
VSS_NCTF
BJ33
VCC_SM
P33
TV_DCONSEL1
AM26
VCC_AXM_NCTF
BJ34
VCC_SM
P36
RSVD
AM28
VCC_AXM_NCTF
BJ36
SB_DQ27
P37
RSVD
AM29
VCC_AXM_NCTF
BJ37
SB_DQ26
P4
H_D#29
AM3
VSS
BJ38
VSS
P50
VSS
AM31
VCC_AXM_NCTF
BJ4
VSS
R1
VTT
AM32
VCC_AXM_NCTF
BJ40
SB_DQ29
R17
H_A#19
AM33
VCC_AXM_NCTF
BJ41
SB_DQ24
R2
VTT
AM35
VCC_NCTF
BJ42
VSS
R20
VCC_AXG
AM36
RSVD
BJ43
SB_DQ18
R24
CFG10
AM37
RSVD
BJ44
SB_DQ17
R28
VSS
AM39
DMI_TXP2
BJ45
SA_DQ11
R3
VTT
AM4
VSS
BJ46
VSS
R30
VCC
AM40
DMI_TXN2
BJ50
SB_DQ16
R32
TEST2
AM41
VSS
BJ51
NC
R35
RSVD
AM43
DMI_TXP3
BJ6
SB_DQ47
R49
VSS
AM44
DMI_TXN3
BJ7
SB_DM5
R50
PEG_TX#4
AM45
VSS
BJ8
SB_DQ46
R51
PEG_TX4
AM47
DMI_RXP0
BK1
NC
T10
VTT
AM49
CL_CLK
BK10
SB_DQ45
T11
VTT
AM5
HPLL_CLK
BK11
SB_DQ34
T13
VTT
AM50
CL_VREF
BK12
SB_DQS#4
T14
VCC_AXG
AM7
HPLL_CLK#
BK13
SB_DQ32
T17
VCC_AXG_NCTF
AM8
SA_DQ58
BK14
SM_RCOMP#
T18
VCC_AXG_NCTF
AM9
SA_DQ62
BK15
VSS
T19
VCC_AXG_NCTF
AN1
VSS
BK16
SM_CS#1
T2
VTT
AN10
SA_DQ59
BK17
VSS
T21
VCC_AXG_NCTF
AN11
SA_DQ63
BK18
RSVD
T22
VCC_AXG_NCTF
AN13
RSVD
BK19
SA_BS1
T23
VCC_AXG_NCTF
AN14
VCC_AXG
BK2
NC
T25
VCC_AXG_NCTF
AN2
VCCD_HPLL
BK20
RSVD
External Design Specification
Intel Confidential
233
Ballout and Package Information
Ball
234
Signal
Ball
Signal
Ball
Signal
T27
VSS_NCTF
AN3
SA_DQ57
BK22
RSVD
T29
VSS
AN38
VSS
BK23
VCC_SM_CK
T3
VTT
AN39
VSS
BK24
VCC_SM_CK
T30
VCC_NCTF
AN41
DMI_RXP2
BK25
VSS
T31
VSS
AN42
DMI_RXN2
BK27
SA_MA2
T33
VSS
AN43
VSS
BK28
SA_MA5
T34
VCC_NCTF
AN45
DMI_RXP3
BK29
VSS
T35
VCC_NCTF
AN46
DMI_RXN3
BK3
SB_DQ52
T37
VSS_NCTF
AN47
DMI_RXN0
BK31
SM_RCOMP_VOH
T38
PEG_TX1
AN49
CL_RST#
BK32
VCC_SM
T39
VSS
AN5
VSS
BK33
VCC_SM
T41
PEG_RX5
AN50
SB_DQ5
BK34
VCC_SM
T42
PEG_TX#5
AN51
SB_DQ4
BK35
VCC_SM
T43
VSS
AN6
SA_DM7
BK36
VSS
T45
PEG_RX#3
AN7
VSS
BK37
SB_DQ31
T46
PEG_TX2
AN9
SA_DQ61
BK38
SB_DQS#3
T47
VSS
AP15
VCC_AXG_NCTF
BK39
SB_DQS3
T49
PEG_RX4
AP16
VCC_AXG_NCTF
BK40
VSS
T5
VTT
AP17
VCC_AXG_NCTF
BK41
SB_DQ28
T50
PEG_RX#4
AP19
VCC_AXG_NCTF
BK42
SB_DQ23
T6
VTT
AP2
SA_DQS#7
BK43
SB_DQ22
T7
VTT
AP20
VCC_AXG_NCTF
BK44
VSS
T9
VTT
AP21
VCC_AXG_NCTF
BK45
SB_DM2
U1
VTT
AP23
VCC_AXG_NCTF
BK46
SB_DQS2
U11
VTT
AP24
VCC_AXG_NCTF
BK47
SB_DQ20
U12
VTT
AP26
VSS_NCTF
BK49
SB_DQ21
U13
VTT
AP28
VSS_NCTF
BK5
SB_DQ42
U15
VCC_AXG_NCTF
AP29
VCC_AXM_NCTF
BK50
NC
U16
VCC_AXG_NCTF
AP3
SA_DQS7
BK51
NC
U17
VCC_AXG_NCTF
AP31
VCC_AXM_NCTF
BK6
VSS
U19
VCC_AXG_NCTF
AP32
VCC_AXM_NCTF
BK7
SB_DQS#5
U2
VTT
AP33
VCC_AXM_NCTF
BK8
VSS
U20
VCC_AXG_NCTF
AP35
VCC_NCTF
BK9
SB_DQ44
U21
VCC_AXG_NCTF
AP36
VCC_NCTF
BL1
VSS_SCB4
U23
VCC_AXG_NCTF
AP4
VSS
BL11
VSS
U24
VSS_NCTF
AP48
VSS
BL13
VSS
U26
VCC_AXG_NCTF
AP49
SB_DQ0
BL15
SM_RCOMP
U28
VSS_NCTF
AP50
VSS
BL17
SA_CAS#
U29
VCC_NCTF
AR1
SB_DQ58
BL19
VSS
Intel Confidential
External Design Specification
Ballout and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
U3
VTT
AR11
VSS
BL2
NC
U31
VCC_NCTF
AR12
RSVD
BL22
VSS
U32
VCC_NCTF
AR13
RSVD
BL24
SA_MA4
U33
VCC_NCTF
AR15
VSS_NCTF
BL28
SA_MA8
U35
VCC_NCTF
AR16
VCCA_SM_NCTF
BL3
NC
U36
VCC_NCTF
AR17
VCCA_SM_NCTF
BL31
SM_RCOMP_VOL
U39
PEG_TX#1
AR19
VSS_NCTF
BL33
VCC_SM
U40
PEG_RX#5
AR2
VSS
BL35
SB_DQ30
U41
VSS
AR20
VCC_AXG_NCTF
BL37
VSS
U43
PEG_TX5
AR21
VCC_AXG_NCTF
BL39
SB_DM3
U44
PEG_RX3
AR23
VCC_AXG_NCTF
BL41
SB_DQ25
U45
VSS
AR24
VCC_AXG_NCTF
BL43
SB_DQ19
U47
PEG_TX#2
AR26
VCC_AXG_NCTF
BL45
SB_DQS#2
U48
VCCD_PEG_PLL
AR28
VSS_NCTF
BL47
VSS
U5
VTT
AR29
VCC_AXD_NCTF
BL49
NC
U50
VSS
AR31
VCC_AXM_NCTF
BL5
SB_DQ43
U51
VCCA_PEG_PLL
AR32
VCC_AXM_NCTF
BL50
NC
U7
VTT
AR33
VCC_AXM_NCTF
BL51
VSS_SCB5
U8
VTT
AR35
VCC_NCTF
BL7
SB_DQS5
U9
VTT
AR36
VCC_NCTF
BL9
SB_DQ41
External Design Specification
Intel Confidential
235
Ballout and Package Information
19.4
Chipset Package Information
The chipset comes in an FCBGA package, which consists of a silicon die mounted face
down on an organic substrate populated with solder balls on the bottom side.
Capacitors may be placed in the area surrounding the die. Because the die-side
capacitors are electrically conductive, and only slightly shorter than the die height, care
should be taken to avoid contacting the capacitors with electrically conductive
materials. Doing so may short the capacitors and possibly damage the device or render
it inactive.
The use of an insulating material between the capacitors and any thermal solution
should be considered to prevent capacitor shorting. An exclusion, or keep out area,
surrounds the die and capacitors, and identifies the contact area for the package. Care
should be taken to avoid contact with the package inside this area.
The chipset package is a 1299-ball FCBGA. Dimensions are in millimeters. Unless
otherwise specified, interpret the dimensions and tolerances in accordance with ASME
Y14.5-1994.
• Tolerances:
— X: ± 0.1
— XX: ± 0.05
• Angles: ± 1.0 degrees
• Package parameters: 35.0 mm x 35.0 mm
• Land metal diameter: 524 microns
• Solder resist opening: 430 microns
236
Intel Confidential
External Design Specification
Ballout and Package Information
Figure 62.
Chipset Drawing
NOTES:
1.
Capacitor Area, Handling Keep Out Zone: Handling refers to any equipment such as
pick and place, trays or shipping media. Capacitor Area Handling Keep Out Zone means all
equipment mentioned above should stay out of this area to not interfere with capacitors
that may be placed in this area.
Handling Area, Package Keep Out Zone: Package Keep Out Zone means capacitors
2.
may not be placed in this area since this is the area where we allow handling i.e. pick and
place.
§
External Design Specification
Intel Confidential
237
Ballout and Package Information
238
Intel Confidential
External Design Specification
I/O Buffer and IBIS Model Documentation
20
I/O Buffer and IBIS Model
Documentation
The I/O Buffer and IBIS Model are no longer password protected and are available on
FDBL/IBL.
§
External Design Specification
Intel Confidential
239
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