3DIC and the Hybrid Memory
Cube
Dean Klein
Micron Technology, Inc.
©2012 Micron Technology, Inc. All rights reserved. Products are warranted only to meet Micron’s production data sheet specifications. Information, products, and/or specifications
are subject to change without notice. All information is provided on an “AS IS” basis without warranties of any kind. Dates are estimates only. Drawings are not to scale. Micron and
the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners.
September 4, 2013
©2012 Micron Technology, Inc.
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1
The Need: Break Down the Memory Wall
4 Channel
3 Channel
2 Channel
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2
Reducing System Cost
LGA2011
4 Channel
3 Channel
Socket 423
2 Channel
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3
Managing System Complexity
DDR
85 page specification
1 page of AC timing params
3 speed bins
Standardization Time:
< 3 yrs years
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4
Managing System Complexity
DDR4
214 page specification
9 pages of AC timing params
12 speed bins for BOL (to 2400)
Standardized Time:
>6 years and going
DDR
85 page specification
1 page of AC timing params
3 speed bins
Standardization Time:
< 3 yrs years
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5
Hybrid Memory Cube (HMC)
Fast process logic and advanced DRAM design in
one optimized package
▶ Power Efficient
▶ Smaller Footprint
▶ Increased Bandwidth
▶ Reduced Latency
▶ Lower TCO
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6
Enabling Technologies
Abstracted Memory
Management
Through-Silicon Via (TSV)
Assembly
Memory Vaults Versus DRAM Arrays
• Significantly improved bandwidth, quality and
reliability versus traditional DRAM technologies
Innovative Design & Process Flow
• Incorporation of thousands of TSV sites per die
reduces signal lengths and reduces power
• Enables memory scalability through parallelism
Logic Base Controller
• Reduced memory complexity and significantly
increased performance
• Allows memory to scale with CPU performance
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Sophisticated Package Assembly
• Higher component density and significantly
improved signal integrity
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7
HMC Architecture
Start with a clean slate
DRAM
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8
HMC Architecture
Re-partition the DRAM
and strip away the
common logic
DRAM
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9
HMC Architecture
Stack multiple DRAMs
DRAM
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10
HMC Architecture
3DI & TSV Technology
Re-insert common logic
on to the Logic Base die
DRAM7
DRAM6
DRAM5
DRAM4
DRAM3
DRAM2
DRAM1
DRAM0
Logic Chip
Vault
DRAM
Logic Base
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11
HMC Architecture
Vault Control
Logic Base
Vault Control
Memory Control
Memory Control
Refresh
Controller
Crossbar Switch
Link Interface
Controller
Link Interface
Controller
Link Interface
Controller
Write
Buffer
Read
Buffer
Read Data
DRAM
Sequencer
Write Data
Vault Control
Request
Vault Control
TSV Repair
DRAM Repair
Crossbar Switch
Link Interface
Controller
Detail of memory interface
Processor
Links
3DI & TSV Technology
DRAM7
DRAM6
DRAM5
DRAM4
DRAM3
DRAM2
DRAM1
DRAM0
Logic Chip
Logic Base
• Multiple high-speed local buses for data movement
• Advanced memory controller functions
• DRAM control at memory rather than
distant host controller
• Reduced memory controller complexity
and increased efficiency
Vault Vaults are managed to maximize
overall device availability
• Optimized management of energy and
refresh
DRAM
Logic Base
September 4, 2013
• Self test, error detection, correction, and
repair in the logic base layer
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12
HMC Architecture
Link Controller Interface
HMC-SR Options:
10 Gpbs, 12.5 Gbps
or 15 Gbps
HMC
Host
TX
16 Lanes
RX
RX
16 Lanes
TX
September 4, 2013
Example:
8 or 16 Transmit Lanes
8 or 16 Receive Lanes
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13
Host Processor Memory Management
Manufacturing Test
• Burn-in
• At-speed Functional
Manage field maintenance
and self test
Manage all present and
future DRAM scaling and
process variation issues
Manage 100+ different
DRAM timing parameters
DRAM Layer
TSV
TSV
TSV
TSV
TSV
TSV
TSV
TSV
DRAM Layer
DRAM Layer
DRAM Layer
HOST
Re-drive Layer
Non-managed DRAM
(WIO, HBM, etc.)
Si Interposer
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14
Host Processor Memory Management
Simple memory requests
and responses. No
DRAM timing to manage
Functions moved to
HMC for management
Manufacturing Test
• Burn-in
• At-speed Functional
Manage field maintenance
and self test
Manage all present and
future DRAM scaling and
process variation issues
Manage 100+ different
DRAM timing parameters
DRAM Layer
TSV
TSV
TSV
TSV
TSV
TSV
TSV
TSV
DRAM Layer
DRAM Layer
DRAM Layer
HOST
Re-drive Layer
Non-managed DRAM
(WIO, HBM, etc.)
Si Interposer
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15
The Package
Up to 1.28 Tbps
Memory Bandwidth!
Standard BGA Packaging Solutions:
Cost Effective Packaging using existing Ecosystems
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HMC Near Memory
▶ All links between host CPU
and HMC logic layer
▶ Maximum bandwidth per GB capacity
HPC/Server – CPU/GPU
 Graphics
 Networking systems
 Test equipment

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HMC “Far” Memory
• Far memory
▶ Some HMC links connect to host,
some to other cubes
▶ Scalable to meet system
requirements
▶ Can be in module form or soldereddown
• Future interfaces may include
▶ Higher speed electrical (SERDES)
▶ Optical
▶ Whatever the most appropriate interface for the job!
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HMC Reliability
▶ Built-In RAS features at a high level...
Logic Stability
(DRAM controls in logic)
DRAM Array
Reliable handshake
(packet integrity verified
before memory access)
Logic / Interface
DRAM Array
DRAM Array
Logic / Interface
Logic / Interface
Vault Data
ECC protected
Host
Link Retry
CRC Protection
on Link Interface
Logic / Interface
DRAM Array
September 4, 2013
Address / Command
Parity for Array
transactions
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19
RAS Feature System Comparison
FEATURE
DRAM

Extensive Test Flow
RDIMM
HMC

Data ECC


Address/Command Parity
Mirroring



(back-up memory)

Sparing (Chipkill)
Lockstep

(redundancy w/better ECC)
CRC Coding

Self Repair

BIST
Error Status
and Debug Registers
DIMM Isolation



(flags faulty DIMM)

Memory Scrubbing
Supported
Redundant or not needed
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©2012 Micron Technology, Inc.
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Technology Comparison (Extreme Performance)
• What does it take to support 1.28TB/s of performance?
• Comparison of HMC to DDR3L-1600 and DDR4-3200
Active Signals
 DDR3 requires ~14,300
 DDR4 requires ~7,400
 HMC only needs ~2,160, HMC is ~85% less than DDR3
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Operating Power (including CPU’s)
 DDR3 system requires ~2.25KW
 DDR4 system requires ~1.23KW
 HMC system only needs ~350W, HMC is ~72% less than DDR4
Board Space
 DDR3 requires ~165,000 sq mm
 DDR4 requires ~82,500 sq mm
 HMC only needs ~8,712 sq mm, HMC is ~90% less than DDR4
Assumptions:
1DPC, (SR x4) RDIMMs, 6.2W/channel for DDR3 @ 12.8GB/s, 8.4W/channel for DDR4 @ 25.6GB/s 5W per Link for HMC @ 160GB/s, 143 pins/channel
for DDR3, 148 pins for DDR4 , 270 per HMC, RDIMM area equals 10mm pitch x 165mm long, HMC w/keep outs equal 1089 sq mm, CPU for RDIMMS
= 65W, CPU for HMC = 95W, each CPU supports up to 4 channels.
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21
Technology Comparison (Single Link)
• What does it take to support 60GB/s of performance?
• Comparison of HMC to DDR3L-1600 and DDR4-3200
DDR4
DDR4
DDR4
DDR3
Channels
 DDR3 requires 5 channels
 DDR4 requires 3 channels
 HMC only needs 1 Link
DDR3
Board Area
 DDR3 requires ~7,734 sq mm
 DDR4 requires ~3,843 sq mm
 HMC only needs ~1,089 sq mm
DDR3
Active Pins
 DDR3 requires 670 pins
 DDR4 requires 345 pins
 HMC only needs 72 pins
DDR4
HMC
BW/pin
 DDR3 ~90MB/pin
 DDR4 ~174MB/pin
 HMC ~833MB/pin
Assumptions: Same as previous example of 1.28TB/s Bandwidth
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Packet Buffer Memory Subsystem
Comparison
Packet Buffer Requirements & Assumptions

4 100GbE ports per Network Processor / Traffic Manager

Packet buffering on ingress or egress

Maintain 800Gbps effective bandwidth across all packet sizes at each packet buffer
Queue
Mgmt
Stats
Table
Lookups
100GbE
100GbE
Network Processor /
Traffic Manager
100GbE
Switch Fabric
▶
100GbE
Ingress or Egress
Packet Buffer
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400Gbps Packet Buffer Comparison
Network
Processor
Network
Processor
All devices drawn to scale
Parameter
DDR4-2400 x16
4 HMC-15G-SR Links
# of Memory
Devices
48
1
HMC System
Level Savings
Total #
of Pins
1848
276
85% fewer pins
Power:
Host PHY+ Memory
56W
33W
41% lower power
6048mm2
961mm2
84% smaller
memory footprint
1.75x
1x
Memory
Surface Area
Host PHY Silicon
Surface Area1
75% smaller
host PHY
1. Relative sizes represented
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Broad Adoption & Momentum
http://www.hybridmemorycube.org
1.0 Specification released April 2013
Over
120 Adopters!
Over 110
Adopters
to date!
Accel, Ltd
Fujitsu Limited
Luxtera Inc.
Pico Computing
ADATA Technology Co., LTD
Galaxy Computer System Co., Ltd.
Marvell
Renesas Electronics Corporation
AIRBUS
GDA Technologies
Mattozetta Technologies
Science & Technology Innovations
Altior
Maxeler Technologies Ltd.
SEAKR Engineering
APIC Corporation
GLOBALFOUNDRIES
GraphStream Incorporated
MediaTek
Arira Design
HGST, a Western Digital Company
Memoir Systems Inc.
ST Microelectronics
Suitcase TV Ltd
Arnold&Richter Cine Technik
HiSilicon Technologies Co., Ltd
Mentor Graphics
Tabula
Atria Logic, Inc.
HOY Technologies
Miranda
BroadPak
Huawei Technologies
Mobiveil, Inc.
Tech-Trek
Teradyne, Inc
Cadence Design Systems, Inc.
Infinera Corporation
Montage Technology, Inc.
The Regents of the University of California
Convey Computer Corporation
Information Sciences Institute USC
Inphi
Napatech A/S
Tilera Corporation
National Instruments
Tongji University
Cray Inc.
DAVE Srl
ISI/Nallatech
Design Magnitude Inc.
Israel Institute of Technology
NEC corpration
Netronome
TU Kaiserslautern
T-Platforms
Dream Chip Technologies GmbH
Juniper Networks
New Global Technology
UC, Irvine
Engineering Physics Center of MSU
Kool Chip
Northwest Logic
UMC
eSilicon Corporation
Korea Advanced Institute of Science
Obsidian Research
University of Heidelberg ZITI
Exablade Corporation
Lawrence Livermore National Laboratory
OmniPhy
University of Rochester
Ezchip Semiconductor
LeCroy Corporation
Oregon Synthesis
Winbond Electronics Corporation
FormFactor Inc.
LogicLink Design, Inc.
Perfcraft
Woodward McCoach, Inc.
ZTE Corporation
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A Robust Ecosystem
OEM’s
Enablers
September 4, 2013
Tools
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Industry Validation
“…like adding a turbocharger to
your computer”
- datacenteracceleration.com
“…wicked fast”
- gigaom.com
“…a complete paradigm shift”
- extremetech.com
“…unprecedented levels of
memory performance”
“…an entirely new
category of memory”
- Electronic News
- Tom’s Hardware
EE Times 40th Anniversary: “one of
the top ten technologies expected to
redefine the industry”
September 4, 2013
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©2012 Micron Technology, Inc.
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HMC 3DIC – The Bottom Line
▶ Improved costs – at a
system and TCO level
▶ When the need exists, the
ecosystem develops.
▶ There are no competing
technologies…
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HMC 3DIC – The Bottom Line
▶ Improved costs – at a
system and TCO level
▶ When the need exists, the
ecosystem develops.
▶ There are no competing
technologies… There are no
universal solutions
September 4, 2013
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©2012 Micron Technology, Inc.
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