STM8S105xx - RS Components International

STM8S105xx
Access line, 16 MHz STM8S 8-bit MCU, up to 32 Kbytes Flash,
integrated EEPROM,10-bit ADC, timers, UART, SPI, I²C
Features
■
■
■
Core
– 16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
– Extended instruction set
Memories
– Medium-density Flash/EEPROM:
– Program memory up to 32 Kbytes; data
retention 20 years at 55°C after 10 kcycles
– Data memory up to 1 Kbytes true data
EEPROM; endurance 300 kcycles
– RAM: Up to 2 Kbytes
Clock, reset and supply management
– 2.95 V to 5.5 V operating voltage
– Flexible clock control, 4 master clock
sources:
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
– Clock security system with clock monitor
– Power management:
– Low power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
– Permanently active, low consumption
power-on and power-down reset
■
Interrupt management
– Nested interrupt controller with 32
interrupts
– Up to 37 external interrupts on 6 vectors
■
Timers
– 2x 16-bit general purpose timers, with 2+3
CAPCOM channels (IC, OC or PWM)
– Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, deadtime insertion and flexible synchronization
– 8-bit basic timer with 8-bit prescaler
– Auto wake-up timer
June 2009
LQFP48 7x7
LQFP44 10x10
LQFP32 7x7
32
1
VFQFPN32 5x5
SDIP32 400 ml
– Two watchdog timers: Window watchdog
and independent watchdog
■
Communications interfaces
– UART with clock output for synchronous
operation, Smartcard, IrDA, LIN
– SPI interface up to 8 Mbit/s
– I2C interface up to 400 Kbit/s
■
Analog-to-digital converter (ADC)
– 10-bit, ±1 LSB ADC with up to 10
multiplexed channels, scan mode and
analog watchdog
■
I/Os
– Up to 38 I/Os on a 48-pin package
including 16 high sink outputs
– Highly robust I/O design, immune against
current injection
■
Development support
– Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
Table 1.
Reference
Device summary
Part number
STM8S105K4, STM8S105K6,
STM8S105xx STM8S105S4, STM8S105S6,
STM8S105C4, STM8S105C6
Doc ID 14771 Rev 8
1/99
www.st.com
1
Contents
STM8S105xx
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
4.1
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
4.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.8
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11
TIM2, TIM3 - 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . 18
4.12
TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.13
Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7
2/99
UART2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.14.2
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.14.3
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.1
6
4.14.1
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Doc ID 14771 Rev 8
STM8S105xx
Contents
8
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
10
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.4
Typical current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.5
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.6
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.1.7
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3.1
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.3.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
9.3.3
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 61
9.3.4
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 63
9.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.3.7
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.8
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
9.3.9
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.3.10
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
9.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1
10.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.1.1
LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
10.1.2
VFQFPN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
10.1.3
SDIP32 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
10.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 93
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
12
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Doc ID 14771 Rev 8
3/99
Contents
STM8S105xx
12.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 95
12.2
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.3
13
4/99
12.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
12.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Doc ID 14771 Rev 8
STM8S105xx
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
STM8S105xx access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 16
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Pin description for STM8S105 microcontrollers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Flash, Data EEPROM and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Description of alternate function remapping bits [7:0] of OPT2 . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 52
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 53
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 57
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Doc ID 14771 Rev 8
5/99
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
6/99
STM8S105xx
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
48-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
44-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 90
32-lead shrink plastic DIP (400 ml) package mechanical data . . . . . . . . . . . . . . . . . . . . . . 91
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Doc ID 14771 Rev 8
STM8S105xx
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
STM8S105xx access line block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
LQFP 48-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
LQFP 44-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
VFQFPN32/LQFP 32-pin pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SDIP32-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Supply current measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . 59
Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 60
Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . 60
Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical HSI accuracy at VDD = 5 V vs 5 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical HSI accuracy vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical LSI accuracy vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 73
Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
48-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
44-pin low profile quad flat package (10 x 10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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List of figures
Figure 49.
Figure 50.
Figure 51.
Figure 52.
8/99
STM8S105xx
32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 90
32-lead shrink plastic DIP (400 ml) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
STM8S105xx access line ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
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STM8S105xx
1
Introduction
Introduction
This datasheet contains the description of the STM8S105xx access line features, pinout,
electrical characteristics, mechanical data and ordering information.
●
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
●
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
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Description
2
STM8S105xx
Description
The STM8S105xx access line 8-bit microcontrollers offer from 16 to 32 Kbytes Flash
program memory, plus integrated true data EEPROM. They are referred to as mediumdensity devices in the STM8S microcontroller family reference manual (RM0016).
All devices of the STM8S105xx access line provide the following benefits:
●
Reduced system cost
●
Integrated true data EEPROM for up to 300 k write/erase cycles
–
High system integration level with internal clock oscillators, watchdog and brownout reset.
Performance and robustness
●
–
16 MHz CPU clock frequency
–
Robust I/O, independent watchdogs with separate clock source
–
Clock security system
Short development cycles
●
–
Applications scalability across a common family product architecture with
compatible pinout, memory map and and modular peripherals.
–
Full documentation and a wide choice of development tools
Product longevity
–
Advanced core and peripherals made in a state-of-the art technology
–
A family of products for applications with 2.95 V to 5.5 V operating supply
Device
No. of maximum GPIO
(I/O)
Ext. Interrupt pins
Timer CAPCOM channels
Timer complemetarty outputs
A/D Converter channels
High sink I/Os
Medium density
Flash Program memory
(bytes)
Data EEPROM (bytes)
RAM (bytes)
STM8S105xx access line features
Pin count
Table 2.
–
Peripheral set
STM8S105C6
STM8S105C4
STM8S105S6
STM8S105S4
STM8S105K6
STM8S105K4
48
48
44
44
32
32
38
38
34
34
25
25
35
35
31
31
23
23
9
9
8
8
8
8
3
3
3
3
3
3
10
10
9
9
7
7
16
16
15
15
12
12
32K
16K
32K
16K
32K
16K
1024
1024
1024
1024
1024
1024
2K
2K
2K
2K
2K
2K
Advanced control timer (TIM1),
General-purpose timers
(TIM2 and TIM3),
Basic timer (TIM4)
SPI, I2C, UART,
Window WDG,
Independent WDG,
ADC
10/99
Doc ID 14771 Rev 8
STM8S105xx
Block diagram
Figure 1.
STM8S105xx access line block diagram
Reset block
XTAL 1-16 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
BOR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interf.
Debug/SWIM
Master/slave
autosynchro
LIN master
SPI emul.
UART2
400 Kbit/s
I2C
8 Mbit/s
SPI
Up to 32 Kbytes
program
Flash
1 Kbytes
data EEPROM
Address and data bus
3
Block diagram
Up to 2 Kbytes
RAM
Boot ROM
16-bit advanced control
timer (TIM1)
16-bit general purpose
timers (TIM2, TIM3)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
5 CAPCOM
channels
Up to 10 channels
ADC1
1/2/4 kHz
beep
8-bit basic timer
(TIM4)
Beeper
AWU timer
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Product overview
4
STM8S105xx
Product overview
The following section intends to give an overview of the basic features of the STM8S105xx
access line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus - single cycle fetching for most instructions
●
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter - 16-Mbyte linear memory space
●
16-bit stack pointer - access to a 64 K-level stack
●
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
12/99
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
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STM8S105xx
4.2
Product overview
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
4.3
●
R/W to RAM and peripheral registers in real-time
●
R/W access to all resources by stalling the CPU
●
Breakpoints on all program-memory instructions (software breakpoints)
●
Two advanced breakpoints, 23 predefined configurations
Interrupt controller
●
Nested interrupts with three software priority levels
●
32 interrupt vectors with hardware priority
●
Up to 37 external interrupts on six vectors including TLI
●
Trap and reset interrupts
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Product overview
4.4
STM8S105xx
Flash program and data EEPROM memory
●
Up to 32 Kbytes of Flash program single voltage Flash memory
●
Up to 1 K bytes true data EEPROM
●
Read while write: Writing in data memory possible while executing code in program
memory.
●
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (memory access
security system). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform in-application programming (IAP), this write protection can be removed by writing
a MASS key sequence in a control register. This allows the application to write to data
EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
The size of the UBC is programmable through the UBC option byte (Table 13), in increments
of 1 page (512 bytes) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
●
Main program memory: Up to 32 Kbytes minus UBC
●
User-specific boot code (UBC): Configurable up to 32 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
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STM8S105xx
Product overview
Figure 2.
Flash memory organisation
Data memory area (1 Kbytes)
Data
EEPROM
memory
Option bytes
UBC area
Remains write protected during IAP
Programmable area from 1 Kbyte
(2 first pages) up to 32 Kbytes
(1 page steps)
Medium density
Flash program memory
(up to 32 Kbytes)
Program memory area
Write access possible for IAP
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
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Product overview
STM8S105xx
Features
●
Clock prescaler: To get the best compromise between speed and current
consumption the clock frequency to the CPU and peripherals can be adjusted by a
programmable prescaler.
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
Master clock sources: Four different clock sources can be used to drive the master
clock:
–
1-16 MHz high-speed external crystal (HSE)
–
Up to 16 MHz high-speed user-external clock (HSE user-ext)
–
16 MHz high-speed internal RC oscillator (HSI)
–
128 kHz low-speed internal RC (LSI)
●
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
●
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 3.
Bit
Peripheral
clock
Bit
Peripheral
clock
Bit
Peripheral
clock
Bit
Peripheral
clock
PCKEN17
TIM1
PCKEN13
UART2
PCKEN27
Reserved
PCKEN23
ADC
PCKEN16
TIM2
PCKEN12
Reserved
PCKEN26
Reserved
PCKEN22
AWU
PCKEN15
TIM3
PCKEN11
SPI
PCKEN25
Reserved
PCKEN21
Reserved
PCKEN10
2C
PCKEN24
Reserved
PCKEN20
Reserved
PCKEN14
16/99
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
TIM4
I
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STM8S105xx
4.6
Product overview
Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
4.7
●
Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
●
Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
●
Active halt mode with regulator off: This mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
●
Halt mode: In this mode the microcontroller uses the least power. The CPU and
peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is
triggered by external event or reset.
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
1.
Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2.
Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
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Product overview
STM8S105xx
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
●
Used for auto wakeup from active halt mode
●
Clock source: Internal 128 kHz internal low frequency RC oscillator or external clock
●
LSI clock can be internally connected to TIM3 input capture channel 1 for calibration
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
4.11
18/99
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
●
Synchronization module to control the timer with external signals
●
Break input to force the timer outputs into a defined state
●
Three complementary outputs with adjustable dead time
●
Encoder mode
●
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2, TIM3 - 16-bit general purpose timers
●
16-bit autoreload (AR) up-counter
●
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
●
Timers with 3 or 2 individually configurable capture/compare channels
●
PWM mode
●
Interrupt sources: 2 or 3 x input capture/output compare, 1 x overflow/update
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STM8S105xx
4.12
Table 4.
Product overview
TIM4 - 8-bit basic timer
●
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
●
Clock source: CPU clock
●
Interrupt source: 1 x overflow/update
TIM timer features
Timer
Counter
size
(bits)
Prescaler
TIM1
16
Any integer from 1 to 65536
Up/down
4
3
Yes
TIM2
16
Any power of 2 from 1 to 32768
Up
3
0
No
TIM3
16
Any power of 2 from 1 to 32768
Up
2
0
No
TIM4
8
Any power of 2 from 1 to 128
Up
0
0
No
Counting CAPCOM Complem.
Ext.
mode
trigger
channels outputs
Timer
synchronization/
chaining
No
4.13
Analog-to-digital converter (ADC1)
STM8S105xx products contain a 10-bit successive approximation A/D converter (ADC1)
with up to 10 multiplexed input channels and the following main features:
4.14
●
Input voltage range: 0 to VDDA
●
Conversion time: 14 clock cycles
●
Single and continuous and buffered continuous conversion modes
●
Buffer size (n x 10 bits) where x = number of input channels
●
Scan mode for single and continuous conversion of a sequence of channels
●
Analog watchdog capability with programmable upper and lower thresholds
●
Analog watchdog interrupt
●
External trigger input
●
Trigger from TIM1 TRGO
●
End of conversion (EOC) interrupt
Communication interfaces
The following communication interfaces are implemented:
●
UART2: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, LIN2.1 master/slave capability
●
SPI : Full and half-duplex, 8 Mbit/s
●
I²C: Up to 400 Kbit/s
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Product overview
4.14.1
STM8S105xx
UART2
Main features
●
One Mbit/s full duplex SCI
●
SPI emulation
●
High precision baud rate generator
●
Smartcard emulation
●
IrDA SIR encoder decoder
●
LIN master mode
●
LIN slave mode
Asynchronous communication (UART mode)
●
Full duplex communication - NRZ standard format (mark/space)
●
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
●
Separate enable bits for transmitter and receiver
●
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line (interrupt)
●
Transmission error detection with interrupt generation
●
Parity control
Synchronous communication
●
Full duplex synchronous transfers
●
SPI master operation
●
8-bit data communication
●
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
●
Emission: Generates 13-bit synch break frame
●
Reception: Detects 11-bit break frame
LIN slave mode
20/99
●
Autonomous header handling - one single interrupt per valid message header
●
Automatic baud rate synchronization - maximum tolerated initial clock deviation ±15 %
●
Synch delimiter checking
●
11-bit LIN synch break detection - break detection always active
●
Parity check on the LIN identifier field
●
LIN error management
●
Hot plugging support
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STM8S105xx
4.14.2
4.14.3
Product overview
SPI
●
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on two lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
CRC calculation
●
1 byte Tx and Rx buffer
●
Slave/master selection input pin
I2C
●
●
I2C master features:
–
Clock generation
–
Start and stop generation
2
I C slave features:
–
Programmable I2C address detection
–
Stop bit detection
●
Generation and detection of 7-bit/10-bit addressing and general call
●
Supports different communication speeds:
–
Standard speed (up to 100 kHz)
–
Fast speed (up to 400 kHz)
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Pinouts and pin description
5
STM8S105xx
Pinouts and pin description
LQFP 48-pin pinout
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
PE3/TIM1_BKIN
Figure 3.
48 47 46 45 44 43 42 41 40 39 38 37
36
1
2
35
3
34
33
4
32
5
31
6
30
7
29
8
28
9
27
10
26
11
25
12
13 14 15 16 17 18 19 20 21 2223 24
PG1
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR/AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
AIN8/PE7
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
[TIM3_CH1] TIM2_CH3/PA3
(HS) PA4
(HS) PA5
(HS) PA6
1.
22/99
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID 14771 Rev 8
STM8S105xx
Pinouts and pin description
LQFP 44-pin pinout
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1[BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1 [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
PE0 (HS)/CLK_CCO
PE1 (T)/I2C_SCL
PE2 (T)/I2C_SDA
Figure 4.
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
PG1
PG0
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
VDDIO_2
VSSIO_2
PC5 (HS)/SPI_SCK
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
VDDA
VSSA
AIN7/PB7
AIN6/PB6
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
(TIM1_CH1N] AIN0/PB0
AIN9/PE6
NRST
OSCIN/PA1
OSCOUT/PA2
VSSIO_1
VSS
VCAP
VDD
VDDIO_1
(HS) PA4
(HS) PA5
(HS) PA6
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID 14771 Rev 8
23/99
Pinouts and pin description
VFQFPN32/LQFP 32-pin pinout
PD7/TLI [TIM1_CH4]
PD6/UART2_RX
PD5/UART2_TX
PD4 (HS)/TIM2_CH1 [BEEP]
PD3 (HS)/TIM2_CH2 [ADC_ETR]
PD2 (HS)/TIM3_CH1[TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/TIM3_CH2 [TIM1_BKIN] [CLK_CCO]
Figure 5.
STM8S105xx
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
VDDA
VSSA
[I2C_SDA] AIN5/PB5
[I2C_SCL] AIN4/PB4
[TIM1_ETR] AIN3/PB3
[TIM1_CH3N] AIN2/PB2
[TIM1_CH2N] AIN1/PB1
[TIM1_CH1N] AIN0/PB0
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
24/99
1.
(HS) high sink capability.
2.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID 14771 Rev 8
STM8S105xx
Pinouts and pin description
Figure 6.
SDIP32-pin pinout
ADC_ETR/TIM2_CH2/PD3(HS)
[BEEP]TIM2_CH1/PD4(HS)
UART2_TX/PD5
UART2_RX/PD6
(TIM1_CH4)TLI/PD7
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
VDDIO
AIN12/PF4
VDDA
VSSA
[I2C_SDA]AIN5/PB5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PD2(HS)/TIM3_CH1[TIM2_CH3]
PD1(HS)/SWIM
PD0(HS)/TIM3_CH2[TIM1_BKIN][CLK_CCO]
PC7(HS)/SPI_MISO
PC6(HS)/SPI_MOSI
PC5(HS)/SPI_SCK
PC4(HS)/TIM1_CH4
PC3(HS)/TIM1_CH3
PC2(HS)/TIM1_CH2
PC1(HS)/TIM1_CH1/UART2_CK
PE5/SPI_NSS
PB0/AIN0[TIM1_CH1N]
PB1/AIN1[TIM1_CH2N]
PB2/AIN2[TIM1_CH3N]
PB3/AIN3[TIM1_ETR]
PB4/AIN4[I2C_SCL]
105_ai15057
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Table 5.
Legend/abbreviations
Type
I= Input, O = Output, S = Power supply
Level
Input
CM = CMOS
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
configuration
Output
Reset state
float = floating, wpu = weak pull-up
T = True open drain, OD = Open drain, PP = Push pull
Bold X
Doc ID 14771 Rev 8
25/99
Pinouts and pin description
Pin description for STM8S105 microcontrollers
2
2
7 PA1/OSCIN
I/O X
X
3
3
3
8 PA2/OSCOUT
I/O X
X
4
4
-
-
5
5
4
6
6
7
Main function
(after reset)
2
PP
X
OD
I/O
Speed
6 NRST
Output
High sink
1
wpu
SDIP32
1
floating
VFQFPN32/LQFP32
1
Pin name
Type
LQFP44
Input
LQFP48
Pin number
Ext. interrupt
Table 6.
STM8S105xx
Default
alternate
function
Reset
X
O1
X
X
Port A1
Resonator/
crystal in
O1
X
X
Port A2
Resonator/
crystal out
S
I/O ground
9 VSS
S
Digital ground
5
10 VCAP
S
1.8 V regulator capacitor
7
6
11 VDD
S
Digital power supply
8
8
7
12 VDDIO_1
S
I/O power supply
9
-
-
-
PA3/TIM2_CH3
[TIM3_CH1]
I/O X
X
X
O1
X
X
Port A3
10
9
-
-
PA4
I/O X
X
X
HS O3
X
X
Port A4
11 10
-
-
PA5
I/O X
X
X
HS O3
X
X
Port A5
12 11
-
-
PA6
I/O X
X
X
HS O3
X
X
Port A6
I/O X
X
O1
X
X
Port F4
-
-
VSSIO_1
Timer 2 channel3
TIM3_CH1
[AFR1]
Analog input
12(1)
8
13 PF4/AIN12
9
14 VDDA
S
Analog power supply
14 13 10 15 VSSA
S
Analog ground
13 12
Alternate
function after
remap
[option bit]
15 14
-
-
PB7/AIN7
I/O X
X
X
O1
X
X
Port B7 Analog input 7
16 15
-
-
PB6/AIN6
I/O X
X
X
O1
X
X
Port B6 Analog input 6
17 16 11 16
PB5/AIN5
[I2C_SDA]
I/O X
X
X
O1
X
X
Port B5 Analog input 5
I2C_SDA
[AFR6]
18 17 12 17
PB4/AIN4
[I2C_SCL]
I/O X
X
X
O1
X
X
Port B4 Analog input 4
I2C_SCL
[AFR6]
19 18 13 18
PB3/AIN3
[TIM1_ETR]
I/O X
X
X
O1
X
X
Port B3 Analog input 3
TIM1_ETR
[AFR5]
20 19 14 19
PB2/AIN2
[TIM1_CH3N]
I/O X
X
X
O1
X
X
Port B2 Analog input
TIM1_
CH3N
[AFR5]
21 20 15 20
PB1/AIN1
[TIM1_CH2N]
I/O X
X
X
O1
X
X
Port B1 Analog input 1
TIM1_
CH2N
[AFR5]
26/99
Doc ID 14771 Rev 8
STM8S105xx
Pin description for STM8S105 microcontrollers (continued)
Output
Speed
OD
PP
O1
X
X
Port B0 Analog input 0
23
-
24 22
High sink
X
floating
X
Pin name
Type
I/O X
SDIP32
PB0/AIN0
[TIM1_CH1N]
LQFP44
22 21 16 21
LQFP48
Ext. interrupt
Input
wpu
VFQFPN32/LQFP32
Pin number
Main function
(after reset)
Table 6.
Pinouts and pin description
Default
alternate
function
-
-
PE7/AIN8
I/O X
X
X
O1
X
X
Port E7 Analog input 8
-
-
PE6/AIN9
I/O X
X
X
O1
X
X
Port E6 Analog input 9(2)
I/O X
X
X
O1
X
X
Port E5
25 23 17 22 PE5/SPI_NSS
PC1/TIM1_CH1/
UART2_CK
I/O X
X
X
HS O3
X
X
27 25 19 24 PC2/TIM1_CH2
I/O X
X
X
HS O3
X
X
Port C2
Timer 1- channel
2
28 26 20 25 PC3/TIM1_CH3
I/O X
X
X
HS O3
X
X
Port C3
Timer 1 channel 3
29
I/O X
X
X
HS O3
X
X
Port C4
Timer 1 channel 4
I/O X
X
X
HS O3
X
X
Port C5 SPI clock
-
21 26 PC4/TIM1_CH4
30 27 22 27 PC5/SPI_SCK
31 28
-
-
VSSIO_2
S
I/O ground
32 29
-
-
VDDIO_2
S
I/O power supply
33 30 23 28 PC6/SPI_MOSI
I/O X
X
X
HS O3
X
X
Port C6
SPI master out/
slave in
34 31 24 29 PC7/SPI_MISO
I/O X
X
X
HS O3
X
X
Port C7
SPI master in/
slave out
35 32
-
-
PG0
I/O X
X
O1
X
X
Port G0
36 33
-
-
PG1
I/O X
X
O1
X
X
Port G1
37
-
-
PE3/TIM1_BKIN
I/O X
X
X
O1
X
X
Port E3
38 34
-
-
PE2/I2C_SDA
I/O X
X
O1 T(3)
Port E2 I2C data
39 35
-
-
PE1/I2C_SCL
I/O X
X
O1 T(3)
Port E1 I2C clock
40 36
-
-
PE0/CLK_CCO
I/O X
-
X
X
HS O3
X
Doc ID 14771 Rev 8
X
Port E0
TIM1_CH1N
[AFR5]
SPI master/slave
select
Timer 1 channel 1/
Port C1 UART2
synchronous
clock
26 24 18 23
Alternate
function after
remap
[option bit]
Timer 1 - break
input
Configurable
clock output
27/99
Pinouts and pin description
Pin description for STM8S105 microcontrollers (continued)
Main function
(after reset)
PP
OD
Speed
High sink
Output
Ext. interrupt
Pin name
floating
Input
Type
SDIP32
VFQFPN32/LQFP32
LQFP44
LQFP48
Pin number
wpu
Table 6.
STM8S105xx
Default
alternate
function
PD0/TIM3_CH2
41 37 25 30 [TIM1_BKIN]
[CLK_CCO]
I/O X
X
X
HS O3
X
X
Timer 3 Port D0
channel 2
42 38 26 31 PD1/SWIM
I/O X
X
X
HS O4
X
X
Port D1
SWIM data
interface
Alternate
function after
remap
[option bit]
TIM1_BKIN
[AFR3]/
CLK_CCO
[AFR2]
43 39 27 32
PD2/TIM3_CH1
[TIM2_CH3]
I/O X
X
X
HS O3
X
X
Port D2
Timer 3 channel 1
TIM2_CH3
[AFR1]
44 40 28
1
PD3/TIM2_CH2
[ADC_ETR]
I/O X
X
X
HS O3
X
X
Port D3
Timer 2 channel 2
ADC_ETR
[AFR0]
45 41 29
2
PD4/TIM2_CH1
[BEEP]
I/O X
X
X
HS O3
X
X
Port D4
Timer 2 channel 1
BEEP output
[AFR7]
46 42 30
3 PD5/UART2_TX
I/O X
X
X
O1
X
X
Port D5
UART2 data
transmit
47 43 31
4 PD6/UART2_RX I/O X
X
X
O1
X
X
Port D6
UART2 data
receive
48 44 32
5
X
X
O1
X
X
Port D7
Top level
interrupt
PD7/TLI
[TIM1_CH4]
I/O X
TIM1_CH4
[AFR4]
1. AIN12 is not selectable in ADC scan mode or with analog watchdog.
2. In 44-pin package, AIN9 cannot be used by ADC scan mode.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented).
28/99
Doc ID 14771 Rev 8
STM8S105xx
5.1
Pinouts and pin description
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of eight AFR (alternate function
remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active,
the default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the
GPIO section of the family reference manual, RM0016).
Doc ID 14771 Rev 8
29/99
Memory and register map
STM8S105xx
6
Memory and register map
6.1
Memory map
Figure 7.
Memory map
0x00 0000
0x00 07FF
RAM
(2 Kbytes)
512 bytes stack
Reserved
0x00 4000
0x00 43FF
0x00 4400
0x00 47FF
0x00 4800
1 Kbyte data EEPROM
Reserved
Option bytes
0x00 487F
0x00 4900
Reserved
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
GPIO and periph. reg.
(see Table 8 & Table 9)
Reserved
0x00 5FFF
0x00 6000
2 Kbytes boot ROM
0x00 67FF
0x00 6800
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
CPU/SWIM/debug/ITC
registers (see Table 10 )
32 interrupt vectors
Flash program memory
(16 to 32 Kbytes)
0x00 FFFF
0x01 0000
Reserved
0x02 7FFF
30/99
Doc ID 14771 Rev 8
STM8S105xx
Memory and register map
Table 7 lists the boundary addresses for each memory size. The top of the stack is at the
RAM end address in each case.
Table 7.
Flash, Data EEPROM and RAM boundary addresses
Memory area
Size (bytes)
Start address
End address
32K
0x00 8000
0x00 FFFF
16K
0x00 8000
0x00 BFFF
RAM
2K
0x00 0000
0x00 07FF
Data EEPROM
1024
0x00 4000
0x00 43FF
Flash program memory
6.2
Register map
Table 8.
I/O port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0x00
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0x00
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
0x00 500A
PC_ODR
Port C data output latch register
0x00
0x00 500B
PB_IDR
Port C input pin value register
0x00
PC_DDR
Port C data direction register
0x00
0x00 500D
PC_CR1
Port C control register 1
0x00
0x00 500E
PC_CR2
Port C control register 2
0x00
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0x00
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x02
0x00 5013
PD_CR2
Port D control register 2
0x00
Address
0x00 5002
0x00 5007
0x00 500C
0x00 5011
Block
Port A
Port B
Port C
Port D
Doc ID 14771 Rev 8
31/99
Memory and register map
Table 8.
I/O port hardware register map (continued)
Register label
Register name
Reset
status
0x00 5014
PE_ODR
Port E data output latch register
0x00
0x00 5015
PE_IDR
Port E input pin value register
0x00
PE_DDR
Port E data direction register
0x00
0x00 5017
PE_CR1
Port E control register 1
0x00
0x00 5018
PE_CR2
Port E control register 2
0x00
0x00 5019
PF_ODR
Port F data output latch register
0x00
0x00 501A
PF_IDR
Port F input pin value register
0x00
PF_DDR
Port F data direction register
0x00
0x00 501C
PF_CR1
Port F control register 1
0x00
0x00 501D
PF_CR2
Port F control register 2
0x00
0x00 501E
PG_ODR
Port G data output latch register
0x00
0x00 501F
PG_IDR
Port G input pin value register
0x00
PG_DDR
Port G data direction register
0x00
0x00 5021
PG_CR1
Port G control register 1
0x00
0x00 5022
PG_CR2
Port G control register 2
0x00
0x00 5023
PH_ODR
Port H data output latch register
0x00
0x00 5024
PH_IDR
Port H input pin value register
0x00
PH_DDR
Port H data direction register
0x00
0x00 5026
PH_CR1
Port H control register 1
0x00
0x00 5027
PH_CR2
Port H control register 2
0x00
0x00 5028
PI_ODR
Port I data output latch register
0x00
0x00 5029
PI_IDR
Port I input pin value register
0x00
PI_DDR
Port I data direction register
0x00
0x00 502B
PI_CR1
Port I control register 1
0x00
0x00 502C
PI_CR2
Port I control register 2
0x00
Address
0x00 5016
0x00 501B
0x00 5020
0x00 5025
0x00 502A
32/99
STM8S105xx
Block
Port E
Port F
Port G
Port H
Port I
Doc ID 14771 Rev 8
STM8S105xx
Memory and register map
Table 9.
Address
General hardware register map
Block
Register label
0x00 5050
to
0x00 5059
Register name
Reset
status
Reserved area (10 bytes)
0x00 505A
FLASH_CR1
Flash control register 1
0x00
0x00 505B
FLASH_CR2
Flash control register 2
0x00
0x00 505C
FLASH_NCR2
Flash complementary control
register 2
0xFF
0x00 505D
FLASH _FPR
Flash protection register
0x00
0x00 505E
FLASH _NFPR
Flash complementary protection register
0xFF
0x00 505F
FLASH _IAPSR
Flash in-application programming status
register
0x00
Flash
0x00 5060
to
0x00 5061
0x00 5062
Reserved area (2 bytes)
Flash
FLASH _PUKR
0x00 5063
0x00 5064
Flash program memory unprotection
register
0x00
Reserved area (1 byte)
Flash
FLASH _DUKR
0x00 5065
to
0x00 509F
Data EEPROM unprotection register
0x00
Reserved area (59 bytes)
0x00 50A0
EXTI_CR1
External interrupt control register 1
0x00
EXTI_CR2
External interrupt control register 2
0x00
ITC - EXTI
0x00 50A1
0x00 50A2
to
0x00 50B2
0x00 50B3
Reserved area (17 bytes)
RST
RST_SR
0x00 50B4
to
0x00 50BF
Reset status register
xx
Reserved area (12 bytes)
0x00 50C0
CLK_ICKR
Internal clock control register
0x01
CLK_ECKR
External clock control register
0x00
CLK
0x00 50C1
0x00 50C2
Reserved area (1 byte)
Doc ID 14771 Rev 8
33/99
Memory and register map
Table 9.
STM8S105xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 50C3
CLK_CMSR
Clock master status register
0xE1
0x00 50C4
CLK_SWR
Clock master switch register
0xE1
0x00 50C5
CLK_SWCR
Clock switch control register
0bxxxx
0000
0x00 50C6
CLK_CKDIVR
Clock divider register
0x18
CLK_PCKENR1
Peripheral clock gating register 1
0xFF
CLK_CSSR
Clock security system register
0x00
0x00 50C9
CLK_CCOR
Configurable clock control register
0x00
0x00 50CA
CLK_PCKENR2
Peripheral clock gating register 2
0xFF
0x00 50CB
CLK_CANCCR
CAN clock control register
0x00
0x00 50CC
CLK_HSITRIMR
HSI clock calibration trimming register
xx
0x00 50CD
CLK_SWIMCCR
SWIM clock control register
x0
Address
Block
0x00 50C7
0x00 50C8
CLK
0x00 50CE
to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
WWDG_CR
WWDG control register
0x7F
WWDG_WR
WWDR window register
0x7F
WWDG
0x00 50D2
0x00 50D3
to
0x00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
IWDG
0x00 50E2
IWDG_KR
IWDG key register
-
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
AWU
0x00 50F2
0x00 50F3
0x00 50F4
to
0x00 50FF
34/99
BEEP
AWU_CSR1
AWU control/status register 1
0x00
AWU_APR
AWU asynchronous prescaler buffer
register
0x3F
AWU_TBR
AWU timebase selection register
0x00
BEEP_CSR
BEEP control/status register
0x1F
Reserved area (12 bytes)
Doc ID 14771 Rev 8
STM8S105xx
Memory and register map
Table 9.
General hardware register map (continued)
Register label
Register name
Reset
status
00 5200h
SPI_CR1
SPI control register 1
0x00
00 5201h
SPI_CR2
SPI control register 2
0x00
00 5202h
SPI_ICR
SPI interrupt control register
0x00
SPI_SR
SPI status register
0x02
00 5204h
SPI_DR
SPI data register
0x00
00 5205h
SPI_CRCPR
SPI CRC polynomial register
0x07
00 5206h
SPI_RXCRCR
SPI Rx CRC register
0xFF
00 5207h
SPI_TXCRCR
SPI Tx CRC register
0xFF
Address
Block
00 5203h
SPI
00 5208h
to
00 520Fh
Reserved area (8 bytes)
I2C control register 1
I2C_CR1
00 5210h
00 5211h
2C
I2C_CR2
control register 2
0x00
frequency register
0x00
I
00 5212h
I2C_FREQR
00 5213h
I2C_OARL
I2C Own address register low
0x00
I2C_OARH
2C
0x00
00 5214h
I
2C
0x00
I
own address register high
00 5215h
Reserved
00 5216h
00 5217h
00 5218h
00 5219h
I2C
I2C_DR
I2C data register
0x00
I2C_SR1
I2C status register 1
0x00
I2C_SR2
2C
I
status register 2
0x00
I2C_SR3
I2C
status register 3
0x00
interrupt control register
0x00
00 521Ah
I2C_ITR
00 521Bh
I2C_CCRL
I2C clock control register low
0x00
I2C_CCRH
I2C
0x00
00 521Ch
00 521Dh
00 521Eh
I
2C
2
I C TRISE register
I2C_TRISER
I2C_PECR
clock control register high
2C
I
packet error checking register
00 521Fh
to
00 522Fh
Reserved area (17 bytes)
0x00 5230
to
0x00 523F
Reserved area (6 bytes)
Doc ID 14771 Rev 8
0x02
0x00
35/99
Memory and register map
Table 9.
STM8S105xx
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5240
UART2_SR
UART2 status register
C0h
0x00 5241
UART2_DR
UART2 data register
xx
0x00 5242
UART2_BRR1
UART2 baud rate register 1
0x00
0x00 5243
UART2_BRR2
UART2 baud rate register 2
0x00
0x00 5244
UART2_CR1
UART2 control register 1
0x00
UART2_CR2
UART2 control register 2
0x00
0x00 5246
UART2_CR3
UART2 control register 3
0x00
005247
UART2_CR4
UART2 control register 4
0x00
0x00 5248
Reserved
0x00 5249
UART2_CR6
UART2 control register 6
0x00
0x00 524A
UART2_GTR
UART2 guard time register
0x00
0x00 524B
UART2_PSCR
UART2 prescaler register
0x00
Address
Block
0x00 5245
UART2
0x00 524C
to
0x00 524F
Reserved area (4 bytes)
0x00 5250
TIM1_CR1
TIM1 control register 1
0x00
0x00 5251
TIM1_CR2
TIM1 control register 2
0x00
0x00 5252
TIM1_SMCR
TIM1 slave mode control register
0x00
0x00 5253
TIM1_ETR
TIM1 external trigger register
0x00
0x00 5254
TIM1_IER
TIM1 interrupt enable register
0x00
0x00 5255
TIM1_SR1
TIM1 status register 1
0x00
0x00 5256
TIM1_SR2
TIM1 status register 2
0x00
0x00 5257
TIM1_EGR
TIM1 event generation register
0x00
0x00 5258
TIM1_CCMR1
TIM1 capture/compare mode register 1
0x00
TIM1_CCMR2
TIM1 capture/compare mode register 2
0x00
0x00 525A
TIM1_CCMR3
TIM1 capture/compare mode register 3
0x00
0x00 525B
TIM1_CCMR4
TIM1 capture/compare mode register 4
0x00
0x00 525C
TIM1_CCER1
TIM1 capture/compare enable register 1
0x00
0x00 525D
TIM1_CCER2
TIM1 capture/compare enable register 2
0x00
0x00 525E
TIM1_CNTRH
TIM1 counter high
0x00
0x00 525F
TIM1_CNTRL
TIM1 counter low
0x00
0x00 5260
TIM1_PSCRH
TIM1 prescaler register high
0x00
0x00 5261
TIM1_PSCRL
TIM1 prescaler register low
0x00
0x00 5262
TIM1_ARRH
TIM1 auto-reload register high
0xFF
0x00 5263
TIM1_ARRL
TIM1 auto-reload register low
0xFF
0x00 5259
TIM1
36/99
Doc ID 14771 Rev 8
STM8S105xx
Memory and register map
Table 9.
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5264
TIM1_RCR
TIM1 repetition counter register
0x00
0x00 5265
TIM1_CCR1H
TIM1 capture/compare register 1 high
0x00
0x00 5266
TIM1_CCR1L
TIM1 capture/compare register 1 low
0x00
0x00 5267
TIM1_CCR2H
TIM1 capture/compare register 2 high
0x00
0x00 5268
TIM1_CCR2L
TIM1 capture/compare register 2 low
0x00
TIM1_CCR3H
TIM1 capture/compare register 3 high
0x00
TIM1_CCR3L
TIM1 capture/compare register 3 low
0x00
0x00 526B
TIM1_CCR4H
TIM1 capture/compare register 4 high
0x00
0x00 526C
TIM1_CCR4L
TIM1 capture/compare register 4 low
0x00
0x00 526D
TIM1_BKR
TIM1 break register
0x00
0x00 526E
TIM1_DTR
TIM1 dead-time register
0x00
0x00 526F
TIM1_OISR
TIM1 output idle state register
0x00
Address
0x00 5269
0x00 526A
Block
TIM1
cont’d
0x00 5270
to
0x00 52FF
Reserved area (147 bytes)
0x00 5300
TIM2_CR1
TIM2 control register 1
0x00
0x00 5301
TIM2_IER
TIM2 interrupt enable register
0x00
0x00 5302
TIM2_SR1
TIM2 status register 1
0x00
0x00 5303
TIM2_SR2
TIM2 status register 2
0x00
0x00 5304
TIM2_EGR
TIM2 event generation register
0x00
0x00 5305
TIM2_CCMR1
TIM2 capture/compare mode register 1
0x00
0x00 5306
TIM2_CCMR2
TIM2 capture/compare mode register 2
0x00
0x00 5307
TIM2_CCMR3
TIM2 capture/compare mode register 3
0x00
0x00 5308
TIM2_CCER1
TIM2 capture/compare enable register 1
0x00
TIM2_CCER2
TIM2 capture/compare enable register 2
0x00
0x00 530A
TIM2_CNTRH
TIM2 counter high
0x00
0x00 530B
TIM2_CNTRL
TIM2 counter low
0x00
0x00 530C
TIM2_PSCR
TIM2 prescaler register
0x00
0x00 530D
TIM2_ARRH
TIM2 auto-reload register high
0xFF
0x00 530E
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 530F
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5310
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5311
TIM2_CCR2H
TIM2 capture/compare reg. 2 high
0x00
0x00 5312
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5313
TIM2_CCR3H
TIM2 capture/compare register 3 high
0x00
0x00 5309
TIM2
Doc ID 14771 Rev 8
37/99
Memory and register map
Table 9.
STM8S105xx
General hardware register map (continued)
Address
Block
Register label
Register name
Reset
status
0x00 5314
TIM2
cont’d
TIM2_CCR3L
TIM2 capture/compare register 3 low
0x00
0x00 5315
to
0x00 531F
Reserved area (11 bytes)
0x00 5320
TIM3_CR1
TIM3 control register 1
0x00
0x00 5321
TIM3_IER
TIM3 interrupt enable register
0x00
0x00 5322
TIM3_SR1
TIM3 status register 1
0x00
0x00 5323
TIM3_SR2
TIM3 status register 2
0x00
0x00 5324
TIM3_EGR
TIM3 event generation register
0x00
0x00 5325
TIM3_CCMR1
TIM3 capture/compare mode register 1
0x00
0x00 5326
TIM3_CCMR2
TIM3 capture/compare mode register 2
0x00
0x00 5327
TIM3_CCER1
TIM3 capture/compare enable register 1
0x00
TIM3_CNTRH
TIM3 counter high
0x00
0x00 5329
TIM3_CNTRL
TIM3 counter low
0x00
0x00 532A
TIM3_PSCR
TIM3 prescaler register
0x00
0x00 532B
TIM3_ARRH
TIM3 auto-reload register high
0xFF
0x00 532C
TIM3_ARRL
TIM3 auto-reload register low
0xFF
0x00 532D
TIM3_CCR1H
TIM3 capture/compare register 1 high
0x00
0x00 532E
TIM3_CCR1L
TIM3 capture/compare register 1 low
0x00
0x00 532F
TIM3_CCR2H
TIM3 capture/compare register 2 high
0x00
0x00 5330
TIM3_CCR2L
TIM3 capture/compare register 2 low
0x00
0x00 5328
TIM3
0x00 5331
to
0x00 533F
0x00 5340
TIM4_CR1
TIM4 control register 1
0x00
0x00 5341
TIM4_IER
TIM4 interrupt enable register
0x00
0x00 5342
TIM4_SR
TIM4 status register
0x00
TIM4_EGR
TIM4 event generation register
0x00
0x00 5344
TIM4_CNTR
TIM4 counter
0x00
0x00 5345
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 5346
TIM4_ARR
TIM4 auto-reload register
0xFF
0x00 5343
0x00 5347
to
0x00 53DF
38/99
Reserved area (15 bytes)
TIM4
Reserved area (153 bytes)
Doc ID 14771 Rev 8
STM8S105xx
Memory and register map
Table 9.
General hardware register map (continued)
Address
Block
Register label
Register name
Reset
status
0x00 53E0
to
0x00 53F3
ADC1
ADC _DBxR
ADC data buffer registers
0x00
0x00 53F4
to
0x00 53FF
Reserved area (12 bytes)
0x00 5400
ADC _CSR
ADC control/status register
0x00
0x00 5401
ADC_CR1
ADC configuration register 1
0x00
0x00 5402
ADC_CR2
ADC configuration register 2
0x00
0x00 5403
ADC_CR3
ADC configuration register 3
0x00
0x00 5404
ADC_DRH
ADC data register high
0x00
0x00 5405
ADC_DRL
ADC data register low
0x00
0x00 5406
ADC_TDRH
ADC Schmitt trigger disable register high
0x00
0x00 5407
ADC_TDRL
ADC Schmitt trigger disable register low
0x00
ADC_HTRH
ADC high threshold register high
0x03
0x00 5409
ADC_HTRL
ADC high threshold register low
0xFF
0x00 540A
ADC_LTRH
ADC low threshold register high
0x00
0x00 540B
ADC_LTRL
ADC low threshold register low
0x00
0x00 540C
ADC_AWSRH
ADC analog watchdog status register
high
0x00
0x00 540D
ADC_AWSRL
ADC analog watchdog status register low
0x00
0x00 540E
ADC _AWCRH
ADC analog watchdog control register
high
0x00
0x00 540F
ADC_AWCRL
ADC analog watchdog control register
low
0x00
0x00 5408
0x00 5410
to 0x00
57FF
ADC1
Reserved area (1008 bytes)
Doc ID 14771 Rev 8
39/99
Memory and register map
Table 10.
STM8S105xx
CPU/SWIM/debug module/interrupt controller registers
Register label
Register name
Reset
status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x00
0x00 7F03
PCL
Program counter low
0x00
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x07
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CCR
Condition code register
0x28
Address
Block
0x00 7F04
0x00 7F05
CPU(1)
0x00 7F0B to
0x00 7F5F
0x00 7F60
Reserved area (85 bytes)
CPU
CFG_GCR
Global configuration register
0x00
0x00 7F70
ITC_SPR1
Interrupt software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt software priority register 3
0xFF
ITC_SPR4
Interrupt software priority register 4
0xFF
0x00 7F74
ITC_SPR5
Interrupt software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt software priority register 8
0xFF
0x00 7F73
ITC - SPR
0x00 7F78 to
0x00 7F79
0x00 7F80
0x00 7F81 to
0x00 7F8F
40/99
Reserved area (2 bytes)
SWIM
SWIM_CSR
SWIM control status register
Reserved area (15 bytes)
Doc ID 14771 Rev 8
0x00
STM8S105xx
Table 10.
Memory and register map
CPU/SWIM/debug module/interrupt controller registers (continued)
Register label
Register name
Reset
status
0x00 7F90
DM_BK1RE
DM breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
DM breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
DM breakpoint 1 register low byte
0xFF
0x00 7F93
DM_BK2RE
DM breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
DM breakpoint 2 register high byte
0xFF
DM_BK2RL
DM breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
DM debug module control register 1
0x00
0x00 7F97
DM_CR2
DM debug module control register 2
0x00
0x00 7F98
DM_CSR1
DM debug module control/status register 1
0x10
0x00 7F99
DM_CSR2
DM debug module control/status register 2
0x00
0x00 7F9A
DM_ENFCTR
DM enable function register
0xFF
Address
0x00 7F95
Block
DM
0x00 7F9B to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
Doc ID 14771 Rev 8
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Interrupt vector mapping
STM8S105xx
7
Interrupt vector mapping
Table 11.
Interrupt mapping
IRQ
no.
Source
block
RESET
TRAP
Wakeup from
halt mode
Wakeup from
active-halt mode
Vector address
Yes
Yes
0x00 8000
Software interrupt
-
-
0x00 8004
External top level interrupt
-
-
0x00 8008
Yes
0x00 800C
-
0x00 8010
Yes(1)
0x00 8014
Description
Reset
0
TLI
1
AWU
Auto wake up from halt
-
2
CLK
Clock controller
Yes
(1)
3
EXTI0
Port A external interrupts
4
EXTI1
Port B external interrupts
Yes
Yes
0x00 8018
5
EXTI2
Port C external interrupts
Yes
Yes
0x00 801C
6
EXTI3
Port D external interrupts
Yes
Yes
0x00 8020
7
EXTI4
Port E external interrupts
Yes
Yes
0x00 8024
8
Reserved
-
-
0x00 8028
9
Reserved
-
-
0x00 802C
Yes
Yes
0x00 8030
10
SPI
End of transfer
11
TIM1
TIM1 update/overflow/underflow/
trigger/break
-
-
0x00 8034
12
TIM1
TIM1 capture/compare
-
-
0x00 8038
13
TIM2
TIM2 update /overflow
-
-
0x00 803C
14
TIM2
TIM2 capture/compare
-
-
0x00 8040
15
TIM3
Update/overflow
-
-
0x00 8044
16
TIM3
Capture/compare
-
-
0x00 8048
17
Reserved
-
-
0x00 804C
18
Reserved
-
-
0x00 8050
19
I2C
I2C interrupt
Yes
Yes
0x00 8054
20
UART2
Tx complete
-
-
0x00 8058
21
UART2
Receive register DATA FULL
-
-
0x00 805C
22
ADC1
ADC1 end of conversion/analog
watchdog interrupt
-
-
0x00 8060
23
TIM4
TIM4 update/overflow
-
-
0x00 8064
24
Flash
EOP/WR_PG_DIS
-
-
0x00 8068
0x00 806C to
0x00 807C
Reserved
1. Except PA1
42/99
Doc ID 14771 Rev 8
STM8S105xx
8
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 12: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 12.
Addr.
Option bytes
Option
name
Option
byte
no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
Read-out
4800h
protection
OPT0
ROP[7:0]
00h
(ROP)
4801h
User boot
OPT1
UBC[7:0]
00h
4802h
code(UBC)
NOPT1
NUBC[7:0]
FFh
4803h
Alternate
OPT2
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
00h
NOPT2
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
function
4804h
remapping
(AFR)
OPT3
Reserved
HSITRIM
4806h
NOPT3
Reserved
NHSITRIM
4807h
OPT4
Reserved
NOPT4
Reserved
4805h
Miscellaneous
option
LSI
IWDG
WWDG
WWDG
_EN
_HW
_HW
_HALT
NLSI
NIWDG_H
NWWDG
NWWG
_EN
W
_HW
_HALT
EXT
CKAWU
PRS
PRS
CLK
SEL
C1
C0
NEXT
NCKAWUS
NPR
NPR
CLK
EL
SC1
SC0
00h
FFh
00h
Clock option
4808h
4809h
HSE clock
480Ah
startup
480Bh
FFh
OPT5
HSECNT[7:0]
00h
NOPT5
NHSECNT[7:0]
FFh
OPT6
Reserved
00h
NOPT6
Reserved
FFh
OPT7
Reserved
00h
NOPT7
Reserved
FFh
OPTBL
BL[7:0]
00h
NOPTBL
NBL[7:0]
FFh
Reserved
480Ch
480Dh
Reserved
480Eh
487Eh
Bootloader
487Fh
Doc ID 14771 Rev 8
43/99
Option bytes
STM8S105xx
Table 13.
Option byte description
Option byte no.
Description
OPT0
ROP[7:0] Memory readout protection (ROP)
AAh: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Pages 0 to 1 defined as UBC, memory write-protected
0x02: Pages 0 to 3 defined as UBC, memory write-protected
0x03: Pages 0 to 4 defined as UBC, memory write-protected
...
0x3E: Pages 0 to 63 defined as UBC, memory write-protected
Other values: Reserved
Note: Refer to the family reference manual (RM0016) section on Flash
write protection for more details.
OPT2
AFR[7:0]
Refer to Table 14 for the alternate function remapping decriptions of bits
[7:0].
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
OPT3
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
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STM8S105xx
Option bytes
Table 13.
Option byte description (continued)
Option byte no.
Description
OPT5
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
OPT6
Reserved.
OPT7
Reserved.
OPTBL
Table 14.
BL[7:0] Bootloader option byte
This option is checked by the boot ROM code after reset. Depending on
content of addresses 0x487E, 0x487F and 0x8000 (reset vector) the
CPU jumps to the bootloader or to the reset vector. Refer to the STM8S
bootloader manual for more details.
Description of alternate function remapping bits [7:0] of OPT2
Description(1)
Option byte no.
OPT2
AFR7Alternate function remapping option 7
0: AFR7 remapping option inactive: Default alternate function(2).
1: Port D4 alternate function = BEEP.
AFR6 Alternate function remapping option 6
0: AFR6 remapping option inactive: Default alternate functions(2).
1: Port B5 alternate function = I2C_SDA; port B4 alternate
function = I2C_SCL.
AFR5 Alternate function remapping option 5
0: AFR5 remapping option inactive: Default alternate functions(2).
1: Port B3 alternate function = TIM1_ETR; port B2 alternate
function = TIM1_NCC3; port B1 alternate function = TIM1_CH2N;
port B0 alternate function = TIM1_CH1N.
AFR4 Alternate function remapping option 4
0: AFR4 remapping option inactive: Default alternate function(2).
1: Port D7 alternate function = TIM1_CH4.
AFR3 Alternate function remapping option 3
0: AFR3 remapping option inactive: Default alternate function(2).
1: Port D0 alternate function = TIM1_BKIN.
AFR2 Alternate function remapping option 2
0: AFR2 remapping option inactive: Default alternate function(2).
1: Port D0 alternate function = CLK_CCO.
Note: AFR2 option has priority over AFR3 if both are activated.
AFR1 Alternate function remapping option 1
0: AFR1 remapping option inactive: Default alternate functions(2).
1: Port A3 alternate function = TIM3_CH1; port D2 alternate function
TIM2_CH3.
AFR0 Alternate function remapping option 0
0: AFR0 remapping option inactive: Default alternate function(2).
1: Port D3 alternate function = ADC_ETR.
1. Do not use more than one remapping option in the same port.
2. Refer to pinout description.
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Electrical characteristics
STM8S105xx
9
Electrical characteristics
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
9.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
9.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
9.1.4
Typical current consumption
For typical current consumption measurements, VDD, VDDIO and VDDA are connected
together in the configuration shown in Figure 8.
Figure 8.
Supply current measurement conditions
5 V or 3.3 V
A
VDD
VDDA
VDDIO
VSS
VSSA
VSSIO
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STM8S105xx
Electrical characteristics
9.1.5
Pin loading conditions
9.1.6
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
Figure 9.
Pin loading conditions
STM8 PIN
50pF
9.1.7
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 10. Pin input voltage
STM8 PIN
VIN
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Electrical characteristics
9.2
STM8S105xx
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 15.
Symbol
VDDx - VSS
Voltage characteristics
Ratings
Supply voltage (including VDDA and VDDIO)(1)
Input voltage on true open drain pins (PE1, PE2)
VIN
Input voltage on any other pin(2)
(2)
Min
Max
-0.3
6.5
VSS - 0.3
6.5
VSS - 0.3
VDD + 0.3
|VDDx - VDD| Variations between different power pins
50
|VSSx - VSS| Variations between all the different ground pins
50
VESD
Electrostatic discharge voltage
Unit
V
mV
see Absolute maximum
ratings (electrical
sensitivity) on page 84
1. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
48/99
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STM8S105xx
Electrical characteristics
Table 16.
Current characteristics
Symbol
Max.(1)
Ratings
IVDD
Total current into VDD power lines (source)(2)
60
IVSS
(2)
Total current out of VSS ground lines (sink)
60
Output current sunk by any I/O and control pin
20
Output current source by any I/Os and control pin
20
Total output current sourced (sum of all I/O and control pins)
for devices with two VDDIO pins(3)
200
Total output current sourced (sum of all I/O and control pins)
for devices with one VDDIO pin(3)
100
Total output current sunk (sum of all I/O and control pins) for
devices with two VSSIO pins(3)
160
Total output current sunk (sum of all I/O and control pins) for
devices with one VSSIO pin(3)
80
Injected current on NRST pin
±4
IIO
ΣIIO
IINJ(PIN)
(4)(5)
ΣIINJ(PIN)(4)
mA
Injected current on OSCIN pin
Injected current on any other
Unit
±4
pin(6)
±4
Total injected current (sum of all I/O and control pins)(6)
±20
1. Data based on characterization results, not tested in production.
2. All power (VDD, VDDIO, VDDA) and ground (VSS, VSSIO, VSSA) pins must always be connected to the
external supply.
3. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package
between the VDDIO/VSSIO pins.
4. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
5. Negative injection disturbs the analog performance of the device. See note in Section Figure 44.: Typical
application with I2C bus and timing diagram 1) on page 79.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 17.
Thermal characteristics
Symbol
Ratings
Value
TSTG
Storage temperature range
-65 to 150
TJ
Maximum junction temperature
150
Unit
°C
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Electrical characteristics
9.3
STM8S105xx
Operating conditions
Table 18.
General operating conditions
Symbol
Parameter
Conditions
fCPU
Internal CPU clock frequency
VDD/VDD_IO Standard operating voltage
CEXT
PD(2)
VCAP external capacitor
(1)
Power dissipation at
TA = 85 °C for suffix 6
or TA= 125° C for suffix 3
Max
Unit
0
16
MHz
2.95
5.5
V
470
3300
nF
44 and 48-pin devices, with
output on eight standard
ports, two high sink ports
and two open drain ports
simultaneously(3)
443
32-pin package, with output
on eight standard ports and
two high sink ports
simultaneously(3)
360
Ambient temperature for 6
suffix version
Maximum power dissipation
Ambient temperature for 3
suffix version
TA
TJ
0.05 ≤ ESR ≤ 0.2Ω at 1 MHz
Min
mW
-40
85
Low power dissipation
-40
105
Maximum power dissipation
-40
125
Low power dissipation (4)
-40
140
6 suffix version
-40
105
3 suffix version
-40
130(5)
(4)
°C
Junction temperature range
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors.
2. To calculate PDmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Section 10.2: Thermal
characteristics) with the value for TJmax given in Table 18 and the value for ΘJA given in Table 56: Thermal
characteristics.
3. Refer to Section 10.2: Thermal characteristics on page 92 for the calculation method.
4. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see
Section 10.2: Thermal characteristics on page 92).
5.
50/99
TJmax is given by the test limit. Above this value the product behavior is not guaranteed.
Doc ID 14771 Rev 8
STM8S105xx
Electrical characteristics
Figure 11. fCPUmax versus VDD
fCPU [MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 °C
12
8
4
0
2.95
4.0
5.0
5.5
SUPPLY VOLTAGE [V]
Table 19.
Symbol
tVDD
Operating conditions at power-up/power-down
Parameter
Conditions
Min
Typ
Max
VDD rise time rate
2(1)
∞
VDD fall time rate
2(1)
∞
tTEMP
Reset release
delay
VIT+
Power-on reset
threshold
2.65
2.8
2.95
VIT-
Brown-out reset
threshold
2.58
2.7
2.88
VHYS(BOR)
Brown-out reset
hysteresis
1.7(1)
VDD rising
Unit
µs/V
ms
V
70
mV
1. Guaranteed by design, not tested in production.
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 18. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 12. External capacitor CEXT
ESR
C
ESL
Rleak
1. ESR is the equivalent series resistance and ESL is the equivalent inductance.
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Electrical characteristics
9.3.2
STM8S105xx
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 46.
Total current consumption in run mode
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except
if explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 20.
Symbol
Total current consumption with code execution in run mode at VDD = 5 V
Parameter
Conditions
IDD(RUN)
3.2
HSE user ext. clock (16 MHz)
2.6
3.2
HSI RC osc. (16 MHz)
2.5
3.2
HSE user ext. clock (16 MHz)
1.6
2.2
HSI RC osc. (16 MHz)
1.3
2.0
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MH3z/8)
0.75
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.55
HSE crystal osc. (16 MHz)
7.7
HSE user ext. clock (16 MHz)
7.0
8
HSI RC osc.(16 MHz)
7.0
8.0
fCPU = fMASTER =
2 MHz
HSI RC osc. (16 MHz/8)(2)
1.5
fCPU = fMASTER/128 =
125 kHz
HSI RC osc. (16 MHz)
1.35
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)
0.75
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.6
fCPU = fMASTER/128 =
125 kHz
fCPU = fMASTER =
16 MHz
Supply current in
run mode, code
executed from
Flash
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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Max(1)
HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
Supply current in
run mode, code
executed from
RAM
Typ
Doc ID 14771 Rev 8
Unit
mA
2.0
STM8S105xx
Table 21.
Symbol
Electrical characteristics
Total current consumption with code execution in run mode at VDD = 3.3 V
Parameter
Supply
current in
run mode,
code
executed
from RAM
IDD(RUN)
Supply
current in
run mode,
code
executed
from Flash
Conditions
fCPU = fMASTER = 16 MHz
fCPU = fMASTER/128 = 125 kHz
Typ
Max(1)
HSE crystal osc. (16 MHz)
2.8
HSE user ext. clock (16 MHz)
2.6
3.2
HSI RC osc. (16 MHz)
2.5
3.2
HSE user ext. clock (16 MHz)
1.6
2.2
HSI RC osc. (16 MHz)
1.3
2.0
fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)
0.75
fCPU = fMASTER = 128 kHz
LSI RC osc. (128 kHz)
0.55
HSE crystal osc. (16 MHz)
7.3
HSE user ext. clock (16 MHz)
7.0
8
HSI RC osc.(16 MHz)
7.0
8.0
fCPU = fMASTER = 16 MHz
Unit
mA
MHz/8)(2)
fCPU = fMASTER = 2 MHz.
HSI RC osc. (16
fCPU = fMASTER/128 = 125 kHz
HSI RC osc. (16 MHz)
1.5
1.35
fCPU = fMASTER/128 = 15.625 kHz HSI RC osc. (16 MHz/8)
0.75
fCPU = fMASTER = 128 kHz
0.6
LSI RC osc. (128 kHz)
2.0
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
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Electrical characteristics
STM8S105xx
Total current consumption in wait mode
Table 22.
Symbol
Total current consumption in wait mode at VDD = 5 V
Parameter
Conditions
Max(1)
HSE crystal osc. (16 MHz)
2.15
HSE user ext. clock (16 MHz)
1.55
2.0
HSI RC osc. (16 MHz)
1.5
1.9
HSI RC osc. (16 MHz)
1.3
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
0.7
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.5
fCPU = fMASTER =
16 MHz
IDD(WFI)
Typ
Supply current in fCPU = fMASTER/128 =
125 kHz
wait mode
Unit
mA
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Table 23.
Symbol
Total current consumption in wait mode at VDD = 3.3 V
Parameter
Conditions
1.75
HSE user ext. clock (16 MHz)
1.55
2.0
HSI RC osc. (16 MHz)
1.5
1.9
HSI RC osc. (16 MHz)
1.3
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
0.7
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.5
Supply current in fCPU = fMASTER/128 =
125 kHz
wait mode
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
54/99
Max(1)
HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
IDD(WFI)
Typ
Doc ID 14771 Rev 8
Unit
mA
STM8S105xx
Electrical characteristics
Total current consumption in active halt mode
Table 24.
Total current consumption in active halt mode at VDD = 5 V
Conditions
Symbol
Parameter
Main
voltage
regulator
(MVR)(2)
Flash mode
(3)
Typ
Clock source
Max at Max at
Unit
85 °C(1) 125 °C(1)
HSE crystal osc.
(16 MHz)
1080
LSI RC osc.
(128 kHz)
200
HSE crystal osc.
(16 MHz)
1030
LSI RC osc.
(128 kHz)
140
270
350
68
120
220
12
60
150
Operating mode
320
400
On
Supply current in
active halt mode
IDD(AH)
µA
Power-down mode
Operating mode
Off
LSI RC osc.
Power-down mode (128 kHz)
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Table 25.
Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Symbol
Parameter
Main
voltage
regulator
(MVR)(2)
Flash mode(3)
Typ
Clock source
Max at Max at
Unit
85 °C(1) 125 °C(1)
HSE crystal osc.
(16 MHz)
680
LSI RC osc.
(128 kHz)
200
HSE crystal osc.
(16 MHz)
630
LSI RC osc.
(128 kHz)
140
270
350
66
120
220
10
60
150
Operating mode
320
400
On
IDD(AH)
Supply current in
active halt mode
µA
Power-down mode
Operating mode
Off
LSI RC osc.
Power-down mode (128 kHz)
1. Data based on characterization results, not tested in production.
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
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Electrical characteristics
STM8S105xx
Total current consumption in halt mode
Table 26.
Symbol
IDD(H)
Total current consumption in halt mode at VDD = 5 V
Parameter
Supply current in
halt mode
Conditions
Flash in operating mode, HSI clock
after wakeup
Typ
Max at
85 °C(1)
Max at
125 °C(1)
62
90
150
Unit
µA
Flash in powerdown mode, HSI clock
after wakeup
6.5
20
80
Typ
Max at
85 °C(1)
Max at
125 °C(1)
Flash in operating mode, HSI clock
after wakeup
60
90
150
Flash in powerdown mode, HSI clock
after wakeup
4.5
20
80
1. Data based on characterization results, not tested in production.
Table 27.
Symbol
IDD(H)
Total current consumption in halt mode at VDD = 3.3 V
Parameter
Supply current in
halt mode
Conditions
µA
1. Data based on characterization results, not tested in production.
56/99
Unit
Doc ID 14771 Rev 8
STM8S105xx
Electrical characteristics
Low power mode wakeup times
Table 28.
Wakeup times
Symbol
Parameter
Conditions
tWU(WFI)
Wakeup time from wait
mode to run mode(3)
MVR voltage
regulator on(4)
Wakeup time active halt
mode to run mode.(3)
MVR voltage
regulator off(4)
tWU(H)
Wakeup time from halt
mode to run mode(3)
Unit
See
note(2)
fCPU = fMASTER = 16 MHz
tWU(AH)
Max(1)
Typ
0.56
Flash in operating
mode(5)
Flash in powerdown mode(5)
Flash in operating
mode(5)
1(6)
3(6)
HSI
(after wakeup)
Flash in powerdown mode(5)
µs
48(6)
50(6)
Flash in operating mode(5)
Flash in power-down mode
2(6)
52
(5)
54
1. Data guaranteed by design, not tested in production.
2. tWU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
Total current consumption and timing in forced reset state
Table 29.
Symbol
Total current consumption and timing in forced reset state
Parameter
Conditions
IDD(R)
Supply current in reset state(2)
tRESETBL
Reset release to bootloader vector fetch
Typ
VDD = 5 V
500
VDD = 3.3 V
400
Max(1)
Unit
µA
150
µs
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS.
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Electrical characteristics
STM8S105xx
Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz.
Table 30.
Peripheral current consumption
Symbol
Parameter
IDD(TIM1)
TIM1 supply current (1)
IDD(TIM2)
(1)
TIM2 supply current
Typ.
230
115
IDD(TIM3)
TIM3 timer supply current
(1)
90
IDD(TIM4)
TIM4 timer supply current (1)
30
(2)
µA
IDD(UART2)
UART2 supply current
IDD(SPI)
SPI supply current (2)
45
IDD(I2C)
I2C
65
IDD(ADC1)
supply current
Unit
(2)
ADC1 supply current when converting (3)
110
955
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
58/99
Doc ID 14771 Rev 8
STM8S105xx
Electrical characteristics
Current consumption curves
Figure 15 to Figure 18 show typical current consumption measured with code executing in
RAM.
Figure 13. Typ. IDD(RUN) vs. VDD, HSE user external clock, fCPU = 16 MHz
-40°C
3
25°C
2.95
85°C
125°C
2.9
IDD(RUN)HSE [mA]
2.85
2.8
2.75
2.7
2.65
2.6
2.55
2.5
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
ai15380
Figure 14. Typ. IDD(RUN) vs. fCPU, HSE user external clock, VDD = 5 V
-40°C
5
25°C
4.5
85°C
4
125°C
IDD(RUN)HSE [mA]
3.5
3
2.5
2
1.5
1
0.5
0
0
5
10
fcpu [MHz]
15
20
ai15381
Figure 15. Typ. IDD(RUN) vs. VDD, HSI RC osc, fCPU = 16 MHz
-40°C
3
25°C
2.9
85°C
2.8
125°C
IDD(RUN)HSI [mA]
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
ai15382
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Electrical characteristics
STM8S105xx
Figure 16. Typ. IDD(WFI) vs. VDD, HSE user external clock, fCPU = 16 MHz
-40°C
IDD(WFI)HSE [mA]
25°C
2.4
85°C
2.2
125°C
2
1.8
1.6
1.4
1.2
1
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
ai15383
Figure 17. Typ. IDD(WFI) vs. fCPU, HSE user external clock VDD = 5 V
-40°C
25°C
3
85°C
IDD(WFI)HSE [mA]
2.5
125°C
2
1.5
1
0.5
0
0
5
10
15
20
fcpu [MHz]
ai15384
Figure 18. Typ. IDD(WFI) vs. VDD, HSI RC osc, fCPU = 16 MHz
-40˚C
2
25˚C
1.9
85˚C
1.8
125˚C
IDD(WFI)HSI [mA]
1.7
1.6
TBD
1.5
1.4
1.3
1.2
1.1
1
2.5
3
3.5
4
4.5
VDD [V]
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5
5.5
6
STM8S105xx
9.3.3
Electrical characteristics
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 31.
HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
fHSE_ext
User external clock source
frequency
0
16
VHSEH(1)
OSCIN input pin high level
voltage
0.7 x VDD
VDD + 0.3 V
V
VHSEL
OSCIN input pin low level
voltage
(1)
ILEAK_HSE
OSCIN input leakage current
VSS < VIN < VDD
VSS
0.3 x VDD
-1
+1
µA
1. Data based on characterization results, not tested in production.
Figure 19. HSE external clock source
VHSEH
VHSEL
fHSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Electrical characteristics
Table 32.
HSE oscillator characteristics
Symbol
Parameter
Conditions
External high speed oscillator
frequency
fHSE
RF
Feedback resistor
C(1)
Recommended load
capacitance (2)
IDD(HSE)
gm
tSU(HSE)
STM8S105xx
Typ
1
Max
Unit
16
MHz
220
kΩ
20
HSE oscillator power
consumption
Startup time
pF
C = 20 pF,
fOSC = 16 MHz
6 (startup)
1.6 (stabilized)(3)
C = 10 pF,
fOSC =16 MHz
6 (startup)
1.2 (stabilized)(3)
Oscillator transconductance
(4)
Min
mA
5
mA/V
VDD is stabilized
1
ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4.
tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 20. HSE oscillator circuit diagram
fHSE to core
Rm
Lm
RF
CO
CL1
OSCIN
Cm
gm
Resonator
Consumption
control
Resonator
STM8
OSCOUT
CL2
HSE oscillator critical gm formula
g mcrit = ( 2 × Π × f HSE ) 2 × R m ( 2Co + C )
2
Rm: Notional resistance (see crystal specification), Lm: Notional inductance (see crystal
specification),
Cm: Notional capacitance (see crystal specification), Co: Shunt capacitance (see crystal
specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
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STM8S105xx
9.3.4
Electrical characteristics
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 33.
Symbol
fHSI
HSI oscillator characteristics
Parameter
Conditions
Min
Frequency
Typ
Max
16
Accuracy of HSI
oscillator
ACCHSI
Accuracy of HSI
oscillator (factory
calibrated)
tsu(HSI)
HSI oscillator wakeup
time including
calibration
IDD(HSI)
HSI oscillator power
consumption
User-trimmed with
CLK_HSITRIMR register
for given VDD and TA
conditions(1)
MHz
1(2)
VDD = 5 V, TA = 25°C(3)
-2.5(4)
1.3(4)
VDD = 5 V,
25 °C ≤ TA ≤ 85 °C
-2.5(4)
2(4)
-4.5(3)(4)
3(3)(4)
2.95 ≤ VDD ≤ 5.5 V,
-40 °C ≤ TA ≤ 125 °C
Unit
170
%
1(2)
µs
250(3)
µA
1. Refer to application note.
2. Guaranteed by design, not tested in production.
3. Data based on characterization results, not tested in production.
4. Subject to further characterization to give better results.
Figure 21. Typical HSI accuracy at VDD = 5 V vs 5 temperatures
3.00%
2.00%
1.00%
0.00%
max
-1.00%
min
-2.00%
-3.00%
-4.00%
-5.00%
-40
0
25
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85
125
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Electrical characteristics
STM8S105xx
Figure 22. Typical HSI accuracy vs VDD @ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
1.00%
0.50%
% accuracy
0.00%
-0.50%
-1.00%
-1.50%
-2.00%
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 34.
LSI oscillator characteristics
Symbol
fLSI
Parameter
Frequency
tsu(LSI)
LSI oscillator wakeup time
IDD(LSI)
LSI oscillator power consumption
Min
Typ
Max
Unit
110
128
146
kHz
7(1)
µs
5
µA
1. Guaranteeed by design, not tested in production.
Figure 23. Typical LSI accuracy vs VDD @ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
5.00%
4.00%
3.00%
% accuracy
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
2
2.5
3
3.5
4
VDD (V)
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4.5
5
5.5
6
STM8S105xx
9.3.5
Electrical characteristics
Memory characteristics
RAM and hardware registers
Table 35.
RAM and hardware registers
Symbol
Parameter
Conditions
Min
Unit
VRM
Data retention mode(1)
Halt mode (or reset)
VIT-max(2)
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Table 19 on page 51 for the value of VIT-max.
Flash program memory/data EEPROM memory
General conditions: TA = -40 to 125 °C.
Table 36.
Symbol
VDD
tprog
terase
Flash program memory/data EEPROM memory
Parameter
Operating voltage
(all modes, execution/write/erase)
Conditions
fCPU ≤16 MHz
tRET
IDD
2.95
Max
Unit
5.5
V
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/128 bytes)
6
6.6
ms
Fast programming time for 1 block
(128 bytes)
3
3.3
ms
Erase time for 1 block (128 bytes)
3
3.3
ms
cycles(2)
NRW
Min(1) Typ
Erase/write
(program memory)
TA = +85 °C
10 k
Erase/write cycles (data memory)(2)
TA = +125 ° C
300 k
Data retention (program memory)
after 10k erase/write cycles
at TA = +85 °C
TRET = 55° C
20
Data retention (data memory) after
10k erase/write cycles
at TA = +85 °C
TRET = 55° C
20
Data retention (data memory) after
300 k erase/write cycles
at TA = +125 °C
TRET = 85° C
1
Supply current (Flash programming or
erasing for 1 to 128 bytes)
cycles
1M
years
2
mA
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
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Electrical characteristics
9.3.6
STM8S105xx
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 37.
Symbol
I/O static characteristics
Parameter
VIL
Input low level
voltage
VIH
Input high level
voltage
Vhys
Hysteresis(1)
Rpu
Pull-up resistor
tR, tF
Rise and fall time
(10 % - 90 %)
Conditions
VDD = 5 V
Min
Typ
Max
Unit
-0.3
0.3 x VDD
V
0.7 x VDD
VDD + 0.3 V
V
700
60
kΩ
Fast I/Os
Load = 50 pF
20 (2)
ns
Standard and high sink I/Os
Load = 50 pF
125 (2)
ns
Input leakage
current, analog and
digital
VSS ≤ VIN ≤ VDD
±1 (2)
µA
Ilkg ana
Analog input
leakage current
VSS ≤ VIN ≤ VDD
±250 (2)
nA
Ilkg(inj)
Leakage current in
adjacent I/O(2)
Injection current ±4 mA
±1(2)
µA
Ilkg
VDD = 5 V, VIN = VSS
30
45
mV
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested
in production.
2. Data based on characterization results, not tested in production.
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Electrical characteristics
Figure 24. Typical VIL and VIH vs VDD @ 4 temperatures
-40˚C
6
25˚C
5
85˚C
125˚C
VIL/VIH [V]
4
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 25. Typical pull-up resistance vs VDD @ 4 temperatures
-40˚C
25˚C
60
Pull-up resistance [kΩ]
85˚C
55
125˚C
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 26. Typical pull-up current vs VDD @ 4 temperatures
140
Pull-up current [µA]
120
100
80
-40˚C
60
25˚C
40
85˚C
125˚C
20
0
0
1
2
3
4
5
6
VDD [V]
1. The pull-up is a pure resistor (slope goes through 0).
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Electrical characteristics
Table 38.
Symbol
VOL
VOH
STM8S105xx
Output driving current (standard ports)
Parameter
Conditions
Min
Max
Output low level with eight pins sunk
IIO= 10 mA, VDD = 5 V
2
Output low level with four pins sunk
IIO = 4 mA, VDD = 3.3 V
1(1)
Output high level with eight pins
sourced
IIO = 10 mA, VDD = 5 V
Unit
V
2.4
V
Output high level with four pins
sourced
IIO = 4 mA, VDD = 3.3 V
2
(1)
1. Data based on characterization results, not tested in production
Table 39.
Symbol
Output driving current (true open drain ports)
Parameter
Conditions
Max
IIO = 10 mA, VDD = 5 V
VOL
Output low level with two pins sunk
Unit
1
1.5(1)
IIO = 10 mA, VDD = 3.3 V
V
2(1)
IIO = 20 mA, VDD = 5 V
1. Data based on characterization results, not tested in production
Table 40.
Symbol
VOL
Output driving current (high sink ports)
Parameter
Conditions
IIO = 10 mA, VDD = 5 V
Output low level with four pins sunk
IIO = 10 mA, VDD = 3.3 V
1.1(1)
Output low level with four pins sunk
IIO = 20 mA, VDD = 5 V
1.6(1)
V
3.8
IIO = 10 mA, VDD = 3.3 V
1.9(1)
Output high level with four pins sourced
IIO = 20 mA, VDD = 5 V
2.9(1)
Doc ID 14771 Rev 8
Unit
0.9
Output high level with four pins sourced
1. Data based on characterization results, not tested in production
68/99
Max
Output low level with eight pins sunk
Output high level with eight pins sourced IIO = 10 mA, VDD = 5 V
VOH
Min
STM8S105xx
Electrical characteristics
Typical output level curves
Figure 28 to Figure 35 show typical output level curves measured with output on a single
pin.
Figure 27. Typ. VOL @ VDD = 5 V (standard ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
IOL [mA]
Figure 28. Typ. VOL @ VDD = 3.3 V (standard ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
IOL [mA]
Figure 29. Typ. VOL @ VDD = 5 V (true open drain ports)
-40˚C
2
25˚C
1.75
85˚C
1.5
125˚C
VOL [V]
1.25
1
0.75
0.5
0.25
0
0
5
10
15
20
25
IOL [mA]
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Electrical characteristics
STM8S105xx
Figure 30. Typ. VOL @ VDD = 3.3 V (true open drain ports)
-40˚C
2
VOL [V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
IOL [mA]
Figure 31. Typ. VOL @ VDD = 5 V (high sink ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
0.75
0.5
0.25
0
0
5
10
15
20
25
IOL [mA]
Figure 32. Typ. VOL @ VDD = 3.3 V (high sink ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
0.75
0.5
0.25
0
0
2
4
6
8
IOL [mA]
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10
12
14
STM8S105xx
Electrical characteristics
Figure 33. Typ. VDD - VOH @ VDD = 5 V (standard ports)
-40˚C
2
VDD - VOH [V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
IOH [mA]
Figure 34. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
-40˚C
2
VDD - VOH [V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
1
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
IOH [mA]
Figure 35. Typ. VDD - VOH @ VDD = 5 V (high sink ports)
-40˚C
2
VDD - VOH [V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
1
0.75
0.5
0.25
0
0
5
10
15
20
25
IOH [mA]
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Electrical characteristics
STM8S105xx
Figure 36. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
-40˚C
2
VDD - VOH [V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
1
0.75
0.5
0.25
0
0
2
4
6
8
IOH [mA]
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10
12
14
STM8S105xx
9.3.7
Electrical characteristics
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 41.
Symbol
VIL(NRST)
VIH(NRST)
VOL(NRST)
NRST pin characteristics
Parameter
Conditions
NRST Input low level voltage (1)
NRST Input high level voltage
NRST Output low level voltage
NRST Pull-up resistor
tIFP(NRST)
NRST Input filtered pulse (3)
tOP(NRST)
NRST Input not filtered
NRST output pulse
(1)
Max
-0.3 V
0.3 x VDD
0.7 x VDD
VDD + 0.3
IOL=2 mA
Unit
V
0.5
(2)
RPU(NRST)
tINFP(NRST)
(1)
Typ 1)
Min
30
pulse (3)
40
60
kΩ
75
ns
500
ns
15
µs
(1)
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor
Data guaranteed by design, not tested in production.
Figure 37. Typical NRST VIL and VIH vs VDD @ 4 temperatures
-40˚C
6
25˚C
85˚C
5
125˚C
4
VIL/VIH [V]
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 38. Typical NRST pull-up resistance vs VDD @ 4 temperatures
-40˚C
25˚C
60
85˚C
NRESET pull-up resistance [kΩ]
3.
55
125˚C
50
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
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Electrical characteristics
STM8S105xx
Figure 39. Typical NRST pull-up current vs VDD @ 4 temperatures
140
NRESET pull-up current [µA]
120
100
80
60
-40˚C
25˚C
40
85˚C
20
125˚C
0
0
1
2
3
4
5
6
VDD [V]
The reset network shown in Figure 40 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 37. Otherwise the reset is not taken into account internally.
Figure 40. Recommended reset pin protection
STM8
VDD
RPU
NRST
External
reset
circuit
(optional)
74/99
0.01µF
Doc ID 14771 Rev 8
Filter
Internal reset
STM8S105xx
Electrical characteristics
SPI serial peripheral interface
9.3.8
Unless otherwise specified, the parameters given in Table 42 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 42.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
SPI characteristics
Parameter
Conditions
Min
Max
Master mode
0
8
Slave mode
0
6
SPI clock frequency
SPI clock rise and fall time Capacitive load: C = 30 pF
Unit
MHz
25
tsu(NSS)(1)
NSS setup time
Slave mode
4 x tMASTER
th(NSS)(1)
NSS hold time
Slave mode
70
SCK high and low time
Master mode
tSCK/2 - 15
Master mode
5
Slave mode
5
Master mode
7
Slave mode
10
(1)
tw(SCKH)
tw(SCKL)(1)
tsu(MI) (1)
tsu(SI)(1)
Data input setup time
th(MI) (1)
th(SI)(1)
Data input hold time
(1)(2)
Data output access time
Slave mode
tdis(SO)(1)(3) Data output disable time
Slave mode
ta(SO)
tSCK/2 + 15
ns
3 x tMASTER
25
tv(SO)
(1)
Data output valid time
Slave mode (after enable edge)
73
tv(MO)
(1)
Data output valid time
Master mode (after enable edge)
36
th(SO)
(1)
th(MO)(1)
Slave mode (after enable edge)
28
Master mode (after enable edge)
12
Data output hold time
1. Values based on design simulation and/or characterization results, and not tested in production.
2. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
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Electrical characteristics
STM8S105xx
Figure 41. SPI timing diagram - slave mode and CPHA = 0
NSS input
tSU(NSS)
SCK Input
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
Figure 42. SPI timing diagram - slave mode and CPHA = 1(1)
NSS input
tSU(NSS)
SCK Input
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
th(SO)
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
M SB IN
B I T1 IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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STM8S105xx
Electrical characteristics
Figure 43. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
tv(MO)
B I T1 OUT
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3 VDD and 0.7 VDD.
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Electrical characteristics
9.3.9
STM8S105xx
I2C interface characteristics
Table 43.
I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Min(2)
Max(2)
Min(2)
Max(2)
Unit
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(4)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
300
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
µs
STOP to START condition time
(bus free)
4.7
1.3
µs
tw(STO:STA)
Cb
µs
900(3)
µs
Capacitive load for each bus line
1. fMASTER, must be at least 8 MHz to achieve max fast
400
I 2C
400
speed (400 kHz).
2. Data based on standard I2C protocol requirement, not tested in production.
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time.
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL.
78/99
ns
Doc ID 14771 Rev 8
pF
STM8S105xx
Electrical characteristics
Figure 44. Typical application with I2C bus and timing diagram 1)
VDD
VDD
STM8S105xx
SDA
I²C bus
SCL
S TART REPEATED
S TART
S TART
tsu(STA)
SDA
tf(SDA)
tr(SDA)
th(STA)
SCL
tw(SCKH)
tsu(SDA)
tw(SCKL)
tr(SCK)
th(SDA)
tf(SCK)
S TOP
tsu(STA:STO)
tsu(STO)
ai15385
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
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Electrical characteristics
9.3.10
STM8S105xx
10-bit ADC characteristics
Subject to general operating conditions for VDDA, fMASTER, and TA unless otherwise
specified.
Table 44.
Symbol
fADC
ADC characteristics
Parameter
Conditions
Min
Typ
Max
VDDA = 2.95 to 5.5 V
1
4
VDDA = 4.5 to 5.5 V
1
6
3
5.5
V
ADC clock frequency
Unit
MHz
VDDA
Analog supply
VREF+
Positive reference voltage
2.75(1)
VDDA
V
VREF-
Negative reference voltage
VSSA
0.5(1)
V
VSSA
VDDA
V
VAIN
Conversion voltage range(2)
VREF-
VREF+
V
CADC
Internal sample and hold
capacitor
tS(2)
Sampling time
tSTAB
Wakeup time from standby
tCONV
Total conversion time (including
sampling time, 10-bit resolution)
Devices with external
VREF+/VREF- pins
3
fADC = 4 MHz
0.75
fADC = 6 MHz
0.5
pF
µs
7
µs
fADC = 4 MHz
3.5
µs
fADC = 6 MHz
2.33
µs
14
1/fADC
1. Data guaranteed by design, not tested in production..
2. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
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STM8S105xx
Electrical characteristics
Table 45.
Symbol
|ET|
|EO|
|EG|
|ED|
|EL|
ADC accuracy with RAIN < 10 kΩ , VDDA = 5 V
Parameter
Total unadjusted error
Offset error
(2)
(2)
Gain error (2)
Differential linearity
Integral linearity
error (2)
error (2)
Conditions
Typ
Max(1)
fADC = 2 MHz
1
2.5
fADC = 4 MHz
1.4
3
fADC = 6 MHz
1.6
3.5
fADC = 2 MHz
0.6
2
fADC = 4 MHz
1.1
2.5
fADC = 6 MHz
1.2
2.5
fADC = 2 MHz
0.2
2
fADC = 4 MHz
0.6
2.5
fADC = 6 MHz
0.8
2.5
fADC = 2 MHz
0.7
1.5
fADC = 4 MHz
0.7
1.5
fADC = 6 MHz
0.8
1.5
fADC = 2 MHz
0.6
1.5
fADC = 4 MHz
0.6
1.5
fADC = 6 MHz
0.6
1.5
Unit
LSB
1. Data based on characterisation results for LQFP80 device with VREF+/VREF-, not tested in production.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
Table 46.
Symbol
ADC accuracy with RAIN < 10 kΩ RAIN, VDDA = 3.3 V
Parameter
|ET|
Total unadjusted error(2)
|EO|
Offset error(2)
|EG|
Gain error(2)
|ED|
Differential linearity error(2)
|EL|
Integral linearity error(2)
Conditions
Typ
Max(1)
fADC = 2 MHz
1.1
2
fADC = 4 MHz
1.6
2.5
fADC = 2 MHz
0.7
1.5
fADC = 4 MHz
1.3
2
fADC = 2 MHz
0.2
1.5
fADC = 4 MHz
0.5
2
fADC = 2 MHz
0.7
1
fADC = 4 MHz
0.7
1
fADC = 2 MHz
0.6
1.5
fADC = 4 MHz
0.6
1.5
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Unit
LSB
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Electrical characteristics
STM8S105xx
Figure 45. ADC accuracy characteristics
EG
1023
1022
1021
1LSB
IDEAL
V
–V
DDA
SSA
= ----------------------------------------1024
(2)
ET
7
(3)
(1)
6
5
EO
4
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
1021102210231024
VDDA
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 46. Typical application with ADC
VDD
VT
0.6V
RAIN
AINx
VAIN
CAIN
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STM8
10-bit A/D
conversion
VT
0.6V
Doc ID 14771 Rev 8
IL
±1µA
CADC
STM8S105xx
9.3.11
Electrical characteristics
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 47.
Symbol
EMS data
Parameter
Conditions
Level/class
VFESD
VDD = 5 V, TA=+25 °C,
Voltage limits to be applied on any I/O pin to
fMASTER = 16 MHz,
induce a functional disturbance
onforming to IEC 1000-4-2
2B
VEFTB
Fast transient voltage burst limits to be
VDD= 5 V, TA=+25 °C,
applied through 100pF on VDD and VSS pins fMASTER = 16 MHz,
to induce a functional disturbance
conforming to IEC 1000-4-4
4A
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Electrical characteristics
STM8S105xx
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 48.
EMI data
Conditions
Symbol
Max fHSE/fCPU(1)
Parameter
Monitored
frequency band
General conditions
Peak level
SEMI
VDD = 5 V,
TA = +25 °C,
LQFP48 package
conforming to SAE J 1752/3
8 MHz/
8 MHz
8 MHz/
16 MHz
0.1MHz to 30 MHz
13
14
30 MHz to 130 MHz
23
19
130 MHz to 1 GHz
-4
-4
2
1.5
SAE EMI level
Unit
dBµV
—
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 49.
Symbol
ESD absolute maximum ratings
Ratings
Conditions
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge voltage
(Human body model)
TA = +25°C, conforming
to JESD22-A114
A
2000
V
VESD(CDM)
Electrostatic discharge voltage
(Charge device model)
TA=+25°C, conforming to
JESD22-C101
IV
1000
V
1. Data based on characterization results, not tested in production
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Class
Doc ID 14771 Rev 8
STM8S105xx
Electrical characteristics
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance:
●
A supply overvoltage (applied to each power supply pin)
●
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 50.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
Conditions
Class(1)
TA = +25 °C
A
TA = +85 °C
A
TA = +125 °C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
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Package characteristics
10
STM8S105xx
Package characteristics
To meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
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STM8S105xx
Package characteristics
10.1
Package mechanical data
10.1.1
LQFP package mechanical data
Figure 47. 48-pin low profile quad flat package (7 x 7)
D
ccc C
D1
D3
36
A
A2
25
24
37
L1
b
E3 E1 E
48
Pin 1
identification
13
1
L
A1
K
c
12
5B_ME
Table 51.
48-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.170
c
0.090
D
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.220
0.270
0.0067
0.0087
0.0106
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
5.500
0.0059
0.0079
0.2165
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.500
0.2165
e
0.500
0.0197
L
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0.0°
3.5°
0.0236
0.0295
0.0394
7.0°
0.0°
0.080
3.5°
7.0°
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
STM8S105xx
Figure 48. 44-pin low profile quad flat package (10 x 10)
D
ccc C
D1
D3
A
A2
23
33
22
34
L1
b
E3 E1 E
44
Pin 1
identification
12
1
L
A1
K
c
11
4Y_ME
Table 52.
44-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.600
A1
0.050
A2
1.350
b
0.300
c
0.090
D
11.800
D1
9.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.370
0.450
0.0118
0.0146
0.0177
0.200
0.0035
12.000
12.200
0.4646
0.4724
0.4803
10.000
10.200
0.3858
0.3937
0.4016
8.000
0.0059
0.0079
0.3150
E
11.800
12.000
12.200
0.4646
0.4724
0.4803
E1
9.800
10.000
10.200
0.3858
0.3937
0.4016
E3
8.000
0.3150
e
0.800
0.0315
L
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0.0°
3.5°
0.0236
0.0295
0.0394
7.0°
0.0°
0.100
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Typ
Doc ID 14771 Rev 8
3.5°
7.0°
0.0039
STM8S105xx
Package characteristics
Figure 49. 32-pin low profile quad flat package (7 x 7)
ccc C
D
D1
D3
24
A
A2
17
16
25
L1
b
E3
32
E1 E
9
Pin 1
identification
L
A1
1
K
c
8
5V_ME
Table 53.
32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
Typ
1.600
A1
0.050
A2
1.350
b
0.300
c
0.090
D
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.370
0.450
0.0118
0.0146
0.0177
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
5.600
0.0059
0.0079
0.2205
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.600
0.2205
e
0.800
0.0315
L
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0.0°
3.5°
0.0236
0.0295
0.0394
7.0°
0.0°
0.100
3.5°
7.0°
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
10.1.2
STM8S105xx
VFQFPN package mechanical data
Figure 50. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E
b
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
Table 54.
42_ME
32-lead very thin fine pitch quad flat no-lead package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.80
0.90
1.00
0.0315
0.0354
0.0394
A1
0
0.02
0.05
0.0008
0.0020
A3
0.20
0.0079
b
0.18
0.25
0.30
0.0071
0.0098
0.0118
D
4.85
5.00
5.15
0.1909
0.1969
0.2028
D2
3.20
3.45
3.70
0.1260
E
4.85
5.00
5.15
0.1909
0.1969
0.2028
E2
3.20
3.45
3.70
0.1260
0.1358
0.1457
e
L
ddd
0.50
0.30
0.40
0.0197
0.50
0.0118
0.08
1. Values in inches are converted from mm and rounded to 4 decimal digits
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0.1457
Doc ID 14771 Rev 8
0.0157
0.0197
0.0031
STM8S105xx
10.1.3
Package characteristics
SDIP32 package mechanical data
Figure 51. 32-lead shrink plastic DIP (400 ml) package
E
E1
A2
A1
B1
B
A
L
e
eA
C
eB
D
32
17
1
16
76_ME
Table 55.
32-lead shrink plastic DIP (400 ml) package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
3.556
3.759
5.080
0.1400
0.1480
0.2000
A1
0.508
A2
3.048
3.556
4.572
0.1200
0.1400
0.1800
B
0.356
0.457
0.584
0.0140
0.0180
0.0230
B1
0.762
1.016
1.397
0.0300
0.0400
0.0550
C
0.203
0.254
0.356
0.0079
0.0100
0.0140
D
27.430
27.940
28.450
1.0799
1.1000
1.1201
E
9.906
10.410
11.050
0.3900
0.4098
0.4350
E1
7.620
8.890
9.398
0.3000
0.3500
0.3700
0.0200
e
1.778
0.0700
eA
10.160
0.4000
eB
L
12.700
2.540
3.048
3.810
0.5000
0.1000
0.1200
0.1500
1. Values in inches are converted from mm and rounded to 4 decimal digits
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Package characteristics
10.2
STM8S105xx
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 18: General operating conditions on page 50.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
●
TAmax is the maximum ambient temperature in ° C
●
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
●
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
●
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
●
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.
Table 56.
Thermal characteristics(1)
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP 48 - 7 x 7 mm
57
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 44 - 10 x 10 mm
54
°C/W
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
59
°C/W
ΘJA
Thermal resistance junction-ambient
VFQFPN 32 - 5 x 5 mm
22
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.2.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
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10.2.2
Package characteristics
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Figure 52: STM8S105xx access line ordering information scheme on page 94).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
●
Maximum ambient temperature TAmaz = 82 °C (measured according to JESD51-2)
●
IDDmax = 15 mA, VDD = 5.5 V
●
Maximum 8 standard I/Os used at the same time in output at low level with
IOL = 10 mA, VOL= 2 V
●
Maximum 4 high sink I/Os used at the same time in output at low level with
IOL = 20 mA, VOL= 1.5 V
●
Maximum 2 true open drain I/Os used at the same time in output at low level with
IOL = 20 mA, VOL= 2 V
PINTmax = 15 mA x 5.5 V = 82.5 mW
PIOmax = (10 mA x 2 V x 8 )+(20 mA x 2 V x 2)+(20 mA x 1.5 V x 4) = 360 mW
This gives: PINTmax = 82.5 mW and PIOmax 360 mW:
PDmax = 82.5 mW + 360 mW
Thus: PDmax = 443 mW
Using the values obtained in Table 56: Thermal characteristics on page 92 TJmax is
calculated as follows for LQFP32 59°C/W:
TJmax = 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
This is within the range of the suffix 6 version parts (-40 < TJ < 106° C). In this case, parts
must be ordered at least with the temperature range suffix 6.
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Ordering information
11
STM8S105xx
Ordering information
Figure 52. STM8S105xx access line ordering information scheme
Example:
STM8
S
105
K
4
T
6
C
TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
105 = access line STM8S105x
Pin count
K = 32 pins
S = 44 pins
C = 48 pins
Program memory size
4 = 16 Kbytes
6 = 32 Kbytes
Package type
B = SDIP
T = LQFP
U = VFQFPN
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST sales office nearest to
you.
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12
STM8 development tools
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
●
Occurrence and time profiling and code coverage (new features)
●
Advanced breakpoints with up to 4 levels of conditions
●
Data breakpoints
●
Program and data trace recording up to 128 KB records
●
Read/write on the fly of memory during emulation
●
In-circuit debugging/programming via SWIM protocol
●
8-bit probe analyzer
●
1 input and 2 output triggers
●
Power supply follower managing application voltages between 1.62 to 5.5 V
●
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
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STM8 development tools
12.2
STM8S105xx
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
12.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST Visual Develop – Full-featured integrated development environment from ST, featuring
●
Seamless integration of C and ASM toolsets
●
Full-featured debugger
●
Project management
●
Syntax highlighting editor
●
Integrated programming interface
●
Support of advanced emulation features for STice such as code profiling and coverage
ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
12.3
●
Cosmic C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
●
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
●
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
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STM8S105xx
13
Revision history
Revision history
Table 57.
Document revision history
Date
Revision
05-Jun-2008
1
Initial release.
23-Jun-2008
2
Corrected number of high sink outputs to 9 in I/Os on page 1.
Updated part numbers in Table 2: STM8S105xx access line features
on page 10.
3
Updated part numbers in Table 2: STM8S105xx access line features
on page 10.
USART renamed UART1, LINUART renamed UART2.
Added Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin access
line devices.
4
Removed STM8S102xx and STM8S104xx root part numbers
corresponding to devices without data EEPROM.
Updated STM8S103 pinout in Section 5.2 on page 29.
Added low and medium density Flash memory categories.
Added Note 1 in Table 16: Current characteristics.
Updated Table 6: Option bytes on page 39.
05-Feb-2009
5
Updated STM8S103 pinout in Section 5.2 on page 29
Updated number of High Sink I/Os in pinout.
TSSOP20 pinout modified (PD4 moved to pin 1 etc.)
Added WFQFN20 package
Updated Section 6: Option bytes on page 39
Added Section 7: Memory and register map on page 44
27-Feb-2009
6
Removed STM8S103x products (separate STM8S103 datasheet
created)
Updated Section 9: Electrical characteristics
7
Added SDIP32 silhouette and package to the Features and
Section 10.1.3: SDIP32 package mechanical data; added Figure 6:
SDIP32-pin pinout; updated Table 6: Pin description for STM8S105
microcontrollers and Figure 52: STM8S105xx access line ordering
information scheme for the SDIP.
Updated VDD range (2.95 V to 5.5 V) on page 1.
Amended name of package VQFPN32
Added Table 3 on page 16.
Updated Section 4.8: Auto wakeup counter on page 18.
Updated pins 25, 30, and 31 in Figure 5.
Removed Table 7: Pin-to-pin comparison of pin 7 to 12 in 32-pin
access line devices.
Added Table 14: Description of alternate function remapping bits
[7:0] of OPT2.
12-Aug-2008
17-Sep-2008
12-May-2009
Changes
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Revision history
STM8S105xx
Table 57.
Document revision history (continued)
Date
12-May-2009
10-Jun-2009
98/99
Revision
Changes
7
cont’d
Section 9: Electrical characteristics: Updated VCAP specifications;
updated Table 15, Table 18, Table 20, Table 21, Table 22, Table 23,
Table 24, Table 25, Table 26, Table 27, Table 29, Table 35, and
Table 42; added current consumption curves Figure 13 to Figure 18;
removed figure 20: typical HSE frequency vs fcpu @ 4 temperatures;
updated Figure 13, Figure 14, Figure 15, Figure 16 and Figure 17 on
page 60; modified HSI accuracy in Table 33: HSI oscillator
characteristics on page 63; added Figure 44: Typical application with
I2C bus and timing diagram 1) on page 79; modified fSCK, tV(SO) and
tV(MO) in Table 42: SPI characteristics on page 75; updated figures
and tables of High speed internal RC oscillator (HSI) on page 63;
replaced Figure 23, Figure 24, Figure 26, and Figure 39 on page 74.
Section 10: Package characteristics: Updated Table 56: Thermal
characteristics and removed Table 57: Junction temperature range.
Updated Figure 52: STM8S105xx access line ordering information
scheme.
8
Document status changed from “preliminary data” to “datasheet”.
Standardized name of the VFQFPN package.
Removed ‘wpu’ from I2C pins in Table 6: Pin description for
STM8S105 microcontrollers.
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