AD8131 Low-Cost, High-Speed Differential Driver

a
Low-Cost, High-Speed
Differential Driver
AD8131
FUNCTIONAL BLOCK DIAGRAM
FEATURES
High Speed
400 MHz –3 dB Full Power Bandwidth
2000 V/␮s Slew Rate
Fixed Gain of 2 with No External Components
Internal Common-Mode Feedback to Improve Gain
and Phase Balance
–60 dB @10 MHz
Separate Input to Set the Common-Mode Output
Voltage
Low Distortion
68 dB SFDR @ 5 MHz 200 ⍀ Load
Low Power 7.5 mA @ 3 V
Power Supply Range +2.7 V to ⴞ5 V
8 +DIN
1
750V
VOCM
750V
2
7 NC
V+ 3
6 V–
1.5kV
1.5kV
+OUT 4
5 –OUT
AD8131
NC = NO CONNECT
–20
DVOUT,dm = 2V p-p
DVOUT,cm/DVOUT, dm
–30
BALANCE ERROR – dB
APPLICATIONS
Video Line Driver
Digital Line Driver
Low Power Differential ADC Driver
Differential In/Out Level Shifting
Single-Ended Input to Differential Output Driver
–DIN
–40
–50
VS = +5V
–60
–70
VS = 65V
–80
GENERAL DESCRIPTION
The AD8131 is a differential or single-ended input to differential output driver requiring no external components for a fixed
gain of 2. The AD8131 is a major advancement over op amps
for driving signals over long lines or for driving differential input
ADCs. The AD8131 has a unique internal feedback feature that
provides output gain and phase matching that are balanced to
–60 dB at 10 MHz, reducing radiated EMI and suppressing
harmonics. Manufactured on ADI’s next generation XFCB
bipolar process, the AD8131 has a –3 dB bandwidth of 400 MHz
and delivers a differential signal with very low harmonic distortion.
The AD8131 is a differential driver for the transmission of
high-speed signals over low-cost twisted pair or coax cables.
The AD8131 can be used for either analog or digital video
signals or for other high-speed data transmission. The AD8131
driver is capable of driving either Cat3 or Cat5 twisted pair or coax
with minimal line attenuation. The AD8131 has considerable
cost and performance improvements over discrete line driver
solutions.
1
10
100
FREQUENCY – MHz
1000
Figure 1. Output Balance Error vs. Frequency
The AD8131 can replace transformers in a variety of applications preserving low frequency and dc information. The AD8131
does not have the susceptibility to magnetic interference and
hysteresis of transformers, while being smaller in size, easier
to work with, and has the high reliability associated with ICs.
The AD8131’s differential output also helps balance the input
for differential ADCs, optimizing the distortion performance of
the ADCs. The common-mode level of the differential output
is adjustable by a voltage on the VOCM pin, easily level-shifting
the input signals for driving single supply ADCs with dual supply
signals. Fast overload recovery preserves sampling accuracy.
The AD8131 will be available in both SOIC and µSOIC packages
for operation over –40ⴗC to +85ⴗC.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
AD8131–SPECIFICATIONS
(@ 25ⴗC, VS = ⴞ5 V, VOCM = 0, G = 2, RL,dm = 200 ⍀, unless otherwise noted. Refer to
Figures 2 and 37 for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
Parameter
Conditions
Min
Typ
Max
Unit
ⴞDIN to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
IP3
Voltage Noise (RTO)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Offset Voltage
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Gain
Output Balance Error
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, 10% to 90%
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V Step
400
320
85
2000
14
5
MHz
MHz
MHz
V/µs
ns
ns
VOUT = 2 V p-p, 5 MHz, RL,dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
f = 20 MHz
NTSC, RL,dm = 150 Ω
NTSC, RL,dm = 150 Ω
–68
–63
–95
–79
–94
–70
–101
–77
–54
30
25
0.01
0.06
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
%
Degrees
VOS,dm = VOUT,dm; VDIN+ = VDIN– = VOCM = 0 V
TMIN to T MAX Variation
VOCM = Float
TMIN to T MAX Variation
Single-Ended Input
Differential Input
±2
±8
±4
± 10
1.125
1.5
1
–7.0 to +5.0
–70
∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ± 0.5 V
Maximum ∆VOUT; Single-Ended Output
∆VOUT,dm/∆VIN,dm; ∆VIN,dm = ± 0.5 V
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
1.97
–3.6 to +3.6
60
2
–70
±7
2.03
mV
µV/°C
mV
µV/°C
kΩ
kΩ
pF
V
dB
V
mA
V/V
dB
VOCM to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
∆VOCM = 600 mV
VOCM = –1 V to +1 V
210
500
MHz
V/µs
VOS,cm = VOUT,cm; VDIN+ = V DIN– = VOCM = 0 V
VOCM = Float
± 3.6
120
± 1.5
± 2.5
0.5
–60
1
V
kΩ
mV
mV
µA
dB
V/V
[∆VOUT,dm/∆VOCM]; ∆VOCM = ± 0.5 V
∆VOUT,cm/∆VOCM; ∆VOCM = ± 1 V
VDIN+ = VDIN– = VOCM = 0 V
TMIN to T MAX Variation
∆VOUT,dm/∆VS; ∆VS = ± 1 V
OPERATING TEMPERATURE RANGE
0.988
± 1.4
10.5
–40
11.5
25
–70
±7
1.012
± 5.5
12.5
–56
V
mA
µA/°C
dB
+85
°C
Specifications subject to change without notice.
–2–
REV. 0
AD8131
(@ 25ⴗC, V = 5 V, V = 2.5 V, G = 2, R = 200 ⍀, unless otherwise noted. Refer to Figures 2 and 37
SPECIFICATIONS
for test setup and label descriptions. All specifications refer to single-ended input and differential outputs unless noted.)
S
Parameter
OCM
L,dm
Conditions
Min
Typ
Max
Unit
ⴞDIN to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Large Signal Bandwidth
–3 dB Small Signal Bandwidth
Bandwidth for 0.1 dB Flatness
Slew Rate
Settling Time
Overdrive Recovery Time
NOISE/HARMONIC PERFORMANCE
Second Harmonic
Third Harmonic
IMD
IP3
Voltage Noise (RTO)
Differential Gain Error
Differential Phase Error
INPUT CHARACTERISTICS
Offset Voltage
Input Resistance
Input Capacitance
Input Common-Mode Voltage
CMRR
OUTPUT CHARACTERISTICS
Output Voltage Swing
Linear Output Current
Gain
Output Balance Error
VOUT = 2 V p-p
VOUT = 0.2 V p-p
VOUT = 0.2 V p-p
VOUT = 2 V p-p, 10% to 90%
0.1%, VOUT = 2 V p-p
VIN = 5 V to 0 V Step
385
285
65
1600
18
5
MHz
MHz
MHz
V/µs
ns
ns
VOUT = 2 V p-p, 5 MHz, RL,dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 800 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 200 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 200 Ω
VOUT = 2 V p-p, 5 MHz, RL,dm = 800 Ω
VOUT = 2 V p-p, 20 MHz, R L,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
20 MHz, RL,dm = 800 Ω
f = 20 MHz
NTSC, RL,dm = 150 Ω
NTSC, RL,dm = 150 Ω
–67
–56
–94
–77
–74
–67
–95
–74
–51
29
25
0.02
0.08
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBm
nV/√Hz
%
Degrees
VOS,dm = VOUT,dm; VDIN+ = VDIN– = VOCM = 2.5 V
TMIN to T MAX Variation
VOCM = Float
TMIN to T MAX Variation
Single-Ended Input
Differential Input
±3
±7
±8
±4
± 10
1.125
1.5
1
–1.0 to +4.0
–70
mV
µV/°C
mV
µV/°C
kΩ
kΩ
pF
V
dB
1.0 to 3.7
45
2
–62
V
mA
V/V
dB
∆VOUT,dm/∆VIN,cm; ∆VIN,cm = ± 0.5 V
Maximum ∆VOUT; Single-Ended Output
∆VOUT,dm/∆VIN,dm; ∆VIN,dm = ± 0.5 V
∆VOUT,cm/∆VOUT,dm; ∆VOUT,dm = 1 V
1.96
2.04
VOCM to ⴞOUT Specifications
DYNAMIC PERFORMANCE
–3 dB Bandwidth
Slew Rate
DC PERFORMANCE
Input Voltage Range
Input Resistance
Input Offset Voltage
Input Bias Current
VOCM CMRR
Gain
POWER SUPPLY
Operating Range
Quiescent Current
Power Supply Rejection Ratio
∆VOCM = 600 mV
VOCM = 1.5 V to 3.5 V
VOS,cm = VOUT,cm; VDIN+ = VDIN– = VOCM = 2.5 V
VOCM = Float
[∆VOUT,dm/∆VOCM]; ∆VOCM = 2.5 V ± 0.5 V
∆VOUT,cm/∆VOCM; ∆VOCM = 2.5 V ± 1 V
VDIN+ = VDIN = VOCM = 2.5 V
TMIN to T MAX Variation
∆VOUT,dm/∆VS; ∆VS = ± 0.5 V
OPERATING TEMPERATURE RANGE
2.7
9.25
–40
Specifications subject to change without notice.
REV. 0
0.985
–3–
200
450
MHz
V/µs
1.0 to 3.7
30
±5
± 10
0.5
–60
1
V
kΩ
mV
mV
µA
dB
V/V
10.25
20
–70
± 12
1.015
11
11.25
–56
V
mA
µA/°C
dB
+85
°C
AD8131
ABSOLUTE MAXIMUM RATINGS 1
PIN FUNCTION DESCRIPTIONS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 5.5 V
VOCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± VS
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 250 mW
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
Pin No. Name
1
2
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the
device at these or any other conditions above listed in the operational section of this
specification is not implied. Exposure to Absolute Maximum Ratings for any
extended periods may affect device reliability.
2
Thermal resistance measured on SEMI standard 4-layer board.
8-Lead SOIC θ JA = 121°C/W
8-Lead µSOIC θ JA = 142°C/W
Function
–DIN
VOCM
Negative Input.
Voltage applied to this pin sets the commonmode output voltage with a ratio of 1:1. For
example, 1 V dc on VOCM will set the dc bias
level on +OUT and –OUT to 1 V.
V+
Positive Supply Voltage.
+OUT Positive Output. Note: the voltage at –DIN is
inverted at +OUT.
–OUT Negative Output. Note: the voltage at +DIN
is inverted at –OUT.
V–
Negative Supply Voltage.
NC
No Connect.
+DIN
Positive Input
3
4
5
6
7
8
PIN CONFIGURATION
–DIN
8 +DIN
1
750V
750V
VOCM
2
7 NC
V+ 3
6 V–
1.5kV
1.5kV
+OUT 4
5 –OUT
AD8131
NC = NO CONNECT
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD8131AR
AD8131AR-REEL
AD8131AR-REEL7
AD8131ARM
AD8131ARM-REEL
AD8131ARM-REEL7
AD8131-EVAL
–40°C to +85°C
8-Lead SOIC
SO-8
–40°C to +85°C
8-Lead µSOIC
RM-8
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD8131 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. 0
AD8131
12
12
VOUT = 200mV p-p
VS = 65V
VOUT = 200mV p-p
9
9
1500V
RL,dm = 200V
AD8131
750V
6
GAIN – dB
49.9V
GAIN – dB
mSO
750V
3
VS = 65V
6
3
VS = 5V
SOIC
24.9V
0
0
1500V
–3
–3
1
Figure 2. Basic Test Circuit
10
100
FREQUENCY – MHz
1000
Figure 3. Small Signal Frequency
Response
12
1
10
100
FREQUENCY – MHz
Figure 4. Small Signal Frequency
Response
12
VOUT = 2V p-p
VS = 65V
VOUT = 2V p-p
9
9
1500V
mSO
6
GAIN – dB
GAIN – dB
VS = 65V
SOIC
3
750V
6
0
2:1 TRANSFORMER
300V
LPF
49.9V
AD8131
HPF
ZIN = 50V
300V
24.9V 750V
3
VS = 5V
1500V
0
–3
–3
1
10
100
FREQUENCY – MHz
1000
1
Figure 5. Large Signal Frequency
Response
–50
10
100
FREQUENCY – MHz
1000
Figure 6. Large Signal Frequency
Response
–40
RL,dm = 800V
VOUT,dm = 1V p-p
–50
RL,dm = 800V
VOUT,dm = 2V p-p
Figure 7. Harmonic Distortion Test
Circuit (RL,dm = 800 Ω)
–55
HD3 (VS = 65V)
HD3 (F = 20MHz)
HD3 (VS = 5V)
–80
HD2 (VS = 3V)
–90
HD2 (VS = 5V)
–100
HD3 (VS = 5V)
–70
–80
HD2 (VS = 65V)
–90
10
20
30
40
50
FREQUENCY – MHz
60
70
–110
0
–75
HD2 (F = 20MHz)
–85
–95
HD2 (VS = 5V)
–105
–100
Figure 8. Harmonic Distortion vs.
Frequency
REV. 0
–60
DISTORTION – dBc
–70
–110
0
VS = 65V
RL,dm = 800V
–65
HD3 (VS = 3V)
DISTORTION – dBc
–60
DISTORTION – dBc
1000
HD2 (F = 5MHz)
HD3 (F = 5MHz)
–115
10
20
30
40
50
FREQUENCY – MHz
60
70
Figure 9. Harmonic Distortion vs.
Frequency
–5–
0
1
2
3
4
5
6
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
Figure 10. Harmonic Distortion vs.
Differential Output Voltage
AD8131
VS = 5V
RL,dm = 800V
–60
HD3 (F = 20MHz)
DISTORTION – dBc
DISTORTION – dBc
–60
–70
–80
HD2 (F = 20MHz)
HD3 (F = 5MHz)
–90
–50
VS = 3V
RL,dm = 800V
–60
HD3 (F = 20MHz)
–70
–80
HD2 (F = 20MHz)
–90
–100
–100
VS = 65V
VOUT,dm = 2V p-p
HD3 (F = 5MHz)
DISTORTION – dBc
–50
–50
HD3 (F = 20MHz)
HD2 (F = 20MHz)
–70
–80
–90
HD2 (F = 5MHz)
–100
HD2 (F = 5MHz)
HD2 (F = 5MHz)
HD3 (F = 5MHz)
Figure 11. Harmonic Distortion vs.
Differential Output Voltage
–50
Figure 12. Harmonic Distortion vs.
Differential Output Voltage
–50
VS = 5V
VOUT,dm = 2V p-p
–60
VS = 3V
VOUT,dm = 1V p-p
–60
HD2 (F = 20MHz)
HD3 (F = 20MHz)
–70
–80
–90
HD2 (F = 5MHz)
DISTORTION – dBc
DISTORTION – dBc
–110
1.75
0.25
0.50
0.75
1.25
1.0
1.5
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
DIFFERENTIAL OUTPUT VOLTAGE – V p-p
–110
200
300 400 500 600 700 800 900 1000
RLOAD – V
Figure 13. Harmonic Distortion vs.
RLOAD
10
0
HD3 (F = 20MHz)
–10
HD2 (F = 20MHz)
fC = 50MHz
VS = 65V
RL,dm = 800V
–20
–70
–30
POUT – dBm
–110
0
–80
–90
–40
–50
–60
–70
–80
HD2 (F = 5MHz)
–100
–100
HD3 (F = 5MHz)
HD3 (F = 5MHz)
–90
–100
–110
200 300 400 500 600 700 800 900 1000
RLOAD – V
Figure 14. Harmonic Distortion vs.
RLOAD
–110
200 300 400 500 600 700 800 900 1000
RLOAD – V
Figure 15. Harmonic Distortion vs.
RLOAD
–110
49.5
50
FREQUENCY – MHz
50.5
Figure 16. Intermodulation Distortion
45
RL,dm = 800V
INTERCEPT – dBm
40
VS = 65V
VOUT,dm
35
VS = 5V
VS = 65V
VOUT+
VS = 65V
30
VOUT–
25
VS = 5V
V+DIN
20
1V
15
0
10
30
20
40
50
60
FREQUENCY – MHz
70
5ns
40mV
5ns
80
Figure 17. Third Order Intercept vs.
Frequency
Figure 18. Large Signal Transient
Response
–6–
Figure 19. Small Signal Transient
Response
REV. 0
AD8131
VS = 5V
VOUT = 1.5V p-p
VOUT = 2V p-p
VS = 3V
VS = 65V
2mV/DIV
VOUT,dm
VS = 65V
V+DIN
400mV
300mV
5ns
Figure 20. Large Signal Transient
Response
5ns
4ns
1V/DIV
Figure 21. Large Signal Transient
Response
Figure 22. 0.1% Settling Time
0
DVOUT,dm
DVS
CL = 5pF
CL = 0pF
CL = 20pF
–10
–20
1500V
49.9V
750V
24.9V
CL
AD8131
150V
+PSRR
(VS = 65V, +5V)
–40
–50
VS = 65V
24.9V
24.9V
–30
PSRR – dB
750V
–PSRR
(VS = 65V)
–60
–70
1500V
400mV
Figure 23. Capacitor Load Drive Test
Circuit
1.25ns
–80
10
100
FREQUENCY – MHz
1000
Figure 25. PSRR vs. Frequency
Figure 24. Large Signal Transient
Response for Various Capacitor
Loads
–20
1
100
VS = 65V
VIN,cm = 1V p-p
SINGLE-ENDED OUTPUT
–30
1500V
AD8131
24.9V
VOUT,dm
VOUT,cm
100V
1500V
–50
REV. 0
DVOUT,dm/
DVIN,cm
–60
–70
–80
1
Figure 26. CMRR Test Circuit
IMPEDANCE – V
750V
100V
CMRR – dB
–40
750V
10
1
VS = 5V
DVOUT,cm/DVIN,cm
10
100
FREQUENCY – MHz
VS = 65V
1000
Figure 27. CMRR vs. Frequency
–7–
0.1
1
10
FREQUENCY – MHz
100
Figure 28. Single-Ended ZOUT vs.
Frequency
AD8131
4
DVOUT,dm = 2V p-p
DVOUT,cm/DVOUT,dm
DIFFERENTIAL OFFSET VOLTAGE – mV
–20
–30
750V
49.9V
750V
BALANCE ERROR – dB
1500V
100V
AD8131
100V
24.9V
–40
–50
–60
–70
1500V
VS = 5V
VS = 65V
–80
1
Figure 29. Output Balance Error Test
Circuit
Figure 30. Output Balance Error vs.
Frequency
15
VS = 65V
2
0
VS = +3V(VOCM = 0V)
6
VS = 5V
90
3
70
0
GAIN – dB
9
NOISE – nV/ Hz
SUPPLY CURRENT – mA
VS = 65V
50
–10
10
30
50
TEMPERATURE – 8C
DVOUT,cm
DVOCM
VS = 65V
11
–30
90
70
Figure 31. Output Offset Voltage vs.
Temperature
110
13
VS = 5V
1
–1
–50
1000
10
100
FREQUENCY – MHz
3
VS = 65V
DVOCM = 600mV p-p
–3
DVOCM = 2V p-p
7
–6
30
VS = 3V
5
–50
–30
–10
10
30
50
TEMPERATURE – 8C
90
70
Figure 32. Quiescent Current vs.
Temperature
–20
DVOUT,dm
DVOCM
–30
10
0.1k
–9
1k
100k
10k
1M
FREQUENCY – Hz
100M
Figure 33. Voltage Noise vs.
Frequency
1
100
10
FREQUENCY – MHz
1000
Figure 34. VOCM Gain Response
VS = 65V
DVOCM = 600mV p-p
VOUT,cm
–40
GAIN – dB
10M
–50
DVOCM = 2V p-p
–60
–70
VS = 65V
VOCM = –1V TO +1V
–80
–90
400mV
1
10
100
FREQUENCY – MHz
5ns
1000
Figure 35. VOCM CMRR vs. Frequency
Figure 36. VOCM Transient Response
–8–
REV. 0
AD8131
The AD8131 uses two feedback loops to separately control the
differential and common-mode output voltages. The differential
feedback, set by internal resistors, controls only the differential
output voltage. The common-mode feedback controls only the
common-mode output voltage. This architecture makes it easy
to arbitrarily set the output common-mode level. It is forced, by
internal common-mode feedback, to be equal to the voltage
applied to the VOCM input, without affecting the differential
output voltage.
The AD8131 architecture results in outputs that are very highly
balanced over a wide frequency range without requiring external
components or adjustments. The common-mode feedback loop
forces the signal component of the output common-mode voltage
to be zeroed. The result is nearly perfectly balanced differential
outputs, of identical amplitude and exactly 180 degrees apart
in phase.
OPERATIONAL DESCRIPTION
Definition of Terms
RF
+DIN
RG
+IN
AD8131
VOCM
–DIN
–OUT
–OUT
RL,dm
VOUT,dm
+OUT
RG
–IN
+OUT
RF
Figure 37. Circuit Definitions
Differential voltage refers to the difference between two node
voltages. For example, the output differential voltage (or
equivalently output differential-mode voltage) is defined as:
VOUT,dm = (V+OUT – V–OUT)
V+OUT and V–OUT refer to the voltages at the +OUT and –OUT
terminals with respect to a common reference.
Analyzing an Application Circuit
The AD8131 uses high open-loop gain and negative feedback to
force its differential and common-mode output voltages in such
a way as to minimize the differential and common-mode error
voltages. The differential error voltage is defined as the voltage
between the differential inputs labeled +IN and –IN in Figure
37. For most purposes, this voltage can be assumed to be zero.
Similarly, the difference between the actual output commonmode voltage and the voltage applied to VOCM can also be
assumed to be zero. Starting from these two assumptions, any
application circuit can be analyzed.
Common-mode voltage refers to the average of two node voltages. The output common-mode voltage is defined as:
VOUT,cm = (V+OUT + V–OUT)/2
Balance is a measure of how well differential signals are matched
in amplitude and exactly 180 degrees apart in phase. Balance
is most easily determined by placing a well-matched resistor
divider between the differential voltage nodes and comparing
the magnitude of the signal at the divider’s midpoint with the
magnitude of the differential signal. By this definition, output
balance is the magnitude of the output common-mode voltage
divided by the magnitude of the output differential-mode
voltage:
Output Balance Error =
Closed-Loop Gain
The differential mode gain of the circuit in Figure 37 can be
determined to be described by the following equation:
VOUT ,dm
VOUT , cm
VIN ,dm
VOUT , dm
RF
= 2
RG
where RF = 1.5 kΩ and R G = 750 Ω nominally.
THEORY OF OPERATION
Estimating the Output Noise Voltage
The AD8131 differs from conventional op amps in that it has
two outputs whose voltages move in opposite directions. Like
an op amp, it relies on high open-loop gain and negative feedback to force these outputs to the desired voltages. The AD8131
behaves much like a standard voltage feedback op amp and
makes it easy to perform single-ended-to-differential conversion,
common-mode level-shifting, and amplification of differential
signals.
Similar to the case of a conventional op amp, the differential
output errors (noise and offset voltages) can be estimated by
multiplying the input referred terms, at +IN and –IN, by the
circuit noise gain. The noise gain is defined as:
R 
GN = 1 +  F  = 3
 RG 
The total output referred noise for the AD8131, including the
contributions of RF, RG, and op amp, is nominally 25 nV/√Hz
at 20 MHz.
Previous differential drivers, both discrete and integrated
designs, have been based on using two independent amplifiers,
and two independent feedback loops, one to control each of the
outputs. When these circuits are driven from a single-ended
source, the resulting outputs are typically not well balanced.
Achieving a balanced output has typically required exceptional
matching of the amplifiers and feedback networks.
Calculating an Application Circuit’s Input Impedance
The effective input impedance of a circuit such as that in Figure
37, at +DIN and –DIN, will depend on whether the amplifier is
being driven by a single-ended or differential signal source. For
balanced differential input signals, the input impedance (RIN,dm)
between the inputs (+DIN and –D IN) is simply:
DC common-mode level-shifting has also been difficult with
previous differential drivers. Level-shifting has required the use
of a third amplifier and feedback loop to control the output
common-mode level. Sometimes the third amplifier has also
been used to attempt to correct an inherently unbalanced
circuit. Excellent performance over a wide frequency range has
proven difficult with this approach.
REV. 0
=
R IN,dm = 2 × RG = 1.5 kΩ
In the case of a single-ended input signal (for example if –DIN is
grounded and the input signal is applied to +DIN), the input
impedance becomes:
–9–
AD8131
RIN ,dm


RG
= 
RF
1 −

2 × RG + RF

(
)
In this case, the input signal is provided by a signal generator
with an output impedance of 50 Ω. This is terminated with a
49.9 Ω resistor near +DIN of the AD8131. The effective parallel
resistance of the source and termination is 25 Ω. The 24.9 Ω
resistor from –DIN to ground matches the +DIN source impedance
and minimizes any dc and gain errors.


 = 1.125 kΩ




If +DIN is driven by a low-impedance source over a short distance, such as the output of an op amp, then no termination
resistor is required at +DIN. In this case, the –D IN can be
directly tied to ground.
The circuit’s input impedance is effectively higher than it would
be for a conventional op amp connected as an inverter because
a fraction of the differential output voltage appears at the inputs
as a common-mode signal, partially bootstrapping the voltage
across the input resistor RG.
+3 V Supply Differential A-to-D Driver
Input Common-Mode Voltage Range in Single Supply
Applications
The AD8131 is optimized for level-shifting “ground” referenced
input signals. For a single-ended input this would imply, for
example, that the voltage at –DIN in Figure 37 would be zero
volts when the amplifier’s negative power supply voltage (at V–)
was also set to zero volts.
Setting the Output Common-Mode Voltage
The AD8131’s V OCM pin is internally biased at a voltage
approximately equal to the midsupply point (average value of
the voltages on V+ and V–). Relying on this internal bias will
result in an output common-mode voltage that is within about
25 mV of the expected value.
In cases where more accurate control of the output commonmode level is required, it is recommended that an external
source, or resistor divider (made up of 10 kΩ resistors), be used.
Driving a Capacitive Load
A purely capacitive load can react with the pin and bondwire
inductance of the AD8131 resulting in high frequency ringing in
the pulse response. One way to minimize this effect is to place a
small resistor in series with the amplifier’s outputs as shown in
Figure 23.
APPLICATIONS
Twisted-Pair Line Driver
Many newer A-to-D converters can run from a single +3 V
supply, which can save significant system power. In order to
increase the dynamic range at the analog input, they have differential inputs, which doubles the dynamic range with respect to a
single-ended input. An added benefit of using a differential
input is that the distortion can be improved.
The low distortion and ability to run from a single +3 V supply
make the AD8131 suited as an A-to-D driver for some 10-bit,
single supply applications. Figure 39 shows a schematic for a
circuit for an AD8131 driving an AD9203, a 10-bit, 40 MSPS
A-to-D converter.
The common mode of the AD8131 output is set at midsupply
by the voltage divider connected to VOCM, and ac bypassed with
a 0.1 µF capacitor. This provides for maximum dynamic range
between the supplies at the output of the AD8131. The 110 Ω
resistors at the AD8131 output, along with the shunt capacitors
form a one pole, low-pass filter for lowering noise and antialiasing.
Figure 40 shows an FFT plot that was taken from the combined
devices at an analog input frequency of 2.5 MHz and a 40 MSPS
sampling rate. The performance of the AD8131 compares very
favorably with a center-tapped transformer drive, which has
typically been the best way to drive this A-to-D converter. The
AD8131 has the advantage of maintaining dc performance,
which a transformer solution cannot provide.
Unity-Gain, Single-Ended-to-Differential Driver
The AD8131 has on-chip resistors that provide for a gain-oftwo without any external parts. Several on-chip resistors are
trimmed to ensure that the gain is accurate, the common-mode
rejection is good, and the output is well balanced. This makes
the AD8131 very suitable as a single-ended-to-differential
twisted-pair line driver.
Figure 38 shows a circuit of an AD8131 driving a twisted-pair
line, like a Category 3 or Category 5 (Cat3 or Cat5), that are
already installed in many buildings for telephony and data communications. The characteristic impedance of such transmission
lines is usually about 100 Ω. The outstanding balance of the
AD8131 output will minimize the common-mode signal and therefore the amount of EMI generated by driving the twisted pair.
The two resistors in series with each output terminate the line at
the transmit end. Since the impedances of the outputs of the
AD8131 are very low, they can be thought of as a short circuit,
and the two terminating resistors form a 100 Ω termination at
the transmit end of the transmission line. The receive end is
directly terminated by a 100 Ω resistor across the line.
If it is not necessary to offset the output common-mode voltage (via the VOCM pin), then the AD8131 can make a simple
unity-gain single-ended-to-differential amplifier that does not
require any external components. Figure 41 shows the schematic
for this circuit.
Referring to Figure 2, when –DIN is left floating, there is 100
percent feedback of +OUT to –IN via the internal feedback
resistor. This contrasts with the typical gain-of-two operation
where –DIN is grounded and one third of the +OUT is fed back
to –IN. The result is a closed-loop differential gain of one.
Upon careful observation, it can be seen that only +DIN and
VOCM are referenced to ground. It is the case that the ground
voltage at VOCM is the reference for this circuit. In this unity
gain configuration, if a dc voltage is applied to VOCM to shift the
common-mode voltage, a differential dc voltage will be created
at the output, along with the common-mode voltage change.
Thus, this configuration cannot be used when it is desired to
offset the common-mode voltage of the output with respect to
the input at +DIN.
This back-termination of the transmission line divides the output signal by two. The fixed gain of two of the AD8131 will
create a net unity gain for the system from end to end.
–10–
REV. 0
AD8131
10
0
–10
+5V
–20
–30
10mF
POUT – dBm
+
0.1mF
49.9V
3
8
2
49.9V
24.9V
5
100V
AD8131
1
0.1mF
–100
–110
RECEIVER
+
–120
2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0
FREQUENCY – MHz
10mF
–5V
Figure 38. Single-Ended-to-Differential 100 Ω Line Driver
+
0.1mF
8
49.9V
2
0.1mF
1
+3V
10kV
24.9V
Figure 40. FFT Plot for AD8131/AD9203
3V
3V
LPF
+5V
+
10mF
28
26 AVDD
AINN
110V
0.1mF
0.1mF
AD8131
25
110V
8
AD9203
VOCM
20pF
DIGITAL
OUTPUTS
49.9V
2
1
AINP
AVSS
27
INPUT
10mF
2
DRVDD
20pF
6
–70
–90
49.9V
3
–50
–60
–80
4
6
–40
–OUT
3
5
VOCM
6
DRVSS
1
4
+OUT
+
0.1mF
10mF
–5V
10kV
Figure 41. Unity Gain, Single-Ended-to-Differential
Amplifier
Figure 39. Test Circuit for AD8131 Driving an AD9203,
10 Bit, 40 Msps A-to-D Converter
REV. 0
–11–
AD8131
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
C3724–2.5–10/99
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.1497 (3.80)
8
5
1
4
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.0196 (0.50)
3 458
0.0099 (0.25)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0040 (0.10)
88
0.0098 (0.25) 08 0.0500 (1.27)
0.0160 (0.41)
0.0075 (0.19)
0.0192 (0.49)
0.0138 (0.35)
SEATING
PLANE
8-Lead ␮SOIC
(RM-8)
0.122 (3.10)
0.114 (2.90)
8
5
0.122 (3.10)
0.114 (2.90)
0.199 (5.05)
0.187 (4.75)
1
4
PIN 1
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
SEATING 0.008 (0.20)
PLANE
0.011 (0.28)
0.003 (0.08)
338
278
0.028 (0.71)
0.016 (0.41)
PRINTED IN U.S.A.
0.006 (0.15)
0.002 (0.05)
0.043 (1.09)
0.037 (0.94)
–12–
REV. 0
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www.datasheetcatalog.com
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