DATASHEET
AC’97 2.3 CODECS WITH STEREO MICROPHONE
& UNIVERSAL JACK
FEATURES
•
•
High Performance SD Technology
•
AC’97 Rev 2.3 Complaint
DESCRIPTION
•
20-bit Full Duplex Stereo ADC & DACs
•
Independent Sample Rates for ADC & DACs
•
5-Wire AC-Link Protocol Compliance
•
20-Bit SPDIF Output
•
Universal Jacks™
•
Full Stereo Microphone Pre-Amp
•
Internal Jack Sensing on Headphone & Line_Out
•
Internal Microphone Input Sensing
•
Digital PC Beep Option
•
Extended AC’97 2.3 Paging Registers
•
General Purpose I/Os and Crystal Elimination
Circuit
•
Headphone Drive Capability (50 mW per channel)
•
Switchable Headphone Out (pins 39/41 or 35/36)
•
0dB, 10dB, 20dB and 30dB Microphone Boost
Capability
•
+3.3 V (STAC9753A) and +5 V (STAC9752A) Analog
Power Supply Options
•
Pin Compatible with STAC9750/52/66
Analog LINE_OUT SNR: 94dB
•
Digital DAC SNR: 92dB
•
Digital ADC SNR: 85dB
•
Full-scale Total Harmonic Distortion: 0.002%
•
Crosstalk Between Input Channels: -70dB
•
Spurious Tone Rejection: 100dB
•
Stereo Microphone Input
The AC’97 CODEC is designed to achieve a DAC SNR in
excess of 94dB. The DACs, ADCs, and mixer are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs,
two stereo outputs, and one mono output channel.
The STAC9752A/9753A includes digital input/output capability for support of modern PC systems, with an output that
supports the SPDIF format. The STAC9752A/9753A is a
standard 2-channel stereo CODEC. With TSI’s headphone
drive capability, headphones can be driven with without an
external amplifier.
The STAC9752A/9753A may be used as a secondary
CODEC, with the STAC9700/21/56/08/84/50/52 as the primary, in a multiple CODEC configuration conforming to the
AC'97 Rev. 2.3 specification. This configuration can provide
the true six-channel, AC-3 playback required for DVD applications.
The STAC9752A/9753A communicates via the five-wire
AC-Link to any digital component of AC'97, providing flexibility in the audio system design.
Packaged in an AC'97 compliant 48-pin TQFP, the
STAC9752A/9753A can be placed on a motherboard,
daughter boards, PCI, AMR, CNR, MDC or ACR cards.
The STAC9752A/9753A provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital (AD) conversion,
mixing, and analog processing.
Supported audio sample rates include 48 KHz, 44.1 KHz,
32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz; additional rates are supported in the STAC9752A/9753A soft
audio drivers. All ADCs and DACs operate at 20-bit resolu-
RELATED MATERIALS
•
Data Sheet
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
Reference Designs
TSI's STAC9752A/9753A are general purpose 20-bit, full
duplex, audio CODECs conforming to the analog component specification of AC'97 (Audio CODEC 97 Component
Specification Rev. 2.3). The STAC9752A/9753A incorporates TSI's proprietary SD technology.
KEY SPECIFICATIONS
•
STAC9752A/9753A
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STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
TABLE OF CONTENTS
PRODUCT BRIEF ......................................................................................................................... 6
Features ....................................................................................................................................................6
Description ................................................................................................................................................6
STAC9752A/9753A Block Diagram ..........................................................................................................8
Key Specifications ....................................................................................................................................8
Related Materials ......................................................................................................................................8
Additional Support ....................................................................................................................................9
CHARACTERISTICS AND SPECIFICATIONS ........................................................................... 10
Electrical Specifications ..........................................................................................................................10
Absolute Maximum Ratings .........................................................................................................10
Recommended Operation Conditions .........................................................................................10
Power Consumption ....................................................................................................................11
AC-Link Static Digital Specifications ............................................................................................11
STAC9752A Analog Performance Characteristics .......................................................................12
STAC9753A Analog Performance Characteristics .......................................................................13
AC Timing Characteristics ......................................................................................................................15
Cold Reset ...................................................................................................................................15
Warm Reset .................................................................................................................................15
Clocks ..........................................................................................................................................16
STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies ......................................16
Data Setup and Hold ...................................................................................................................17
Signal Rise and Fall Times ..........................................................................................................17
AC-Link Low Power Mode Timing ................................................................................................18
ATE Test Mode ............................................................................................................................18
TYPICAL CONNECTION AND POWER DIAGRAMS ................................................................. 20
STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP ........................................................20
STAC9752A/9753A Typical Connection Diagram for 32-pad QFN ........................................................21
Split Independent Power Supply Operation ............................................................................................22
Split Independent Power Supply Operation for the 32-pad QFP Package .............................................23
CONTROLLER, CODEC, AND AC-LINK .................................................................................... 24
AC-Link Physical interface ......................................................................................................................24
Controller to Single CODEC ...................................................................................................................24
Controller to Multiple CODECs ...............................................................................................................25
Primary CODEC Addressing ........................................................................................................25
Secondary CODEC Addressing ...................................................................................................26
CODEC ID Strapping .....................................................................................................................6
Clocking for Multiple CODEC Implementations ......................................................................................26
STAC9752A/9753A as a Primary CODEC .............................................................................................26
STAC9752A/9753A as a Secondary CODEC ..............................................................................27
AC-Link Power Management ..................................................................................................................27
Powering down the AC-Link .........................................................................................................27
Waking up the AC-Link ................................................................................................................27
Controller Initiates Wake-up ..........................................................................................28
CODEC Initiates Wake-up .............................................................................................28
CODEC Reset ..............................................................................................................................28
Cold AC‘97 Reset ..........................................................................................................28
Warm AC‘97 Reset ........................................................................................................28
Register AC‘97 Reset ....................................................................................................29
AC-LINK DIGITAL INTERFACE ................................................................................................. 30
Overview .................................................................................................................................................30
AC-Link Serial Interface Protocol ............................................................................................................31
AC-Link Variable Sample Rate Operation ...................................................................................31
Variable Sample Rate Signaling Protocol ....................................................................................31
SLOTREQ Behavior and Power Management ..............................................................32
Primary and Secondary CODEC Register Addressing ................................................................33
AC-Link Output Frame (SDATA_OUT) ...................................................................................................33
Slot 0: TAG / CODEC ID ..............................................................................................................35
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Slot 1: Command Address Port ...................................................................................................35
Slot 2: Command Data Port .........................................................................................................36
Slot 3: PCM Playback Left Channel .............................................................................................36
Slot 4: PCM Playback Right Channel ..........................................................................................36
Slot 5: NOT USED (Modem Line 1 Output Channel) ...................................................................36
Slot 6 -11: DAC ............................................................................................................................37
Slot 12: Audio GPIO Control Channel ..........................................................................................37
AC-Link Input Frame (SDATA_IN) ..........................................................................................................37
Slot 0: TAG ..................................................................................................................................38
Slot 1: Status Address Port / SLOTREQ Signaling Bits ...............................................................38
Status Address Port .......................................................................................................38
SLOTREQ signaling bits ................................................................................................38
Slot 2: Status Data Port ...............................................................................................................39
Slot 3: PCM Record Left Channel ................................................................................................39
Slot 4: PCM Record Right Channel .............................................................................................39
Slot 5: NOT USED (Modem Line 1 ADC) .....................................................................................39
Slot 6-9: ADC ...............................................................................................................................39
Slots 7-8: Vendor Reserved .........................................................................................................40
Slot 10 & 11: ADC ........................................................................................................................40
Slot 12: Reserved ........................................................................................................................40
AC-Link Interoperability Requirements and Recommendations .............................................................40
“Atomic slot” Treatment of Slot 1 Address and Slot 2 Data ..........................................................40
Slot Assignments for Audio .....................................................................................................................41
STAC9752A/9753A FUNCTIONAL BLOCKS ............................................................................ 43
STAC9752A/9753A Mixer Description ....................................................................................................43
Mixer Functional Diagrams .........................................................................................................44
Mixer Analog Input .......................................................................................................................44
Mixer Analog Output ....................................................................................................................44
SPDIF Digital Mux ..................................................................................................................................44
PC Beep Implementation ........................................................................................................................45
Analog PC Beep ..........................................................................................................................45
Digital PC Beep ............................................................................................................................45
PROGRAMMING REGISTERS ................................................................................................... 46
Register Descriptions ..............................................................................................................................47
Reset (00h) ..................................................................................................................................47
Master Volume Registers (02h) ...................................................................................................47
Headphone Volume Registers (04h) ............................................................................................48
Master Volume MONO (06h) .......................................................................................................49
PC BEEP Volume (0Ah) ..............................................................................................................49
Phone Volume (Index 0Ch) ..........................................................................................................50
Stereo or Mic Volume (Index 0Eh) ...............................................................................................50
LineIn Volume (Index 10h) ...........................................................................................................51
CD Volume (Index 12h) ...............................................................................................................52
Video Volume (Index 14h) ..........................................................................................................52
Aux Volume (Index 16h) ..............................................................................................................53
PCMOut Volume (Index 18h) .......................................................................................................53
Record Select (1Ah) .....................................................................................................................54
Record Gain (1Ch) .......................................................................................................................55
General Purpose (20h) ................................................................................................................55
3D Control (22h) ..........................................................................................................................56
Audio Interrupt and Paging (24h) .................................................................................................56
Powerdown Ctrl/Stat (26h) ...........................................................................................................57
Ready Status .................................................................................................................58
Powerdown Controls .....................................................................................................58
External Amplifier Power Down Control Output .............................................................58
Extended Audio ID (28h) ..............................................................................................................59
Extended Audio Control/Status (2Ah) ..........................................................................................60
Variable Rate Sampling Enable .....................................................................................61
SPDIF ............................................................................................................................61
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
SPCV (SPDIF Configuration Valid) ...............................................................................61
SPSA1, SPSA0 (SPDIF Slot Assignment) ....................................................................61
PCM DAC Rate Registers (2Ch and 32h) ....................................................................................62
PCM DAC Rate (2Ch) ..................................................................................................................62
PCM LR ADC Rate (32h) .............................................................................................................62
SPDIF Control (3Ah) ....................................................................................................................63
General Purpose Input & Outputs ...........................................................................................................63
EAPD ...........................................................................................................................................63
GPIO Pin Definitions ....................................................................................................................64
GPIO Pin Implementation ............................................................................................................64
Extended Modem Status and Control Register (3Eh) ..................................................................64
GPIO Pin Configuration Register (4Ch) .......................................................................................65
GPIO Pin Polarity/Type Register (4Eh) ........................................................................................65
GPIO Pin Sticky Register (50h) ...................................................................................................65
GPIO Pin Mask Register (52h) ....................................................................................................66
GPIO Pin Status Register (54h) ...................................................................................................66
Extended CODEC Registers Page Structure Definition ..........................................................................66
Extended Registers Page 00 .......................................................................................................67
Extended Registers Page 01 .......................................................................................................67
Extended Registers Page 02, 03 .................................................................................................67
STAC9752A/9753A Paging Registers ....................................................................................................67
CODEC Class/Rev (60h Page 01h) ...........................................................................................67
PCI SVID (62h Page 01h) ..........................................................................................................68
PCI SSID (64h Page 01h) ..........................................................................................................68
Function Select (66h Page 01h) ................................................................................................69
Function Information (68h Page 01h) ........................................................................................70
Digital Audio Control (6Ah, Page 00h) .........................................................................................72
Sense Details (6Ah Page 01h)................................................................................................... 72
Revision Code (6Ch) ....................................................................................................................74
Analog Special (6Eh) ...................................................................................................................74
Analog Current Adjust (72h) ........................................................................................................75
EAPD Access Register (74h) ....................................................................................................... 76
Register 78h Enable (76h) ...........................................................................................................77
Universal Jacks™ Selection (78h) ...............................................................................................77
Vendor ID1 and ID2 (Index 7Ch and 7Eh) ..............................................................................................78
Vendor ID1 (7Ch) .........................................................................................................................78
Vendor ID2 (7Eh) .........................................................................................................................78
LOW POWER MODES ................................................................................................................ 79
MULTIPLE CODEC SUPPORT ................................................................................................... 81
Primary/Secondary CODEC Selection ....................................................................................................81
Primary CODEC Operation ..........................................................................................................81
Secondary CODEC Operation .....................................................................................................81
Secondary CODEC Register Access Definitions ....................................................................................81
TESTABILITY .............................................................................................................................. 83
ATE Test Mode .......................................................................................................................................83
STAC9752A/9753A PIN DESCRIPTION .................................................................................... 84
Pin Description for the 48-pin LQFP Package ........................................................................................84
Pinout List 48-pin LQFP Package ..........................................................................................................85
Pin Description for the 32-pad QFN Package .........................................................................................86
Pinout List 32-pad QFN Package ..........................................................................................................87
STAC9752A/9753A Digital I/O ................................................................................................................87
STAC9752A/9753A Analog I/O ..............................................................................................................88
STAC9752A/9753A Filter/References ....................................................................................................89
STAC9752A/9753A Power and Ground Signals .....................................................................................89
STAC9752A/9753A No Connects ...........................................................................................................89
ORDERING INFORMATION ....................................................................................................... 90
PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION ....................................... 91
48-Pin LQFP ...........................................................................................................................................91
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
32-Pad QFN ............................................................................................................................................92
PC Board Recommendations for 32-pad QFN Package 93
SOLDER REFLOW PROFILE ..................................................................................................... 94
Standard Reflow Profile Data .................................................................................................................94
Pb Free Process - Package Classification Reflow Temperatures .........................................................94
APPENDIX A: PROGRAMMING REGISTERS ........................................................................... 96
REVISION HISTORY ................................................................................................................... 98
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
LIST OF FIGURES
STAC9752A/9753A Block Diagram ..............................................................................................................10
Cold Reset Timing .........................................................................................................................................17
Warm Reset Timing .......................................................................................................................................17
Clocks Timing ................................................................................................................................................18
Data Setup and Hold Timing ........................................................................................................................19
Signal Rise and Fall Times Timing ...............................................................................................................20
AC-Link Low Power Mode Timing ..................................................................................................................20
ATE Test Mode Timing ..................................................................................................................................20
STAC9752A/9753A Typical Connection Diagram 48-pin LQFP ...................................................................22
STAC9752A/9753A Typical Connection Diagram 32-pad QFN ...................................................................23
Split Connection Diagram 32-pad QFN .........................................................................................................25
AC-Link to its Companion Controller .............................................................................................................26
STAC9752A/9753A Powerdown Timing .......................................................................................................29
Bi-directional AC-Link Frame with Slot assignments .................................................................................... 32
AC-Link Audio Output Frame ........................................................................................................................35
Start of an Audio Output Frame ....................................................................................................................36
STAC9752A/9753A Audio Input Frame ........................................................................................................39
Start of an Audio Input Frame .......................................................................................................................39
Bi-directional AC-Link Frame with Slot assignments .....................................................................................43
AC-Link Input Slots Dedicated To CODEC ....................................................................................................44
STAC9752A/9753A 2-Channel Mixer Functional Diagram ...........................................................................46
Example of STAC9752A/9753A Powerdown/Powerup Flow ........................................................................81
Powerdown/Powerup Flow With Analog Still Alive .......................................................................................82
Pin Description Drawing ................................................................................................................................86
STAC9752A/9753A 32 pad QFN Pin Description Drawing ...........................................................................88
Package Drawing - 48-pin LQFP ...................................................................................................................93
Package Drawing - 32-pad QFN ....................................................................................................................94
Recommended PCB Layout for 32-pad QFN Package ..................................................................................95
Reflow Profile ................................................................................................................................................96
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STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
LIST OF TABLES
Table 1. Clock mode configuration .................................................................................................................18
Table 2. Common Clocks and Sources ..........................................................................................................19
Table 3. Recommended CODEC ID strapping ..............................................................................................28
Table 4. AC-Link Output Slots (transmitted from the Controller) ....................................................................32
Table 5. The AC-Link Input Slots (transmitted from the CODEC) ..................................................................33
Table 6. VRA Behavior ..................................................................................................................................34
Table 7. Output Slot 0 Bit Definitions .............................................................................................................37
Table 8. Command Address Port Bit Assignments ........................................................................................38
Table 9. Status Address Port Bit Assignments ..............................................................................................40
Table 10. Status Data Port Bit Assignments ..................................................................................................41
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits ................................................................................42
Table 12. Secondary CODEC Addressing: Slot 0 tag bits .............................................................................43
Table 13. AC-Link Output Slots Dedicated To CODEC .................................................................................43
Table 14. AC-Link Output Slots Dedicated To Audio .....................................................................................44
Table 15. AC-Link Input Slots Dedicated To Audio ........................................................................................44
Table 16. Audio Interrupt Slot Definitions .......................................................................................................44
Table 17. Digital PC Beep Examples .............................................................................................................47
Table 18. Programming Registers .................................................................................................................48
Table 19. Extended Audio ID Register Functions ..........................................................................................61
Table 20. AMAP compliant ............................................................................................................................63
Table 21. Hardware Supported Sample Rates ..............................................................................................64
Table 22. Supported Jack and Mic Sense Functions .....................................................................................72
Table 23. Reg 68h Default Values .................................................................................................................73
Table 24. Gain or Attenuation Examples .......................................................................................................73
Table 25. Register 68h/Page 01h Bit Overview .............................................................................................74
Table 26. Sensed Bits (Outputs) ....................................................................................................................75
Table 27. Sensed Bits (Inputs) .......................................................................................................................76
Table 28. Low Power Modes .........................................................................................................................81
Table 29. CODEC ID Selection ......................................................................................................................83
Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions ............................................................84
Table 31. Test Mode Activation .....................................................................................................................85
Table 32. ATE Test Mode Operation .............................................................................................................85
Table 33. STAC9752A/9753A 48 Pin LQFP Pin List .....................................................................................87
Table 34. STAC9752A/9753A 32 Pad QFN Pin List ......................................................................................89
Table 35. STAC9752A/9753A Digital Connection Signals .............................................................................89
Table 36. STAC9752A/9753A Analog Connection Signals ............................................................................90
Table 37. STAC9752A/9753A Filtering and Voltage References ..................................................................91
Table 38. STAC9752A/9753A Power and Ground Signals ............................................................................91
Table 39. STAC9752A/9753A No Connects ..................................................................................................91
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STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
1. PRODUCT BRIEF
1.1.
1.2.
Features
•
High performance SD technology
•
AC’97 Rev 2.3 Complaint, 20-bit, full duplex stereo ADCs & DACs
•
Independent sample rates for ADCs & DACs
•
5-Wire AC-Link protocol compliance
•
20-Bit SPDIF Output
•
Universal Jacks™
•
Full Stereo Microphone Pre-Amp
•
Internal Jack Sensing on Headphone & Line_Out
•
Internal Microphone Input Sensing
•
Digital PC Beep Option
•
Extended AC’97 2.3 Paging Registers
•
Digital-ready status
•
General purpose I/Os
•
Crystal Elimination Circuit
•
Headphone drive capability (50 mW per channel)
•
Switchable Headphone Out (pins 39/41 or 35/36)
•
0, 10db, 20db, and 30 dB microphone boost capability
•
+3.3 V (STAC9753A) and +5 V (STAC9752A) analog power supply options
•
Pin compatible with STAC9700/21/56
•
100% compatible with STAC9750/52/66
•
TSI Surround (SS3D) Stereo Enhancement
•
Energy saving dynamic power modes
•
Multi-CODEC option (Intel AC'97 rev 2.3)
•
94dB SNR LINE-LINE
Description
TSI's STAC9752A/9753A are general purpose 20-bit, full duplex, audio CODECs conforming to the
analog component specification of AC'97 (Audio Codec 97 Component Specification Rev. 2.3). The
STAC9752A/9753A incorporates TSI's proprietary SD technology to achieve a DAC SNR in excess
of 92dB. The DACs, ADCs and mixer are integrated with analog I/Os, which include four analog
line-level stereo inputs, two analog line-level mono inputs, two stereo outputs, and one mono output
channel.
The STAC9752A/9753A include digital output capability for support of modern PC systems with an
output that supports the SPDIF format.
The STAC9752A/9753A are standard 2-channel stereo CODEC. With TSI’s headphone drive capability, headphones can be driven without an external amplifier.
The STAC9700/21/44/56/08/84/50/66 may be used as a secondary or tertiary CODEC, with the
STAC9752A/9753A as the primary, in a multiple CODEC configuration conforming to the AC'97 Rev.
2.3 specification. This configuration can provide the true six-channel, AC-3 playback required for
DVD applications.
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STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
The STAC9752A/9753A communicates via the five wire AC-Link to any digital component of AC'97,
providing flexibility in the audio system design.
Packaged in an AC'97 compliant 48-pin LQFP or in the 32-pad/pin QFN, the STAC9752A/9753A can
be placed on motherboards, daughter boards, PCI, AMR, CNR, MDC or ACR cards.
The STAC9752A/9753A block diagram is illustrated in Figure 1.
The STAC9752A/9753A provides variable sample rate Digital-to-Analog (DA) and Analog-to-Digital
(AD) conversion, mixing, and analog processing. Supported audio sample rates include 48 KHz,
44.1 KHz, 32 KHz, 22.05 KHz, 16 KHz, 11.025 KHz, and 8 KHz; additional rates are supported in the
STAC9752A/9753A soft audio drivers All ADC's and DAC's operate at 20-bit resolution.
Two 20-Bit DACs convert the digital stereo PCM_OUT content to audio. The MIXER block combines
the PCM_OUT with any analog sources to drive the LINE_OUT and HP_OUT outputs. The
MONO_OUT delivers either mic only, or a mono mix of sources from the MIXER. The stereo, variable-sample-rate, 20-bit ADCs provide record capability for any mix of mono or stereo sources, and
deliver a digital stereo PCM-in signal back to the AC-Link. The microphone input in mono mode and
the mono mix input can be recorded simultaneously, thus allowing for an all digital output in support
of the digital-ready initiative. For a digital-ready record path, the microphone is connected to the left
channel ADC while the mono output of the stereo mixer is connected to right channel ADC.
The STAC9752A/9753A includes full Stereo Microphone Pre-Amp support and can be used with the
10, 20 and 30dB Microphone Boost options. This integration allows for additional cost savings and
options.
The STAC9752A/9753A also includes TSI’s Universal Jacks™ functionality for jack interchangeability. The STAC9752A/9753A includes internal jack sensing using proprietary current- and impedance-sensing techniques. The impedance load on any of the inputs or outputs, including the
Headphone and Line Outputs, can be detected. This enables jack sensing on the Headphone and
Line_Out. The STAC9752A/9753A jack sense can detect the presence of devices on the Headphone and Line Outputs and on both Mic inputs.
The STAC9752A/9753A implementation of jack sense uses the Extended Paging Registers defined
by the AC'97 2.3 Specification. This allows for additional registry space to hold the identification
information about the CODEC, the jack sensing details and results, and the external surroundings of
the CODEC. The information within the Extended Paging Registers will allow for the automatic configuration of the audio subsystem without end-user intervention. For example, the BIOS can populate the Extended Paging Registers with valuable information for both the audio driver and the
operating system such as gain and attenuation stages, input population and input phase. With this
input information, the TSI driver will automatically provide to the Volume Control Panel only the volume sliders that are implemented in the system, thus improving the end-user's experience with the
PC.
The information in the Extended Paging Registers will also allow for automatic configuration of
microphone inputs, the ability to switch between SPDIF and analog outputs, the routing of the master volume slider to the proper physical output, and SoftEQ configurations. The fully parametric TSI
SoftEQ can be initiated upon jack insertion and sensed impedance levels.
The STAC9752A/9753A also offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP
is a new feature added to the AC’97 Specification Rev 2.3.
The STAC9752A/9753A is designed primarily to support stereo (2-speaker) audio. True AC-3 playback can be achieved for 6-speaker applications by taking advantage of the multi-CODEC option
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
available in the AC'97 architecture and supported by the STAC9752A/9753A. Additionally, the
STAC9752A/9753A provides for a stereo enhancement feature, TSI Surround 3D (SS3D). SS3D
provides the listener with several options for improved speaker separation beyond the normal 2- or
4-speaker arrangements.
The STAC9752A/9753A can be SoundBlaster® and Windows Sound System® compatible when
used with TSI’s WDM driver for Windows 98/2K/ME/XP or with Intel/Microsoft driver included with
Windows 2K/ME/XP.
SoundBlaster is a registered trademark of Creative Labs.
Windows is a registered trademark of Microsoft Corporation.
1.3.
STAC9752A/9753A Block Diagram
Figure 1. STAC9752A/9753A Block Diagram
Video
Registers
64x16 bits
ADC
MIXER
ADC
Mic
Sensing
Line In
DAC
Analog mixing
and Gain Control
Universal JacksTM
Jack Sharing
Internal Jack Sense
Left or Right
Channel Stereo
or Mono Mic
M
U
X
Left or Right
Channel Stereo
or Mono Mic
HP_OUT
LINE_OUT
MONO_OUT
PCM in ADCs
Variable Sample Rate
20-Bit DACs and
20-Bit ADCs
1.5.
CD
DAC
Digital
Interface
CID0
CID1
1.4.
AUX
Multi-Codec
Mic Boost
0,10, 20, or
30 dB
PCM out DACs
AC-link
SYNC
BIT_CLK
SDATA_OUT
SDATA_IN
RESET#
PHONE
PC_BEEP
Power
Management
M
U
X
Digital PCBEEP
Stereo
Mono
SPDIF Output
Key Specifications
•
Analog LINE_OUT SNR: 94 dB
•
Digital DAC SNR: 92 dB
•
Digital ADC SNR: 85 dB
•
Full-scale Total Harmonic Distortion: 0.002%
•
Crosstalk between Input Channels: -70 dB
•
Spurious Tone Rejection: 100 dB
•
Stereo Microphone Input
Related Materials
•
Product Brief
•
Reference Designs for MB, AMR, CNR, and ACR applications
•
Audio Precision Performance Plots
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
1.6.
Additional Support
Additional product and company information can be obtained by going to the
TSI web site at: www.TSI.com
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
2. CHARACTERISTICS AND SPECIFICATIONS
2.1.
Electrical Specifications
2.1.1.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the STAC9752A/9753A. These ratings,
which are standard values for TSI commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the specifications is not
implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability.
Electrical parameters are guaranteed only over the recommended operating temperature range.
Item
Pin
Maximum Rating
Analog maximum supply voltage
AVdd
6 Volts
Digital maximum supply voltage
DVdd
5.5 Volts
VREFOUT output current
±5 mA
Voltage on any pin relative to ground
Vss - 0.3 V to Vdd + 0.3 V
Operating temperature
0oC to +70oC
Storage temperature
-55 oC to +125 oC
Soldering temperature
260 oC for 10 seconds *
Soldering temperature information for all available packages
begins on page 96.
2.1.2.
Recommended Operation Conditions
Parameter
Power Supply Voltage
Min.
Typ.
Max.
Units
Digital - 3.3 V
3.135
3.3
3.465
V
Analog - 5 V
4.75
5
5.25
V
Analog - 3.3 V
3.135
3.3
3.465
V
+70
C
+90
C
Ambient Operating Temperature
Case Temperature
0
Tcase (48-LQFP)
ESD: The STAC9752A/9753A is an ESD (electrostatic discharge) sensitive device. The human body and test
equipment can accumulate and discharge electrostatic charges up to 4000 Volts without detection. Even though the
STAC9752A/9753A implements internal ESD protection circuitry, proper ESD precautions should be followed to
avoid damaging the functionality or performance.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
2.1.3.
Power Consumption
Parameter
Min
Typ
Max
Unit
-
35
-
mA
+ 5 V Analog
-
80
-
mA
+ 3.3 V Analog
-
70
-
mA
PR0 Supply Current
-
TBD
-
mA
PR1 Supply Current
-
TBD
-
mA
PR2 Supply Current
-
TBD
-
mA
PR3 Supply Current
-
TBD
-
mA
PR4 Supply Current
-
TBD
-
mA
PR5 Supply Current
-
TBD
-
mA
PR6 Supply Current
-
TBD
-
mA
Digital Supply Current
+ 3.3 V Digital
Analog Supply Current
Power Down Status
2.1.4.
AC-Link Static Digital Specifications
(Tambient = 25 ºC, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 50 pF external load)
Parameter
Symbol
Min
Typ
Max
Unit
Input Voltage Range
Vin
-0.30
-
DVdd + 0.30
V
Low level input range
Vil
-
-
0.35 x DVdd
V
High level input voltage
Vih
0.65 x DVdd
-
-
V
High level output voltage
Voh
0.90 x DVdd
-
-
V
Low level output voltage
Vol
-
-
0.1 x DVdd
V
Input Leakage Current (AC-Link inputs)
-
-10
-
10
A
Output Leakage Current (Hi-Z AC-Link outputs)
-
-10
-
10
A
Output buffer drive current
-
-
4
-
mA
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
2.1.5.
STAC9752A Analog Performance Characteristics
(Tambient = 25 ºC, AVdd = 5.0 V ± 5%, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 1 KHz input sine wave;
Sample Frequency = 48 KHz; 0dB = 1 Vrms, 10 KW / 50 pF load, Testbench Characterization BW: 20 Hz – 20 KHz,
0dB settings on all gain stages)
Parameter
Min
Typ
Max
Unit
-
1.0
0.03
-
Vrms
Vrms
-
-
-
1.0
1.0
1.0
50
-
Vrms
Vrms
Vrms
mW
20
94
94
92
85
-
20,000
dB
dB
dB
dB
Hz
84
74
20
19,200
28,800
100
55
70
-
95
95
84
80
-
19,200
28,800
1
0.5
0.5
dB
dB
dB
dB
dB
Hz
Hz
Hz
dB
dB
ms
dB
dB
dB
dB
K
pF
V
dB
dB
Full Scale Input Voltage:
All Analog Inputs except Mic
Mic Inputs (Note 1)
Full Scale Output:
Line Output
PCM (DAC) to LINE_OUT
MONO_OUT
HEADPHONE_OUT (32 load) (peak)
Analog S/N: (Note 2)
CD to LINE_OUT
Other to LINE_OUT
D/A to LINE_OUT
LINE_IN to A/D with High pass filter enabled
Analog Frequency Response (Note 3)
Total Harmonic Distortion: (Note 4)
CD to LINE_OUT
Other to LINE_OUT
D/A to LINE_OUT (full scale)
LINE_IN to A/D with High pass filter enabled
HEADPHONE_OUT
A/D & D/A Digital Filter Pass Band (Note 5)
A/D & D/A Digital Filter Transition Band
A/D & D/A Digital Filter Stop Band
A/D & D/A Digital Filter Stop Band Rejection (Note 6)
DAC Out-of-Band Rejection (Note 7)
Group Delay (48 KHz sample rate)
Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency)
Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency)
Spurious Tone Rejection
Attenuation, Gain Step Size
Input Impedance (Note 8)
Input Capacitance
VREFout
Interchannel Gain Mismatch ADC
Interchannel Gain Mismatch DAC
Note:
1.
2.
3.
4.
5.
6.
7.
8.
100
100
1.5
50
15
0.5 x AVdd
-
With +30 dB Boost on, 1.0 Vrms with Boost off
Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).
± 1dB limits for Line Output & 0dB gain
Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a 20 KHz BW, 48 KHz Sample
Frequency
± 0.25dB limits
Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth
28.8 to 100 KHz, with respect to a 1 Vrms DAC output.
For all inputs except PC BEEP.
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2.1.6.
STAC9753A Analog Performance Characteristics
(Tambient = 25 ºC, AVdd = 5.0 V ± 5%, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 1 KHz input sine wave;
Sample Frequency = 48 KHz; 0dB = 1 Vrms, 10 KW / 50 pF load, Testbench Characterization BW: 20 Hz – 20 KHz,
0dB settings on all gain stages)
Parameter
Min
Typ
Max
Unit
All Analog Inputs except Mic
-
1.0
-
Vrms
Mic Inputs (Note 1)
-
0.03
-
Vrms
-
0.5
-
Vrms
Full Scale Input Voltage:
Full Scale Output:
Line Output
PCM (DAC) to LINE_OUT
0.5
Vrms
MONO_OUT
-
0.5
-
Vrms
HEADPHONE_OUT (32 load) (peak)
-
12.5
-
mW
CD to LINE_OUT
-
93
-
dB
Other to LINE_OUT
-
93
-
dB
D/A to LINE_OUT
-
91
-
dB
LINE_IN to A/D with High pass filter enabled
-
85
-
dB
20
-
20,000
Hz
CD to LINE_OUT
-
93
-
dB
Other to LINE_OUT
-
93
-
dB
D/A to LINE_OUT (full scale)
-
84
-
dB
LINE_IN to A/D with High pass filter enabled
-
84
-
dB
74
80
-
dB
20
-
19,200
Hz
A/D & D/A Digital Filter Transition Band
19,200
-
28,800
Hz
A/D & D/A Digital Filter Stop Band
28,800
-
-
Hz
A/D & D/A Digital Filter Stop Band Rejection (Note 6)
100
-
-
dB
DAC Out-of-Band Rejection (Note 7)
55
-
-
dB
-
-
1
ms
Any Analog Input to LINE_OUT Crosstalk (10 KHz Signal Frequency)
70
-
-
dB
Any Analog Input to LINE_OUT Crosstalk (1 KHz Signal Frequency)
-
100
-
dB
Spurious Tone Rejection
-
100
-
dB
Attenuation, Gain Step Size
-
1.5
-
dB
Input Impedance (Note 8)
-
50
-
K
Input Capacitance
-
15
-
pF
VREFout
-
0.5 x AVdd
-
V
Interchannel Gain Mismatch ADC
-
-
0.5
dB
Interchannel Gain Mismatch DAC
-
-
0.5
dB
Gain Drift
-
100
-
ppm/ºC
Analog S/N: (Note 2)
Analog Frequency Response (Note 3)
Total Harmonic Distortion: (Note 4)
HEADPHONE_OUT
A/D & D/A Digital Filter Pass Band (Note 5)
Group Delay (48 KHz sample rate)
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Note:
1.
2.
3.
4.
5.
6.
7.
8.
With +30 dB Boost on, 1.0Vrms with Boost off
Ratio of Full Scale signal to idle channel noise output is measured “A weighted” over a 20 Hz to a 20 KHz bandwidth.
(AES17-1991 Idle Channel Noise or EIAJ CP-307 Signal-to-noise Ratio).0 dB gain, 20 KHz BW, 48 KHz Sample
Frequency± 1 dB limits
± 1dB limits for Line Output & 0 dB gain
Ratio of Full Scale signal to THD+N output with -3dB signal, measured “A weighted” over a,20 KHz BW, 48 KHz Sample
Frequency
± 0.25dB limits
Stop Band rejection determines filter requirements. Out-of-Band rejection determines audible noise.
The integrated Out-of-Band noise generated by the DAC process, during normal PCM audio playback, over a bandwidth
28.8 to 100 KHz, with respect to a 1 Vrms DAC output.
For all inputs except PC BEEP.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
2.2.
AC Timing Characteristics
(Tambient = 25 °C, AVdd = 3.3 V or 5 V ± 5%, DVdd = 3.3 V ± 5%, AVss = DVss = 0 V; 75 pF external
load for BIT_CLK and 60 pF external load for SDATA_IN)
2.2.1.
Cold Reset
Figure 2. Cold Reset Timing
Trst2clk
Tres_low
RESET#
Ttri2actv
BIT_CLK
Ttri2actv
SDATA_IN
Parameter
Symbol
Min
Typ
Max
Units
RESET# active low pulse width
Tres_low
1.0
-
-
s
RESET# inactive to SDATA_IN or BIT_CLK active delay
Tri2actv
-
-
25
ns
RESET# inactive to BIT_CLK startup delay
Trst2clk
.01628
-
400
s
BIT_CLK active to RESET# asserted (Not shown in diagram)
Tclk2rst
0.416
-
-
s
Note: BIT_CLK and SDATA_IN are in a high impedance state during reset.
2.2.2.
Warm Reset
Figure 3. Warm Reset Timing
Tsync_high
Tsync_2clk
SYNC
BIT_CLK
Parameter
SYNC active high pulse width
SYNC inactive to BIT_CLK startup delay
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Symbol
Min
Typ
Max
Units
Tsync_high
1.0
1.3
-
s
Tsync2clk
162.8
-
-
ns
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
2.2.3.
Clocks
Figure 4. Clocks Timing
T clk_low
B IT _C LK
T clk_high
T clk_period
T sync_low
T sync_high
SYNC
T sync_period
Parameter
Symbol
BIT_CLK frequency
BIT_CLK period
Tclk_period
BIT_CLK output jitter
Min
Typ
Max
Units
-
12.288
-
MHz
-
81.4
-
ns
-
750
-
ps
BLT_CLK high pulse width (Note 1)
Tclk_high
36
40.7
45
ns
BIT_CLK low pulse width (Note 1)
Tclk_low
36
40.7
45
ns
-
48.0
-
KHz
Tsync_period
-
20.8
-
s
SYNC high pulse width
Tsync_high
-
1.3
-
s
SYNC low pulse width
Tsync_low
-
19.5
-
s
SYNC frequency
SYNC period
Note:
2.2.4.
1.
Worst case duty cycle restricted to 45/55.
STAC9752A/9753A Crystal Elimination Circuit and Clock Frequencies
The STAC9752A/9753A supports several clock frequency inputs as described in the following table.
In general, when a 24.576 MHz crystal is not used, the XTALOUT pin should be tied to ground. This
short to ground configures the part into an alternate clock mode and enables an on board PLL.
CODEC Modes:
P = The STAC9752A/9753A as a Primary CODEC
S = The STAC9752A/9753A as a Secondary CODEC.
Table 1. Clock mode configuration
XTL_OUT Pin Config
CID1 Pin Config
CID0 pin config
Clock Source Input
CODEC Mode
CODEC
ID
XTAL
float
float
24.576 MHz xtal
P
0
XTAL or open
float
pulldown
12.288 MHz bit clk
S
1
XTAL or open
pulldown
float
12.288 MHz bit clk
S
2
XTAL or open
pulldown
pulldown
12.288 MHz bit clk
S
3
short to ground
float
float
14.31818 MHz source
P
0
short to ground
float
pulldown
27 MHz source
P
0
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Table 1. Clock mode configuration
XTL_OUT Pin Config
CID1 Pin Config
CID0 pin config
Clock Source Input
CODEC Mode
CODEC
ID
short to ground
pulldown
float
48 MHz source
P
0
short to ground
pulldown
pulldown
24.576 MHz source
P
0
Table 2. Common Clocks and Sources
2.2.5.
Clock Source
Clock Frequency
XTAL
24.576 MHz
BIT_CLK
12.288 MHz
VGA
14.31818 MHz
Digital Video
27 MHz
USB
48 MHz
Data Setup and Hold
(50pF external load)
Figure 5. Data Setup and Hold Timing
tco
B IT _ C L K
T s etup
V ih
V il
SDATA_O UT
S D A T A _ IN
SYNC
V oh
V ol
T hold
Parameter
Symbol
Min
Typ
Max
Units
Setup to falling edge of BIT_CLK
Tsetup
10
-
-
ns
Hold from falling edge of BIT_CLK
Thold
10
-
-
ns
tco
-
-
15
ns
Output Valid Data from rising edge of BIT_CLK
Note:
2.2.6.
Setup and hold time parameters for SDATA_IN are with respect to the AC'97 controller.
Signal Rise and Fall Times
(BIT_CLK: 75pF external load; from 10% to 90% of Vdd)
(SDATA_IN: 60pF external load; from 10% to 90% of Vdd)
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Figure 6. Signal Rise and Fall Times Timing
B IT _C LK
T riseclk
T fallclk
T risedin
T falldin
S D A T A _IN
Parameter
Symbol
Min
Typ
Max
Units
BIT_CLK rise time
Triseclk
-
-
6
ns
BIT_CLK fall time
Tfallclk
-
-
6
ns
SDATA_IN rise time
Trisedin
-
-
6
ns
SDATA_IN fall time
Tfalldin
-
-
6
ns
2.2.7.
AC-Link Low Power Mode Timing
Figure 7. AC-Link Low Power Mode Timing
SYNC
Slot 1
Slot 2
W rite to
0x20
Data PR4
BIT_CLK
SDATA_O UT
Don't care
Ts2_pdown
SDATA_IN
Note: BIT_CLK not to scale
Parameter
End of Slot 2 to BIT_CLK, SDATA_IN low
2.2.8.
Symbol
Min
Typ
Max
Units
Ts2_pdown
-
-
1.0
s
Typ
Max
Units
ATE Test Mode
Figure 8. ATE Test Mode Timing
RESET#
SDATA_OUT
Tsetup2rst
Hi-Z
SDATA_IN, BIT_CLK
Toff
Parameter
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Setup to trailing edge of RESET# (also applies to SYNC)
Rising edge of RESET# to Hi-Z delay
Note:
1.
2.
3.
Tsetup2rst
15.0
-
-
ns
Toff
-
-
25.0
ns
All AC-Link signals are normally low through the trailing edge of RESET#. Bringing SDATA_OUT high for the trailing edge
of RESET# causes the STAC9752A/9753A AC-Link outputs to go high impedance, which is suitable for ATE in-circuit
testing.
Once the test mode has been entered, the STAC9752A/9753A must be issued another RESET# with all AC-Link signals
low to return to the normal operating mode.
# denotes active low.
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3. TYPICAL CONNECTION AND POWER DIAGRAMS
3.1.
STAC9752A/9753A Typical Connection Diagram for 48-pin LQFP
Figure 9. STAC9752A/9753A Typical Connection Diagram 48-pin LQFP
*O P TIO NAL
2 *
F errite Bead
3.3V ± 5%
0.1 µF
1 µF
0.1 µF
25
AVdd1
0.1 µF
1 µF
38
1
AVdd2
D Vdd1
0.1 µF
(N ear C lk source)
C LO C K_IN *
9
D Vdd2
XTL_IN
O PTIO N AL
2
24.576 M H z
12
PC _BEEP
XTL_O U T
3
13
PH O N E
SD AT A_O U T
14
AU X_L
BIT_C LK
AU X_R
SD AT A_IN
15
SYN C
16
VID EO _L
R ESET #
17
VID EO _R
C ID 0
18
C ID 1
C D _L
19
S TAC 9753
C D _G N D
20
C D _R
EAPD
VR EFO U T
VR EF
21
M IC 1
NC
22
M IC 2
NC
23
NC
LIN E_IN _L
SPD IF
24
LIN E_IN _R
G PIO 1
32
1 µF *
C AP2
G PIO 0
0.1 µF
LIN E_O U T _L
*O PTIO NA L
LIN E_O U T _R
820 pF
29
820 pF
30
*A dd resistiv e div ider
when using 5V clock.
27 pF
AFILT 1
M O N O _O U T
H P_O U T _L
AFILT 2
H P_C O M M
AVss1
26
AVss2
42
D Vss1
4
D Vss2
7
H P_O U T _R
27 pF
0 
5
EM I
F ilter
22 
6
8
27 pF
10
T U N E T O LAYO U T
11
45
46
47
28
27
1 µF
31
33
34
48
44
43
35
36
37
39
40
H P_C O M M should be tied to
ground at the headphone pin.
41
*T erminate ground
plane as close to codec
as possible
Analog
G round
D igital
G round
NOTE: PIN 48: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally
biased at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has
confused many designers. It should not have any DC path to GND. Connecting the CD_GND
signal directly to ground will change the internal bias of the entire CODEC, and cause significant
distortion. If there is no analog CD input, then this pin can be No-Connect.
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3.2.
STAC9752A/9753A Typical Connection Diagram for 32-pad QFN
Figure 10. STAC9752A/9753A Typical Connection Diagram 32-pad QFN
*OPTIONAL
2 *
Ferrite Bead
3.3V ± 5%
10 µF
1
2
EMI
Filter
22 
27 pF
TUNE TO LAYOUT
3
5
7
8
LINK PINS
22
1 µF*
0.1 µF
1 µF
26
9
AVdd2
DVdd2
0.1 µF
XTL_IN
GPIO
SDATA_OUT
EAPD/GPIO
BIT_CLK
SPDIF_OUT
SDATA_IN
30
31
32
SPDIF and
GPIO PINS
SYNC
STAC9753A
(3.3V Analog)
RESET#
VREFOUT
18
VREF
CAP2
19
1 µF
in 32-pad QFN
0.1 µF
*OPTIONAL
VREF PINS
820 pF
20
820 pF
21
AFILT1
14
MIC2
AFILT2
15
LINE_IN_L
FILTER PINS
9
10
STANDARD
ANALOG I/O
13
MIC1
LINE_IN_R
PHONE
23
LINE_OUT_L
CD_L
11
CD_GND
12
CD_R
HP_OUT_L
MONO_OUT
AVss1
HP_OUT_R
25
LINE_OUT_R
AVss2
17
29
DVss1
4
DVss2
7
16
24
27
UNIVERSAL
JACKSTM
PINS
28
*Terminate ground
plane as close to codec
as possible
Analog
Ground
Digital
Ground
NOTE: PIN 48: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
Note: The CD_GND signal is an AC signal return for the two CD input channels. It is normally
biased at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has
confused many designers. It should not have any DC path to GND. Connecting the CD_GND
signal directly to ground will change the internal bias of the entire CODEC, and cause bad
distortion. If there is no analog CD input, then this pin can be No-Connect.
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3.3.
Split Independent Power Supply Operation
In PC applications, one power supply input to the STAC9752A/9753A may be derived from a supply
regulator and the other directly from the PCI power supply bus. When power is applied to the PC, the
regulated supply input to the IC will be applied some time delay after the PCI power supply. Without
proper on-chip partitioning of the analog and digital circuitry, some manufacturer's CODECs would
be subject to on-chip SCR type latch-up.
TSI’s STAC9752A/9753A specifically allows power-up sequencing delays between the analog
(AVddx) and digital (VDddx) supply pins. These two power supplies can power-up independently
and at different rates with no adverse effects to the CODEC. The IC is designed with independent
analog and digital circuitry that prevents on-chip SCR type latch-up.
However, the STAC9752A/9753A is not designed to operate for extended periods with only the analog supply active.
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3.4.
Split Independent Power Supply Operation for the 32-pad QFP Package
Figure 11. Split Connection Diagram 32-pad QFN
3.3V or 5V ± 5%
3.3V ± 5%
10 µF
1
2
EMI
Filter
22 
3
0.1 µF
10 µF
26
9
AVdd2
DVdd2
0.1 µF
XTL_IN
GPIO
EAPD/GPI0
BIT_CLK
SPDIF_OUT
27 pF
TUNE TO LAYOUT
5
7
8
LINK PINS
22
1 µF*
SDATA_IN
STAC9752A
(5V Analog)
or
STAC9753A
(3.3V Analog)
SYNC
RESET#
CAP2
0.1 µF
820 pF
20
19
VREFOUT
18
VREF
1 µF
VREF PINS
13
14
MIC2
15
LINE_IN_L
9
11
12
25
32
SPDIF and
GPIO PINS
MIC1
AFILT2
10
STANDARD
ANALOG I/O
AFILT1
21
FILTER PINS
31
in 32-pad QFN
*OPTIONAL
820 pF
30
SDATA_OUT
PHONE
16
LINE_IN_R
CD_L
23
LINE_OUT_L
CD_GND
24
LINE_OUT_R
CD_R
27
HP_OUT_L
MONO_OUT
AVss1
AVss2
17
29
DVss1
4
DVss2
7
HP_OUT_R
*Terminate ground
plane as close to codec
as possible
Analog
Ground
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4. CONTROLLER, CODEC, AND AC-LINK
This section describes the physical and high-level functional aspects of the AC‘97 Controller to
CODEC interface, referred to as the AC-Link.
4.1.
AC-Link Physical interface
The STAC9752A/9753A communicates with its companion Digital Controller via the AC-Link digital
serial interface. AC-Link has been defined to support connections between a single Controller and
up to four CODECs. All digital audio, modem and handset data streams, as well as all control (command/status) information are communicated over this serial interconnect, which consists of a clock
(BIT_CLK), frame synchronization (SYNC), serial data in (SDATA_IN), serial data out
(SDATA_OUT), and a reset (RESET#).
4.2.
Controller to Single CODEC
The simplest and most common AC‘97 system configuration is a point-to-point AC-Link connection
between Controller and the STAC9752A/9753A, as illustrated in Figure 12.
Figure 12. AC-Link to its Companion Controller
S YN C
XTA L_IN
B IT _C LK
D igital D C '97
C ontroller
S D A T A _O U T
A C '97 C odec
S D A T A _IN
RESET#
XTA L_O U T
A primary CODEC may act as either a source or a consumer of the BIT_CLK, depending on the configuration.
While RESET# is asserted, if a clock is present at the BIT_CLK pin for at least five cycles before
RESET# is de-asserted, then the CODEC is a consumer of BIT_CLK, and must not drive BIT_CLK
when RESET# is de-asserted. The clock is being provided by other than the primary CODEC, for
instance by the controller or an independent clock chip. In this case the primary CODEC must act as
a consumer of the BIT_CLK signal as if it were a secondary CODEC.
This clock source detection must be done each time the RESET# line is asserted. In the case of a
warm reset, where the clock is halted but RESET# is not asserted, the CODEC must remember the
clock source, and not begin generating the clock on the assertion of SYNC if the CODEC had previously determined that it was a consumer of BIT_CLK.
The STAC9752A/9753A uses the XTAL_OUT pin (Pin 3) and the CID0 and CID1 pins (Pins 45 & 46)
to determine its alternate clock frequencies. See section 2.2.4: page 18 for additional information on
Crystal Elimination and for supported clock frequencies.
If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on
BIT_CLK as defined in the previous paragraph then the AC‘97 CODEC derives its clock internally
from an externally attached 24.576 MHz crystal or oscillator, or optionally from an external
14.318 MHz oscillator, and drives a buffered 12.288 MHz clock to its digital Controller over AC-Link
under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental impediment
to high quality output, and the internally generated clock will provide AC‘97 components with a clean
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clock that is independent of the physical proximity of AC‘97’s Digital Controller (henceforth referred
to as “the Controller”).
If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by
other than the primary CODEC, for instance by the controller or by a discrete clock source. In this
case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary
CODEC.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-Link is synchronized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller generates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This
yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-Link
on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiving side of AC-Link on each immediately following falling edge of BIT_CLK.
4.3.
Controller to Multiple CODECs
Several vendor specific methods of supporting multiple CODEC configurations on AC-Link have
been implemented or proposed, including CODECs with selective AC-Link pass-through and controllers with duplicate AC-Links.
Potential implementations include:
•
6-channel audio using 3 x 2-channel CODECs
•
Separate CODECs for independent audio and modem AFE
•
Docking stations, where one CODEC is in the laptop and another is in the dock
This specification defines support for up to four CODECs on the AC-Link. By definition there can be
one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC
ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets;
each is individually accessible and they do not share registers.
Multiple CODEC AC-Link implementations must run off a common BIT_CLK. They can potentially
save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC‘97 Digital Controller.
Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of multiple devices on one serial input line.
Support for multiple CODEC operation necessitates a specially designed Controller. An AC‘97 Digital Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs,
supporting one Primary CODEC and up to three Secondary CODECs.
4.3.1.
Primary CODEC Addressing
Primary AC‘97 CODECs respond to register read and write commands directed to CODEC ID 00
(see Section 4 for details of the Primary and Secondary CODEC addressing protocols). Primary
devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID 00, and
reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem ID Register(s).
The Primary CODEC may either drive the BIT_CLK signal or consume a signal provided by the Digital Controller or other clock generator.
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4.3.2.
Secondary CODEC Addressing
Secondary AC‘97 CODECs respond to register read and write commands directed to CODEC IDs
01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other methods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended
Modem ID Register(s).
CODECs configured as Secondary must power up with the BIT_CLK pin configured as an input.
Using the provided BIT_CLK signal is necessary to ensure that everything on the AC-Link is synchronous. BIT_CLK is the clock source (multiplied by 2 so that the internal rate is 24.576 MHz).
4.3.3.
CODEC ID Strapping
Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping
(i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted
polarity and default to 00 = Primary (via a weak internal pullup) when left floating. This eliminates the
need for external resistors for CODECs configured as Primary, and maintains backward compatibility
with existing layouts that treat pins 45 and 46 as “no connect” or a capacitor connected to ground.
Pulldowns are typically 0-10 KW and connected to Digital (not Analog) Ground.
Table 3. Recommended CODEC ID strapping
4.4.
CID1 (pin 46)
CID0 (pin 45)
Configuration
NC
NC
Primary ID 00
NC
pulldown
Secondary ID 01
pulldown
NC
Secondary ID 10
pulldown
pulldown
Secondary ID 11
Clocking for Multiple CODEC Implementations
To keep the system synchronous, all Primary and Secondary CODEC clocking must be derived from
the same clock source, so they are operating on the same time base. In addition, all AC-Link protocol timing must be based on the BIT_CLK signal, to ensure that everything on the AC-Link will be
synchronous.
The following are potential 24.576 MHz clock options available to a Secondary CODEC:
•
Using an external 24.576 MHz signal source (external oscillator or AC‘97 Digital Controller)
•
Using the Primary’s crystal out
•
Using the Primary’s BIT_CLK output to derive 24.576 MHz
See section 2.2.4: page 18 for clock frequencies supported and configurations.
4.5.
STAC9752A/9753A as a Primary CODEC
Primary devices are required to support correctly either of the following clocking options:
•
24.576 MHz crystal attached to XTAL_IN and XTAL_OUT
•
24.576 MHz external oscillator provided to XTAL_IN
•
12.288 MHz oscillator provided to the BIT_CLK input
The Primary device may also optionally support the following clocking option:
•
14.318 MHz external oscillator provided to XTAL_IN
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See section 2.2.4: page 18 for clock frequencies supported and configurations.
4.5.1.
STAC9752A/9753A as a Secondary CODEC
Secondary devices are required to function correctly using one or more of the following clocking
options:
•
24.576 MHz external oscillator provided to XTAL_IN (synchronous and in phase with Primary
24.576 MHz clock)
•
BIT_CLK input provided by the Primary. In this mode, a clock at XTAL_IN (Pin 2) is ignored.
See section 2.2.4: page 18 for clock frequencies supported and configurations.
4.6.
AC-Link Power Management
4.6.1.
Powering down the AC-Link
The AC-Link signals can be placed in a low power mode. When AC‘97’s Powerdown Register (26h)
is programmed to the appropriate value, both BIT_CLK and SDATA_IN are brought to and held at a
logic low voltage level. After signaling a reset to AC‘97, the AC‘97 Controller should not attempt to
play or capture audio data until it has sampled a CODEC Ready indication from AC‘97.
Figure 13. STAC9752A/9753A Powerdown Timing
SYNC
B IT _ C L K
SD AT A_O U T
s lo t 2
per
fra m e
TAG
S D A T A _ IN
s lo t 2
per
fra m e
TAG
W rite to
0 x2 0
D A TA
PR4
N o te : B IT _ C L K n o t to s c a le
BIT_CLK and SDATA_IN are transitioned low immediately following decode of the write to the Powerdown Register (26h) with PR4. When the AC‘97 Controller driver is at the point where it is ready to
program the AC-Link into its low power mode, slots 1 and 2 are assumed to be the only valid stream
in the audio output frame.
After programming the AC‘97 device to this low power, halted mode, the AC‘97 Controller is required
to drive and keep SYNC and SDATA_OUT low.
Once the AC‘97 CODEC has been instructed to halt BIT_CLK, a special “wake-up” protocol must be
used to bring the AC-Link to the active mode since normal audio output and input frames can not be
communicated in the absence of BIT_CLK.
4.6.2.
Waking up the AC-Link
There are two methods for bringing the AC-Link out of a low power, halted mode. Regardless of the
method, it is the AC‘97 Controller that performs the wake-up task.
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4.6.2.1.
Controller Initiates Wake-up
AC-Link protocol provides for a “Cold AC‘97 Reset”, and a “Warm AC‘97 Reset”. The current powerdown state would ultimately dictate which form of AC‘97 reset is appropriate. Unless a “cold” or “register” reset (a write to the Reset Register) is performed, wherein the AC‘97 registers are initialized to
their default values, registers are required to keep state during all powerdown modes.
Once powered down, re-activation of the AC-Link via re-assertion of the SYNC signal must not occur
for a minimum of four audio frame times following the frame in which the powerdown was triggered.
When AC-Link powers up the CODEC indicates readiness via the CODEC Ready bit (input slot 0, bit
15).
4.6.2.2.
CODEC Initiates Wake-up
The STAC9752A/9753A (running off Vaux) can trigger a wake event (PME#) by transitioning
SDATA_IN from low to high and holding it high until either a warm or cold reset is observed on the
AC-Link. This functionality is typically implemented in modem CODECs that detect ring, Caller ID,
etc.
Note that when the AC-Link is either programmed to the low power mode or shut off completely,
BIT_CLK may stop if the primary CODEC is supplying the clock, which shuts down the AC-Link clock
to the Secondary CODEC1. In order for a Secondary CODEC to react to an external event (phone
ringing), it must support an independent clocking scheme for any PME# associated logic that must
be kept alive when the AC-Link is down. This includes logic to asynchronously drive SDATA_IN to a
logic high-level, which signals a wake request to the AC‘97 Digital Controller.
4.6.3.
CODEC Reset
There are three types of AC‘97 reset:
•
a cold reset where all AC‘97 logic (most registers included) is initialized to its default state
•
a warm reset where the contents of the AC‘97 register set are left unaltered
•
a register reset which only initializes the AC‘97 registers to their default states
4.6.3.1.
Cold AC‘97 Reset
A cold reset is achieved by asserting RESET# low for the minimum specified time, then subsequently de-asserting RESET# high. BIT_CLK and SDATA_IN will be activated, or re-activated as the
case may be, and all AC‘97 control registers will be initialized to their default power on reset values.
RESET# is an asynchronous AC‘97 input.
4.6.3.2.
Warm AC‘97 Reset
A warm AC‘97 reset will re-activate the AC-Link without altering the current AC‘97 register values. A
warm reset is signaled by driving SYNC high for a minimum of 1 ms in the absence of BIT_CLK.
Within normal audio frames SYNC is a synchronous AC‘97 input. However, in the absence of
BIT_CLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to
AC‘97.
1.
Secondary CODEC always configures its BIT_CLK pin as an input.
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AC‘97 MUST NOT respond with the activation of BIT_CLK until SYNC has been sampled low again
by AC‘97. This will preclude the false detection of a new audio frame.
4.6.3.3.
Register AC‘97 Reset
Most registers in an AC97 device can be restored to their default values by performing a write (any
value) to the Reset Register, 00h.
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5. AC-LINK DIGITAL INTERFACE
5.1.
Overview
AC-Link is the 5-pin digital serial interface that links AC‘97 CODEC to the Controller. The AC-Link
protocol is a bi-directional, fixed clock rate, serial digital stream. AC-Link handles multiple input and
output PCM audio streams, as well as control register accesses employing a time division multiplexed (TDM) scheme that divides each audio frame into 12 outgoing and 12 incoming data streams,
each with 20-bit sample resolution.
The STAC9752A/9753A DACs, ADCs, and SPDIF can be assigned to slots 3&4, 6&9, 7&8 or 10&11.
Figure 14. Bi-directional AC-Link Frame with Slot assignments
SLOTS
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD
ADDR
CMD
DATA
PCM
LEFT
PCM
RT
NA
PCM
CTR
PCM
LSURR
PCM
RSURR
PCM
LFE
SPDIF
SPDIF
IO
CTRL
TAG
STATUS
ADDR
STATUS
DATA
PCM
LEFT
PCM
RT
LINE1
ADC
PCM
MIC
Vendor
RSVD
Vendor
RSVD
Vendor
RSVD
LINE2
ADC
HSET
ADC
IO
STATUS
SYNC
OUTGOING STREAMS
(Controller output - SDATA_OUT)
INCOMING STREAMS
(codec output - SDATA_IN)
TAG PHASE
DATA PHASE
Slot 12 can be used by the
AC'97 Codec if a Modem
Codec is not present.
Table 4. AC-Link Output Slots (transmitted from the Controller)
Slot
Name
Description
0
SDATA_OUT TAG
MSBs indicate which slots contain valid data; LSBs convey
CODEC ID
1
Control CMD ADDR write port
Read/write command bit plus 7-bit CODEC register address
2
Control DATA write port
3, 4
PCM L&R DAC playback
20-bit PCM data for Left and Right channels
5
Modem Line 1 DAC
16-bit modem data for modem Line 1 output
16-bit command register write data
6, 7, 8, 9 PCM Center, Surround L&R, LFE 20-bit PCM data for Center, Surround L&R, LFE channels
10
Modem Line 2 DAC
11
Modem handset DAC
12
Modem IO control
12
CODEC IRQ
10-11
SPDIF Out
10-12
Double Rate Audio
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16-bit modem data for modem Line 2 output
16-bit modem data for modem Handset output
GPIO write port for modem Control
Can be used by CODEC if a modem CODEC is not present.
Optional AC-Link bandwidth for SPDIF output
Optional AC-Link bandwidth for 88.2 or 96 KHz on L, C, R
channels
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Table 5. The AC-Link Input Slots (transmitted from the CODEC)
5.2.
Slot
Name
0
SDATA_IN TAG
1
STATUS ADDR read port
2
STATUS DATA read port
3, 4
PCM L&R ADC record
Description
MSBs indicate which slots contain valid data
MSBs echo register address; LSBs indicate which slots request data
16-bit command register read data
20-bit PCM data from Left and Right inputs
5
Modem Line 1 ADC
16-bit modem data from modem Line1 input
6-11
PCM ADC Record
20-bit PCM data - Alternative Slots for Input
12
GPIO Status
GPIO read port and interrupt status
AC-Link Serial Interface Protocol
The AC‘97 Controller signals synchronization of all AC-Link data transactions. The AC‘97 CODEC,
Controller, or external clock source drives the serial bit clock onto AC-Link, which the AC‘97 Controller then qualifies with a synchronization signal to construct audio frames. SYNC, fixed at 48 KHz, is
derived by dividing down the serial bit clock (BIT_CLK). BIT_CLK, fixed at 12.288 MHz, provides the
necessary clocking granularity to support twelve 20-bit outgoing and incoming time slots. AC-Link
serial data is transitioned on each rising edge of BIT_CLK. The receiver of AC-Link data (CODEC for
outgoing data and Controller for incoming data) samples each serial bit on the falling edges of
BIT_CLK.
The AC-Link protocol provides for a special 16-bit time slot (Slot 0) wherein each bit conveys a valid
tag for its corresponding time slot within the current audio frame. A 1 in a given bit position of slot 0
indicates that the corresponding time slot within the current audio frame has been assigned to a data
stream, and contains valid data. If a slot is tagged invalid, it is the responsibility of the source of the
data, (AC‘97 CODEC for the input stream, AC‘97 Controller for the output stream), to stuff all bit
positions with 0s during that slot’s active time.
SYNC remains high for a total duration of 16 BIT_CLKs at the beginning of each audio frame. The
portion of the audio frame where SYNC is high is defined as the “Tag Phase”. The remainder of the
audio frame where SYNC is low is defined as the “Data Phase”.
Additionally, for power savings, all clock, sync, and data signals can be halted. This requires that an
AC‘97 CODEC be implemented as a static design to allow its register contents to remain intact when
entering a power savings mode.
5.2.1.
AC-Link Variable Sample Rate Operation
The AC-Link serial interconnect defines a digital data and control pipe between the Controller and
the CODEC. The AC-Link supports twelve 20-bit slots at 48 KHz on SDATA_IN and SDATA_OUT.
The time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastructure that the source of each slot’s data sets or clears to indicate the validity of the slot data within the
current audio frame. This tag infrastructure can be used to support transfers between Controller and
CODEC at any sample rate.
5.2.2.
Variable Sample Rate Signaling Protocol
AC-Link’s tag infrastructure imposes FIFO requirements on both sides of the AC-Link. For example,
in passing a 44.1 KHz stream across the AC-Link, for every 480 audio output frames that are sent
across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441
PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave
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valid and non-valid slots? Each possible method brings with it different FIFO requirements. To
achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different manufacturers, it is necessary to standardize the scheme for at least one side of the AC-Link so that the
FIFO requirements will be common to all designs. The CODEC side of the AC-Link is the focus of
this standardization.
The new standard approach calls for the addition of “on demand” slot request flags. These flags are
passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time
the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)
in a given audio input frame, it knows that it must pass along the next PCM sample for the corresponding slot(s) in the AC-Link output frame that immediately follows.
The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to
1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:
1. Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate
Registers 2C-34h.
2. Enables the on demand CODEC-to-Controller signaling protocol using SLOTREQ bits that
becomes necessary when a DAC’s sample rate varies from the 48 KHz AC-Link serial frame
rate.
The table below summarizes the behavior:
Table 6. VRA Behavior
AC‘97 Functionality
VRA = 0
VRA = 1
SLOTREQ bits
always 0 (data each frame)
0 or 1 (data on demand)
sample rate registers
forced to 48 KHz
writable
Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should
NOT be used.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-Link output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current
AC-Link input frame signal which active output slots require data from the AC‘97 Digital Controller in
the next audio output frame. An active output slot is defined as any slot supported by the CODEC
that is not in a power-down state. For fixed 48 KHz operation the SLOTREQ bits are always set
active (low) and a sample is transferred in each frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to Controller), the CODEC sets the TAG bit; for SDATA_OUT (Controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame.
The VRM (Variable Rate Mic Audio) bit in the Extended Audio Status and Control Register controls
the optional MIC ADC input behavior in the same way that VRA = 1 controls the PCM ADC.
5.2.2.1.
SLOTREQ Behavior and Power Management
SLOTREQ bits for fixed rate, powered down, and all unsupported Slots should be driven with 0s for
maximum compatibility with the original AC '97 Component Specification. When a DAC channel is
powered down, it disappears completely from the serial frame: output tag and slot are ignored, and
the SLOTREQ bit is absent (forced to zero).
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When the Controller wants to power-down a channel, all it needs to do is:
1. Disable source of DAC samples in Controller
2. Set PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh
When it wants to power up the channel, all it needs to do is:
1. Clear PR bit for DAC channel in Registers 26h, 2Ah, or 3Eh
2. Enable source of DAC samples in Controller
5.2.3.
Primary and Secondary CODEC Register Addressing
The 2-bit CODEC ID field in the LSBs of Output Slot 0 is an addition to the original AC-Link protocol
that enables an AC‘97 Digital Controller to independently access Primary and Secondary CODEC
registers.
For Primary CODEC access, the AC‘97 Digital Controller:
1. Sets the AC-Link Frame valid bit (Slot 0, bit 15).
2. Validates the tag bits for Slot 1 and 2 Command Address and Data (Slot 0, bits 14 and 13).
3. Sets a zero value (00) into the CODEC ID field (Slot 0, bits 1 and 0).
4. Transmits the desired Primary CODEC Command Address and Command Data in Slots 1 and 2.
For Secondary CODEC access, the AC‘97 Digital Controller:
1. Sets the AC-Link Frame valid bit (Slot 0, bit 15).
2. Places a non-zero value (01, 10, or 11) into the CODEC ID field (Slot 0, bits 1 and 0).
3. Transmits the desired Secondary CODEC Command Address and Command Data in Slots 1
and 2.
Secondary CODECs disregard the Command Address and Command Data (Slot 0, bits 14 and 13)
tag bits. In a sense the Secondary CODEC ID field functions as an alternative Valid Command
Address (for Secondary reads and writes) and Command Data (for Secondary writes) tag indicator.
Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state
of the Secondary CODEC ID bits) if it is not valid. AC‘97 Digital Controllers should set the frame valid
bit for a frame with a Secondary register access, even if no other bits in the output tag slot except the
Secondary CODEC ID bits are set.
5.3.
AC-Link Output Frame (SDATA_OUT)
The AC-Link output frame data streams correspond to the multiplexed bundles of all digital output
data targeting AC‘97’s DAC inputs, and control registers. As mentioned earlier, each AC-Link output
frame supports up to twelve 20-bit outgoing data time slots. Slot 0 is a special reserved time slot containing 16-bits which are used for AC-Link protocol infrastructure.
Figure 15 illustrates the time slot based AC-Link protocol.
Figure 15. AC-Link Audio Output Frame
A new AC-Link output frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97 Controller transitions SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit posiTSI™ CONFIDENTIAL
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Data Phase
Tag Phase
SYNC
20.8 uS (48 kHZ)
12.288 MHz
BIT_CLK
valid
Frame
SDATA_OUT
slot1
slot2
slot(12)
"0"
CID1
CID0
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame
Time Slot "Valid" Bits
("1" = time slot contains valid PCM data)
Slot 1
Slot 2
Slot 3
Slot 12
tion is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the AC‘97
CODEC on the following falling edge of BIT_CLK. This sequence ensures that data transitions and
subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 16. Start of an Audio Output Frame
S Y N C
d e te c te d b y
c o d e c
S Y N C
a s s e rte d
f ir s t
S D A T A _ O U T
b it o f f r a m e
S Y N C
B IT _ C L K
v a lid
F ra m e
S D A T A _ O U T
E n d
o f p r e v io u s a u d io
s lo t 1
s lo t 2
fra m e
SDATA_OUT’s composite stream is MSB justified (MSB first) with all non-valid slots’ bit positions
stuffed with 0s by the AC‘97 Controller. If there are less than 20 valid bits within an assigned and
valid time slot, the AC‘97 Controller always stuffs all trailing non-valid bit positions of the 20-bit slot
with 0s.
As an example, consider an 8-bit sample stream that is being played out to one of the
STAC9752A/9753A DACs. The first 8-bit positions are presented to the DAC (MSB justified) followed by the next 12 bit-positions which are stuffed with 0s by the AC‘97 Controller. This ensures
that regardless of the resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be
introduced by the least significant bits.
When mono audio sample streams are output from the AC‘97 Controller it is necessary that BOTH
left and right sample stream time slots be filled with the same data.
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5.3.1.
Slot 0: TAG / CODEC ID
Table 7. Output Slot 0 Bit Definitions
Bit
Description
15
Frame Valid
14
Slot 1 Primary CODEC Valid Command Address bit (Primary CODEC only)
13
Slot 2 Primary CODEC Valid Command Data bit (Primary CODEC only)
12-3
Slot 3-12 Valid Data bits
12
Slot 3: PCM Left channel
11
Slot 4: PCM Right channel
10
Slot 5: Modem Line 1 (not used on STAC9752A/9753A)
9
Slot 6: Alternative PCM1 Left
8
Slot 7: Alternative PCM2 Left
7
Slot 8: Alternative PCM2 Right
6
Slot 9: Alternative PCM1 Right
5
Slot 10: SPDIF Left
4
Slot 11: SPDIF Right
3
Slot 12: Audio GPIO
2
Reserved (Set to 0)
1-0
2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Note: The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Within slot 0 the first bit is a global bit (SDATA_OUT slot 0, bit 15) which flags the validity for the
entire audio frame. If the “Valid Frame” bit is a 1, this indicates that the current audio frame contains
at least one time slot of valid data. The next 12 bit positions sampled by AC‘97 indicate which of the
corresponding 12 time slots contain valid data. In this way data streams of differing sample rates can
be transmitted across AC-Link at its fixed 48 KHz audio frame rate.
The two LSBs of Slot 0 transmit the CODEC ID used to distinguish Primary and Secondary CODEC
register access.
5.3.2.
Slot 1: Command Address Port
The command port is used to control features, and monitor status (see AC-Link input frame Slots 1
and 2) for AC‘97 CODEC functions including, but not limited to, mixer settings, and power management (refer to the control register section of this specification).
The control interface architecture supports up to 64 16-bit read/write registers, addressable on even
byte boundaries. Only the even registers (00h, 02h, etc.) are currently defined, odd register (01h,
03h, etc.) accesses are reserved for future expansion.
Note that shadowing of the control register file on the AC‘97 Controller is an option left open to the
implementation of the AC‘97 Controller. The AC‘97 CODEC’s control register file is nonetheless
required to be readable as well as writeable to provide more robust testability.
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AC-Link output frame slot 1 communicates control register address, and write/read command information to the STAC9752A/9753A.
Table 8. Command Address Port Bit Assignments
Bit
Description
Comments
19
Read/Write command
1 = read, 0 = write
18:12
Control Register Index
sixty-four 16-bit locations, addressed on even byte boundaries
11:0
Reserved
Stuffed with 0s
The first bit (MSB) sampled by AC‘97 indicates whether the current control transaction is a read or a
write operation. The following 7 bit positions communicate the targeted control register address. The
trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC‘97 Controller.
5.3.3.
Slot 2: Command Data Port
The command data port is used to deliver 16-bit control register write data in the event that the current command port operation is a write cycle. (as indicated by Slot 1, bit 19)
•
Bit(19:4) Control Register Write Data (Stuffed with 0s if current operation is a read)
•
Bit(3:0)
Reserved
(Stuffed with 0s)
If the current command port operation is a read then the entire slot time must be stuffed with 0s by
the AC‘97 Controller.
5.3.4.
Slot 3: PCM Playback Left Channel
AC-Link output frame slot 3 is the composite digital audio left playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s.
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.5.
Slot 4: PCM Playback Right Channel
AC-Link output frame slot 4 is the composite digital audio right playback stream. In a typical “Games
Compatible” PC this slot is composed of standard PCM (.wav) output samples digitally mixed (on the
AC‘97 Controller or host processor) with music synthesis output samples. If a sample stream of resolution less than 20-bits is transferred, the AC‘97 Controller must stuff all trailing non-valid bit positions within this time slot with 0s.
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.6.
Slot 5: NOT USED (Modem Line 1 Output Channel)
Audio output frame slot 5 is reserved for modem operation and is not used by the
STAC9752A/9753A.
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5.3.7.
Slot 6 -11: DAC
The DAC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.3.8.
Slot 12: Audio GPIO Control Channel
AC-Link output frame slot 12 contains the audio GPIO control outputs.
5.4.
AC-Link Input Frame (SDATA_IN)
The AC-Link input frame data streams correspond to the multiplexed bundles of all digital input data
targeting the AC‘97 Controller. As is the case for an audio output frame, each AC-Link input frame
consists of twelve 20-bit time slots. Slot 0 is a special reserved time slot containing 16-bits which are
used for AC-Link protocol infrastructure.
The following diagram illustrates the time slot-based AC-Link protocol.
Figure 17. STAC9752A/9753A Audio Input Frame
Data Phase
Tag Phase
SYNC
20.8 uS (48 kHZ)
12.288 MHz
BIT_CLK
valid
Frame
SDATA_IN
slot1
slot2
slot(12)
"0"
"0"
"0"
19
"0"
19
"0"
19
"0"
19
"0"
End of previous audio frame
Time Slot "Valid" Bits
Slot 1
Slot 2
Slot 3
Slot 12
("1" = time slot contains valid PCM data)
A new AC-Link input frame begins with a low to high transition of SYNC. SYNC is synchronous to
the rising edge of BIT_CLK. On the immediately following falling edge of BIT_CLK, the AC‘97
CODEC samples the assertion of SYNC. This falling edge marks the time when both sides of
AC-Link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC‘97
CODEC transitions SDATA_IN into the first bit position of slot 0 (“CODEC Ready” bit). Each new bit
position is presented to AC-Link on a rising edge of BIT_CLK, and subsequently sampled by the
AC‘97 Controller on the following falling edge of BIT_CLK. This sequence ensures that data transitions and subsequent sample points for both incoming and outgoing data streams are time aligned.
Figure 18. Start of an Audio Input Frame
S Y N C
d e te c te d
f ir s t
S D A TA _O U T
b it o f f r a m e
S Y N C
B IT _ C L K
C odec
R eady
S D A T A _ IN
s lo t 1
s lo t 2
E n d o f p r e v io u s a u d io f r a m e
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SDATA_IN’s composite stream is MSB justified (MSB first) with all non-valid bit positions (for
assigned and/or unassigned time slots) stuffed with 0s by the AC‘97 CODEC. SDATA_IN data is
sampled on the falling edges of BIT_CLK.
5.4.1.
Slot 0: TAG
Within slot 0, the first bit is a global bit (SDATA_IN slot 0, bit 15) which flags whether the AC‘97
CODEC is in the “CODEC Ready” state or not. If the “CODEC Ready” bit is a 0, this indicates that
the AC‘97 CODEC is not ready for normal operation. This condition is normal following the deassertion of power on reset for example, while the AC‘97 CODEC’s voltage references settle. When the
AC-Link “CODEC Ready” indicator bit is a 1 it indicates that the AC-Link and AC‘97 CODEC control
and status registers are in a fully operational state. CODEC must assert “CODEC Ready” within
400 ms after it starts receiving valid SYNC pulses from the controller, to provide indication of connection to the link and Control/Status registers are available for access. The AC’97 Controller and
related software must wait until all of the lower four bits of the Control/Status Register, 26h, are set
before attempting any register writes, or attempting to enable any audio stream, to avoid undesirable
audio artifacts.
Prior to any attempts at putting an AC‘97 CODEC into operation, the AC‘97 Controller should poll the
first bit in the AC-Link input frame (SDATA_IN slot 0, bit 15) for an indication that CODEC has gone
“CODEC Ready”. Once an AC‘97 CODEC is sampled “CODEC Ready”1 then the next 12 bit positions sampled by the AC‘97 Controller indicate which of the corresponding 12 time slots are
assigned to input data streams, and that they contain valid data.
5.4.2.
Slot 1: Status Address Port / SLOTREQ Signaling Bits
5.4.2.1.
Status Address Port
The status port is used to monitor status for the STAC9752A/9753A functions including, but not limited to, mixer settings and power management. AC-Link input frame slot 1’s stream echoes the control register index, for historical reference, for the data to be returned in slot 2. (Assuming that slots 1
and 2 had been tagged “valid” by the AC‘97 CODEC during slot 0.
Table 9. Status Address Port Bit Assignments
Bit
Description
Comments
19
Reserved
Stuffed with 0s
18:12
Control Register Index
Echo of register index for which data is being returned
11:2
SLOTREQ
See Section 5.4.2.2: page 40
1:0
Reserved
Stuffed with 0s
The first bit (MSB) generated by AC‘97 is always stuffed with a 0. The following 7 bit positions communicate the associated control register address, the next 10 bits support AC‘97’s variable sample
rate signaling protocol, and the trailing 2 bit positions are stuffed with 0s by AC‘97.
5.4.2.2.
SLOTREQ signaling bits
AC-Link input frame Slot #1, the Status Address Port, now delivers CODEC control register read
address and variable sample rate slot request flags for all output slots. Ten of the formerly reserved
least significant bits have been defined as data request flags for output slots 3-12.
1. There are several subsections within an AC‘97 CODEC that can independently go busy/ready. It is the responsibility of the
AC’97 Controller to probe more deeply into the AC‘97 CODEC’s register file to determine which subsections are actually ready.
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The AC-Link input frame Slot 1 tag bit is independent of the bit 11-2 slot request field, and ONLY indicates valid Status Address Port data (Control Register Index). The CODEC should only set
SDATA_IN tag bits for Slot 1 (Address) and Slot 2 (Data) to 1 when returning valid data from a previous register read. They should otherwise be set to 0. SLOTREQ bits have validity independent of the
Slot 1 tag bit.
SLOTREQ bits are always 0 in the following cases
•
Fixed rate mode (VRA = 0)
•
Inactive (powered down) ADC channel
SLOTREQ bits are only set to 1 by the CODEC in the following case
•
5.4.3.
Variable rate audio mode (VRA = 1) AND active (power ready) ADC AND a non-48 KHz ADC
sample rate and CODEC does not need a sample
Slot 2: Status Data Port
The status data port delivers 16-bit control register read data.
Table 10. Status Data Port Bit Assignments
Bit
Description
Comments
19:4
Control Register Read Data
Stuffed with 0s if tagged "invalid"
3:0
Reserved
Stuffed with 0s
If Slot 2 is tagged invalid by AC‘97, then the entire slot will be stuffed with 0s by AC‘97.
5.4.4.
Slot 3: PCM Record Left Channel
Audio input frame slot 3 is the left channel output of STAC9752A/9753A input MUX, post-ADC.
STAC9752A/9753A ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.5.
Slot 4: PCM Record Right Channel
Audio input frame slot 4 is the right channel output of STAC9752A/9753A input MUX, post-ADC.
STAC9752A/9753A ADCs are implemented to support 20-bit resolution.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.6.
Slot 5: NOT USED (Modem Line 1 ADC)
Audio input frame slot 5 is not used by the STAC9752A/9753A and is always stuffed with 0s.
5.4.7.
Slot 6-9: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 6&9 by Register
6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
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5.4.8.
Slots 7-8: Vendor Reserved
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 7&8 by Register
6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.9.
Slot 10 & 11: ADC
The left and right ADC channels of the STAC9752A/9753A may be assigned to slots 10&11 by Register 6Eh.
NOTE: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
5.4.10.
Slot 12: Reserved
AC-Link input frame slot 12 contains the GPIO status inputs and allows for audio interrupts. Slot 12
can be used by the AC’97 CODEC is a modem CODEC is not present.
5.5.
AC-Link Interoperability Requirements and Recommendations
5.5.1.
“Atomic slot” Treatment of Slot 1 Address and Slot 2 Data
Command or Status Address and Data cannot be split across multiple AC-Link frames. The following
transactions require that valid Slot 1 Address and valid Slot 2 Data be treated as “atomic” (inseparable) with Slot 0 Tag bits for Address and Data set accordingly (that is, both valid):
1. AC‘97 Digital Controller write commands to Primary CODECs
2. AC‘97 CODEC status responses
Whenever the AC‘97 Digital Controller addresses a Primary CODEC or an AC‘97 CODEC responds
to a read command, Slot 0 Tag bits should always be set to indicate actual Slot 1 and Slot 2 data
validity.
Table 11. Primary CODEC Addressing: Slot 0 Tag Bits
Function
Slot 0, bit 15
Slot 0, bit 14
Slot 0, bit 13
Slot 0, Bits 1-0
(Valid Frame) (Valid Slot 1 Address) (Valid Slot 2 Data) (CODEC ID)
AC‘97 Digital Controller
Primary Read Frame N,
SDATA_OUT
1
1
0
00
AC‘97 Digital Controller
Primary Write Frame N,
SDATA_OUT
1
1
1
00
AC‘97 CODEC Status Frame
N+1, SDATA_IN
1
1
1
00
When the AC‘97 Digital Controller addresses a Secondary CODEC, the Slot 0 Tag bits for Address
and Data must be 0. A non-zero, 2-bit CODEC ID in the LSBs of Slot 0 indicates a valid Read or
Write Address in Slot 1, and the Slot 1 R/W bit indicates presence or absence of valid Data in Slot 2.
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Table 12. Secondary CODEC Addressing: Slot 0 tag bits
Slot 0, bit 15
Slot 0, bit 14
Slot 0, bit 13
Slot 0, Bits 1-0
(Valid Frame) (Valid Slot 1 Address) (Valid Slot 2 Data) (CODEC ID)
Function
5.6.
AC‘97 Digital Controller
Secondary Read Frame N,
SDATA_OUT
1
0
0
01, 10, or 11
AC‘97 Digital Controller
Secondary Write Frame N,
SDATA_OUT
1
0
0
01, 10, or 11
AC‘97 CODEC Status Frame
N+1, SDATA_IN
1
1
1
00
Slot Assignments for Audio
Figure 19. Bi-directional AC-Link Frame with Slot assignments
SLOTS
0
1
2
3
4
5
6
7
8
9
10
11
12
TAG
CMD
ADDR
CMD
DATA
PCM
LEFT
PCM
RT
NA
PCM
CTR
PCM
LSURR
PCM
RSURR
PCM
LFE
SPDIF
SPDIF
IO
CTRL
TAG
STATUS
ADDR
STATUS
DATA
PCM
LEFT
PCM
RT
LINE1
ADC
PCM
MIC
Vendor
RSVD
Vendor
RSVD
Vendor
RSVD
LINE2
ADC
HSET
ADC
IO
STATUS
SYNC
OUTGOING STREAMS
(Controller output - SDATA_OUT)
INCOMING STREAMS
(codec output - SDATA_IN)
TAG PHASE
DATA PHASE
Slot 12 can be used by the
AC'97 Codec if a Modem
Codec is not present.
The AC-link output slots (transmitted to the Codec) are defined as follows:
Table 13. AC-Link Output Slots Dedicated To CODEC
Slot
Name
Description
0
SDATA_OUT TAG
MSBs indicate which slots contain valid data; LSBs convey Codec ID
1
Control CMD ADDR write port
Read/write command bit plus 7-bit Codec register address
2
Control DATA write port
16-bit command register write data
3,4
PCM L & R DAC playback
16, 18, or 20-bit PCM data for left and right channels
5
Modem Line 1 DAC
16-bit modem data for modem line 1 output
6,7,8,9
PCM Center, Rear, LFE
16, 18, or 20-bit PCM data for Center, L & R Rear, LFE channels
10
Modem Line 2 DAC
16-bit modem data for modem line 2 output
11
Modem handset DAC
16-bit modem data for modem handset output
12
Modem IO control
GPIO write port for modem control
10-12
Double rate audio
Optional AC-link bandwidth for 88.2 or 96 kHz on L, C, R channels
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The AC-link input slots (transmitted from the Codec) are defined as follows:
Figure 20. AC-Link Input Slots Dedicated To CODEC
Slot
Name
Description
0
SDATA_IN TAG
MSBs indicate which slots contain valid data
1
STATUS ADDR read port
MSBs echo register address; LSBs indicate which slots request data
2
STATUS DATA read port
16-bit command register read data
3,4
PCM L & R ADC record
16-bit PCM data from left and right inputs
5
Modem Line 1 ADC
16-bit modem data from modem line 1 input
6
Dedicated Microphone ADC
16-bit PCM data from optional 3rd ADC input
7,8,9
Vendor reserved
Vendor specific (enhanced input for docking, array mic, etc)
10
Modem Line 2 ADC
16-bit modem data from modem line 2 input
11
Modem handset input
16-bit modem data for modem handset input
12
Modem IO status
GPIO read port for modem control
Note: The DAC & ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
The AC-Link output slots dedicated to audio are defined as follows:
Table 14. AC-Link Output Slots Dedicated To Audio
Slot
Name
Description
3
PCM L DAC playback
20-bit PCM data for left channel
4
PCM R DAC playback
20-bit PCM data for right channel
6
PCM Center
20-bit PCM data for Center channel
7
PCM L Surround
20-bit PCM data for L Surround channel
8
PCM R Surround
20-bit PCM data for R Surround channel
9
PCM LFE
20-bit PCM data for LFE channel
10:11
SPDIF Out
20-bit SPDIF Output
12
Reserved
Reserved
The AC-Link input slots dedicated to audio are defined as follows:
Table 15. AC-Link Input Slots Dedicated To Audio
Slot
Name
Description
3
PCM L ADC record
20-bit PCM data from left input
4
PCM R ADC record
20-bit PCM data from right inputs
6
Dedicated Microphone ADC
20-bit PCM data from optional 3rd ADC input
7
Vendor reserved
Vendor specific (enhanced input for docking, array mic, etc.)
8
Vendor reserved
Vendor specific (enhanced input for docking, array mic, etc.)
9
Vendor reserved
Vendor specific (enhanced input for docking, array mic, etc.)
12
Audio Interrupt
Provides optional interrupt capability for Audio CODEC (not usable
when a modem is present)
Note: The ADC can be assigned to slots 3&4, 6&9, 7&8, or 10&11.
Table 16. Audio Interrupt Slot Definitions
Bit
Description
19-1
Reserved (Audio CODEC will return zeros in bits 19-1)
0
Optional: Assertion = 1 will cause interrupt to be propagated to Audio controller system interrupt. See
register 24h definition for enabling mechanism.
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6. STAC9752A/9753A FUNCTIONAL BLOCKS
6.1.
STAC9752A/9753A Mixer Description
The STAC9752A/9753A includes an analog mixer for maximum flexibility. The analog mixer is
designed to the AC'97 specification to manage the record and playback of all digital and analog
audio sources in the PC environment. The analog mixer also includes several extensions of the
AC’97 specification to support “all analog record” capability as well as “POP BYPASS” mode for all
digital playback. The analog sources include:
•
System Audio: digital PCM input and output for business, games & multimedia
•
CD/DVD: analog CD/DVD-ROM audio with internal connections to CODEC mixer
•
Stereo or Mono microphone: choice of desktop mic, with programmable boost and gain
•
Speakerphone: use of system mic and speakers for telephone, DSVD, and video conferencing
•
Video: TV tuner or video capture card with internal connections to CODEC mixer
•
AUX/synth: analog FM or wavetable synthesizer, or other internal source
•
Line in: external analog line-level source from consumer audio, video camera, etc.
Source
Function
Connection
PC_BEEP
PC BEEP pass through to LINE_OUT
from PC_BEEP output
PHONE
MONO input
from telephony subsystem
MIC1
desktop microphone
from stereo or mono mic jack
MIC2
second microphone
from stereo or second mono mic jack
LINE_IN
external audio source
from line-in jack
CD
audio from CD-ROM
cable from CD-ROM
VIDEO
audio from TV tuner or video camera
cable from TV or VidCap card
AUX
upgrade synth or other external source
internal connector
PCM out
digital audio output from AC'97 Controller
AC-Link
Destination
Function
Connection
To headphone out jack
HP_OUT
stereo mix of all sources
LINE_OUT
stereo mix of all sources
To output jack
MONO_OUT
mic or MONO Analog mixer output
to telephony subsystem
PCM in
digital data from the CODEC to the AC'97 Controller
AC-Link
SPDIF
SPDIF digital audio output
To SPDIF output connector
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6.1.1.
Mixer Functional Diagrams
Figure 21. STAC9752A/9753A 2-Channel Mixer Functional Diagram
mute
HP
28h: D5-D4
3D
20h:D13
22h:D2-D3
DA C 1
(FRONT)
02h
vol
mute
LO
78h D 3 &
20h D15
18h
vol
Mic Mux
78h D9:D 8
0Ch
L
R
R
L
R
Left C h.
M ic
V IDEO
78h D 11:D10
0Eh:D 6 &
6Eh:D 2
78h D7 &
20h D 8
-6dB

30 dB
0Eh
vol
R ig ht C h.
M ic
10h
vol
vol
18,20
16h
14,15
vol
14h
16,17
mute

20h:D 13
22h:D 2-D 3

PINS 21/22
1/2
06h
vol
mute
37
+ 0 dB
MONO_OUT
-6dB
20h:D9,D15
MUX
6Eh:D12
mute
AC Link
SD ATA_OUT
Slots 6Eh : D4-5
3&4, 7&8, 6&9, 10&11
-6dB

mute
MUX
vol
mute
-6dB

3D
mute
traditionally Line In L/R
-6dB
-6dB
12h
CD
AUX

mute
MUX
MUX MUX
L
vol
mute
PINS 23/24
MUX
vol
13
PHONE
Analog
Audio
Input
Sources
0Ah
12
LIN E_OU T
traditionally M ic
Line In Mux
Digital PCBeep
PC_BEEP
traditionally
If both are s elec ted,
HP wi ll be on and
Li ne Out is Off
23/24
78h D 13:D 12
mute
H P_OU T
PINS 35/36
35/36
MUX
Slot
Selec t
78h D 15:D 14
SEL
MUX
78h D 4 &
20h D 15
PINS 39/41
traditionally
MUX
vol
SEL
MUX
39/41
04h
1C h
vol
mute
+ 22 dB
Slot
Selec t
STEREO
A DC
PCMIn
2A h:D5-D4
6.1.2.
Slot
Select
48
SPDIF_OUT
Mixer Analog Input
The mixer provides recording and playback of any audio sources or output mix of all sources. The
STAC9752A/9753A supports the following input sources:
•
Any mono or stereo source
•
Mono or stereo mix of all sources
•
Two-channel input w/mono output reference (mic or stereo mix)
Note: All unused inputs should be tied together and connected to ground through a capacitor (0.1
mF suggested).
Note: The MIC inputs should be tied to ground through a separate capacitor (0.1 mF suggested).
6.1.3.
Mixer Analog Output
The mixer generates three distinct outputs:
6.2.
•
A stereo mix of all sources for output to the LINE_OUT
•
A stereo mix of all sources for output to HP_OUT
•
A mono, mic only or mix of all sources for MONO_OUT
SPDIF Digital Mux
The STAC9752A/9753A incorporates a digital output that supports SPDIF formats. A multiplexer
determines which of two digital input streams are used for the digital output conversion process.
These two streams include the PCM OUT data from the audio controller and the ADC recorded output. The normal analog LINE_OUT signal can be converted to the SPDIF formats by using the internal ADC to record the “MIX” output, which is the combination of all analog and all digital sources. In
the case of digital controllers with support for four or more channels, the SPDIF output mode can be
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used to support compressed 6-channel output streams for delivery to home theater systems. These
can be routed on alternate AC-Link slots to the SPDIF output, while the standard 2-channel output is
delivered as selected by bits D5 and D4 in Register 6E. If the digital controller supports six channels,
a SPDIF output with four analog channels can also be configured.
If the Digital Controller has independent DMA engines, SPDIF and Analog can be used simultaneously and independently.
6.3.
PC Beep Implementation
The STAC9752A/9753A offers two styles of PC BEEP, Analog and Digital. The digital PC BEEP is a
new feature added to the AC’97 Specification Rev 2.3. This style of PC BEEP will eventually replace
the Analog style, thus eliminating the need for a PC BEEP pin. Until this feature is widely accepted,
TSI will provide BOTH styles of PC BEEP. Both PC BEEP styles use Reg 0Ah. Additional information
about Reg0Ah can be found in Section 7.1.5: page 51.
6.3.1.
Analog PC Beep
PC Beep is active on power up and defaults to an un-muted state. The PC_BEEP input is routed
directly to the MONO_OUT, LINE_OUT and HP_OUT pins of the CODEC. Because the PC_BEEP
input drive is often a full scale digital signal, some resistive attenuation of the PC_BEEP input is recommended to keep the beep tone within reasonable volume levels. The user should mute this input
before using any other mixer input because the PC Beep input can contribute noise to the lineout
during normal operation. This style of PC BEEP is related to the AC’97 Specification Rev 2.2. To use
the analog PC BEEP, write a value of 00h to bits F[7:0](D[12:5]) to disable the Digital PC Beep generation. PV[3:0] (D[4:1]) controls the volume level from 0 to 45dB of attenuation in 3dB steps.
6.3.2.
Digital PC Beep
The Digital PC Beep uses the identical register as the Analog style, Reg 0Ah. This register controls
the level and frequency for the PC BEEP. The beep frequency is the result of dividing the 48 KHz
clock by 2 times the number specified in F[7:0] +2, allowing tones from 94 Hz to 12 KHz. A value of
00h written to bits F[7:0] disables the digital PC Beep generation and enables the analog style PC
BEEP. The volume control bits, PV[3:0] operate identically to the analog PC BEEP mode. Applying a
signal to the PC BEEP pin, pin 12, may cause the digital PC BEEP signal to become distorted or
inaudible. When using the digital PC BEEP feature, it is recommended to leave the PC BEEP input
pin unconnected or connected to analog ground through a capacitor. Connecting a capacitor from
the PC BEEP input pin to ground will create a more pleasing sound by changing the digital output to
a more sinusoidal signal.
Table 17. Digital PC Beep Examples
Value
Reg 0Ah
Frequency
1
0x01
12,000Hz
10
0x0A
1200Hz
25
0x19
480Hz
50
0x32
240Hz
100
0x64
120Hz
127
0x0F
94.48Hz
255
0xFF
47.05Hz
This will be programmed directly by the BIOS.
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7. PROGRAMMING REGISTERS
Table 18. Programming Registers
Address
Name
Default
Location
6A90h
7.1.1; page 49
00h
Reset
02h
Master Volume
8000h
7.1.2; page 49
04h
HP_OUT Mixer Volume
8000h
7.1.3; page 50
06h
Master Volume MONO
8000h
7.1.4; page 51
0Ah
PC Beep Mixer Volume
0000h
7.1.5; page 51
0Ch
Phone Mixer Volume
8008h
7.1.6; page 52
0Eh
Mic Mixer Volume
8008h
7.1.7; page 52
10h
Line In Mixer Volume
8808h
7.1.8; page 53
12h
CD Mixer Volume
8808h
7.1.9; page 54
14h
Video Mixer Volume
8808h
7.1.10; page 54
16h
Aux Mixer Volume
8808h
7.1.11; page 55
18h
PCM Out Mixer Volume
8808h
7.1.12; page 55
1Ah
Record Select
0000h
7.1.13; page 56
1Ch
Record Gain
8000h
7.1.14; page 57
20h
General Purpose
0000h
7.1.15; page 57
22h
3D Control
0000h
7.1.16; page 58
24h
Audio Int. & Paging
0000h
7.1.17: page 58
26h
Powerdown Ctrl/Stat
000Fh
7.1.18; page 59
28h
Extended Audio ID
0A05h
7.1.19; page 61
2Ah
Extended Audio Control/Status
0400h*
7.1.20; page 62
2Ch
PCM DAC Rate
BB80h
7.1.22; page 64
32h
PCM LR ADC Rate
BB80h
7.1.23; page 64
3Ah
SPDIF Control
2000h
7.1.24; page 65
3Eh
Extended Modem Stat/Ctl
0100h
7.2.4; page 66
4Ch
GPIO Pin Configuration
0003h
7.2.5; page 67
4Eh
GPIO Pin Polarity/Type
FFFFh
7.2.6; page 67
50h
GPIO Pin Sticky
0000h
7.2.7; page 67
52h
GPIO Wake-up
0000h
7.2.8; page 68
54h
GPIO Pin Status
0000h
7.2.9; page 68
60h
CODEC Class/Rev
1201h
7.3; page 68
62h (Page 01h) PCI SVID
FFFFh
7.4.2; page 70
64h (Page 01h) PCI SSID
FFFFh
7.4.3; page 70
66h (Page 01h) Function Select
0000h
7.4.4; page 71
xxxxh
7.4.5; page 72
0000h
7.4.6; page 74
68h (Page 01h) Function Information
6Ah
Digital Audio Control
6Ah (Page01h) Sense Details
6Ch
Revision Code
6Ch (Page01h) Reserved
6Eh
Analog Special
6Eh (Page01h) Reserved
NA
7.4.7: page 74
xxxxh
7.4.7; page 74
0000h
NA
1000h
7.4.9: page 76
0000h
NA
70h
Enable Register
0000h
NA
72h
Analog Current Adjust
0000h
7.4.10; page 77
74h
EAPD Access
0800h
7.4.11; page 78
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Table 18. Programming Registers
Address
Name
Default
Location
76h
Register 78h Enable
0000h
7.4.11; page 78
78h
High Pass Filter Bypass
0000h
7.4.11; page 78
7Ah
Universal Jacks™ Selection
0000h
7.4.11; page 78
7Ch
Vendor ID1
8384h
7.5.1; page 80
7Eh
Vendor ID2
7652h
7.5.2; page 80
Note: * depends upon CODECID
7.1.
Register Descriptions
7.1.1.
Reset (00h)
Default: 6A90h
D15
D14
D13
D12
D11
D10
D9
D8
RSRVD
SE4
SE3
SE2
SE1
SE0
ID9
ID8
D7
D6
D5
D4
D3
D2
D1
D0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
Writing any value to this register performs a register reset, which causes all registers to revert to
their default values. This register reset also resets all the digital block. Reading this register returns
the ID code of the part.
Bit(s)
Reset Value
Name
15
0
Reserved
Bit not used, should read back 0
14:10
11010
SE4:SE0
TSI ID for SS3D
9
1
ID9
20 Bit ADC Resolution (Supported)
8
0
ID8
18 Bit ADC Resolution
7
1
ID7
20 Bit DAC Resolution (Supported)
6
0
ID6
18 Bit DAC Resolution
5
0
ID5
Loudness (Bass Boost)
4
1
ID4
Headphone Out (Supported)
3
0
ID3
Simulated Stereo ( Mono To Stereo )
2
0
ID2
Bass & Treble Control
1
0
ID1
Reserved
0
0
ID0
Dedicated Mic PCM IN Channel
7.1.2.
Description
Master Volume Registers (02h)
Default: 8000h
D15
D14
D13
D12
D11
D10
D9
D8
Mute
RSRVD
ML5
ML4
ML3
ML2
ML1
ML0
D7
D6
D5
D4
D3
D2
D1
D0
MR5
MR4
MR3
MR2
MR1
MR0
Reserved
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Bit(s)
Reset Value
Name
15
1
Mute
14
0
Reserved
13
0
ML5
Description
0 = No mute
1 = Mutes both left & right channels
Bit not used, should read back 0
0 = Lineout attenuation is a function of bits12-8
1 = Forces register bits 12-8 to be 11111
Always reads back 0
12:8
0
ML<4:0>
Left Lineout Volume Control
00000 = 0dB attenuation
00001 = 1.5dB attenuation
.....
11111 = 46.5dB attenuation
7:6
0
Reserved
Bits not used, should read back 0
5
0
MR5
4:0
7.1.3.
0
MR<4:0>
0 = Lineout attenuation is a function of bits 4-0
1 = Forces register bits 4-0 to be 11111
Always reads back 0
Right Channel Lineout Volume Control
00000 = 0dB attenuation
00001 = 1.5dB attenuation
.....
11111 = 46.5dB attenuation
Headphone Volume Registers (04h)
Default: 8000h
D15
D14
D13
D12
D11
D10
D9
D8
Mute
RSRVD
HPL5
HPL4
HPL3
HPL2
HPL1
HPL0
D7
D6
D5
D4
D3
D2
D1
D0
HPR5
HPR4
HPR3
HPR2
HPR1
HPR0
Reserved
Bit(s)
Reset Value
Name
15
1
Mute
14
0
Reserved
13
0
ML5
Description
0 = No mute
1 = Mutes both left & right channels
Bit not used, should read back 0
0 = Headphone attenuation is a function of bits12-8
1 = Forces register bits 12-8 to be 11111
Always reads back 0
12:8
0
ML<4:0>
Left Headphone Volume Control
00000 = 0dB attenuation
00001 = 1.5dB attenuation
.....
11111 = 46.5dB attenuation
7:6
0
Reserved
Bits not used, should read back 0
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Bit(s)
Reset Value
Name
5
0
MR5
4:0
7.1.4.
0
MR<4:0>
Description
0 = Headphone attenuation is a function of bits 4-0
1 = Forces register bits 4-0 to be 11111
Always reads back 0
Right Channel Headphone Volume Control
00000 = 0dB attenuation
00001 = 1.5dB attenuation
.....
11111 = 46.5dB attenuation
Master Volume MONO (06h)
Default: 8000h
D15
D14
D13
D12
Mute
D7
D6
Reserved
D9
D8
D5
D4
D3
D2
D1
D0
MM4
MM3
MM2
MM1
MM0
Reset Value
Name
15
1
Mute
14:6
0
Reserved
5
0
MM5
7.1.5.
D10
MM5
Bit(s)
4:0
D11
Reserved
0
MM<4:0>
Description
0 = no mute
1 = mute mono
Bit not used, should read back 0
0 = Mono attenuation is a function of bits 4-0
1 = Forces register bits 4-0 to be 11111
Always reads back 0
Mono Volume Control
00000 = 0dB attenuation
00001 = 1.5dB attenuation
.....
11111 = 46.5dB attenuation
PC BEEP Volume (0Ah)
Default: 0000h
Additional information on the PC Beep can be found in Section 6.3: page 47.
D15
D14
Mute
D13
Reserved
D12
D11
D10
D9
D8
F7
F6
F5
F4
F3
D7
D6
D5
D4
D3
D2
D1
D0
F2
F1
F0
PV3
PV2
PV1
PV0
RSRVD
Bit(s)
Reset Value
Name
15
1
Mute
14:13
0
Reserved
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
Description
0 = No mute
1 = Mute PC BEEP
Bit not used, should read back 0
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Bit(s)
Reset Value
Name
Description
The Beep frequency is the result of dividing the 48KHz clock by 4 times
the number specified in F[7:0] allowing tones from 47Hz to 12KHz.
12:5
00h
F[7:0]
A value of 00h in bits F[7:0] disables internal PC BEEP generation and
enables external PC BEEP input if available.
4:1
0
PV(3:0)
0
0
Reserved
7.1.6.
PCBEEP Volume Control
0000 = 0dB attenuation
0001 = 3dB attenuation
.....
1111 = 45dB attenuation
Bit not used, should read back 0
Phone Volume (Index 0Ch)
Default: 8008h.
D15
D14
D13
D12
D6
D5
D4
GN4
Mute
D11
D10
D9
D8
D3
D2
D1
D0
GN3
GN2
GN1
GN0
D10
D9
D8
Reserved
D7
Reserved
Bit(s)
Reset Value
Name
15
1
Mute
14:5
0
Reserved
Bit not used, should read back 0
GN<4:0>
Phone Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 =
0dB gain
.....
11111 = -34.5dB gain
4:0
7.1.7.
0
Description
0 = No mute
1 = Mute phone
Stereo or Mic Volume (Index 0Eh)
To enable Stereo Mic, Register 78h (unlocked), bit D6 must be enabled.
In Stereo mode, the left and right volume is controlled by GN4:GN0.
Default: 8008h.
D15
D14
D13
D12
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
BOOSTEN
Reserved
GN4
GN3
GN2
GN1
GN0
Mute
D11
Reserved
Bit(s)
Reset Value
Name
15
1
Mute
14:7
0
Reserved
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
Description
0 = no mute
1 = mute phone
Bit not used, should read back 0
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Bit(s)
Reset Value
Name
6
0
BOOSTEN
5
0
Reserved
4:0
7.1.8.
0
GN<4:0>
Description
Works with MICGAINVAL (Register 6Eh Bit D2)
BOOSTEN
MICGAINVAL
=
Mic Gain Boost
0
0
=
0 dB
0
1
=
10 dB
1
0
=
20 dB
1
1
=
30 dB
Phone Volume Control
00000 =
12dB gain
00001 = 10.5dB gain
.....
01000 =
0dB gain
.....
11111 = -34.5dB gain
LineIn Volume (Index 10h)
Default: 8808h.
D15
D14
Mute
D13
Reserved
D7
D6
D5
Reserved
D12
D11
D10
D9
D8
GL4
GL3
GL2
GL1
GR0
D4
D3
D2
D1
D0
GR4
GR3
GR2
GR1
GR0
Bit(s)
Reset Value
Name
Description
15
1
Mute
14:13
0
Reserved
Bit not used, should read back 0
0 = no mute
1 = mute linein
12:8
0
GL<4:0>
Left LineIn Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 =
0dB gain
.....
11111 = -34.5dB gain
7:5
0
Reserved
Bit not used, should read back 0
GR<4:0>
Right LineIn Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
4:0
0
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7.1.9.
CD Volume (Index 12h)
Default: 8808h.
D15
D14
Mute
D13
Reserved
D7
D6
D5
Reserved
D12
D11
D10
D9
D8
GL4
GL3
GL2
GL1
GR0
D4
D3
D2
D1
D0
GR4
GR3
GR2
GR1
GR0
Bit(s)
Reset Value
Name
Description
15
1
Mute
14:13
0
Reserved
Bit not used, should read back 0
0 = no mute
1 = mute CD
12:8
0
GL<4:0>
Left CD Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 =
0dB gain
.....
11111 = -34.5dB gain
7:5
0
Reserved
Bit not used, should read back 0
GR<4:0>
right CD Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 =
0dB gain
.....
11111 = -34.5dB gain
4:0
0
7.1.10.
Video Volume (Index 14h)
Default: 8808h.
D15
D14
Mute
D13
Reserved
D7
D6
D5
Reserved
D12
D11
D10
D9
D8
GL4
GL3
GL2
GL1
GR0
D4
D3
D2
D1
D0
GR4
GR3
GR2
GR1
GR0
Bit(s)
Reset Value
Name
15
1
Mute
14:13
0
Reserved
Bit not used, should read back 0
GL<4:0>
Left Video Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
12:8
0
TSI™ CONFIDENTIAL
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Description
0 = no mute
1 = mute video
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Bit(s)
Reset Value
Name
7:5
0
Reserved
Bit not used, should read back 0
GR<4:0>
Right video Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
4:0
7.1.11.
0
Description
Aux Volume (Index 16h)
Default: 8808h.
D15
D14
Mute
D13
Reserved
D7
D6
D5
Reserved
D12
D11
D10
D9
D8
GL4
GL3
GL2
GL1
GR0
D4
D3
D2
D1
D0
GR4
GR3
GR2
GR1
GR0
Bit(s)
Reset Value
Name
Description
15
1
Mute
14:13
0
Reserved
Bit not used, should read back 0
0 = no mute
1 = mute aux
12:8
0
GL<4:0>
Left Aux Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
7:5
0
Reserved
Bit not used, should read back 0
GR<4:0>
Right Aux Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
4:0
7.1.12.
0
PCMOut Volume (Index 18h)
Default: 8808h.
D15
D14
Mute
D13
Reserved
D7
D6
D5
Reserved
Bit(s)
Reset Value
Name
15
1
Mute
14:13
0
Reserved
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D12
D11
D10
D9
D8
GL4
GL3
GL2
GL1
GR0
D4
D3
D2
D1
D0
GR4
GR3
GR2
GR1
GR0
Description
0 = no mute
1 = mute PCM out
Bit not used, should read back 0
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Bit(s)
Reset Value
Name
Description
12:8
0
GL<4:0>
Left PCM Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
7:5
0
Reserved
Bit not used, should read back 0
GR<4:0>
Right PCM Volume Control
00000 = 12dB gain
00001 = 10.5dB gain
.....
01000 = 0dB gain
.....
11111 = -34.5dB gain
4:0
7.1.13.
0
Record Select (1Ah)
Default: 0000h (corresponding to Mic in)
Used to select the record source independently for right and left.
D15
D14
D7
D6
D13
D12
D11
D4
D3
Reserved
D5
Reserved
Bit(s)
Reset Value
Name
15:11
0
Reserved
Bits not used, should read back 0
10:8
0
SL2:SL0
7:3
0
Reserved
Bits not used, should read back 0
SR2:SR0
Right Channel Input Select
000 = Mic
001 = CD In (right)
010 = Video In (right)
011 = Aux In (right)
100 = Line In (right)
101 = Stereo Mix (right)
110 = Mono Mix
111 = Phone
0
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D9
D8
SL2
SL1
SL0
D2
D1
D0
SR2
SR1
SR0
Description
Left Channel Input Select
000 = Mic
001 = CD In (left)
010 = Video In (left)
011 = Aux In (left)
100 = Line In (left)
101 = Stereo Mix (left)
110 = Mono Mix
111 = Phone
2:0
D10
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7.1.14.
Record Gain (1Ch)
Default: 8000h (corresponding to 0 dB gain with mute on)
D15
D14
D13
Mute
D12
Reserved
D7
D6
D5
D4
Reserved
D11
D10
D9
D8
GL3
GL2
GL1
GL0
D3
D2
D1
D0
GR3
GR2
GR1
GR0
Bit(s)
Reset Value
Name
Description
15
1
MUTE
14:12
0
Reserved
Bits not used, should read back 0
MUTES RECORD GAIN
11:8
0
GL<3:0>
Left Channel Volume Control
0000 = 0dB gain
0001 = 1.5dB gain
....
1111 = 22.5dB gain
7:4
0
Reserved
Bits not used, should read back 0
GR<3:0>
Right Channel Volume Control
0000 = 0dB gain
0001 = 1.5dB gain
....
1111 = 22.5dB gain
3:0
7.1.15.
0
General Purpose (20h)
Default: 0000h
D15
D14
D13
POP BYP
Reserved
3D
D7
D6
D5
D12
D11
D10
Reserved
D4
LOOPBACK
D3
D2
D9
D8
MIX
MS
D1
D0
Reserved
Bit(s)
Reset Value
Name
15
0
POP BYPASS
14
0
Reserved
13
0
3D
12:10
0
Reserved
9
0
MIX
8
0
MS
7
0
LOOPBACK
6:0
0
Reserved
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Description
0 = Normal
1 = DAC bypasses mixer and connects directly to Line Out, Headphone
Out and Mono Out.
Bit not used, should read back 0
0 = 3D effect disabled
1 = 3D effect enabled
Bit not used, should read back 0
Mono Output select (0 = Mix, 1 = Mic)
Mic select (0 = Mic1, 1 = Mic2)
1 = Enables ADC to DAC Loop Back Test
0 = Loopback Disabled
Do not send in conflicting data on AC-Link while running this.
Bit not used, should read back 0
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7.1.16.
3D Control (22h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D3
D2
D1
DP3
DP2
D8
Reserved
D7
D6
D5
D4
Reserved
Bit(s)
Reset Value
Name
15:4
0
Reserved
Bits not used, should read back 0
D0
Reserved
Description
3:2
0
DP3,DP2
LINE_OUT SEPARATION RATIO
DP3 DP2 effect
0
0
0 ( OFF )
0
1
3 ( LOW )
1
0
4.5 ( MED )
1
1
6 ( HIGH )
1:0
0
Reserved
Bits not used, should read back 0
This register is used to control the 3D stereo enhancement function, TSI Surround 3D (SS3D), built
into the AC'97 component. Note that register bits DP3-DP2 are used to control the separation ratios
in the 3D control for LINE_OUT. SS3D provides for a wider soundstage, extending beyond the normal 2-speaker arrangement. Note that the 3D bit in the general purpose register (20h) must be set to
1 to enable SS3D functionality, which allow the bits in register 22h to take effect.
The three separation ratios are implemented. The separation ratio defines a series of equations that
determine the amount of depth difference (High, Medium and Low) perceived during two-channel
playback. The ratios provide for options to narrow or widen the soundstage.
7.1.17.
Audio Interrupt and Paging (24h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
PG3
PG2
PG1
PG0
Reserved
Bit(s) Reset Value
15
14-13
0
0
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Access
Read / Write
Read Only
Name
Reserved
Description
I4
0 = Interrupt is clear
1 = interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink
will follow this bit change when interrupt enable (I0) is unmasked.
I3-I2
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been
confirmed as interrupting. The information should be used to scan
possible interrupting events in proper pages.
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Bit(s) Reset Value
12
0
Access
Name
Read / Write
Description
I1
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If
sense cycle is not supported this bit is read only.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the
AC‘97 controller that no conflict is possible with modem slot 12 GPI functionality. Some AC’97 2.2 compliant controllers will not
likely support audio CODEC interrupt infrastructure. In either case,
Software should poll the interrupt status after initiating a sense
cycle and wait for Sense Cycle Max Delay to determine if an
interrupting event has occurred.
11
0
Read / Write
I0
10:4
0
Read Only
Reserved
Bits not used, should read back 0
PG3:PG0
Page Selector
0h = Vendor Specific
1h = Page ID 01 (See Section 7.4 for additional information on the
Paging Registers)
.........
Fh = Reserved Pages
This register is used to select a descriptor of 16 word pages
between registers 60h to 6Fh. Value 0h is used to select vendor
specific space to maintain compatibility with AC’97 2.2 vendor
specific registers.
System Software determines implemented pages by writing the
page number and reading the value back. All implemented pages
must be consecutive. (i.e., page 2h cannot be implemented without
page 1h).
These registers are not reset on RESET#.
3:0
0
7.1.18.
Read / Write
Powerdown Ctrl/Stat (26h)
Default: 000Fh
D15
D14
D13
D12
D11
D10
D9
D8
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
D7
D6
D5
D4
D3
D2
D1
D0
REF
ANL
DAC
ADC
Reserved
Bit(s)
Reset Value
Name
15
0
EAPD
14
0
PR6
0 = Headphone Amp powered up
1 = Headphone Amp powered down
13
0
PR5
0 = Digital Clk active
1 = Digital Clk disable.
12
0
PR4
0 = Digital active
1 = Powerdown: PLL, AC-Link, Xtal oscillator;
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Description
1 = Forces EAPD pad to Vdd
0 = Forces EAPD pad to GND
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Bit(s)
Reset Value
Name
11
0
PR3
0 = VREF and VREFOUT are active
1 = VREF and VREFOUT are powered down, and PR2 is asserted in
analog block
10
0
PR2
0 = Analog active
1 = All signal path analog is powered down
9
0
PR1
0 = DAC powered up
1 = DAC powered down
8
0
PR0
0 = ADC powered up
1 = ADC powered down
7:4
0
Reserved
3
1
REF
Read Only --- VREF status
1 = VREF’S enabled
2
1
ANL
Read Only ---- ANALOG MIXERS, etc. Status
1 = analog mixers ready.
1
1
DAC
Read Only ---- DAC Status
1 = DAC ready to playback
0
1
ADC
Read Only ---- ADC Status
1 = ADC ready to record
7.1.18.1.
Description
Bit not used, should read back 0
Ready Status
The lower half of this register is read only status, a 1 indicating that each subsection is ready. Ready
is defined as the subsection's ability to perform in its nominal state. When this register is written, the
bit values that come in on AC-Link will have no effect on read-only bits 0-7.
When the AC-Link “CODEC Ready” indicator bit (SDATA_IN slot 0, bit 15) is a 1, it indicates that the
AC-Link and AC'97 control and status registers are in a fully operational state. The AC'97 controller
must further probe this Powerdown Control/Status Register to determine exactly which subsections,
if any, are ready. When this register is written, the bit values that come in on AC-Link will have no
effect on read-only bits 0-7.
7.1.18.2.
Powerdown Controls
The STAC9752A/9753A is capable of operating at reduced power when no activity is required. The
power-down state is controlled by the Powerdown Register (26h). See the section “Low Power
Modes” for more information.
7.1.18.3.
External Amplifier Power Down Control Output
The EAPD bit (bit 15 of the Powerdown Control/Status Register (Index 26h)), directly controls the
EAPD output, pin 45, and produces a logical 1 when this bit is set to logic high. This function is used
to control an external audio amplifier power-down. EAPD = 0 places approximately 0V on the output
pin, enabling an external audio amplifier. EAPD = 1 places approximately DVdd on the output pin,
disabling the external audio amplifier. Audio amplifiers that operate with reverse polarity will likely
require an external inverter to maintain software driver compatibility.
EAPD can also act as a GPIO. See Section 7.4.11: page 78. The GPIO controls in Section 7.2:
page 65 have no effect on EAPD.
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7.1.19.
Extended Audio ID (28h)
Default: 0A05h
D15
D14
ID1
ID0
D7
D6
Reserved
D13
D12
D11
D10
Reserved
D9
D8
AMAP
RSVD
D5
D4
D3
D2
D1
D0
DSA1
DSA0
RESVD
SPDIF
RSVD
VRA
The Extended Audio ID register is a read-only register except for bits D4 and D5. ID1 and ID0 echo
the configuration of the CODEC as defined by the programming of pins 45 and 46 externally. “00”
returned defines the CODEC as the primary CODEC, while any other code identifies the CODEC as
one of three secondary CODECs. The AMAP bit, D9, will return a 1 indicating that the CODEC supports the optional “AC’97 2.3 Compliant AC-Link Slot to Audio DAC Mappings”. The default condition
assumes that 00 is loaded in the DSA0 and DSA1 bits of the Extended Audio ID (Index 28h). With 00
in the DSA1 and DSA0 bits, the CODEC slot assignments are as per the AC’97 specification recommendations. If the DSA1 and DSA0 bits do not contain 00, the slot assignments are as per the table
in the section describing the Extended Audio ID (Index 28h). The VRA bit, D0, will return a 1 indicating that the CODEC supports the optional variable sample rate conversion as defined by the AC’97
specification.
Table 19. Extended Audio ID Register Functions
Bit
Name
Access
Reset Value
Function
00 = XTAL_OUT grounded (Note Note:)
CID1#,CID0# = XTAL_OUT crystal or floating
15:14
ID [1,0]
Read only
variable
13:12
Reserved
Read only
00
Bits not used, should read back 00
11:10
REV[1:0]
Read only
10
Indicates CODEC is AC’97 Rev 2.3 compliant
9:6
RSVD
Read only
0
Reserved
DAC slot assignment
5:4
DSA [1,0]
Read/Write
00
If CID[1:0] = 00 then DSA[1:0] resets to 00
If CID[1:0] = 01 then DSA[1:0] resets to 01
If CID[1:0] = 10 then DSA[1:0] resets to 01
If CID[1:0] = 11 then DSA[1:0] resets to 10
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
3
RSVD
Read only
0
Reserved
2
SPDIF
Read only
1
0 = SPDIF pulled high on reset, SPDIF disabled
1 = default, SPDIF enabled (Note Note:)
1
RSVD
Read only
0
Reserved
0
VRA
Read only
1
Variable sample rates supported (Always = 1)
Note: 1) External CID pin status (from analog), these bits are the logical inversion of the pin
polarity (pin 45-46). These bits are zero if XTAL_OUT is grounded with an alternate external clock
source (in primary mode only). Secondary mode can either be through BIT CLK driven or 24 MHz
clock driver, with XTAL_OUT floating.
Note: 2) If pin 48 is held high at powerup, this bit will be held to zero, to indicate the SPDIF is not
available. TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
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7.1.20.
Extended Audio Control/Status (2Ah)
Default: 0400h* (*default depends on CODEC ID)
D15
D14
D13
VCFG
D12
D11
Reserved
D7
D6
Reserved
Bit(s) Reset Value
D10
D9
SPCV
D8
Reserved
D5
D4
D3
D2
D1
D0
SPSA1
SPSA0
RSRVD
SPDIF
RSRVD
VRA enable
Name
Description
15
VCFG
Determines the SPDIF transmitter behavior when data is not being
transmitted. When asserted, this bit forces the deassertion of the SPDIF
“Validity” flag, which is bit 28 transmitted by the SPDIF sub-frame. The “V” bit
is defined in the SPDIF Control Register (Reg 3Ah).
If “V” = 1 and “VCFG” = 0, then for each S/PDIF sub-frame (Left & Right),
bit<28> “Validity” flag reflects whether or not an internal CODEC transmission
error has occurred. Specifically an internal CODEC error should result in the
“Validity” flag being set to 1.
If “V” = 0 and “VCFG” = 1, In the case where the S/PDIF transmitter does not
receive a valid sample from the AC'97 controller, (Left or Right), the S/PDIF
transmitter should set the “Validity” flag to 0 and pad the “Audio Sample Word”
with 0s for sub-frame in question. If a valid sample (Left or Right) was
received and successfully transmitted, the “Validity” flag should be 0 for that
sub-frame.
Default state, coming out of reset, for “V” and “VCFG” should be 0 and 0.
These bits are set-able via driver .inf options.
14-11
Reserved
Reserved
10
0
SPCV
0 = invalid SPDIF configuration
1 = valid SPDIF configuration
9:6
0
Reserved
Bit not used, should read back 0
SPDIF slot assignment
5:4
0
If CID[1:0] = 00 then SPSA[1:0] resets to 01
If CID[1:0] = 01 then SPSA[1:0] resets to 10
If CID[1:0] = 10 then SPSA[1:0] resets to 10
SPSA1:SPSA0 If CID[1:0] = 11 then SPSA[1:0] resets to 11
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
3
Reserved
2
0
SPDIF
1
0
Reserved
0
0
VRA Enable
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Reserved
0 = disables SPDIF (SPDIF_OUT is high-Z ) (Note 1)
1 = enable SPDIF
SPDIF is a control register for Reg 3Ah, this bit must be set low (i.e. SPDIF
disabled) in order to write to Reg 3Ah Bits D15, D13:D0.
Bit not used, should read back 0
0 = VRA disabled, DAC and ADC set to 48 KHz (Registers 2Ch and 32h
loaded with the value BB80h)
1 = VRA enabled, Reg. 2Ch & 32h control sample rate
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7.1.20.1.
Variable Rate Sampling Enable
The Extended Audio Status Control register also contains one active bit to enable or disable the Variable Sampling Rate capabilities of the DACs and ADCs. If the VRA bit D0 is 1, the variable sample
rate control registers (2Ch and 32h) are active, and “on-demand” slot data required transfers are
allowed. If the VRA bit is 0, the DACs and ADCs will operate at the default 48 KHz data rate.
The STAC9752A/9753A supports “on-demand” slot request flags. These flags are passed from the
CODEC to the AC’97 controller in every audio input frame. Each time a slot request flag is set (active
low) in a given audio frame, the controller will pass the next PCM sample for the corresponding slot
in the audio frame that immediately follows. The VRA enable bit must be set to 1 to enable
“on-demand” data transfers. If the VRA enable bit is not set, the CODEC will default to 48 KHz transfers and every audio frame will include an active slot request flag and data is transferred every
frame.
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
the FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each audio output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits are asserted during the current
audio input frame for active output slots, which will require data in the next audio output frame.
For variable sample rate input, the tag bit for each input slot indicates whether valid data is present
or not. Thus, even in variable sample rate mode, the CODEC is always the master: for SDATA_IN
(CODEC to controller), the CODEC sets the TAG bit; for SDATA_OUT (controller to CODEC), the
CODEC sets the SLOTREQ bit and then checks for the TAG bit in the next frame. Whenever VRA is
set to 0, the PCM rate registers (2Ch and 32h) are overwritten with BB80h (48 KHz).
7.1.20.2.
SPDIF
The SPDIF bit in the Extended Audio Status Control Register is used to enable and disable the
SPDIF functionality within the STAC9752A/9753A. If the SPDIF is set to a 1, then the function is
enabled. When set to a 0, it is disabled.
7.1.20.3.
SPCV (SPDIF Configuration Valid)
The SPCV bit is read only and indicates whether or not the SPDIF system is set up correctly. When
SPCV is a 0, it indicates the system configuration is invalid. When SPCV is a 1, it indicates the system configuration is valid.
7.1.20.4.
SPSA1, SPSA0 (SPDIF Slot Assignment)
SPSA1 and SPSA0 combine to provide the slot assignments for the SPDIF data. The following
details the slot assignment relationship between SPSA1 and SPSA0.
The STAC9752A/9753A are AMAP compliant with the following table.
Table 20. AMAP compliant
CODEC
ID
00
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Function
2-ch Primary with
SPDIF
SPSA = 00
SPSA = 01
SPSA = 10
SPSA = 11
Slot Assignment Slot Assignment Slot Assignment Slot Assignment
3&4
63
7&8*
6&9
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Table 20. AMAP compliant
01
2-ch Dock CODEC
with SPDIF
3&4
7&8
6&9*
10 & 11
10
+2-ch Surr w/ SPDIF
3&4
7&8
6&9*
10 & 11
11
+2-ch Cntr/LFE with
SPDIF
3&4
7&8
6&9
10 & 11 *
Note:* is the default slot assignment
7.1.21.
PCM DAC Rate Registers (2Ch and 32h)
The internal sample rate for the DACs and ADCs are controlled by the value in these read/write registers that contain a 16-bit unsigned value between 0 and 65535 representing the conversion rate in
Hertz (Hz). In VRA mode (register 2Ah, bit D0 = 1), if the value written to these registers is supported, that value will be echoed back when read, otherwise the closest (higher in the case of a tie)
sample rate is supported and returned. Per PC 99 / PC 2001 specification, independent sample
rates are supported for record and playback.
Whenever VRA is set to 0 the PCM rate registers (2Ch and 32h) will be loaded with BB80h (48 KHz).
If VRA is set to a 0, any write to this address will be ignored and the rate remains at 48KHz.
Table 21. Hardware Supported Sample Rates
7.1.22.
Sample Rate
SR15-SR0 Value
8 KHz
1F40h
11.025 KHz
2B11h
16 KHz
3E80h
22.05 KHz
5622h
32 KHz
7D00h
44.1 KHz
AC44h
48 KHz
BB80h
PCM DAC Rate (2Ch)
Default: BB80h (see table 21: page 64)
7.1.23.
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
PCM LR ADC Rate (32h)
Default: BB80h (see table 21: page 64)
D15
D14
D13
D12
D11
D10
D9
D8
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
D7
D6
D5
D4
D3
D2
D1
D0
SR7
SR6
SR5
SR4
SR3
SR2
SR1
SR0
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7.1.24.
SPDIF Control (3Ah)
Default: 2000h
D15
D14
D13
D12
D11
D10
D9
D8
V
DRS
SPSR1
SPSR2
L
CC6
CC5
CC4
D7
D6
D5
D4
D3
D2
D1
D0
CC3
CC2
CC1
CC0
PRE
COPY
/AUDIO
PRO
Bit(s)
Reset Value
Access
Name
Description (note 1-2)
V
Validity: This bit affects the "Validity" flag, bit<28>, transmitted in
each S/PDIF subframe, and enables the S/PDIF transmitter to
maintain connection during error or mute conditions. Subframe
bit<28> = 0 indicates that data is valid for conversion at the
receiver, 1 indicates invalid data (not suitable for conversion at
the receiver).
15 in 2.3
If “V” = 1, then each S/PDIF subframe (Left & Right) should have
bit<28> “Validity” flag = 1 or set based on the assertion or
de-assertion of the AC '97 “VFORCE” bit within the Extended
Audio Status and Control Register (D15, register 2Ah).
14
7.2.
0
Read Only
DRS
1 = Double Rate SPDIF support (always = 0)
13:12
10
SPDIF Sample Rate.
00 - 44.1 KHz Rate
Read & Write SPSR[1,0] 01 - Reserved
10 - 48 KHz Rate (default)
11 - 32 KHz Rate
11
0
Read & Write
L
10:4
0
Read & Write
CC[6, 0]
3
0
Read & Write
PRE
2
0
Read & Write
COPY
1
0
Read & Write
/AUDIO
0 = PCM data
1 = Non-Audio or non-PCM format
0
0
Read & Write
PRO
0 = Consumer use of the channel
1 = Professional use of the channel
Generation Level is defined by the IEC standard, or as
appropriate.
Category Code is defined by the IEC standard or as appropriate
by media.
0 = 0 sec Pre-emphasis
1 = Pre-emphasis is 50/15 sec
0 = Copyright not asserted
1 = Copyright is asserted
General Purpose Input & Outputs
7.2.1.
EAPD
EAPD can act as a GPIO, but is unaffected by the following registers. To use EAPD as a GPIO, use
Register 74h, the EAPD Access Register. Information about this register is located in Section
7.4.11: page 78. Additional information about EAPD can also be found in Section 7.1.18.3:
page 60.
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7.2.2.
GPIO Pin Definitions
GPIO pins are programmable to have input/output functionality. The data values (status) for these
pins are all in one register with input/output configuration in a separate register. Control of GPIO pins
configured for output is achieved by setting the corresponding bit in output slot 12; status of GPIO
pins configured for input is returned on input slot 12. The CODEC must constantly set the GPIO pins
that are configured for output, based upon the value of the corresponding bit position of the control
slot 12. The CODEC should ignore output slot 12 bits that correspond to GPIO control pins configured as inputs. The CODEC must constantly update status on input slot 12, based upon the logic
level detected at each GPIO pin configured for input. A GPIO output pin value that is written via slot
12 in the current frame won’t affect the GPIO status that is returned in that particular write frame.
This slot-12 based control/status protocol minimizes the latency and complexity, especially for
host-based Controllers and host data pump software, and provides high speed monitoring and control, above what could be achieved with command/status slots. For host-based implementations,
most AC‘97 registers can be shadowed by the driver in order to provide immediate response when
read by the processor, and GPIO pins configured as inputs should be capable of triggering an interrupt upon a change of status.
The AC-Link request for GPIO pin status is always delayed by at least one frame time. Read-Modify-Writes across the AC-Link will thus incur latency issues and must be accounted for by the software driver or AC‘97 Digital Controller firmware. PCI re-tries should be kept to a minimum wherever
possible.
7.2.3.
GPIO Pin Implementation
The GPIOs are set to a high impedance state on power-on or a cold reset. It is up to the AC‘97 Digital Controller to first enable the output after setting it to the desired state.
7.2.4.
Extended Modem Status and Control Register (3Eh)
Default: 0100h
D15
D14
D13
D7
D6
D5
D12
D11
D10
D9
D3
D2
D1
PRA
Reserved
D4
Reserved
Bit(s)
Access
Reset Value
Name
15:9
Read Only
0
Reserved
8
Read / Write
1
PRA
7:1
Read Only
0
Reserved
0
Read Only
0
GPIO
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D8
D0
GPIO
Description
Bit not used, should read back 0
0 = GPIO powered up / enabled
1 = GPIO powered down / disabled
Bit not used, should read back 0
0 = GPIO not ready (powered down)
1 = GPIO ready (powered up)
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7.2.5.
GPIO Pin Configuration Register (4Ch)
Default: 0003h
D15
D14
D13
D12
D11
D10
D3
D2
D9
D8
Reserved
D7
D6
D5
D4
Reserved
D1
D0
GC1
(GPIO1)
GC0
(GPIO0)
Bit(s)
Access
Reset Value
Name
15:2
Read Only
0
Reserved
Bit not used, should read back 0
1
Read / Write
1
GC1
0 = GPIO1 configured as output
1 = GPIO1 configured as input
0
Read / Write
1
GC0
0 = GPIO0 configured as output
1 = GPIO0 configured as input
7.2.6.
Description
GPIO Pin Polarity/Type Register (4Eh)
Default: FFFFh
D15
D14
D13
D12
D11
D10
D3
D2
D9
D8
Reserved
D7
D6
D5
D4
Reserved
D0
GP0
(GPIO0)
Bit(s)
Access
Reset Value
15:2
Read Only
0
1
Read / Write
1
GP1
0 = GPIO1 Input Polarity Inverted, CMOS output drive.
1 = GPIO1 Input Polarity Non-inverted, Open-Drain output drive.
0
Read / Write
1
GP0
0 = GPIO0 Input Polarity Inverted, CMOS output drive.
1 = GPIO0 Input Polarity Non-inverted, Open-Drain output drive.
7.2.7.
Name
D1
GP1
(GPIO1)
Description
Reserved Bit not used, should read back 0
GPIO Pin Sticky Register (50h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
Reserved
D7
D6
D5
D4
Reserved
D3
D2
GS1 (GPIO1) GS0 (GPIO0)
Bit(s)
Access
Reset Value
Name
15:2
Read Only
0
Reserved
1
Read / Write
0
GS1
0 = GPIO1 Non Sticky configuration.
1 = GPIO1 Sticky configuration.
0
Read / Write
0
GS0
0 = GPIO0 Non Sticky configuration.
1 = GPIO0 Sticky configuration.
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Description
Bit not used, should read back 0
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7.2.8.
GPIO Pin Mask Register (52h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
D1
D0
Reserved
D7
D6
D5
D4
D3
D2
Reserved
GW1 (GPIO1) GW0 (GPIO0)
Bit(s)
Access
Reset Value
Name
15:2
Read Only
0
Reserved
1
Read / Write
0
GW1
0 = GPIO1 interrupt not passed to GPIO_INT slot 12.
1 = GPIO1 interrupt is passed to GPIO_INT slot 12.
0
Read / Write
0
GW0
0 = GPIO0 interrupt not passed to GPIO_INT slot 12.
1 = GPIO0 interrupt is passed to GPIO_INT slot 12.
7.2.9.
Description
Bit not used, should read back 0
GPIO Pin Status Register (54h)
Default: 0000h
D15
D14
D13
D12
D7
D6
D5
D4
D11
D10
D9
D8
Reserved
D3
D2
Reserved
Bit(s)
Access
15:2 Read Only
1
0
7.3.
Read /
Write
Read /
Write
Reset
Name
Value
0
x
x
D1
D0
GI1 (GPIO1)
GI0 (GPIO0)
Description
Rsvd Bit not used, should read back 0
GI1
When GPIO1 is configured as output and Register h74 bit[0] = 0 (default), the
value of this register will be placed on the GPIO1 pad.
When GPIO1 is configured as output and Register h74 bit[0] = 1, the GPIO1 pad
will get its value from slot12.
When GPIO1 is configured as input and configured as a sticky writing a 1 does
nothing, writing a 0 clears this bit.
When GPIO1 is configured as input this register reflects the value on the GPIO1
pad after interpretation of the polarity and sticky configurations.
GI0
When GPIO0 is configured as output and Register h74 bit[0] = 0 (default), the
value of this register will be placed on the GPIO0 pad.
When GPIO0 is configured as output and Register h74 bit[0] = 1, the GPIO0 pad
will get its value from slot12.
When GPIO0 is configured as input and configured as a sticky writing a 1 does
nothing, writing a 0 clears this bit.
When GPIO0 is configured as input this register reflects the value on the GPIO0
pad after interpretation of the polarity and sticky configurations.
Extended CODEC Registers Page Structure Definition
Registers 60h-68h are the Extended CODEC Registers: These registers allow for the definition of
further capabilities. These bits provide a paged address space for extended CODEC information.
The Page Selector bits in the Audio Interrupt and Paging register (Register 24h bits 3:0) control the
page of information viewed through this page window.
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7.3.1.
Extended Registers Page 00
Page 00 of the Extended CODEC Registers is reserved for vendor specific use. Driver writers should
not access these registers unless the Vendor ID register has been checked first to ensure that the
vendor of the AC '97 component has been identified and the usage of the vendor defined registers
understood.
7.3.2.
Extended Registers Page 01
The usage of Page 01 of the Extended CODEC Registers is defined in Register 24h found in
Section 7.1.17: page 58.
7.3.3.
Extended Registers Page 02, 03
Pages 02 and 03 of the Extended CODEC Registers are reserved for future use.
7.4.
STAC9752A/9753A Paging Registers
The AC’97 Specification Rev 2.3 uses a paging mechanism in order to increase the number of registers. The registers currently used in the paging are 60h to 6Eh. Additional information about the
Extended CODEC Registers, please refer to Section 7.3: page 68.
One of two pages can be made active at any time, set in Register 24h. Register 24h is the Audio
Interrupt and Paging Register. Additional details about Register 24h is located in Section 7.1.17:
page 58.
If page 00h is active, registers 60h to 6Eh are Vendor Specific.
If page 01h is active, registers 60h to 6Eh have the following functionality:
Reg
NAME
60h CODEC Class/Revision
FUNCTION
Location
Provides the CODEC Class and a Vendor specified revision
identifier.
7.4.1: page 69
62h
PCI SVID
Allows for population by the system BIOS to identify the PCI Sub
System Vendor ID.
7.4.2: page 70
64h
PCI SSID
Allows for population by the system BIOS to identify the PCI Sub
System ID.
Note:: page 70
66h
Function Select
Provides the type of audio function being selected and which jack
conductor the selected value is measured from.
Note:: page 71
68h
Function Information
Includes information about Gain, Inversion, Buffer delays,
Information Validity, and Function Information presence.
7.4.5: page 72
6Ah
Sense Register
Includes information about the connector/jack location, Input verses
Output sensing, the Order of the sense results, and the TSI specific
sense results.
7.4.7: page 74
6Ch
Reserved
6Eh
Reserved
7.4.1.
CODEC Class/Rev (60h Page 01h)
Register 24h must be set to Page 01h to access this register.
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Default: 12xxh
D15
D14
D13
Reserved
D12
D11
D10
D9
D8
CL4
CL3
CL2
CL1
CL0
D7
D6
D5
D4
D3
D2
D1
D0
RV7
RV6
RV5
RV4
RV3
RV2
RV1
RV0
Bit(s)
Reset Value
Name
15-13
12-8
7-0
7.4.2.
Description
Reserved
Reserved -NOT DEFINED
CL4:CL0
CODEC Compatibility Class (RO)
This is a CODEC vendor specific field to define software compatibility for
the CODEC. Software reads this field, together with CODEC vendor ID
(reg 7C-7Eh), to determine vendor specific programming interface
compatibility. Software can rely on vendor specific register behavior to be
compatible among vendor CODECs of the same class.
00h - Field not implemented
01h-1Fh - Vendor specific compatibility class code
Equals Vendor ID2(Reg 7Eh) bits D7 to D0
RV7:RV0
Revision ID: (RO)
This register specifies a device specific revision identifier. The value is
chosen by the vendor. Zero is an acceptable value. This field should be
viewed as a vendor defined extension to the CODEC ID. This number
changes with new CODEC stepping of the same CODEC ID.
PCI SVID (62h Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: FFFFh
D15
D14
D13
D12
D11
D10
D9
D8
PVI15
PVI14
PVI13
PVI12
PVI11
PVI10
PVI9
PVI8
D7
D6
D5
D4
D3
D2
D1
D0
PVI7
PVI6
PVI5
PVI4
PVI3
PVI2
PVI1
PVI0
Bit(s) Reset Value
Name
Description
PCI Sub System Vendor ID:
This field provides the PCI Sub System Vendor ID of the Audio or Modem Sub
PVI15:PVI0 Assembly Vendor (i.e., CNR manufacturer, Motherboard Vendor). This is NOT the
CODEC vendor PCI Vendor ID, nor the AC '97 controller PCI Vendor ID.
If data is not available, returns FFFFh.
15-0
Note: This register is populated by the BIOS and does not reset on RESET#.
7.4.3.
PCI SSID (64h Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: FFFFh
D15
D14
D13
D12
D11
D10
D9
D8
PI15
PI14
PI13
PI12
PI11
PI10
PI9
PI8
D7
D6
D5
D4
D3
D2
D1
D0
PI7
PI6
PI5
PI4
PI3
PI2
PI1
PI0
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Bit(s) Reset Value
Name
Description
PCI Sub System ID:
This field provides the PCI Sub System ID of the Audio or Modem Sub Assembly
(i.e., CNR Model, Motherboard SKU). This is NOT the CODEC vendor PCI ID, nor
PI15:PVI0
the AC '97 controller PCI ID. Information in this field must be available for AC '97
controller reads when CODEC ready is asserted in AC link.If data is not available,
returns FFFFh.
15-0
Note: This register is populated by the BIOS and does not reset on RESET#.
7.4.4.
Function Select (66h Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
D4
D3
D2
D1
D0
FC3
FC2
FC1
FC0
T/R
Reserved
D7
D6
D5
Reserved
Bit(s) Reset Value
15-5
4-1
Name
Description
Reserved Reserved
00h
Function Code bits:
00h - Line Out (Master Out)
01h - Head Phone Out (AUX Out)
Setting the T/R bit to 0 = Left, 1 = Right
02h - DAC 3 (C/LFE) - Not Supported
03h - SPDIF out
04h - Phone In
05h - Mic1 (Mic select = 0)
06h - Mic2 (Mic select = 1)
07h - Line In
08h - CD In
09h - Video In
FC3:FC0 0Ah - Aux In
0Bh - Mono Out
0C-0Fh - Reserved
For supported Jack and Mic Sense Functions, see Table 22: page 72.
The Function Code Bits are used to read Register 68h (Page 01h) and Register
6Ah (Page 01h).
Mono I/O should report relevant sense and function information on Tip, and report
not supported on Ring.
Setting the function code to unsupported values will return a 0 when accessing the
Information Valid Bit in page 01 register 68h bit 5.
0
0
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T/R
Tip or Ring selection Bit.This bit sets which jack conductor the sense value is
measured from. Software will program the corresponding the Ring/Tip selector bit
together with the I/O number in bits FC[3:0].
0 - Tip (Left)
1 - Ring (Right)
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Note: This register does not reset on RESET#.
Table 22. Supported Jack and Mic Sense Functions
Function Code
I/O
Sense Capability
00h
Line_Out
Jack Sense
01h
Headphone_Out
Jack Sense
05h
Mic1
Mic Sense
06h
Mic2
Mic Sense
7.4.5.
Function Information (68h Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: 00xxh, see table 23: page 73.
D15
D14
D13
D12
D11
D10
D9
D8
G4
G3
G2
G1
G0
INV
DL4
DL3
D3
D2
D1
D7
D6
D5
D4
DL2
DL1
DL0
IV
Bit(s) Reset Value
15
14-11
0
0
10
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Name
G4
Reserved
D0
FIP
Description
Gain Sign Bit: The CODEC updates this bit with the sign of the gain value
present in G[3:0]. The BIOS updates this to take into consideration external
amplifiers or other external logic when relevant.
G[4] indicates whether the value is a gain or attenuation.
Gain in the G4 bit is in terms of dB.
This bit is Read/Write and only reset on POR and not by RESET#.
G3:G0
Gain Bits: The CODEC updates these bits with the gain value (dB relative to
level-out) in 1.5dBV increments. The BIOS updates these to take into
consideration external amplifiers or other external logic when relevant.
G[0:3] indicates the magnitude of the gain. G[4] indicates whether the value is a
gain or attenuation.
For Gain/Attenuation settings, see Table 24: page 73.
These bits are read/write and are not reset on RESET#.
INV
Inversion bit: Indicates that the CODEC presents a 180 degree phase shift to the
signal.
0h - No inversion reported
1h - Inverted
This bit is read/write and is not reset on RESET#.
BIOS should invert for each inverting gain stage.
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Bit(s) Reset Value
9-5
Name
Description
DL4:DL0
Buffer delays: CODEC will provide number a delay measurement for the input
and output channels. Software will use this value to accurately calculate audio
stream position with respect to what is been reproduced or recorded. These
values are in 20.83 sec (1/48000 second) units.
For output channels, this timing is from the end of AC Link frame in which the
sample is provided, until the time the analog signal appears at the output pin. For
input streams, this is from when the analog signal is presented at the pin until the
representative sample is provided on the AC Link.
Analog in and out paths are not considered as part of this delay.
The measurement is a 'typical' measurement, at a 48 KHz sample rate, with
minimal in-CODEC processing (i.e., 3D effects are turned off.)
00h - Information not provided
01h…1Eh - Buffer delay in 20.83 sec units
1Fh - reserved
These bits are read/write and are not reset on RESET#.
The default value is the delay internal to the CODEC. The BIOS may add to this
value the known delays external to the CODEC, such as for an external amplifier.
Information Valid Bit: Indicates whether a sensing method is provided by the
CODEC and if information field is valid. This field is updated by the CODEC.
0h--After CODEC RESET# de-assertion, it indicates the CODEC does NOT
provides sensing logic and this bit will be Read Only. After a sense cycle is
completed indicates that no information is provided on the sensing method.
1h--After CODEC RESET# de-assertion, it indicates the CODEC provides
sensing logic for this I/O and this bit is Read/Write. After clearing this bit by
writing1, when a sense cycle is completed the assertion of this bit indicates that
there is valid information in the remaining descriptor bits. Writing 0 to this bit has
no effect.
BIOS should NOT write this bit, as it is reset on RESET#.
4
1
IV
3-1
0
Reserved
0
NA
Bit not used, should read back 0
Function Information Present
This bit is set to a 1 indicates that the G[4:0], INV, DL[4:0](Register 68h, Page
01h) and ST[2:0](register 6Ah, Page 01h) are supported and R/W capable.
This bit is Read Only.
FIP
Table 23. Reg 68h Default Values
Reg 66h Function Code
Reg 68h Default Value
00h Line Out
0010h
01h Headphone Out
0010h
05h Mic1
0010h
06h Mic2
0010h
All other Function Codes
0000h
For RESET#: Reg 68h default value is 0000h.
Table 24. Gain or Attenuation Examples
G[4:0]
Gain or Attenuation (dB relative to level-out)
00000
0 dBV
00001
+1.5 dBV
01111
+24 dBV
10001
-1.5 dBV
11111
-24 dBV
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Table 25. Register 68h/Page 01h Bit Overview
7.4.6.
Bit
Bit R/W Overview
D5:D15
Read/Write and only reset on POR (Power on Reset) and not by RESET#.
D4
Read/Write and should NOT be set by the BIOS
D3:1
Reserved
D0
Read Only.
Digital Audio Control (6Ah, Page 00h)
To access Register 6Ah, Page 00h must be selected in Register 24h.
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
D3
D2
D1
D0
SPOR
DO1
RSVD
Reserved
D7
D6
D5
D4
Reserved
Bit(s) Reset Value
Name
15:3
0
Reserved
2
0
SPOR
1
0
DO1
0
0
Reserved
7.4.7.
Description
Bits not used, should read back 0
Over-ride Register 2Ah, D12 write-lock when SPDIF_EN = 1.
All bits except SPDIF sample-rate are affected (D13-D12). Allows for sub-code
changing on-the-fly.
SPDIF Digital Output Source Selection:
DO1 = 0; PCM data from the AC-Link to SPDIF
DO1 = 1; ADC record data to SPDIF
Bits not used, should read back 0
Sense Details (6Ah Page 01h)
Register 24h must be set to Page 01h to access this register.
Default: NA
D15
D14
D13
ST2
ST1
ST0
S4
S3
S2
S1
S0
D7
D6
D5
D4
D3
D2
D1
D0
OR1
OR0
SR5
SR4
SR3
SR2
SR1
SR1
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D12
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D10
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Bit(s) Reset Value
Name
Description
Connector/Jack location bits
This field describes the location of the jack in the system.
0h - Rear I/O Panel
1h - Front Panel
ST2:ST0 2h - Motherboard
3h - Dock/External
4h:6h - Reserved
7h - No Connection/unused I/O
These bits are Read/Write.
15-13
12-8
7-6
S4:S0
Sensed bits meaning relates to the I/O being sense as output or inputs.
Sensed bits (outputs): See Table 26: page 75.
This field allows for the reporting of the type of output peripheral/device plugged in
the jack. Values specified below should be interrogated in conjunction with the
SR[5:0] and OR[1:0] bits for accurate reporting.
Sensed bits (inputs): See Table 27: page 76.
This field allows for the reporting of the type of input peripheral/device plugged in
the jack. Values specified below should be interrogated in conjunction with the
SR[5:0] and OR[1:0] bits for accurate reporting.
This field is Read Only.
OR1:0
Order Bits. These bits indicate the order the sense result bits SR[5:0] are using.
00 - 100 (i.e., Ohms)
01 - 101 (i.e., 10 Ohms)
10 - 102 (i.e., 100 Ohms)
11 - 103 (i.e., 1K Ohms)
Sense Result bits
5-0
SR5:SR0
These bits are used to report a vendor specific fingerprint or value. (Resistance,
impedance, reactance, ect). This field is Read Only.
Table 26. Sensed Bits (Outputs)
Reported Value
Output Peripheral/Device
0h
Data not valid. Indicates that the reported value(s) is invalid.
1h
No connection. Indicates that there are no connected devices.
2h
Fingerprint. Indicates a specific fingerprint value for devices that are not specified or unknown.
3h
Speakers (8 ohms)
4h
Speakers (4 ohms)
5h
Powered Speakers
6h
Stereo Headphone
7h
Reserved
8h
Reserved
9h
Headset (mono speaker left channel and mic.)
Ah
Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with
OR[1:0] provide information regarding the type of device sensed.
Bh-Eh
Reserved
Fh
Unknown (use fingerprint)
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Table 27. Sensed Bits (Inputs)
Reported Value
Input Peripheral/Device
0h
Data not valid. Indicates that the reported value(s) is invalid.
1h
No connection. Indicates that there are no connected devices.
2h
Fingerprint. Indicates a specific fingerprint value for devices that are not specified.
3h
Microphone (mono)
7.4.8.
4h
Reserved
5h
Stereo Line In (CE device attached)
6h
Reserved
7h
Reserved
8h
Reserved
9h
Headset (mono speaker left channel and mic.)
Ah
Other. Allows a vendor to report sensing other type of devices/peripherals. SR[5:0] together with
OR[1:0] provide information regarding the type of device sensed.
Bh-Eh
Reserved
Fh
Unknown (use fingerprint)
Revision Code (6Ch)
To access Register 6Ch, Page 00h must be selected in Register 24h.
Default: xxxxh
D15
D14
D13
D12
D11
D10
D9
D8
D2
D1
D0
MINORREV
D7
D6
D5
D4
D3
MAJORREV
Bit(s) Reset Value
Name
Description
15:8
00h
MINORREV
Minor Revision ID. These bits are read only and will be updated based on minor
device changes which will not require software changes.
7:0
xx
MAJORREV
Major Revision ID. These bits are read only and will be updated based on major
device changes.
7.4.9.
Analog Special (6Eh)
To access Register 6Eh, Page 00h must be selected in Register 24h.
Default: 1000h
D15
D14
D13
Reserved
D12
D11
D7
D6
D5
D4
RSVD
MUTEFIX
DISABLE
ADCSLT1
ADCSLT0
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D10
AC97MIX
D3
76
D9
D8
Reserved
D2
RSVD MIC GAIN VAL
D1
D0
SPLYOVR EN
SPLYOVR VAL
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Bit(s) Reset Value
15:13
Name
0
Description
Reserved
Bits not used, should read back 0
12
1
AC97MIX
0 = mixer record contains a mix of all mono and stereo analog input signals,
not the DAC (ALL ANALOG mode)
1 = mixer record contains a mix of all mono and stereo analog input signals
plus the DAC signal (AC97 mode)
This bit only has an effect when either Stereo Mix or Mono Mix is selected as
the record source in Reg. 1Ah.
The “ALL” mode is useful in conjunction with the POP BYPASS mode (Reg.
20h;D15) to record all analog sources, perform further processing in the
digital domain, including combining with other PCM data, and routing through
the DACs directly to Line Out, Headphone Out, or Mono Out.
A Stereo Mix recording will be affected by the setting of the 3D Effects bit
(Reg. 20h;D13)
11:7
0
Reserved
Bits not used, should read back 0
MUTEFIX
DISABLE
0 = MUTE FIX Enabled
1 = MUTE FIX Disabled
When this bit is zero, and either channel is set to -46.5dB attenuation, 1Fh,
then that channel is fully muted. When this bit is one, then operation is per
AC’97 specification.
6
0
5:4
0
ADCSLT1:0
3
0
Reserved
2
Select slots for ADC data on ACLINK
00 = left slot 3, right slot 4
01 = left slot 7, right slot 8
10 = left slot 6, right slot 9
11 = left slot 10, right slot 11
Reserved
Adds +10dB gain to the selected MIC input. Use in conjunction with
BOOSTEN (Reg. 0Eh;D6)
BOOSTEN MICGAINVAL
0
0
= 0 dB
MIC GAIN VAL
0
1
= 10 dB
1
0
= 20 dB
1
1
= 30 dB
0
Supply Override bit allows override of the supply detect.
1
0
SPLYOVR_EN
0 = no override on supply detect
1 = override supply detect with bit 0
Supply Override Value provides the analog voltage operation values.
0
7.4.10.
0
SPLYOVR_VAL
0 = force 3.3 V operation
1 = force 5 V operation
Analog Current Adjust (72h)
To unlock Register 72h, write 0xABBA to Register 70h.
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
D3
D2
D1
D0
Reserved
D7
D6
D5
D4
INT APOP
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Reserved
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Bit(s) Reset Value
15:8
0
7
0
6:0
0
7.4.11.
Name
Description
Reserved
Reserved
0 = Anti Pop Enabled
1 = Anti Pop Disabled
The STAC9752A/9753A includes an internal power supply anti-pop circuit that
prevents audible clicks and pops from being heard when the CODEC is powered
on and off. This function is accomplished by delaying the charge/discharge of the
VREF capacitor (Pin 27). CVREF value of 1 F will cause a turn-on delay of
INT_APOP roughly 3 seconds, which will allow the power supplies to stabilize before the
CODEC outputs are enabled. The delay will be extended to 30 seconds if a value
of CVREF value of 10 F is used. The CODEC outputs are also kept stable for the
same amount of time at power-off to allow the system to be gracefully turned off.
The INT_APOP bit allows this delay circuit to be bypassed for rapid production
testing. Any external component anti-pop circuit is unaffected by the internal
circuit.
Reserved
Reserved
EAPD Access Register (74h)
Default: 0800h
D15
D14
D13
EAPD
D12
Reserved
D7
D6
D5
D11
D10
EAPD_OEN
D4
D3
Reserved
Bit(s) Reset Value
Name
15
0
EAPD
14:12
0
Reserved
11
1
10:3
0
D9
D8
Reserved
D2
D1
D0
INTDIS
GPIOACC
GPIOSLT12
Description
EAPD data Enable
EAPD data output on EAPD when bit D11 = 1
EAPD data input from pin when bit D11 = 0
Bit not used, should read back 0
EAPD Pin Enable
EAPD_OEN 0 = EAPD configured as input pin
1 = EAPD configured as output pin
Reserved
Bit not used, should read back 0
Interrupt disable option.
Interrupts cleared by writing a 1 to I4 (Reg24h:D15)
2
0
INTDIS
1
0
GPIOACC
0
0
0 = will clear both SENSE and GPIO interrupts
1 = will only clear SENSE interrupts. GPIO interrupts will have to be cleared in
Reg54h.
GPIO ACCESS
0 = ACLINK access from GPIO Pads
1 = ACLINK access from GPIO Register 54h
0 = GPIO0/1 access via Reg54h when GPIO is set as an output, for input Slot 12
data will be 0h.
1 = GPIO0/1 access via Slot 12 when GPIO is set as an output, for inputs
GPIOSLT12 Reg54h will not be updated.
This can only be used if a modem CODEC is not present in the system and using
Slot 12.
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7.4.12.
Register 78h Enable (76h)
Default: 0000h
D15
D14
D13
D12
D11
D10
D9
D8
EN15
EN14
EN13
EN12
EN11
EN10
EN9
EN8
D7
D6
D5
D4
D3
D2
D1
D0
EN7
EN6
EN5
EN4
EN3
EN2
EN1
EN0
D9
Universal Jacks™ Selection (78h)
7.4.13.
To unlock Register 78h, write 0xABBA to Register 76h.
Default: 0000h
D15
D14
D13
HP SEL
D7
D6
STMIC SEL
Bit(s)
15:14
D5
MSPWDN
Reset
Value
00
D12
LO SEL
D11
D10
RSVD
LI SEL
D3
D2
D4
HP3dB
DACBYHP
DACBYLO
Name
HP SEL
Line Out Selection
00 - LO on pins 35/36 (default)
01 - LO on pins 23/24
10 - Off
11 - Off
13:12
00
LO SEL
11
0
RSVD
Reserved
10
00
LI SEL
Line In Selection
0 - LI on pins 23/24 (default)
1 - LI on pins 35/36
00
MIC SEL
7
0
STMIC SEL
6
0
MSPWDN
5
0
HP3dB
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D1
D0
Reserved
ADC HPF
BYP
Description
Headphone Amp Selection
00 - HP on pins 39/41 (default)
01 - HP on pins 35/36
10 - Off
11 - Off
9:8
Reserved
D8
MIC SEL
Microphone Selection
00 - MIC on pins 21/22 (default)
01 - MIC on pins 23/24
10 - MIC on pins 35/36
11 - MIC on pins 39/41
Stereo MIC Select
0 - Mono MIC
1 - Stereo MIC
MIC Sense Power Down
0 - On
1 - Off
Headphone 3dB
0 - Off
1 - On
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Bit(s)
4
7.5.
Reset
Value
Name
0
Description
DACBYPHP
Independent DAC bypass for HP Volume (Reg 04h)
This can be over ridden by Reg 20h D15, pop bypass
0 - Off
1 - On
Independent DAC bypass for LO Volume (Reg 02h)
This can be over ridden by Reg 20h D15, pop bypass
0 - Off
1 - On
3
0
DACBYPLO
2
0
Reserved
Reserved
1
0
Reserved
Reserved
0
0
ADC HPF BYP
0 = Normal operation, (ADC High Pass Filter active)
1 = ADC High Pass Filter Bypass
Vendor ID1 and ID2 (Index 7Ch and 7Eh)
These two registers contain four 8-bit ID codes. The first three codes have been assigned by Microsoft using their Plug and Play Vendor ID methodology. The fourth code is a TSI assigned code identifying the STAC9752A/9753A. The ID1 register (index 7Ch) contains the value 8384h, which is the
first (83h) and second (84h) bytes of the Microsoft ID code. The ID2 register (index 7Eh) contains the
value 7652h, which is the third (76h) byte of the Microsoft ID code, and 52h which is the
STAC9752A/9753A ID code.
7.5.1.
Vendor ID1 (7Ch)
Default: 8384h
D15
7.5.2.
D14
D13
D12
D11
D10
D9
D8
1
0
0
0
0
0
1
1
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
1
0
0
Vendor ID2 (7Eh)
Default: 7652h
D15
D14
D13
D12
D11
D10
D9
D8
0
1
1
1
0
1
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
0
1
0
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8. LOW POWER MODES
The STAC9752A/9753A is capable of operating at reduced power when no activity is required. The
state of power down is controlled by the Powerdown Register (26h). There are seven separate commands of power down. The power down options are listed in Table 28. The first three bits, PR0..PR2,
can be used individually or in combination with each other, and control power distribution to the
ADCs, DACs and Mixer. The last analog power control bit, PR3, affects analog bias and reference
voltages, and can only be used in combination with PR1, PR2, and PR3. PR3 essentially removes
power from all analog sections of the CODEC, and is generally only asserted when the CODEC will
not be needed for long periods. PR0 and PR1 control the PCM ADCs and DACs only. PR2 and PR3
do not need to be "set" before a PR4, but PR0 and PR1 should be "set" before PR4. PR5 disables
the DSP clock and does not require an external cold reset for recovery. PR6 disables the headphone
driver amplifier for additional analog power saving.
Table 28. Low Power Modes
GRP Bits
Function
PR0
PCM in ADCs & Input Mux Powerdown
PR1
PCM out DACs Powerdown
PR2
Analog Mixer powerdown (VREF still on)
PR3
Analog Mixer powerdown (VREF off)
PR4
Digital Interface (AC-Link) powerdown (BIT CLK forced low)
PR5
Digital Clock disable, BIT CLK still on
PR6
Powerdown HEADPHONE_OUT
Figure 22. Example of STAC9752A/9753A Powerdown/Powerup Flow
PR0=1
Normal
PR1=1
ADCs off PR0
PR0=0 & ADC=1
Ready =1
PR2=1
DACs off PR1
PR1=0 & DAC=1
PR4=1
Analog off
PR2 or PR3
PR2=0 & ANL=1
Default
Digital I/F off
PR4
Shut off
AC-Link
Warm Reset
Cold Reset
The Figure 22 illustrates one example procedure to do a complete powerdown of
STAC9752A/9753A. From normal operation, sequential writes to the Powerdown Register are performed to power down STAC9752A/9753A a section at a time. After everything has been shut off, a
final write (of PR4) can be executed to shut down the AC-Link. The part will remain in sleep mode
with all its registers holding their static values. To wake up, the AC'97 Controller will send an
extended pulse on the sync line, issuing a warm reset. This will restart the AC-Link (resetting PR4 to
zero). The STAC9752A/9753A can also be woken up with a cold reset. A cold reset will reset all of
the registers to their default states (Paged Registers are semi-exempt). When a section is powered
back on, the Powerdown Control/Status register (index 26h) should be read to verify that the section
is ready (stable) before attempting any operation that requires it.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Figure 23. Powerdown/Powerup Flow With Analog Still Alive
PR0=1
PR1=1
PR4=1
Normal
ADCs off PR0
PR0=0 & ADC=1
DACs off PR1
PR1=0 & DAC=1
Digital I/F off
PR4
Shut off
AC-Link
Warm Reset
Figure 23 illustrates a state when all the mixers should work with the static volume settings that are
contained in their associated registers. This configuration can be used when playing a CD (or external LINE_IN source) through the STAC9752A/9753A to the speakers, while most of the system in
low power mode. The procedure for this follows the previous example, except that the analog mixer
is never shut down.
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9. MULTIPLE CODEC SUPPORT
The STAC9752A/9753A provides support for the multi-CODEC option according to the Intel AC'97,
rev 2.3 specification. By definition there can be only one Primary CODEC (CODEC ID 00) and up to
three Secondary CODECs (CODEC IDs 01,10, and 11). The CODEC ID functions as a chip select.
Secondary devices therefore have completely orthogonal register sets; each is individually accessible and they do not share registers.
9.1.
Primary/Secondary CODEC Selection
In a multi-CODEC environment the CODEC ID is provided by external programming of pins 45 and
46 (CID0 and CID1). The CID pin electrical function is logically inverted from the CODEC ID designation. The corresponding pin state and its associated CODEC ID are listed in the "CODEC ID
Selection" table. Also see slot assignment discussion, “Multi-Channel Programming Register (Index
74)”.
Table 29. CODEC ID Selection
9.1.1.
CID1 State
CID0 State
CODEC ID
CODEC Status
DVdd or floating
DVdd or floating
00
Primary
DVdd or floating
0V
01
Secondary
0V
DVdd or floating
10
Secondary
0V
0V
11
Secondary
Primary CODEC Operation
As a Primary device the STAC9752A/9753A is completely compatible with existing AC'97 definitions
and extensions. Primary CODEC registers are accessed exactly as defined in the AC'97 Component
Specification and AC'97 Extensions. The STAC9752A/9753A operates as Primary by default, and
the external ID pins (45 and 46), have internal pull-ups so that these pins may be left as no-connects
for primary operation.
When used as the Primary CODEC, the STAC9752A/9753A generates the master AC-Link BIT_CLK
for both the AC'97 Digital Controller and any Secondary CODECs. The STAC9752A/9753Acan support up to four, 10 KW / 50 pF loads on the BIT_CLK output. This is to ensure that up to four CODEC
implementations will not load down the clock output.
9.1.2.
Secondary CODEC Operation
When the STAC9752A/9753A is configured as a Secondary device the BIT_CLK pin is configured as
an input at power up. Using the BIT_CLK provided by the Primary CODEC insures that everything
on the AC-Link will be synchronous. As a Secondary device, it can be defined as CODEC ID 01, 10,
or 11 in the two-bit field(s) of the Extended Audio and/or Extended Modem ID Register(s).
9.2.
Secondary CODEC Register Access Definitions
The AC'97 Digital Controller can independently access Primary and Secondary CODEC registers by
using a 2-bit CODEC ID field (chip select) which is defined as the LSBs of Output Slot 0. For Secondary CODEC access, the AC'97 Digital Controller must invalidate the tag bits for Slot 1 and 2
Command Address and Data (Slot 0, bits 14 and 13) and place a non-zero value (01, 10, or 11) into
the CODEC ID field (Slot 0, bits 1 and 0).
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As a Secondary CODEC, the STAC9752A/9753A will disregard the Command Address and Command Data (Slot 0, bits 14 and 13) tag bits unless it sees a 2-bit CODEC ID value (Slot 0, bits 1 and
0) that matches its configuration. In a sense the Secondary CODEC ID field functions as an alternative Valid Command Address (for Secondary reads and writes) and Command Data (for Secondary
writes) tag indicator.
Secondary CODECs must monitor the Frame Valid bit, and ignore the frame (regardless of the state
of the Secondary CODEC ID bits) if it is not valid. AC'97 Digital Controllers should set the frame valid
bit for a frame with a secondary register access, even if no other bits in the output tag slot except the
Secondary CODEC ID bits are set.
This method is designed to be backward compatible with existing AC'97 controllers and CODECs.
There is no change to output Slot 1 or 2 definitions.
Table 30. Secondary CODEC Register Access Slot 0 Bit Definitions
Output Tag Slot (16-bits)
Bit
15
Description
Frame Valid
14
Slot 1 Valid Command Address bit (†Primary CODEC only)
13
Slot 2 Valid Command Data bit (†Primary CODEC only)
12-3
2
Slot 3-12 Valid bits as defined by AC'97
Reserved (Set to “0”)
†1-0
2-bit CODEC ID field (00 reserved for Primary; 01, 10, 11 indicate Secondary)
Note: † New definitions for Secondary CODEC Register Access
Using three CODECs typically requires a controller to support SDATA_IN2.
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10. TESTABILITY
The STAC9752A/9753A has two test modes. One is for ATE in-circuit test and the other is restricted
for TSI’s internal use. STAC9752A/9753A enters the ATE in-circuit test mode if SDATA_OUT is sampled high at the trailing edge of RESET#. Once in the ATE test mode, the digital AC-Link outputs
(BIT_CLK and SDATA_IN) are driven to a high impedance state. This allows ATE in-circuit testing of
the AC'97 controller. Use of the ATE test mode is the recommended means of removing the CODEC
from the AC-Link when another CODEC is to be used as the primary. This case will never occur during standard operating conditions. Once either of the two test modes have been entered, the
STAC9752A/9753A must be issued another RESET# with all AC-Link signals held low to return to
the normal operating mode.
Table 31. Test Mode Activation
SYNC
SDATA_OUT
Description
0
0
Normal AC '97 operation
0
1
ATE Test Mode
1
0
TSI Internal Test Mode
1
1
Reserved
10.1. ATE Test Mode
ATE test mode allows for in-circuit testing to be completed at board level. For this to work, the outputs of the device must be driven to a high impedance state (Z). Internal pullups for digital I/O pins
must be disabled in this mode. This mode initiates on the rising edge of RESET# pin. Only a cold
reset will exit the ATE Test Mode.
Table 32. ATE Test Mode Operation
Pin Name
Pin #
Function
Description
SDATA_OUT
5
1
BIT_CLK
6
Z
SDATA_IN
8
Z
SYNC
10
0
RESET#
11
1
N.C.
31
Z
Always an input
N.C.
33
Z
Always an input
N.C.
34
Z
Always an input
GPIO0
43
Z
GPIO1
44
Z
CID0
45
Z
CID1
46
Z
EAPD
47
Z
SPDIF
48
Z
Must be held high at the rising edge of RESET#
Must be held low at rising edge of RESET#
Note: Pins 31, 33, and 34 are NO CONNECTS.
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11. STAC9752A/9753A PIN DESCRIPTION
11.1. Pin Description for the 48-pin LQFP Package
36
35
34
33
32
31
30
29
28
27
26
25
LINE_OUT_R
LINE_OUT_L
NC
NC
CAP2
NC
AFILT2
AFILT1
VREFout
VREF
AVss1
AVdd1
Figure 24. Pin Description Drawing
37
38
39
40
41
42
43
44
45
46
47
48
48 pin LQFP
24
23
22
21
20
19
18
17
16
15
14
13
LINE_IN_R
LINE_IN_L
MIC2
MIC1
CD_R
CD_GND
CD_L
VIDEO_R
VIDEO_L
AUX_R
AUX_L
PHONE
DVdd1 1
XTL_IN 2
XTL_OUT 3
DVss1 4
SDATA_OUT 5
BIT_CLK 6
DVss2 7
SDATA_IN 8
DVdd2 9
SYNC 10
RESET# 11
PC_BEEP 12
MONO_OUT
AVdd2
HP_OUT_L
No Connect
HP_OUT_R
AVss2
GPIO0
GPIO1
CID0
CID1
EAPD
SPDIF OUT
PIN 48: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
Pin 19: The CD_GND signal is an AC signal return for the two CD input channels. It is normally
biased at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal
directly to ground will change the internal bias of the entire CODEC, and cause significant distortion.
If there is no analog CD input, then this pin can be No-Connect.
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11.2. Pinout List 48-pin LQFP Package
Table 33. STAC9752A/9753A 48 Pin LQFP Pin List
Pin#
PIN Name
Pin#
Pin Name
1
DVDD
25
AVDD1
2
XTAL_IN
26
AVSS1
3
XTAL_OUT
27
VREF IN
4
DVSS1
28
VREF_OUT
5
SDATA_OUT
29
AFILT1
6
BIT_CLK
30
AFILT2
7
DVSS2
31
N.C.
8
SDATA_IN
32
CAP2
9
DVDD
33
N.C.
10
SYNC
34
N.C.
11
RESET#
35
Line_Out_L
12
PC_BEEP
36
Line_Out_R
13
PHONE
37
MONO
14
AUX_L
38
AVDD2
15
AUX_R
39
HP_L
16
VIDEO_L
40
No Connect
17
VIDEO_R
41
HP_R
18
CD L
42
AVSS3
19
CD GND **
43
GPIO0
20
CD R
44
GPIO1
21
MIC_L
45
CID0
22
MIC_R
46
CID1
23
LINE_IN_L
47
EAPD / GPIO
24
LINE_IN_R
48
S/PDIF-OUT
PIN 48: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
** The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased at
about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many
designers. It should not have any DC path to GND. Connecting the CD_GND signal directly to
ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is
no analog CD input, then this pin can be No-Connect.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
11.3. Pin Description for the 32-pad QFN Package
24
23
22
21
20
19
18
17
LINE_OUT_R
LINE_OUT_L
CAP2
AFILT2
AFILT1
VREF_OUT
VREF
AVSS1
Figure 25. STAC9752A/9753A 32 pad QFN Pin Description Drawing
25
26
27
28
29
30
31
32
32 pad QFN
16
15
14
13
12
11
10
9
LINE_IN_R
LINE_IN_L
MIC 2
MIC 1
CD_R
CD_GND
CD_L
PHONE
CLOCK_IN
SDATA_OUT
BIT_CLK
DVSS2
SDATA_IN
DVDD
SYNC
RESET#
1
2
3
4
5
6
7
8
MONO_OUT
AVDD2
HP_L
HP_R
AVSS
GPIO3
EAPD/GPIO4
SPDIF-OUT
PIN 32: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
Pin 11: The CD_GND signal is an AC signal return for the two CD input channels. It is normally
biased at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal
directly to ground will change the internal bias of the entire CODEC, and cause significant distortion.
If there is no analog CD input, then this pin can be No-Connect.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
11.4. Pinout List 32-pad QFN Package
Table 34. STAC9752A/9753A 32 Pad QFN Pin List
Pin#
PIN Name
Pin#
Pin Name
1
CLOCK_IN
17
AVSS1
2
SDATA_OUT
18
VREF IN
3
BIT_CLK
19
VREF_OUT
4
DVSS2
20
AFILT1
5
SDATA_IN
21
AFILT2
6
DVDD
22
CAP2
7
SYNC
23
Line_Out_L
8
RESET#
24
Line_Out_R
9
PHONE
25
MONO
10
CD L
26
AVDD2
11
CD GND **
27
HP_L
12
CD R
28
HP_R
13
MIC 1
29
AVSS3
14
MIC 2
30
GPIO1
15
LINE IN L
31
EAPD / GPIO
16
LINE IN R
32
S/PDIF-OUT
PIN 32: TO DISABLE SPDIF, USE AN 1 KW - 10 KW EXTERNAL PULLUP RESISTOR.
Pin 11: The CD_GND signal is an AC signal return for the two CD input channels. It is normally
biased at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused many designers. It should not have any DC path to GND. Connecting the CD_GND signal
directly to ground will change the internal bias of the entire CODEC, and cause significant distortion.
If there is no analog CD input, then this pin can be No-Connect.
11.5. STAC9752A/9753A Digital I/O
These signals connect the STAC9752A/9753A to its AC'97 controller counterpart, an external crystal, multi-CODEC selection and external audio amplifier.
Table 35. STAC9752A/9753A Digital Connection Signals
Pin Name
48 LQFP 32 QFN
Type
Pin #
Pin #
Description
Internal Pull-up
/Pull-down
XTL_IN / CLOCK_IN
2
1
I
Clock Input
N/A
XTL_OUT
3
-
I/O
24.576 MHz Crystal
N/A
SDATA_OUT
5
2
I
AC-Link Serial Data output
(inbound stream)
N/A
BIT_CLK
6
3
I/O
AC-Link Bit Clock
Pull-down 50K +/- 25%
SDATA_IN
8
5
O
AC-Link Serial Data input,
(outbound stream)
N/A
SYNC
10
7
I
AC-Link Frame Sync
N/A
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Table 35. STAC9752A/9753A Digital Connection Signals
48 LQFP 32 QFN
Type
Pin #
Pin #
Pin Name
Description
Internal Pull-up
/Pull-down
RESET#
11
8
I
AC-Link Reset
N/A
GPIO0
43
-
I/O
General Purpose I/O
Pull-up 50K +/- 25%
GPIO1
44
30
I/O
General Purpose I/O
Pull-up 50K +/- 25%
CID0
45
-
Chip ID Select0
Pull-up 50K +/- 25%
CID1
46
-
Chip ID Select1
Pull-up 50K +/- 25%
Pull-down 50K +/- 25%
Pull-down 50K +/- 25%
EAPD/GPIO
47
31
I/O
External Amplifier Power Down
General Purpose I/O
SPDIF-OUT
48
32
O
SPDIF digital output
11.6. STAC9752A/9753A Analog I/O
These signals connect the STAC9752A/9753A to analog sources and sinks, including microphones
and speakers.
Table 36. STAC9752A/9753A Analog Connection Signals
Pin Name
48 LQFP
Pin #
PHONE
13
32 QFN
Type
Pin #
9
I^
Description
Phone Input
Internal Pull-up
/Pull-down
N/A
AUX_L
14
-
I^
Aux Left Channel
N/A
AUX_R
15
-
I^
Aux Right Channel
N/A
VIDEO_L
16
-
I^
Video Audio Left Channel
N/A
VIDEO_R
17
-
I^
Video Audio Right Channel
N/A
CD_L
18
10
I^
CD Audio Left Channel
N/A
CD_GND
19
11
I^
CD Audio analog Return (see note 3)
N/A
CD_R
20
12
I^
CD Audio Right Channel
N/A
MIC1_L*
21
13
I^
Desktop Microphone Input
N/A
MIC1_R*
22
14
I^
Second Microphone Input
N/A
LINE_IN_L*
23
15
I*
Line In Left Channel
N/A
LINE_IN_R*
24
16
I*
Line In Right Channel
N/A
LINE_OUT_L*
35
23
O*
Line Out Left Channel
(with headphone support)
N/A
LINE_OUT_R*
36
24
O*
Line Out Right Channel
(with headphone support)
N/A
MONO_OUT
37
25
O
To telephony subsystem speakerphone
N/A
HP_OUT_L*
39
27
O*
Headphone Out Left Channel
N/A
HP_OUT_R
41
28
O*
Headphone Out Right Channel
N/A
1. ^ any unused input pins should be tied together and connected through a capacitor (0.1 µF suggested) to ground, except the MIC inputs which should have their own capacitor to ground if not
used.
2. * Universal Jack™ capable. Only pins 35/36 OR 39/41 may be used to drive headphones. It is
not possible to drive 2 sets of headphones at the same time.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
3. The CD_GND signal is an AC signal return for the two CD input channels. It is normally biased
at about 2.5V. The name of the pin in the AC’97 specification is CD_GND, and this has confused
many designers. It should not have any DC path to GND. Connecting the CD_GND signal
directly to ground will change the internal bias of the entire CODEC, and cause significant distortion. If there is no analog CD input, then this pin can be No-Connect.
11.7. STAC9752A/9753A Filter/References
These signals are connected to resistors, capacitors, or specific voltages.
Table 37. STAC9752A/9753A Filtering and Voltage References
Signal Name
48 LQFP 32 QFN
Type
Pin #
Pin #
Internal Pull-up
/Pull-down
Description
VREF IN
27
18
O
Analog ground
N/A
VREFOUT
28
19
O
Reference Voltage out 5mA drive
N/A
AFILT0
29
20
O
Anti-Aliasign FIlter Cap - ADC Right Channel
N/A
AFILT1
30
21
O
Anti-Aliasign FIlter Cap - ADC Left Channel
N/A
CAP2
32
20
O
ADC reference Cap
N/A
11.8. STAC9752A/9753A Power and Ground Signals
Pin Name
48 LQFP
Pin #
32 QFN
Pin #
Type
AVdd2
38
26
I
Analog Vdd = 5.0V or 3.3V
N/A
AVss1
26
17
I
Analog Gnd
N/A
AVss3
42
29
I
Analog Gnd
N/A
DVdd2
9
6
I
Digital Vdd = 3.3V
N/A
DVss1
4
-
I
Digital Gnd
N/A
DVss2
7
4
I
Digital Gnd
N/A
Internal Pull-up
/Pull-down
Description
Table 38. STAC9752A/9753A Power and Ground Signals
11.9. STAC9752A/9753A No Connects
These pins have no function and may be connected to traditional AC97 functions.
Pin Name
48 LQFP
Pin #
32 QFN
Pin #
Type
N.C.
31
-
-
No Connect
Pull-down 50K +/-25%
N.C.
33
-
-
No Connect
Pull-down 50K +/-25%
N.C.
34
-
-
No Connect
Pull-down 50K +/-25%
N.C.
40
-
-
No Connect
Pin is high impedance, can be left floating
Description
Internal Pull-up
/Pull-down
Table 39. STAC9752A/9753A No Connects
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
12. ORDERING INFORMATION
Ordering Information
Part Number
Package
Temp Range
Supply Range
STAC9752AXTAEyyX
48-pin RoHS QFP 7mm x 7mm x 1.4mm
0° C to +70° C
DVdd = 3.3V, AVdd = 5.0V
STAC9753AXTAEyyX
48-pin RoHS QFP 7mm x 7mm x 1.4mm
0° C to +70° C
DVdd = 3.3V, AVdd = 3.3V
STAC9752AXNAEyyX
32-pin RoHS QFN 5mm x 5mm x 0.9mm
0° C to +70° C
DVdd = 3.3V, AVdd = 5.0V
STAC9753AXNAEyyX
32-pin RoHS QFN 5mm x 5mm x 0.9mm
0° C to +70° C
DVdd = 3.3V, AVdd = 3.3V
Note: the yy is the revision. Comtact sales for currnet orderable information.
Add an “R” to thye end fo rtape and reel delivery. MOQ is 2Ku for 48pin QFP and 2.5ku for 32pin
QFN.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
13. PACKAGE DRAWINGS AND PC BOARD LAYOUT INFORMATION
13.1. 48-Pin LQFP
Figure 26. Package Drawing - 48-pin LQFP
A2
D
Key
A
A1
D1
E1
E
b
48 pin LQFP
e
LQFP Dimensions in mm
Min.
Nom.
Max.
A
1.40
1.50
1.60
A1
0.05
0.10
0.15
A2
1.35
1.40
1.45
D
8.80
9.00
9.20
D1
6.90
7.00
7.10
E
8.80
9.00
9.20
E1
6.90
7.00
7.10
L
0.45
0.60
0.75
e
Pin 1
0.50
c
0.09
-
0.20
b
0.17
0.22
0.27
c
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
13.2. 32-Pad QFN
Figure 27. Package Drawing - 32-pad QFN
QFN Dimensions in mm
Key
Min
Nom
Max
A
-
0.60
0.80
A1
0
0.02
0.05
A3
b
©2014 TEMPO SEMICONDCUTOR, INC.
94
0.18
0.25
D
5.00 BSC
D1
3.50 BSC
E
5.00 BSC
E1
3.50 BSC
e
0.50 BSC
0.30
L
0.30
0.40
0.50
D2
3.20
3.50
3.60
E2
3.20
3.50
3.60
ZD
TSI™ CONFIDENTIAL
0.20 REF.
0.75 BSC
ZE
0.75 BSC
R
0.20~0.25
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STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
13.3. PC Board Recommendations for 32-pad QFN Package
Figure 28. Recommended PCB Layout for 32-pad QFN Package
SUGGESTED FOOTPRINT
PAD DETAIL
4.75 mm
0.30 mm
2.375 mm
32
0.15 mm
24
1
0.50 mm typical
0.375 mm
8
2.375 mm
0.75 mm
16
4.75 mm
NOTES:
1. Oblong pad is preferred geometry.
2. Oblong pad may be replaced with Rectangular pad of the same overall
dimensions.
3. Oblong pad may be replaced with Bullet pad of the same overall dimensions. If
a Bullet pad is used, flat shall be to the outside.
4. Solderpaste shall be oblong pad regardless of the pad geometry. Solderpaste
opening shall be the same dimensions as pad detail.
5. Recommended solderpaste stencil thickness is 0.127 mm, electropolished.
6. Soldermask is to be 1 mm larger in X- and Y-dimensions.
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
14. SOLDER REFLOW PROFILE
14.1. Standard Reflow Profile Data
Note: These devices can be hand soldered at 360 oC for 3 to 5 seconds.
FROM: IPC / JEDEC J-STD-020C “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid
State Surface Mount Devices” (www.jedec.org/download).
Profile Feature
Pb Free Assembly
o
Average Ramp-Up Rate (Tsmax - Tp)
3 C / second max
Preheat
Temperature Min (Tsmin)
Temperature Max (Tsmax)
Time (tsmin - tsmax)
150 oC
200 oC
60 - 180 seconds
Time maintained above
Temperature (TL)
Time (tL)
217 oC
60 - 150 seconds
Peak / Classification Temperature (Tp)
Time within 5
oC
of actual Peak Temperature (tp)
See “Package Classification Reflow Temperatures” on page 96.
20 - 40 seconds
Ramp-Down rate
6 oC / second max
Time 25 oC to Peak Temperature
8 minutes max
Note: All temperatures refer to topside of the package, measured on the package body surface.
Figure 29. Reflow Profile
14.2. Pb Free Process - Package Classification Reflow Temperatures
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
Package Type
MSL
Reflow Temperature
LQFP 48-pin
3
260 oC*
QFN 32-pad
3
260 oC*
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AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
15. APPENDIX A: PROGRAMMING REGISTERS
Reg #
Name
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
00h
Reset
RSRVD
SE4
SE3
SE2
SE1
SE0
ID9
ID8
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
6A90h
02h
Master Volume
Mute
RSRVD
ML5
ML4
ML3
ML2
ML1
ML0
Reserved
MR5
MR4
MR3
MR2
MR1
MR0
8000h
04h
HP_OUT
Mixer Volume
Mute
RSRVD HPL5
HPL4
HPL3
HPL2
HPL1
HPL0
Reserved
HPR5
HPR4
HPR3
HPR2
HPR1
HPR0
8000h
06h
Master Volume
Mono
Mute
MM5
MM4
MM3
MM2
MM1
MM0
8000h
0Ah
PC_BEEP
Volume
Mute
0Ch
Phone volume
Mute
0Eh
Mic Volume
Mute
10h
Line In Volume
Mute
Reserved
GL4
GL3
GL2
GL1
GL0
12h
CD Volume
Mute
Reserved
GL4
GL3
GL2
GL1
14h
Video Volume
Mute
Reserved
GL4
GL3
GL2
GL1
16h
AUX Volume
Mute
Reserved
GL4
GL3
GL2
18h
PCM Out
Volume
Mute
Reserved
GL4
GL3
GL2
SL2
SL1
SL0
Reserved
GL3
GL2
GL1
GL0
3D
Reserved
MIX
MS
Reserved
X
X
F7
F6
F5
F
F3
F2
F1
F0
PV3
PV2
PV1
PV0
GN4
GN3
GN2
GN1
GN0
GN4
GN3
GN2
GN1
GN0
8008h
Reserved
GR4
GR3
GR2
GR1
GR0
8808h
GL0
Reserved
GR4
GR3
GR2
GR1
GR0
8808h
GL0
Reserved
GR4
GR3
GR2
GR1
GR0
8808h
GL1
GL0
Reserved
GR4
GR3
GR2
GR1
GR0
8808h
GL1
GL0
Reserved
GR4
GR3
GR2
GR1
GR0
8808h
SR2
SR1
SR0
0000h
GR3
GR2
GR1
GR0
8000h
Reserved
Reserved
Reserved
boosten RSRVD
8008h
1Ah
Record Select
1Ch
Record Gain
Mute
20h
General
Purpose
POP
BYP
22h
3D Control
24h
Audio Int. &
Paging
I4
I3
I2
I1
I0
26h
Powerdownn
Ctrl/Stat
EAPD
PR6
PR5
PR4
PR3
PR2
PR1
PR0
28h
Extended
Audio ID
ID1
ID0
REV1
REV0
AMAP
LDAC
2Ah
Extended
Audio
Control/Status
VCFG
2Ch
PCM DAC
Rate
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
SR2
32h
PCM LR
ADC Rate
SR15
SR14
SR13
SR12
SR11
SR10
SR9
SR8
SR7
SR6
SR5
SR4
SR3
3Ah
SPDIF Control
V
DRS
L
CC6
CC5
CC4
CC3
CC2
CC1
CC0
PRE
3Eh
Extended
Modem Status
4Ch
GPIO Pin
Config
Reserved
GC1
GC0
0300h
(GPIO1) (GPIO0)
4Eh
GPIO Pin
Polarity/Type
Reserved
GP1
GP0
FFFFh
(GPIO1) (GPIO0)
50h
GPIO Pin
Sticky
Reserved
GS1
GS0
0000h
(GPIO1) (GPIO0)
52h
GPIO Pin
Mask
Reserved
GW1
GW0
0000h
(GPIO1) (GPIO0)
54h
GPIO Pin
Status
Reserved
GI1
GI0
0000h
(GPIO1) (GPIO0)
60h
Page
01h
CODEC
Class/Rev
RSRVD
Reserved
Reserved
Reserved
SDAC
CDAC
DSA1
DSA0
0000h
DP3
DP2
Reserved
PG3
PG2
PG1
PG0
0000h
REF
ANL
DAC
ADC
000Fh
RSVD
SPDIF
DRA
VRA
0A05h
VRA
0400h*
SR1
SR0
BB80h
SR2
SR1
SR0
BB80h
COPY
#PCM/A
UDIO
PRO
2000h
GPIO
0100h
PRL/RS PRK/RS PRJ/RS PRI/RS
MADC/ LDAC/R SDAC/R CDAC/
VRM/R
DRA/RS
SPCV
SPSA1 SPSA0
SPDIF
VD
VD
VD
VD
RSVD
SVD
SVD
RSVD
SVD
VD
SPSR1 SPSR2
Reserved
Reserved
CL4
PRA
CL3
CL2
CL1
CL0
Reserved
RV7
0000h
RV6
RV5
RV4
RV3
RV2
RV1
RV0
12xxh
PVI6
PVI5
PVI4
PVI3
PVI2
PVI1
PVI0
FFFFh
PI6
PI5
PI4
PI3
PI2
PI1
PI0
FFFFh
FC3
FC2
FC1
FC0
T/R
0000h
FIP
xxxxh
VENDOR Reserved
PCI SVID
PVI15
PVI14
PVI13
PVI12
PVI11
PVI10
PVI9
PVI8
PVI7
VENDOR Reserved
PCI SID
PI15
PI14
PI13
PI12
PI11
PI10
PI9
66h
66h
Page
01h
LPBK
Reserved
64h
64h
Page
01h
Reserved
Reserved
62h
62h
Page
01h
Reserved
RSRVD 0000h
PI8
PI7
VENDOR Reserved
Function
Select
Reserved
68h
VENDOR Reserved
68h
Page
01h
Function
Information
6Ah
Digital Audio
Control
6Ah
Page
01h
Sense Details
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
G4
G3
G2
G1
G0
INV
DL4
DL3
DL2
DL1
DL0
IV
Reserved
Reserved
ST2
ST1
ST0
S4
S3
S2
97
S1
S0
OR1
OR0
SR5
SR4
SR3
SPOR
DO1
RSVD
0000h
SR2
SR1
SR0
NA
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
Reg #
Name
6Ch
Revision Code
D15
D14
D13
D12
D11
D10
D9
D6
D5
D4
D3
D2
D1
D0
Default
xxxxh
Reserved
Analog Special
AC97
ALL
MIX
Reserved
MUTE
FIX
DISBLE
Reserved
6Eh
Page
01h
ADC
slot1
ADC
slot0
RSVD
MIC
GAIN
VALUE
SPLY
OVR
EN
SPLY
OVR
VAL
1000h
Reserved
70h
72h
D7
xxxx
6Ch
Page
01h
6Eh
D8
VENDOR Reserved
Analog Current
Adjust
74h
EAPD Access
76h
Regsiter 78
Enable
78h
Universal
Jack™ Select
EAPD
EAPD_
OEN
Reserved
0000h
INT
APOP
Reserved
Reserved
Reserved
0000h
INTDIS
GPIO
ACC
GPIO
SLT12
EN15:0
HP Sel
LO Sel
RSVD
LI Sel
MIC Sel
0800h
0000h
STMIC
MS
HP3dB
SEL PWDN
DAC
BYHP
DAC
BYLO
RSVD
RSVD
ADC
HPF
BYP
0000h
7Ah
Reserved
7Ch
Vendor ID1
1
0
0
0
0
0
1
VENDOR Reserved
1
1
0
0
0
0
1
0
0
8384h
0000h
7Eh
Vendor ID2
9752
0
1
1
1
0
1
1
0
0
1
0
0
0
0
1
0
7652h
*depends upon chip ID
TSI™ CONFIDENTIAL
©2014 TEMPO SEMICONDCUTOR, INC.
98
V 1.6 10/14
STAC9752A/9753A
STAC9752A/9753A
AC’97 2.3 CODECs with Stereo Microphone & Universal Jack
16. REVISION HISTORY
Revision
Date
Description of Change
0.9
Inital Release
0.91
Corrected Note 4 in performance characteristics, was missing the text “Ratio of Full Scale
signal toTHD+N output with -3dB signal, measured “A weighted” over a”. Complete note
now reads “Ratio of Full Scale signal toTHD+N output with -3dB signal, measured “A
weighted” over a 20 Hz to a 20 KHz bandwidth. 48 KHz Sample Frequency”.
0.92
Added updated 32-pin package drawing
0.93
Added more 32-pin package information - Recommended PCB Layout. Added pull-up/
pull-down column to pin characteristics table.
0.94
Corrected pin 40 LQFP 48-pin package error. It is not a Headphone_Comm, but is a no
connect.
1.0
Removed “Preliminary” from the Datasheet.
1.1
Updated 48-pin and 32-pin package drawings. Updated reflow profile information.
1.2
Revised reflow profile information.
1.3
Updated Logo. Updated 32-pin package drawing.
1.4
30 October 2006
1.5
Dec 2006
1.6
October 2014
Release in IDT format.
corrected orderable part numbers and added note.
Released in TSI format
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herein at any time and at TSI’s sole discretion. All information in this document, including descriptions of product features and performance, is
subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the
independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is
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