Intel® Server Board S3420GP

Intel® Server Board S3420GP

Technical Product Specification

Intel order number E65697-010

Revision 2.4

January, 2011

Enterprise Platforms and Services Division - Marketing

Revision History Intel® Server Board S3420GP TPS

Revision History

Date

Feb. 2009

May 2009

July. 2009

Aug. 2009

Nov. 2009

Dec. 2009

Dec. 2009

Jan. 2010

Apr. 2010

1.2

2.0

2.1

2.2

Revision

Number

0.3

0.5

0.9

1.0

1.1

Modifications

Initial release.

Update block diagram.

Updated POST error code and diagram.

Updated MTBF.

Additional details for memory configuration.

Added Intel

®

Server Board S3420GPV details.

Updated processor name.

Corrected the typo.

Corrected the typo, updated processor name and remove CCC certification marking information.

July. 2010 2.3 Corrected the typo.

Jan.2011 2.4 

Corrected the typo. Added RDIMM support on S3420GPV.



Updated Table 45.



Add USB device readiness beep code information. ii

Intel order number E65697-010

Intel® Server Board S3420GP TPS Disclaimers

Disclaimers

Information in this document is provided in connection with Intel

®

products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

.

Designers must not rely on the absence or characteristics of any features or instructions marked

"reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel

®

Server Board S3420GP may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.

Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel’s own chassis are designed and tested to meet the intended thermal requirements of these components when the fully integrated system is used together. It is the responsibility of the system integrator that chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.

Intel, Pentium, Itanium, and Xeon are trademarks or registered trademarks of Intel Corporation.

*Other brands and names may be claimed as the property of others.

Copyright © 2011 Intel Corporation

Revision 2.4 iii


Table of Contents Intel® Server Board S3420GP TPS

Table of Contents

1. Introduction ............................................................................................................................ 1

1.1 Chapter Outline ......................................................................................................... 1

1.2 Server Board Use Disclaimer .................................................................................... 1

2. Overview ................................................................................................................................. 2

2.1 Intel

®

Server Board S3420GP Feature Set ............................................................... 2

2.2 Server Board Layout ................................................................................................. 5

2.2.1 Server Board Connector and Component Layout .................................................... 6

2.2.2 Intel

®

Server Board S3420GP Mechanical Drawings ............................................... 8

2.2.3 Server Board Rear I/O Layout ................................................................................ 14

3. Functional Architecture ....................................................................................................... 15

3.1 Processor Sub-System ........................................................................................... 17

3.1.1 Intel

®

Xeon

®

Processor 3400 Series ....................................................................... 17

3.1.2 Intel

®

Core

TM

Processor i3-500 Series and Intel

®

Pentium

®

Processor G6950 ...... 17

3.1.3 Intel

®

Turbo Boost Technology ............................................................................... 17

3.1.4 Simultaneous Multithreading (SMT) ....................................................................... 18

3.1.5 Enhanced Intel SpeedStep

®

Technology ................................................................ 18

3.2 Memory Subsystem................................................................................................. 18

3.2.1 Memory Sizing and Configuration ........................................................................... 18

3.2.2 Post Error Codes ..................................................................................................... 19

3.2.3 Publishing System Memory .................................................................................... 20

3.2.4 Memory Map and Population Rules ........................................................................ 21

3.3 Intel

®

3420 Chipset PCH ......................................................................................... 24

3.4 I/O Sub-system ........................................................................................................ 25

3.4.1 PCI Express Interface ............................................................................................. 25

3.4.2 Serial ATA Support .................................................................................................. 26

3.4.3 USB 2.0 Support ..................................................................................................... 26

3.5 Optional Intel

®

SAS Entry RAID Module AXX4SASMOD ....................................... 27

3.6 Integrated Baseboard Management Controller ...................................................... 27

3.6.1 Integrated BMC Embedded LAN Channel .............................................................. 29

3.6.2 Optional RMM3 Advanced Management Board ..................................................... 29

3.6.3 Serial Ports .............................................................................................................. 30

3.6.4 Floppy Disk Controller ............................................................................................. 30

3.6.5 Keyboard and Mouse Support ................................................................................ 30

3.6.6 Wake-up Control ..................................................................................................... 31

3.7 Video Support .......................................................................................................... 31

3.7.1 Intel

®

Server Board S3420GPLX and Intel

®

Server Board S3420GPLC ............... 31

3.7.2 Video for Intel

®

Server Board S3420GPV ............................................................... 32

3.8 Network Interface Controller (NIC) ......................................................................... 33

3.8.1 GigE Controller 82574L ........................................................................................... 33 iv


Intel® Server Board S3420GP TPS Table of Contents

3.8.2

GigE PHY 82578DM ............................................................................................... 33

3.8.3 MAC Address Definition .......................................................................................... 33

3.9 Intel

®

I/O Acceleration Technology 2 (Intel

®

I/OAT2) ............................................. 34

3.9.1 Direct Cache Access (DCA) .................................................................................... 34

3.10 Intel

®

Virtualization Technology for Directed I/O (Intel

®

VT-d) ................................ 34

4. Platform Management ......................................................................................................... 35

4.1 Feature Support ...................................................................................................... 35

4.1.1 IPMI 2.0 Features .................................................................................................... 35

4.1.2 Non-IPMI Features .................................................................................................. 36

4.2 Optional Advanced Management Feature Support ................................................ 37

4.2.1 Enabling Advanced Management Features ........................................................... 37

4.2.2 Keyboard, Video, Mouse (KVM) Redirection .......................................................... 37

4.2.3 Media Redirection ................................................................................................... 38

4.2.4 Web Services for Management (WS-MAN) ............................................................ 38

4.2.5 Local Directory Authentication Protocol (LDAP) ..................................................... 39

4.2.6 Embedded Webserver ............................................................................................ 39

4.3 Management Engine (ME) ...................................................................................... 39

5. Server Management Capability for Intel® Server Board S3420GPV .............................. 40

5.1 Super I/O ................................................................................................................. 40

5.1.1 Key Features of Super I/O ...................................................................................... 40

5.1.2 Sensor and Hardware Monitor ................................................................................ 40

5.1.3 Fan controller (Manual) ........................................................................................... 42

5.1.4 Voltage and Temperature Status Screen ............................................................... 44

5.2 SMBIOS ................................................................................................................... 45

5.2.1 Data Storage ........................................................................................................... 45

5.3 Event log and Viewer .............................................................................................. 45

5.3.1 Event Log Viewer in Setup ...................................................................................... 45

6. BIOS User Interface ............................................................................................................. 47

6.1 Logo/Diagnostic Screen .......................................................................................... 47

6.2

6.3

BIOS Boot Popup Menu .......................................................................................... 47

BIOS Setup utility .................................................................................................... 47

6.3.1 Operation ................................................................................................................. 48

6.3.2 Server Platform Setup Utility Screens .................................................................... 50

6.4 Loading BIOS Defaults ............................................................................................ 74

7. Connector/Header Locations and Pin-outs ...................................................................... 76

7.1

7.2

Board Connector Information .................................................................................. 76

Power Connectors ................................................................................................... 76

7.3 System Management Headers ............................................................................... 77

7.3.1 Intel

®

Remote Management Module 3 (Intel

®

RMM3) Connector .......................... 77

7.3.2 LCP/IPMB Header ................................................................................................... 78

7.3.3 HSBP Header .......................................................................................................... 78

Revision 2.4 v


Table of Contents Intel® Server Board S3420GP TPS

7.3.4 SGPIO Header ........................................................................................................ 79

7.4 Front Control Panel Connector ............................................................................... 79

7.4.1 Power Button ........................................................................................................... 80

7.4.2 Reset Button ............................................................................................................ 80

7.4.3 NMI Button ............................................................................................................... 80

7.4.4 System Status Indicator LED .................................................................................. 80

7.5 I/O Connectors ........................................................................................................ 81

7.5.1 VGA Connector ....................................................................................................... 81

7.5.2 Rear NIC and USB connector ................................................................................. 82

7.5.3 SATA ....................................................................................................................... 83

7.5.4 50-pin PCI Express* Connector .............................................................................. 83

7.5.5 Serial Port Connectors ............................................................................................ 84

7.5.6 USB Connector ....................................................................................................... 84

7.6 PCI Express* Slot/PCI Slot/Riser Card Slot / ......................................................... 85

7.7 Fan Headers ............................................................................................................ 90

8. Jumper Blocks...................................................................................................................... 91

8.1 CMOS Clear and Password Reset Usage Procedure ............................................ 92

8.1.1 Clearing the CMOS ................................................................................................. 92

8.1.2 Clearing the Password ............................................................................................ 92

8.2 Integrated BMC Force Update Procedure (only for the Intel

®

Server Board

S3420GPLX and S3420GPLC) ................................................................................................. 93

8.3 ME Force Update Jumper ....................................................................................... 93

8.4 BIOS Recovery Jumper .......................................................................................... 94

9. Intel

®

Light Guided Diagnostics ......................................................................................... 95

9.1 System Status LED (For the Intel

®

Server Board S3420GPLX and S3420GPLC) 95

9.2 Post Code Diagnostic LEDs .................................................................................... 96

10. Design and Environmental Specifications ........................................................................ 97

10.1 Intel

®

Server Board S3420GP Design Specifications ............................................. 97

10.2 Board-level Calculated MTBF ................................................................................. 97

10.3 Server Board Power Requirements ........................................................................ 98

10.3.1 Processor Power Support ....................................................................................... 98

10.4 Power Supply Output Requirements ...................................................................... 99

10.4.1 Grounding ................................................................................................................ 99

10.4.2 Standby Outputs ...................................................................................................... 99

10.4.3 Remote Sense ......................................................................................................... 99

10.4.4 Voltage Regulation ................................................................................................ 100

10.4.5 Dynamic Loading ................................................................................................... 100

10.4.6 Capacitive Loading ................................................................................................ 100

10.4.7 Closed-loop Stability ............................................................................................. 100

10.4.8 Common Mode Noise ........................................................................................... 101

10.4.9 Ripple/Noise .......................................................................................................... 101 vi


Intel® Server Board S3420GP TPS Table of Contents

10.4.10 Timing Requirements ............................................................................................ 101

10.4.11 Residual Voltage Immunity in Standby Mode ....................................................... 103

10.4.12 Protection Circuits ................................................................................................. 103

11. Regulatory and Certification Information ........................................................................ 105

11.1 Product Regulatory Compliance ........................................................................... 105

11.1.1 Product Safety Compliance .................................................................................. 105

11.1.2 Product EMC Compliance – Class A Compliance ................................................ 105

11.1.3 Certifications/Registrations/Declarations .............................................................. 106

11.1.4 Product Ecology Requirements ............................................................................ 106

11.2 Product Regulatory Compliance Markings ........................................................... 107

11.3 Electromagnetic Compatibility Notices ................................................................. 109

11.3.1 FCC Verification Statement (USA) ....................................................................... 109

11.3.2 ICES-003 (Canada) ............................................................................................... 110

11.3.3 Europe (CE Declaration of Conformity) ................................................................ 110

11.3.4 VCCI (Japan) ......................................................................................................... 110

11.3.5 BSMI (Taiwan) ....................................................................................................... 111

11.3.6 RRL (Korea) .......................................................................................................... 111

Appendix A: Integration and Usage Tips ............................................................................... 112

Appendix B: Integrated BMC Sensor Tables ......................................................................... 113

Appendix C: POST Code Diagnostic LED Decoder .............................................................. 119

Appendix D: POST Code Errors .............................................................................................. 123

Appendix E: Supported Intel

®

Server Chassis ...................................................................... 128

Glossary ..................................................................................................................................... 129

Reference Documents .............................................................................................................. 132

Revision 2.4 vii


List of Figures Intel® Server Board S3420GP TPS

List of Figures

Figure 1. Intel

®

Server Board S3420GPLX Picture ........................................................................ 5

Figure 2. Intel

®

Server Board S3420GP Layout ............................................................................. 6

Figure 3. Intel

®

Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION 8

Figure 4. Intel

®

Server Board S3420GP – Hole and Component Positions .................................. 9

Figure 5. Intel

®

Server Board S3420GP – Major Connector Pin Location (1 of 2) ...................... 10

Figure 6. Intel

®

Server Board S3420GP –Major Connector Pin Location (2 of 2) ....................... 11

Figure 7. Intel

®

Server Board S3420GP – Primary Side Keepout Zone ...................................... 12

Figure 8. Intel

®

Server Board S3420GP – Secondary Side Keepout Zone ................................. 13

Figure 9. Intel

®

Server Board S3420GP Rear I/O Layout ............................................................ 14

Figure 10. Intel

®

Server Board S3420GP Functional Block Diagram For S3420GPLX .............. 15

Figure 11. Intel

®

Server Board S3420GP Functional Block Diagram From S3420GPLC ........... 16

Figure 12. Intel

®

Server Board S3420GP Functional Block Diagram From S3420GPV ............. 17

Figure 13. Integrated BMC Hardware .......................................................................................... 29

Figure 14. Server Management Bus (SMBUS) Block Diagram ................................................... 35

Figure 15. Setup Utility — Hardware Monitor Screen Display ..................................................... 41

Figure 16. Setup Utility — Fan controller (Manual) Display ......................................................... 43

Figure 17. Setup Utility — Voltage and Temperature Status Screen .......................................... 44

Figure 18. Event Log Viewer ........................................................................................................ 46

Figure 19. Setup Utility – Main Screen Display ............................................................................ 51

Figure 20. Setup Utility – Advanced Screen Display ................................................................... 53

Figure 21. Setup Utility – Processor Configuration Screen Display ............................................ 54

Figure 22. Setup Utility – Memory Configuration Screen Display ................................................ 56

Figure 23. Setup Utility – Mass Storage Controller Configuration Screen Display ..................... 58

Figure 24. Setup Utility – Serial Port Configuration Screen Display ............................................ 59

Figure 25. Setup Utility – USB Controller Configuration Screen Display .................................... 60

Figure 26. Setup Utility – PCI Configuration Screen Display ....................................................... 62

Figure 27. Setup Utility – System Acoustic and Performance Configuration Screen Display ..... 63

Figure 28. Setup Utility – Security Configuration Screen Display ................................................ 64

Figure 29. Setup Utility – Server Management Configuraiton Screen Display ............................ 66

Figure 30. Setup Utility – Console Redirection Screen Display ................................................... 67

Figure 31. Setup Utility – Server Management System Information Screen Display .................. 69

Figure 32. Setup Utility – Boot Options Screen Display .............................................................. 70

Figure 33. Setup Utility – Delete Boot Option Screen Display ..................................................... 71

Figure 34. Setup Utility — Hard Disk Order Screen Display ........................................................ 72

Figure 35. Setup Utility – CDROM Order Screen Display ........................................................... 72

Figure 36. Setup Utility — Floppy Order Screen Display ............................................................. 73

Figure 37. Setup Utility – Network Device Order Screen Display ................................................ 73

Figure 38. Setup Utility – Boot Manager Screen Display ............................................................. 74

Figure 39. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5) .................................................. 91

viii


Intel® Server Board S3420GP TPS List of Figures

Figure 40. Power Distribution Block Diagram .............................................................................. 98

Figure 41. Output Voltage Timing............................................................................................... 102

Figure 42. Turn On/Off Timing (Power Supply Signals) ............................................................ 103

Figure 43. Diagnostic LED Placement Diagram ........................................................................ 119

Revision 2.4 ix


List of Tables Intel® Server Board S3420GP TPS

List of Tables

Table 1. Intel

®

Server Board S3420GP Feature Set ...................................................................... 2

Table 2. Major Board Components ................................................................................................ 7

Table 3. Standard Platform DIMM Nomenclature ........................................................................ 21

Table 4. Memory Configuration Table .......................................................................................... 22

Table 5. UDIMM memory configuration rule ................................................................................ 23

Table 6. UDIMM Maximum configuration ..................................................................................... 23

Table 7. RDIMM memory configuration rule ................................................................................ 24

Table 8. RDIMM Maximum configuration ..................................................................................... 24

Table 9. Optional RMM3 Advanced Management Board Features ............................................. 30

Table 10. Serial B Header (J1B1) Pin-out .................................................................................... 30

Table 11. Video Modes ................................................................................................................. 31

Table 12. Dual Video Modes ........................................................................................................ 32

Table 13. Setup Utility — Hardware Monitor Screen Fields ........................................................ 41

Table 14. Setup Utility — Hardware Monitor Screen Fields ........................................................ 43

Table 15. Setup Utility — Voltage and Temperature Status Fields ............................................. 44

Table 16. BIOS Setup Page Layout ............................................................................................. 48

Table 17. BIOS Setup: Keyboard Command Bar ........................................................................ 49

Table 18. Setup Utility – Main Screen Fields ............................................................................... 51

Table 19. Setup Utility – Advanced Screen Display Fields .......................................................... 53

Table 20. Setup Utility – Processor Configuration Screen Fields ................................................ 54

Table 21. Setup Utility – Memory Configuration Screen Fields ................................................... 56

Table 22. Setup Utility – Mass Storage Controller Configuration Screen Fields ......................... 58

Table 23. Setup Utility – Serial Ports Configuration Screen Fields ............................................. 59

Table 24. Setup Utility – USB Controller Configuration Screen Fields ........................................ 61

Table 25. Setup Utility – PCI Configuration Screen Fields .......................................................... 62

Table 26. Setup Utility – System Acoustic and Performance Configuration Screen Fields ........ 63

Table 27. Setup Utility – Security Configuration Screen Fields ................................................... 64

Table 28. Setup Utility – Server Management Configuration Screen Fields ............................... 66

Table 29. Setup Utility – Console Redirection Configuration Fields ............................................ 68

Table 30. Setup Utility – Server Management System Information Fields .................................. 69

Table 31. Setup Utility – Boot Options Screen Fields .................................................................. 70

Table 32. Setup Utility – Delete Boot Option Fields ..................................................................... 72

Table 33. Setup Utility — Hard Disk Order Fields ........................................................................ 72

Table 34. Setup Utility – CDROM Order Fields............................................................................ 73

Table 35. Setup Utility — Floppy Order Fields ............................................................................. 73

Table 36. Setup Utility – Network Device Order Fields ................................................................ 74

Table 37. Setup Utility – Boot Manager Screen Fields ................................................................ 74

Table 38. Board Connector Matrix ............................................................................................... 76

Table 39. Baseboard Power Connector Pin-out (J9A1) ............................................................... 77 x


Intel® Server Board S3420GP TPS List of Tables

Table 40. SSI Processor Power Connector Pin-out (J9C1) ......................................................... 77

Table 41. Intel

®

RMM3 Connector Pin-out (J2C1) ....................................................................... 78

Table 42. LPC/IPMB Header Pin-out (J1H2) ............................................................................... 78

Table 43. HSBP Header Pin-out (J1J1) ....................................................................................... 78

Table 44. SGPIO Header Pin-out (J1J3) ...................................................................................... 79

Table 45. Front Panel SSI Standard 24-pin Connector Pin-out (J1C1) ....................................... 79

Table 46. System Status LED Indicator States ............................................................................ 80

Table 47. VGA Connector Pin-out (J7A1) .................................................................................... 81

Table 48. RJ-45 10/100/1000 NIC Connector Pin-out (J5A1) ..................................................... 82

Table 49. RJ-45 10/100/1000 NIC Connector Pin-out (J6A1) ..................................................... 82

Table 50. SATA Connector Pin-out (J1H4, J1H1, J1G1, J1H3, J1G3, J1F4) ............................. 83

Table 51. 50-pin PCI Express* Connector Pin-out (J2H1) ........................................................... 83

Table 52. External Serial A Port Pin-out (J8A1) ........................................................................... 84

Table 53. Internal 9-pin Serial B Header Pin-out (J1B2) ............................................................. 84

Table 54. Internal USB Connector Pin-out ( J1E1, J1D1) ........................................................... 84

Table 55. Pin-out of Internal USB Connector for Floppy ( J1J2) ................................................. 85

Table 56. Pin-out of Internal USB Connector for low-profile Intel

®

Z-U130 Value Solid State

Drive (J3F2) ............................................................................................................................ 85

Table 57. Pin-out of adaptive riser slot/PCI Express slot 6 .......................................................... 85

Table 58. SSI 4-pin Fan Header Pin-out (J6D1, J1J4, J6J2, J7J1, J6B1) .................................. 90

Table 59. Server Board Jumpers (J1F1, J1F2, J1F3, J1F5, J1A2) ............................................. 91

Table 60. Front Panel Status LED Behavior Summary................................................................ 95

Table 61. POST Code Diagnostic LED Location ......................................................................... 96

Table 62. Server Board Design Specifications............................................................................. 97

Table 63. Intel

®

Xeon

®

Processor TDP Guidelines ...................................................................... 98

Table 64. 350-W Load Ratings ..................................................................................................... 99

Table 65. Voltage Regulation Limits ........................................................................................... 100

Table 66. Transient Load Requirements .................................................................................... 100

Table 67. Capacitve Loading Conditions ................................................................................... 100

Table 68. Ripple and Noise ........................................................................................................ 101

Table 69. Output Voltage Timing ................................................................................................ 101

Table 70. Turn On/Off Timing ..................................................................................................... 102

Table 71. Over-Current Protection (OCP) .................................................................................. 104

Table 72. Over-voltage Protection (OVP) Limits ........................................................................ 104

Table 73. Integrated BMC Core Sensors ................................................................................... 115

Table 74. POST Progress Code LED Example ......................................................................... 119

Table 75. Diagnostic LED POST Code Decoder ....................................................................... 120

Table 76. POST Error Messages and Handling ......................................................................... 123

Table 77. POST Error Beep Codes ............................................................................................ 127

Revision 2.4 xi


List of Tables

<This page is intentionally left blank.>

Intel® Server Board S3420GP TPS xii


Intel® Server Board S3420GP TPS Introduction

1. Introduction

This Technical Product Specification (TPS) provides board specific information detailing the features, functionality, and high-level architecture of the Intel

®

Server Board S3420GP.

In addition, you can obtain design-level information for specific subsystems by ordering the

External Product Specifications (EPS) or External Design Specifications (EDS) for a given subsystem. EPS and EDS documents are not publicly available and must be ordered through your local Intel representative.

1.1 Chapter Outline

This document is divided into the following chapters:





































Chapter 1 – Introduction

Chapter 2 – Server Board Overview

Chapter 3 – Functional Architecture

Chapter 4 – Platform Management

Chapter 5 – BIOS User Interface

Chapter 6 – Connector/Header Locations and Pin-outs

Chapter 7 – Jumpers Blocks

Chapter 8 – Intel

®

Light-Guided Diagnostics

Chapter 9 – Design and Environmental Specifications

Chapter 10 – Regulatory and Certification Information

Chapter 11 – Regulatory and Certification Information

Appendix A – Integration and Usage Tips

Appendix B – Integrated BMC Sensor Tables

Appendix C – POST Code Diagnostic LED Decoder

Appendix D – POST Code Errors

Appendix E – Supported Intel

®

Server Chassis

Glossary

Reference Documents

1.2 Server Board Use Disclaimer

Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system meets the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.

Revision 2.4 1


Overview Intel® Server Board S3420GP TPS

2. Overview

The Intel

®

Server Board S3420GP is a monolithic printed circuit board (PCB) with features designed to support entry-level severs. It has three board SKUs: S3420GPLX, S3420GPLC, and S3420GPV.

2.1 Intel

®

Server Board S3420GP Feature Set

Table 1. Intel

®

Server Board S3420GP Feature Set

Feature

Processor

Memory

Chipset

I/O

Support for one Xeon

Series or Intel

®

®

Description

Processor 3400 Series or Intel

®

Pentium

®

Core

TM

Processor i3-500

Processor G6950 in FC-LGA 1156 socket package.

 2.5 GT/s point-to-point DMI interface to PCH

 LGA 1156 pin socket

Two memory channels with support for 1066/1333 MHz ECC Unbuffered (UDIMM) or

ECC Registered (RDIMM) (Intel

®

Xeon

®

Processor 3400 Series only) DDR3.

Intel

®

Server Board S3420GPLX and S3420GPLC

 Up to 2 UDIMMs or 3 RDIMM (Intel per channel

®

Xeon

®

Processor 3400 Series only)

 32 GB max with x8 ECC RDIMM (2 Gb DRAM) and 16 GB max with x8

ECC UDIMM (2 Gb DRAM)

Intel

®

Server Board S3420GPV

 Up to 2 UDIMMs or 2 RDIMM (Intel per channel

®

Xeon

®

Processor 3400 Series only)



16 GB max with x8 ECC UDIMM (2 Gb DRAM) and 16 GB max with x8

ECC RDIMM (2 Gb DRAM)

Intel

®

Server board S3420GPLX

 Support for Intel

®

3420 Chipset Platform Controller Hub (PCH)

 ServerEngines* LLC Pilot II BMC controller (Integrated BMC)

 PCI switch

Intel

®

Server board S3420GPLC


®


 ServerEngines* LLC Pilot II BMC controller (Integrated BMC)

Intel

®

Server board S3420GPV


®


External connections:

 DB-15 video connectors

 DB-9 serial Port A connector

 Four ports on two USB/LAN combo connectors at rear of board.

Internal connections:

 Two USB 2x5 pin headers, each supporting two USB 2.0 ports (Only one header for Intel

®

Server board S3420GPV)



One 2x5 Serial Port B header (Intel

S3420GPLC)

®

Server board S3420GPLX and

 Six SATA II connectors

 One connector supports for optional Intel

®

(Intel

®

Server board S3420GPLX)

Remote Management Module 3

2


Intel® Server Board S3420GP TPS Overview

Feature

Add-in PCI Card, PCI

Express* Card

System Fan Support

Video

Onboard Hard Drive

RAID Support

LAN

Description

Intel

®

Server Board S3420GPLX

 Slot1: One 3.3V/5V PCI 32 bit/33 MHz connector.

 Slot2: One PCI Express* Gen1 x4 (x1 throughput) connector.





Intel

®

Server Board S3420GPLC/ S3420GPV

 Slot1: One 3.3V/5V PCI 32 bit/33 MHz connector.




Five 4-pin fan headers supporting four system fans and one processor.

Intel

®

Server Board S3420GPLX/ S3420GPLC

 Onboard ServerEngines* LLC Pilot II BMC Controller

 Integrated 2D Video Controller with 8MB Video Memory

 64-MB DDR2 667 MHz Memory

Intel

®




Silicon Motion SM712GX04LF02-BA

Support for six Serial ATA II hard drives through six onboard SATA II connectors with

SW RAID 0, 1, 5, and 10.

Intel

®

Server Board S3420GPLX:

 Up to four SAS hard drives through option Intel

® card

SAS Entry RAID Module

Intel

®

Server Board S3420GPLX /S3420GPLC/S3420GPV

 Intel

®

Rapid Storage RAID through onboard SATA connectors provides

SATA RAID 0, 1, 5 and 10.

 Intel

®

Embedded Server RAID Technology II through onboard SATA connectors provides SATA RAID 0, 1, and 10.

Intel

®




Intel

®

Embedded Server RAID Technology II through optional Intel

®

SAS

Entry RAID Module AXX4SASMOD provides SAS RAID 0, 1, and 10 with optional RAID 5 support provided by the Intel

®

RAID Activation Key

AXXRAKSW5

 IT/IR RAID through optional Intel

®

SAS Entry RAID Module AXX4SASMOD provides entry level hardware RAID 0, 1, 10, and native SAS pass through mode

 Four ports full featured SAS/SATA hardware RAID through optional Intel

®

Integrated RAID Module SROMBSASMR (AXXROMBSASMR) provides

RAID 0, 1, 5, 6 and striping capability for spans 10, 50, 60.

 One Gigabit Ethernet device 82574L connect to PCI-E x1 interfaces on the

PCH.

 One Gigabit Ethernet PHY 82578DM connected to PCH through PCI-E x1 interface.

Revision 2.4 3


Overview

Feature

Server Management

Intel® Server Board S3420GP TPS

Intel

®

Description

Server Board S3420GPLX/S3420GPLC:

Onboard LLC Pilot II Controller (iBMC)

 Integrated Baseboard Management Controller (Integrated BMC), IPMI 2.0 compliant

 Integrated 2D video controller on PCI-E x1

Intel

®


 Intel

®

Remote Management Module III (RMM3)

4



2.2 Server Board Layout

Overview

Revision 2.4

Figure 1. Intel

®

Server Board S3420GPLX Picture


5

DD

CC

BB


2.2.1 Server Board Connector and Component Layout

The following figure shows the board layout of the server board. Each connector and major component is identified by a number or letter, and Table 2 provides the description.

A B C D E F G H I J

K

L M

N

O

P

AA

Z

Y

X

W

V

U

T S R Q

AF003290

Figure 2. Intel

®

Server Board S3420GP Layout

6



Table 2. Major Board Components

Description

A Slot 1, 32 Mbit/33 MHz PCI

B Slot 2, PCI Express* Gen1 x1 (x4 connector)

(Intel Server Board S3420GPLX only)

C Intel RMM3 Connector(Intel Server Board

S3420GPLX only)

D Slot 3, PCI Express* Gen1 x4 (PCI Express*

Gen2 compliant)

E Slot 4, PCI Express* Gen2 x4 (x8 connector)

(x8 connector)( Intel only)

®


F Slot 5. PCI Express* Gen2 x8 (x8 connector)

G Slot 6, PCI Express* Gen2 x8 (x16 connector)

I Ethernet and Dual USB COMBO

J Ethernet and Dual USB COMBO

K System FAN 4

L Video port

M External Serial port

N Main Power Connector

O CPU Power connector

P DIMM slots (4 slots on Intel

S3420GPV)

®

Server Board

Q

S

T

U

Description

System FAN2 and System FAN 3

CPU Fan connector

USB SSD connector (Intel

®

Server Board

S3420GPLX and S3420GPLC)

50-pin PCI Express* connector (Intel

®

S3420GPLX only)

Server Board

V System FAN 1 (Intel

® and S3420GPLC)


W IPMB(Intel

®

Server Board S3420GPLX and

S3420GPLC)

X SATA_SGPIO

Y HSBP (Intel

®


S3420GPLC)

Z USB Floppy (Intel

®

S3420GPLC)


AA Six SATA ports

BB Internal USB Connector ( One for Internal USB header on Intel

®

Server Board S3420GPV)

CC Front Panel Connector

DD Internal Serial Port (Intel and S3420GPLC)

®


Revision 2.4


7

Overview

2.2.2 Intel

®

Server Board S3420GP Mechanical Drawings


Figure 3. Intel

®

Server Board S3420GP – Key Connector and LED Indicator IDENTIFICATION

8



Figure 4. Intel

®

Server Board S3420GP – Hole and Component Positions

Revision 2.4


9


Figure 5. Intel

®

Server Board S3420GP – Major Connector Pin Location (1 of 2)

10



Figure 6. Intel

®

Server Board S3420GP –Major Connector Pin Location (2 of 2)

Revision 2.4


11


Figure 7. Intel

®

Server Board S3420GP – Primary Side Keepout Zone

12



Figure 8. Intel

®

Server Board S3420GP – Secondary Side Keepout Zone

Revision 2.4


13


2.2.3 Server Board Rear I/O Layout

The following figure shows the layout of the rear I/O components for the server board.

A Serial Port A

B Video

C NIC Port 1 (1 Gb) and Dual USB Port

Connector

D NIC port 2 (1 Gb) and Dual USB Port

Connector

Figure 9. Intel

®

Server Board S3420GP Rear I/O Layout

14


3. Functional Architecture

The architecture and design of the Intel

®

Server Board S3420GP is based on the Intel

®

3420

Chipset. The chipset is designed for systems based on the Intel

®

Xeon

® or Intel

®

Core

TM

i3-500 Desktop Processor Series or Intel

®

Pentium

®

Processor 3400 Series

Processor Processor

G6950in the FC-LGA 1156 socket package. The chipset contains two main components:





Intel

®

3420 Chipset

PCI Express* switch (Intel

®

Server Board S3420GPLX only).

This chapter provides a high-level description of the functionality associated with each chipset component and the architectural blocks that make up the server board.

Figure 10. Intel

®

Server Board S3420GP Functional Block Diagram For S3420GPLX

Revision 2.4


15

Functional Architecture Intel® Server Board S3420GP TPS


®

Server Board S3420GP Functional Block Diagram From S3420GPLC

16



®

Server Board S3420GP Functional Block Diagram From S3420GPV

3.1 Processor Sub-System

The Intel

®

Server Board S3420GP supports the following processor:





Intel

®

Xeon

®

Processor 3400 series

Intel

®

Core

TM

Processor i3-500 Desktop series

Intel

®

Pentium

®

Processor G6950



The Intel

®

Xeon

®

3400 Processor Series are made up of multi-core processors based on the 45 nm processor technology. The Intel

®

Core

TM


®

Pentium

®

Processor G6950are made up of dual core processor based on the 32 nm processor technology.

3.1.1 Intel

®

Xeon

®

Processor 3400 Series

The Intel

®

Xeon

®

Processor 3400 Series highly integrated solution variant is composed of four

Nehalem-based processor cores.





FC-LGA 1156 socket package with 2.5 GT/s.

Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not supported.

The server board does not support previous generations of the Intel

®

Xeon

®

processors.

3.1.2 Intel

®

Core

TM


®

Pentium

®

Processor G6950

The Intel

®

Duo Core

TM


®

Pentium integrated solution variant is composed of two processor cores.

®

Processor G6950 highly





FC-LGA 1156 socket package with 2.5 GT/s.

Up to 95 W Thermal Design Power (TDP); processors with higher TDP are not supported.

Please get the detail supported processor list from Intel website.

3.1.3 Intel

®

Turbo Boost Technology

Intel

®

Turbo Boost Technology is featured on certain processors in the Intel

®

3400 Series. Intel

®

Xeon

®

Processor

Turbo Boost Technology opportunistically and automatically allows the processor to run faster than the marked frequency if the processor is operating below power, temperature, and current limits. This results in increased performance for both multi-threaded and single-threaded workloads.

Intel

®

Turbo Boost Technology operation:



Turbo Boost operates under Operating System control – It is only entered when the operating system requests the highest (P0) performance state.



Turbo Boost operation can be enabled or disabled by BIOS.

Revision 2.4


17








Turbo Boost converts any available power and thermal headroom into higher frequency on active cores. At nominal marked processor frequency, many applications consume less than the rated processor power draw.

Turbo Boost availability is independent of the number of active cores.

Maximum Turbo Boost frequency depends on the number of active cores and varies by processor configuration.



The amount of time the system spends in Turbo Boost operation depends on workload, operating environment, and platform design.

If the processor supports the Intel

®

Turbo Boost Technology feature, the BIOS Setup provides an option to enable or disable this feature. The default state is enabled.

3.1.4 Simultaneous Multithreading (SMT)

Most Intel

®

Xeon

®

processors support Simultaneous Multithreading (SMT). The BIOS detects processors that support this feature and enables the feature during POST.

If the processor supports this feature, the BIOS Setup provides an option to enable or disable this feature. The default is enabled.

3.1.5 Enhanced Intel SpeedStep

®

Technology

Most processors support the Enhanced Intel SpeedStep

®

technology. This technology changes the processor operating ratio and voltage similar to the Thermal Monitor 1 (TM1) feature. The

BIOS implements this technology in conjunction with the TM1 feature.

The BIOS enables a combination of TM1 and TM2 according to the processor BIOS writer's guide.

3.2 Memory Subsystem

The Intel

®

Xeon

®

Processor 3400 Series has an Integrated Memory Controller (IMC) in its package. Each Intel

®

Xeon

®

Processor 3400 Series produces up to two DDR3 channels of memory. Each DDR3 channel in the IMC supports up to three DDR3 RDIMM slots or up to two

UDIMM slots. The DDR3 RDIMM frequency can be 800/1066/1333 MHz. DDR3 UDIMM frequency can be 1066/1333 MHz. All RDIMMs and UDIMMs include ECC (Error Correction

Code) operation. Various speeds and memory technologies are supported.

Note: Intel

®

Xeon

®

Processor L3406 only supports DDR3 Unbuffered DIMM (UDIMM).

The Intel

®

Core

TM


®

Pentium

®

Processor G6950 have an

Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. Only DDR3 UDIMM can be supported with the

Intel

®

Core

®

i3-500 Desktop Processor Series and Intel

®

Pentium

®

Processor G6950.

RAS (Reliability, Availability, and Serviceability) is not supported on the Intel

®

S3420GP.

Server Board

3.2.1 Memory Sizing and Configuration

The Intel

®

Server Board S3420GP supports various memory module sizes and configurations.

These combinations of sizes and configurations are valid only for DDR3 DIMMs approved by

Intel Corporation.

18


S3420GP supports:











DIMM sizes of 1 GB, 2 GB, 4 GB, and 8 GB.

DIMMs composed of DRAM using 2 Gb technology.

DRAMs organized as single rank, dual rank, or quad rank DIMMS.

DIMM speeds of 800, 1066, or 1333 MT/s.

Registered or Unregistered (unbuffered) DIMMs (RDIMMs or UDIMMs).

Note: UDIMMs should be ECC, and may or may not have thermal sensors; RDIMMs must have

ECC and must have thermal sensors.

S3420GP has the following limitations:

















256 Mb technology, x4 DRAM on UDIMM, and quad rank UDIMM are NOT supported x16 DRAM on UDIMM is not supported on combo routing

Memory suppliers not productizing native 800 ECC UDIMMs

Intel

®

Xeon

®

3400 Series support all timings defined by JEDEC.

256 Mb/512 Mb technology, x4 and x16 DRAMs on RDIMM are NOT supported

All channels in a system will run at the fastest common frequency

No mixing of registered and unbuffered DIMMs

No mixing of different ranks or speeds on UDIMM or RDIMM.

3.2.2 Post Error Codes

The range {0xE0 - 0xEF} of POST codes is used for memory errors in early POST. In late POST, this range is used for reporting other system errors.











0xE8 - No Usable Memory Error: If no memory is available, the system emits POST

Diagnostic LED code 0xE8 and halts the system.

0xE8 - Configuration Error: If a DDR3 DIMM has no SPD information, the BIOS treats the DIMM slot as if no DDR3 DIMM is present on it. Therefore, if this is the only DDR3

DIMM installed in the system, the BIOS halts with POST Diagnostic LED code 0xE8 (no usable memory) and halts the system.

0xEB - Memory Test Error: If a DDR3 DIMM or a set of DDR3 DIMMs on the same memory channel (row) fails HW Memory BIST but usable memory remains available, the

BIOS emits a beep code and displays POST Diagnostic LED code 0xEB momentarily during the beeping and then continues POST. If all of the memory fails HW Memory

BIST, the system acts as if no memory is available, beeping and halting with the POST

Diagnostic LED code 0xE8 (No Usable Memory) displayed.

0xEA - Channel Training Error: If the memory initialization process is unable to properly perform the DQ/DQS training on a memory channel, the BIOS emits a beep code and displays POST Diagnostic LED code 0xEA momentarily during the beeping. If there is usable memory in the system on other channels, POST memory initialization continues. Otherwise, the system halts with POST Diagnostic LED code 0xEA staying displayed.

0xED - Population Error: If the installed memory contains a mix of RDIMMs and

UDIMMs, the system halts with POST Diagnostic LED code 0xED.

Revision 2.4


19




3.2.3









0xEE - Mismatch Error: If more than two quad-ranked DIMMs are installed on any channel in the system, the system halts with POST Diagnostic LED code 0xEE.

Publishing System Memory

The BIOS displays the Total Memory of the system during POST if Quiet Boot is disabled in the BIOS setup. This is the total size of memory discovered by the BIOS during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the system.

The BIOS displays the Effective Memory of the system in the BIOS Setup. The term

Effective Memory refers to the total size of all active DDR3 DIMMs (not disabled) and not used as redundant units.

The BIOS provides the total memory of the system in the main page of the BIOS setup.

This total is the same as the amount described by the first bullet in this section.

If Quiet Boot is disabled, the BIOS displays the total system memory on the diagnostic screen at the end of POST. This total is the same as the amount described by the first bullet in this section.

The BIOS provides the total amount of memory in the system.



3.2.3.1 Memory Reservation for Memory-mapped Functions

A region of size 40 MB of memory below 4 GB is always reserved for mapping chipset, processor, and BIOS (flash) spaces as memory-mapped I/O regions. This region appears as a loss of memory to the operating system. In addition to this loss, the BIOS creates another reserved region for memory-mapped PCIe functions, including a standard 64 MB or 256 MB of standard PCI Express* MMIO configuration space.

If PAE is turned on in the operating system, the operating system reclaims all these reserved regions.

In addition to this memory reservation, the BIOS creates another reserved region for memorymapped PCI Express* functions, including a standard 64 MB or 256 MB of standard PCI

Express* Memory Mapped I/O (MMIO) configuration space. This is based on the selection of

Maximize Memory below 4 GB in the BIOS Setup.

If this is set to Enabled, the BIOS maximizes usage of memory below 4 GB for an operating system without PAE capability by limiting PCI Express* Extended Configuration Space to 64 buses rather than the standard 256 buses. This is done using the MAX_BUS_NUMBER feature offered by the Intel

®

Express* functions.

S3420 I/O Hub and a variably-sized Memory Mapped I/O region for the PCI

When 4 GB or more of physical memory is installed (physical memory is the memory installed as DDR3 DIMMs), the reserved memory is lost. However, the Intel

®

3420 chipset provides a feature called high-memory reclaim, which allows the BIOS and operating system to remap the lost physical memory into system memory above 4 GB (the system memory is the memory the processor can see).

The BIOS always enables high-memory reclaim if it discovers installed physical memory equal to or greater than 4 GB. For the operating system, the reclaimed memory is recoverable only if the PAE feature in the processor is supported and enabled. Most operating systems support this feature. For details, see the relevant operating system manuals.

20


Only ECC memory is supported on this platform.

3.2.4 Memory Map and Population Rules

The following nomenclature is followed for DIMM sockets:

Note: Intel

®

Server Board S3420GP may support up to three DIMM sockets per channel.

Table 3. Standard Platform DIMM Nomenclature

Channel A Channel B

A1 A2 A3 B1 B2 B3

The rules for determining the operating frequency of the memory channels are simple, but not necessarily straightforward. There are several limiting factors, including the number of DIMMs on a channel and organization of the DIMM - that is, either single-rank (SR), dual-rank (DR), or quad-rank (QR):













The speed of the processor’s IMC is the maximum speed possible.

The speed of the slowest component – the slowest DIMM or the IMC – determines the maximum frequency, subject to further limitations.

A single 1333-MHz DIMM (SR or DR) on a channel may run at full 1333-MHz speed.

If two SR/DR DIMMs are installed on a channel, the speed is limited to 1066 MHZ.

A single QR RDIMM on a channel is limited to 1066 MHz.

Two QR RDIMMs or a mix of QR + SR/DR on a channel is limited to 800 MHz.

3.2.4.2 Memory Subsystem Nomenclature

1. DIMMs are organized into physical slots on DDR3 memory channels that belong to processor sockets.

2. The memory channels are identified as channels A, B.

3. For Intel

®

Xeon

®

3400 Series, each socket can support a maximum of six DIMM sockets (three DIMM sockets per channel), which can support a maximum of six

DIMM sockets.

4. The Intel

®

Xeon

®

Processor 3400 Series on the Intel

®

Server Board S3420GP is populated on the processor socket. It has an Integrated Memory Controller (IMC).

The IMC provides two DDR3 channels and groups DIMMs on the board into an autonomous memory.

5. The DIMM identifiers on the silkscreen on the board provide information about the channel and the processor socket to which they belong. For example, DIMM_A1 is the first slot on channel A.

Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the following factors:

Revision 2.4


21






Existing DDR3 DIMM population

DDR3 DIMM characteristics



Optimization techniques used by the supported processors to maximize memory bandwidth

In the Independent Channel mode, all DDR3 channels operate independently. Slot-to-slot DIMM matching is not required across channels (for example, A1 and B1 do not have to match each other in terms of size, organization, and timing). DIMMs within a channel do not have to match in terms of size and organization, but they operate in the minimal common frequency. Also,

Independent Channel mode can be used to support single DIMM configuration in channel A and in the Single Channel mode.

You must observe the following general rules when selecting and configuring memory to obtain the best performance from the system.

1. DDR3 RDIMMs must always be populated using a fill-farthest method.

2. DDR3 UDIMMs must always be populated on DIMM A1/A2/B1/B2.

3. Intel

®

Xeon

®

Processor 3400 Series support either RDIMMs or UDIMMs.

4. Intel

®

Xeon

®

Processor L3406, Intel

®

Core

Processor G6950 only support UDIMMs.

TM

Processor i3-500 series or Intel

®

Pentium

®

5. RDIMM and UDIMM CAN NOT be mixed.

6. The minimal memory set is {DIMMA1}.

7. DDR3 DIMMs on adjacent slots on the same channel do not need to be identical.

Each socket supports a maximum of six slots. Standard Intel

®

server boards and systems that use the Intel

®

3420 chipset support three slots per DDR3 channel, two DDR3 channels per socket, and only one socket is supported on the Intel

®

Server Board S3420GP.

RDIMM

Table 4. Memory Configuration Table

A1

Channel A

A2 A3 B1

Channel B

B2 B3

X

X X

X X X

X X

X X X

X X X X

X X X X

X X X X X

22


A1

Channel A

A2 A3 B1

Channel B

B2 B3

UDIMM

X X X X X X

X

X X

X X

X X X

X X X X

This table defines half of the valid memory configurations. You can exchange Channel A DIMMs with the DIMMs on Channel B to get another half.

DIMM slots per channel DIMMs populated per channel

2 1

2 2

Speed

1066, 1333

1066, 1333

Ranks per channel

Single Rank, Dual Rank


Table 5. UDIMM memory configuration rule

To get the maximum memory size on UDIMM, you get the detail information from below table.

Max Memory Possible

Single Rank UDIMM

Dual Rank UDIMMs

1Gb DRAM Technology

4GB

(4x 1GB DIMMs)

8GB

(4x 2GB DIMMs)

8GB

2Gb DRAM Technology

(4x 2GB DIMMs)

16GB

(4x 4GB DIMMs)

Table 6. UDIMM Maximum configuration

Intel

®

Server Board S3420GP has the following limitations on UDIMM.

















Not support 800MHz ECC UDIMMs

No support for LV DIMMs

256Mb technology, x4 DRAM on UDIMM and quad rank UDIMM are NOT supported x16 DRAM is not supported on combo routing



Non-ECC UDIMMs not supported

Mixing ECC and non-ECC UDIMMs anywhere on the platform will prevent the system to boot/function correctly

Revision 2.4


23


DIMM slots per channel DIMMs populated per channel

3 1

3 1

Speed

1066, 1333

Ranks per channel


1066 Rank

3

3

2

3 2

3**

1066, 1333 Single Rank, Dual Rank

800* Rank

800* Single Rank, Dual Rank

Quad Rank RDIMMs

Table 7. RDIMM memory configuration rule

To get the maximum memory size on RDIMM, refer to the following table:

Max Memory Possible

Single Rank RDIMM

1Gb DRAM Technology

6GB

(6x 1GB DIMMs)

2Gb DRAM Technology

12GB

(6x 2GB DIMMs)

Dual Rank RDIMMs 12GB

(6x 2GB DIMMs)

16GB

(4x 4GB DIMMs)

24GB

(6x 4GB DIMMs)

32GB

(4x 8GB DIMMs)

Table 8. RDIMM Maximum configuration

Intel

®

Server Board S3420GP has the following limitations on RDIMM:

Note: Intel

®

Server Board S3420GPV has two DIMM slots per channel on board and totally four

DIMM slots which support maximum RDIMM size to 16GB (4x 4GB DIMMs) because of thermal limitation without BMC control.









No support for LV DIMMs

256Mb/512Mb technology, x4 and x16 DRAMs on RDIMM are NOT supported



Note : 1066MHz or 1333MHz RDIMMs run at 800MHz.

3.3 Intel

®

3420 Chipset PCH

The Intel

®

3420 Chipset component is the Platform Controller Hub (PCH). The PCH is designed for use with Intel

® processor in a UP server platform. The role of the PCH in Intel

®

Server Board

S3420GP is to manage the flow of information between its eleven interfaces:



DMI interface to Processor

24






















PCI Express* Interface

PCI Interface

SATA Interface

USB Host Interface

SMBus Host Interface

SPI Interface

LPC interface to IBMC

JTAG interface

LAN interface

ACPI interface

3.4 I/O Sub-system

Intel

®

3420 Chipset PCH provides extensive I/O support.

3.4.1 PCI Express Interface

Two different PCI-E configurations on single board are dependent on different board SKUs:



Intel

®

Server Board S3420GPLX

One PCI-E X16 slot connected to the PCI-E ports of CPU. Two PCI-E x8 slots and one SAS



 module connected to PCI-E ports of PCIe switch. One PCI-E X8 slot and one PCI-E x4 slot connected to the PCI-E ports of PCH.

Intel

®

Server Board S3420GPLC

One PCI-E X16 slot and one PCI-E X8 slot connected to the PCI-E ports of CPU. One PCI-

E x8 slot connected to the PCI-E ports of PCH.

Intel

®

Server Board S3420GPV

One PCI-E X16 slot and one PCI-E X8 slot connected to the PCI-E ports of CPU. One PCI-

E x8 slot connected to the PCI-E ports of PCH.

There is one 32-bit, 33-MHz, 3.3-V/5-V PCI slot.

Compatibility with the PCI addressing model is maintained to ensure all existing applications and drivers operate unchanged.

The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-

Play specification. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s/direction, which provides a 250-MB/s communications channel in each direction (500 MB/s total). This is close to twice the data rate of classic PCI. The fact that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would imply 300 MB/s. The external graphics ports support 5.0 GT/s speed as well. Operating at 5.0 GT/s results in twice as much bandwidth per lane as compared to 2.5 GT/s operation.

When operating with two PCI Express* controllers, each controller can operate at either 2.5

GT/s or 5.0 GT/s. The PCI Express* architecture is specified in three layers: Transaction Layer,

Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries.

Revision 2.4


25


3.4.2 Serial ATA Support

The Intel

®

3420 Chipset has two integrated SATA host controllers that support independent

DMA operation on up to six ports and supports data transfer rates of up to 3.0 GB/s (300 MB/s).

The SATA controller contains two modes of operation – a legacy mode using I/O space and an

AHCI mode using memory space.

Software that uses legacy mode does not have AHCI capabilities. The Intel

®

3420 Chipset supports the Serial ATA Specification, Revision 1.0a. The Ibex Peak also supports several optional sections of the Serial ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0

(AHCI support is required for some elements).

3.4.2.1 Intel

®

Matrix Storage Technology

The Intel

®

3420 Chipset provides support for Intel

®

Matrix Storage Technology, providing both

AHCI (see above for details on AHCI) and integrated RAID functionality. The industry leading

RAID capability provides high-performance RAID 0, 1, 5, and 10 functionality on up to six SATA ports of PCH. Matrix RAID support is provided to allow multiple RAID levels to be combined on a single set of hard drives, such as RAID 0 and RAID 1 on two disks. Other RAID features include hot spare support, SMART alerting, and RAID 0 autos replace. Software components include an Option ROM for pre-boot configuration and boot functionality, a Microsoft Windows* compatible driver, and a user interface to configure and manage the RAID capability of the

Intel

®

3420 Chipset.

3.4.3 USB 2.0 Support

On the Intel

®

3420 Chipset, the USB controller functionality is provided by the dual EHCI controllers with an interface for up to ten USB 2.0 ports. All ports are high-speed, full-speed, and low-speed capable.









Four external connectors are located on the back edge of the server board.

Two internal 2x5 header (J1E2 and J1D1) are provided, each supporting two optional

USB 2.0 ports.

One port on internal vertical connector to support NIC.

One port on 1x4pin (J1J2) on-board header on Intel

®

S3420GPLC) to support floppy.


3.4.3.1 Native USB Support

During the power-on self test (POST), the BIOS initializes and configures the USB subsystem.

The BIOS is capable of initializing and using the following types of USB devices.





USB Specification-compliant keyboards

USB Specification-compliant mouse

USB Specification-compliant storage devices that utilize bulk-only transport mechanism



USB devices are scanned to determine if they are required for booting.

The BIOS supports USB 2.0 mode of operation, and as such supports USB 1.1 and USB 2.0 compliant devices and host controllers.

26


During the pre-boot phase, the BIOS automatically supports the hot addition and hot removal of

USB devices and a short beep is emitted to indicate such an action. For example, if a USB device is hot plugged, the BIOS detects the device insertion, initializes the device, and makes it available to the user. During POST, when the USB controller is initialized, it emits a short beep for each USB device plugged into the system as they were all just “hot added”.

Boards and systems based on the Intel

®

Server Board S3420GPLX or S3420GPLC are designed to indicate USB readiness by a series of beep codes during POST, before video becomes available. These beeps indicate that the USB is powered and initialized. Devices such as a pen drive or USB CD/DVD ROM drive attached to external USB port will generate a beep code once the device is recognized, powered and initialized. These beep codes do not signal any error. They signal USB and external device readiness during POST.

Only on-board USB controllers are initialized by BIOS. This does not prevent the operating system from supporting any available USB controllers including add-in cards.

3.4.3.2 Legacy USB Support

The BIOS supports PS/2 emulation of USB keyboards and mouse. During POST, the BIOS initializes and configures the root hub ports and searches for a keyboard and/or a mouse on the

USB hub and then enables the devices that are recognized.

3.5 Optional Intel

®

SAS Entry RAID Module AXX4SASMOD

The Intel

Intel

®

®

Server Board S3420GPLX provides one 50-pin PCI Express* connector (J2H1) for the installation of an optional Intel

®

SAS Entry RAID Module AXX4SASMOD. Once the optional

SAS Entry RAID Module AXX4SASMOD is detected, the x4 PCI Express* links from the

PCI switches to the 50-pin PCI Express* connector. The optional Intel

®

SAS Entry RAID Module

AXX4SASMOD includes a SAS1064e controller that supports x4 PCI Express* link widths and is a single-function PCI Express* end-point device.

The SAS controller supports the SAS protocol as described in the Serial Attached SCSI

Standard, version 1.0, and also supports SAS 1.1 features. A 32-bit external memory bus off the

SAS1064e controller provides an interface for Flash ROM and NVSRAM (Non-volatile Static

Random Access Memory) devices.

The optional Intel

®

SAS Entry RAID Module AXX4SASMOD provides four SAS connectors that support up to four hard drives with a non-expander backplane or up to eight hard drives with an expander backplane.

4 ports full featured SAS/SATA hardware RAID through optional Intel

10, 50, 60.

®

Integrated RAID Module

SROMBSASMR (AXXROMBSASMR), provides RAID 0, 1, 5, 6 and striping capability for spans

3.6 Integrated Baseboard Management Controller

The Intel

®


®

Server Board S3420GPLC have the integrated baseboard management controller, but Intel

® integrated baseboard management control.

Server Board S3420GPV does not have the

Revision 2.4


27


The ServerEngines* LLC Pilot II Integrated BMC is provided by an embedded ARM9 controller and associated peripheral functionality that is required for IPMI-based server management.

Firmware usage of these hardware features is platform-dependant.

The following is a summary of the Integrated BMC management hardware features used by the

ServerEngines* LLC Pilot II Integrated BMC:



















250 MHz 32-bit ARM9 Processor

Memory Management Unit (MMU)

Two 10/100 Ethernet Controllers with NC-SI support

16-bit DDR2 667 MHz interface

Dedicated RTC

12 10-bit ADCs

Eight Fan Tachometers

Four PWMs

Battery-backed Chassis Intrusion I/O Register





JTAG Master

Six I

2

C interfaces

General-purpose I/O Ports (16 direct, 64 serial)



Additionally, the ServerEngines* Pilot II part integrates a super I/O module with the following features:

 KCS/BT

 Two 16C550 Serial Ports

 Serial Support

 12 GPIO Ports (shared with BMC)

 LPC



SMI and PME Support

The Pilot II contains an integrated KVMS subsystem and graphics controller with the following features:



USB 2.0 for keyboard, mouse, and storage devices

 USB 1.1 interface for legacy PS/2 to USB bridging

 Hardware Video Compression for text and graphics

 Hardware

 2D Acceleration

 DDR2

 Up to 1600x1200 pixel resolution

 PCI Express* x1 support

28


Figure 13. Integrated BMC Hardware

3.6.1 Integrated BMC Embedded LAN Channel

The Integrated BMC hardware includes two dedicated 10/100 network interfaces.

Interface 1: This interface is available from either of the available NIC ports in system that can be shared with the host. Only one NIC may be enabled for management traffic at any time. To change the NIC enabled for management traffic, please use the “Write LAN Channel Port” OEM

IPMI command. The default active interface is port 1 (NIC1).

Interface 2: This interface is available from the optional RMM3 which is a dedicated management NIC that is not shared with the host.

For these channels, support can be enabled for IPMI-over-LAN and DHCP.

For security reasons, embedded LAN channels have the following default settings:



IP Address: Static



All users disabled

3.6.2 Optional RMM3 Advanced Management Board

Intel

®

Server Board S3420GPLX provides one RMM3 module slot. RMM3 advanced management board serves two purposes:

Revision 2.4


29


 Give the customer the option to add a dedicated management 100 Mbit LAN interface to the product.

 Provide additional flash space, enabling the Advanced Management functions to support

WS-MAN and CIMON.

Table 9. Optional RMM3 Advanced Management Board Features

Feature

KVM Redirection

USB Media Redirection

WS-MAN

Description

Remote console access via keyboard, video, and mouse redirection over LAN.

Remote USB media access over LAN.

Full SMASH profiles for WS-MAN based consoles.

3.6.3 Serial Ports

The server board provides two serial ports: an external DB9 serial port connector and an internal DH-10 serial header.

The rear DB9 serial A port is a fully-functional serial port that can support any standard serial device.

The Serial B port is an optional port accessed through a 9-pin internal DH-10 header (J1B1).

You can use a standard DH-10 to DB9 cable to direct serial A port to the rear of a chassis. The serial B interface follows the standard RS-232 pin-out as defined in the following table.

Table 10. Serial B Header (J1B1) Pin-out

Pin Signal Name

1 DCD

Serial Port B Header Pin-out

2 DSR

3 RX

4 RTS

5 TX

6 CTS

7 DTR

8 RI

9 GND

3.6.4 Floppy Disk Controller

The server board does not support a floppy disk controller interface. However, the system BIOS recognizes USB floppy devices.

3.6.5 Keyboard and Mouse Support

The server board does not support PS/2 interface keyboards and mouse. However, the system

BIOS recognizes USB specification-compliant keyboard and mouse.

30


3.6.6 Wake-up Control

The super I/O contains functionality that allows various events to power on and power off the system.

3.7 Video Support

3.7.1 Intel

®


®

Server Board S3420GPLC

The server board includes on-board Server Engine* LLC Pilot II* Controller with 64 MB DDR2 memory in which 8MB is usable/accessible memory for iBMC video/graphic display functions.

The graphic controller internally has access to larger memory for the internal operations. The

32MB memory reported by display driver is the attached memory. Attached memory can be

32MB or greater but only 8MB is accessible for display functions. The SVGA subsystem supports a variety of modes, up to 1600 x 1200 resolution under 2D. It also supports both CRT and LCD monitors up to a 100 Hz vertical refresh rate..

The video is accessed using a standard 15-pin VGA connector found on the back edge of the server board. The on-board video controller can be disabled using the BIOS Setup utility or when an add-in video card is detected. The system BIOS provides the option for dual-video operation when an add-in video card is configured in the system.

The integrated video controller supports all standard VGA modes. The following table shows the

2D modes supported for both CRT and LCD.

Table 11. Video Modes

2D Mode

Resolution

8 bpp

2D Video Mode Support (Color Bit)

16 bpp 24 bpp 32 bpp

640x480 Supported Supported Supported Supported

60, 72, 75, 85 60, 72, 75, 85 60, 72, 75, 85 60, 72, 75, 85 Monitor

Refresh Rate

(Hz)

800x600 Supported Supported Supported Supported

56, 60, 72, 75,

85

56, 60, 72, 75,

85

56, 60, 72, 75,

85

56, 60, 72, 75,

85

Monitor

Refresh Rate

(Hz)

1024x768 Supported

60, 70, 75, 85

Supported

60, 70, 75, 85

Supported

60, 70, 75, 85

Supported

60, 70, 75, 85 Monitor

Refresh Rate

(Hz)

1152x864 Supported Supported Supported N/A

75 75 75 N/A Monitor

Refresh Rate

(Hz)

1280x1024 Supported

60, 75, 85

Supported

60, 75, 85

Supported

60

N/A

N/A Monitor

Refresh Rate

Revision 2.4


31


2D Mode

Resolution 8 bpp

2D Video Mode Support (Color Bit)

16 bpp 24 bpp 32 bpp

1440x900 Supported Supported Supported N/A

(Hz)

60 60 60 N/A Monitor

Refresh Rate

(Hz)

1600x1200 Supported

60, 65, 70, 75,

85

Supported

60, 65, 70

N/A

N/A

N/A

N/A Monitor

Refresh Rate

(Hz)

The BIOS supports both single-video and dual-video modes. The dual-video mode is disabled by default.









In the single mode (dual monitor video = disabled), the on-board video controller is disabled when an add-in video card is detected.

In single mode, the onboard video controller is disabled when an add-in video card is detected.

In dual mode, the onboard video controller is enabled and is the primary video device.

The external video card is allocated resources and is considered the secondary video device.

When KVM is enabled in iBMC FW, dual video is enabled.

Table 12. Dual Video Modes

Onboard Video

Dual Monitor Video

Enabled

Disabled

Enabled

Disabled

Onboard video controller.

Warning: System video is completely disabled if this option is disabled and an add-in video adapter is not installed.

If enabled, both the onboard video controller and an add-in video adapter are enabled for system video. The onboard video controller becomes the primary video device.

3.7.2 Video for Intel

®


SM712 is a one video chip from Silicon Motion, Inc (SMI). It is one in SMI’s LynxEM family. It is

PCI 2.1 compliant with the standard PCI 33MHz & 66 MHz PCI Master/Slave interface.



33 MHz & 66 MHz PCI Master/Slave interface



PCI 2.1 compliant







Memory control is provided for the 4MB internal memory

Support 640x480, 800x600, 1024x768 resolution and up to 85Hz.

Dual Video mode is supported.

32


3.8 Network Interface Controller (NIC)

The Intel

®

Server Board S3420GPLX, S3420GPLC and S3420GPV support two network interfaces, One is provided from the onboard Intel the other is the onboard Intel

®

®

82574L GbE PCI Express network controller;

82578 Gigabit Network controller.

3.8.1 GigE Controller 82574L

The 82574 family (82574L and 82574IT) are single, compact, low-power components that offer a fully-integrated Gigabit Ethernet Media Access Control (MAC) and Physical Layer (PHY) port.

The 82574 uses the PCI Express* architecture and provides a single-port implementation in a relatively small area so it can be used for server and client configurations as a LAN on

Motherboard (LOM) design.

External interfaces provided on the 82574:

 PCIe Rev. 2.0 (2.5 GHz) x1

 MDI (Copper) standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASETX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab)

 NC-SI or SMBus connection to a Manageability Controller (MC)

 EEE 1149.1 JTAG (note that BSDL testing is NOT supported)

3.8.2

GigE PHY 82578DM

The 82578 is a single port Gigabit Ethernet Physical Layer Transceiver (PHY). It connects to the

Media Access Controller (MAC) through a dedicated interconnect. The 82578DM supports operation at 1000/100/10 Mb/s data rates. The PHY circuitry provides a standard IEEE 802.3

Ethernet interface for 1000BASE-T, 100BASE-TX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab).

The 82578 operates with the Platform Controller Hub (PCH) chipset that incorporates the MAC.

The 82578 interfaces with its MAC through two interfaces: PCIe-based and SMBus. The PCIe

(main) interface is used for all link speeds when the system is in an active state (S0) while the

SMBus is used only when the system is in a low power state (Sx). In SMBus mode, the link speed is reduced to 10 Mb/s. The PCIe interface incorporates two aspects: a PCIe SerDes

(electrically) and a custom logic protocol.

3.8.3 MAC Address Definition

Each Intel

®

Server Board S3420GPLX has the following four MAC addresses assigned to it at the Intel factory:





NIC 1 MAC address

NIC 2 MAC address – Assigned the NIC 1 MAC address +1





Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2

Intel

®


MAC address +3

®

RMM3) MAC address – Assigned the NIC 1

Each Intel

®

Server Board S3420GPLC has the following three MAC addresses assigned to it at the Intel factory:





NIC 1 MAC address


Revision 2.4


33




Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2

Each Intel

®

Intel

®

Server Board S3420GPV has the following two MAC addresses assigned to it at the

factory:





NIC 1 MAC address


3.9 Intel

®

I/O Acceleration Technology 2 (Intel

®

I/OAT2)

The Intel

®

3420 chipset series platforms do not support Intel

®

I/O Acceleration Technology.

3.9.1 Direct Cache Access (DCA)

Direct Cache Access (DCA) is not supported on Intel

®

Xeon

®

Processor 3400 Series.

3.10 Intel

®

Virtualization Technology for Directed I/O (Intel

®

VT-d)

The Intel

®

3420 chipset provides hardware support for implementation of Intel

Technology with Directed I/O (Intel

®

VT-d). Intel VT-d Technology consists of technology components that support the virtualization of platforms based on Intel

®

Virtualization

®

Architecture Processor.

Intel VT-d Technology enables multiple operating systems and applications to run in dependent partitions. A partition behaves like a virtual machine (VM) and provides isolation and protection across partitions. Each partition is allocated its own subset of host physical memory.

The Intel

®

Virtualization Technology is designed to support multiple software environments sharing the same hardware resources. The Intel

®

Virtualization Technology can be enabled or disabled in the BIOS setup. The default behavior is disabled.

Note: If the setup options are changed to enable or disable the Virtualization Technology setting in the processor, the user must perform an AC power cycle for the changes to take effect.

34


Intel® Server Board S3420GP TPS Platform Management

4. Platform Management

This chapter is only for The Intel

®


®

Server Board

S3420GPLC.

The platform management subsystem is based on the Integrated BMC features of the

ServerEngines* Pilot II. The onboard platform management subsystem consists of communication buses, sensors, system BIOS, and server management firmware. The following diagram provides an overview of the Server Management Bus (SMBUS) architecture used on this server board.

Figure 14. Server Management Bus (SMBUS) Block Diagram

4.1 Feature Support

4.1.1 IPMI 2.0 Features

 Integrated Baseboard Management Controller (Integrated BMC).

 IPMI timer.



Messaging support, including command bridging and user/session support.

 Chassis device functionality, including power/reset control and BIOS boot flags support.

 Event receiver device: The Integrated BMC receives and processes events from other platform subsystems.

Revision 2.4


35

Platform Management Intel® Server Board S3420GP TPS

 Field replaceable unit (FRU) inventory device functionality: The Integrated BMC supports access to system FRU devices using IPMI FRU commands.

 System event log (SEL) device functionality: The Integrated BMC supports and provides access to a SEL.



Sensor device record (SDR) repository device functionality: The Integrated BMC supports storage and access of system SDRs.

 Sensor device and sensor scanning/monitoring: The Integrated BMC provides IPMI management of sensors. It polls sensors to monitor and report system health.

 IPMI o

Host interfaces include system management software (SMS) with receive message queue support and server management mode (SMM). o

Terminal mode serial interface o

IPMB o

LAN interface that supports the IPMI-over-LAN protocol (RMCP, RMCP+)

 Serial-over-LAN

 ACPI state synchronization: The Integrated BMC tracks ACPI state changes provided by the BIOS.

 Integrated Baseboard Management Controller (Integrated BMC) self test: The Integrated

BMC performs initialization and run-time self tests, and makes results available to external entities.

For more information, refer to the IPMI 2.0 Specification.

4.1.2 Non-IPMI Features

The Integrated BMC supports the following non-IPMI features. This list does not preclude support for future enhancements or additions.

 In-circuit Integrated BMC firmware update.

 Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality

 Chassis intrusion detection and chassis intrusion cable presence detection.

 Basic fan control using TControl version 2 SDRs.

 Acoustic management: Support for multiple fan profiles.

 Signal testing support: The Integrated Baseboard Management Controller (Integrated

BMC) provides test commands for setting and getting platform signal states.

 The Integrated Baseboard Management Controller (Integrated BMC) generates diagnostic beep codes for fault conditions.

 System GUID storage and retrieval.

 Front panel management: The Integrated Baseboard Management Controller (Integrated

BMC) controls the system status LED and chassis ID LED. It supports secure lockout of certain front panel functionality and monitors button presses. The chassis ID LED is turned on using a front panel button or a command.

 Power retention

 Power fault analysis

 Intel

®

Light-Guided Diagnostics

36



 Power unit management: Support for power unit sensor. The Integrated Baseboard

Management Controller (Integrated BMC) handles power-good dropout conditions.

 DIMM temperature monitoring: New sensors and improved acoustic management using closed-loop fan control algorithm taking into account DIMM temperature readings.



Address Resolution Protocol (ARP): The Integrated BMC sends and responds to ARPs

(supported on embedded NICs)

 Dynamic Host Configuration Protocol (DHCP): The Integrated BMC performs DHCP

(supported on embedded NICs).

 Platform environment control interface (PECI) thermal management support.

 E-mail



Embedded server

 Integrated

 Integrated Remote Media Redirection

 Lightweight Directory Authentication Protocol (LDAP) support

4.2 Optional Advanced Management Feature Support

This section explains the advanced management features supported by the Integrated

Baseboard Management Controller (Integrated BMC) firmware.

4.2.1 Enabling Advanced Management Features

The Integrated BMC enables the advanced management features only when it detects the presence of the Intel

®


®

RMM3, the advanced features are dormant. Only the Intel

®

RMM3) card. Without the Intel

®

Server Board S3420GPLX has a

RMM3 module interface.

4.2.1.1 Intel

®

RMM3

The Intel

®

RMM3 provides the Integrated BMC with an additional dedicated network interface.

The dedicated interface consumes its own LAN channel. Additionally, the Intel

®

RMM3 provides additional flash storage for advanced features like Web Services for Management (WS-MAN).

4.2.2 Keyboard, Video, Mouse (KVM) Redirection

The Integrated BMC firmware supports keyboard, video, and mouse redirection over LAN. This feature is available remotely from the embedded web server as a Java applet. This feature is enabled only when the Intel

®

RMM3 is present. The client system must have a Java Runtime

Environment (JRE) version 5.0 or later to run the KVM or media redirection applets.

The keyboard and mouse are emulated by the Integrated BMC as USB human interface devices.

4.2.2.2 Video

Video output from the KVM subsystem is equivalent to the video output on the local console.

Video redirection is available after video is initialized by the system BIOS. The KVM video resolution and refresh rates will always match the values set in the operating system.

Revision 2.4


37

Platform Management Intel® Server Board S3420GP TPS

4.2.2.3 Availability

Up to two remote KVM sessions are supported. The default inactivity timeout is 30 minutes; however, this can be changed through the embedded web server. Remote KVM activation does not disable the local system keyboard, video, or mouse. Unless the feature is disabled locally, remote KVM is not deactivated by local system input.

KVM sessions persist across system reset but not across an AC power loss.

4.2.3 Media Redirection

The embedded web server provides a Java applet to enable remote media redirection. This may be used in conjunction with the remote KVM feature or as a standalone applet.

The media redirection feature is intended to allow system administrators or users to mount a remote IDE or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the server.

Once mounted, the remote device appears just like a local device to the server, allowing system administrators or users to install software (including operating systems), copy files, update the

BIOS, and so forth, or boot the server from this device.

The following capabilities are supported:

 The operation of remotely mounted devices is independent of the local devices on the server. Both remote and local devices are usable in parallel

 Either IDE (CD-ROM, floppy) or USB devices can be mounted as a remote device to the server.

 It is possible to boot all supported operating systems from the remotely mounted device and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. Refer to the

Tested/supported Operating System List for more information.



It is possible to mount at least two devices concurrently.

 The mounted device is visible to (and useable by) the managed system’s operating system and BIOS in both pre-boot and post-boot states.



The mounted device shows up in the BIOS boot order and it is possible to change the

BIOS boot order to boot from this remote device.

 It is possible to install an operating system on a bare metal server (no operating system present) using the remotely mounted device. This may also require the use of KVM-r to configure the operating system during install.

If either a virtual IDE or virtual floppy device is remotely attached during system boot, both virtual IDE and virtual floppy are presented as bootable devices. It is not possible to present only a single mounted device type to the system BIOS.

4.2.3.1 Availability

The default inactivity timeout is 30 minutes, but may be changed through the embedded web server.

Media redirection sessions persist across system reset but not across an AC power loss.

4.2.4 Web Services for Management (WS-MAN)

The Integrated BMC firmware supports the Web Services for Management (WS-MAN) specification, version 1.0.

38



4.2.5 Local Directory Authentication Protocol (LDAP)

The Integrated BMC firmware supports the Local Directory Authentication Protocol (LDAP) protocol for user authentication.

Note: IPMI users/passwords and sessions are not supported over LDAP.

4.2.6 Embedded Webserver

The Integrated BMC provides an embedded web server for out-of-band management. User authentication is handled by IPMI user names and passwords. Base functionality for the embedded web server includes:

 Power Control – Limited control based on IPMI user privilege.



Sensor Reading – Limited access based on IPMI user privilege.

 SEL Reading – Limited access based on IPMI user privilege.

 KVM/Media Redirection – Limited access based on IPMI user privilege. Only available when the Intel

®

RMM3 is present.

 IPMI User Management – Limited access based on IPMI user privilege.

The web server is available on all enabled LAN channels.

See Appendix B for Integrated BMC core sensors.

4.3 Management Engine (ME)

Intel Management Engine is tied to essential platform functionality. This Management Engine firmware includes the following applications:

 Platform Clocks – Tune PCH clock silicon to the parameters of a specific board, configure clocks at run time, power management clocks.

 Thermal Report – ME FW reports thermal and power information available only on PECI to host accessible registers/Embedded Controller via SMBus.

Revision 2.4


39

Server Management Capability for Intel® Server Board S3420GPV Intel® Server Board S3420GP TPS

5. Server Management Capability for Intel® Server Board

S3420GPV

5.1 Super I/O

5.1.1 Key Features of Super I/O

The W83627DHG-P is from the Nuvoton's Super I/O product line. This family features the LPC

(Low Pin Count) interface. This interface is more economical than its ISA counterpart. It has approximately forty pins less, yet it provides as great performance. In addition, the improvement allows even more efficient operation of software, BIOS, and device drivers.

The W83627DHG-P provides below key features

 Meet LPC Spec. 1.01

 Integrated hardware monitor functions

 Support ACPI (Advanced Configuration and Power Interface)

 Support up to 2 16550-compatible UARTs ports

 8042-based controller

 Smart Fan control system



Five fan-speed monitoring inputs

 Four controls

 GPIO

 Support PECI 1.0 and 1.1a Specifications

5.1.2 Sensor and Hardware Monitor

Hardware Monitor Screen allows the user to configure Fan speed control and show the monitored voltage to user. To access this screen from the BIOS Main screen, choose Server

Management > Hardware Monitor.

Fan Speed Control management has two options.



Auto – is for SC5299UP chassis support.



300m, 900m, 1500m, 3000m can be selected according to the local altitude where the system is placed to assure the system is properly cooled. The default altitude setting is 900m.

40


Intel® Server Board S3420GP TPS Server Management Capability for Intel® Server Board S3420GPV



Main

Advance d

Hardware monitor

Security Server Management

Boot

Options

Real-time Temperature and Voltage Status

Fan Controller

Auto/Manual

CPU Fan Altitude

300m/900m/1500m/3000m

Board Fan Altitude

300m/900m/1500m/3000m

Boot

Manager



Revision 2.4

Hysteresis

Figure 15. Setup Utility — Hardware Monitor Screen Display

Table 13. Setup Utility — Hardware Monitor Screen Fields

Setup Item

Voltage and

Temperature Status

CPU Fan Controller

CPU Fan Altitude

Board Fan Altitude

Default Fan PWM

Options Help Text display monitored voltage, current

Fan speed PWM and temperature

Auto

Manual

CPU temperature control policy

Auto Fan speed control setting by default

Manual user adjust Fan speed control setting value manually

300m/900m/1500m/3000m Select CPU FAN default mode

PWM according to altitude under Auto

300m/900m/1500m/3000m Select Board Fan default PWM according to altitude under Auto mode

3 Degree Celsius

Hysteresis – is used to smoothing the FAN speed transition when

4 Degree Celsius temperature approaching temperature target upward or downward. Select Hysteresis to keep

FAN at the same speed within the range

40%

60%

80%

100%

Select Default FAN PWM to make

FAN speed keep the invariable speed when temperature is below

FSC temperature target at low user conditions. This delivers optimized acoustic level


41


Note: The two options of Hysteresis and Default Fan PWM apply to all the four fans

5.1.3 Fan controller (Manual)

Fan controller (Manual) allows the user to configure Fan speed control manually. To access this screen from the Main screen, choose Server Management > Hardware Monitor > Fan

controller (Manual).

[Manual] is designed for the third party chassis which supports four fan headers. Each of them has four minimum fan PWM output selections 40%, 60%, 80%, and 100% and associated with different cooling capabilities as well as different acoustic levels. The default PWM is 100% and can be customized to 40%, 60%, 80% according to the third party chassis cooling capability and acoustic requirement.

Hysteresis is used to prevent fan oscillation when temperature is crossing the target control temperature back and forth.

42





Advanc

Main ed

Hardware monitor

Secu rit y

Server

Management

Real-time Temperature and Voltage Status

Fan Controller Manual

CPU Fan

Hysteresis

Default Fan PW M

System Fan

Hysteresis

Default Fan PWM

Auxiliary Fan 1

Hysteresis

Default Fan PWM

Auxiliary Fan 2

Hysteresis

Default Fan PWM

Boot

Options

[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius

[40%/60%/80%/100%]

[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius

[40%/60%/80%/100%]

[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius

[40%/60%/80%/100%]

Boot Manager

[2 Degree Celsius/3 Degree Celsius/4 Degree Celsius

[40%/60%/80%/100%]



Figure 16. Setup Utility — Fan controller (Manual) Display

Table 14. Setup Utility — Hardware Monitor Screen Fields

Setup Item

Voltage and

Temperature Status

CPU Fan Controller

Options

Auto

Manual

Help Text display monitored voltage, current

Fan speed PWM and temperature

CPU temperature control policy

Auto - Fan speed control setting by default

Manual - user adjust Fan speed control setting value manually

Comments

Revision 2.4


43


Setup Item

CPU Fan Altitude

System Fan Altitude

Hysteresis

Default Fan PWM

Options Help Text

300m/900m/1500m/3000m Select CPU FAN default PWM according to altitude under Auto mode

300m/900m/1500m/3000m Select Board Fan default PWM according to altitude under Auto mode

2 Degree Celsius

3 Degree Celsius

4 Degree Celsius

Hysteresis – is used to smoothing the FAN speed transition when temperature approaching temperature target upward or downward. Select Hysteresis to keep FAN at the same speed within the range

40%

60%

80%

100%

Select Default FAN PWM to make

FAN speed keep the invariable speed when temperature is below

FSC temperature target at low customized conditions. This delivers optimized acoustic level

Comments

The change can not take effect immediately by increasing the

PWM. It requires a power cycle or a thermal event to take the change in effect.

Note: the two options of Hysteresis and Default Fan PWM apply to all the four Fans

5.1.4 Voltage and Temperature Status Screen

Display monitored voltage, current Fan speed PWM and temperature



Server Management

Real time Temperature and PWM:

CPU Fan PWM

System Fan PWM

System temperature

Voltage status:

+Vccp

+12V

+3.3V

+5.0V

+1.5V

+1.05V

+3.3V(standby)

Figure 17. Setup Utility — Voltage and Temperature Status Screen

Table 15. Setup Utility — Voltage and Temperature Status Fields



44



Setup Item

CPU Fan PWM

System Fan PWM

System temperature

+Vccp

+12V

+3.3V

+5.0V

+1.5V

+1.05V

+3.3V(standby)

Comments

Get and display CPU fan PWM periodically

Get and display system fan PWM periodically

Get and display current system temperature monitored by system sensor

Get and display +Vccp voltage periodically

Get and display +12 voltage periodically

Get and display +3.3 voltage periodically

Get and display +5.0V voltage periodically

Get and display +1.5V voltage periodically

Get and display +1.05 voltage periodically

Get and display +3.3V(standby)voltage periodically

5.2 SMBIOS

5.2.1 Data Storage

On Intel

®


®

Server Board S3420GPLC with iBMC, the

SMBIOS type 1, 2, 3 are from FRUSDR by BMC. But on Intel

®

Server Board S3420GPV,

SMBIOS type 1, 2, 3 are stored in BIOS flash during manufactory build, so it’s also non-volatile data storage.

BIOS retrieve the SMBIOS data from flash during POST, and it builds the SMBIOS type 1, 2, 3 into SMBIOS table and then transfers the control to operating system. Operating system and system management software can use the SMBIOS table for system management purpose.

5.3 Event log and Viewer

5.3.1 Event Log Viewer in Setup

On Intel

®


®

Server Board S3420GPLC, there is a dedicated utility to view the event log. There is no IPMI support - the way to view the event log in BIOS

Setup, on Intel

®

Server Board S3420GPV.

There is one page in BIOS setup for event log viewer. It is located in Error Manager Page.

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45




Error Manager

No. Event Info Time

005 M-BIT MEM ECC Error CPU0 Ch 0 Dimm0 10/15/09 15:12:23

004 S-BIT MEM ECC Error CPU0 Ch 0 Dimm0 10/15/09 15:11:25

003 PCIE UNCOR ERR Bus0 Dev 1C Fun0 10/15/09 15:08:36

002 MEM Parity Error CPU0 Ch 0 Dimm0 10/15/09 15:07:11

001 Thermal Trip Occurred. 10/15/09 15:05:05

Figure 18. Event Log Viewer



The Event log viewer is at another page than the BIOS error manager. The event log viewer can display many log in one page. Each event log is displayed in one line. The latest one is on the top. When there are more event logs on one page, Page Up and Page Down keys can be used.

There is a scroll bar to allow end-users to view the logs from top to bottom.

46


Intel® Server Board S3420GP TPS BIOS User Interface

6. BIOS User Interface

6.1 Logo/Diagnostic Screen

The logo/Diagnostic Screen displays in one of two forms:

 If Quiet Boot is enabled in the BIOS setup, a logo splash screen displays. By default,

Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press <Esc> to hide the logo and display the diagnostic screen.

 If a logo is not present in the flash ROM or if Quiet Boot is disabled in the system configuration, the summary and diagnostic screen displays.

The diagnostic screen displays the following information:

 BIOS

 Platform

 Total memory detected (Total size of all installed DDR3 DIMMs)

 Processor information (Intel branded string, speed, and number of physical processor identified)

 Keyboards detected (if plugged in)

 Mouse devices detected (if plugged in)

6.2 BIOS Boot Popup Menu

The BIOS Boot Specification (BBS) provides for a Boot Popup Menu invoked by pressing the

<F6> key during POST. The BBS popup menu displays all available boot devices. The list order in the popup menu is not the same as the boot order in the BIOS setup; it simply lists the bootable devices from which the system can be booted.

When a User Password or Administrator Password is active in Setup, the password is to access the Boot Popup Menu.

6.3 BIOS Setup utility

The BIOS setup utility is a text-based utility that allows the user to configure the system and view current settings and environment information for the platform devices. The Setup utility controls the platform’s built-in devices, boot manager, and error manager.

The BIOS setup interface consists of a number of pages or screens. Each page contains information or links to other pages. The advanced tab in Setup displays a list of general categories as links. These links lead to pages containing a specific category’s configuration.

The following sections describe the look and behavior for platform setup.

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47

BIOS User Interface Intel® Server Board S3420GP TPS

6.3.1 Operation

The BIOS Setup has the following features:

 Localization - The BIOS Setup uses the Unicode standard and is capable of displaying setup forms in all languages currently included in the Unicode standard. The Intel

® server board BIOS is only available in English.

 Console Redirection - The BIOS Setup is functional through console redirection over various terminal emulation standards. This may limit some functionality for compatibility

(for example, color usage or some keys or key sequences or support of pointing devices).

The setup page layout is sectioned into functional areas. Each occupies a specific area of the screen and has dedicated functionality. The following table lists and describes each functional area.

Table 16. BIOS Setup Page Layout

Functional Area

Title Bar

Setup Item List

Item Specific Help Area

Keyboard Command Bar

Description

The title bar is located at the top of the screen and displays the title of the form

(page) the user is currently viewing. It may also display navigational information.

The Setup Item List is a set of controllable and informational items. Each item in the list occupies the left column of the screen.

A Setup Item may also open a new window with more options for that functionality on the board.

The Item Specific Help area is located on the right side of the screen and contains help text for the highlighted Setup Item. Help information may include the meaning and usage of the item, allowable values, effects of the options, and so forth.

The Keyboard Command Bar is located at the bottom right of the screen and continuously displays help for keyboard special keys and navigation keys.

6.3.1.2 Entering BIOS Setup

To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo displays. The following message displays on the diagnostics screen and under the Quiet Boot logo screen:

Press <F2> to enter setup

When the Setup is entered, the Main screen displays. However, serious errors cause the system to display the Error Manager screen instead of the Main screen.

The bottom right portion of the Setup screen provides a list of commands used to navigate through the Setup utility. These commands display at all times.

Each Setup menu page contains a number of features. Each feature is associated with a value field except those used for informative purposes. Each value field contains configurable parameters. Depending on the security option chosen and, in effect, by the password, a menu

48


Intel® Server Board S3420GP TPS BIOS User Interface feature’s value may or may not be changed. If a value cannot be changed, its field is made inaccessible and appears grayed out.

Table 17. BIOS Setup: Keyboard Command Bar

Key Option

<Enter> Execute

Command

<Esc>







<Tab>

-

+

<F9>

Exit

Select Item

Select Item

Select Menu

Select Field

Change Value

Change Value

Setup Defaults

Description

The <Enter> key is used to activate sub-menus when the selected feature is a submenu, or to display a pick list if a selected option has a value field, or to select a sub-field for multi-valued features like time and date. If a pick list is displayed, the

<Enter> key selects the currently highlighted item, undoes the pick list, and returns the focus to the parent menu.

The <Esc> key provides a mechanism for backing out of any field. When the <Esc> key is pressed while editing any field or selecting features of a menu, the parent menu is re-entered.

When the <Esc> key is pressed in any sub-menu, the parent menu is re-entered.

When the <Esc> key is pressed in any major menu, the exit confirmation window is displayed and the user is asked whether changes can be discarded. If “No” is selected and the <Enter> key is pressed, or if the <Esc> key is pressed, the user is returned to where they were before <Esc> was pressed, without affecting any existing settings. If “Yes” is selected and the <Enter> key is pressed, the setup is exited and the BIOS returns to the main System Options Menu screen.

The up arrow is used to select the previous value in a pick list, or the previous option in a menu item's option list. The selected item must then be activated by pressing the <Enter> key.

The down arrow is used to select the next value in a menu item’s option list, or a value field’s pick list. The selected item must then be activated by pressing the

<Enter> key.

The left and right arrow keys are used to move between the major menu pages.

The keys have no affect if a sub-menu or pick list is displayed.

The <Tab> key is used to move between fields. For example, <Tab> can be used to move from hours to minutes in the time item in the main menu.

The minus key on the keypad is used to change the value of the current item to the previous value. This key scrolls through the values in the associated pick list without displaying the full list.

The plus key on the keypad is used to change the value of the current menu item to the next value. This key scrolls through the values in the associated pick list without displaying the full list. On 106-key Japanese keyboards, the plus key has a different scan code than the plus key on the other keyboards, but will have the same effect.

Pressing <F9> causes the following to display:

Load Optimized Defaults?

Yes No

If “Yes” is highlighted and <Enter> is pressed, all Setup fields are set to their default values. If “No” is highlighted and <Enter> is pressed, or if the <Esc> key is pressed, the user is returned to where they were before <F9> was pressed without affecting any existing field values.

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49

BIOS User Interface

Key

<F10>

Option

Save and Exit


Description

Pressing <F10> causes the following message to display:

Save configuration and reset?

Yes No

If “Yes” is highlighted and <Enter> is pressed, all changes are saved and the Setup is exited. If “No” is highlighted and <Enter> is pressed, or the <Esc> key is pressed, the user is returned to where they were before <F10> was pressed without affecting any existing values.

The Menu Selection Bar is located at the top of the BIOS Setup Utility screen. It displays the major menu selections available to the user. By using the left and right arrow keys, the user can select the menus listed here. Some menus are hidden and become available by scrolling off the left or right of the current selections.

6.3.2 Server Platform Setup Utility Screens

The following sections describe the screens available for the configuration of a server platform.

In these sections, tables are used to describe the contents of each screen. These tables follow the following guidelines:

 The Setup Item, Options, and Help Text columns in the tables document the text and values displayed on the BIOS Setup screens.



In the Options column, the default values display in bold. These values are not displayed in bold on the BIOS Setup screen; the bold text in this document serves as a reference point.

 The Comments column provides additional information where it may be helpful. This information does not display on the BIOS Setup screens.



Information enclosed in angular brackets (< >) in the screen shots identifies text that can vary, depending on the option(s) installed. For example, <Current Date> is replaced by the actual current date.

 Information enclosed in square brackets ([ ]) in the tables identifies areas where the user must type in text instead of selecting from a provided option.

 Whenever information is changed (except Date and Time), the system requires a save and reboot to take place. Pressing <ESC> discards the changes and boots the system according to the boot order set from the last boot.

The Main screen is the first screen displayed when the BIOS Setup is entered, unless an error occurred. If an error occurred, the Error Manager screen displays instead.

50







Main

Advance d

Security Server Management Boot Options



Logged in as <Administrator or User>



Platform ID

<Platform Identification String>





System BIOS



Version

Build Date

SXXXX.86B.xx.yy.zzzz

<MM/DD/YYYY>







Memory



Total Memory

Quiet Boot



POST Error Pause

System Date



System Time

<How much memory is installed>





Enabled/Disabled



Enabled/Disabled



<Current Date>

<Current Time>





Figure 19. Setup Utility – Main Screen Display

Boot Manager





Setup Item

Logged in as

Platform ID

Table 18. Setup Utility – Main Screen Fields

Options Help Text Comments

Information only. Displays password level that setup is running in: Administrator or User.

With no passwords set,

Administrator is the default mode.

Information only. Displays the

Platform ID.

LX SKU: S3420GPX

LC SKU: S3420GPC

V SKU: S3420GPV

System BIOS

Version

Build Date

Information only. Displays the current BIOS version. xx = major version yy = minor version zzzz = build number

Information only. Displays the current BIOS build date.

Memory

Revision 2.4


51


Setup Item Options

Size

Quiet Boot

POST Error Pause

System Date

System Time

Enabled

Disabled

Enabled

Disabled

[Day of week

MM/DD/YYYY]

[HH:MM:SS]

Help Text

[Enabled] – Display the logo screen during POST.

[Disabled] – Display the diagnostic screen during POST.

[Enabled] – Go to the Error

Manager for critical POST errors.

[Disabled] – Attempt to boot and do not go to the Error Manager for critical POST errors.

Comments

Information only. Displays the total physical memory installed in the system, in MB or GB. The term physical memory indicates the total memory discovered in the form of installed DDR3 DIMMs.

If enabled, the POST Error Pause option takes the system to the error manager to review the errors when major errors occur. Minor and fatal error displays are not affected by this setting.

System Date has configurable fields for Month, Day, and Year.

Use [Enter] or [Tab] key to select the next field.

Use [+] or [-] key to modify the selected field.

System Time has configurable fields for Hours, Minutes, and

Seconds.

Hours are in 24-hour format.

Use [Enter] or [Tab] key to select the next field.

Use [+] or [-] key to modify the selected field.

The Advanced screen provides an access point to configure several options. On this screen, the user selects the option they want to configure. Configurations are performed on the selected screen, and not directly on the Advanced screen.

To access this screen from the Main screen, press the right arrow until the Advanced screen is chosen.

52



Main

Advance d

Security

► Processor Configuration

Server Management Boot Options

► Memory Configuration

► Mass Storage Controller Configuration

► Serial Port Configuration

► USB Configuration

► PCI Configuration

► System Acoustic and Performance Configuration

Figure 20. Setup Utility – Advanced Screen Display

Boot Manager

Table 19. Setup Utility – Advanced Screen Display Fields

Setup Item

Processor Configuration

Memory Configuration

Mass Storage Controller Configuration

Serial Port Configuration

USB Configuration

PCI Configuration

System Acoustic and Performance

Configuration

Help Text

View/Configure processor information and settings.

View/Configure memory information and settings.

View/Configure mass storage controller information and settings.

View/Configure serial port information and settings.

View/Configure USB information and settings.

View/Configure PCI information and settings.

View/Configure system acoustic and performance information and settings.





The Processor screen allows the user to view the processor core frequency, system bus frequency, and to enable or disable several processor options. This screen also allows the user to view information about a specific processor.

To access this screen from the Main screen, select Advanced > Processor.

Revision 2.4


53


Advanced

Processor Configuration

Processor Socket

Processor ID

Processor Frequency

Microcode Revision

L1 Cache RAM

L2 Cache RAM

L3 Cache RAM

CPU 1

<CPUID>

<Proc Freq>

<Rev data>

Size of Cache

Size of Cache

Size of Cache

<ID string from Processor 1> Processor 1 Version

Current QPI Link Speed

QPI Link Frequency

Intel

®

Turbo Boost Technology

Enhanced Intel SpeedStep

®

Tech

<Slow/Fast >

<Unknown GT/s/4.8 GT/s/5.866 GT/s/6.4 GT/s>


Enabled/Disabled

Processor C3 Report

Core Multi-Processing

Enabled/ Disabled

Processor C6 Report Enabled/ Disabled

Intel

®

Hyper-Threading Technology Enabled/Disabled

All/1/2

Enabled/Disabled Execute Disable Bit

Intel

®

Virtualization Technology

Intel

®

VT for Directed I/O



Pass-through DMA Support

Hardware Prefetcher

Adjacent Cache Line Prefetch




Setup Item

Processor ID

Processor Frequency

Core Frequency

Microcode Revision

L1 Cache RAM

Figure 21. Setup Utility – Processor Configuration Screen Display

Table 20. Setup Utility – Processor Configuration Screen Fields

Options Help Text Comments

Information only. Processor

CPUID.

Information only. Current frequency of the processor.

Information only. Frequency at which the processor are currently running.

Information only. Revision of the loaded microcode.

Information only. Size of the

Processor L1 Cache.

54



Setup Item

L2 Cache RAM

L3 Cache RAM

Processor Version

Current QPI Link Speed

Options

QPI Link Frequency

Intel

®

Turbo Boost

Technology

Enabled

Disabled

Enhanced Intel

SpeedStep

®

Technology

Enabled

Disabled

Intel

®

Hyper-Threading

Technology

Enabled

Disabled

Core Multi-Processing

Execute Disable Bit

All

1

2

Enabled

Disabled

Intel

®

Virtualization

Technology

Enabled

Disabled

Intel

®

Virtualization

Technology for Directed

I/O

Pass-through DMA

Support

Enabled

Disabled

Enabled

Disabled

Hardware Prefetcher Enabled

Disabled

BIOS User Interface

Help Text Comments


Processor L2 Cache


Processor L3 Cache.

Information only. ID string from the Processor.

Intel

®

Turbo Boost Technology allows the processor to automatically increase its frequency if it is running below power, temperature, and current specifications.

Enhanced Intel SpeedStep

®

Technology allows the system to dynamically adjust processor voltage and core frequency, which can result in decreased average power consumption and decreased average heat production.

Contact your OS vendor regarding OS support of this feature.

Intel

®

HT Technology allows multithreaded software applications to execute threads in parallel within the processor.


Enable 1, 2 or All cores of installed processor packages.

Information only. Current speed that the QPI Link is using.

Information only. Current frequency that the QPI Link is using.

This option is only visible if all processor in the system support Intel

Technology.

®

Turbo Boost

Execute Disable Bit can help prevent certain classes of malicious buffer overflow attacks.


Intel

®

Virtualization Technology allows a platform to run multiple operating systems and applications in independent partitions.

Note: A change to this option requires the system to be powered off and then back on before the setting takes effect.

Enable/Disable Intel

®

Virtualization

Technology for Directed I/O.

Report the I/O device assignment to VMM through DMAR ACPI Tables

Enable/Disable Intel

®

DMA support.

VT-d Pass-through Only visible when Intel

®

Directed I/O is enabled.

Virtualization Technology for

Hardware Prefetcher is a speculative prefetch unit within the processor(s).

Note: Modifying this setting may affect system performance.

Revision 2.4


55

BIOS User Interface

Setup Item

Adjacent Cache Line

Prefetch

Options

Enabled

Disabled


Comments Help Text

[Enabled] - Cache lines are fetched in pairs

(even line + odd line).

[Disabled] - Only the current cache line required is fetched.

Note: Modifying this setting may affect system performance.

The Memory screen allows the user to view details about the system memory DDR3 DIMMs installed. This screen also allows the user to open the Configure Memory RAS and Performance screen.

To access this screen from the Main screen, select Advanced > Memory.

Advanced

Memory Configuration

Total Memory

Effective Memory

Current Configuration

Current Memory Speed

►

DIMM Information

DIMM_A1

DIMM_A2

DIMM_A3

DIMM_B1

DIMM_B2

DIMM_B3

<Total Physical Memory Installed in System>

<Total Effective Memory>

<Independent >

<Speed that installed memory is running at.>

Installed/Not Installed/Failed/Disabled/Spare Unit






Figure 22. Setup Utility – Memory Configuration Screen Display

Table 21. Setup Utility – Memory Configuration Screen Fields

Setup Item

Total Memory

Comments

Information only. The amount of memory available in the system in the form of installed DDR3 DIMMs in units of MB or GB.

56



Setup Item

Effective Memory

Comments

Information only. The amount of memory available to the operating system in MB or GB.

The Effective Memory is the difference between the Total Physical

Memory and the sum of all memory reserved for internal usage,

RAS redundancy and SMRAM. This difference includes the sum of all DDR3 DIMMs that failed Memory BIST during POST, or were disabled by the BIOS during memory discovery phase to optimize memory configuration.

Current Configuration Information only. Displays one of the following:

Independent Mode: System memory is configured for optimal performance and efficiency and no RAS is enabled.

Sparing Mode: System memory is configured for RAS with optimal effective memory.

Current Memory

Speed

DIMM_ XY

Information only. Displays the speed the memory is running at.

Displays the state of each DIMM socket present on the board.

Each DIMM socket field reflects one of the following possible states:

Installed: There is a DDR3 DIMM installed in this slot.

Not Installed: There is no DDR3 DIMM installed in this slot.

Disabled: The DDR3 DIMM installed in this slot was disabled by the BIOS to optimize memory configuration.

Failed: The DDR3 DIMM installed in this slot is faulty/malfunctioning.

Spare Unit: The DDR3 DIMM is functioning as a spare unit for memory RAS purposes.

Note: X denotes the Channel Identifier and Y denote the DIMM

Identifier within the Channel.

6.3.2.2.3 Mass Storage Controller Screen

The Mass Storage screen allows the user to configure the SATA/SAS controller when it is present on the baseboard, midplane, or backplane of an Intel system.

To access this screen from the Main menu, select Advanced > Mass Storage.

Revision 2.4


57


Advanced

Mass Storage Controller Configuration

Intel

®

Entry SAS RAID Module Enabled/Disabled

Configure Intel

®

Entry SAS RAID Module

LSI

®

Integrated RAID/Intel

®

ESRTII

Onboard SATA Controller

Configure SATA Mode


ENHANCED/COMPATIBILITY/AHCI/SW RAID

► SATA Port 0 Not Installed/<Drive Info.>

► SATA Port 1

► SATA Port 2

► SATA Port 3

► SATA Port 4

► SATA Port 5

Not Installed/<Drive Info.>





Figure 23. Setup Utility – Mass Storage Controller Configuration Screen Display

Table 22. Setup Utility – Mass Storage Controller Configuration Screen Fields

Setup Item

Intel

®

Entry SAS RAID

Module

Configure Intel

®

Entry

SAS RAID Module

Onboard SATA

Controller

SATA Mode

Enabled

Disabled

LSI

®

Intel

®

Options

Integrated

RAID

ESRTII

Enabled

Disabled

ENHANCED

COMPATIBILITY

AHCI

Intel ESRT2

Matrix RAID

®

Help Text

Enabled or Disable the Intel

®

SAS

Entry RAID Module

LSI

®

RAID 0, RAID 1, and RAID 1e, as well as IT (JBOD) mode;

Intel

Integrated RAID - Supports

ESRTII - Intel

®

Embedded

Server RAID Technology II, which supports RAID 0, RAID 1, RAID

10.

Onboard Serial ATA (SATA) controller.

[ENHANCED] - Supports up to 6

SATA ports with IDE Native

Mode.

[COMPATIBILITY] - Supports up to 4 SATA ports[0/1/2/3] with IDE

Legacy mode and 2 SATA ports[4/5] with IDE Native Mode.

[AHCI] - Supports all SATA ports using the Advanced Host

Controller Interface.

[Intel ESRT2] - Supports RAID

0/1/10 with Intel

®

Embedded

Software RAIDII Technology.

[Matrix RAID] – Supports RAID levels 0/1/10 and 5 with Intel

®

Matrix Storage RAID Technology.

Comments

Unavailable if the SAS Module

(AXX4SASMOD) is not present.

Note: This option is not available on some models.

Unavailable if the SAS Module

(AXX4SASMOD) is disabled or not present


Disappears when the Onboard

SATA Controller is disabled.

58



Setup Item

SATA Port 0

SATA Port 1

SATA Port 2

SATA Port 3

SATA Port 4

SATA Port 5

Options

< Not

Installed/Drive information>

< Not


< Not


< Not


< Not


< Not


Help Text

BIOS User Interface

Comments

Information only. This field is unavailable when RAID Mode is enabled.






The Serial Ports screen allows the user to configure the Serial A [COM 1] and Serial B [COM2] ports.

To access this screen from the Main screen, select Advanced > Serial Port.

Advanced

Serial Port Configuration



Serial A Enable

Address

IRQ

Serial B Enable

Address



IRQ


3F8h/2F8h/3E8h/2E8h

3 or 4


3F8h/2F8h/3E8h/2E8h



3 or 4

Figure 24. Setup Utility – Serial Port Configuration Screen Display

Table 23. Setup Utility – Serial Ports Configuration Screen Fields

Setup Item

Serial A

Enable

Options

Enabled

Disabled

Address 3F8h

2F8h

3E8h

2E8h

Help Text

Enable or Disable Serial port A.

Select Serial port A base I/O address.

Revision 2.4




59


Setup Item Options

IRQ 3

4

Serial B

Enable

Enabled

Disabled

Address 3F8h

2F8h

3E8h

2E8h

IRQ 3

4

Help Text

Select Serial port A interrupt request (IRQ) line.

Enable or Disable Serial port B.

Select Serial port B base I/O address.

Select Serial port B interrupt request (IRQ).

6.3.2.2.5 USB Configuration Screen

The USB Configuration screen allows the user to configure the USB controller options.

To access this screen from the Main screen, select Advanced > USB Configuration.

Advanced

USB Configuration

Detected USB Devices

<Total USB Devices in System>

USB Controller

Legacy USB Support

Port 60/64 Emulation

Make USB Devices Non-Bootable

USB Mass Storage Device Configuration

Device Reset timeout

Mass Storage Devices:

<Mass storage devices one line/device>

USB 2.0 controller


Enabled/Disabled/Auto


Enabled/Disabled

10 seconds/20 seconds/30 seconds/40 seconds

Auto/Floppy/Forced FDD/Hard Disk/CD-ROM


Figure 25. Setup Utility – USB Controller Configuration Screen Display

60



Table 24. Setup Utility – USB Controller Configuration Screen Fields

Setup Item

Detected USB

Devices

USB Controller

Legacy USB

Support

Port 60/64

Emulation

Make USB

Devices Non-

Bootable

Device Reset timeout

One line for each mass storage device in system

USB 2.0 controller

Options

Enabled

Disabled

Enabled

Disabled

Auto

Enabled

Disabled

Enabled

Disabled

10 sec

20 sec

30 sec

40 sec

Auto

Floppy

Forced FDD

Hard Disk

CD-ROM

Enabled

Disabled

Help Text

[Enabled] - All onboard USB controllers are turned on and accessible by the OS.

[Disabled] - All onboard USB controllers are turned off and inaccessible by the OS.

USB device boot support and PS/2 emulation for USB keyboard and USB mouse devices.

[Auto] - Legacy USB support is enabled if a USB device is attached.

I/O port 60h/64h emulation support.

Note: This may be needed for legacy USB keyboard support when using an OS that is USB unaware.

Exclude USB in Boot Table.

[Enabled] - This removes all USB Mass Storage devices as Boot options.

[Disabled] - This allows all USB Mass Storage devices as

Boot options.

USB Mass Storage device Start Unit command timeout.

Setting to a larger value provides more time for a mass storage device to be ready, if needed.

[Auto] - USB devices less than 530 MB are emulated as floppies.

[Forced FDD] - HDD formatted drive are emulated as a

FDD (e.g., ZIP drive).

Onboard USB ports are enabled to support USB 2.0 mode.


Comments

Information only. Shows the number of USB devices in the system.

Grayed out if the USB Controller is disabled.




Hidden if no USB Mass storage devices are installed.


This setup screen can show a maximum of eight devices on this screen. If more than eight devices are installed in the system, the USB

Devices Enabled shows the correct count, but only displays the first eight devices here.


The PCI Screen allows the user to configure the PCI add-in cards, onboard NIC controllers, and video options.

To access this screen from the Main screen, select Advanced > PCI.

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61






Advanced

PCI Configuration

Maximize Memory below 4GB

Memory Mapped I/O above 4GB

Onboard Video

Dual Monitor Video

Onboard NIC1 ROM

Onboard NIC2 ROM

Onboard NIC iSCSI ROM










<MAC #>

<MAC #>

NIC 1 MAC Address

NIC 2 MAC Address

Setup Item

Maximize Memory below 4GB

Memory Mapped I/O above 4GB

Onboard Video

Dual Monitor Video

Onboard NIC1 ROM

Onboard NIC2 ROM

Figure 26. Setup Utility – PCI Configuration Screen Display

Table 25. Setup Utility – PCI Configuration Screen Fields

Options

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Enabled

Disabled

Help Text

If enabled. the BIOS maximizes usage of memory below 4 GB for OS without PAE by limiting PCIE

Extended Configuration Space to 64 buses.

Enable or disable memory mapped I/O of 64-bit

PCI devices to 4 GB or greater address space.

Onboard video controller.

Warning: System video is completely disabled if this option is disabled and an add-in video adapter is not installed.

Comments

When disabled, the system requires an add-in video card for the video to be seen.


Note: This option does not appear on some models.

If enabled. both the onboard video controller and an add-in video adapter are enabled for system video. The onboard video controller becomes the primary video device.

If enabled. loads the embedded option ROM for the onboard network controllers.

Warning: If [Disabled] is selected, NIC1 cannot be used to boot or wake the system.


Warning: If [Disabled] is selected, NIC2 cannot be used to boot or wake the system.

62



Setup Item

Onboard NIC iSCSI

ROM

NIC 1 MAC Address

Options

Enabled

Disabled

No entry allowed

No entry allowed

Help Text


Warning: If [Disabled] is selected, NIC1 and NIC2 cannot be used to boot or wake the system.

Comments

This option is grayed out and not accessible if either the NIC1 or NIC2 ROMs are enabled.


Information only. 12 hex digits of the MAC address.

Information only. 12 hex digits of the MAC address.

NIC 2 MAC Address

6.3.2.2.7 System Acoustic and Performance Configuration

The System Acoustic and Performance Configuration screen allows the user to configure the thermal characteristics of the system.

To access this screen from the Main screen, select Advanced > System Acoustic and

Performance Configuration.



Advanced

System Acoustic and Performance Configuration

Set Throttling Mode

Altitude

Set Fan Profile

Auto/CLTT/OLTT

300m or less/301m-900m/901m – 1500m/Higher than 1500m

Performance, Acoustic

Figure 27. Setup Utility – System Acoustic and Performance Configuration Screen Display

Table 26. Setup Utility – System Acoustic and Performance Configuration Screen Fields

Setup Item

Set Throttling

Mode

Auto

CLTT

OLTT

Options Help Text

[Auto] – Auto Throttling mode.

[CLTT] – Closed Loop Thermal Throttling Mode.

[OLTT] – Open Loop Thermal Throttling Mode.

Comments

Note: The OLTT option is shown for

informational

purposes only. If the user selects

OLTT, the BIOS overrides that selection if the system can support

CLTT. OLTT is configured only when

UDIMMs without

Thermal Sensors are installed.



Revision 2.4


63


Setup Item

Altitude

Set Fan Profile

Options

300m or less

301m-900m

901m-1500m

Higher than 1500m

Performance

Acoustics

Help Text

[300m or less] (980ft or less)

Optimal performance setting near sea level.

[301m - 900m] (980ft - 2950ft)

Optimal performance setting at moderate elevation.

[901m – 1500m] (2950ft – 4920ft)

Optimal performance setting at high elevation.

[Higher than 1500m] (4920ft or greater)

Optimal performance setting at the highest elevations.

[Performance] - Fan control provides primary system cooling before attempting to throttle memory.

[Acoustic] - The system will favor using throttling of memory over boosting fans to cool the system if thermal thresholds are met.

Comments


This option is grayed out if CLTT is enabled.


The Security screen allows the user to enable and set the user and administrative password and to lock out the front panel buttons so they cannot be used.

Trusted Platform Module (TPM) security is NOT supported on the Intel

®

Server S3420GP board.

To access this screen from the Main screen, select Security.



Main Advanced Security Server Management Boot Options

Administrator Password Status

User Password Status

Set Administrator Password

Set User Password

Front Panel Lockout

<Installed/Not Installed>

<Installed/Not Installed>

[1234aBcD]

[1234aBcD]


Setup Item

Administrator Password

Status

Options

<Installed

Not Installed>

Help Text

Boot Manager

Figure 28. Setup Utility – Security Configuration Screen Display

Table 27. Setup Utility – Security Configuration Screen Fields



Comments

Information only. Indicates the status of the administrator password.

64



Setup Item Options

User Password Status <Installed

Not Installed>

Set Administrator

Password

[123aBcD]

Set User Password

Front Panel Lockout

[123aBcD]

Enabled

Disabled

Help Text

Administrator password is used to control change access in BIOS Setup

Utility.

Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive.

Note: Administrator password must be set in order to use the user account.

User password is used to control entry access to BIOS Setup Utility.

Only alphanumeric characters can be used. Maximum length is 7 characters. It is case sensitive.

Note: Removing the administrator password also automatically removes the user password.

If enabled, locks the power button and reset button on the system's front panel.

If [Enabled] is selected, power and reset must be controlled via a system management interface.

Comments

Information only. Indicates the status of the user password.

This option is only to control access to the setup.

Administrator has full access to all the setup items. Clearing the

Administrator password also clears the user password.

Available only if the administrator password is installed. This option only protects the setup.

User password only has limited access to the setup items.

6.3.2.4 Server Management Screen

The Server Management screen allows the user to configure several server management features. This screen also provides an access point to the screens for configuring console redirection and displaying system information.

To access this screen from the Main screen, select Server Management.

Revision 2.4


65




Main

Advance d

Assert NMI on SERR

Clear System Event Log

Security

Assert NMI on PERR

Resume on AC Power Loss




Stay Off/Last state/Reset


Boot Options Boot Manager



FRB-2 Enable


O/S Boot Watchdog Timer


Power off/Reset

O/S Boot Watchdog Timer Policy

O/S Boot Watchdog Timer Timeout

ACPI 1.0 Support

Plug & Play BMC Detection

5 minutes/10 minutes/15 minutes/20 minutes



► Console Redirection

► System Information

Figure 29. Setup Utility – Server Management Configuraiton Screen Display

Table 28. Setup Utility – Server Management Configuration Screen Fields

Setup Item Options

Assert NMI on SERR Enabled

Disabled

Assert NMI on PERR Enabled

Disabled

Resume on AC

Power Loss

Stay Off

Last state

Reset

Clear System Event

Log

FRB-2 Enable

Enabled

Disabled

Enabled

Disabled

Help Text

On SERR, generate an NMI and log an error.

Note: [Enabled] must be selected for the Assert NMI on PERR setup option to be visible.

On PERR, generate an NMI and log an error.

Note: This option is only active if the Assert NMI on

SERR option is [Enabled] selected.

System action to take on AC power loss recovery.

[Stay Off] - System stays off.

[Last State] - System returns to the same state before the AC power loss.

[Reset] - System powers on.

If enabled, clears the System Event Log. All current entries will be lost.

Note: This option is reset to [Disabled] after a reboot.

Fault Resilient Boot (FRB).

If enabled, the BIOS programs the BMC watchdog timer for approximately 6 minutes. If the BIOS does not complete POST before the timer expires, the BMC resets the system.

Comments

66



Setup Item

O/S Boot Watchdog

Timer

O/S Boot Watchdog

Timer Policy

Options

Enabled

Disabled

Power Off

Reset

Help Text

If enabled, the BIOS programs the watchdog timer with the timeout value selected. If the OS does not complete booting before the timer expires, the BMC resets the system and an error is logged.

Requires OS support or Intel Management Software.

If the OS boot watchdog timer is enabled, this is the system action taken if the watchdog timer expires.

[Reset] - System performs a reset.

[Power Off] - System powers off.

If the OS watchdog timer is enabled, this is the timeout value used by the BIOS to configure the watchdog timer.

Comments

Grayed out when the O/S

Boot Watchdog Timer is disabled.

O/S Boot Watchdog

Timer Timeout

Plug & Play BMC

Detection

ACPI 1.0 Support

Console Redirection

System Information

5 minutes

10 minutes

15 minutes

20 minutes

Enabled

Disabled

Enabled

Disabled

Grayed out when the O/S

Boot Watchdog Timer is disabled.

If enabled, the BMC is detectable by OSs that support plug and play loading of an IPMI driver. Do not enable if your OS does not support this driver.

[Enabled] - Publish ACPI 1.0 version of FADT in Root

System Description Table.

This may be required for compatibility with OS versions that only support ACPI 1.0.

View/Configure console redirection information and settings.

View system information

Needs to be [Enabled] for

Microsoft Windows 2000* support.

Takes the user to the

Console Redirection screen.

Takes the user to the

System Information screen.

6.3.2.4.1 Console Redirection Screen

The Console Redirection screen allows the user to enable or disable console redirection and to configure the connection options for this feature.

To access this screen from the Main screen, select Server Management > Console

Redirection.





Console Redirection


Console Redirection

Flow Control

Baud Rate

Terminal Type

Legacy OS Redirection

Disabled/Serial Port A/Serial Port B

None/RTS/CTS

9.6k/19.2k/38.4k/57.6k/115.2k

PC-ANSI/VT100/VT100+/VT-UTF8

Disabled/Enabled

Figure 30. Setup Utility – Console Redirection Screen Display

Revision 2.4


67


Table 29. Setup Utility – Console Redirection Configuration Fields

Setup Item Options

Console Redirection Disabled

Serial Port A

Serial Port B

Flow Control None

RTS/CTS

Help Text

Console redirection allows a serial port to be used for server management tasks.

[Disabled] - No console redirection.

[Serial Port A] - Configure serial port A for console redirection.

[Serial Port B] - Configure serial port B for console redirection.

Enabling this option disables the display of the Quiet Boot logo screen during POST.

Flow control is the handshake protocol.

Setting must match the remote terminal application.

[None] - Configure for no flow control.

[RTS/CTS] - Configure for hardware flow control.

Serial port transmission speed. Setting must match the remote terminal application.

Baud Rate

Terminal Type

9600

19.2K

38.4K

57.6K

115.2K

PC-ANSI

VT100

VT100+

VT-UTF8

Disabled

Enabled

Character formatting used for console redirection. Setting must match the remote terminal application.

Legacy OS

Redirection

This option enables legacy OS redirection (i.e., DOS) on serial port. If it is enabled, the associated serial port is hidden from the legacy OS.

6.3.2.5 Server Management System Information Screen

The Server Management System Information screen allows the user to view part numbers, serial numbers, and firmware revisions.

To access this screen from the Main screen, select Server Management > System

Information.

68





System Information


Board Part Number

Board Serial Number

System Part Number

System Serial Number

Chassis Part Number

Chassis Serial Number

BMC Firmware Revision

HSC Firmware Revision

ME Firmware Revision

SDR Revision

UUID

Figure 31. Setup Utility – Server Management System Information Screen Display

Table 30. Setup Utility – Server Management System Information Fields

Setup Item

Board Part Number

Board Serial Number

System Part Number

System Serial Number

Chassis Part Number

Chassis Serial Number

BMC Firmware Revision

HSC Firmware Revision

ME Firmware Revision

SDR Revision

Comments

Information only

Information only

Information only

Information only

Information only

Information only

Information only

Information only

Information only

Information only



The Boot Options screen displays any bootable media encountered during POST, and allows the user to configure the preferred boot device.

To access this screen from the Main screen, select Boot Options.

Revision 2.4


69




Main

Advance d

System Boot Timeout

Security Server Management Boot Options

<0 - 65535>

Boot Option #1

Boot Option #2

<Available Boot devices>


Boot Option #x


Hard Disk Order

CDROM Order

Network Device Order

►Delete Boot Option

EFI Optimized Boot

Boot Option Retry



Setup Item

Boot Timeout

Boot Option #x

Hard Disk Order

CDROM Order

Floppy Order

Network Device Order

Figure 32. Setup Utility – Boot Options Screen Display

Table 31. Setup Utility – Boot Options Screen Fields

Options

0 - 65535

Available boot devices.

Boot Manager



Help Text

The number of seconds the BIOS should pause at the end of POST to allow the user to press the [F2] key for entering the BIOS Setup utility.

Valid values are 0-65535. Zero is the default. A value of 65535 causes the system to go to the Boot Manager menu and wait for user input for every system boot.

Comments

After entering the preferred timeout, press the Enter key to register that timeout value to the system. These settings are in seconds.

Set system boot order by selecting the boot option for this position.

Set the order of the legacy devices in this group.

Visible when one or more hard disk drives are in the system.



Visible when one or more

CD-ROM drives are in the system.

Visible when one or more floppy drives are in the system.

Set the order of the legacy devices in Visible when one or more of

70



Setup Item

BEV Device Order

Add New Boot Option

Delete Boot Option

Options this group.

Help Text


Add a new EFI boot option to the boot order.

Remove an EFI boot option from the boot order.

Comments these devices are available in the system.

Visible when one or more of these devices are available in the system.

This option is only visible if an EFI bootable device is available to the system (for example, a USB drive).

If the EFI shell is deleted, you can restore it by setting

CMOS defaults (F9).

EFI Optimized Boot Enabled

Disabled

If enabled, the BIOS only loads modules required for booting EFIaware Operating Systems.

Boot Option Retry Enabled

Disabled

If enabled, this continually retries non-

EFI-based boot options without waiting for user input.

If all types of bootable devices are installed in the system, the default boot order is:

1. CD/DVD-ROM

2. Floppy Disk Drive

3. Hard Disk Drive

4. PXE Network Device

5. BEV (Boot Entry Vector) Device

6. EFI Shell and EFI Boot paths

6.3.2.6.1 Delete Boot Option Screen

The Delete Boot Option screen allows the user to remove an EFI boot option from the boot order.

To access this screen from the Main screen, select Boot Options > Delete Boot Options.





Delete Boot Option

Delete Boot Option

Boot Options

Select one to Delete/Internal EFI Shell

Figure 33. Setup Utility – Delete Boot Option Screen Display

Revision 2.4


71


Table 32. Setup Utility – Delete Boot Option Fields

Setup Item Options

Delete Boot Option Select one to Delete

Internal EFI Shell

Help Text

Remove an EFI boot option from the boot order.

6.3.2.6.2 Hard Screen

The Hard Disk Order screen allows the user to control the hard disks.

To access this screen from the Main screen, choose Boot Options > Hard Disk Order.



Hard Disk #1

Hard Disk #2

Boot Options

< Available Hard Disks >

< Available Hard Disks >

Figure 34. Setup Utility — Hard Disk Order Screen Display

Table 33. Setup Utility — Hard Disk Order Fields

Setup Item

Hard Disk #1

Hard Disk #2

Options

Available

Legacy devices for this Device group.

Available


Help Text







The CDROM Order screen allows the user to control the CDROM devices.

To access this screen from the Main screen, select Boot Options > CDROM Order.

Boot Options

<Available CDROM devices>

<Available CDROM devices>

CDROM

#1

CDROM

#2

Figure 35. Setup Utility – CDROM Order Screen Display



72



Setup Item

CDROM #1

CDROM #2

Table 34. Setup Utility – CDROM Order Fields

Options

Available


Available


Help Text



The Floppy Order screen allows the user to control the floppy drives.

To access this screen from the Main screen, choose Boot Options > Floppy Order.



Floppy Disk

#1

Floppy Disk

#2

Boot Options

<Available Floppy Disk >

<Available Floppy Disk >



Figure 36. Setup Utility — Floppy Order Screen Display

Table 35. Setup Utility — Floppy Order Fields

Setup Item

Floppy Disk #1

Floppy Disk #2

Options

Available


Available


Help Text



6.3.2.6.5 Network Device Order Screen

The Network Device Order screen allows the user to control the network bootable devices.

To access this screen from the Main screen, select Boot Options > Network Device Order.





Network

Device #1

Network

Device #2

Boot Options

<Available Network devices>

<Available Network devices>

Figure 37. Setup Utility – Network Device Order Screen Display

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73


Table 36. Setup Utility – Network Device Order Fields

Setup Item

Network Device #1

Network Device #2

Options

Available


Available


Help Text



The Boot Manager screen allows the user to view a list of devices available for booting, and to select a boot device for immediately booting the system.

To access this screen from the Main screen, select Boot Manager.



Main

Advance d

Security

[Internal EFI Shell]

<Boot device #1>

<Boot Option #x>

Server Management Boot Options

Figure 38. Setup Utility – Boot Manager Screen Display

Table 37. Setup Utility – Boot Manager Screen Fields

Boot Manager



Setup Item

Internal EFI Shell

Boot Device #x

Help Text

Select this option to boot now.

Note: This list is not the system boot option order. Use the

Boot Options menu to view and configure the system boot option order.

Select this option to boot now.

Note: This list is not the system boot option order. Use the

Boot Options menu to view and configure the system boot option order.

6.4 Loading BIOS Defaults

Different mechanisms exist for resetting the system configuration to the default values. When a request to reset the system configuration is detected, the BIOS loads the default system configuration values during the next POST. You can send the request to reset the system to the defaults in the following ways:

 Pressing <F9> from within the BIOS Setup utility.

 Moving the clear system configuration jumper.

74



 IPMI command (set System Boot options command)

 Int15 AX=DA209

 Choosing Load User Defaults from the Exit page of the BIOS Setup loads user set defaults instead of the BIOS factory defaults.

The recommended steps to load the BIOS defaults are:

1. Power down the system (Do not remove AC power).

2. Move the Clear CMOS jumper from pins 1-2 to pins 2-3.

3. Move the Clear CMOS jumper from pins 2-3 to pins 1-2.

4. Power up the system.

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75

Connector/Header Locations and Pin-outs Intel® Server Board S3420GP TPS

7. Connector/Header Locations and Pin-outs

7.1 Board Connector Information

The following section provides detailed information regarding all connectors, headers, and jumpers on the server board. It lists all connector types available on the board and the corresponding reference designators printed on the silkscreen.

Connector

Power supply

Table 38. Board Connector Matrix

Quantity

3 J9A1, J9C1

Reference Designators Connector Type Pin Count

Main power

CPU power

24

8

DIMM sockets 240

Header 34

Header 50

Main memory

Intel

®

RMM3

50-pin PCI

Express*

Connector

CPU Fan

System Fans

1

4

NIC/Stack 2x USB 2

6 J8J3, J8J2, J8J1, J9J3, J9J2, J8J4

1 J2C1

1 J2H1

J6D1

J1J4, J6J2, J7J1, J6B1

J5A1, J6A1

Serial port A

Serial port B

Front panel

USB floppy

Dual- USB Internal

Header

PCI-E x16

PCI-E x8

PCI-E x4

PCI 32

XDP Connector

1

3

Chassis Intrusion 1

Serial ATA 6

1

1

1

1

1

1

1

J8A1

J1B2

J4H3

J1C1

J4B3

J2B2, J3B1, J4B2

J2B1

J1B1

J5J1

J4B1

J1H4, J1H1, J1G1, J1H3, J1G3, J1F4

Header

Header

Dual USB

4

4

8

Connector

Header

Header

Header

9

9

24

4

Header 10

Card Edge

Card Edge

Card Edge

Card Edge

Connector

Header

Header

164

98

64

120

60

2

7

Z-U130 USB 1 J3F2

SATA_SGPIO 1 J1J3

Header

Header

7.2 Power Connectors

The main power supply connection uses an SSI-compliant 2x12 pin connector (J9A1). In addition, there is one additional power related connector:

10

4



One SSI-compliant 2x4 pin power connector (J9C1), which provides 12-V power to the

CPU VRD.

76


Intel® Server Board S3420GP TPS Connector/Header Locations and Pin-outs

The following tables define the connector pin-outs.

Table 39. Baseboard Power Connector Pin-out (J9A1)

1

Pin Signal

+3.3 Vdc

Color Pin

Orange 13

Signal

+3.3 Vdc

2 +3.3 Vdc Orange 14 -12 Vdc

3 GND Black 15

Color

Orange

Blue

Black

5 GND Black 17 Black

Black

7 GND Black 19 Black

White

9 5 Purple 21 Red

Red

Red

Black

Table 40. SSI Processor Power Connector Pin-out (J9C1)

Pin Signal Color

1 GND Black

2 GND Black

3 GND Black

4 GND Black

5 +12 Yellow/black

6 +12 Yellow/black

7 +12 Yellow/black

8 +12 Yellow/black

7.3 System Management Headers

7.3.1 Intel

®


®

RMM3) Connector

A 34-pin Intel

®

Intel

®

RMM 3 connector (J2C1) is included on the server board to support the optional

Remote Management Module 3. This server board does not support third-party management cards.

Note: This connector is not compatible with the Intel

®

Remote Management Module (Intel

®

RMM) or the Intel

®


®

RMM2).

Revision 2.4


77


7.3.2

7.3.3

Table 41. Intel

®

RMM3 Connector Pin-out (J2C1)

Pin Signal Name

1 P3V3_AUX

3 P3V3_AUX

5 GND

7 GND

9 GND

11 GND

13 GND

15 GND

17 GND

19 GND

21 GND

23 P3V3_AUX

25 P3V3_AUX

27 P3V3_AUX

29 GND

31 GND

33 GND

Pin Signal Name

2 RMII_IBMC_RMM3_MDIO

4 RMII_IBMC_RMM3_MDC

6 RMII_IBMC_RMM3_RXD1

8 RMII_IBMC_RMM3_RXD0

12 CLK_50M_RMM3

14 RMII_IBMC_RMM3_RX_ER

16 RMII_IBMC_RMM3_TX_EN

18 KEY

20 RMII_IBMC_RMM3_TXD0

22 RMII_IBMC_RMM3_TXD1

24 SPI_IBMC_BK_CS_N

26 TP_RMM3_SPI_WE

28 SPI_IBMC_BK_DO

30 SPI_IBMC_BK_CLK

32 SPI_IBMC_BK_DI

34 FM_RMM3_Present_N

LCP/IPMB Header

Table 42. LPC/IPMB Header Pin-out (J1H2)

Pin

1

Signal Name

SMB_IPMB_5VSB_DAT

2 GND

3 SMB_IPMB_5VSB_CLK

Description

Integrated BMC IMB 5V standby data line

Ground

Integrated BMC IMB 5V standby clock line

+5 V standby power 4 P5V_STBY

HSBP Header

Table 43. HSBP Header Pin-out (J1J1)

Pin Signal Name

1 SMB_HSBP_5V_DAT

2 GND

3 SMB_HSBP_5V_CLK

4 FM_HSBP_ADD_C2

78



7.3.4

Connector/Header Locations and Pin-outs

SGPIO Header

Table 44. SGPIO Header Pin-out (J1J3)

Pin Signal Name Description

1 SGPIO_CLOCK SGPIO Signal

2 SGPIO_LOAD

7.4 Front Control Panel Connector

The server board provides a 24-pin SSI front panel connector (J1C1) for use with Intel

® third-party chassis. The following table provides the pin-out for this connector. and

Table 45. Front Panel SSI Standard 24-pin Connector Pin-out (J1C1)

Pin Signal Name

1 P3V3_AUX

(Power_LED_Anode)

3 Key

5 FP_PWR_LED_N

7 P3V3

(HDD_ACTIVITY_Anode)

Description

Power LED +

No Connection

Power LED -

HDD Activity

LED+

HDD

LED-

11

17

19

21 PU_FM_SIO_TEMP_SE

23

FP_PWR_BTN_N

13 GND

GND)

15 RST_FP_BTN_N

GND (Reset GND)

FP_ID_BTN_N

NSOR

FP_NMI_BTN_N

Power Button

2

4

6

Pin Signal Name

P3V3_STBY

P5V_STBY (ID LED

Anode)

FP_ID_LED_BUF_N

8 FP_LED_STATUS_GR

EEN_N

10 FP_LED_STATUS_AM

BER_N

12 NIC1_ACT_LED_N

Description

Front Panel

Power

ID LED +

ID LED -

Status LED

Green -

Status LED

Amber

NIC 1 Activity

LED -

NIC 1 Link LED Power Button

Ground

14 NIC1_LINK_LED_N

Button 16 SMB_SENSOR_3V3ST

B_DATA

Reset Button

Ground

ID Button

18 SMB_SENSOR_3V3ST

20

22

B_CLK

FP_CHASS_INTRU

NIC2_ACT_LED_N Front Panel

Temperature

Sensor

NMI Button 24 NIC2_LINK_LED_N

SMB Sensor

DATA

SMB Sensor

Clock

Chassis Intrusion

NIC 2 Activity

LED -

NIC 2 Link LED -

Combined system BIOS and the Integrated BMC support provide the functionality of the various supported control panel buttons and LEDs. The following sections describe the supported functionality of each control panel feature.

Note: Control panel features are also routed through the bridge board connector at location

J1C1 as is implemented in Intel

®

Server Systems configured using a bridge board and a hotswap backplane.

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7.4.1 Power Button

The BIOS supports a front control panel power button. Pressing the power button initiates a request that the Integrated BMC forwards to the ACPI power state machines in the chipset. It is monitored by the Integrated BMC and does not directly control power on the power supply.

 Power Button — Off to On

The Integrated BMC monitors the power button and the wake-up event signals from the chipset. A transition from either source results in the Integrated BMC starting the powerup sequence. Since the processor are not executing, the BIOS does not participate in this sequence. The hardware receives the power good and reset signals from the

Integrated BMC and then transitions to an ON state.

 Power Button — On to Off (Operating system absent)

The System Control Interrupt (SCI) is masked. The BIOS sets up the power button event to generate an SMI and checks the power button status bit in the ACPI hardware registers when an SMI occurs. If the status bit is set, the BIOS sets the ACPI power state of the machine in the chipset to the OFF state. The Integrated BMC monitors power state signals from the chipset and de-asserts PS_PWR_ON to the power supply.

As a safety mechanism, if the BIOS fails to service the request, the Integrated BMC automatically powers off the system in 4 to 5 seconds.

 Power Button — On to Off (Operating system present)

If an ACPI operating system is running, pressing the power button switch generates a request using SCI to the operating system to shut down the system. The operating system retains control of the system and the operating system policy determines the sleep state into which the system transitions, if any. Otherwise, the BIOS turns off the system.

7.4.2 Reset Button

The platform supports a front control panel reset button. Pressing the reset button initiates a request forwarded by the Integrated BMC to the chipset. The BIOS does not affect the behavior of the reset button.

7.4.3 NMI Button

The Intel

®

S3420GP Server Board family BIOS does not support the NMI button.

7.4.4 System Status Indicator LED

The Intel

®

Server Board S3420GP that uses the Intel

®

Xeon

®

Processor 3400 Series has a system status indicator LED on the front panel. This indicator LED has specific states and corresponding interpretation as shown in the following table.

Table 46. System Status LED Indicator States

Color

Green

State

Solid on

Criticality

Ok

Description

System booted and ready

80



Color State

Green ~1 Hz blink

Amber ~1 Hz blink

Amber Solid on

Criticality

Degraded

Non-critical

Critical, nonrecoverable

Description

System degraded:

 Non-critical temperature threshold asserted.

 Non-critical voltage threshold asserted.

 Non-critical fan threshold asserted.

 Fan redundancy lost, sufficient system cooling maintained.

This does not apply to non-redundant systems.

 Power supply predictive failure.

 Power supply redundancy lost. This does not apply to nonredundant systems.



Correctable errors over a threshold of 10 and migrating to a spare DIMM (memory sparing). This indicates the user no longer has spared DIMMs indicating a redundancy lost condition. Corresponding DIMM LED should light up.

1

Non-fatal alarm – system is likely to fail:

 CATERR

 Critical temperature threshold asserted.

 Critical voltage threshold asserted.

 Critical fan threshold asserted.

 VRD hot asserted.

 SMI asserted.

Fatal alarm – system has failed or shutdown:

 Thermtrip

 Non-recoverable

 Non-recoverable voltage threshold asserted.

 Power fault/Power Control Failure.

 Fan redundancy lost, insufficient system cooling. This does not apply to non-redundant systems.

Off N/A Not ready AC power off, if no degraded, non-critical, critical, or non-recoverable conditions exist.

Notes:

1. The BIOS detects these conditions and sends a Set Fault Indication command to the Integrated BMC to provide the contribution to the system status LED.

2. Support for upper non-critical limit is not provided in the default SDR configuration. However, if a user does enable this threshold in the SDR, then the system status LED should behave as described.

There is no precedence or lock-out mechanism for the control sources. When a new request arrives, all previous requests are terminated. For example, if the chassis ID LED is blinking and the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is pressed again with no intervening commands, the chassis ID LED turns off.

7.5 I/O Connectors

7.5.1 VGA Connector

The following table details the pin-out definition of the VGA connector (J7A1).

Table 47. VGA Connector Pin-out (J7A1)

1

Pin

2

Signal Name

V_IO_R_CONN

V_IO_G_CONN

Description

Red (analog color signal R)

Green (analog color signal G)

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81


3

Pin Signal Name

V_IO_B_CONN

4 TP_VID_CONN_B4

5 GND

6 GND

7 GND

8 GND

9 TP_VID_CONN_B9

10 GND

11 TP_VID_CONN_B11

12 V_IO_DDCDAT

13

14

V_IO_HSYNC_CONN

V_IO_VSYNC_CONN

15 V_IO_DDCCLK

Description

Blue (analog color signal B)

Ground

Ground

Ground

Ground

Ground

DDCDAT

HSYNC (horizontal sync)

VSYNC (vertical sync)

DDCCLK

7.5.2 Rear NIC and USB connector

The server board provides two stacked RJ-45/2xUSB connectors side-by-side on the back edge of the board (J6A1, J5A1). The pin-out for NIC connectors are identical and defined in the following table.

Table 48. RJ-45 10/100/1000 NIC Connector Pin-out (J5A1)

Pin Signal Name

1 P5V_USB_PWR75

3 USB_PCH_11_FB_DP

5 P5V_USB_PWR75

7 USB_PCH_10_FB_DP

9 P1V9_LAN2_R

11 NIC2_MDIN<0>

13 NIC2_MDIN<1>

15 NIC2_MDIN<2>

17 NIC2_MDIN<3>

19 LED_NIC2_1

21 LED_NIC2_LINK100_R_0

Pin Signal Name

Table 49. RJ-45 10/100/1000 NIC Connector Pin-out (J6A1)

Pin Signal Name

1 P5V_USB_PWR75

3 USB_PCH_11_FB_DP

5 P5V_USB_PWR75

7 USB_PCH_10_FB_DP

9 P1V8_PHY_VCT_R

11 NIC1_MDIN<0>

Pin Signal Name

13 NIC1_MDIN<1>

15 NIC1_MDIN<2>

17 NIC1_MDIN<3>

19 LED_NIC1_LINK_ACT_0_R 20

82



Pin Signal Name

21 LED_NIC1_2

Pin Signal Name

7.5.3 SATA

The sever board provides up to six SATA connectors. The pin configuration for each connector is identical and defined in the following table.

Table 50. SATA Connector Pin-out (J1H4, J1H1, J1G1, J1H3, J1G3, J1F4)

Pin Signal Name

1 GND

2

3

SATA/SAS_TX_P_C

SATA/SAS_TX_N_C

4 GND

5

6

SATA/SAS_RX_N_C

SATA/SAS_RX_P_C

7 GND

Description

Ground

Positive side of transmit differential pair

Negative side of transmit differential pair

Ground

Negative side of receive differential pair

Positive side of receive differential pair

Ground

7.5.4 50-pin PCI Express* Connector

The Intel

®

Server Board S3420GPLX provides one 50-pin PCI Express* connector for Intel

®

SAS Entry RAID Module AXX4SASMOD.

The pin configuration is identical and defined in the following table.

Table 51. 50-pin PCI Express* Connector Pin-out (J2H1)

Pin Signal Name

1 P3V3_AUX

Pin Signal Name

2 P3V3_AUX

3 PE_RST_IO_MODULE_N 4 GND

5 GND 6 PE2_ESB_RXP_C<0>

7 GND 8 PE2_ESB_RXN_C<0>

9 PE2_ESB_TXP_C<0> 10 GND

11 PE2_ESB_TXN_C<0> 12 GND

13 GND

15 GND

14

16

PE2_ESB_RXP_C<1>

PE2_ESB_RXN_C<1>



21 GND 22 PE2_ESB_RXP_C<2>

23 GND 24 PE2_ESB_RXN_C<2>



29 GND

31 GND

30

32

PE2_ESB_RXP_C<3>

PE2_ESB_RXN_C<3>



37 GND 38 CLK_100M_LP_PCIE_SLOT3_P

39 GND

41 PE_WAKE_N

43 P3V3

40

42

44

CLK_100M_LP_PCIE_SLOT3_N

GND

P3V3

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Pin Signal Name

45 P3V3

47 P3V3

49 P3V3

Pin

46 P3V3

48 P3V3

50 P3V3

Signal Name

7.5.5 Serial Port Connectors

The server board provides one external DB9 Serial A port (J8A1) and one internal 9-pin serial B header (J1B2). The following tables define the pin-outs.

Table 52. External Serial A Port Pin-out (J8A1)

1

Pin

2

Signal Name

SPA_DCD

SPA_SIN_L

3

4

SPA_SOUT_N

SPA_DTR

5 GND

6

7

8

9

SPA_DSR

SPA_RTS

SPA_CTS

SPA_RI

10 NC

Description

DCD (carrier detect)

RXD (receive data)

TXD (Transmit data)

DTR (Data terminal ready)

Ground

DSR (data set ready)

RTS (request to send)

CTS (clear to send)

RI (Ring Indicate)

Table 53. Internal 9-pin Serial B Header Pin-out (J1B2)

Pin

1

Signal Name

SPB_DCD

Description

DCD (carrier detect)

4 SPB_RTS RTS (request to send)

6

7

SPB_CTS

SPB_DTR

CTS (clear to send)

DTR (Data terminal ready)

8 SPB_RI RI (Ring indicate)

9 SPB_EN_N Enable

10 NC

7.5.6 USB Connector

There are four external USB ports on two NIC/USB combinations. Section 5.5.2 details the pinout of the connector.

Two 2x5 connector on the server board (J1E1, J1D1) provides an option to support an additional USB port, each connector supporting two USB ports. The following table defines the pin-out of the connector.

Table 54. Internal USB Connector Pin-out ( J1E1, J1D1)

Pin

1

2

Signal Name

USB2_VBUS4

USB2_VBUS5

Description

USB power (port 4)

USB power (port 5)

84



Pin

3

4

Signal Name Description

USB_ICH_P4N_CONN USB port 4 negative signal

USB_ICH_P5N_CONN USB port 5 negative signal

5

6

USB_ICH_P4P_CONN USB port 4 positive signal

USB_ICH_P5P_CONN USB port 5 positive signal

7 Ground

8 Ground

9 Key

10 TP_USB_ICH_NC

One x connector (J1J2) on the server board provides an option to support a USB floppy connector.

Table 55. Pin-out of Internal USB Connector for Floppy ( J1J2)

Pin Signal Name

1 +5V

2 USB_N

3 USB_P

4 GND

One 2x5 connectors (J3F2) on the server board provides an option to support an Intel

Value Solid State Drive. The following table defines the pin-out of the connector.

®

Z-U130

Table 56. Pin-out of Internal USB Connector for low-profile Intel

®

(J3F2)

Z-U130 Value Solid State Drive

Pin Signal Name

1 +5V

2 NC

3 USB Data -

4 NC

5 USB Data +

6 NC

7 Ground

8 NC

9 Key

10 LED#

Description

N/A

USB port ## negative signal

N/A

USB port ## positive signal

N/A

N/A

N/A

7.6 PCI Express* Slot/PCI Slot/Riser Card Slot

A PCI-E Riser card will enable a PCI-E add-on card to be accommodated in the 1U chassis.

The following table shows the pin-out for this riser slot.

Table 57. Pin-out of adaptive riser slot/PCI Express slot 6

Pin Signal

B1 +12V

Description

P12V

B2 +12V P12V

B3 RSVD P12V

Pin

Signal Description

A2 +12V P12V

A3 +12V P12V

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Pin Signal Description Pin

Signal Description

B5 SMCLK PU_S6_SMBCLK

B6 SMDATA PU_S6_SMBDAT

B7 GND GND

B8 +3.3V P3V3

B9 JTAG1 JTAG_S6_TRST_N

B10 +3.3VAUX P3V3_AUX

B11 WAKE_N FM_PE_WAKE_N

KEY

KEY

A5 JTAG2

A6 JTAG3

A10 +3_3V

P3V3_RISER_A5

JTAG_S6_TDI

A7 JTAG4 NC

A8 JTAG5 P3V3_RISER_A8

A9 +3_3V P3V3

P3V3

A11 PERST_N RST_PE_S236_N_R1

KEY

KEY

B12 RSVD

B13 GND

NC

GND

A12 GND GND

A13 REFCLKP CLK_100M_SLOT6A_DP

B14 PETP0 P2E_CPU_C_S6_TXP<7> A14 REFCLKN CLK_100M_SLOT6A_DPN

B15 PETN0 P2E_CPU_C_S6_TXN<7> A15 GND GND

B16 GND GND

B17 PRSNT2_N NC

A16 PERP0 P2E_CPU_S6_RXP<7>

A17 PERN0 P2E_CPU_S6_RXN<7>

B19 PETP1 P2E_CPU_C_S6_TXP<6> A19 RSVD NC

B20 PETN1 P2E_CPU_C_S6_TXN<6> A20 GND

B21 GND GND A21 PERP1

GND

P2E_CPU_S6_RXP<6>

B22 GND GND A22 PERN1 P2E_CPU_S6_RXN<6>

B23 PETP2 P2E_CPU_C_S6_TXP<5> A23 GND


B25 GND GND

GND

GND


B26 GND GND A26 PERN2 P2E_CPU_S6_RXN<5>

B27 PETP3 P2E_CPU_C_S6_TXP<4> A27 GND GND


B29 GND

B30 RSVD

GND

NC

B31 PRSNT2_N NC


A30 PERN3 P2E_CPU_S6_RXN<4>

A31 GND GND

NC B32 GND

End of x4

GND A32 RSVD

End of x4

B33 PETP4 P2E_CPU_C_S6_TXP<3> A33 RSVD NC



GND

P2E_CPU_S6_RXN<3>

B36 GND GND A36 PERN4 P2E_CPU_S6_RXP<3>



B39 GND GND

GND

GND

A39 PERP5 P2E_CPU_S6_RXN<2>

B40 GND GND A40 PERN5 P2E_CPU_S6_RXP<2>

B41 PETP6 P2E_CPU_C_S6_TXP<1> A41 GND GND


B43 GND

B44 GND

GND

GND

A43 PERP6

A44 PERN6


P2E_CPU_S6_RXN<1>

P2E_CPU_S6_RXP<1>

GND



GND

P2E_CPU_S6_RXN<0>

86



Pin Signal

B48 PRSNT2_N NC

Description

End of x8

B50 PETP8 NC

B51 PETN8 NC

B52 GND GND

B53 GND GND

B54 PETP9 NC

B55 PETN9 NC

B56 GND

B57 GND

GND

GND

B58 PETP10 NC

B59 PETN10 NC

B60 GND GND

B61 GND GND

B62 PExP11 NC

B63 PETN11 NC

B64 GND GND

B65 GND GND

B66 PETP12 NC

B67 PETN12 NC

B68 GND

B69 GND

GND

GND

B70 PETP13 NC

B71 PETN13 NC

B72 GND GND

B73 GND GND

B74 PETP14 NC

B75 PETN14 NC

B76 GND

B77 GND

GND

GND

B78 PETP15 NC

B79 PETN15 NC

B80 GND GND

B81 PRSNT2_N NC

B82

RSVD NC

Pin

Signal Description

A48 PERN7 P2E_CPU_S6_RXP<0>

End of x8

A50 RSVD

A51 GND

NC

GND

A52 PERP8 NC

A53 PERN8 NC

A54 GND GND

A55 GND GND

A56 PERP9 NC

A57 PERN9 NC

A58 GND GND

A59 GND GND

A60 PERP10 NC

A61 PERN10 NC

A62 GND

A63 GND

GND

GND

A64 PERP11 NC

A65 PERN11 NC

A66 GND GND

A67 GND GND

A68 PERP12 NC

A69 PERN12 NC

A70 GND GND

A71 GND GND

A72 PERP13 NC

A73 PERN13 NC

A74 GND

A75 GND

GND

GND

A76 PERP14 NC

A77 PERN14 NC

A78 GND

A79 GND

GND

GND

A80 PERP15 NC

A81 PERN15 NC

A82

GND GND

Three PCI Express* x8 connectors (J2B2, J3B1 and J4B2)

Pin Signal Pin Signal Pin Signal

A1 PRSNT1# B1 +12V A26 HSIP[2]

Pin Signal

B26 GND

A3 +12V

A4 GND

Revision 2.4

B3 RESERVED A28 GND

B4 GND A29 HSIP[3]


B28 HSON[3]

B29 GND

87


Pin Signal Pin Signal

A5 JTAG2/TCk B5 SMCLK

A6 JTAG3/TDI B6 SMDAT

A7 JTAG4/TDO B7 GND

Pin Signal

A30 HSIN[3]

Pin Signal

B30 RESERVED

A31 GND B31 PRSNT2#

A32 RESERVED B32 GND

A8 JTAG5/TMS B8 +3.3V

A9 +3.3V

A10 +3.3V

A11 PERST#

B10 3.3VAUX

B11 WAKE#

A33 RESERVED B33 HSOP[4]

A35 HSIP[4]

A36 HSIN[4]

B34 HSON[4]

B35 GND

B36 GND

A13 REFCLK+ B13 GND

A14 REFCLK- B14 HSOP[0]

A15 GND

A16 HSIP[0]

B15 HSON[0]

B16 GND

A17 HSIN[0]

A18 GND

A38 GND

A39 HSIP[5]

A40 HSIN[5]

A41 GND

B17 PRSNT2# A42 GND

B18 GND A43 HSIP[6]

A19 RESERVED B19 HSOP[1] A44 HSIN[6]

B38 HSON[5]

B39 GND

B40 GND

B41 HSOP[6]

B42 HSON[6]

B43 GND

B44 GND

A21 HSIP[1]

A22 HSIN[1]

A23 GND

B21 GND

B22 GND

B23 HSOP[2]

A46 GND

A47 HSIP[7]

A48 HSIN[7]

B46 HSON[7]

B47 GND

B48 PRSNT2#

A25 HSIP[2] B25 GND

One PCI Express* X4 connector (J2B1)

Pin# Signal Pin# Signal

A1 PRSNT1_N B1 +12V

Pin# Signal

A17 PERN0

Pin# Signal

B17 PRSNT2_N

A5 JTAG2

A6 JTAG3

A7 JTAG4

A8 JTAG5

B5 SMCLK

B6 SMDAT

B7 GND

B8 +3.3V

A21 PERP1

A22 PERN1

A23 GND

A24 GND

B21 GND

B22 GND

B23 PETP2

B24 PETN2

88



Pin# Signal

A9 +3.3V

Pin# Signal

B9 JTAG1

Pin# Signal

A25 PERP2

A10 +3.3V B10 3.3VAUX A26 PERN2

A11 PERST_N B11 WAKE_N A27 GND

Pin# Signal

B25 GND

B26 GND

B27 PETP3

A13 REFCLK+ B13 GND

A14 REFCLK- B14 PETP0

A29 PERP3

A30 PERN3

B29 GND

B30 RSVD

A16 PERP0 B16 GND

One PCI X32 connector (J1B1)

Pin # Signal Pin # Signal

A32 RSVD

Pin # Signal

B32 GND

Pin # Signal

B12

B13

GND

GND

A12

A13

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7.7 Fan Headers

The server board provides five SSI-compliant 4-pin fan headers to be used as the CPU and chassis. The pin configuration for each of the 4-pin fan headers is identical and defined in the following table.



One 4-pin fan headers are designated as processor cooling fans:

1

2

3

Pin

4

Table 58. SSI 4-pin Fan Header Pin-out (J6D1, J1J4, J6J2, J7J1, J6B1)

Signal Name

Ground

12 V

Fan Tach

Fan PWM

Type

GND

Description

Ground is the power supply ground

Power Power supply 12 V

In FAN_TACH signal is connected to the Integrated BMC to monitor the fan speed

Out FAN_PWM signal to control fan speed

90


Intel® Server Board S3420GP TPS Jumper Blocks

8. Jumper Blocks

The server board has several 3-pin jumper blocks that can be used to configure, protect, or recover specific features of the server board.

Figure 39. Jumper Blocks (J1A2, J1F1, J1F3, J1F2 and J1F5)

Table 59. Server Board Jumpers (J1F1, J1F2, J1F3, J1F5, J1A2)

Jumper Name

J1F5: CMOS

Clear

J1F1: ME Force

Update

J1F2:

Password Clear

J1F3: BIOS

Recovery

J1A2: BMC

Force Update

Pins

1-2

2-3

1-2

2-3

1-2

2-3

1-2

2-3

1-2

2-3

System Results

These pins should have a jumper in place for normal system operation. (Default)

If these pins are jumpered with AC power plugged, the CMOS settings are cleared within five seconds. These pins should not be jumpered for normal operation.

ME Firmware Force Update Mode – Disabled (Default)

ME Firmware Force Update Mode – Enabled


If these pins are jumpered, administrator and user passwords are cleared within 5-10 seconds after the system is powered on. These pins should not be jumpered for normal operation.


Given that the main system BIOS will not boot with these pins jumpered, system can only boot from EFI-bootable recovery media with the recovery BIOS image.

Integrated BMC Firmware Force Update Mode – Disabled (Default)

Integrated BMC Firmware Force Update Mode – Enabled

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Jumper Blocks Intel® Server Board S3420GP TPS

8.1 CMOS Clear and Password Reset Usage Procedure

The CMOS Clear (J1F5) and Password Reset (J1F2) recovery features are designed such that the desired operation can be achieved with minimal system downtime. The usage procedure for these two features has changed from previous generation Intel server boards. The following procedure outlines the new usage model.

8.1.1 Clearing the CMOS

To clear the CMOS, perform the following steps:

1. Power down the server. Do not unplug the power cord.

2. Open the server chassis. For instructions, see your server chassis documentation.

3. Move jumper (J1F5) from the default operating position (covering pins 1 and 2) to the reset/clear position (covering pins 2 and 3).

4. Wait five seconds.

5. Remove AC power.

6. Move the jumper back to the default position (covering pins 1 and 2).

7. Close the server chassis.

8. Power up the server.

The CMOS is now cleared and can be reset by going into the BIOS setup.

Note: Removing AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down, after the procedure is followed and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds, and reinstall the AC power cord. Power up the system and proceed to the <F2> BIOS Setup utility to reset the preferred settings.

8.1.2 Clearing the Password

To clear the password, perform the following steps:

1. Power down the server. Do not unplug the power cord.

2. Open the chassis. For instructions, see your server chassis documentation.

3. Move jumper (J1F2) from the default operating position (covering pins 1 and 2) to the password clear position (covering pins 2 and 3).


5. Power up the server and wait 10 seconds or until POST completes.

6. Power down the server.

7. Open the chassis and move the jumper back to the default position (covering pins 1 and

2).


9. Power up the server.

The password is now cleared and can be reset by going into the BIOS setup.

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Intel® Server Board S3420GP TPS Jumper Blocks

8.2 Integrated BMC Force Update Procedure (only for the Intel

®

Server Board


When performing the standard Integrated BMC firmware update procedure, the update utility places the Integrated BMC into an update mode, allowing the firmware to load safely onto the flash device. In the unlikely event the Integrated BMC firmware update process fails due to the

Integrated BMC not being in the proper update state, the server board provides an Integrated

BMC Force Update jumper (J1A2), which forces the Integrated BMC into the proper update state. The following procedure should be completed in the event the standard Integrated BMC firmware update process fails.

1. Power down and remove the AC power cord.


3. Move jumper from the default operating position (covering pins 1 and 2) to the enabled position (covering pins 2 and 3).


5. Reconnect the AC cord and power up the server.

6. Perform the Integrated BMC firmware update procedure as documented in the

README.TXT file that is included in the given Integrated BMC firmware update package.

After successful completion of the firmware update process, the firmware update utility may generate an error stating that the Integrated BMC is still in update mode.


8. Open the server chassis.

9. Move jumper from the enabled position (covering pins 2 and 3) to the disabled position

(covering pins 1 and 2).



Note: Normal Integrated BMC functionality is disabled with the Force Integrated BMC Update jumper set to the enabled position. The server should never be run with the Integrated BMC

Force Update jumper set in this position. This jumper setting should only be used when the standard firmware update process fails. This jumper should remain in the default/disabled position when the server is running normally.

8.3 ME Force Update Jumper

When performing the standard ME force update procedure, the update utility places the ME into an update mode, allowing the ME to load safely onto the flash device. In the unlikely event ME firmware update process fails due to ME not being in the proper update state, the server board provides an Integrated BMC Force Update jumper (J1F1), which forces the ME into the proper update state. The following procedure should be completed in the event the standard ME firmware update process fails.



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Jumper Blocks Intel® Server Board S3420GP TPS

3. Move jumper from the default operating position (covering pins 1 and 2) to the enabled position (covering pins 2 and 3).



6. Perform the ME firmware update procedure as documented in the README.TXT file that is included in the given ME firmware update package (same package as BIOS).


8. Open the server chassis.

9. Move jumper from the enabled position (covering pins 2 and 3) to the disabled position

(covering pins 1 and 2).



8.4 BIOS Recovery Jumper

The following procedure boots the recovery BIOS and flashes the normal BIOS:

1. Turn off the system power.

2. Move the BIOS recovery jumper to the recovery state.

3. Insert a bootable BIOS recovery media containing the new BIOS image files.

4. Turn on the system power.

The BIOS POST screen will appear displaying the progress, and the system will boot to the EFI shell. The EFI shell then executes the Startup.nsh batch file to start the flash update process.

The user should then switch off the power and return the recovery jumper to its normal position.

The user should not interrupt the BIOS POST on the first boot after recovery.

When the flash update completes:

1. Remove the recovery media.

2. Turn off the system power.

3. Restore the jumper to its original position.

4. Turn on the system power.

5. Re-flash any custom blocks, such as user binary or language blocks.

The system should now boot using the updated system BIOS.

94


Intel® Server Board S3420GP TPS Intel® Light Guided Diagnostics

9. Intel

®

Light Guided Diagnostics

The server board has several on-board diagnostic LEDs to assist in troubleshooting board-level issues. This section shows where each LED is located on the server board and describes the function of each LED.

9.1 System Status LED (For the Intel

®


S3420GPLC)

The server board provides a system status indicator LED on the front panel. This indicator LED has specific states and corresponding interpretation as shown in the following table.

Table 60. Front Panel Status LED Behavior Summary

Color

Off N/A

State

Amber Solid on

Amber Blink

Green Solid on

Green Blink

Criticality

Not ready

Critical, nonrecoverable

Non-critical

System OK

Degraded

Description

AC power off. If no degraded, non-critical, critical, or nonrecoverable conditions exist.

Fatal alarm – system has failed or shutdown:

Thermtrip asserted.

Non-recoverable temperature threshold asserted.

Non-recoverable voltage threshold asserted.

Power fault/Power Control Failure.

Fan redundancy lost, insufficient system cooling. This does not apply to non-redundant systems.

Uncorrectable memory error.

Non-fatal alarm – system is likely to fail:

CATERR asserted.

Critical temperature threshold asserted.

Critical voltage threshold asserted.

Critical fan threshold asserted.

VRD hot asserted.

SMI Timeout asserted.

Correctable error threshold has been reached for a failing DDR3

DIMM.

System booted and ready.

System degraded:

Non-critical temperature threshold asserted.

Non-critical voltage threshold asserted.

Non-critical fan threshold asserted.

Fan redundancy lost, sufficient system cooling maintained. This does not apply to non-redundant systems.

Power supply predictive failure.

Unable to use all of the installed memory (more than one DDR3

DIMM installed).

Correctable error threshold has been reached for a failing DDR3

DIMM on a given channel.

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Intel® Light Guided Diagnostics Intel® Server Board S3420GP TPS

9.2 Post Code Diagnostic LEDs

During the system boot process, the BIOS executes several platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, The diagnostic LEDs can be used to identify the last POST process executed.

Table 61. POST Code Diagnostic LED Location

A Status LED (For Intel

®

Server Board


B ID LED

C Diagnostic LED #7 (MSB LED)

D Diagnostic LED #6

E Diagnostic LED #5

F Diagnostic LED #4

G Diagnostic LED #3

H Diagnostic LED #2

I Diagnostic LED #1

J Diagnostic LED #0 (LSB LED)

96


Intel® Server Board S3420GP TPS Design and Environmental Specifications

10. Design and Environmental Specifications

10.1 Intel

®

Server Board S3420GP Design Specifications

The operation of the server board at conditions beyond those shown in the following table may cause permanent damage to the system. Exposure to absolute maximum rating conditions for extended periods may affect system reliability.

Table 62. Server Board Design Specifications

Operating Temperature

Non-Operating Temperature

DC Voltage

Shock (Unpackaged)

Shock (Packaged)

<20 pounds

20 to <40 pounds

40 to <80 pounds

80 to <100 pounds

100 to <120 pounds

120 pounds

Vibration (Unpackaged)

0º C to 55º C

1

(32º F to 131º F)

-40º C to 70º C (-40º F to 158º F)

± 5% of all nominal voltages

Trapezoidal, 50 G, 170 inches/sec

36 inches

30 inches

24 inches

18 inches

12 inches

9 inches

5 Hz to 500 Hz 3.13 g RMS random

1

Chassis design must provide proper airflow to avoid exceeding the Intel temperature.

®

Xeon

®

processor maximum case

Disclaimer Note: Intel Corporation server boards contain a number of high-density VLSI and power delivery components that need adequate airflow to cool. Intel ensures through its own chassis development and testing that when Intel server building blocks are used together, the fully integrated system will meet the intended thermal requirements of these components. It is the responsibility of the system integrator who chooses not to use Intel developed server building blocks to consult vendor datasheets and operating parameters to determine the amount of airflow required for their specific application and environmental conditions. Intel Corporation cannot be held responsible, if components fail or the server board does not operate correctly when used outside any of their published operating or non-operating limits.

10.2 Board-level Calculated MTBF

This section provides results of MTBF (Mean Time Between Failures) testing done by a third party testing facility. MTBF is a standard measure for the reliability and performance of the board under extreme working conditions. The MTBF was measured at 20000 hours at 35 degrees Celsius.

The following table shows the MTBF for the server boards as configured from the factory;

Product Code

Intel

®


Intel

®

Server Board S3420GPLC

Intel

®


Calculated MTBF

335000 hours

335000 hours

277139 hours

Operating Temperature

35 degrees C

35 degrees C

35 degrees C

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97

Design and Environmental Specifications Intel® Server Board S3420GP TPS

10.3 Server Board Power Requirements

This section provides power supply design guidelines for a system using the Intel

®

Server Board

S3420GP, including voltage and current specifications, and power supply on/off sequencing characteristics. The following diagram shows the power distribution implemented on this server board.

Figure 40. Power Distribution Block Diagram

10.3.1 Processor Power Support

The server board supports the Thermal Design Power (TDP) guideline for Intel

®

Xeon

® processor. The Flexible Motherboard Guidelines (FMB) were also followed to help determine the suggested thermal and current design values for anticipating future processor needs. The following table provides maximum values for Icc, TDP power and T

CASE

Processor 3400 Series.

for the Intel

®

Xeon

®

Table 63. Intel

®

Xeon

®

Processor TDP Guidelines

95 W

TDP Power Maximum T

CASE

67.0º C

Icc Maximum

150 A

98


Intel® Server Board S3420GP TPS Design and Environmental Specifications

10.4 Power Supply Output Requirements

This section is for reference purposes only. The intent is to provide guidance to system designers to determine a power supply for use with this server board. This section specifies the power supply requirements Intel used to develop a power supply for the Intel

®

Server System

SR1630GP and SR1630HGP.

The following tables define two power and current ratings for this 350-W power supply. The combined output power of all outputs should not exceed the rated output power. The power supply must meet both static and dynamic voltage regulation requirements for the minimum loading conditions.

Table 64. 350-W Load Ratings

10.4.1

Voltage

+3.3 V

+5 V

+12 V

-12 V

+5 VSB

0A

Minimum Continuous

0.2A

1.0 A

1.5A

0.1 A

14 A

18A

24 A

0.3A

Maximum Continuous

2.0 A

28A

2.5 A

Peak

Notes:

1. Maximum continuous total DC output power should not exceed 350 W.

2. Peak total DC output power should not exceed 400 W.

3. Peak power and peak current loading should be supported for a minimum of 12 seconds.

4. Combined 3.3 V/5 V power should not exceed 100 W.

Grounding

The grounds of the power supply output connector pins provide the power return path. The output connector ground pins are connected to the safety ground (power supply enclosure).

This grounding is designed to ensure passing the maximum allowed common mode noise levels.

The power supply is provided with a reliable protective earth ground. All secondary circuits are connected to protective earth ground. Resistance of the ground returns to chassis does not exceed 1.0 m

. This path may be used to carry DC current.

10.4.2 Standby Outputs

The 5 VSB output is present when an AC input greater than the power supply turn on voltage is applied.

10.4.3 Remote Sense

The power supply has remote sense return (ReturnS) to regulate out ground drops for all output voltages: +3.3 V, +5 V, +12 V, -12 V, and 5 VSB. The power supply uses remote sense to regulate out drops in the system for the +3.3 V, +5 V, and 12 V outputs. The power supply must operate within specification over the full range of voltage drops from the power supply’s output connector to the remote sense points.

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99


10.4.4 Voltage Regulation

The power supply output voltages must stay within the following voltage limits when operating at steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.

All outputs are measured with reference to the return remote sense signal (ReturnS).

Table 65. Voltage Regulation Limits

Parameter

+ 3.3 V

+ 5 V

+ 12 V

- 12 V

+ 5 VSB

Tolerance

- 5%/+5%

- 5%/+5%

- 5%/+5%

- 10%/+10%

- 5%/+5%

Minimum

+3.14

+4.75

+11.40

-13.20

+4.75

Normal

+3.30

+5.00

+12.00

-12.00

+5.00

Maximum

+3.46

+5.25

+12.60

-10.80

+5.25

Units

Vrms

Vrms

Vrms

Vrms

Vrms

10.4.5 Dynamic Loading

The output voltages remain within limits for the step loading and capacitive loading specified in the following table. The load transient repetition rate is tested between 50 Hz and 5 kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a test specification. The

 step load may occur anywhere within the Min load to the Max load conditions.

Table 66. Transient Load Requirements

+3.3 V

+5 V

12 V

+5 VSB

Output  Step Load Size

(See note 1)

5.0 A

6.0 A

11.0 A

0.5 A

Load Slew Rate Test capacitive Load

0.25 A/

sec 250

0.25 A/

sec 400

0.25 A/

sec 500

0.25 A/

sec 20

Notes:

1. Step loads on each 12 V output may happen simultaneously and should be tested that way.

10.4.6 Capacitive Loading

The power supply is stable and meets all requirements with the following capacitive loading ranges.

Table 67. Capacitve Loading Conditions

Output

+3.3 V

+5 V

+12 V

-12 V

+5 VSB

100

Minimum

400

500

1

20

Maximum

2200

2200

2200

350

350

F

Units

F

F

F

F

10.4.7 Closed-loop Stability

The power supply is unconditionally stable under all line/load/transient load conditions including capacitive load ranges. A minimum of 45° phase margin and -10 dB-gain margin is required.

The power supply manufacturer provides proof of the unit’s closed-loop stability with local

100


Intel® Server Board S3420GP TPS Design and Environmental Specifications sensing through the submission of Bode plots. Closed-loop stability is ensured at the maximum and minimum loads as applicable.

10.4.8 Common Mode Noise

The Common Mode noise on any output does not exceed 350 mV pk-pk over the frequency band of 10 Hz to 20 MHz.

 The measurement is made across a 100Ω resistor between each of the DC outputs, including ground, at the DC power connector and chassis ground (power subsystem enclosure).

 The test setup uses a FET probe such as Tektronix* model P6046 or equivalent.

10.4.9 Ripple/Noise

The maximum allowed ripple/noise output of the power supply is defined in the following table.

This is measured over a bandwidth of 0 Hz to 20 MHz at the power supply output connectors. A

10

F tantalum capacitor is placed in parallel with a 0.1 F ceramic capacitor at the point of measurement.

Table 68. Ripple and Noise

+3.3 V

50 mVp-p

+5 V

50 mVp-p

+12 V

120 mVp-p

-12 V

120 mVp-p

+5 VSB

50 mVp-p

10.4.10 Timing Requirements

The timing requirements for the power supply operation are as follows:







The output voltages must rise from 10% to within regulation limits (T vout_rise

) within 5 ms to 70 ms, except for 5 VSB, in which case it is allowed to rise from 1.0 ms to 25 ms.

The +3.3 V, +5 V, and +12 V output voltages should start to rise approximately at the same time.

All outputs must rise monotonically.





The +5 V output must be greater than the +3.3 V output during any point of the voltage rise.

The +5 V output must never be greater than the +3.3 V output by more than 2.25 V.





Each output voltage should reach regulation within 50 ms (T vout_on

) of each other when the power supply is turned on.

Each output voltage should fall out of regulation within 400 msec (T vout_off when the power supply is turned off.

) of each other

Figure 41 and Figure 42 shows the timing requirements for the power supply being turned on and off via the AC input with PSON held low and the PSON signal with the AC input applied.

Table 69. Output Voltage Timing

Item

T vout_rise

T vout_on

T vout_off

Description

Output voltage rise time from each main output.

All main outputs must be within regulation of each other within this time.

All main outputs must leave regulation within this time.

5.0

1

Minimum

70

1

Maximum Units

Msec

Revision 2.4


101

Design and Environmental Specifications

Note:

1. The 5 VSB output voltage rise time should be from 1.0 ms to 25.0 ms.


Item

T sb_on_delay

T ac_on_delay

T vout_holdup

T pwok_holdup

T pson_on_delay

T pson_pwok

T pwok_on

T pwok_off

T pwok_low

T sb_vout

Figure 41. Output Voltage Timing

Table 70. Turn On/Off Timing

Description

Delay from AC being applied to 5 VSB being within regulation.

Delay from AC being applied to all output voltages being within regulation.

Duration for which all output voltages stay within regulation after loss of AC. Measured at 80% of maximum load.

Delay from loss of AC to de-assertion of PWOK.

Measured at 80% of maximum load.

Delay from PSON

#

active to output voltages within regulation limits.

Delay from PSON

# asserted.

deactive to PWOK being de-

Delay from output voltages within regulation limits to PWOK asserted at turn on.

Delay from PWOK de-asserted to output voltages

(3.3 V, 5 V, 12 V, -12 V) dropping out of regulation limits.

Duration of PWOK being in the de-asserted state during an off/on cycle using AC or the PSON signal.

Delay from 5 VSB being in regulation to O/Ps being in regulation at AC turn on.

Minimum Maximum

Msec

21 N/A

N/A 50

100 500

Msec

Msec

1 N/A

Units

Msec

100 N/A

Msec

102


Item

T

5VSB_holdup


Description

Duration for which the 5 VSB output voltage stays within regulation after loss of AC.

Design and Environmental Specifications

Minimum Maximum Units

Figure 42. Turn On/Off Timing (Power Supply Signals)

10.4.11 Residual Voltage Immunity in Standby Mode

The power supply is immune to any residual voltage placed on its outputs (typically, a leakage voltage through the system from standby output) up to 500 mV. There is no additional heat generated nor stressing of any internal components with this voltage applied to any individual output and all outputs simultaneously. It also does not trip the power supply protection circuits during turn on.

The residual voltage at the power supply outputs for a no-load condition does not exceed 100 mV when AC voltage is applied and the PSON# signal is de-asserted.

10.4.12 Protection Circuits

Protection circuits inside the power supply should cause only the power supply’s main outputs to shut down. If the power supply latches off due to a protection circuit tripping, an AC cycle

OFF for 15 seconds and a PSON

#

cycle HIGH for 1 second should reset the power supply.

10.4.12.1 Over-current Protection (OCP)

The power supply has current limits to prevent the +3.3 V, +5 V, and +12 V outputs from exceeding the values shown in the following table. If the current limits are exceeded, the power supply shuts down and latches off. The latch is cleared by toggling the PSON

#

signal or using an AC power interruption. The power supply is not damaged from repeated power cycling in this condition. -12 V and 5 VSB are protected under over-current or shorted conditions so no damage can occur to the power supply. Auto-recovery feature is a requirement on 5 VSB rail.

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103


Table 71. Over-Current Protection (OCP)

Voltage

+3.3V 15A

+5V 20A

Over Current Limit

Min

+12V 30A

-12V 0.625A

5VSB N/A

Max

21A

27A

40A

2A

4A

10.4.12.2 Over-Voltage Protection (OVP)

The power supply over-voltage protection is locally sensed. The power supply shuts down and latches off after an over-voltage condition occurs. You can clear this latch by toggling the

PSON

#

signal or using an AC power interruption. The following table contains the over-voltage limits. The values are measured at the output of the power supply’s connectors. The voltage never exceeds the maximum levels when measured at the power pins of the power supply connector during any single point of fail. The voltage never trips any lower than the minimum levels when measured at the power pins of the power supply connector.

Exception: +5 VSB rail should be able to recover after an over-voltage condition occurs.

Table 72. Over-voltage Protection (OVP) Limits

Output Voltage

+3.3 V

+5 V

+12 V

-12 V

+5 VSB

Minimum (V)

3.9

5.7

13.3

-13.3

5.7

Maximum (V)

4.5

6.2

14.5

-14.5

6.5

104


Intel® Server Board S3420GP TPS Regulatory and Certification Information

11. Regulatory and Certification Information

11.1 Product Regulatory Compliance

Intended Application –This product is to be evaluated and certified as Information Technology

Equipment (ITE), which may be installed in offices, schools, computer rooms, and similar commercial type locations. The suitability of this product for other product certification categories and/or environments (such as: medical, industrial, telecommunications, NEBS, residential, alarm systems, test equipment, etc.), other than an ITE application, will require further evaluation and may require additional regulatory approvals.

Note: The use and/or integration of telecommunication devices such as modems and/or wireless devices have not been planned for with respect to these systems. If there is any change of plan to use such devices, then telecommunication type certifications will require additional planning. If NEBS compliance is required for system level products, additional certification planning and design will be required.

11.1.1 Product Safety Compliance



CSA 60950-1 Certification (Canada) or cUL









CE Declaration to EU Low Voltage Directive 2006/95/EC (Europe – EN60950-1)

IEC60950-1 (International) CB Certificate & Report, (report to include all CB country national deviations)

BSMI Declaration of Conformity (Taiwan)

UL 60950-1 Recognition (USA

)

11.1.2 Product EMC Compliance – Class A Compliance

Note: This product requires complying with Class A EMC requirements. However, Intel targets a

10 db margin to support customer enablement.



















AS/NZS CISPR 22 Emissions (Australia/New Zealand)

ICES-003 – (Canada)

EN55022 - Emissions (Europe)

EN55024 - Immunity (Europe)

CE – EMC Directive 2004/108/EC (Europe)

CISPR 22 – Emissions (International)

KCC MIC Notice No. 1997-41 (EMC) & 1997-42

(EMI) (Korea)

BSMI CNS13438 Emissions (Taiwan)

FCC – Part 15 Emissions (USA) Verification

Revision 2.4


105

Regulatory and Certification Information Intel® Server Board S3420GP TPS

11.1.3 Certifications/Registrations/Declarations



UL Certification (US/Canada)





CE Declaration of Conformity (CENELEC Europe)

FCC/ICES-003 Class A Attestation (USA/Canada)









C-Tick Declaration of Conformity (Australia)

MED Declaration of Conformity (New Zealand)

BSMI Declaration (Taiwan)





RRL Certification (Korea)

GOST – Listed on one System License (Russia)



Belarus – Listed on one System License (Belarus)

Ecology Declaration (International)

11.1.4 Product Ecology Requirements

Intel restricts the use of banned substances in accordance with world wide product ecology regulatory requirements. Suppliers Declarations of Conformity to the banned substances must be obtained from all suppliers; and a Material Declaration Data Sheet (MDDS) must be produced to illustrate compliance. Due verification of random materials is required as a screening/audit to verify suppliers declarations.

The server board complies with the following ecology regulatory requirements:

















All materials, parts, and subassemblies must not contain restricted materials as defined in Intel’s Environmental Product Content Specification of Suppliers and Outsourced

Manufacturers – http://supplier.intel.com/ehs/environmental.htm

.

Europe - European Directive 2002/95/EC - Restriction of Hazardous Substances (RoHS)

Threshold limits and banned substances are noted below.

Quantity limit of 0.1% by mass (1000 PPM) for Lead, Mercury, Hexavalent Chromium,

Polybrominated Biphenyls Diphenyl Ethers (PBB/PBDE)

Quantity limit of 0.01% by mass (100 PPM) for Cadmium

China RoHS

All plastic parts that weigh >25gm shall be marked with the ISO11469 requirements for recycling. Example >PC/ABS<

EU Packaging Directive

CA. Lithium Perchlorate insert Perchlorate Material – Special handling may apply. Refer to http://www.dtsc.ca.gov/hazardouswaste/perchlorate .

This notice is required by California Code of Regulations, Title 22, Division 4.5, Chapter

33: Best Management Practices for Perchlorate Materials. This product/part includes a battery which contains Perchlorate material.

German Green Dot

Japan Recycling

106



11.2 Product Regulatory Compliance Markings

The server board is provided with the following regulatory marks .

Regulatory Compliance

UL Mark

Region

USA/Canada

Marking

CE Mark Europe

EMC Marking (Class A) Canada

BSMI Marking (Class A) Taiwan

CANADA ICES-003 CLASS A

D33025

C-tick Marking

RRL MIC Mark

Australia/New Zealand

N232

Korea

Country of Origin

Model Designation

PB Free Marking?

China RoHS Marking

인증번호 : CPU-S3420GP (A)

Exporting Requirements MADE IN xxxxx (Provided by label, not silk screen)

Regulatory Identification

S3420GP

Environmental

Requirements

China

Refer to Jedec Standard J-STD609

China Recycling Package

Marking

(Marked on packaging label)

China

Revision 2.4


107

Regulatory and Certification Information

Regulatory Compliance

Other Recycling Package

Marking


Region

Other Recycling

Package Marks


Marking

Other Recycling Package

Marking


CA. Lithium Perchlorate insert

Perchlorate Material – Special handling may apply. See www.dtsc.ca.gov/hazardouswaste/perchlorate

This notice is required by California Code of

Regulations, Title 22, Division 4.5, Chapter 33:

Best Management Practices for Perchlorate

Materials. This product/part includes a battery which contains Perchlorate material.

108



11.3 Electromagnetic Compatibility Notices

11.3.1 FCC Verification Statement (USA)

This device complies with Part 15 of the FCC Rules. Operation is subject to two conditions: (1)

This device may not cause harmful interference, and (2) this device must accept any interference received, including interference that may cause undesired operation.

Intel Corporation

5200 N.E. Elam Young Parkway

Hillsboro, OR 97124-6497

Phone: 1-800-628-8686

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses, and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of these measures:





Reorient or relocate the receiving antenna.

Increase the separation between the equipment and the receiver.





Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.

Consult the dealer or an experienced radio/TV technician for help.

Any changes or modifications not expressly approved by the grantee of this device could void the user’s authority to operate the equipment. The customer is responsible for ensuring compliance of the modified product.

All cables used to connect to peripherals must be shielded and grounded. Operation with cables, connected to peripherals that are not shielded and grounded may result in interference to radio and TV reception.

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109

Regulatory and Certification Information Intel® Server Board S3420GP TPS

11.3.2 ICES-003 (Canada)

Cet appareil numérique respecte les limites bruits radioélectriques applicables aux appareils numériques de Classe B prescrites dans la norme sur le matériel brouilleur:

“Appareils Numériques”, NMB-003 édictée par le Ministre Canadian des Communications.

English translation of the notice above:

This digital apparatus does not exceed the Class B limits for radio noise emissions from digital apparatus set out in the interference-causing equipment standard entitled “Digital Apparatus,”

ICES-003 of the Canadian Department of Communications.

11.3.3 Europe (CE Declaration of Conformity)

This product has been tested in accordance too, and complies with the Low Voltage Directive

(73/23/EEC) and EMC Directive (89/336/EEC). The product has been marked with the CE Mark to illustrate its compliance.

11.3.4 VCCI (Japan)


This is a Class B product based on the standard of the Voluntary Control Council for

Interference (VCCI) from Information Technology Equipment. If this is used near a radio or television receiver in a domestic environment, it may cause radio interference. Install and use the equipment according to the instruction manual.

110



11.3.5 BSMI (Taiwan)

The BSMI Certification Marking and EMC warning is located on the outside rear area of the product.

11.3.6 RRL (Korea)

Following is the

RRL certification information for Korea.


1. Type of Equipment (Model Name): On License and Product

2. Certification No.: On RRL certificate. Obtain certificate from local Intel representative

3. Name of Certification Recipient: Intel Corporation

4. Date of Manufacturer: Refer to date code on product

5. Manufacturer/Nation: Intel Corporation/Refer to country of origin marked on product

Revision 2.4


111

Appendix A: Integration and Usage Tips Intel® Server Board S3420GP TPS

Appendix A: Integration and Usage Tips



















When adding or removing components or peripherals from the server board, AC power must be removed. With AC power plugged into the server board, 5-Volt standby is still present even though the server board is powered off.

Supports only Intel

®

Xeon

®

Processor 3400 Series with 95 W and less Thermal Design

Power (TDP). Does not support previous generations of the Intel

®

Xeon

®

processor.

On the back edge of the server board are diagnostic LEDs that display a sequence of amber POST codes during the boot process. If the server board hangs during POST, the

LEDs displays the last POST event run before the hang.

Supports only registered DDR3 DIMMs (RDIMMs) and unbuffered DDR3 DIMMs

(UDIMMs). Does not support the mixing of RDIMMs and UDIMMs.

For the best performance, the number of DDR3 DIMMs installed should be balanced across both processor sockets and memory channels. For example, a two-DIMM configuration performs better than a one-DIMM configuration. In a two-DIMM configuration, DIMMs should be installed in DIMM sockets A1 and A2. A six-DIMM configuration (DIMM socketsA1, A2, A3, B1, B2 and B3) performs better than a three-

DIMM configuration (DIMM sockets A1, A2, and A3).

The Intel

®

Remote Management Module 3 (Intel with the Intel

®

®

RMM3) connector is not compatible

Remote Management Module (Product Order Code - AXXRMM) or Intel

®

Remote Management Module 2 (Product Order Code - AXXRMM2).

Clear the CMOS with the AC power cord plugged in. Removing the AC power before performing the CMOS clear operation causes the system to automatically power up and immediately power down after the CMOS clear procedure is followed and AC power is re-applied. If this happens, remove the AC power cord, wait 30 seconds, and then reconnect the AC power cord. Power up the system and proceed to the <F2> BIOS Setup utility to reset the needed settings.

Normal Integrated BMC functionality is disabled with the force Integrated BMC update jumper set to the “enabled” position (pins 2-3). The server should never be run with the

Integrated BMC force update jumper set in this position and should only be used when the standard firmware update process fails. This jumper should remain in the default

(disabled) position (pins 1-2) when the server is running normally.

When performing a normal BIOS update procedure, the BIOS recovery jumper must be set to its default position (pins 1-2).

112


Intel® Server Board S3420GP TPS Appendix B: Integrated BMC Sensor Tables

Appendix B: Integrated BMC Sensor Tables

This appendix lists the sensor identification numbers and information about the sensor type, name, supported thresholds, assertion and de-assertion information, and a brief description of the sensor purpose. See the Intelligent Platform Management Interface Specification, Version

2.0, for sensor and event/reading-type table information.







Sensor Type

The Sensor Type values are the values enumerated in the Sensor Type Codes table in the IPMI specification. The Sensor Type provides the context in which to interpret the sensor, such as the physical entity or characteristic that is represented by this sensor.

Event/Reading Type

The Event/Reading Type values are from the Event/Reading Type Code Ranges and

Generic Event/Reading Type Codes tables in the IPMI specification. Digital sensors are a specific type of discrete sensor, which have only two states.

Event Offset/Triggers

Event Thresholds are event-generating thresholds for threshold types of sensors.

-

[u,l][nr,c,nc]: upper non-recoverable, upper critical, upper non-critical, lower nonrecoverable, lower critical, lower non-critical

- uc, lc: upper critical, lower critical

Event Triggers are supported event-generating offsets for discrete type sensors. The offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes tables in the IPMI specification, depending on whether the sensor event/reading type is generic or a sensor-specific response.



Assertion/De-assertion Enables

Assertion and de-assertion indicators reveal the type of events the sensor generates:





Readable Value/Offsets

-

Readable Value indicates the type of value returned for threshold and other nondiscrete type sensors.

-

Readable Offsets indicate the offsets for discrete sensors that are readable with the

Get Sensor Reading command. Unless otherwise indicated, all event triggers are readable; Readable Offsets consist of the reading type offsets that do not generate events.

Event Data

Event data is the data that is included in an event message generated by the sensor. For threshold-based sensors, the following abbreviations are used:

Revision 2.4


113

Appendix B: Integrated BMC Sensor Tables Intel® Server Board S3420GP TPS



Rearm Sensors

The rearm is a request for the event status for a sensor to be rechecked and updated upon a transition between good and bad states. Rearming the sensors can be done manually or automatically. This column indicates the type supported by the sensor. The following abbreviations are used to describe a sensor:







-

M: Manual rearm

Default Hysteresis

The hysteresis setting applies to all thresholds of the sensor. This column provides the count of hysteresis for the sensor, which can be 1 or 2 (positive or negative hysteresis).

Criticality

Criticality is a classification of the severity and nature of the condition. It also controls the behavior of the Control Panel Status LED

Standby

Some sensors operate on standby power. These sensors may be accessed and/or generate events when the main (system) power is off, but AC power is present.

114



Sensor Name

3

IPMI Watchdog

Physical Scrty

FP Interrupt

(NMI)

System Event Log

System Event

(System Event)

BB +1.05 PCH

Table 73. Integrated BMC Core Sensors

Sensor # Platform

Applicability

Sensor Type

03h All

Watchdog 2

23h

04h

Chassis

Intrusion is chassisspecific

Physical

Security

05h

Critical

05h All

Interrupt

13h

07h All

Event

Logging

Disabled

10h

08h All

System

Event

12h

Event /

Reading

Type

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Sensor

Specific

6Fh

Event Offset

Triggers

Contrib. To

System

Status

OK 00 - Timer expired, status only

01 - Hard reset

02 - Power down

03 - Power cycle

08 - Timer interrupt

00 - Chassis intrusion

04 - LAN least lost

00 - Front panel

NMI/diagnostic interrupt

OK

Degraded

OK

02 - Log area reset/cleared

04 – PEF action

OK

10h All

Voltage

02h

Threshold

01h

[u,l] [c,nc] nc =

Degraded c = Nonfatal

Assert /

Deassert

Readable

Value /

Offsets

As and

De

As and

De

Analog

Event

Data

R, T

Rearm Standby

A X

A

X

A –

A –

Revision 2.4


115


Sensor Name

3

BB +1.1V P1 Vccp

Sensor # Platform

Applicability

Sensor Type

11h All

Voltage

02h

Event /

Reading

Type

Threshold

01h

BB +1.1V P2 Vccp

BB +1.5V P1 DDR3

BB +1.5V P2 DDR3

BB +1.8V AUX

BB +3.3V

BB +3.3V STBY

BB Vbat

12h All

13h

14h

15h

16h

17h

18h

All

All

All

All

All

All

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Voltage

02h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Threshold

01h

Generic

05h

Event Offset

Triggers

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

01 - Limit exceeded

Contrib. To

System

Status nc =

Degraded c = Nonfatal nc =







Assert /

Deassert

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

As and

De

Non-fatal

As and

De

Readable

Value /

Offsets

Analog

Analog

Analog

Analog

Analog

Analog

Analog

Event

Data

R, T

R, T

R, T

R, T

R, T

R, T

R, T

Rearm Standby

A

A

A

A

A

A

A

–

–

–

–

X

–

X

A X

116



Sensor Name

BB +5.0V

BB +12.0V

BB -12.0V

3

BB +5.0V STBY

Server board Temp

Front panel temp

PCH Thermal Margin

Processor MEMTHRM

MRGN

Sensor # Platform

Applicability

Sensor Type

19h All

Voltage

02h

Event /

Reading

Type

Threshold

01h

1Ah

1Bh

1Ch

20h

All

All

All

All

Voltage

02h

Voltage

02h

Voltage

02h

Threshold

01h

Threshold

01h

Threshold

01h

Temperatur e

01h

Threshold

01h

21h All

Temperatur e

01h

22h All

Temperatur e

01h

Temperatur

23h All e

01h

Threshold

01h

Threshold

01h

Threshold

01h

Event Offset

Triggers

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

[u,l] [c,nc]

Contrib. To

System

Status nc =







Assert /

Deassert

As and

De

Readable

Value /

Offsets

Analog

As and

De

Analog

As and

De

As and

De

As and

De

As and

De

Analog

Analog

Analog

Analog

Event

Data

R, T

R, T

R, T

R, T

R, T

R, T

Rearm Standby

A

A

A

A

A

A

–

X

–

–

X

X

Revision 2.4


117


Sensor Name

3

Fan Tach Sensors

Sensor # Platform

Applicability

Sensor Type

30h–

34h

Chassisspecific

Fan

04h

Event /

Reading

Type

Threshold

01h

Processor Therm

Margin

Processor Therm Ctrl %

Processor VRD Temp

Temperatur

62h All e

01h

64h

66h

All

All

Temperatur e

01h

Temperatur e

01h

PCH Thermal Trip 6Ah

All

All

07h

Temperatur e

01h

Threshold

01h

Threshold

01h

Digital

Discrete

05h

Digital

Discrete

03h

Digital

Discrete

03h

Event Offset

Triggers

[l] [c,nc]

Contrib. To

System

Status nc =


2

Assert /

Deassert

Readable

Value /

Offsets

As and

De

Analog

Event

Data

R, T

[u] [c]

01 - Limit exceeded

01 – State

Asserted

01 – State

Asserted

Rearm Standby

M

Non-fatal

As and

De

Analog Trig Offset

Fatal

Fatal

As and

De

Non-fatal

As and

De

As and

De

A –

M –

M –

M –

118


Intel® Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder

Appendix C: POST Code Diagnostic LED Decoder

During the system boot process, the BIOS executes a number of platform configuration processes, each of which is assigned a specific hex POST code number. As each configuration routine is started, the BIOS displays the POST code to the POST Code Diagnostic LEDs on the back edge of the server board. To assist in troubleshooting a system hang during the POST process, you can use the diagnostic LEDs to identify the last POST process executed.

Each POST code is represented by the eight amber diagnostic LEDs. The POST codes are divided into two nibbles: an upper nibble and a lower nibble. The upper nibble bits are represented by diagnostic LEDs #4, #5, #6, and #7. The lower nibble bits are represented by diagnostics LEDs #0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, then the corresponding LED is lit. If the bit is clear, then the corresponding LED is off.

The diagnostic LED #7 is labeled as “MSB”, and the diagnostic LED #0 is labeled as “LSB”.

Figure 43. Diagnostic LED Placement Diagram

In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The

LEDs are decoded as follows:

Table 74. POST Progress Code LED Example

LEDs

Status

MSB

LED #7

8h

ON

1

Upper Nibble LEDs

LED #6

4h

LED #5

2h

OFF ON

LED #4

1h

OFF

LED #3

8h

ON

Lower Nibble LEDs

LED #2

4h

LED #1

2h

OFF ON

Results



0 1 0 1 1 0

Ah Ch

Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as ACh.

LSB

LED #0

1h

OFF

0

Revision 2.4


119

Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S3420GP TPS

Table 75. Diagnostic LED POST Code Decoder

Checkpoint

LED

Host Processor

Diagnostic LED Decoder

O = On, X=Off

Upper Nibble

MSB

Lower Nibble

LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

Description

0x04h X X X X X O X X Early processor initialization (flat32.asm) where system BSP is selected

0x10h X X X O X X X X Power-on initialization of the host processor (Boot Strap Processor)

0x11h X X X O X X X O Host processor cache initialization (including AP)

0x12h X X X O X X O X Starting application processor initialization

0x13h X X X O X X O O SMM initialization

Chipset

0x21h X X O X X X X O Initializing a chipset component

Memory

0x22h X X O X X X O X Reading configuration data from memory (SPD on FBDIMM)

0x23h X X O X X X O O Detecting presence of memory

0x24h X X O X

0x25h X X O X X O X O Configuring memory parameters in the memory controller

0x26h X X O X X O O X Optimizing memory controller settings

0x27h X X O X X O O O Initializing memory, such as ECC init

0x28h X X O X O X X X Testing memory

PCI Bus

0x50h X O X O X X X X Enumerating PCI buses

0x51h X O X O X X X O Allocating resources to PCI buses

0x52h X O X O X X O X Hot Plug PCI controller initialization

0x53h X O X O X X O O Reserved for PCI bus

0x54h X O X O X O X X Reserved for PCI bus

0x55h X O X O X O X O Reserved for PCI bus

0x56h X O X O X O O X Reserved for PCI bus

0x57h X O X O X O O O Reserved for PCI bus

USB

0x58h X O X O O X X X Resetting USB bus

0x59h X O X O O X X O Reserved for USB devices

ATA/ATAPI/SATA

0x5Ah X O X O O X O X Resetting SATA bus and all devices

0x5Bh X O X O O X O O Detecting the presence of ATA device

0x5Ch X O X O O O X X Enable SMART if supported by ATA device

0x5Dh X O X O O O X O Reserved for ATA

SMBUS

0x5Eh X O X O O O O X Resetting SMBUS

0x5Fh X O X O O O O O Reserved for SMBUS

Local Console

0x70h X O O O X X X X Resetting the video controller (VGA)

0x71h X O O O X X X O Disabling the video controller (VGA)

0x72h X O O O X X O X Enabling the video controller (VGA)

Remote Console

120


Intel® Server Board S3420GP TPS Appendix C: POST Code Diagnostic LED Decoder

Checkpoint

LED

MSB


O = On, X=Off

Upper Nibble Lower Nibble

LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

0x78h X O O O O X X X Resetting the console controller

Description

0x79h X O O O O X X O Disabling the console controller

0x7Ah X O O O O X O X Enabling the console controller

Keyboard (only USB)

0x90h O X X O X X X X Resetting the keyboard

0x91h O X X O X X X O Disabling the keyboard

0x92h O X X O X X O X Detecting the presence of the keyboard

0x93h O X X O X X O O Enabling the keyboard

0x94h O X X O X O X X Clearing keyboard input buffer

0x95h O X X O X O X O Reserved for keyboard

Mouse (only USB)

0x98h O X X O X X O X Resetting the mouse

X O

0x9Ah O X X O X O O X Detecting the presence of mouse

0x9Bh O X X O X O O O Enabling the mouse

Fixed Media

0xB0h O X O O X X X X Resetting fixed media device

0xB1h O X O O X X X O Disabling fixed media device

0xB2h O X O O X X O X

Detecting presence of a fixed media device (SATA hard drive detection, etc.)

0xB3h O X O O X X O O Enabling/configuring a fixed media device

Removable Media

0xB8h O X O O O X X X Resetting removable media device

0xB9h O X O O O X X O Disabling removable media device

0xBAh O X O O O X O X

Detecting presence of a removable media device (SATA CDROM detection, etc.)

0xBCh O X O O O O X X Enabling/configuring a removable media device

Boot Device Selection (BDS)

0xD0 O O X O X X X X Entered the Boot Device Selection phase (BDS)

0xD1

0xD2

O O X O X X X O Return to last good boot device

O O X O X X O X Setup boot device selection policy

0xD3

0xD4

0xD5

0xD6

O O X O X X O O Connect boot device controller

O O X O X O X X Attempt flash update boot mode

O O X O X O X O Transfer control to EFI boot

O O X O X O O X Trying to boot device selection

0xDF O O X O O O O O Reserved for boot device selection

Pre-EFI Initialization (PEI) Core

0xE0h O O O X X X X X Entered Pre-EFI Initialization phase (PEI)

0xE1h O O O X X X X O Started dispatching early initialization modules (PEIM)

0xE2h O O O X X X O X Initial memory found, configured, and installed correctly

0xE3h O O O X X X O O Transfer control to the DXE Core

Driver eXecution Environment (DXE) Core

0xE4h O O O X X O X X Entered EFI driver execution phase (DXE)

0xE5h O O O X X O X O Started dispatching drivers

Revision 2.4


121

Appendix C: POST Code Diagnostic LED Decoder Intel® Server Board S3420GP TPS

Checkpoint

LED

MSB


O = On, X=Off

Upper Nibble Lower Nibble

LSB

8h 4h 2h 1h 8h 4h 2h 1h

#7 #6 #5 #4 #3 #2 #1 #0

0xE6h O O O X X O O X Started connecting drivers

DXE Drivers

0xE7h O O O X O O X O Waiting for user input

0xE8h O O O X O X X X Checking password

0xE9h O O O X O X X O Entering BIOS setup

0xEAh O O O X O O X X Flash Update

Description

0xEEh O O O X O O X X Calling Int 19. One beep unless silent boot is enabled.

0xEFh O O O X O O X O Unrecoverable boot failure

Pre-EFI Initialization Module (PEIM)/Recovery

0x30h X X O O X X X X Crisis recovery has been initiated because of a user request

0x31h X X O O X X X O Crisis recovery has been initiated by software (corrupt flash)

0x34h X X O O X O X X Loading crisis recovery capsule

0x35h X X O O X O X O Handing off control to the crisis recovery capsule

0x3Fh X X O O O O O O Crisis recovery capsule failed integrity check of capsule descriptors

Runtime Phase/EFI Operating System Boot

0XF2h O O O O X X O X Signal that the OS has switched to virtual memory mode

0XF4h O O O O X O X X Entering the sleep state

0XF5h O O O O X O X O Exiting the sleep state

0XF8h O O O O O X X X

Operating system has requested EFI to close boot services has been cancelled.

Progress Code

0XF9h O X X O X X X X Resetting the keyboard

0xFAh O X X O X X X O Disabling the keyboard

122


Intel® Server Board S3420GP TPS Appendix D: POST Code Errors

0146

0192

0194

0195

0197

0198

019F

5220

5221

5224

8110

8111

Error Code

0012

0048

0108

0109

0113

0140

Appendix D: POST Code Errors

Whenever possible, the BIOS outputs the current boot progress codes on the video screen.

Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class, subclass, and operation information. The class and subclass fields point to the type of hardware that is being initialized. The operation field represents the specific initialization activity. Based on the data bit availability to display progress codes, a progress code can be customized to fit the data width. The higher the data bit, the higher the granularity of information that can be sent on the progress port. The progress codes may be reported by the system BIOS or option ROMs.

The Response section in the following table is divided into three types:







No Pause: The message displays on the screen during POST or in the Error Manager.

The system continues booting with a degraded state. The user may want to replace the erroneous unit. The setup POST error Pause setting does not have any effect with this error.

Pause: The message displays on the Error Manager screen, and an error is logged to the SEL. The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error, where the user can take immediate corrective action or choose to continue booting.

Halt: The message displays on the Error Manager screen, an error is logged to the SEL, and the system cannot boot unless the error is resolved. The user must replace the faulty part and restart the system. The setup POST error Pause setting does not have any effect with this error.

Table 76. POST Error Messages and Handling

Error Message

CMOS date/time not set

Password check failed

Keyboard component encountered a locked error.

Keyboard component encountered a stuck key error.

Fixed Media The SAS RAID firmware cannot run properly. The user should attempt to reflash the firmware.

PCI component encountered a PERR error.

Pause

Halt

No Pause

No Pause

Pause

Response

PCI out of resources error

L3 cache size mismatch

CPUID, processor family are different

Front side bus mismatch

Processor speeds mismatched

Processor family is unsupported.

Processor and chipset stepping configuration is unsupported.

CMOS/NVRAM Configuration Cleared

Passwords cleared by jumper

Password clear Jumper is Set.

Processor 01 internal error (IERR) on last boot

Processor 02 internal error (IERR) on last boot

Pause

Pause

Pause

Halt

Halt

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Revision 2.4


123

Appendix D: POST Code Errors Intel® Server Board S3420GP TPS

8160

8161

8170

8171

8180

8181

8190

8198

8300

84F2

84F3

84F4

84FF

8500

8520

8521

Error Code

8120

8121

8130

8131

8140

8141

8522

8523

8524

8525

8526

8527

8528

8529

852A

852B

852C

852D

852E

852F

8540

8541

8542

Error Message

Processor 01 thermal trip error on last boot

Processor 02 thermal trip error on last boot

Processor 01 disabled

Processor 02 disabled

Processor 01 Failed FRB-3 Timer.

Processor 02 Failed FRB-3 Timer.

Processor 01 unable to apply BIOS update

Processor 02 unable to apply BIOS update

Processor 01 failed Self Test (BIST).

Processor 02 failed Self Test (BIST).

Processor 01 BIOS does not support the current stepping for processor

Processor 02 BIOS does not support the current stepping for processor

Watchdog timer failed on last boot

Operating system boot watchdog timer expired on last boot

Integrated Baseboard Management Controller failed self-test

Integrated Baseboard Management Controller failed to respond

Integrated Baseboard Management Controller in update mode

Sensor data record empty

System event log full

Memory component could not be configured in the selected RAS mode.

DIMM_A1 failed Self Test (BIST).




DIMM_B1 failed Self Test (BIST).




DIMM_C1 failed Self Test (BIST).




DIMM_D1 failed Self Test (BIST).




DIMM_A1 Disabled.

DIMM_A2 Disabled.

DIMM_A3 Disabled.

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

No Pause

No Pause

Pause

Pause

Pause

Pause

No Pause

No Pause

Response

Pause

Pause

Pause

Pause

Pause

Pause

No Pause

Pause

Pause

Pause

124



Error Code Error Message

85A1

85A2

85A3

85A4

85A5

85A6

85A7

85A8

85A9

8581

8582

8583

8584

8585

8586

8587

8588

8589

858A

858B

858C

858D

858E

858F

85A0

8567

8568

8569

856A

856B

856C

856D

856E

856F

8580

8560

8561

8562

8563

8564

8565

8566

DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error.




DIMM_B1 Component encountered a Serial Presence Detection (SPD) fail error.




DIMM_C1 Component encountered a Serial Presence Detection (SPD) fail error.




DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error.




DIMM_A1 Correctable ECC error encountered.




DIMM_B1 Correctable ECC error encountered.




DIMM_C1 Correctable ECC error encountered.




DIMM_D1 Correctable ECC error encountered.




DIMM_A1 Uncorrectable ECC error encountered.




DIMM_B1 Uncorrectable ECC error encountered.




DIMM_C1 Uncorrectable ECC error encountered.


Revision 2.4


Appendix D: POST Code Errors

Response

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause after 10 occurrences

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause

Pause
















Pause

125

Appendix D: POST Code Errors Intel® Server Board S3420GP TPS

96E7

0xA022

0xA027

0xA028

0xA421

0xA500

0xA501

0xA5A0

0xA5A1

92A9

92C6

92C7

92C8

94C6

94C9

9506

95A6

95A7

95A8

9609

9641

9667

9687

96A7

96AB

9226

9243

9246

9266

9268

9269

8601

8602

8603

8604

9000

9223

9286

9287

9288

92A3

Error Code

85AA

85AB

85AC

85AD

85AE

85AF

Error Message



DIMM_D1 Uncorrectable ECC error encountered.




Override jumper is set to force boot from lower alternate BIOS bank of flash ROM

WatchDog timer expired (secondary BIOS may be bad!)

Secondary BIOS checksum fail

Chipset Reclaim of non critical variables complete.

Unspecified processor component has encountered a non specific error.

Keyboard component was not detected.

Keyboard component encountered a controller error.

Mouse component was not detected.

Mouse component encountered a controller error.

Local Console component encountered a controller error.

Local Console component encountered an output error.

Local Console component encountered a resource conflict error.

Remote Console component encountered a controller error.

Remote Console component encountered an input error.

Remote Console component encountered an output error.

Serial port component was not detected

Serial port component encountered a resource conflict error

Serial Port controller error

Serial Port component encountered an input error.

Serial Port component encountered an output error.

LPC component encountered a controller error.

LPC component encountered a resource conflict error.

ATA/ATPI component encountered a controller error.

PCI component encountered a controller error.

PCI component encountered a read error.

PCI component encountered a write error.

Unspecified software component encountered a start error.

PEI Core component encountered a load error.

PEI module component encountered an illegal software state error.

DXE core component encountered an illegal software state error.

DXE boot services driver component encountered an illegal software state error.

DXE boot services driver component encountered invalid configuration.

SMM driver component encountered an illegal software state error.

Processor component encountered a mismatch error.

Processor component encountered a low voltage error.

Processor component encountered a high voltage error.

PCI component encountered a SERR error.

ATA/ATPI ATA bus SMART not supported.

ATA/ATPI ATA SMART is disabled.

PCI Express* component encountered a PERR error.

PCI Express* component encountered a SERR error.

126


Pause

No Pause

No Pause

No Pause

No Pause

Pause

No Pause

No Pause

No Pause

No Pause

No Pause

No Pause

Halt

Halt

Halt

No Pause

Halt

Pause

No Pause

No Pause

Halt

No Pause

No Pause

No Pause

Halt

Pause

Pause

Pause

Pause

Pause

Pause

No Pause

No Pause

No Pause

No Pause

Pause

No Pause

Response

No Pause

No Pause

No Pause

No Pause

No Pause

No Pause

No Pause

No Pause

No Pause

Pause

Intel® Server Board S3420GP TPS Appendix D: POST Code Errors

Error Code

0xA5A4

0xA6A0

Error Message

PCI Express* IBIST error. Pause

DXE boot services driver Not enough memory available to shadow a legacy option ROM. No Pause

Response

POST Error Beep Codes

The following table lists POST error beep codes. Prior to system video initialization, the BIOS uses these beep codes to inform users on error conditions. The beep code is followed by a user-visible code on POST Progress LEDs.

Table 77. POST Error Beep Codes

3

Beeps Error Message

Memory error

POST Progress Code

Multiple

Description

System halted because a fatal error related to the memory was detected.

Revision 2.4


127

Appendix E: Supported Intel® Server Chassis Intel® Server Board S3420GP TPS

Appendix E: Supported Intel® Server Chassis

The Intel

®

Server Board S3420GP is supported in the following Intel server chassis. Please refer to the latest Configuration Guide for detailed information at http://www.intel.com/support/motherboards/server/s3420gp/sb/CS-030741.htm

.











Intel

®

Server Chassis SR1630

Intel

®

Server Chassis SC5650UP

Intel

®

Server Chassis SC5299UP

Intel

®

Server Chassis SC5299BRP

Intel

®

Server Chassis SC5299DP

128


Intel® Server Board S3420GP TPS Glossary

APIC

ARP

ASIC

ASMI

BIOS

BIST

Bridge

Glossary

This appendix contains important terms used in this document. For ease of use, numeric entries are listed first (for example, “82460GX”) followed by alpha entries (for example, “AGP 4x”).

Acronyms are followed by non-acronyms.

Term

ACPI Advanced Configuration and Power Interface

Definition

Advanced Programmable Interrupt Control

Address Resolution Protocol

Application Specific Integrated Circuit

Advanced Server Management Interface

Basic Input/Output System

Built-In Self Test

Circuitry connecting one computer bus to another, allowing an agent on one to access the other

CBC

CEK

CHAP

DHCP

Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they bridge the IPMB buses of multiple chassis.

Common Enabling Kit

Challenge Handshake Authentication Protocol

In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes of memory, which normally resides on the server board.

Dynamic Host Configuration Protocol

EMP

EPS

ESB2

F MB

Emergency Management Port

External Product Specification

Enterprise South Bridge 2

Flexible Mother Board

FRU

FSB

Field Replaceable Unit

Front Side Bus

GPA Guest Physical Address

GPIO General I/O

HPA Host Physical Address

Hz

I

2

Hertz (1 cycle/second)

IA Intel

®

Architecture

Revision 2.4


129

Glossary

Term

ICH I/O Hub

ICMB Intelligent Chassis Management Bus

IFB

ILM

I/O and Firmware Bridge

Independent Loading Mechanism

IMC Integrated Memory Controller

INTR Interrupt

I/OAT I/O Acceleration Technology

IPMB

IPMI

Intelligent Platform Management Bus

Intelligent Platform Management Interface

IR Infrared

KCS

KVM

LAN

LCD

LDAP

LED

LPC

LUN

Keyboard Controller Style

Keyboard, Video, Mouse

Local Area Network

Liquid Crystal Display

Local Directory Authentication Protocol

Light Emitting Diode

Low Pin Count

Logical Unit Number

Definition

MD2

MD5

Message Digest 2 – Hashing Algorithm

Message Digest 5 – Hashing Algorithm – Higher Security

MMU Memory Management Unit ms Milliseconds

MTTR Memory Type Range Register

Mux Multiplexor

NIC Network Interface Controller


Ohm Unit of electrical resistance

PECI

PEF

PEP

PIA

PLD

PMI

POST

PSMI

Platform Environment Control Interface

Platform Event Filtering

Platform Event Paging

Platform Information Area (This feature configures the firmware for the platform hardware)

Programmable Logic Device

Platform Management Interrupt

Power-On Self Test

Power Supply Management Interface

130



Term Definition

RAM

RASUM

RISC

Random Access Memory

Reliability, Availability, Serviceability, Usability, and Manageability

Reduced Instruction Set Computing

SSE2

SSE3

SSE4

TBD

TDP

TIM

UDP

UHCI

URS

ROM

RTC

SDR

SECC

Read Only Memory

Real-Time Clock (Component of ICH peripheral chip on the server board)

Sensor Data Record

Single Edge Connector Cartridge

SEEPROM Serial Electrically Erasable Programmable Read-Only Memory

SEL System Event Log

SMBUS

SMI

SMS

SNMP

System Management BUS

Server Management Interrupt (SMI is the highest priority non-maskable interrupt)

Server Management Software

Simple Network Management Protocol

Streaming SIMD Extensions 2



To Be Determined

Thermal Design Power

Thermal Interface Material

User Datagram Protocol

Universal Host Controller Interface

Unified Retention System

VRD Voltage Regulator Down

WS-MAN Web Services for Management

Glossary

Revision 2.4


131

Reference Documents Intel® Server Board S3420GP TPS

Reference Documents

Refer to the following documents for additional information:





Intel

®

Server Board S3420GP BIOS External Product Specification

Intel

®

Server Board S3420GP Common Core Integrated BMC External Product

Specification

132


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