CXA1352AS
2-channel 5 Elements Graphic Equalizer IC
Description
The CXA1352AS is a bipolar IC for graphic
equalizer use. All controls are DC performed while
the addition of single-potentiometers easily
composes a 2-channel graphic equalizer.
22 pin SDIP (Plastic)
Features
• Microcomputer control possible
• Built-in electronic volume
• Built-in pseudo loudness function
• Built-in balance function
• Each channel corresponds to 5 elements
• 2 channels of FIX OUT and LINE OUT pins
Absolute Maximum Ratings (Ta=25 °C)
• Supply voltage
VCC
12
V
• Storage temperature
Tstg –65 to +150 °C
• Allowable power dissipation
PD
1200
mW
Applications
Graphic equalizer for cassette tape recorder with
radio, mobile stereo and portable stereo
Operating Conditions
• Supply voltage
Structure
Bipolar silicon monolithic IC
VCC
DVCC
Topr
• Operating temperature
4.0 to 10.0
3.5 to VCC
–20 to +75
V
V
°C
1kHz
4kHz
10kHz
DVCC
DC2
IN2
VCC
LINE
OUT2
OUT2
(FIX)
OUT2
(VARIABLE)
VG
Block Diagram and Pin Configuration
22
21
20
19
18
17
16
15
14
13
12
14dB
29dB
VOLUME
GRAPHIC EQUALIZER
CONTROL
BIAS
GRAPHIC EQUALIZER
29dB
14dB
BAL
VOL
DC1
7
8
9
10
11
ISET
100Hz
6
OUT1
(VARIABLE)
5
OUT1
(Fix)
4
LINE
OUT1
3
GND
2
1N1
1
400Hz
VOLUME
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
—1—
E91912B95-TE
CXA1352AS
Pin Description
Pin
No.
1
2
20
21
22
Symbol Voltage
400 Hz
100 Hz
10 kHz
4 kHz
1 kHz
I/O
resistance
Equivalent circuit
Description
DVCC
VCC
Graphic equalizer control
pin
1
2
DVCC
2
60 kΩ
10k
147 40k
DC input
4
20
20k
21
4
22
VOL
GND
DVCC
Volume control pin
DC input
VCC
9k
3
BAL
DVCC
2
147 40k
Balance control pin
DC input
3
60 kΩ
20k
GND
VCC
Connects the DC
feedback capacitor of the
LPF used in the 100 Hz
graphic equalizer
30k
5
18
DC1
DC2
VCC
2
147
—
5
18
GND
VCC
6
17
IN1
IN2
VCC
2
25 kΩ
147
Signal input pin
6
17
50k
5k
50k
1k
GND
7
GND
GND
7
—2—
GND pin
CXA1352AS
Pin
No.
Symbol Voltage
I/O
resistance
Equivalent circuit
Description
VCC
8
15
L OUT1
L OUT2
VCC
2
147
0
300
27k
8
Line output pin
300
15
GND
VCC
9
14
F OUT1
F OUT2
VCC
2
147
0
300
30k
9
Fix output pin
14
300
GND
VCC
10
13
OUT1
OUT2
VCC
2
147
0
250
Electronic volume output
pin
20k
10
250
13
GND
VCC
147
11
ISET
1.3 V
0
Reference current setting
pin
(for graphic equalizer)
Normally 160 kΩ resistor
is connected
300
11
GND
—3—
CXA1352AS
Pin
No.
Symbol Voltage
I/O
resistance
Equivalent circuit
Description
VCC
40k
12
VG
VCC
2
147
20 kΩ
300
12
300
40k
Signal reference voltage
pin
A capacitor is connected
for ripple rejection
GND
16
VCC
16
VCC
Power supply pin
(operation)
VCC
DVCC
19
VCC
19
DVCC
DVCC
60 kΩ
30k
Power supply pin (control)
30k
42k
GND
—4—
CXA1352AS
Electrical Characteristics
No.
1
2
Item
Supply voltage
(operation)
Supply voltage
(control)
(Ta=25 °C, VCC=8 V, DVCC=5 V)
Min.
Typ.
Max.
Unit
VCC
4.0
—
10.0
V
DVCC
3.5
—
VCC
V
8.0
12.0
16.0
mA
—
–34.0
—
dBm
3
Current consumption
ICC
4
Reference input level
VIN
5
Reference output level
6
Reference LINE
output level
Reference FIX
output level
Graphic equalizer
setting frequency (1)
Graphic equalizer
setting frequency (2)
Graphic equalizer
setting frequency (3)
Graphic equalizer
setting frequency (4)
Graphic equalizer
setting frequency (5)
Graphic equalizer
frequency deviation
7
8
9
10
11
12
13
Test conditions
Symbol
Graphic equalizer ALL FLAT,
Volume MID
VOUT
Graphic equalizer ALL FLAT,
Volume MAX, f=1 kHz
–23.0 –20.0 –17.0
dBm
VLINE
f=1 kHz
–6.5
–2.5
dBm
VFIX
Graphic equalizer ALL FLAT,
f=1 kHz
–23.0 –20.0 –17.0
dBm
GEQ1
LPF cut off frequency (–3 dB)
—
200
—
Hz
GEQ2
BPF (1) central frequency
—
400
—
Hz
GEQ3
BPF (2) central frequency
—
1.0
—
kHz
GEQ4
BPF (3) central frequency
—
4.0
—
kHz
GEQ5
HPF cut off frequency (–3 dB)
—
8.0
—
kHz
∆ EQ
14
Maximum boost (1)
GEQB1
15
Maximum boost (2)
GEQB2
16
Maximum cut (1)
GEQC1
17
Maximum cut (2)
GEQC2
18
Total harmonic
distortion
THD
19
Volume attenuation (1)
VOL1
20
Volume attenuation (2)
VOL2
21
Balance adjustment (1)
BAL1
22
Balance adjustment (2)
BAL2
23
Noise level
VNOIS
24
Output offset voltage
VOFF
–4.5
Cut off frequency and central
–20
0
20
frequency deviation
f=400 Hz, 1 kHz, 4 kHz
9.0
11.2 14.0
maximum boost
f=100 Hz, 10 kHz maximum boost
8.0
10.7 14.0
f=400 Hz, 1 kHz, 4kHz
–13.0 –10.7 –8.5
maximum cut
f=100 Hz, 10 kHz maximum cut
–12.0 –9.5 –7.0
RL=2 kΩ, Graphic equalizer
ALL FLAT, Volume MAX, f=1 kHz,
—
0.25
1.0
Reference +10 dB is input
Graphic equalizer ALL FLAT,
–1.5
0
1.5
Volume MAX, f=1 kHz
Graphic equalizer ALL FLAT,
—
–94.4 –80.0
Volume MIN, f=1 kHz
Graphic equalizer ALL FLAT,
—
0
—
BAL=MAX,Volume MAX, f=1kHz
Graphic equalizer ALL FLAT,
—
–66
—
BAL=MIN, Volume MAX, f=1kHz
Rg=5 kΩ, Graphic equalizer ALL
—
–93.1 –88.0
FLAT, Volume MAX, “A” WTG filter
Graphic equalizer ALL FLAT,
3.5
4.0
4.5
Volume MAX
—5—
%
dB
dB
dB
dB
%
dB
dB
dB
dB
dB
V
—6—
CUT
CUT
CUT
CUT
MAX
R8
620
∗
C1
1000p
∗
C3
1000p
2
1
18
19
20
∗
C6
1000p
21
∗
C4
1000p
∗
C8
100µ/
25V
22
∗
C2
1000p
AUDIO
SG
MIN
R1
50k
CH1
R2
50k
BOOST
R3
50k
BOOST
R4
50k
R5
50k
BOOST
R6
50k
BOOST
CH2
CUT
R7
50k
BOOST
4
∗
∗
C5
C7
1000p 1000p
3
5
S1
R9
39k
6
R19
20k
R15 R17 R18
20k 160k 20k
∗±5%
±1%
2. CAPACITOR TOLERANCE ∗±5%
±2%
COUPLING CAPACITPR
±10%
R13
20k
11
C18
4.7µ/25V
10
C16
4.7µ/25V
9
C14
4.7µ/25V
8
1. RESISTOR TOLERANCE
NOTE
R11
5.1k
C11
4.7µ/
25V
7
14
∗
C20
R16 47µ/
20k 25V
C19
4.7µ/25V
13
12
R14
20k
C17
4.7µ/25V
15
C15
4.7µ/25V
∗
C13
100µ/
A 25V
R12
5.1k
C12
4.7µ/
25V
17
16
CXA1352AS
∗
C10
4.7µ/
25V
R10
39k
S2
POWER
SUPPLY
GND
∗
C9
4.7µ/
25V
POWER
SUPPLY
1kHz
BAL
4kHz
VOL
10kHz
DC1
DVCC
400Hz
VCC
GND
L OUT2
L OUT1
F OUT2
F OUT1
DC2
100Hz
OUT2
OUT1
IN2
IN1
VG
ISET
Electrical Characteristics Test Circuit
S8
S5
S6
S7
S3
R21
2k
R20
2k
S4
S10
S9
S11
OSCILLO
–SCOPE
DISTORTION
ANALYZER
AC
VOLTMETER
NOISE FILTER
“A” WTG
DIN AUDIO
1kHz BPF
OUT
IN
S17 FILTER
S13
S12
S15
S14
S16
DC
VOLTMETER
S18
S19
S20
CXA1352AS
GND
R7
50k
R1
50k
R2
50k
R3
50k
R4
50k
R5
50k
C1
2.2µ
C2
2.2µ
C3
2.2µ
C4
2.2µ
C5
2.2µ
C6
2.2µ
GND
3
4
R8
5.1k
GND GND
5
C11
4.7µ
7
GND
Signal input
6
9
10
C18
2.2µ
11
R10
160k
C20
4.7µ
GND
To power amplifier
For spectrum analyzer display or
recording through graphic equalizer
To line amplifier
8
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
2
1
CXA1352AS
12
13
14
15
16
17
18
C16
2.2µ
C19
2.2µ
19
C17
2.2µ
20
C14
2.2µ
C15
2.2µ
21
C12
4.7µ
C13
220µ
22
C9
4.7µ
C10
4.7µ
R9
5.1k
GND
1kHz
C8
220µ
GND
To power amplifier
4kHz
VOL
C7
2.2µ
GND
VCC
GND
Signal input
10kHz
DC1
R6
50k
DVCC
GND
For spectrum analyzer display or
recording through graphic equalizer
To line amplifier
DVCC
GND
DVCC
DC2
400Hz
IN2
IN1
—7—
100Hz
VCC
BAL
L OUT2
L OUT1
F OUT2
F OUT1
OUT2
OUT1
VG
ISET
Application Circuit
CXA1352AS
CXA1352AS
Description of Operation
1. Graphic equalizer
• Conventional system
OPERATIONAL AMPLIFIER
R1
VI
VO
RV
R2
CUT
BOOST
L
R0=R1=R2
Z (s)
C
R
Fig. 1.
Fig. 1. indicates the conventional graphic equalizer system. This circuit performs boost and cut near “fO”
controlled by the variable volume RV. (“fO” is resonance frequency determined by Z (s) (formed LCR).) The
operation can be seen as follows : When the LCR circuit goes to the far left of RV, a state of graphic
equalizer becomes maximum cut. At that time, assuming transmittance as T (s), we have
T (s) =
Z (s)
Z (s)+ RO
Here as
Then
Z (s) = sL+R+
T (s) =
1
sC
LCs2+RCs+1
LCs2 + (R+Ro) Cs+1
Defining fo as fO =
ωo
1
ωoL
, ωo as ωo =
, and Q as Q =
,
2π
LC
R
we can obtain the frequency
characteristics at cut.
Also, when LCR circuit goes to the far right of RV, a state of graphic equalizer becomes maximum boost.
At that time transmittance is :
T (s) =
Z (s) +RO
=
Z (s)
LCs2+ (R+Ro) Cs+1
LCs2+RCs+1
Defining fo, ωo and Q as for cut, we can obtain the frequency characteristics at boost.
—8—
CXA1352AS
Fig. 2. Indicates frequency characteristics at boost and cut.
Response (dB)
Boost
FIat
0dB
fO=
1
2π LC
Cut
Frequency (Hz)
fO
Fig. 2.
• CXA1352AS system
Operational amplifier
R
VI
VO
H(s)=
ωo s
Q
ωo
2
s +
s+ωo2
Q
R
Z(s)
Z(s)
H(s)
Ic
Ib
Gm1
Gm2
Fig. 3.
The structure of the graphic equalizer used in this IC is shown on Fig. 3. This circuit performs boost and
cut controlled by 2 transconductance amplifiers that can vary the conversion coefficient through control
currents Ib, and Ic around ωo. (“ωo” is central frequency determined by Band Pass Filter.) Considering
output impedance Z (s) of Gm1, Gm2 we have
Z (s) =
1
H(s) • Gm1
—9—
CXA1352AS
Here, using ωo and Q we can express BPF transmittance H (s) as
ωo
•s
Q
ωo
s2 +
s + ωo2
Q
H (s) =
Z (s) =
Q
1
ωo • Q
s+
+
ωo • Gm1
Gm1
Gm1 • s
This formula shows that this system and the aforementioned LCR circuit have equivalent impedance
characteristics on Z (s).
Then, regarding Gm as the maximum value of Gm1 and Gm2, the operation can be observed as follows.
Maximum cut occurs when Gm1=Gm and Gm2=0. At that time we have transmittance T (s) as
ωo
s2 +
• s + ωo2
Z (s)
Q
T (s) =
=
(1+R • Gm) • ωo2
Z (s) +R
• s+ ωo2
s2 +
Q
This is equal to the frequency characteristics of the conventional graphic equalizer at cut.
Also, maximum boost occurs when Gm1=0 and Gm2=Gm. At that time we have transmittance T (s) as
(1+R • Gm) • ωo2
s2 +
• s+ ωo2
Q
Z (s) +R
T (s) =
=
ωo
Z (s)
s2 +
• s + ωo2
Q
This is equal to the frequency characteristics of the conventional graphic equalizer at boost.
We can then deduce that, as far as the operation is concerned the graphic equalizer on this IC and the
conventional graphic equalizer are equal, even when the system differs. The merit in using this IC’s system
rests with the fact that monolithic filter technology realizes a graphic equalizer without external parts.
The structure of the actual graphic equalizer, including BPF, is shown on Fig. 4.
SUM
VI
1
VO
R1
30k
C3
VI
C2
R2
30k
1
Gm1
Gm2
Gm3
C1
Gm4
I CUT
GND
GND
I BOOST
GND
GND
Fig. 4
—10—
GND
CXA1352AS
2. Control through microcomputer possible
Volume, balance and the 100 Hz, 400 Hz, 1 kHz, 4 kHz, 10 kHz boost, cut control respectively are all
executed through DC voltage.
Also, the control voltage range is determined through DVCC (control power supply, independent from VCC)
and is from 0 V to DVCC. Accordingly, the control range can be varied at will, by changing DVCC voltage.
By setting DVCC 5 V, control through the microcomputer becomes possible.
Setting to DVCC=VCC enables usage with single power supply.
3. Pseudo loudness
A loudness function interlocking with volume (VOL) is featured.
With this IC, to provide a loudness effect, the 100 Hz and 10 kHz graphic equalizer part does not use a
BPF but is composed of a low pass filter (LPF) and a high pass filter (HPF) respectively.
The operation is explained as follows. As VOL drops below the center, the 100 Hz and 10 kHz graphic
equalizer part Ib (See Fig. 3.) gradually increases even if the graphic equalizer control pin (100 Hz and 10
kHz) is flat, boost applies and as a result loudness effect is obtained.
—11—
CXA1352AS
Notes on Operation
1. Power supply
DVCC can be used independently from VCC but supply voltage should be
VCC≥DVCC, without fall.
2. Pseudo loudness
As mentioned in the paragraph on Description of Operation, as it is interlocked with VOL, loudness can not
be put OFF.
3. Output pin
This IC features 2 channels for each of OUT pin, LINE OUT pin and FIX OUT pin.
Usage of the respective output pins is indicated as follows.
• OUT pin
Normally used as the graphic equalizer output.
• LINE OUT pin
A sound from a source that has not passed through the graphic equalizer is only amplified and output
from this pin.
• FIX OUT pin
This pin is useful for REC or spectrum analyzer display after the sound formation at the graphic
equalizer.
The relation between the input and the respective outputs is shown on Fig. 5.
IN AMP
–34dBm
IN
14dB
GRAPHIC EQUALIZER
GEBPF+GEHPF+
GELPF+SUM AMP
F OUT
–20dBm
VOLUME
LINE AMP
29dB
OUT
–20dBm
(VARIABLE)
L OUT
–5dBm
Fig. 5.
4. Reference resistor
To check the central frequency deviation of the graphic equalizer, the control current that determines the
filter time constant is determined by means of an external, not an internal, resistor.
This is the 160 kΩ external resistor connected to ISET pin (Pin 11). Accordingly, for the resistor to be
connected to ISET pin, it is recommended to use a resistor with excellent dispersion and temperature
characteristics.
Also, by varying the value of the resistor connected to ISET pin, the frequency characteristics of the
graphic equalizer can be shifted. By reducing the resistor value the shift moves to the high band and by
increasing the value the shift moves to the low band.
However, 5 elements cannot be shifted independently.
—12—
CXA1352AS
Example of Representative Characteristics
Frequency characterlstlcs
15
VCC=8V
DVCC=5V
0dB=–20dBm, 1kHz
VOL : MAX
ALL BOOST
10
RESPONSE(dB)
ALL FLAT
BOOST
5
0
–5
CUT
–10
ALL CUT
–15
50
100
200
500
1k
2k
5k
10k
20k
FREQUENCY(Hz)
Loudness characteristics
8
VOL=0.0V
BOOST(dB)
1.0V
1.5V
4
2.0V
2.5V
0
VCC=8V
DVCC=5V
0dB=at 1kHz
ALL FLAT
–4
50
100
5.0V
200
500
1k
2k
FREQUENCY(Hz)
—13—
5k
10k
20k
CXA1352AS
THD-OUT characteristics (ALL FLAT)
THD-OUT characteristics (ALL BOOST)
VCC=8V, DVCC=5V
0dB=–20dBm‚ VOL : MAX
10.0
10.0
5.0
5.0
2.0
2.0
THD+N (%)
THD+N (%)
VCC=8V, DVCC=5V
0dB=–20dBm, VOL : MAX
1.0
0.5
0.2
100Hz
1.0
0.5
1kHz
0.2
1kHz
0.1
100Hz
0.1
10kHz
10kHz
0.05
0
10
0.05
20
0
OUT pin output level (dB)
THD-F OUT characteristics (ALL FLAT)
VCC=8V, DVCC=5V
0dB=–20dBm, VOL : MAX
10.0
10.0
5.0
5.0
2.0
2.0
THD+N (%)
THD+N (%)
VCC=8V, DVCC=5V
0dB=–20dBm, VOL : MAX
1kHz
10kHz
0.5
20
OUT pin output level (dB)
THD-OUT characteristics (ALL CUT)
1.0
10
100Hz
1.0
0.5
10kHz
0.2
0.2
0.1
0.1
0.05
0.05
1kHz
100Hz
0
10
20
0
OUT pin output level (dB)
10
20
FIX OUT pin output level (dB)
—14—
30
CXA1352AS
THD-F OUT characteristics (ALL BOOST)
THD-F OUT characteristics (ALL CUT)
VCC=8V, DVCC=5V
0dB=–20dBm, VOL : MAX
VCC=8V, DVCC=5V
0dB=–20dBm, VOL : MAX
5.0
5.0
2.0
2.0
THD+N (%)
10.0
THD+N (%)
10.0
1.0
0.5
0.2
0.1
10kHz
0.5
100Hz
0.2
10kHz
1kHz
1kHz
1.0
100Hz
0.1
0.05
0.05
0
10
20
30
0
FIX OUT pin output level (dB)
10
20
FIX OUT pin output level (dB)
THD-L OUT characteristics
Output voltage vs. Control voltage (VOL)
VCC=8V, DVCC=5V
0dB=–6dBm, VOL : MAX
0
10.0
OUT pin output level (dBm)
5.0
THD+N (%)
2.0
1.0
0.5
0.2
z
kH
10 Hz
0
10
0.1
0.05
–20
–40
VCC=8V
DVCC=5V
VIN=–14dBm,1kHz
ALL FLAT
–60
1kHz
–10
0
–80
10
0.1
LINE OUT pin output level (dB)
0.2
0.5
1
Control voltage (V)
—15—
2
5
CXA1352AS
Output voltage vs. Control voltage (VOL)
0
100
–20
80
OUT pin output level (%)
OUT pin output level (dBm)
Output voltage vs. Control voltage (VOL)
–40
–60
–80
60
40
VCC=8V
DVCC=5V
VIN=–14dBm, 1kHz
100%=0dBm
ALLFLAT
20
VCC=8V
DVCC=5V
VIN=–14dBm, 1kHz
ALL FLAT
–100
0
0
1.0
2.0
3.0
4.0
5.0
0
Control voltage (V)
1.0
2.0
3.0
Control voltage (V)
—16—
4.0
5.0
CXA1352AS
Unit : mm
+ 0.1
0.05
0.25 –
22PIN SDIP (PLASTIC)
+ 0.4
19.2 – 0.1
7.62
+ 0.3
6.4 – 0.1
12
22
0° to 15°
11
1
0.5 ± 0.1
+ 0.15
0.9 – 0.1
+ 0.4
3.9 – 0.1
0.51 MIN
1.778
+ 0.15
3.25 – 0.2
Package Outline
Two kinds of package surface:
1.All mat surface type.
2.All mirror surface type.
PACKAGE STRUCTURE
MOLDING COMPOUND
EPOXY RESIN
SONY CODE
SDIP-22P-01
LEAD TREATMENT
SOLDER PLATING
EIAJ CODE
SDIP022-P-0300
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.95g
JEDEC CODE
—17—
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