2nd Generation Intel Core Processor Family with Intel 6

2nd Generation Intel® Core™
Processor Family with
Intel® 6 Series Chipset
Development Kit
User Guide
March 2011
Document Number: 325208
About This Document
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED,
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The 2nd Generation Intel® Core™ Processor with Intel® 6 Series Chipset may contain design defects or errors known as errata which
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*Other names and brands may be claimed as the property of others.
Copyright © 2011, Intel Corporation. All Rights Reserved.
2nd Generation Intel® Core™ Processor with Intel® 6 Series Chipset Development Kit
User Guide
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March 2011
Document Number: 325208-001
About This Document
Contents
1
About This Document ................................................................................................... 7
1.1
1.2
1.3
1.4
1.5
2
Getting Started ........................................................................................................... 16
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
Content Overview ...................................................................................................7
Text Conventions ....................................................................................................7
Glossary of Terms and Acronyms .............................................................................9
Related Documents and Information ....................................................................... 14
Development Kit Technical Support ........................................................................ 15
1.5.1
Online Support .......................................................................................... 15
1.5.2
Additional Technical Support ....................................................................... 15
Development Kit Contents ..................................................................................... 16
Additional Required Hardware Not Included In This Kit ............................................. 16
Additional Required Software Not Included in this Kit................................................ 17
Workspace Preparation.......................................................................................... 18
System Setup ...................................................................................................... 18
System Power-Up ................................................................................................. 19
System Power-Down ............................................................................................. 19
System BIOS ....................................................................................................... 19
2.8.1
Configuring the BIOS ................................................................................. 20
2.8.2
Programming BIOS Using a Bootable USB Device.......................................... 20
Development Kit Features .......................................................................................... 22
3.1
3.2
Processor Support ................................................................................................ 24
3.1.1
Clock Requirements ................................................................................... 25
3.1.2
Processor Voltage Regulator ....................................................................... 25
3.1.2.1
SVID Supported in Intel® MVP-7 Voltage Regulator ....................... 25
3.1.3
Power Management and Key Signals............................................................ 25
3.1.4
Memory Support ....................................................................................... 26
3.1.5
Graphics Support ...................................................................................... 27
3.1.5.1
Internal Graphics Support ........................................................... 27
3.1.5.2
External Graphics Support .......................................................... 28
3.1.5.3
Direct Media Interface (DMI)-2 Interface ...................................... 28
3.1.6
Intel® Flexible Display Interface (Intel® FDI) ................................................ 28
3.1.7
Processor Thermals ................................................................................... 29
3.1.8
Processor Active Cooling ............................................................................ 29
PCH Support ........................................................................................................ 29
3.2.1
Introduction to the Intel® 6 Series Chipset ................................................... 29
3.2.2
Key Power Management Signals .................................................................. 29
3.2.3
PCIe* Support .......................................................................................... 30
3.2.4
On-Board LAN ........................................................................................... 32
3.2.5
Soft Audio and Modem ............................................................................... 33
3.2.5.1
Realtek* Audio Card Support ...................................................... 33
3.2.6
SATA Storage ........................................................................................... 34
3.2.7
Displays ................................................................................................... 34
3.2.7.1
DP/HDMI Support ...................................................................... 36
3.2.7.2
DMC Support ............................................................................. 37
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3.2.7.3
Switchable Graphics ................................................................... 37
USB Connectors ........................................................................................ 38
3.2.8.1
USB2.0 ..................................................................................... 38
3.2.9
LPC Super I/O (SIO)/LPC Slot ..................................................................... 40
3.2.10 Serial Port, IrDA ........................................................................................ 40
3.2.11 System Management Controller (SMC)/Keyboard Controller (KBC).................. 40
3.2.12 SPI .......................................................................................................... 41
3.2.12.1 Multi-BIOS Support .................................................................... 41
3.2.12.2 Clocks ...................................................................................... 42
3.2.12.3 CPU_ITP Clock and XDP Clock ..................................................... 43
3.2.13 Real Time Clock ........................................................................................ 44
Debug Interfaces .................................................................................................. 45
3.3.1
Processor and PCH Debug .......................................................................... 45
Chassis ................................................................................................................ 45
Power Supply Solutions, Usage, and Recommendations ............................................ 45
3.5.1
Power Supply Solutions .............................................................................. 45
3.5.2
Power Supply Usage and Recommendation .................................................. 46
Power Management .............................................................................................. 47
3.6.1
Power Management States ......................................................................... 47
3.2.8
3.3
3.4
3.5
3.6
4
Development Board Summary .................................................................................... 48
4.1
4.2
4.3
4.4
4.5
5
Features .............................................................................................................. 48
Connectors .......................................................................................................... 51
4.2.1
Back Panel Connectors ............................................................................... 51
Configuration Settings ........................................................................................... 52
4.3.1
Configuration Jumpers/Switches ................................................................. 52
Power On and Reset Button ................................................................................... 53
LEDs ................................................................................................................... 54
Quick Start ................................................................................................................. 56
5.1
5.2
5.3
5.4
Required Peripherals ............................................................................................. 56
Instructions to Flash BIOS to SPI ........................................................................... 56
H8 Programming .................................................................................................. 56
Key Jumpers ........................................................................................................ 57
Figures
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
Figure
1. Development Board Block Diagram ........................................................ 22
2. Side View of Stacked SODIMM Slots ....................................................... 27
3. PCIe* Port Mapping – Schematic Snapshot ............................................. 31
4. On-Board LAN Block Diagram ................................................................ 33
5. Back Panel Connectors .......................................................................... 35
6. Display Ports On-Board ......................................................................... 36
7 Mini PCIe Connector Soldered In Place of DMC ......................................... 37
8. Switchable Graphics with eDP from PCH ................................................. 38
9. Clock (Integrated Mode) Block Diagram .................................................. 43
10. Block Diagram of GDXC and XDP Clock on the Development Board .......... 43
11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board 44
12. Development Board Components – Top View ......................................... 48
13. Development Board Components - Bottom View .................................... 50
14. Back Panel Connectors ........................................................................ 51
15. Jumpers for Programming SPI and H8 .................................................. 58
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About This Document
Tables
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
Table
1. Text Conventions ....................................................................................7
2. Terms ....................................................................................................9
3. Acronyms ............................................................................................. 11
4. Related Documents and Information ........................................................ 15
5. Development Board Feature Description .................................................. 22
6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration . 28
7. Other PEG Interface Straps .................................................................... 28
8. PCIe* Ports........................................................................................... 30
9. Reworks for Different Port Mappings ........................................................ 32
10. Selection of I/O Voltage for the Intel® High Definition Audio ..................... 33
11. SATA Ports.......................................................................................... 34
12. USB Port Mapping ................................................................................ 39
13. USB2.0 Ports....................................................................................... 40
14. Jumper Settings for SPI Programming.................................................... 41
15. Multi-BIOS Implementation .................................................................. 42
16. Development Board Power Management States ...................................... 47
17. Development Board Components List - Top View..................................... 49
18. Development Board Components List - Bottom View ............................... 50
19. Back Panel Connectors ......................................................................... 51
20. Configuration Jumper/Switches ............................................................. 52
21. Power On and Reset Button .................................................................. 54
22. Other Development Board Switches ....................................................... 54
23. Development Board LEDs ..................................................................... 54
24. H8 Programming Jumpers .................................................................... 57
25. Key Jumpers ....................................................................................... 58
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About This Document
Revision History
Document
Number
Revision
Number
325208
001
Description
Revision Date
Initial release.
March 2011
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User Guide
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About This Document
1
About This Document
This guide describes the use of the 2nd Generation Intel® Core™ Processor Family with
Intel® 6 Series Chipset Development Kit. The document has been written for OEMs,
system evaluators, and embedded system developers, and assumes basic familiarity
in the fundamental concepts involved with installing and configuring hardware for a
personal computer system. The document defines all jumpers, headers, LED functions,
their locations on the development kit, and other subsystem features and POST codes.
For the latest information about the 2nd Generation Intel® Core™ Processor Family
with Intel® 6 Series Chipset development board design collateral, please visit the
Intel® Embedded Design Center.
1.1
Content Overview
This manual is arranged into the following sections:
1.2
•
About This Document contains a description of conventions used in this document.
The last few sections explain how to obtain literature and contact customer
support.
•
Getting Started describes the contents of the development kit and explains the
basics steps necessary to get the board running. This section also includes
information on how to update the BIOS.
•
Development Kit Features describes details on the hardware features of the
development board. It explains the Power Management and Testability features.
•
Development Board Summary provides a list of major board components and
connectors. It gives a description of jumper settings and functions. The section
also explains the use of the programming headers.
•
Add-In Cards contains information on add-in cards available from Intel that can be
used with the development board.
Text Conventions
The notations listed in Table 1 may be used throughout this document.
Table 1. Text Conventions
Notation
Definition
#
The pound symbol (#) appended to a signal name indicates that the signal
is active low (e.g., PRSNT1#).
Variables
Variables are shown in italics. Variables must be replaced with correct
values.
Instructions
Instruction mnemonics are shown in uppercase. When you are
programming, instructions are not case-sensitive. You may use either
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Notation
Definition
uppercase or lowercase.
Numbers
Units of Measure
A
Gbyte
Gb
GT
Kbyte
KΩ
mA
Mbyte
MHz
ms
MT
mW
ns
pF
W
V
µA
µF
µs
µW
Signal Names
Hexadecimal numbers are represented by a string of hexadecimal digits
followed by the character H. A zero prefix is added to numbers that begin
with A through F. (For example, FF is shown as 0FFH.) Decimal and binary
numbers are represented by their customary notations (i.e., 255 is a
decimal number and 1111 is a binary number; in some cases, the letter B
is added for clarity).
The following abbreviations are used to represent units of measure:
amps, amperes
gigabytes
gigabits
giga transfers
kilobytes
kilo-ohms
milliamps, mill amperes
megabytes
megahertz
milliseconds
Mega Transfers
milliwatts
nanoseconds
picofarads
watts
volts
microamps, microamperes
microfarads
microseconds
microwatts
Signal names are shown in uppercase. When several signals share a
common name, an individual signal is represented by the signal name
followed by a number, while the group is represented by the signal name
followed by a variable (n). For example, the lower chip-select signals are
named CS0#, CS1#, CS2#, and so on; they are collectively called CSn#.
A pound symbol (#) appended to a signal name identifies an active-low
signal. Port pins are represented by the port abbreviation, a period, and
the pin number (e.g., P1.0).
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1.3
Glossary of Terms and Acronyms
Table 2 defines conventions and terminology used throughout this document.
Table 2. Terms
Term
Definition
Aggressor
A network that transmits a coupled signal to another network.
Anti-etch
Any plane-split, void or cutout in a VCC or GND plane.
Bus Agent
A component or group of components that, when combined, represent a
single load on the AGTL+ bus.
The reception on a victim network of a signal imposed by aggressor
network(s) through inductive and capacitive coupling between the
networks.
Backward Crosstalk - Coupling that creates a signal in a victim network
that travels in the opposite direction as the aggressor’s signal.
Crosstalk
Forward Crosstalk - Coupling that creates a signal in a victim network that
travels in the same direction as the aggressor’s signal.
Even Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch in the same direction that the victim is switching.
Odd Mode Crosstalk - Coupling from a signal or multiple aggressors when
all the aggressors switch to the direction opposite the victim’s switching.
Duck Bay 3
PCI Express* interposer card that provides Express-card support for the
development board
Flight time is a term in the timing equation that includes the signal
propagation delay, any effects the system has on the TCO (time from
clock-in to data-out) of the driver, plus any adjustments to the signal at
the receiver needed to ensure the setup time of the receiver. More
precisely, flight time is defined as:
Flight Time
The time difference between a signal at the input pin of a receiving agent
crossing the switching voltage (adjusted to meet the receiver
manufacturer’s conditions required for AC timing specifications; i.e.,
ringback, etc.) and the output pin of the driving agent crossing the
switching voltage when the driver is driving a test load used to specify the
driver’s AC timings.
Maximum and Minimum Flight Time - Flight time variations are caused by
many different parameters. The more obvious causes include variation of
the board dielectric constant, changes in load condition, crosstalk, power
noise, variation in termination resistance, and differences in I/O buffer
performance as a function of temperature, voltage, and manufacturing
process. Some less obvious causes include effects of Simultaneous
Switching Output (SSO) and packaging effects.
Maximum flight time is the largest acceptable flight time a network will
experience under all conditions.
Minimum flight time is the smallest acceptable flight time a network will
experience under all conditions.
Gen 2
PCI Express Generation 2
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Term
Definition
Infrared Data
Assoc.
The Infrared Data Association (IrDA) has outlined a specification for serial
communication between two devices via a bidirectional infrared data port.
The CRB has such a port and it is located on the rear of the platform
between the two USB connectors.
Intel® MVP 7.0
Inter-Symbol
Interference
Mott Canyon IV
The Intel® Mobile Voltage Positioning specification for the 2nd generation
Intel® Core™ Processor Family. It is a DC-DC converter module that
supplies the required voltage and current to a single processor.
Inter-symbol interference is the effect of a previous signal (or transition)
on the interconnect delay. For example, when a signal is transmitted
down a line and the reflections due to the transition have not completely
dissipated, the following data transition launched onto the bus is affected.
ISI is dependent upon frequency, time delay of the line, and the reflection
coefficient at the driver and receiver. ISI may impact both timing and
signal integrity.
This Add-in card enables Intel® High Definition Audio functionality.
Network
The network is the trace of a Printed Circuit Board (PCB) that completes
an electrical connection between two or more components.
Overshoot
The maximum voltage observed for a signal at the device pad, measured
with respect to VCC.
Pad
The electrical contact point of a semiconductor die to the package
substrate. A pad is only observable in simulations.
Pin
The contact point of a component package to the traces on a substrate,
such as the motherboard. Signal quality and timings may be measured at
the pin.
Power-Good
Ringback
RJ45
System Bus
Setup Window
Simultaneous
Switching Output
“Power-Good,” “PWRGOOD,” or “CPUPWRGOOD” (an active high signal)
indicates that all of the system power supplies and clocks are stable.
PWRGOOD should go active at a predetermined time after system
voltages are stable and should go inactive as soon as any of these
voltages fail their specifications.
The voltage to which a signal changes after reaching its maximum
absolute value. Ringback may be caused by reflections, driver oscillations,
or other transmission line phenomena.
A type of registered jack.
The System Bus is the microprocessor bus of the processor.
The time between the beginning of Setup to Clock (TSU_MIN) and the
arrival of a valid clock edge. This window may be different for each type of
bus agent in the system.
Simultaneous Switching Output (SSO) effects are differences in electrical
timing parameters and degradation in signal quality caused by multiple
signal outputs simultaneously switching voltage levels in the opposite
direction from a single signal or in the same direction. These are called
odd mode and even mode switching, respectively. This simultaneous
switching of multiple outputs creates higher current swings that may
cause additional propagation delay (“push-out”) or a decrease in
propagation delay (“pull-in”). These SSO effects may impact the setup
and/or hold times and are not always taken into account by simulations.
System timing budgets should include margin for SSO effects.
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Term
Definition
Stub
The branch from the bus trunk terminating at the pad of an agent.
Trunk
The main connection, excluding interconnect branches, from one end.
System
Management Bus
A two-wire interface through which various system components may
communicate.
Undershoot
The minimum voltage extending below VSS observed for a signal at the
device pad.
VCC (CPU core)
VCC (CPU core) is the core power for the processor. The system bus is
terminated to VCC (CPU core).
A network that receives a coupled crosstalk signal from another network
is called the victim network.
Victim
Table 3 defines acronyms used throughout this document.
Table 3. Acronyms
Acronym
AC
Definition
Audio Codec
ACPI
Advanced Configuration and Power Interface
ADD2
Advanced Digital Display 2
ADD2N
Advanced Digital Display 2 Normal
AIC
Add-In Card
AMC
Audio/Modem Codec.
Intel
®
AMT
ASF
AMI*
Intel® Advanced Management Technology
Alert Standard Format
American Megatrends Inc.* (BIOS developer)
ATA
Advanced Technology Attachment (disk drive interface)
ATX
Advance Technology Extended (motherboard form factor)
BGA
Ball Grid Array
BIOS
Basic Input/Output System
BLI
Backlight Inverter
BPM
Break Point Monitor
CK-SSCD
CMC
CMOS
Spread Spectrum Differential Clock
Common Mode Choke
Complementary Metal-Oxide-Semiconductor
CPU
Central Processing Unit (processor)
DDI
Digital Display Interface
DDR
Double Data Rate
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Acronym
Definition
DMC
Display Mini PCIe connector
DMI
Direct Media Interface
DP
DPST
Display Port
Display Power Saving Technology
EC
Embedded Controller
ECC
Error Correcting Code
eDP
Embedded Display Port
EEPROM
Electrically Erasable Programmable Read-Only Memory
EHCI
Enhanced Host Controller Interface
EM2
Eaglemont 2 card
EMA
Extended Media Access
EMI
Electro Magnetic Interference
eSATA
External Serial Advanced Technology Attachment
ESD
Electrostatic Discharge
EV
Engineering Validation
EVMC
Electrical Validation Margining Card
ERB
Early Engineering Reference Board
FCBGA
Flip Chip Ball Grid Array
FCIM
Full Clock Integration Mode
FDD
Floppy Disk Drive
FDI
Flexible Display Interface
FIFO
First In First Out - describes a type of buffer
FIR
FPIO
FS
Fast Infrared
Front Panel IO
Full-speed. Refers to USB
FSB
Front Side Bus
FWH
Firmware Hub
GFX
Graphics
GMCH
Graphics Memory Controller Hub
GPIO
General Purpose IO
Intel
®
HDA
HDMI
HPD
HS
Intel® High Definition Audio
High Definition Media Interface
Hot Plug Detect
High Speed. Refers to USB
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Acronym
Definition
ICH
I/O Controller Hub
IDE
Integrated Drive Electronics
®
Intel MVP
IP/IPv6
Intel® Mobile Voltage Positioning
Internet Protocol/Internet Protocol version 6
IrDA
Infrared Data Association
ISI
Inter-Symbol Interference
ITP
In- Target Probe
KBC
Keyboard Controller
LAI
Logic Analyzer Interface
LAN
Local Area Network
LED
Light Emitting Diode
LOM
LAN on Motherboard
LPC
Low Pin Count (often used in reference to LPC bus)
LS
LVDS
MC
Low-speed. Refers to USB.
Low Voltage Differential Signaling
Modem Codec
MDC
Mobile Daughter Card
ME
Manageability Engine
MHz
Megahertz
MPI
Metalized Particle Interconnect
OC
Over current
ODD
Optical Disc Drive
OS
Operating System
OEM
Original Equipment Manufacturer
PCB
Printed Circuit Board
PCIe*
PCI Express*
PCH
Platform Controller Hub
PCM
Pulse Code Modulation
PECI
Platform Environment Control Interface
PEG
PCI Express* Graphics
PGA
Pin Grid Array
PLC
Platform LAN Connect
PLL
Phase Locked Loop
POST
Power On Self Test
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Acronym
PWM
Pulse width modulation
RAID
Redundant Array of Inexpensive Disks
rPGA
Reduced pitch Pin Grid Array
RTC
Real Time Clock
SATA
Serial ATA
SIO
Super Input/Output
SKU
Stock Keeping Unit
SMC
System Management Controller
SMBus
SO-DIMM
System Management Bus
Small Outline Dual In-line Memory Module
SOIC
Small-Outline Integrated Circuit
SPD
Serial Presence Detect
SPI
Serial Peripheral Interface
SPWG
Standard Panels Working Group - http://www.spwg.org/
SSO
Simultaneous Switching Output
SUT
System Under Test
STR
Suspend To RAM
TCO
Total Cost of Ownership
TCP
Transmission Control Protocol
TPM
Trusted Platform Module
TDM
Time Division Multiplexed
TDR
Time Domain Reflectometry
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
USB
Universal Serial Bus
VGA
Video Graphics Adapter
VID
Voltage Identification
VREG or VR
XDP
1.4
Definition
Voltage Regulator
eXtended Debug Port
Related Documents and Information
Table 4 provides a summary of available Intel classified documents and information
related to this development kit. To obtain, please contact your Intel representative.
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Table 4. Related Documents and Information
Document
Document
Number
[Cougar Point-M] Mobile Chipset I/O Buffer Information Specification (IBIS)
/ FASE Models
431974
[Huron River] Platform, Emerald Lake Fab 2 Customer Reference Board
Schematic
431433
[Huron River] Platform, Emerald Lake Fab 2 Customer Reference Board File
451503
[Huron River] Platform, Emerald Lake Customer Reference Board Cadence /
OrCad Symbol Files
431414
[Huron River] Platform Power Sequence Product Specification
437432
[Huron River] Platform Design Guide
436735
2nd Generation Intel® Core™ Processor Family Mobile External Design
Specification (EDS), Volume 1 and 2
445463/
Intel® 6 Series Chipset and Intel® C200 Series Chipset External Design
Specification (EDS)
445465
443554
Note: The items listed in the above table are Intel classified; please contact your Intel
representative.
1.5
Development Kit Technical Support
1.5.1
Online Support
Intel’s web site (http://www.intel.com/) provides up-to-date technical information and
product support.
1.5.2
Additional Technical Support
If you require additional technical support, please contact your Intel representative or
local distributor.
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Getting Started
2
Getting Started
2.1
Development Kit Contents
The following hardware, software and documentation are included in the kit. Check for
damage that may have occurred during shipment. Contact your sales representative if
any items are missing or damaged.
•
Letter to the Customer
o Information regarding website to download:
o System BIOS
o BIOS installation utilities
o Chipset drivers
o Intel Embedded Graphics Drivers
o Intel® Active Management Technology (Intel® AMT) software installation
kit
•
Development Kit User Guide (this document)
•
Pre-assembled development system, which includes:
o Development board
o Chassis and mounting screws (installed)
o 2nd generation Intel® Core™ processor
o Processor thermal solution and CPU back plate
•
Intel® 6 Series Chipset (installed)
•
Intel® 6 Series Chipset heatsink (installed)
•
One type 2032, 3V lithium coin cell battery (installed)
•
One 1GB DDR3 SO-DIMM
•
One power supply
•
One SATA hard disk drive
•
One SATA DVD-ROM drive
•
SATA cabling (data and power)
Current drivers required for this development are available at
http://platforms.intel.com.
2.2
Additional Required Hardware Not Included In
This Kit
The following additional hardware may be necessary to successfully set up and
operate the motherboard:
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•
VGA Monitor: Any standard VGA or multi-resolution monitor may be used. The
setup instructions in this section assume the use of a standard VGA monitor, TV,
or flat panel monitor.
•
Keyboard: The development kit can support either a PS/2* or USB style
keyboard.
•
Mouse: The development kit can support either a PS/2 or USB style mouse.
•
Hard Disk Drives (HDDs) and Optical Disc Drives (ODD): Up to six SATA
drives and two IDE devices (master and slave) may be connected to the
development kit. An optical disc drive may be used to load the OS. All these
storage devices may be attached to the board simultaneously.
•
Video Adapter: Integrated video is output from the VGA connector on the back
panel of the development kit. Alternately, an on-board HDMI connector, on-board
DP connector or LVDS displays can be used for desired display options. Check the
BIOS and the graphics driver, where appropriate, for the proper video output
settings.
•
Network Adapter: A Gigabit network interface is provided on the board. The
network interface will not be operational until after all the necessary drivers have
been installed. A standard PCI/PCI Express* adapter may be used in conjunction
with, or in place of, the on-board network adapter.
You must supply appropriate network cables to utilize the LAN connector or any other
installed network cards.
2.3
•
Other Devices and Adapters: The development kit functions much like a
standard desktop computer motherboard. Most PC-compatible peripherals can be
attached and configured to work with the development kit.
•
Add-In Cards: The following add-in cards are mentioned throughout this
document and are used to enable different features on the board. They are not
provided with the board. Please contact your Intel representative for more
information on the functionality and availability of these cards.
o
Eaglemont card
o
Mott Canyon 4 card
o
Elk Creek card
o
ADD 2 card
o
Saddle String 3 card
Additional Required Software Not Included in this
Kit
The following additional software may be necessary to operate this system:
•
Operating System: The user must supply any needed operating system
installation files and licenses. A recent version of the Linux-based operating
system Fedora will be loaded into the SATA drive.
•
Application Software: The user must supply any needed application software.
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Getting Started
2.4
Workspace Preparation
The development kit is shipped as an open system to provide flexibility in changing
hardware configurations and peripherals in a lab environment. Because the board is
not in a protective chassis, the user is required to take the following safety
precautions in handling and operating the board.
2.5
•
The power supply cord is the main disconnect device to main power (AC power). A
power outlet should be readily accessible.
•
To avoid shock, ensure that the power cord is connected to a properly wired and
grounded receptacle.
•
Ensure that any equipment to which this product will be attached is also
connected to properly wired and grounded receptacles.
•
Use a flame-retardant work surface and take note of the closest fire extinguisher
and emergency exits.
•
Ensure a static-free work environment before removing any components from
their anti-static packaging. Wear an electrostatic discharge (ESD) wrist strap when
handling the development board or other development kit components. The
development board is susceptible to ESD damage, and such damage may cause
product failure or unpredictable operation.
System Setup
Please complete the steps outlined below to ensure the successful setup and operation
of your development kit system.
The following items should already be completed in the kit (i.e., no user procedure
required):
•
Place one or more DDR3 SO-DIMMs in memory sockets, populating J4V1 and/or
J4U1.
•
Place the quad-core Intel® Core™ i7-2710QE processor in socket U3E1 and lock in
place. Make sure to align the chip to the pin 1 marking. The kit includes a second
CPU for evaluation — the dual-core Intel® Core™ i5-2510E processor.
•
Install the MPI socket and place the chipset at U7F1
•
Attach the heat sink/fan for the processor at U3E1 and plug the fan power cable
into J3B1.
•
Install the configuration jumpers as shown in Table 24 of this document. Refer to
Table 19 for a complete list of jumper settings.
•
Verify presence of RTC battery in battery holder at BT5G1.
•
Plug a mobile ATX AC brick into J1F2. Optionally plug in a battery pack into J1H1
or J1H2. Do not mix mobile and desktop power configurations.
•
Attach a hard drive in J8J1.
The following steps need to be completed by the user:
1. Connect a PS/2 keyboard in J1A1 (bottom) or a USB keyboard in one of the
USB connectors.
2. Connect a PS/2 mouse in J1A1 (top) or a USB mouse in one of the USB
connectors.
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3. If internal graphics is not used, plug a PCIe* graphics card in the PCIe x16
slot J5C1 and connect a monitor to the card.
4. Connect an Ethernet* cable (optional), one end of the cable to the
motherboard, the other end to a live Ethernet hub.
5. Connect the monitor to the VGA connector. Also plug the monitor’s power
cable into an outlet.
2.6
System Power-Up
Having completed the steps outlined above, you are now ready to power up the
development kit:
1. Press the power button located at SW1E1.
2. As the system boots, press F2 to enter the BIOS setup screen.
3. Check time, date, and configuration settings. The default settings should be
sufficient for most users with the exception of Intel SpeedStep® Technology.
This feature is disabled by default and can be enabled in setup.
4. The PCIe hot plug support has to be enabled in setup if hot plug detect is
required.
5. Save and exit the BIOS setup.
The system boots and is ready for use.
Note: Fan/heatsink installation is discussed in Section 8.
Install operating system and necessary drivers:
Depending on the operating system chosen, drivers for components included in this
development kit can be found in http://edc.intel.com/Platforms/Core-QM67HM65/#sdrvutil. Please note that not all drivers are supported across all operating
systems.
2.7
System Power-Down
There are three options for powering-down the development board:
•
Use OS-controlled shutdown through the Windows* Start menu (or equivalent)
•
Press the power button on the motherboard at SW1E1 to begin power-down.
•
If the system is hung, it is possible to asynchronously shut the system down by
holding the power button down continuously for 4 seconds.
Note: Powering-down the board by shutting off power at the ATX power supply is not
recommended.
2.8
System BIOS
A version of the AMI* BIOS is pre-loaded on the development board.
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2.8.1
Configuring the BIOS
The default BIOS settings may need to be modified to enable or disable various
features of the development board. The BIOS settings are configured through a menudriven user interface, which is accessible during the Power On Self Test (POST). Press
the F2 key or Delete during POST to enter the BIOS interface.
For AMI BIOS POST codes, visit: http://www.ami.com.
For BIOS updates, please contact your Intel representative or visit
http://edc.intel.com/Platforms/Core-QM67-HM65/#sdrvutil.
2.8.2
Programming BIOS Using a Bootable USB Device
The flash chips that store the BIOS and BIOS extensions on the development board
are connected to the SPI bus and are soldered down. One method of programming
these devices is through software utilities described below. The software files and
utilities needed to program the BIOS are contained on the included CD-ROM.
Follow these steps to program the system BIOS using a bootable USB device:
1. Prepare the workspace as outlined in Section 2.4.
2. Set up the system as outlined in Section 2.5.
3. Unplug the hard disk drive (HDD) SATA cable from the board at connector
J6J3 so that the board will boot from the bootable USB key.
4. Copy the following files and utilities to a bootable USB device, preferably a
USB flash memory stick.
BIOS Image Files:
o spifull.bin
BIOS programming software utilities:
o fpt.exe (DOS SPI flash utility)
o fparts.txt (helper file)
MAC Address programming software utility:
o eeupdate.exe
o Other helper files contained on the included CD-ROM
5. Record the 12-digit MAC address of the board from the sticker near the CPU.
6. Insert the bootable USB key into one of the USB ports on the development
board.
7. Switch on the power supply (to “1”).
8. Press the power (PWR) button on the development board.
9. Wait for the system to boot from the USB key to a DOS prompt.
10. From the DOS prompt (C:>), run the following:
o fpt –f spifull.bin
Make sure there are no warnings or errors.
11. From DOS, run the following to reprogram the MAC address:
o eeupdate /nic=1 /mac=xxxxxxxxxxxx
o where xxxxxxxxxxxx is the MAC address from the sticker
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Make sure there are no warnings or errors.
12. From DOS, run the following to update the Keyboard and System Controller
flash:
o kscupdate ksc.bin
Make sure there are no warnings or errors.
13. Power the system down by pressing the PWR button.
14. Clear the CMOS by performing the following:
a.
Shunt the CMOS CLR jumper (J5F3 – near the on-board battery).
b.
Press the PWR button on the board. The board will not power on, but a
couple of LEDs will flash.
15. Switch the power supply off to power down the board.
a.
Remove the CMOS CLR jumper (J5F3).
16. Unplug the bootable USB key.
Verify Correct BIOS Installation:
1. Switch the power supply back on.
2. Press the PWR button on the board to power-up the system.
3. Boot to BIOS Configuration screen by pressing F2 at the BIOS splash screen.
4. In the BIOS Main screen, check that the “Project Version” lists the correct
version of the BIOS.
5. Press the PWR key on the board to power the system back down, or you may
simply exit the BIOS menu and continue booting into the operating system.
The system is now ready for normal operation.
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Development Kit Features
3
Development Kit Features
Figure 1. Development Board Block Diagram
Table 5. Development Board Feature Description
Feature
Processor
Development Board
Implementation
Intel® Core™ i7/i5-Mobile processor
supported in 989-pin rPGA package
in Socket-G
Description
Supports two DDR channels. The
development board supports x4 (in
each direction) Direct Media
Interface (DMI), two interfaces
working at 5 GT/s; the board
supports x4 Intel® Flexible Display
Interface (Intel® FDI); max
supported speed is 2.7GT/s
Intel® 6 Series Chipset 989-pin FCBGA footprint
Memory
2x DDR3 SO-DIMM slots
The development board supports
DDR3 frequency of up to 1333 MHz.
External
Graphics
1x PCIe x16 graphics slot
Can be supported as: 1x16 PEG
through x16 PEG slot on board.
Supports Gen 2 speeds (5 GT/s).
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Development Board
Implementation
Feature
Description
1x 24-bit dual-channel LVDS
interface
50-pin connector (J7D3) on-board;
cables from Intel 5 series-M chipsetbased platform development boards
can be re-used.
Embedded display port
x4 eDP from Intel® Core™ i7/i5
processor connected to on-board
embedded display port (eDP)
connector at J4E1.
Display Port
Port B: Connected to x16 connector
at J8C2. Requires Eaglemont add-in
card Port C: Switchable connection
to x16 connector at J8C2 or docking
connector at J9C1 Port D: Default
connection to Display Port connector
at J5A1.
HDMI
Port B: Connected to x16 connector
at J8C2. Requires Eaglemont add-in
card Port C: Switchable connection
to x16 connector at J8C2 or docking
connector at J9C1 Port D:
Unpopulated stuffing option
connection to HDMI connector at
J3A1.
Video
DMC
Display Mini PCIe connector is
provided on-board (J7M1). DisplayPort D is optionally connected to
DMC. PCIe – Port-8 is by default
connected to DMC.
Video
SDVO
Port B: Connected to x16 connector
at J8C2. Requires ADD2N add-in
card.
Video
CRT
On-board right-angled CRT
connector
No slots on-board
Not supported by the Intel 6 Series
chipset.
PCIe
8x PCIe x1 lanes from the Intel 6
Series chipset
PCIe Gen 2.0 Compliance, 5 GT/s
speed; four ports to x1 PCIe slots;
one port to x4 slot, one lane to
Intel® 82579 Gigabit Ethernet
Controller LAN, one lane to docking
by default, one lane to display Mini
PCIe.
On-Board LAN
Intel 82579 Gigabit Ethernet PHY
(Lewisville) supported
EU7M1 is the PHY on-board and
J4A1is the LAN connector.
SPI flash devices
Support for multi-vendor SPI 2x 8MB SOIC-8 parts provided on-board.
Supports multi-package (SOIC-8
Video Cables
Video
Video
Video
PCI
BIOS (SPI)
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Development Kit Features
Feature
Development Board
Implementation
Description
and SOIC-16).
Soft
Audio/Soft
Modem
SATA
USB2.0
LPC
SMC/KBC
Clocks
RTC
Processor
Voltage
Regulator
3.1
Intel® High Definition Audio MDC
header
Support via interposer; use Mott
Canyon 4 daughter card (support
via sideband cable).
6x SATA ports
Two ports capable of 6 GT/s; one
Direct Connect connector, one cable
connect, one SATA ODD connector,
two eSATA connectors, and one to
dock
14x USB 2.0/1.1 ports
One Dual Stacked Dual and DP
Connector, one Dual USB connector
on RJ45, eight ports available as
FPIOs. Two ports routed to USB2/3
Dual Stacked connector; optional
Routing to Docking for USB Lane 4
Over Current protection provided in
Pairs. Floater OC7# used as
SMC_WAKE_SCI#
1x LPC slot
Includes sideband headers
H8S/2117* microcontroller; two PS/2
ports, one scan matrix keyboard
connector
ACPI compliant
CK505 system clock
Board supports both Buffered mode
and Fully integrated clocking
schemes.
Battery-backed real-time clock
Implementation similar to previous
generation Intel mobile platforms.
Intel® Mobile Voltage Positioning-7
compliant CPU and graphics voltage
regulators (GFX VRs)
Uses Serial VID interface Manual
Override Option for VIDs not
available on VR controller; uses
Serial VID interface instead of
Parallel VIDs.
Processor Support
The development board supports the 2nd Generation Intel® Core™ processor family in
a 989-pin rPGA package (U3E1), which fits into Socket G2.
The processor features a monolithic die with integrated memory and graphics
controller.
Note: Socket G2 -- Socket 988B specifically meant for 2nd Generation Intel® Core™
processor family. It has pins A1, B1 de-populated compared to rPGA 989.
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3.1.1
Clock Requirements
The processor requires two external clock inputs:
•
100 MHz BCLK given as reference clock input to Core, DMI, Intel FDI, PEG and
DDR PLLs.
•
120 MHz DP_CLK given as reference CLK input for the Display port PLL
Note: To achieve a 100 MHz BCLK, ensure the J6G1 jumper on-board is unstuffed (1-X).
3.1.2
Processor Voltage Regulator
The board implements an on-board Intel Mobile Voltage Positioning (Intel® MVP)-7
voltage regulator (VR) for the processor-core and graphics-core power supply.
The main feature of Intel MVP-7 regulator is that it is serial-VID-based, which is
introduced for the first time in this platform. Both the processor core and graphics
core VRs are integrated into single package. The serial VID interface is shared by both
the processor core and graphics core VRs.
3.1.2.1
SVID Supported in Intel® MVP-7 Voltage Regulator
Intel® Mobile Voltage Positioning (Intel® MVP)-7 uses a 3-wire serial interface called
SVID (DATA, CLK and ALERT#), for regulating both the processor core and graphics
core voltages.
Some of the main differences in the platform with the introduction of SVID are:
•
SVID can be used to communicate the power states along with the VID signals.
Hence, signals like PSI# and DPRSLPVR used to indicate the power states in
previous platforms, will be absent in this platform.
•
There is no support for on-board override mechanism as done in case of Parallel
VIDs in previous platforms.
•
SVID interface is shared by both the processor core VR and graphics core VR.
Note: Ensure jumpers J1C6, J1D3 and J1D7, which are placed on the SVID path between
processor and Intel MVP, are shorted (1-2).
3.1.3
Power Management and Key Signals
The processor supports C0, C2, C2E, C3, Deep Power Down Technology, and C7
states. All power management handshakes happen over the DMI-2 interface. None of
the ‘Power State’ status signals can be observed on the board directly. The only way
to detect the entry to/exit from the C2/C3 C-States is to read the DMI-2
transmissions.
Some important power management pins on the processor are listed below.
•
SM_DRAMPWROK: Input from the Intel® 6 Series Chipset PCH indicating to the
MCH with regards to DRAM power. When DRAM power is turned off, MCH uses this
as one of the conditions to assert DDR3 RST signal.
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Development Kit Features
•
UNCOREPWRGOOD: Input from the chipset indicating that the system rails and
clocks are stable. Once the PWRGOOD is asserted, the processor is ready to be
brought out of reset.
•
PLT_RST#: The chipset asserts PLT_RST# signal during power-up or when
software initiates hardware reset to reset all the devices on the platform.
Some other key signals from processor are:
3.1.4
•
VCCSA_VID: VID output from processor to system agent VR. This input is used
by system agent VR to select the output voltage.
•
VCCP_SEL: VCCP_SEL pin of the processor (ball# A19) is used to select VCCP
voltage.
Memory Support
The development board supports dual-channel DDR3 memory interface with one
SODIMM per channel. The integrated memory controller can support a maximum of
two ranks of memory per channel.
There are two DDR3 SO-DIMM sockets (J4U1 for Channel A and J4V1 for Channel
B SODIMM slot) on the bottom side of board in stacked manner. Please see Figure 2
for snapshots on stacked SODIMM slots.
The board supports:
•
Data transfer rate: 1067 MT/s (PC3-8500), 1333MT/s (PC3-10600)
•
DDR3 SO-DIMM Modules supported:
o Raw Card A – double-sided, x16 data width, unbuffered, non-ECC
o Raw Card B – single-sided, x8 data width, unbuffered, non-ECC
o Raw Card C – single-sided, x16 data width, unbuffered, non-ECC
o Raw Card F – double-sided, x8 data width, unbuffered, non-ECC
•
DDR3 DRAM device technology supported:
o Standard 1-Gb, 2-Gb and 4-Gb technologies
•
DDR3 module with inbuilt thermal sensor can be supported. There is also an onboard a thermal sensor (U2W2) closer to the SODIMMs.
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Figure 2. Side View of Stacked SODIMM Slots
NOTE: The channel B connector has a height of 5.2 mm and the Channel A slot has height of
9.2 mm.
3.1.5
Graphics Support
3.1.5.1
Internal Graphics Support
The development board supports internal graphics (from CPU) through Embedded
display port from the processor. There are x4 differential lanes from processor to
panel (sink). The processor can support link rates of 1.62 Gbps or 2.7 Gbps.
The eDP is no longer mux’ed with PEG lanes; the processor has dedicated eDP ports
and an on-board eDP connector is provided to support this feature. The Eaglemont
AIC is not required to support eDP from the processor.
To enable eDP:
J8D3 should be (1-2). This is done because the eDP and LVDS embedded displays
have the same enable/control signals. To ensure that only one embedded display is
supported at a time, eDP should be enabled and disable LVDS display. By doing the
jumper settings change, power supply input to eDP panel is enabled and the LVDS is
disabled. This jumper is a new addition for the easy switching between LVDS and eDP
display.
By default on-board configuration is J8D3 (2-3), i.e., this supports LVDS panel.
Jumper setting change is required to enable eDP panel only.
Pull-down CFG4 strap by shorting the jumper J1E1. Strap definition is provided in the
following table.
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Development Kit Features
3.1.5.2
Strap
0
1
CFG4
An eDP panel device is
connected to eDP port (Short
J1E1 – (1-2))
No Display Port connected to eDP
(default—J1E1- (1-X))
External Graphics Support
The development board supports external graphics through an on-board PCIe graphics
x16 slot. This interface is fully compliant to the PCIe Base Specification Revision 2.0.
The board supports Gen 2 (5.0 GT/s) PCIe frequencies.
Switchable Graphics is also supported on the board. It can be validated using the Elk
Creek add-in card.
Table 6. CFG[6] and [5] Straps Combined and Used for PEG Interface Configuration
Strap
CFG[6:5]
11
X16 PEG interface (DefaultUNSTUFF R2R31, R2R25)
10
PEG 2x8 bifurcation enabled
(STUFF R2R31)
Table 7. Other PEG Interface Straps
Strap
1
CFG2
Lane-reversed (STUFF R2R47)
Not lane-reversed. (Default)
CFG7
PEG wait for BIOS for training
(STUFF R2R20)
PEG training followed by RST#
deassertion (Default UNSTUFF R2R0)
NOTE:
3.1.5.3
0
The processor supports lane-reversal of the PEG lanes, but the development board uses
non-lane-reversed routing.
Direct Media Interface (DMI)-2 Interface
The development board supports x4 DMI-2 bidirectional lanes (four lanes in each
direction) between the processor and PCH. DMI is the key interface between the
processor and the Intel® 6 Series Chipset. Apart from this, it is also used to transfer
information such as ME data, and power-management signals such as SLP#,
DPRSLP#, DPRSLPVR#, STP_CLK#. All the power-management handshakes happen
across this interface. The board supports a maximum speed of 5 GT/s (Gen 2 speed).
The series resistors in the path of FDI/DMI lanes for earlier platforms are removed in
the development board.
3.1.6
Intel® Flexible Display Interface (Intel® FDI)
Intel FDI is a dedicated link to transmit the display-related pixel information over
unidirectional 2x4 lanes from processor to PCH. The maximum supported speed for
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this interface is 2.7GT/s. The synchronization signals are directed from PCH to
processor.
3.1.7
Processor Thermals
The processor temperature is communicated to the Embedded Controller over the
PECI, a single wire interface..
Some important signals include:
3.1.8
•
CATERR#: Indicates that the system has experienced a catastrophic error and
cannot continue to operate. It is indicated by red LED (CR1D1 on board).
•
PROCHOT#: PROCHOT# will go active when the processor temperature
monitoring sensor detects that the processor has exceeded the thermal
specifications.
•
THERMTRIP#: Assertion indicates that the processor junction temperature has
reached a level beyond which permanent silicon damage may occur.
Processor Active Cooling
The development board supports PWM-based fan speed control. Fan circuitry is
controlled by the signal CPU_PWM_FAN signal from the EC. On the board a 4-pin
header J3B1 is provided to support fan speed output measurement for the processor.
3.2
PCH Support
The development board supports the Intel 6 Series chipset, both MPI socketed and
soldered down on the board.
3.2.1
Introduction to the Intel® 6 Series Chipset
The Intel 6 Series chipset is the next-generation platform controller hub (PCH). The
major differences between the Intel Q5 Series and the Intel 6 Series chipset PCH
include:
3.2.2
•
DMI Gen 2 (5 GT/s)
•
8 PCIe 2.0 ports (5 GT/s)
•
SATA/eSATA Ports - 6 ports (2 FIS-based switching) with up to 2 ports at 6 Gb/s
•
6 USB 2.0 ports (4 dedicated and 2 mux’ed with PCIe)
•
Package Mobile FCBGA 989 balls, 25-x-25-x-0.6 mm FCBGA
•
PCI interface is not supported
Key Power Management Signals
•
RSMRST#: This signal from H8 initiates the Reset sequence in the Intel 6 Series
chipset.
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Development Kit Features
3.2.3
•
DRAMPWROK: Power good signal for DDR.
•
APWROK: Indicates that the ME rails to PCH are stable.
•
SYS_PWROK: Signal indicates that all platform Power Rails to PCH are stable.
•
PLT_RST#: Platform Reset Signal indicated by CR5H1.
PCIe* Support
The development board supports six on-board PCIe (5x1 and 1x4) slots. The Intel 6
Series chipset has a total of eight Gen 2 PCIe ports. By default, four of those IO ports
have been routed to x1 connectors, one to a x4 connector, one to LAN, one to Display
Mini PCIe connector, and one to docking.
Slot 1 and 2 are in-line and close to the PCH. Slots 3 and 4 are in line and close to the
processor. Slot 5 is a x4 slot.
Table 8. PCIe* Ports
PCIe Port
Default Destination
Non-Default
Destination
1
PCIe Slot 1 (J6C2)
-
2
PCIe Slot 2 (J6D2) (in-line
with Slot 1)
-
3
PCIe Slot 3 (J7C1)
-
4
PCIe Slot 4 (J7D2)
-
5
PCIe Slot 5 (J6C1)
-
6
LAN (EU7M1)
PCIe Slot 5 (J6C1)
7
DOCKING (J9C1)
PCIe Slot 5 (J6C1)
PCIe Slot 6 (J8C1)
8
DISPLAY MINI PCIe
Connector(J7M1)
PCIe Slot 5 (J6C1)
DOCKING (J9C1)
More details on the reworks to be done for different destinations of the PCIe ports are
given below.
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Figure 3. PCIe* Port Mapping – Schematic Snapshot
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Table 9. Reworks for Different Port Mappings
Ports
STUFF
Slot 5 as x1
5
Xh
LAN
6
Xf, Xg
Xe, Re
LAN;
Docking x1
7
Xb, Rb
Xa, Ra
Docking – x1 and
DMC
8
Xc
Rc, Rd, Xd
DMC – PCIe
5,6
Xh, Xe, Re
Xf, Xg
Slot 5 as x2, no LAN support;
Xb, Rb
Xa, Ra
Docking x1
Xc
Rc, Rd, Xd
DMC
Slot 5 as x2
5,6,7,8
Slot 5 as x4
7
NO_STUFF
Support
Slot 5 as x1;
Xh
Slot 5 as x4
Xe, Re
Xf, Xg
LAN - not supported
Xa
Xb, Rb, Ra
Docking - not supported
Xd, Rd
Xc, Rc
DMC - not supported
Xb, Ra
Xa, Rb
Docking – x1 not supported
Xh
Slot 6
7, 8
Docking x2
Slot 5 as x1 –supported
Xf, Xg
Xe, Re
LAN – supported
Xc
Rc, Rd, Xd
DMC – supported
Xb, Rb
Xa, Ra
Docking – x2 supported
Xd, Rc
Xc, Rd
DMC - not supported
Xf, Xg
Xe, Re
LAN supported
Xh
3.2.4
Slot 5 as x1 –supported
On-Board LAN
The development board supports 10/100/1000 Mbps Ethernet through the on-board
Intel 82579LM Gigabit Ethernet PHY (EU7M1). The LAN PHY has PCIe and SMBus
connections to the PCH. It is routed to Dock via the Docking Switch. Data transfer
occurs over PCIe lanes. Communication between the LAN controller and the LAN
Connected Device is handled via the SMBus whenever the system is in a low-power
state (Sx).
Figure 4 shows an on-board LAN block diagram.
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Figure 4. On-Board LAN Block Diagram
®
Intel® 6 Series
Chipset
Intel 82579
GbE PHY
On the development board, the LAN connector supported is a stacked RJ45 with dual
USB connector (J4A1). The top port is RJ45 and middle and bottom ports are USB2.0
There is also an option to support PHY on dock. If this is desired, users must plug a
card with a PHY into the PCIe slot 2 (J2D1) on the Saddle String 3 add-in card.
3.2.5
Soft Audio and Modem
Intel High Definition Audio functionality is enabled through the Mott Canyon 4
daughter card. The PCH supports four Intel HD audio codecs. All four are routed to
Mobile Daughter Card (MDC) header through resistor stuffing options. By default,
codec 0 and 1 are connected to the card. An on-board header is provided at J9E6 and
J9E8 for this purpose. No direct connection is provided for the Intel HD Audio Card on
the development board; the Mott Canyon 4 card is required to enable the Intel HD
Audio functionality.
The development board supports low-voltage (LV), high-definition codecs I/O. R8E1,
R8R11, and R8R12, R8R10 resistors are used to select between 3.3 V I/O and 1.5 V
I/O.
Table 10. Selection of I/O Voltage for the Intel® High Definition Audio
3.2.5.1
I/O Voltage for the
Intel HD Audio
Stuff
No stuff
3.3 V (Default)
R8R12, R8R10
R8R11, R8E1
1.5 V
R8R11, R8E1
R8R12, R8R10
Realtek* Audio Card Support
For users who want to use the Realtek* audio card, the PCIe-268Q* is an audio card
with PCIe full-size form factor. Through HDA connector and an extra ATX P4 power
connector, PCIe-268Q can support external speakers (up to 2.3W/ch), microphone-in,
line-in, headphone-out, and SPDIFout ports (in current operating systems, all ports
working at the same time is not supported). The PCIe-268Q also supports to connect
two sets of digital microphone modules. With customized driver, multiple streaming
can be supported for recording and playback by individual ADC and DAC. On-board,
power measuring resistors are reserved for easy probing to measure the power
consumption when different use-case scenarios.
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For more details, please refer to the Realtek PCIe-268Q User Guide.
3.2.6
SATA Storage
The Intel 6 Series chipset has six SATA ports, out of which two ports, ports 0 and 1,
support speeds up to 6 Gbps. SATA port 0 is connected to J8J1 (direct connect), port
1 is connected to J7J1 (cable connect) with power connector at J6H1. Port 2 is
connected to SATA ODD connector J9E7. Ports 3 and 4 are eSATA connectors (J6J1
and J7J1). Port 5 is routed to docking.
Table 11. SATA Ports
SATA Port
Connection Type
Connector
Port 0
Direct Connect
J8J1
Port 1
Cable Connect
J7G1
Port 2
SATA ODD
J9E7
Port 3 & Port 4
e-SATA
J6J1 & J7J1
Port 5
Direct connect (default)
eSATA (optional)
J9C1 (Docking connector)
The development board has a power connector (J8J1) to power the serial ATA hard
disk drive (for direct connect). For cable connect SATA, the power connector is J6H1.
A green LED at CR7G2 indicates activity on SATA channel.
Y-Power cable needs to be connected first to the device on Port 1 before connecting
the signal cable. Hot swap is supported only on port 1.
The eSATA drives should be externally powered. Hence, there is no power supply
support for them on the motherboard.
3.2.7
Displays
The development board supports the following displays via the PCH.
Please note that display connectors DP/HDMI are on Port D of the PCH. Port B and C
can be used through the Eaglemont 2 Fab 3 add-in card.
CRT
A right-angled CRT connector has been provided on-board (J1A2). Optional routing to
the docking connector is supported through a CRT DOCK Switch (U6C1).
LVDS
LVDS support is very similar to that used on earlier platforms. Connector is at J7D3.
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HDMI
J3A1 is the on-board HDMI connector. HDMI connectors are also available on the
Eaglemont 2 Fab 3 AIC. Discrete level shifter is implemented for HDMI interface
support and the level translator IC on earlier boards has been removed.
Display Port (DP)
•
DP connector (bottom port J5A1) is changed from earlier platforms to a stacked
dual USB and DP connector. The physical connector remains the same. Only its
placement has been changed on the development platform.
•
The DP/USB2 is actually two connectors each placed on the board separately. The
middle and the top ports being part of a high-rise, dual-USB connector and the
bottom port used for the DP connector.
•
Display Port connectors are also available on the Eaglemont 2 Fab 3 AIC.
Figure 5. Back Panel Connectors
Embedded Display Port (eDP)
Port D on the Intel 6 Series chipset can be configured as eDP port. By default, eDP
from the processor is used, but optional support is provided for eDP from the PCH as
well. Please refer to Section 3.2.7.3 for more details.
If using eDP from the chipset, the LVDS cable has to has to be connected from the
development board to Elk Creek add-in card for the Sideband signals. Refer to Section
3.2.7.3 for details on enabling eDP from the chipset.
SDVO
•
SDVO can be configured only on Port B. It is supported on ADD-2 add-in card,
which is inserted into the DDI slot J8C2.
•
A maximum of two displays can be active at a time.
Digital Display Interface Configuration Modes
•
3x Display Ports
•
3x HDMI/DVI Ports
•
2x DP + 1x SDVO
•
2x DP + 1x HDMI/DVI
•
2x HDMI/DVI + 1x SDVO
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•
2x HDMI/DVI + 1x DP
•
1x DP + 1x HDMI/DVI + 1x SDVO
Figure 6. Display Ports On-Board
3.2.7.1
DP/HDMI Support
One DP and one HDMI connector are provided on the development board.
Port D of the Digital Display Interface on the PCH is mapped to on-board DP, HDMI,
and DMC connectors.
DP is the default configuration. To select HDMI, rework is required.
For HDMI:
1. UNSTUFF C5A3, C5A4, C5A5, C5A6, C5B1, C5B2, C5B3, C5B4
2. STUFF R5A3, R5A4, R5A5, R5A6, R5B1, R5B2, R5B3, R5B4, R3M6, R2N4,
R2A3, R3M2, R3A11 (with 0-Ohms)
For HPD:
1. UNSTUFF R4A2 and STUFF R4A1 with 0 Ohms
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3.2.7.2
DMC Support
The development board supports a Display Mini PCIe connector. The three primary
data interfaces defined for PCIe Mini Card are: PCIe, USB and DisplayPort.
On the board,
•
PCIe port 8 is connected by default to DMC;
•
An option is provided for Display Port D to be connected to DMC. The reworks
required on the board are:
o UNSTUFF C5A3, C5A4, C5A5, C5A6, C5B3, C5B4, C5B1, C5B2, C5B5,
C5B7
o STUFF C5N3, C5N4, C5M4, C5M5, C5N1, C5N2, C5M2, C5M3, C5B6, C5B8
with 0.1 µF cap
o The caps unstuffed as shown in UNSTUFF above can be used for those
shown in STUFF, also above
o For HPD, UNSTUFF R4A2 and stuff R4A3 with 0 Ohm
An option is provided for USB2.0 port 0 to be connected to DMC. For this, the
following reworks have to be done: STUFF R5B12, R5B13, R6A11, R6A12 (with 0
Ohms), UNSTUFF R5B11, R5B14.
Figure 7 Mini PCIe Connector Soldered In Place of DMC
•
3.2.7.3
C-link support is also provided for DMC. The reworks required for this are:
o UNSTUFF R7C29, R7D1, R7C26
o STUFF R7C25, R7C24, R7C23 (with 0 Ohms)
Switchable Graphics
“Switchable graphics” is a platform feature where you can seamlessly switch between
internal and external graphics modes.
This feature is supported on the 2nd Generation Intel® Core™ processor family and
Intel® 6 Series Chipset development board via the Elk Creek-4 add-in card (on PEG
slot).
To enable switchable graphics, the J9F4 setting needs to be changed to (2-3). No
board reworks are required.
All display interfaces are from the PCH other than eDP, which is supported via the 2nd
Generation Intel® Core™ processor family. If one of the DP ports from PCH is to be
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used for eDP switchable graphics, Ports C and D can be used (see the following
procedure).
Switchable Graphics with eDP over PCH
Display Port D of the PCH can be configured as eDP (Embedded Display Ports). The
development board can support switchable graphics with eDP, from the PCH, as
display.
Figure 8. Switchable Graphics with eDP from PCH
eDP over Port D
Use the following step:
1. Connect a cable from on-board DP (J5A1) connector to Elk Creek DP
Connector.
3.2.8
USB Connectors
3.2.8.1
USB2.0
The PCH provides fourteen USB 2.0/1.1 ports.
Two ports (0 and 1) are routed to a stacked dual USB and DP connector (J5A1), and
two (ports 2 and 3) are routed to a stacked dual USB2.0 connector (J3A2) at the back
panel.
Two more USB ports (8 and 9) are routed to RJ45 plus Dual USB Connector (J4A1) on
the back of the chassis.
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IO headers are provided for the other eight USB lanes. Port 4 is also routed to
docking. To enable USB port 4 to docking, STUFF R8U3, R8U5 and UNSTUFF R8F4,
R8F6.
Overcurrent protection has been provided for ports in pairs. Ports (0,1), (1,2)…
(12,13) share the OC Indicators.
Table 12. USB Port Mapping
USB Port
Panel
Connector
Port 0
Back Panel I/O Connector
J5A1 (stacked dual USB and DP connector)
Port 1
Back Panel I/O Connector
J5A1 (stacked dual USB and DP connector)
Port 2
Back Panel I/O Connector
J3A2 (stacked dual USB2.0 connector)
Port 3
Back Panel I/O Connector
J3A2 (stacked dual USB2.0 connector)
Port 4
FPIO
Docking connector(J9C1) Option to J8H2
(2x5 Connector)
Port 5
FPIO
J8H2 (2x5 Connector)
Port 6
FPIO
J7H5 (2x5 Connector)
Port 7
FPIO
J7H5 (2x5 Connector)
Port 8
Back Panel
J4A1
Port 9
Back Panel
J4A1
Port 10
FPIO
J7H6 (2x5 Connector)
Port 11
FPIO
J7H6 (2x5 Connector)
Port 12
FPIO
J7H2 (2x5 Connector)
Port 13
FPIO
J7H2 (2x5 Connector)
The table below indicates the OC mapping for all the USB2.0 ports.
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Table 13. USB2.0 Ports
3.2.9
OC0#
0 and 1
OC1#
2 and 3
OC2#
4 and 5
OC3#
6 and 7
OC4#
8 and 9
OC5#
10 and 11
OC6#
12 and 13
OC7#
GPIO
LPC Super I/O (SIO)/LPC Slot
A SMSC SIO1007* serves as the SIO on the development board and is located at
U9A1. Shunting the jumper at J8C3 to the 2-3 positions can disable the SIO by
holding it in reset. This allows other SIO solutions to be tested in the LPC slot at J8F2.
A sideband header is provided at J9G2 for this purpose. This sideband header also has
signals for LPC power management.
3.2.10
Serial Port, IrDA
The SMSC SIO incorporates a serial port, and IrDA (Infrared), as well as generalpurpose IOs (GPIO). The Serial Port connector is provided at J1A2. The IrDA
transceiver on the development board supports SIR (slow IR), FIR (Fast IR) and CIR
(Consumer IR). The option to select between these is supported through software and
GPIO pin (IR_MODE) on the SIO.
3.2.11
System Management Controller (SMC)/Keyboard
Controller (KBC)
A Renesas H8S/2117* (U9G4) serves as both SMC and KBC for the development
board. The SMC/KBC controller supports two PS/2 ports, battery monitoring and
charging, wake/runtime SCI events, CPU thermal monitoring/fan control, GMCH
thermal throttling support, LPC docking support and power sequencing control. Also,
the PECI, which was earlier supported from PCH to CPU is now supported directly from
EC, since the EC now has built-in PECI.
The two PS/2 ports on the board are for legacy keyboard and mouse. The keyboard
plugs into the bottom jack and the mouse plugs into the top jack at J1A1. Scan matrix
keyboards can be supported via a connector at J9E2.
There is an LPC slot (J8F2) and LPC Sideband connector (J9G2) on the board to
connect external EC for validation purposes. On-board EC has to be disabled by
shorting pin 1 and 2 of connector J9F2 and external EC has to handle board power
sequencing and thermal management.
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To simply read thermal information from the PCH by the external EC/fan controller,
only PCH SMBus signals (SML1_CLK and SML1_DATA) from the LPC sideband
connector can be used without connecting the EC on the LPC slot.
3.2.12
SPI
The Serial Peripheral Interface on the PCH can be used to support two compatible
flash devices (U8C2 and U8D2), storing Unified BIOS Code. Both U8C2 and U8D2 are
SOIC-8, 8 MB devices. An option is also provided for two SOIC-16 devices (U8C1 and
U8D1).
Of the SOIC-8 and SOIC-16 footprints supported, only one of these can be used at a
time. The footprints are positioned over one another. By default, U8C2 and U8D2 are
stuffed.
SPI sockets can be used. Socket KOZ is available, and a Dedi-Prog Header (J8E1) has
been provided for SPI programming.
Table 14. Jumper Settings for SPI Programming
3.2.12.1
Mode
J8C4
J8D1
J8C5
Normal Operation
1-X
1-X
1-X
Programming SPI0
1-2
1-2
1-2
Programming SPI1
1-2
2-3
1-2
Multi-BIOS Support
Multi-BIOS support is provided through an IO expander. Jumpers J9E1, J9E2, J9E3
need to be configured accordingly to select the required BIOS image.
The BIOS image is selected via the signals BIOS_SEL0, BIOS_SLE1, BIOS_SEL2. The
following table shows the jumper settings to set these signals to the required values.
Jumper
J9E1
J9E2
J9E3
(1-2)
BIOS_SEL0 = 0
BIOS_SEL1=0
BIOS_SEL2 =0
(1-x)
BIOS_SEL0 = 1
BIOS_SEL1=1
BIOS_SEL2 =1
Table 15 shows the different images corresponding to the settings of BIOS_SEL2,
BIOS_SEL1, BIOS_SEL0, and the corresponding LEDs.
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Table 15. Multi-BIOS Implementation
3.2.12.2
BIOS_SEL2
BIOS_SEL1
BIOS_SEL0
IMAGE
0
0
0
0 (DEFAULT)
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
1
1
1
7
Jumper
J9E3
J9E2
J9E1
LED
CR9E1
CR9E2
CR9E3
Clocks
The development board supports both Integrated and Buffered clocking modes. By
default, the board’s system clocks are provided by the CK505 (EU6V1) clock
synthesizer (Buffered mode).
The BCLK frequency can be set by stuffing/unstuffing the resistor pairs R6F25 and
R6F26, R6F27 and R6F22 and R6G1 and setting the jumper J6G1.
For the board, the default clock frequency must be 100 MHz and hence the required
configuration is to set the jumper J6G1 to 1-X.
CPUSTP# is not supported as this clock must always be running during buffered mode.
The clocks on the board are provided by the PCH, which uses clocks from CK505 as
inputs in Buffered-through mode. These inputs are used as a reference to generate all
the other platform clocks.
Overclocking is not supported during Buffered-through mode.
Fully integrated clocking mode: For FCIM, the CK505 can be unstuffed and PCH
provides all clocks. A general block diagram is shown in Figure 8.
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Figure 9. Clock (Integrated Mode) Block Diagram
NOTE: Buffered-through mode, in which CK505 sources all platform clocks, is not supported in
the 2nd Generation Intel® Core™ processor family and Intel® 6 Series Chipset platform.
3.2.12.3
CPU_ITP Clock and XDP Clock
The clock configuration for the clock to XDP and the clock for top-side probing
(GDXC connected to CPU_ITP pins of the processor) is SRC8 from CPT with FCIM
(Fully Integrated Clocking Mode).
The development board has certain back-up stuffing options for Buffered-through
mode. The following figures and tables present the various options.
Figure 10. Block Diagram of GDXC and XDP Clock on the Development Board
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Some of the initial Emerald Lake boards have by default the following configuration.
Pre Power
On-boards
Stuffed by default
Unstuffed by default
XDP
(1) - R6W1, R6W4
(2)- R6W2, R6W5
ITP
(3)- R6W3, R6W6
Option for (*) resistor between
R6W2.1 and R6W3.2
Reworks required for FCIM support related to ITP and XDP clock.
Post Power
On-boards
STUFF
UNSTUFF
XDP- default
(2) - R6W2, R6W5
(1)- R6W1, R6W4
ITP
(*) resistor between R6W2.1 and R6W3.2
(3)- R6W3, R6W6
Figure 11. Layout Snapshot for Reworks for GDXC and XDP Clock Options On-Board
3.2.13
Real Time Clock
An on-board battery at BT5G1 maintains power to the real time clock (RTC) when in a
mechanical off state. A CR2032 battery is installed on the board.
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3.3
Debug Interfaces
3.3.1
Processor and PCH Debug
An XDP (Extended Debug Port) connector is provided at J1C1 for processor run control
debug support. A port 80-83 display add-in card can also be used for debug. The port
80-83 add-in card can be used on the TPM header located at J9A1.
The XDP interface is backwards compatible with the ITP interface. The ITP tools from
ITP 3.0 onwards are supported. Only JTAG and BPM support is available through ITP;
no others hooks are available.
An XDP Connector is also provided at J8H3, for PCH debug support.
3.4
Chassis
The development board form factor is compliant to the full-size ATX specification and
uses a 10-layer board  12” x 9.6”.
3.5
Power Supply Solutions, Usage, and
Recommendations
3.5.1
Power Supply Solutions
The development board can be powered from three different power sources: an ATX
power supply, an AC/DC switching power supply or ‘Mobile Brick’, or up to two
external batteries. The board contains all of the voltage regulators necessary to power
up the system. There are two main supported power supply configurations, Desktop
and Mobile. The Desktop solution consists of only using the ATX power supply. The
Mobile solution consists of using the Intel Adaptive Mobile Power Systems AC brick in
conjunction with the batteries. When the Mobile solution is being used either AC brick
or batteries can be plugged in. When both AC brick and the batteries are connected at
the same time, the batteries are monitored and charged if necessary.
Note: Desktop hard drives and cards can only be used with ATX.
Please use an “ATX12V” 1.1 specification-compliant power supply regardless of vendor
or wattage level (an "ATX12V" rating means V5 min current =0.1 A, "ATX" V5 min
current = 1.0 A, among other differences). For example, the Sparkle Model No.
FSP300-60BTVS* meets this requirement and is an ATX12V 1.1 specificationcompliant power supply.
The board uses the iAMPS (Intel® Adaptive Mobile Power System) solution for AC
brick. For more details, please see the Intel® Adaptive Mobile Power System (Intel®
AMPS) Application Note (document number 348456).
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Note: If the power button on the ATX power supply is used to shut down the system, please
wait at least five seconds before turning the system on again. It is not recommended
to shut down the system this way.
3.5.2
Power Supply Usage and Recommendation
Do not use non-Sparkle ATX power supplies. Only use Sparkle ATX desktop power
supplies.
Recommended power 20-pin ATX power supplies include:
•
Sparkle Model No. FSP300-60BTVS meets this requirement and is an ATX12V
1.1 specification-compliant.
The following 20-pin ATX power supplies may also work if you can't acquire the above
model. Lower-power power supplies may be preferred.
•
Sparkle (SPI) Model No. FSP250-60BT, FSB300-60BT, FSB300-60BTV,
FSP350, FSP40060GN (these supplies have proven successful, although are not
checked against specification).
DO NOT use Delta or Power Man ATX supplies. You may experience the following
symptoms when using a non-Sparkle supply:
•
00 POST Code
•
Blue screen indicating driver or device issue when using a desktop PCI graphics
card
•
Hanging during boot with PEG or PCI graphics
•
PCI video only during boot, but not available afterwards in Windows
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3.6
Power Management
3.6.1
Power Management States
Table 16 lists the power management states that have been defined for the
development board. The board Controller Link (CL) operates at various power levels,
called M-states.
Table 16. Development Board Power Management States
State
Description
G0/S0/C0
System Up and Running
G0/S0/C3
CPU Deep Sleep
G1/S3
Suspend To RAM (all switched rails are turned off)
G1/S4
Suspend To Disk
G2/S5
Soft Off
DSW
G3
†
Deep Sleep
Mechanical Off
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Development Board Summary
4
Development Board Summary
4.1
Features
The following figures show the major components of the development board, and
Table 17 gives a brief description of each component.
Figure 12. Development Board Components – Top View
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Development Board Summary
Table 17. Development Board Components List - Top View
Item#
Description
Reference Designator
1
TPM header
J9A1
2
Docking connector
J9C1
3
DDI connector
J8C2
4a
PCIe slot3
J7C1
4b
PCIe slot4
J7D2
5
PCIe slot5
J6C1
6a
PCIe slot1
J6C2
6b
PCIe slot2
J6D2
7
PEG slot
J5C1
8
CPU
U3E1
9
IMVP VR
EU1B1
10
CPU XDP
J1C1
11
Power on switch
SW1E1
12
Reset switch
SW1E2
13
Power Jack
J1F2
14a
Battery B
J1H1
14b
Battery A
J1H2
15a
eSATA (port4)
J7J1
15b
eSATA (port3)
J6J1
16
SATA (direct connect-port0)
J8J1
17
Embedded Controller
U9G4
18
SATA ODD
J9E7
19
LPC slot
J8F2
20
LVDS connector
J7D3
21
PCH
U7F1
22
PCH XDP
J8H3
23
USB2.0 FPIO headers
J7H5, J7H6, J7H2, J8H2
24
SATA cable connect (port1)
J7G1
25
ATX Power
J5H2
26
RTC battery
BT5G1
27
eDP connector
J4E1
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Development Board Summary
Figure 13. Development Board Components - Bottom View
Table 18. Development Board Components List - Bottom View
Item
Description
Ref Des
1
LAN PHY
EU7M1
2
Display Mini PCIe connector
J7M1
3
DDR Channel A
J4U1
4
DDR Channel B
J4V1
2
5
I C Hub
U1W1
6
DDR3 VR
EU3W1
7
CK505
EU6V1
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Development Board Summary
4.2
Connectors
This section describes the board connectors.
CAUTION:
4.2.1
Many of the connectors provide operating voltage (+5 V DC and +12 V DC, for
example) to devices inside the computer chassis, such as fans and internal
peripherals. Most of these connectors are not overcurrent protected. Do not use
these connectors for powering devices external to the computer chassis. A fault in
the load presented by the external devices could cause damage to the computer,
the interconnecting cable, and the external devices themselves.
Back Panel Connectors
Figure 13 shows the back panel connectors on the board.
Figure 14. Back Panel Connectors
Table 19. Back Panel Connectors
Item
Description
Reference
Designator
1
Display Port with dual USB2.0
J5A1
2
RJ-45 with dual USB Ports
J4A1
3
Dual-stack USB2.0
J3A2
4
HDMI connector
J3A1
5
Reserved (NO-STUFF by default)
6
CRT RS-232
J1A2
7
PS/2 - Mouse on Top
J1A1
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Development Board Summary
4.3
Configuration Settings
4.3.1
Configuration Jumpers/Switches
CAUTION: Do not move jumpers with the power on. To avoid damaging the
development board, always turn off the power and unplug the power cord from the
computer before changing jumper settings.
Table 20. Configuration Jumper/Switches
Reference
Default Setting
Comments
J4B1
(1-2)
ON BOARD DDR3 THERMAL SENSOR
10
J4B3
(1-2)
ON BOARD DDR3 THERMAL SENSOR
10
J1E1
(1-X)
DISPLAY PORT PRESENCE
12
J1J1
(2-3)
PM_EXTTS CONTROLLER
13
J5F2
(1-X)
SRTC RST#
19
J5F3
(1-X)
RTC RST#
19
J9F4
(1-2)
RST SEL FOR PCIe Graphics
17
J8D3
(2-3)
LVDS/EDP VDD EN
18
J8D2
(1-X)
FLASH DESCRIPTOR OVERRIDE+___
19
J9G4
(1-X)
NO REBOOT
19
J6D1
(1-X)
MPC SWITCH CONTROL
23
J8E2
(1-X)
Test Detect
24
J8E3
(1-X)
TEST SETUP
24
J9F3
(1-X)
S_GPIO
24
J8G1
(1-X)
BIOS RECOVERY
24
J9F5
(1-X)
ICC ENABLE
24
J7D1
(2-3)
PCIe SLOT4 POWER CONTROL
38
J7B2
(2-3)
PCIe SLOT 3 POWER CONTROL
38
J9H5
(1-2)
SATA PORT 0 DEVICE STATUS
39
J9H3
(1-2)
E-SATA (PORT 4) DEVICE STATUS
39
J7H1
(1-2)
SATA HOT PLUG REMOVAL DEFAULT
40
J8C4
(1-X)
SPI PROGRAMMING
45
J8C5
(1-X)
SPI PROGRAMMING
45
J8D1
All Open
SPI PROGRAMMING
45
J6G1
(1-X)
BCLK FREQUENCY SELECTION
46
J8C3
(1-2)
SIO RESET
48
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March 2011
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Development Board Summary
Reference
Default Setting
Comments
PG
J9E10
(1-X)
RS232 PORT FOR EC FIRMWARE
DEBUG
49
J8C6
(1-2)
IN CKT H8 PROGRAMMING
49
J8C7
(1-2)
IN CKT H8 PROGRAMMING
49
J8G5
(1-2)
H8 MODE SELECTION
50
J8G4
(1-X)
H8 MODE SELECTION
50
J9F7
(1-X)
SMC/KSC RST
50
J9F6
(1-X)
THERM STRAP
50
J9F2
(1-X)
KBC CORE DEBUG
50
J9E1
(1-X)
BIOS SELECT 0
51
J9E2
(1-X)
BIOS SELECT 1
51
J9E3
(1-X)
BIOS SELECT 2
51
J9H1
(1-2)
Vaux SELECT
51
J9H4
(1-X)
SMC LID
51
J9H2
(1-X)
VIRTUAL BATTERY
51
J9G1
(1-2)
BOOT BLOCK PROGRAMING
52
J6G2
(1-2)
VCCP VR
59
J5C5*
(2-3)
SA VR
61
J1B2
(1-X)
IMVP7 VR ENABLE
64
J5G3
(1-X)
G3 SUPPORT
70
J1E4
(1-X)
FORCE POWER UP VBAT
70
J1F1
(1-X)
FORCE SHUT DOWN
70
A jumper consists of two or more pins mounted on the motherboard. When a jumper
cap is placed over two pins, it is designated as 1-2. When there are more than two
pins on the jumper, the pins to be shorted are indicated as 1-2 (to short pin 1 to pin
2), or 2-3 (to short pin 2 to pin 3). When no jumper cap is to be placed on the
jumper, it is designated as 1-X.
4.4
Power On and Reset Button
The development board has two push-buttons, POWER and RESET. The POWER button
releases power to the entire board, causing the board to boot. The RESET button
forces all systems to warm reset. The two buttons are located near the processor. The
POWER button is located at SW1E1 (see #1 in table below) and the RESET button is
located at SW1E2 (see #2 in table below).
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Development Board Summary
Table 21. Power On and Reset Button
Item#
Description
Reference Designator
1
Power Button
SW1E1
2
Reset Button
SW1E2
3
Processor
U3E1
Table 22. Other Development Board Switches
4.5
Item#
Description
Reference
Designator
Default Switch Settings
1
LID SWITCH
SW9H2
(1-2)
2
VIRTUAL DOCKING
SW9H1
(1-2)
3
VIRTUAL BATTERY
SW9H3
(1-2)
LEDs
The following LEDs provide status of various functions:
Table 23. Development Board LEDs
Function
Reference
Designator
Page# on the
Schematics for
reference
Indicates CATASTROPHIC ERROR
CR1D1
4
DSW
CR5G2
71
SYSTEM POWER GOOD
CR5H1
71
System in S5
CR5H2
71
System in S4
CR5H3
71
System in S3 COLD
CR5H4
71
System in S0
CR5H5
71
System in M0/M3
CR5H6
71
MPC ON/OFF INDICATOR LED
CR6D1
24
SATA ACTIVITY
CR7G2
19
NUM_LOCK
CR9G1
50
CAPS_LOCK
CR9G2
50
SCROLL_LOCK
CR9G3
50
BIOS_SEL0
CR9E1
47
BIOS_SEL1
CR9E2
47
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Development Board Summary
Function
BIOS_SEL2
Reference
Designator
Page# on the
Schematics for
reference
CR9E3
47
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Quick Start
5
Quick Start
This section summarizes the necessary hardware and power on instructions for the
development board.
5.1
5.2
Required Peripherals
•
Fan/heat sink combination for processor
•
DDR3 SDRAM SO-DIMM
•
ATX power supply or Mobile iAMPS AC brick
•
Keyboard, mouse
•
Hard drive
•
Hard drive cable
•
PCI or PCIe graphics if not using internal graphics
•
External display
Instructions to Flash BIOS to SPI
The development board requires a two-partition SPI image for SPI-0 and SPI-1
respectively. The Descriptors sit on SPI-0 while the BIOS on SPI-1.
1. Remove all the power supplies to the board.
2. Connect the Dedi-Prog SF100 at J8E1.
3. Set jumpers J8C4 and J8C5 at 1-2.
4. Set jumper J8D1 at 1-2 for SPI-0 and flash the .bin image corresponding to
SPI-0.
5. Set the jumper J8D1 at 2-3 for SPI-1 and flash the .bin image corresponding
to SPI-1.
6. Once the programming is successful on the SPI, set J8C4, J8C5 and J8D1 at
1-X
7. Remove the Dedi-Prog connector.
5.3
H8 Programming
The microcontroller firmware for system management/keyboard/mouse control can be
upgraded in two ways. The user can either use a special DOS* utility (in-circuit) or
use an external computer connected (remote) to the system via the serial port on the
board.
•
If the user chooses to use an external computer connected to the system via the
serial port, there are three jumpers that must first be set correctly. Please refer to
Table 20 for a summary of these jumpers.
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Required Hardware: One Null Modem Cable and a Host Unit with a serial COM port
(system used to flash the SUT).
Here is the sequence of events necessary to program the H8.
1. Extract all files (keep them in the same folder) to a single directory of your
choice on the host machine or on a floppy disk (recommended).
2. Connect a NULL modem cable to the serial ports of each platform (host and
unit to be flashed).
3. Boot host in DOS mode.
4. Set the jumpers on the board per Table 20.
5. Power on the board and press the PWR button.
6. From the host directory where you extracted the files, run the following
command line:
KSCFLAxx ksc.bin / Remote
where xx refers KSC flash utility version number.
7. This file will program ksc.bin to the KSC flash memory through the remote
(Null modem cable).
8. Follow the instructions provided by the flash utility.
9. After successful programming of the KSC, switch-off board power and move
all three jumpers back to their default setting. The program assumes the host
computer is using serial port 1.
Note: Make sure the board is not powered on, and the power supply is disconnected before
moving any of the jumpers.
Table 24. H8 Programming Jumpers
SMC_INITCLK
(H8 NMI)
Serial Port
(TXD)
Serial Port
(RXD)
Default
(1-2)
(1-2)
(1-2)
For KSC
programming
Open
Short pin
2 and 3
Short pin
2 and 3
J9G1
J8C6
J8C7
Signals
Jumper
Setting
Jumper ID #
5.4
Key Jumpers
The jumpers used for programming SPI and H8 are indicated in Figure 14.
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Quick Start
Figure 15. Jumpers for Programming SPI and H8
The jumper pins that need to be shorted by default are:
Table 25. Key Jumpers
#
Reference
Designator
10
J4B1
ON BOARD DDR3 THERMAL SENSOR
(1-2)
11
J4B3
ON BOARD DDR3 THERMAL SENSOR
(1-2)
12
J1J1
PM EXTTS CONTROLLER
(2-3)
13
J7D1
PCIe SLOT4 POWER CONTROL
(2-3)
14
J7B2
PCIe SLOT 3 POWER CONTROL
(2-3)
15
J9H3
SATA DEVICE STATUS (PORT 4)
(1-2)
16
J9H5
SATA DEVICE STATUS (PORT 0)
(1-2)
Description
Default Setting
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Quick Start
#
Reference
Designator
17
J7H1
18
J8C3
19
J8C6
IN CKT H8 PROGRAMMING
(1-2)
20
J8C7
IN CKT H8 PROGRAMMING
(1-2)
21
J8G5
H8 MODE SELECTION
(1-2)
22
J9H1
23
J6G2
VCCP VR VOLTAGE SELECT
(1-2)
24
J9G1
BOOT BLOCK PROGRAMING
(1-2)
25
J5C5
SA VR
(2-3)
26
J9F4
RST SEL
(1-2)
27
J8D3
LVDS EN
(2-3)
28
J1C6
SVID DATA (CPU, VR)
(1-2)
29
J1D3
SVID CLK (CPU, VR)
(1-2)
30
J1D7
SVID ALERT (CPU, VR)
(1-2)
Description
SATA HOT PLUG
Default Setting
(1-2)
SIO RESET
(1-2)
VAUX SELECT
(1-2)
NOTE: Ensure proper jumper settings before powering-up the board. Please refer to Table 20
for a complete list of jumper settings.
§
2nd Generation Intel® Core™ Processor with Intel® 6 Series Chipset Development Kit
March 2011
User Guide
Document Number: 325208-001
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