AMD K86 Family BIOS and Software Tools Developers

AMD ~
AMD K86™
Family BIOS and Software Tools
Developers Guide
Preliminary Information
AMD K86 Family BIOS
and
Software Tools Developers
Guide
lM
AMD~
Preliminary Information
© 1997 Advanced Micro Devices, Inc. All rights reserved.
Advanced Micro Devices, Inc. ("AMD") reserves the right to make changes in its
products without notice in order to improve design or performance characteristics.
The information in this publication is believed to be accurate at the time of
publication, but AMD makes no representations or warranties with respect to the
accuracy or completeness of the contents of this publication or the information
contained herein, and reserves the right to make changes at any time, without
notice. AMD disclaims responsibility for any consequences resulting from the use
of the information included in this publication.
This publication neither states nor implies any representations or warranties of
any kind, including but not limited to, any implied warranty of merchantability or
fitness for a particular purpose. AMD products are not authorized for use as critical
components in life support devices or systems without AMD's written approval.
AMD assumes no liability whatsoever for claims associated with the sale or use
(including the use of engineering samples) of AMD products except as provided in
AMD's Terms and Conditions of Sale for such product.
Trademarks
AMD, the AMD logo, and the combinations thereof are trademarks of Advanced Micro Devices, Inc.
Am386, Am486, and RISC86 are registered trademarks; K86, AMD·K5, AMD·K6, and the AMD·K6 logo are
trademarks of Advanced Micro Devices, Inc.
MMX is a trademark and Pentium is a registered trademark of the Intel Corporation.
Other product names used in this publication are for identification purposes only and may be trademarks of their
respective companies.
Preliminary Information
AMDl1
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO-June 1997
Contents
1
Introduction
1
Audience ................................................. 1
2
CPU Identification Algorithms
3
3
AMD-KSTM Processor
5
BIOS Consideration Checklist ................................ 5
CPUID ................................................... 5
CPU Speed Detection ............... ',' ...... , ............... 6
Model-Specific Registers (MSRs) ............................. 6
Cache Testing ............................................. 6
SMM Issues ............................................... 6
AMD-KS Processor System Management Mode (SMM) ........... 7
Operating Mode and Default Register Values ................... 7
SMM Initial Register Values ................................. 9
SMM State-Save Area ....................................... 9
SMM Revision Identifier ................................... 12
SMM Base Address ........................................ 12
Auto Halt Restart Slot ..................................... 13
I/O Trap Dword ........................................... 14
I/O Trap Restart Slot ....................................... 14
Exceptions and Interrupts in SMM ........................... 16
AMD-KS Processor RESET State ............................. 18
Segment Register Attributes ................................ 20
State of the AMD-KS Processor After INIT .................... 20
AMD-KS Processor Test and Debug .......................... 21
Hardware Configuration Register (HWCR) .................... 22
Built-In Self-Test (BIST) .................................... 24
Normal BIST ........................................ 25
Test Access Port (TAP) BIST .......................... 26
Output-Float Test ......................................... 26
Contents
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Preliminllry Informlltion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E!O- June 1997
Cache and TLB Testing ..................................... 27
Array Access Register (AAR) ......................... 28
Array Pointer ....................................... 28
Array Test Data ..................................... 29
Debug Registers .......................................... 38
Standard Debug Functions ............................ 38
I/O Breakpoint Extension.· ............................ 38
Debug Compatibility with the Pentium Processor ......... 39
Branch Tracing ........................................... 39
Functional-Redundancy Checking ........................... 40
Boundary Scan Architecture Support ......................... 41
Boundary Scan Test Functional Description ............. 42
Boundary Scan Architecture .......................... 42
Registers ........................................... 43
JTAG Register Organization .......................... 44
Public Instructions .................................. 45
Hardware Debug Tool (HDT) ................................ 57
AMD-K5 Processor x86 Architecture Extensions ............... 57
Additions to the EFLAGS Register ........................... 58
Control Register 4 (CR4) Extensions ......................... 58
Machine-Check Exceptions ........................... 60
4-Mbyte Pages ...................................... 60
Global Pages ....................................... 65
Virtual-8086 Mode Extensions (VME) .................. 67
Protected Virtual Interrupt (PVI) Extensions ............ 79
Model-Specific Registers (MSRs) ............................ 79
Machine-Check Address Register (MCAR) .............. 80
Machine-Check Type Register (MCTR) ................. 80
Time Stamp Counter (TSC) ........................... 81
Array Access Register (AAR) ......................... 82
Hardware Configuration Register (HWCR) .............. 82
Write Allocate Registers ............................. 82
Enable Write Allocate ..................................... 85
New AMD-K5 Processor Instructions ......................... 85
CPUID ................................................... 86
CMPXCHG8B ............................................. 87
MOV to and from CR4 ..................................... 88
RDTSC .................................................. 89
RDMSR and WRMSR ...................................... 90
RSM .................................................... 92
illegal Instruction (Reserved Opcode) ........................ 93
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AMD KB6™ Family BIOS and Software Tools Developers Guide
AMO-K6™ MM)(TM Enhanced Processor
95
BIOS Consideration Checklist ............................... 95
CPUID .................................................. 95
CPU Speed Detection ...................................... 96
Model-Specific Registers (MSRs) ............................ 96
Cache Testing ............................................ 96
SMM Issues .............................................. 96
AMD-K6 Processor System Management Mode ................. 97
Initial Register Values ..................................... 97
SMM State-Save Area ...................................... 98
SMM Revision Identifier .................................. 100
SMM Base Address ....................................... 100
Auto Halt Restart ........................................ 101
IJO Trap Dword .......................................... 101
IJO Trap Restart ......................................... 101
Exceptions and Interrupts Within SMM ...................... 101
AMD-K6 Processor Reset State ............................. 102
Segment Register Attributes ............................... 103
State of the AMD-K6 Processor After INIT ................... 104
AMD-K6 Processor Cache .................................. 104
AMD-K6 Processor Test and Debug ......................... 105
Built-In Self-Test (BIST) ................................... 106
Tri-State Test Mode ...................................... 106
Boundary-Scan Test Access Port (TAP) ...................... 107
TAP Registers ..................................... 107
TAP Instructions ................................... 111
Ll Cache Inhibit ......................................... 112
Purpose ........................................... 112
Debug .................................................. 113
Debug Registers ................................... 113
AMD-K6 Processor x86 Architecture Extensions .............. 117
Model-Specific Registers (MSR) ............................ 117
Machine-Check Address Register (MCAR) ............. 117
Machine-Check Type Register (MCTR) ................ 117
Test Register 12 (TR12) ............................. 118
Time Stamp Counter (TSC) .......................... 118
Contents
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AMD K86™ Family BIOS and Software Tools Developers Guide
21062E!O-June 1997
Extended Feature Enable Register (EFER) ............. 118
SYSCALL Target Address Register (STAR) ............ 118
Write Handling Control Register (WHCR) .............. 119
Machine Check Exception ................................. 122
New AMD-K6 Processor Instructions ........................ 122
System Call Extensions ................................... 122
SYSCALL ............................................... 123
SYSRET ................................................ 125
MMXTM Instructions ...................................... 127
Index
vi
129
Contents
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
List of Figures
SMM Memory ......................................... 8
Hardware Configuration Register (HWCR) ............... 23
Array Access Register (AAR) .., ......................... 28
Test Formats: Dcache Tags for the AMD-K5 Processor
Model 0 ............................................. 30
Test Formats: Dcache Tags for the AMD-K5 Processor
Modell and Greater .................................. 31
Test Formats: Dcache Data for All Models of
the AMD-K5 Processor ................................. 32
Test Formats: Icache Tags for the AMD-K5 Processor
Model 0 ............................................. 33
Test Formats: Icache Tags for the AMD-K5 Processor
Modell and Greater .................................. 34
Test Formats: Icache Instructions for the AMD-K5 Processor
Model 0 ............................................. 35
Test Formats: Icache Instructions for the AMD-K5 Processor
Modell and Greater .................................. 35
Test Formats: 4-Kbyte TLB for All Models of
the AMD-K5 Processor ................................. 36
Test Formats: 4-Mbyte TLB for All Models of
the AMD-K5 Processor ................................. 37
Control Register 4 (CR4) ............................... 58
4-Kbyte Paging Mechanism ............................. 61
4-Mbyte Paging Mechanism ............................ 62
Page-Directory Entry (PDE) ............................ 63
Page-Table Entry (PTE) ................................ 66
EFLAGS Register ..................................... 70
Task State Segment (TSS) .............................. 77
Machine-Check Address Register (MCAR) ................ 80
Machine-Check Type Register (MCTR) ................... 81
Write Allocate Top-of-Memory and Control Register
(WATMCR)-MSR 85h ................................ 84
Write Allocate Programmable Memory Range Register
(WAPMRR)-MSR 86h ................................. 84
Debug Register DR7 ................................. 114
Debug Register DR6 ................................. 115
Debug Registers DRS and DR4 ......................... 115
Debug Registers DR3, DR2, DR1, and DRO ............... 116
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AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Figure 28. Extended Feature Enable Register (EFER) .............. 118
Figure 29. SYSCALL Target Address Register (STAR) .............. 119
Figure 30. Write Handling Control Register (WHCR)MSR COOO_0082h .................................... 120
viii
List of Figures
Preliminary Information
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
List of Tables
Summary of AMD-K5 Processor CPU IDs and
BIOS Boot Strings ...................................... 4
Summary of AMD-K6 MMX Enhanced Processor CPU IDs and
BIOS Boot Strings ...................................... 4
Initial State of Registers in SMM ......................... 9
SMM State-Save Area Map ............................. 10
SMM Revision Identifier Fields ......................... 12
IJO Trap Dword Fields ................................. 14
IJO Trap Restart Slot .................................. 15
Summary of Interrupts and Exceptions ................... 17
State of the AMD-K5 Processor After RESET .............. 18
Segment Register Attribute Fields Initial Values .......... 20
Hardware Configuration Register (HWCR) Fields .......... 23
BIST Error Bit Definition in EAX Register ................ 25
Array IDs in Array Pointers ............................ 29
Branch-Trace Message Special Bus Cycle Fields ........... 39
AMD-K5 Processor Device Identification Register ......... 45
Public TAP Instructions ................................ 46
Control Bit Definitions ................................. 49
Boundary Scan Register Bit Definitions .................. 49
Control Register 4 (CR4) Fields ......................... 59
Page-Directory Entry (PDE) Fields ...................... 64
Page-Table Entry (PTE) Fields .......................... 66
Virtual-Interrupt Additions to EFLAGS Register .......... 71
Instructions that Modify the IF or VIF Flags-Real Mode ... 71
Instructions that Modify the IF or VIF Flags-Protected
Mode ............................................... 72
Instructions that Modify the IF or VIF Flags-Virtual-8086
Mode ............................................... 73
Instructions that Modify the IF or VIF Flags-Virtual-8086
Mode Interrupt Extensions (VME) ....................... 74
Instructions that Modify the IF or VIF Flags-Protected
Mode Virtual Interrupt Extensions (PVI) ................. 75
Interrupt Behavior and Interrupt-Table Access ............ 78
Machine-Check Type Register (MCTR) Fields ............. 81
Initial State of Registers in SMM ........................ 97
AMD-K6 Processor State-Save Map ...................... 98
SMM Revision Identifier .............................. 100
AMD-K6 Processor IJO Trap Dword Configuration ......... 101
State of the AMD-K6 Processor After RESET ............. 102
Data Returned by the CPUID Instruction ................ 105
Boundary Scan Register Bit Definitions ................. 109
AMD-K6 Processor Device Identification Register ........ 110
ix
AMD 11
Pre/iminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
x
21 062E/O-June 1997
Supported TAP Instructions ........................... 111
DR7 LEN and RW Definitions ......................... 114
Extended Feature Enable Register (EFER) Definition ..... 118
SYSCALL Target Address Register (STAR) Definition ..... 119
MMX Instructions and Descriptions ..................... 127
List of Tables
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E,10- June 1997
Revision History
Date
Rev
Sept 1996
A
Initial Release
Mar 1997
B
Added write allocation information for K86 family of processors. See "Write Allocate Registers" on
page 82 for information about the AMD-K5 processor and "Write Handling Control Register
(WHCR)" on page 119 for information about the AMD-K6™ MM)(lM enhanced processor.
Mar 1997
B
Added Test and Debug section for the AMD-K6 MMX enhanced processor. See ''AMD-K6™ Processor Test and Debug" on page 105 for more information.
Mar 1997
C Reorganized entire guide
Apr 1997
D
Changed BIOS boot string for the AMD-K6 processor in Table 2, "Summary of AMD-K6n.t MMXTM
Enhanced Processor CPU IDs and BIOS Boot Strings," on page 4.
June 1997
E
Revised document to comply with MMX trademark.
June 1997
E Replaced overbar with # to identify active-low signals.
June 1997
E Revised information in "Write Handling Control Register (WHCR)" on pages 119 through 121.
June 1997
E
Revision History
Description
Added (tm) to recommended boot-string for the AMD-K6 MMX enhanced processor on pages 3, 4,
and 95.
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Pre/iminDry InformDtion
AMD K86™ Family BIOS and Software Tools Developers Guide
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Revision History
Preliminary Information
21062E/O- June 1997
AMD l1
AMD K86™ Family BIOS and Software Tools Developers Guide
1
Introduction
This document highlights the BIOS and software modifications
required to fully support the K86™ family of processors, which
includes the AMD-KSTM processor and the AMD-K6™ MMXTM
enhanced processor.
There can be more than one way to implement the functionality
detailed in this document, and the information provided is for
demonstration purposes.
Audience
It is assumed that the reader possesses the proper knowledge of
the K86 processors, the x86 architecture, and programming
requirements to understand the information presented in this
document.
Introduction
1
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Pre/iminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
2
21062E/O-June 1997
Introduction
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
2
CPU Identification
Algorithms
The CPUID instruction provides complete information about
the processor (vendor, type, name, etc.) and its capabilities
(features). After detecting the processor and its capabilities,
software can be accurately tuned to the system for maximum
performance and benefit to users. For example, game software
can test the performance level available from a particular
processor by detecting the type or speed of the processor. If the
performance level is high enough, the software can enable
additional capabilities or more advanced algorithms. Another
example involves testing whether the processor supports
MMXTM technology. If the software finds this feature present
when it checks the feature bits, it can utilize these more
powerful instructions for better performance on new
multimedia software.
For more detailed information refer to the AMD Processor
Recognition Application Note, order# #20734, located at
http://www.amd.com
Tables 1 and 2 outline the family codes and model codes for the
AMD K86 processors. Table 1 shows the CPU speed, the
'P-Rating', and the recommended BIOS boot-string associated
with each AMD-KS processor.
Table 2 shows the recommended BIOS boot-string for the
AMD-K6 MMX enhanced processor. This recommended
boot-string is 'AMD-K6(tm)/XXX'. The value for XXX is
CPU Identification Algorithms
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Preliminary Information
AMD K86™Family BIOS and Software Tools Developers Guide
21 062EjO-June 1997
determined by calculating the core frequency of the processor.
Use the Time Stamp Counter (TSC) to 'clock' a timed operation
and compare the result to the Real Time Clock (RTC) to
determine the operating frequency.
Note: Tables 1 and 2 contain information intended to prepare the
infrastructure for potential future products. These products
mayor may not be announced, but BIOS software should be
prepared to support these options.
Table 1.
Summary of AMD-K5™ Processor CPU IDs and BIOS Boot Strings
Instruction
Family Code
Model CPU Speed
(MHz)
Code
CPU Bus
Speed
(MHz)
75
0
5
(AMD-K5™ Processor)
1
2
3
Table 2.
AMD-K5-PR75
CPUID Functions 8000_0002, 3, 4
Return Values
undefined
90
60
AMD-K5-PR90
undefined
100
66
AMD-K5-PR 100
undefined
90
60
AMD-K5-PR 120
AMD-K5(tm) Processor
100
66
AMD-K5-PR133
AMD-K5(tm) Processor
105
60
AMD-K5-PR 150
AMD-K5(tm) Processor
116.7
66
AMD-K5-PR 166
AMD-K5(tm) Processor
133
66
AMD-K5-PR200
AMD-K5(tm) Processor
Summary of AMD-K6™ MM)(TM Enhanced Processor CPU IDs and BIOS Boot Strings
Instruction
Family Code
CPU CPU Bus
Model
Speed Speed
Code
(MHz) (MHz)
5
(AMD-K6™ MM)(TM
Enhanced Processor)
4
50
Recommended
BIOS Boot-String
6
Recommended BIOS Boot-String Display
TBD
60
AMD-K6(tm)/XXX
TBD
66
AMD-K6(tm)/XXX
CPU Identification Algorithms
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
3
AMD-KSTM
Processor
The AMD-K5 processor is socket 7-compatible and
software-compatible with the Pentium® processor. Compatible
in this sense means the devices are pin-for-pin compatible and
that the same software can be executed on both processors with
no software modifications.
The BIOS for the AMD-K5 processor requires minimal changes
to fully support the AMD-K5 processor family.
BIOS Consideration Checklist
CPUID
•
•
•
AMD-K5™ Processor
Use the CPUID instruction to properly identify the AMD-K5
processor.
Determine the processor type, stepping and features using
functions OOOO_OOOlh and 8000_0001h of the CPUID
instruction.
Boot-up display: The processor name is retrieved using
CPUID extended functions 8000_0002h, 8000_0003h, and
8000_0004h. See "CPU Identification Algorithms" on page 3
for more information.
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Pre/iminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
CPU Speed Detection
•
•
•
Use speed detection algorithms that do not rely on
repetitive instruction sequences.
Use the Time Stamp Counter (TSC) to 'clock' a timed
operation and compare the result to the Real Time Clock
(RTC) to determine the operating frequency. See the
example of frequency-determination assembler code
available on the AMD website at http://www.amd.com.
Display the P-Rating shown in Table 1, "Summary of
AMD-KSTM Processor CPU IDs and BIOS Boot Strings," on
page 4.
Model-Specific Registers (MSRs)
•
•
Access only MSRs implemented in the AMD-KS processor.
Program
the
write
allocate
registers-Hardware
Configuration
Register
(HWCR),
Write
Allocate
Top-of-Memory and Control Register (WATMCR), and Write
Allocate
Programmable
Memory
Range
Register
(WAPMRR). See "Write Allocate Registers" on page 82 and
the Implementation of Write Allocate in the K86fM Processors
Application Note, order# 21326 for more information.
•
Perform cache testing on the AMD-KS processor using the
Array Access Register MSR. See" Array Access Register
(AAR)" on page 28 for more information.
•
The System Management Mode (SMM) functionality of the
AMD-KS processor is identical to Pentium.
Implement the AMD-KS processor SMM state-save area in
the same manner as Pentium except for the IDT Base and
possibly Pentium processor-reserved areas. See "AMD_KSTM
Processor System Management Mode (SMM)" on page 7 for
more information.
Cache Testing
SMM Issues
•
6
AMD-K5™ Processor
Preliminary Information
AMD l1
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
AMD-KSTM Processor System Management Mode (SMM)
System Management Mode (SMM) is an alternate operating
mode entered by way of a system management interrupt (SMI)
and handled by an interrupt service routine. SMM is designed
for system control activities such as power management. These
activities appear transparent to conventional operating
systems like DOS and Windows. SMM is primarily targeted for
use by the Basic Input Output System (BIOS) and specialized
low-level device drivers. The code and data for SMM are stored
in the SMM memory area, which is isolated from main memory.
The processor enters SMM by the system logic's assertion of the
SMI# interrupt and the processor's acknowledgment by the
assertion of SMIACT#. At this point the processor saves its
state into the SMM memory state-save area and jumps to the
SMM service routine. The processor returns from SMM when it
executes the RSM (resume) instruction from within the SMM
service routine. Subsequently, the processor restores its state
from the SMM save area, de-asserts SMIACT#, and resumes
execution with the instruction following the point where it
entered SMM.
The following sections summarize the SMM state-save area,
entry into and exit from SMM, exceptions and interrupts in
SMM, memory allocation and addressing in SMM, and the SMI#
and SMIACT# signals.
Operating Mode and Default Register Values
The software environment within SMM has the following
characteristics:
•
•
•
•
•
AMD-K5™ Processor
Addressing and operation in Real mode
4-Gbyte segment limits
Default 16-bit operand, address, and stack sizes, although
instruction prefixes can override these defaults
Control transfers that do not override the default operand
size truncate the EIP to 16 bits
Far jumps or calls cannot transfer control to a segment with
a base address requiring more than 20 bits, as in Real mode
segment-base addressing
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Preliminory Infonnotion
AMD K86™ Family BIOS and Software Tools Developers Guide
•
•
•
•
•
•
21 062EjO- June 1997
A20M# is masked
Interrupt vectors use the Real-mode interrupt vector table
The IF flag in EFLAGS is cleared (INTR not recognized)
The TF flag in EFLAGS is cleared
The NMI and INIT interrupts are disabled
Debug register DR7 is cleared (debug traps disabled)
Figure 1 shows the default map of the SMM memory area. It
consists of a 64-Kbyte area, between 0003_0000h and
0003_FFFFh, of which the top 32 Kbytes (0003_BOOOh to
0003_FFFFh) must be populated with RAM. The default
code-segment (CS) base address for the area-called the SMM
base address-is at 0003_0000h. The top 512 bytes
(0003_FEOOh to 0003_FFFFh) contain a fill-down SMM
state-save area. The default entry point for the SMM service
routine is 0003_BOOOh.
Fill Down
~
0003JFFFh
SMM
State-Save
Area
1----------11 0003JEOOh
=
32-Kbyte
Minimum RAM
SMM
Service Routine
Service Routine Entry Point
0003_8000h
~----------
-
].ooo3-ooooh
SMM Base Address (CS) 111_________
Figure 1. SMM Memory
8
AMD-K5™ Processor
AMD l1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
SMM Initial Register Values
Table 3 shows the initial state of registers when entering SMM.
Table 3.
Initial State of Registers in SMM
Initial Contents
Register
Selector
Base
Limit
CS
3000h
0OO3_0000h
4 Gbytes
DS
OOOOh
OOOO_OOOOh
4 Gbytes
ES
ooooh
OOOO_OOOOh
4 Gbytes
FS
ooooh
OOOO_OOOOh
4 Gbytes
GS
ooooh
OOOO_OOOOh
4 Gbytes
55
OOOoh
oooo_oooOh
4 Gbytes
General-Purpose Registers
Unmodified
EFLAGS
OOOO_OOO2h
EIP
OOOO_BOOOh
CRO
Bits 0, 2, 3, and 31 cleared (PE, EM, TS, and PG); remainder are unmodified
CR4
OOOO_OOOOh
GDTR
Unmodified
LDTR
Unmodified
IDTR
Unmodified
TR
Unmodified
DR7
OOOO_0400h
DR6
Undefined
SMM State-Save Area
When the processor acknowledges an SMI interrupt by
asserting SMIACT#, it saves its state in the 512-byte SMM
state-save area shown in Table 4. The save begins at the top of
the SMM memory area (SMM Base Address + FFFFh) and fills
down to SMM base address + FEOOh.
Table 4 shows the offsets in the SMM state-save area relative to
the SMM base address. The SMM service routine can alter any
of the read and write values in the state-save area. The contents
of any reserved locations in the state-save area are not
necessarily the same between the AMD-K5 processor and
Pentium or 486 processors.
AMD-K5™ Processor
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Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
Table 4.
SMM State-Save Area Map
Offset (Hex)
Contents
FFFC
CRO
FFF8
CR3
FFF4
EFLAGS
FFFO
EIP
FFEC
EDI
FFE8
ESI
FFE4
EBP
FFEO
ESP
FFDC
EBX
FFD8
EDX
FFD4
ECX
FFDO
EAX
DR6 (FFFF_CFF3h)
FFCC
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21062E!O-June 1997
FFC8
DR7
FFC4
TR
FFCO
LDTR
FFBC
GS
FFB8
FS
FFB4
DS
FFBO
SS
FFAC
CS
FFA8
ES
FFA4
I/O Trap Dword
FFAO
reserved
FF9C
I/O Trap EIP
FF98
FF94
reserved
reserved
FF90
lOT Base
FF8C
lOT limit
FF88
GOT Base
FF84
GDT limit
FF80
TSS Attributes
FF7C
TSS Base
FF78
TSS limit
AMD-K5™ Processor
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 4.
SMM State-Save Area Map (continued)
, Offset (Hex)
FF74
Contents
LOT Attributes
FF70
LOT Base
FF6C
LOT limit
FF68
GS Attributes
FF64
GS Base
FF60
GS limit
FFSC
FS Attributes
FFS8
FS Base
FFS4
FS limit
FFSO
OS Attributes
FF4C
OS Base
FF48
OS limit
FF44
SS Attributes
FF40
SS Base
FF3C
SS limit
FF38
CS Attributes
FF34
CS Base
FF30
CS limit
FF2C
ES Attributes
FF28
ES Base
FF24
ES limit
FF20
FF18.
reserved
reserved
reserved
FFIC
FF14
CR2
FFI0
CR4
FFOC
I/O Restart ESI
I/O Restart ECX
I/O Restart EDI
FF08
FF04
AMD-KSTM Processor
AM D~
FF02
Halt Restart Slot
FFOO
I/O Trap Restart Slot
FEFC
SMM Revision Identifier
FEF8
SMM Base Address
FEOO-FEF4
reserved
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AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E!O- June 1997
SMM Revision Identifier
The SMM revision identifier at offset FEFCh in the SMM
state-save area specifies the version of SMM and the extensions
available on the processor. The SMM revision identifier fields,
shown in Table 5, are as follows:
•
•
•
•
Table 5.
Bits 31-18-reserved
Bit 17-SMM base address relocation (always 1 = enabled)
Bit 16-IJO trap restart (always 1 = enabled)
Bits 15-0-SMM revision level = 0000
SMM Revision Identifier Fields
Bits 31-18
Bit 17
Bit 16
Bits 15-0
Reserved
SMM Base Relocation
I/O Trap Extension
SMM Revision level
0
1
1
0000
Note: The I/O trap restart and the SMM base address relocation
functions are always enabled in the AMD-K5 processor and
do not need to be specifically enabled.
SMM Base Address
During RESET, the processor sets the code-segment (CS) base
address for the SMM memory area-the SMM base addressto its default, 0003_0000h. The SMM base address at offset
FEF8h in the SMM state-save area can be changed by the SMM
service routine to any address aligned to a 32-Kbyte boundary.
(Locations not aligned to a 32-Kbyte boundary cause the
processor to enter the Shutdown state when executing the RSM
instruction. )
In some operating environments it may be desirable to relocate
the 64-Kbyte SMM memory area to a high memory area to
provide more low memory for legacy software. During system
initialization, the base of the 64-Kbyte SMM memory area is
relocated by the BIOS. To relocate the SMM base address, the
system enters the SMM handler at the default address. This
handler changes the SMM base address location in the SMM
state-save area, copies the SMM handler to the new location,
and exits SMM.
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AMD-K5™ Processor
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
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The next time SMM is entered, the processor saves its state at
the new base address. This new address is used for every SMM
until the SMM base address in the SMM state-save area is
changed or a hardware reset occurs.
Auto Halt Restart Slot
During entry into SMM, the halt restart slot at offset FF02h in
the SMM state-save area indicates whether SMM was entered
from the Halt state. Before returning from SMM, the halt
restart slot can be written to by the SMM service routine to
specify whether the return from SMM should take the
processor back to the Halt state or to the instruction-execution
state specified by the SMM state-save area.
On entry into SMM, the halt restart slot is configured as
follows:
•
•
Bits 15-1-Undefined
Bit O-Point of entry to SMM:
1 = entered from Halt state
o = not entered from Halt state
After entry into the SMI handler and before returning from
SMM, the halt restart slot can be written using the following
definition:
•
•
Bits 15-1-Undefined
Bit O-Point of return from SMM
1 = return to Halt state
0= return to state specified by SMM state-save area
If the return from SMM takes the processor back to the Halt
state, the HLT instruction is not re-executed, but the Halt
special bus cycle is driven on the bus after the return.
AMD-K5™ Processor
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AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
1/0 Trap Dword
If the assertion of SM! is recognized on the boundary of an 1/0
instruction, the I/O trap dword at offset FFA4h in the SMM
state-save area contains information about the instruction. The
fields of the I/O trap dword, shown in Table 6, are configured as
follows:
Table 6.
•
•
Bits31-16-I/0 port address
Bit lS-I/O string operation (1 = string, 0 = non-string)
•
•
•
Bits 14-2-reserved
Bit 1-Valid I/O instruction (1 =valid, 0 =invalid)
Bit O-Input or output instruction (1 = INx, 0 = OUTx)
1/0 Trap Dword Fields
Bits 31-16
Bit 15
Bit 14-2
Bit 1
Bit 0
I/O Port Address
I/O String Operation
Reserved
Valid I/O Instruction
Input or Output
The I/O trap dword is related to the I/O trap restart slot,
described below. Bit 1 of the 1/0 trap dword (the valid bit)
should be tested if the I/O trap restart slot is to be changed.
1/0 Trap Restart Slot
The I/O trap restart slot at offset FFOOh in the SMM state-save
area specifies whether the trapped 1/0 instruction should be
re-executed on return from SMM. This slot in the state-save
area is called the I/O instruction restart function. Re-executing
a trapped I/O instruction is useful, for example, if an I/O write
occurs to a disk that is powered down. The system logic
monitoring such an access can assert SMI#. Then the SMM
service routine can query the system logic, detect a failed 1/0
write, take action to power-up the 1/0 device, enable the 1/0
trap restart slot feature, and return from SMM.
14
AMD-K5™ Processor
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
The fields of the I/O trap restart slot are defined as follows:
•
•
Bits 31-16-reserved
Bits lS-0-I/0 instruction restart on return from SMM:
OOOOh = execute the next instruction after the trapped
I/O instruction
OOFFh = re-execute the trapped I/O instruction
Table 7 shows the format of the I/O trap restart slot.
Table 7.
1/0 Trap Restart Slot
31-16
15-0
Reserved
I/O Instruction restart on return from SMM:
ooooh = execute the next instruction after the trapped I/O
instruction
OOFFh = re-execute the trapped I/O instruction
•
•
The processor initializes the I/O trap restart slot to OOOOh upon
entry into SMM. If SMM is entered as a result of a trapped 1/0
instruction, the processor indicates the validity of the I/O
instruction by setting or clearing bit 1 of the I/O trap dword at
offset FFA4h in the SMM state-save area. The SMM service
routine should test bit 1 of the I/O trap dword to determine if a
valid 1/0 instruction was being executed when entering SMM
and before writing the I/O trap restart slot. If the I/O instruction
is valid, the SMM service routine can safely rewrite the I/O trap
restart slot with the value OOFFh, causing the processor to
re-execute the trapped I/O instruction when the RSM
instruction is executed. If the I/O instruction is invalid, writing
the I/O trap restart slot has undefined results.
If a second SMI# is asserted and a valid 110 instruction was
trapped by the first SMM handler, the CPU services the second
SMI# prior to re-executing the trapped I/O instruction. The
second entry into SMM never has bit 1 of the I/O trap dword set,
and the second SMM service routine must not rewrite the 1/0
trap restart slot.
During a simultaneous SMI# I/O instruction trap and debug
breakpoint trap, the AMD-KS processor first responds to the
SMI# and postpones recognizing the debug exception until
after returning from SMM via the RSM instruction. If the debug
registers DR3-DRO are used while in SMM, they must be saved
AMD-K5™ Processor
15
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
and restored by the SMM handler. The processor automatically
saves and restores DR7-DR6. If the I/O trap restart slot in the
SMM state-save area contains the value OOFFh when the RSM
instruction is executed, the debug trap does not occur until
after the I/O instruction is re-executed.
Exceptions and Interrupts in SMM
When SMM is entered, the processor disables both INTR and
NMI interrupts. The processor disables INTR interrupts by
clearing the IF flag in the EFLAGS register. To enable INTR
interrupts within SMM, the SMM handler must set the IF flag to
1.
Generating an INTR interrupt is a method for unmasking NMI
interrupts in SMM. The processor recognizes the assertion of
NMI within SMM immediately after the completion of an IRET.
The NMI can thus be enabled by using a dummy INTR
interrupt. Once NMI is recognized within SMM, NMI
recognition remains enabled until SMM is exited, at which
point NMI masking is restored to the state it was in before
entering SMM.
Because the IF flag is cleared when entering SMM, the HLT
instruction should not be executed in SMM without first setting
the IF bit to 1. Setting this bit to 1 enables the processor to exit
the Halt state by means of an INTR interrupt.
Table 8 summarizes the behavior of all interrupts in SMM.
16
AMD-K5™ Processor
AM D ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
Table 8.
Summary of Interrupts and Exceptions
Priority
Description
Type
Samplings
Vector1
Acknowledgment
1
INTn instructions and all
other software
exceptions
exceptions
internal
0-255
none
Entry to service routine
2
BUSCHK#
interrupt
level-sensitive
181
none
Entry to service routine 1
3
R/S#
interrupt
level-sensitive
none
PRDY
Negation of PRDY
4
FLUSH#
interrupt
edge-triggered 4
none
FLUSH#-Acknowledge special
bus cycle
5
SMI#
interrupt
edge-triggered 4
SMM3
SMIACT#
6
INIT
interrupt
edge-triggered4
BIOS
none
Completion of
initialization
7
NMI
interrupt
edge-triggered 4
2
none
NMI interrupts: IRET from
service routine. All others:
Entry to service routine.
8
INTR
interrupt
level-sensitive
0-255
Interrupt acknowledge special
bus cycle
Entry to service routine
9
STPCLK#
interrupt
level-sensitive
none
Stop-Grant
special bus cycle
Negation of STPCLK#
Point of Interruptibilitr
BRDY# of FLUSH#
Acknowledge bus cycle
Entry to SMM service
routine
Notes:
1. For interrupts with vectors, the processor saves its state prior to accessing the service routine and changing the program flow.
Interrupts without vectors do not change program flow; instead, they simply pause program flow for the duration of the interrupt
function and return to where they left off.
2. If the Machine Check Enable (MCE) bit in CR4 is set to 1.
3. The entry point for the 5MI interrupt handler is at offset Boooh from the 5MM Base Address.
4. Only the edge-triggered interrupts are latched when asserted. All interrupts are recognized at the next instruction retirement
boundary.
5. If a bus cycle is in progress, EWBE must be asserted before the interrupt is recognized.
6. For external interrupts (most exceptions, by contrast are recognized when they occur). External interrupts are recognized at
instruction boundaries. When MOV or POP instructions load 55, interruptibility is delayed until after the next instruction, thus
allowing both 55 and the corresponding 5P to load.
1. After assertion of SMI, subsequent assertions of 5MI are masked to prevent recursive entry into SMM. However, other exceptions
or interrupts (except INIT and NMI) are taken in the 5MM service routine.
AMD-K5™ Processor
17
AMD l'4
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
AMD-KSTM Processor RESET State
The state of all architecture registers and Model-Specific
Registers (MSRs) after the AMD-K5 processor has completed
its initialization due to the recognition of the assertion of
RESET are shown in Table 9.
Table 9.
State of the AMD-K5™ Processor After RESET
Register
GDTR
IDTR
TR
LDTR
EIP
EFLAGS
EAX
EBX
ECX
EDX
ESI
EDI
EBP
ESP
CS
55
DS
ES
FS
GS
FPU Stack R7-RO
RESET State
base:OOOO_OOOO IimitoooOh
base:OOOO_OOOO limitoOOOh
OOOOh
ooooh
FFFF_FFFOh
OOOO_OOO2h
OOOO_OOOOh
OOOO_OOOOh
OOOO_OOOOh
OOOO_05XXh
OOOO_OOOOh
OOOO_OOOOh
OOOo_ooOOh
OOOO_OOOOh
FOooh
ooooh
ooooh
ooooh
ooooh
ooooh
OOOO_OOOO_OOOO_OOOO_OOOOh
Notes
1
2
Notes:
1. The contents of fAX indicate if BISTwas successful If fAX =OOOO_OOOOh, then BIST
was successful If fAX is non-zero, BIST failed
2. EDX contains the AMD-K5 processor signature, which is comprised of the instruction
family, model, and stepping.
3. These MSRs are described in ''AMD-K5™ Processor x86 Architecture Extensions" on
page 57.
4. The AMD-K5 processor supports write allocate only on Models 1, 2, and 3, with a
Stepping of 4 or greater.
18
AMD-K5™ Processor
AMD~
Preliminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E,/O-June 1997
Table 9.
State of the AMD-K5™ Processor After RESET (continued)
Register
FPU Control Word
FPU Status Word
FPU Tag Word
FPU Instruction Pointer
FPU Data Pointer
FPU Opcode Register
CRO
CRl
CR3
CR4
DR7
DR6
DR3
DRl
DRl
ORO
MCAR
MaR
TR12
TSC
AAR
HWCR
WATMCR
WAPMRR
RESET State
o04oh
ooooh
5555h
OOOO_OOOO_OooOh
OOOO_OOOO_OOOOh
OOO_oooo_OOOOb
6000_0010h
OOOO_OOOOh
OOOO_OOOOh
OOOO_OOOOh
OOOO_0400h
FFFF_OFFOh
OOOO_OOOOh
oooO_OOOOh
oooo_oOOOh
OOOo_oooOh
OOOO_OOOO_OOOO_OOOOh
oooo_oOOO_oooo_ooOOh
oooo_oooo_oooo_ooooh
oooo_oooo_oOOo_ooOOh
OOOO_OOOO_OOOO_OOOOh
OOOO_OOOO_OOOO_OOOOh
OOOO_OOOO_OOOo_oOOOh
OOOO_OOOO_OOOF_OOOAh
Notes
3
3
3,4
3,4
Notes:
1. The contents of EAX indicate if 81STwas successful If EAX =oooo_ooooh, then 81ST
was successful If EAX is non-zero, 81ST failed
2. £OX contains the AMD-KS processor signature, which is comprised of the instruction
family, model, and stepping.
3. These MSRs are described in ''AMD-KSTM Processor x86 Architedure Extensions on
pageS7.
4. The AMD-KS processor supports write aI/ocate only on Models 1, 2, and 3, with a
Stepping of 4 or greater.
H
AMD-K5™ Processor
19
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Segment Register Attributes
The selector portion of all segment registers is cleared. The
access rights and attribute fields are set up as shown in Table
10.
Table 10. Segment Register Attribute Fields Initial Values
Attribute Field
Value
G
0
DjB
P
DPL
0
0
S
1
Type
2
1
Description
Byte granularity
16-bit
Present
Privilege level
Application segment (except LDTR)
Data, read-write
The limit fields are set to FFFFh. For CS, the base address is set
to FFFF_OOOOh; for all others the base address is O. Note that
IDTR and GDTR consist of the just base and limit values, which
are initialized to 0 and FFFFh, respectively.
State of the AMD-KSTM Processor After INIT
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFFOh-the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
SMM base, MSRs, and the CD and NW bits of the CRO register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
a reset to exit from Protected mode back to Real mode.
20
AMD-K5™ Processor
PreliminQry InformQtion
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
AMD-KSTM Processor Test and Debug
The AMD-KS processor has the following modes in which
processor and system operation can be tested or debugged:
•
•
•
•
•
•
•
a
•
AMD-K5™ Processor
Hardware Configuration Register (HWCR) - The HWCR is a
MSR that contains configuration bits that enable cache,
branch tracing, debug, and clock control
functions.
Built-In Self-Test (BIST)-Both normal and test access port
(TAP) BIST.
Output-Float Test-A test mode that causes the AMD-KS
processor to float all of its output and bidirectional signals.
Cache and TLB Testing-The Array Access Register (AAR)
supports writes and reads to any location in the tag and data
arrays of the processor's on-chip caches and TLBs.
Debug Registers-Standard 486 debug functions with an
liD-breakpoint extension.
Branch Tracing-A pair of special bus cycles can be driven
immediately after taken branches to specify information
about the branch instruction and its target. The Hardware
Configuration Register (HWCR) provides support for this
and other debug functions.
Functional Redundancy Checking-Support for real-time
testing that uses two processors in a master-checker
relationship.
Test Access Port (TAP) Boundary-Scan Testing-The JTAG
test access functions defined by the IEEE Standard Test
Access Port and Boundary-Scan Arch itecture (IEEE
1149.1-1990) specification.
Hardware Debug Tool (HDT)-The hardware debug tool
(HDT), sometimes referred to as the debug port or Probe
mode, is a collection of signals, registers, and processor
microcode enabled when external debug logic drives RIS
Low or loads the AMD-KS processor's Test Access Port
(TAP) instruction register with the USEHDT instruction.
21
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
The test-related signals are described in Chapter 5 of the
AMD-KSTM Processor Technical Reference Manual, order# 18524.
The signals include the following:
•
•
FLUSH
FRCMC
•
•
•
IERR
INIT
PRDY
• RlS
•
RESET
•
•
•
•
•
TCK
TDI
TDO
TMS
TRST
The sections that follow provide details on each of the test and
debug features.
Hardware Configuration Register (HWCR)
The Hardware Configuration Register (HWCR) is a MSR that
contains configuration bits that enable cache, branch tracing,
write allocation, debug, and clock control functions. The
WRMSR and RDMSR instructions access the HWCR when the
ECX register contains the value 83h, as described on page 90.
Figure 2 and Table 11 show the format and fields of the HWCR.
22
AMD-KSTM Processor
AM Dl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E,/O-June 1997
8 7 6 5 4 3 2 1 0
31
0-. ReseNed
--III
Symbol
DDC
DIC
DBP
WA
DC
Description
Bits
Disable Data Cache
7
Disable Instruction Cache
6
Disable Branch Prediction
Write Allocate Enable
4
Debug Control
3-1 --------------------------------~
000 Off
001 Enable branch trace usages
DSPC
Disable Stopping Processor Clocks
0
Figure 2. Hardware Configuration Register (HWCR)
Table 11. Hardware Configuration Register (HWCR) Fields
Bit
Mnemonic
Description
31-8
-
-
7
DDC
Disable Data Cache
6
DlC
Disable Instruction Cache
5
DBP
Disable Branch Prediction
4
WA*
Enable Write Allocate
Function
reserved
Disables data cache
o= enabled, 1 = disabled
Disables instruction cache
o= enabled, 1 = disabled
Disables branch prediction
o= enabled, 1 = disabled
Enables write allocation
o= disabled, 1 = enabled
Note:
*
The AMD-K5 processor supports write allocate only on Models 1, 2, and 3, with a Stepping of 4 or greater.
AMD-K5™ Processor
23
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O- June 1997
Table 11. Hardware Configuration Register (HWCR) Fields (continued)
Bit
Mnemonic
Description
3-1
DC
Debug Control
Function
Debug control bits:
000
Off (disable HWCR debug control)
Enable branch-tracing messages. See "Branch
001
Tracing" on page 39.
010
011
100
101
110
111
0
Disable Stopping
Processor Clocks
DSPC
reserved
reserved
reserved
reserved
reserved
reserved
Disables stopping of internal processor clocks in the
Halt and Stop Grant states
0= enabled, 1 = disabled
Note:
*
The AMD-K5 processor supports write allocate only on Models 1, 2, and J, with a Stepping of 4 or greater.
Built-In Self-Test (BIST)
The processor supports the following types of built-in self-test:
•
NormalBIST-A built-in self-test mode typically used to test
•
system functions after RESET
Test Access Port (TAP) BIST-A self-test mode started by the
TAP instruction, R UNBIST
All internal arrays except the TLB are tested in parallel by
hardware. The TLB is tested by microcode. The AMD-KS
processor does not report parity errors on IERR for every cache
or TLB access. Instead, the AMD-KS fully tests its caches during
the BIST. EADS should not be asserted during a BIST. The
AMD-KS accesses the physical tag array during BISTs, and
these accesses can conflict with inquire cycles.
24
AMD-K5™ Processor
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PreliminQry InformQtion
AMD K86™ Family BIOS and Software Tools Developers Guide
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Normal BIST
The normal BIST is invoked if INIT is asserted at the falling
edge of RESET. The BIST runs tests on the internal hardware
that exercise the following resources:
Instruction cache:
Linear tag directory
Instruction array
Physical tag directory
II
Data cache:
Linear tag directory
Data array
Physical tag directory
II
Entry-point and instruction-decode PLAs
a Microcode ROM
11'1
TLB
1:1
The BIST runs a linear feedback shift register (LFSR) signature
test on the microcode ROM in parallel with a March C test on
the instruction cache, data cache, and physical tags. This is
followed by the March C test on the TLB arrays and an LFSR
signature test on the PLA, in that order. Upon completion of
the PLA test, the processor transfers the test result from an
internal Hardware Debug Test (HDT) data register to the EAX
register for external access, resets the internal microcode, and
begins normal code fetching.
The result of the BIST can be accessed by reading the lower 9
bits of the EAX register. If the EAX register value is
OOOO_OOOOh, the test completed successfully. If the value is not
zero, the non-zero bits indicate where the failure occurred, as
shown in Table 12. The processor continues with its normal
boot process after the BIST is completed, whether the BIST
passed or failed.
Table 12. BIST Error Bit Definition in EAX Register
Bit Value
Bit Number
1
0
AMD-K5™ Processor
31-9
No Error
8
No Error
Always 0
Data path
7
No Error
Instruction-cache instructions
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AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 12. BI5T Error Bit Definition in EAX Register (continued)
Bit Value
Bit Number
1
0
6
5
4
3
2
1
0
Test Access Port
(TAP) 81ST
No Error
No Error
No Error
No Error
No Error
No Error
No Error
Instruction-cache linear tags
Data-cache linear tags
PLA
Microcode ROM
Data-cache data
Instruction cache physical tags
Data-cache physical tags
The TAP BIST performs all the functions of the normal BIST, up
to and including the PLA signature test, in the exact manner as
the normal BIST. However, after the PLA test, the test result is
not transferred to the EAX register.
The TAP BIST is started by loading and executing the
R UNBIST instruction in the test access port, as described in
"Boundary Scan Architecture Support" on page 41. When the
RUNBIST instruction is executed, the processor enters into a
reset mode that is identical to that entered when the RESET
signal is asserted. Upon completion of the TAP BIST, the result
remains in the BIST result register for shifting out through the
TDO signal. The TRST signal must be asserted, or the TAP
instruction must be changed, to exit TAP BIST and return to
normal operation.
Output-Float Test
The Output-Float Test mode is entered if FLUSH is asserted
before the falling edge of RESET. This causes the processor to
place all of its output and bidirectional signals in the
high-impedance state. In this isolated state, system board
traces and connections can be tested for integrity and
drive ability. The Output-Float Test mode can only be exited by
asserting RESET again.
On the AMD-K5 processor and Pentium, FLUSH# is an
edge-triggered interrupt. On the 486 processor, however, the
signal is a level-sensitive input.
26
AMD-KSTM Processor
Preliminary Information
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AMD K86™ Family BIOS and Software Tools Developers Guide
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Cache and TLB Testing
The internal cache for the AMD-K5 processor is divided into
two caches-a 16-Kbyte, 4-way, set-associative instruction
cache and an 8-Kbyte, 4-way, set-associative data cache. Cache
and TLB testing is often done by the BIOS or operating system
during power-up.
Note: The AMD-K6 MMX enhanced processor does not contain
these features. It contains a built-in self-test for all internal
memories.
The individual locations of all SRAM arrays on the AMD-K5
processor are accessible with the RDMSR and WRMSR
instructions. To access an array location, set up the Array
Access MSR code (82h) in ECX, and the array pointer (see
page 28) in EDX. EAX holds the data to be read or written.
Tests can be performed on the following arrays:
•
•
•
•
AMD-K5™ Processor
Data Cache-8-Kbyte, 4-way, set-associative
Data array
Linear-tag array
Physical-tag array
Instruction Cache-16-Kbyte, 4-way, set-associative
Instruction array
Linear-tag array
Physical-tag array
Valid-bit array
Branch-prediction bit array
4-Kbyte TLB-128-entry, 4-way, set-associative
Linear-tag array
Page array
4-Mbyte TLB-4-entry, fully associative
Linear-tag array
Page array
27
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
Array Access Register
(AAR)
21 062EjO- June 1997
The 64-bit Array Access Register (AAR) is a MSR that contains
a 32-bit array pointer that identifies the array location to be
tested and 32 bits of array test data to be read or written. The
WRMSR and RDMSR instructions access the AAR when the
ECX register contains the value 82h, as described on page 90.
Figure 3 shows the format of the AAR.
31
0
Array Pointer
(Contents of EDX)
31
0
Array Data
(Contents of EAX)
I
I
MSR
82h
Figure 3. Array Access Register (AAR)
To read or write an array location, perform the following steps:
1. ECX-Enter 82h into ECX to access the 64-bit AAR.
2. EDX-Enter a 32-bit array pointer into EDX, as shown in
Figures 4 through 12 (top).
3. EAX-Read or write 32 bits of array test data to or from
EAX, as shown in Figures 4 through 12 (bottom).
Array Pointer
The array pointers entered in EDX (Figures 4 through 12, top)
specify particular array locations. For example, in the data- and
instruction-cache arrays, the way (or column) and set (or index)
in the array pointer specify a cache line in the 4-way,
set-associative array. The array pointers for data-cache data
and instruction-cache instructions also specify a dword location
within that cache line. In the data cache, this dword is 32 bits of
data; in the instruction cache, this dword is two instruction
bytes plus their associated pre-decode bits. For the 4-Kbyte
TLB, the way and set specify one of the 128 TLB entries. In
4-Mbyte TLB, one of only four entries is specified.
Bits 7-0 of every array pointer encode the array ID, which
identifies the array to be accessed, as shown in Table 13. To
simplify multiple accesses to an array, the contents of EDX are
28
AMD-KSTM Processor
AM Dl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
retained after the RDMSR instruction executes (EDX is
normally cleared after a RDMSR instruction).
Table 13. Array IDs in Array Pointers
Array Pointer
Bits 7-0
Eoh
Elh
ECh
E4h
Esh
EDh
EGh
E7h
Esh
E9h
EAh
EBh
Array Test Data
AMD-K5™ Processor
Accessed Array
Data Cache: Data
Data Cache: linear Tag
Data Cache: Physical Tag
Instruction Cache: Instructions
Instruction Cache: linear Tag
Instruction Cache: Physical Tag
Instruction Cache: Valid Bits
Instruction Cache: Branch-Prediction Bits
4-Kbyte TLB: Page
4-Kbyte TLB: Virtual Tag
4-Mbyte TLB: Page
4-Mbyte TLB: Virtual Tag
EAX specifies the test data to be read or written with the
RDMSR or WRMSR instruction (see Figures 4 through 12). For
example, in Figure 4 (top) the array pointer in EDX specifies a
way and set within the data-cache linear tag array (E1h in bits
7-0 of the array pointer) or the physical tag array (ECh in bits
7-0 of the array pointer). If the linear tag array (E1h) is
accessed, the data read or written includes the tag and the
status bits. The details of the valid fields in EAX are
proprietary.
29
AMD 11
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
EDX: Array Pointer
29 28 27
13 12
19 18
o
8 7
Array ID
(Elh, ECh)
Set
I
EAX: Test Data
31
26
25
Dirty
Bit
24
23 22
User/Supervisor RfW
Bit
Bit
0
21
o
20
Linear
Valid
Bit
Tag
(El h) Linear Tag
31
23 22
o
21 20
MESI STATE
00 = Invalid, 01 = Shared
10= Modified, 11 = Exclusive
Tag
(ECh) Physical Tag
Figure 4. Test Formats: Dcache Tags for the AMD-K5™ Processor Model 0
30
AMD-K5™ Processor
AM D~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
EDX: Array Pointer
31 30 29 28 27
19 18
13 12
8
o
7
ArraylD
(E1h, ECh)
Set
I
EAX: Test Data
31
28 27 26
25
24
23
22
21
P P Dirty User/Supervisor R/W
C W Bit
Bit
Bit
D T
0
Linear
Valid
Bit
o
20
Tag
(E1h) Linear Tag
31
23 22
21
MESI STATE
00 = Invalid, 01 = Shared
10 = Modified, 11 = Exclusive
o
20
Tag
(ECh) Physical Tag
Figure
s.
Test Formats: Dcache Tags for the AMD-KSTM Processor Modell and Greater
AMD-KSTM Processor
31
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
EDX: Array Pointer
31 30 29 28 27
Way
13 12
19 18
Data Array Index
10 9
8
o
7
Dword
Index into
Block
Array ID
(EOh)
EAX: Test Data
o
31
Valid Bits
(EOh) Data
I
Figure 6. Test Formats: Dcache Data for All Models of the AMD-K5™ Processor
32
AMD-K5™ Processor
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
EDX: Array Pointer
29 28 27
12 11
2019
9 8
7
IcacheWord
(2 Instruction
Icache Index for Alilcache Arrays Bytes +
Pre-decode)
Way
Array 10
(E5h, EDh, E6h, E7h)
EAX: Test Data
0
20 19
31
I
Linear Address
(E5h) Linear Tag
31
21
20 19
0
IV: ~dl
I
Tag (Physical Address 31-11)
(EDh) Physical Tag
31
19
18
0
17
0
16 15
Linea User/
Tag Super
Valid visor
Bit
Byte Valid Bits
(E6h) Valid Bits
31
19 18
17
14 13
12 11
Pre- Byte Offset Within Column of
dicted Block of Last Byte of Predicted
Taken Predicted Branch
Target
Instruction
4 3
Index of Predicted Target
o
Target Byte
(E7h) Branch-Prediction Bits
Figure 7. Test Formats: Icache Tags for the AMD-K5™ Processor Model 0
AMD-K5™ Processor
II
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
EDX: Array Pointer
31 30 29 28 27
20 19
13 12
8
Array 10
(ESh, EDh, E6h, E7h)
!cache Index for All
Icache Arrays
Way
o
7
EAX: Test Data
31
22
21
20
o
19
Linear User!
Tag SuperValid visor
Bit
Linear Address
(ESh) Linear Tag
31
21
0
20 19
IV: ~dl
Valid Bits
(EDh) Physical Tag
0
31
Valid Bits
(E6h) Valid Bits
31
19 18
17
14 13
4 3
12 11
Pre- Byte Offset Within Column of
dicted Block of Last Byte of Predicted
Taken Predicted Branch Target
Instruction
Index of Predicted Target
I
I
0
Target Byte
(E7h) Branch-Prediction Bits
Figure 8. Test Formats: Icache Tags for the AMD-K5™ Processor Model 1 and Greater
:J4
AMD-K5™ Processor
AM D ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
EDX: Array Pointer
31 30 29 28 27
20 19
12 11
9
8
o
7
ArraylD
(E4h)
Set
I
EAX: Test Data
Prefix 1
31
Prefix 0
26 25 24 23 22
21 20
Map
Op)tart End code ROPS/MR
Bit Bit Bit
OM
13 12 11
Byte 1
o
8 7
10 9
Map
OpStan End code ROPS/MR
Bit Bit Bit
OM
Byte 0
(E4h) Instruction Bytes
Figure 9. Test Formats: Icache Instructions for the AMD-KSTM Processor Model 0
EDX: Array Pointer
31 30 29 28 27
20 19
!cache Index for Allicache
Arrays
Way
8
12 11 10
0
o
7
ArraylD
(E4h)
Byte
1
,
PacketO/l>low/hlghlow: Bytes 0-7 and 8-15 high: Bytes 16-23 and 24-31
EAX: Test Data
Prefix 1
31
26 25 24 23 22
Prefix 0
21 20
Map
Opf>tart End code ROPS/MR
Bit Bit Bit
OM
131211109
Byte (n + 8)
o
8 7
Map
OpStart End code ROPS/MR
Bit Bit Bit
OM
Byte (n)
(E4h) Instruction Bytes
Figure 10. Test Formats: Icache Instructions for the AMD-KSTM Processor Modell and Greater
AMD-K5™ Processor
35
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
EDX: Array Pointer
31 30 29 28 27
13 12
8
o
7
TLB Index
Array ID
(E8h. E9h)
I
EAX: Test Data
31
o
22 21 2019
I
Page Frame Address
(E8h) 4-Kbyte Page and Status
31
20 19
o
18 17 16 15 14
Tag (Virtual Address 31-17)
I
(E9h) 4-Kbyte Virtual Tag
S¥m.!m!
GV
D
U/S
R/W
V
Description
Global Valid Bit
Dirty Bit
User Supervisor Bit
Read or Write Bit
Valid Bit
15 - - - - - - - - '
Figure 11. Test Formats: 4-Kbyte TLB for All Models of the AMD-K5™ Processor
36
AMD-K5™ Processor
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
EDX: Array Pointer
31 30 29 28 27
8
o
7
I
Array ID
(EAh, EBh)
EAX: Test Data
31
12 11
10
I~ I~I
(EAh) 4-Mbyte Page and Status
31
(EBh) 4-Mbyte Virtual Tag
RfW
V
Description
Global Valid Bit
Dirty Bit
User Supervisor Bit
Read or Write Bit
Valid Bit
~
14
13
12
11
10
I
Valid Bits
15 14 13 12 11 10 9
1~IDI(11Ivl
Symbol
GV
D
UjS
0
0
Valid Bits
I
II
II
I
Figure 12. Test Formats: 4-Mbyte TLB for All Models of the AMD-K5™ Processor
AMD-K5™ Processor
37
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
Debug Registers
The processor implements the standard debug functions and
registers-DR7-DR6 and DR3-DRO (often called DR7-DRO)available on the 486 processor, plus an liD breakpoint
extension.
Standard Debug
Functions
The debug functions make the processor's state visible to
debug software through four debug registers (DR3-DRO) that
are accessed by MOV instructions. Accesses to memory
addresses can be set as breakpoints in the instruction flow by
invoking one of two debug exceptions (interrupt vectors 1 or 3)
during instruction or data accesses to the addresses. The debug
functions eliminate the need to embed breakpoints in code and
allow debugging of ROM as well as RAM.
For details on the standard 486 debug functions and registers,
see the AMD documentation on the Am4861!0 processor or other
commercial x86 literature.
1/0 Breakpoint
Extension
The processor supports an liD breakpoint extension for
breakpoints on I/O reads and writes. This function is enabled by
setting bit 3 of CR4, as described in "Control Register 4 (CR4)
Extensions" on page 58. When enabled, the I/O breakpoint
function is invoked by the following:
•
•
Entering the 110 port number as a breakpoint address
(zero-extended to 32 bits) in one of the breakpoint registers,
DR3-DRO
Entering the bit pattern, lOb, in the corresponding 2-bit
read-write (RIW) field in DR7
All data breakpoints on the AMD-K5 processor are precise,
including those encountered in repeated string operations. The
trap is taken after completing the iteration on which the
breakpoint match occurs.
Enabled breakpoints slow the processor somewhat. When a
data breakpoint is enabled, the processor disables its dual-issue
load/store operations and performs only single-issue load/store
operations. When an instruction breakpoint is enabled,
instruction issue is completely serialized.
38
AMD-K5™ Processor
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
Debug Compatibility
with the Pentium~
Processor
AM D ~
The differences in debug functions between the AMD-K5
processor and Pentium are described in Appendix A of the
AMD-KSTM Processor Technical Reference Manual, order# 18524.
Branch Tracing
Branch tracing is enabled by writing bits 3-1 with 00lb and
setting bit 5 to 1 (disabling branch prediction) in the Hardware
Configuration Register (HWCR), as described on page 22.
When thus enabled, the processor drives two branch-trace
message special bus cycles immediately after each taken
branch instruction is executed. Both special bus cycles have a
BE7-BEO encoding of DFh (1101_1111b). The first special bus
cycle identifies the branch source, the second identifies the
branch target. The contents of the address and data bus during
these special bus cycles are shown in Table 14.
The branch-trace message special bus cycles are different for
the AMD-K5 processor and Pentium, although their BE7-BEO
encodings are the same.
Table 14. Branch-Trace Message Special Bus Cycle Fields
A31
o= First special bus cycle (source)
Second Special Bus Cycle
1 = Second special bus cycle (target)
Operating Mode of Target:
A30-A29
Not valid
10 = Protected Mode
Signals
First Special Bus Cycle
11 = Virtual-8086 Mode
01 = Not valid
00 = Real Mode
Default Operand Size of Target Segment:
A28
Not valid
1 = 32-bit
A27-A20
A19-A4
A3
031-00
0
Code Segment (CS) selector of Branch Source
0
EIP of Branch Source
0= 16-bit
0
Code Segment (CS) Selector of Branch Target
0
EIP of Branch Target
AMD-K5™ Processor
J9
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Functional-Redundancy Checking
When FRCMC is asserted at RESET, the processor enters
Functional-Redundancy Checking mode as the checker and
reports checking errors on the IERR output. If FRCMC is
negated at RESET, the processor operates normally, although
it also behaves as the master in a functional-redundancy
checking arrangement with a checker.
In the Functional-Redundancy Checking mode, two processors
have their signals tied together. One processor (the master)
operates normally. The other processor (the checker) has its
output and bidirectional signals (except for TDO and IERR)
floated to detect the state of the master's signals. The master
controls instruction fetching and the checker mimics its
behavior by sampling the fetched instructions as they appear
on the bus. Both processors execute the instructions in lock
step. The checker compares the state of the master's output and
bidirectional signals with the state that the checker itself
would have driven for the same instruction stream.
Errors detected by the checker are reported on the IERR
output of the checker. If a mismatch occurs on such a
comparison, the checker asserts IERR for one clock, two clocks
after the detection of the error. Both the master and the
checker continue running the checking program after an error
occurs. No action other than the assertion of IERR is taken by
the processor. On the AMD-K5 processor, the IERR output is
reserved solely for functional-redundancy checking. No other
errors are reported on that output.
Functional-redundancy checking is typically implemented on
single-processor, fault-monitoring systems (which have two
processors). The master processor runs the operational
programs and the checker processor is dedicated entirely to
constant checking. In this arrangement, the accurate operation
test consists solely of reporting one or more errors. The
particular error type or the instruction causing an error is not
reported. The arrangement works because the processor is
entirely deterministic. Speculative prefetching, speculative
execution, and cache replacement all occur in identical ways
and at identical times on both processors if their signals are
tied together so that they run the same program.
40
AMD-K5™ Processor
Preliminary Information
AM D ~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
The Functional-Redundancy Checking mode can only be exited
by the assertion of RESET. Functional-redundancy checking
cannot be performed in the Hardware Debug Tool (HDT) mode.
The assertion of FRCMC is not recognized while PRDY is
asserted.
Boundary Scan Architecture Support
The AMD-KS processor provides test features compatible with
the Standard Test Access Port (TAP) and Boundary Scan Test
Architecture as defined in the IEEE 1149.1-1990 JTAG
Specification. The subsections in this topic include:
a
a
a
II
a
a
Boundary Scan Test Functional Description
Boundary Scan Architecture
Registers
The Test Access Port (TAP) Controller
JTAG Register Organization
JTAG Instructions
The external TAP interface consists of five pins:
III
a
a
Il
a
TCK: The Test Clock input provides the clock for the JTAG
test logic.
TMS: The Test Mode Select input enables TAP controller
operations.
TDI: The Test Data Input provides serial input to registers.
TDO: The Test Data Output provides serial output from the
registers; the signal is tri-stated except when in the Shift-DR
or Shift-IR controller states.
TRST: The TAP Controller Reset input initializes the TAP
controller when asserted Low.
The internal JTAG logic contains the elements listed below:
II
•
AMD-KSTM Processor
The Test Access Port (TAP) Controller-Decodes the inputs
on the Test Mode Select (TMS) line to control test
operations. The TAP is a general-purpose port that provides
access to the test support functions built into the AMD-KS.
Instruction Register-Accepts instructions from the Test
Data Input (TDI) pin. The instruction codes select the
specific test or debug operation to be performed or the test
data register to be accessed.
41
AMDl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
•
Boundary Scan Test
Functional
Description
21 062EjO- June 1997
Implemented Test Data Registers-Boundary Scan
Register, Device Identification Register, and Bypass
Register. See "JTAG Register Organization" on page 44 for
more information.
Note: See Table 18 on page 49 for more information.
The boundary scan testing uses a shift register, contained in a
boundary scan cell, located between the core logic and the I/O
buffers adjacent to each component pin. Signals at each input
and output pin are controlled and observed using scan testing
techniques. The boundary scan cells are interconnected to form
a shift register chain. This register chain, called a Boundary
Scan Register (BSR), constructs a serial path surrounding the
core logic, enabling test data to be shifted through the
boundary scan path. When the system enters the Boundary
Scan Test mode, the BSR chain is directed by a test program to
pass data along the shift register path.
If all the components used to construct a circuit or PCB contain
a boundary scan cell architecture, the resulting serial path can
be used to perform component interconnect testing.
Boundary Scan
Architecture
Boundary Scan architecture has four basic elements:
•
•
•
•
Test Access Port (TAP)
TAP Controller
Instruction Register (IR). See "Instruction Register" on
page 44 for more information.
Test Data Registers. See "Registers" on page 43 for more
information.
The Instruction and Test Data Registers have separate shift
register access paths connected in parallel between the Test
Data In (TDI) and Test Data Out (TDO) pins. Path selection and
boundary scan cell operation is controlled by the TAP
Controller. The controller initializes at start-up, but the Test
Reset (TRST) input can asynchronously reset the test logic, if
required.
All system integrated circuit (IC) I/O signals are shifted in and
out through the serial Test Data In (TDI) and Test Data Out
(TDO) path. The TAP Controller is enabled by the Test Mode
Select (TMS) input. The Test Clock (TCK), obtained from a
system level bus or Automatic Test Equipment (ATE), supplies
42
AMD-K5™ Processor
Preliminary Information
AMD ~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
the timing signal for data transfer and system architecture
operation.
The dedicated TCK input enables the serial test data path
between components to be used independently of
component-specific system clocks. TCK also ensures that test
data can be moved to or from a chip without changing the state
of the on-chip system logic.
The TCK signal is driven by an independent 50% duty cycle
clock (generated by the Automatic Test Equipment). If the TCK
must be stopped (for example, if the ATE must retrieve data
from external memory and is unable to keep the clock running),
it can be stopped at 0 or 1 indefinitely, without causing any
change to the test logic state.
To ensure race-free operation, changes on the TAP's TMS input
are clocked into the test logic. Changes on the TAP's TDI input
are clocked into the selected register (Instruction or Test Data
Register) on the rising edge of TCK. The contents of the
selected register are shifted out onto the TAP output (TDO) on
the falling edge of TCK.
Registers
Boundary scan architectural elements include an Instruction
Register (IR) and a group of Test Data Registers (TDRs). These
registers have separate shift-register-based serial access paths
connected in parallel between the TDI and TDO pins.
The TDRs are internal registers used by the Boundary Scan
Architecture to process the test data. Each Test Data Register
is addressed by an instruction scanned into the Instruction
Register. The AMD-K5 processor includes the following TDRs:
•
•
•
•
AMD-K5™ Processor
Bypass Register (BR). See "Bypass Register" on page 45.
Boundary Scan Register (BSR). See "Boundary Scan
Register" on page 44.
Device Identification Register (DIR). See "Device
Identification Register" on page 45.
Built-In Self-Test Result Register (BISTRR). See
"R UNBIST" on page 48.
43
PreiiminDry IniormDtion
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Instruction Register. The 5-bit Instruction Register (IR) is a
serial-in parallel-out register tha t includes five shift
register-based cells for holding instruction data. The
instruction determines which test to run, which data register to
access, or both. When the TAP controller enters the Capture-IR
state, the processor loads the IDCODE instruction in the IR.
Executing Shift-IR starts instructions shifting into the
instruction register on the rising edge of TCK. Executing
Update-IR loads the instruction from the serial shift register to
the parallel register.
The TAP controller is a synchronous, finite-state machine that
controls the test and debug logic sequence of operations. The
TAP controller changes state in response to the rising edge of
TCK and defaults to the test logic reset state at power-up.
Reinitialization to the test logic reset state is accomplished by
holding the TMS pin High for five TCK periods.
JTAG Register
Organization
All registers in the JTAG logic consist of the following two
register ranks:
•
•
Shift register
Parallel output register fed by the shift register
Parallel input data is loaded into the shift register when the
TAP controller exits the Capture state (Capture-DR or
Capture-IR). The shift register then shifts data from TDI to
TDO when in the Shift state (Shift-DR or Shift-IR). The output
register holds the current data while new· data is shifted into
the shift register. The contents of the output register are
updated when the TAP controller exits the Update state
(Update-DR or Update-IR). The following three registers are
described in this section:
•
•
•
Boundary Scan Register
Device Identification Register
Bypass Register
Boundary Scan Register. The Boundary Scan Register (BSR) is a
261-bit shift register with cells connected to all input and
output pins and containing cells for tri-state 1/0 control. This
arrangement enables serial data to be loaded into or read from
the processor boundary scan area.
44
AMD-K5™ Processor
AM Dl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Output cells determine the value of the signal driven on the
corresponding pin. Input cells only capture data. The EXTEST
and SAMPLE/PRELOAD instructions can operate the BSR.
Device Identification Register. The for mat 0 f the D e vic e
Identification Register (DIR) is shown in Table 15. The fields
include the following values:
•
•
•
•
Version Number-This field is incremented by AMD
manufacturing for each major revision of silicon.
Bond Option-The two bits of the bond option depend on
how the part is bonded at the factory.
Part Number- This field identifies the specific processor
model.
Manufacturer-This field is actually only 11 bits (11-1). The
least-significant bit, bit 0, is always set to 1, as specified by
the IEEE standard.
.
Table 15. AMD-K5™ Processor Device Identification Register
Version
(Bits 31-28)
Bond Option
(Bits 27-26)
Part Number
(Bits 25-12)
Manufacturer
(Bits 11-1)
LSB
(Bit 0)
oh
Xob
051Xh
oooooooooolb
lb
Bypass Register. The Bypass Register, a 1-bit shift register,
provides the shortest path between TDI and TDO. When the
component is not performing a test operation, this path is
selected to allow transfer of test data to and from other
components on the board. The Bypass Register is also selected
during the HIGHZ, ALL1, ALLO, and BYPASS tests and for any
unused instruction codes.
Public Instructions
The processor supports all three IEEE-mandatory instructions
(BYPASS, SAMPLE/PRELOAD, EXTEST), three IEEE-optional
instructions (IDCODE, HIGHZ, R UNBIST), and three
instructions unique to the AMD-K5 processor (ALL1, ALLO,
USEHDT). Table 16 shows the complete set of public TAP
instructions supported by the processor. The AMD-K5 also
implements several private manufacturing test instructions.
The IEEE standard describes the mandatory and optional
instructions. The ALL1 and ALLO instructions simply force all
outputs and bidirectionals High or Low. The USEHDT
instruction is described on page 57. Any instruction encodings
not shown in Table 16 select the BYPASS instruction.
AMD-K5™ Processor
45
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 16. Public TAP Instructions
Instruction
Encoding
Register
BSR
As defined by the IEEE standard
BSR
As defined by the IEEE standard
DIR
As defined by the IEEE standard
BR
As defined by the IEEE standard
ALL1
00000
00001
00010
00011
00100
BR
Forces all outputs and bidirectionals High
ALLO
00101
BR
Forces all outputs and bidirectionals Low
EXTEST
SAMPLE/PRELOAD
IDCODE
HIGHZ
Description
USEHDT
00110
HDTR
Accesses the Hardware Debug Tool (HOD
See page 57
RUNBIST
00111
11111
BISTRR
As defined by the IEEE standard
BYPASS
BYPASS
undefined
BR
As defined by the IEEE standard
BR
Undefined instruction encodings select the BYPASS
instruction
EXTEST. The EXTEST instruction permits circuits outside the
component package to be tested. A common use of the EXTEST
instruction is the testing of board interconnects. Boundary scan
register cells at output pins are used to apply test stimuli, while
those at input pins capture test results. Depending on the value
loaded into their control cells in the boundary scan register, the
1/0 pins are established as input or output. Inputs to the core
logic retain the logic value set prior to execution of the
EXTEST instruction. Upon exiting EXTEST, input pins are
reconnected to the package pins.
SAMPLE/PRELOAD. There are two functions performed by the
SAMPLEIPRELO AD instruction, as follows:
•
•
46
Capturing an instantaneous picture of the normal operation
of the device being tested. This function occurs if the
instruction is executed while the TAP controller is in the
Capture-DR state and causes the Boundary Scan Register to
sample the values present at the device pins.
Preloading data to the device pins to be driven to the board
by the EXTEST instruction. This function occurs if the
instruction is executed while the TAP controller is in the
Update-DR ·state and causes data to be preloaded to the
device pins from the Boundary Scan Register.
AMD-K5™ Processor
Preliminary Information
21 062EjO- June 1997
AMDl1
AMD K86™ Family BIOS and Software Tools Developers Guide
lDeODE. The execution of the IDCODE instruction connects the
device identification register between TDI and TDO. Upon
such connection, the device identification code can be shifted
out of the register.
HIGHZ. This instruction forces all output and bidirectional pins
into a tri-state condition. When this instruction is selected, the
bypass register is selected for shifting between TDI and TDO. A
signal called HIZEXT is responsible for forcing the tri-state to
occur. This signal is generated in the TAP block, underneath
JTAG~BIST, and goes to the PAD_TOP block.
ALL 1. This instruction forces all output and bidirectional pins to
a High logic level.
The ALLl instruction, like the HIGHZ instruction, selects the
bypass register for shifting between TDI and TDO. A signal
called ALLl is responsible for forcing the pins to a High state.
This signal is generated in the TAP block underneath
JTAG_BIST and goes to the PAD_TOP block. In the PAD_TOP
block, this signal goes to boundary scan cells called
BSLCD_OUT. The DOUT pins of the BSLCD_OUT cells are
forced High when ALLl is High. The SELPDR signal selects the
boundary scan cells as the source for driving the outputs if the
SELPDR signal is High. The SELPDR signal is also generated in
the TAP block underneath JTAG_BIST and goes to the
PAD_TOP block.
ALLO. This instruction forces all output and bidirectional pins to
a Low logic level.
The ALLO instruction, like the HIGHZ instruction, selects the
bypass register for shifting between TDI and TDO. A signal
called ALLO is responsible for forcing the pins to a Low state.
This signal is generated in the TAP block underneath
JTAG_BIST and goes to the PAD_TOP block. In the PAD_TOP
block, this signal goes to boundary scan cells called
BSLCD_OUT. The DOUT pins of the BSLCD_OUT cells are
forced Low when ALLO is High. The SELPDR signal selects the
boundary scan cells as the source for driving the outputs if the
SELPDR signal is High. The SELPDR signal is also generated in
the TAP block underneath JTAG_BIST and goes to the
PAD_TOP block.
AMD-K5™ Processor
47
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
RUNBIST. This version of BIST is similar to the normal BIST
mode, except RUNBIST is started by shifting in a TAP
instruction. This instruction should behave according to the
rules of the IEEE 1149.1 definition of RUNBIST.
When the RUNBIST instruction is updated into the instruction
register, a signal from the TAP _RTL block called JTGBIST is
asserted High. This signal goes to the PAD_TOP and
TESTCTRL blocks. In PAD_TOP, this signal goes to the
BRNBIST block and causes both INIT_SAMP and RUNBIST to
be asserted. To the rest of the processor, it looks like a normal
BIST operation is taking place. The JTGBIST signal also goes to
the TESTCTRL block so the BIST controller knows the BIST
operation was initiated from the TAP controller. This operation
is necessary because the BIST results do not get transferred to
the EAX register in this mode of operation. The JTAG_BIST
block also asserts the RESET_TAP pin to the CLOCKS block for
15 system clock cycles in order to fake an external reset.
The pattern that is shifted into the boundary scan ring prior to
the selection of the RUNBIST instruction is driven at output
and bidirectional cells during the duration of the instruction.
The results of the execution of RUNBIST are saved in the BIST
results register, which is 9 bits long and looks like the least
significant 9 bits in the EAX register. This register is selected
for shifting between TDI and TDO and can be shifted out after
the completion of BIST. Bit 0 (ICACHE data status) is shifted
out first. The BIST results should be independent of signals
received at non-clock input pins (except for RESET).
BYPASS. The execution of the BYPASS instruction connects the
bypass register between TDI and TDO, bypassing the test logic.
Because of the pull-up resistor on the TDI input, the bypass
register is selected if there is an open circuit in the board-level
test data path following an instruction scan cycle. Any unused
instruction bit patterns cause the bypass register to be selected
for shifting between TDI and TDO.
48
AMD-K5™ Processor
Preliminary Information
AM D ~
AMD K86™ Family BIOS and Software Tools Developers Guide
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The control bits listed in Table 18 have the characteristics
described in Table 17.
Table 17. Control Bit Definitions
Bit
144
213
257
Definition
Controls the direction of the Oata bus (063-00). If the bit is set to 1, the
bus acts as an input. If the bit is set to 0, the bus acts as an output.
Controls the direction of the Address bus (A31-A3) and Address Parity
(AP). If the bit is set to 1, the bus acts as an input. If the bit is set to 0, the
bus acts as an output.
Controls pins that can be tri-stated, but these pins never act as inputs. If
the bit is set to 1, the pin is tri-stated. If the bit is set to 0, the pin acts as
an output.
Table 18. Boundary Scan Register Bit Definitions
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
Pin Name
OP7
OP7
063
063
062
062
061
061
060
060
059
059
058
058
057
057
056
056
OP6
OP6
Comments
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
-
49
AM D ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E!O-June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
50
Bit
Pin Name
Comments
20
055
Output Cell: Controlled by bit 144
21
055
Input Cell
22
054
Output Cell: Controlled by bit 144
23
054
Input Cell
24
053
Output Cell: Controlled by bit 144
25
053
Input Cell
26
052
Output Cell: Controlled by bit 144
27
052
Input Cell
Output Cell: Controlled by bit 144
28
051
29
051
Input Cell
30
050
Output Cell: Controlled by bit 144
31
050
Input Cell
32
049
Output Cell: Controlled by bit 144
33
049
.Input Cell
34
048
Output Cell: Controlled by bit 144
35
048
Input Cell
36
OP5
Output Cell: Controlled by bit 144
37
OP5
Input Cell
38
047
Output Cell: Controlled by bit 144
39
047
Input Cell
40
046
Output Cell: Controlled by bit 144
41
046
Input Cell
Output Cell: Controlled by bit 144
42
045
43
045
Input Cell
44
044
Output Cell: Controlled by bit 144
45
044
Input Cell
46
043
Output Cell: Controlled by bit 144
47
043
Input Cell
48
042
Output Cell: Controlled by bit 144
49
042
Input Cell
50
041
Output Cell: Controlled by bit 144
51
041
Input Cell
52
040
Output Cell: Controlled by bit 144
53
040
Input Cell
AMD-KSTM Processor
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
Bit
Pin Name
Comments
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
OP4
OP4
039
039
038
038
037
037
036
036
035
035
034
034
033
033
032
032
OP3
OP3
031
031
030
030
029
029
028
028
027
027
026
026
025
025
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
Output Cell: Controlled by bit 144
Input Cell
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
AMD-K5™ Processor
51
AMD~
PreliminDry InformDtion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
52
Bit
Pin Name
Comments
88
024
Output Cell: Controlled by bit 144
89
024
Input Cell
90
OP2
Output Cell: Controlled by bit 144
91
OP2
Input Cell
92
023
Output Cell: Controlled by bit 144
93
023
Input Cell
94
022
Output Cell: Controlled by bit 144
95
022
Input Cell
96
021
Output Cell: Controlled by bit 144
97
021
Input Cell
98
020
Output Cell: Controlled by bit 144
99
020
Input Cell
Output Cell: Controlled by bit 144
100
019
101
019
Input Cell
102
018
Output Cell: Controlled by bit 144
103
018
Input Cell
104
017
Output Cell: Controlled by bit 144
105
017
Input Cell
106
016
Output Cell: Controlled by bit 144
107
016
Input Cell
108
OPl
Output Cell: Controlled by bit 144
109
OPl
Input Cell
110
015
Output Cell: Controlled by bit 144
111
015
Input Cell
112
014
Output Cell: Controlled by bit 144
113
014
Input Cell
114
013
Output Cell: Controlled by bit 144
115
013
Input Cell
116
012
Output Cell: Controlled by bit 144
117
012
Input Cell
118
011
Output Cell: Controlled by bit 144
119
011
Input Cell
120
010
Output Cell: Controlled by bit 144
121
010
Input Cell
AMD-K5™ Processor
AM D l1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
AMD-K5™ Processor
Bit
Pin Name
Comments
122
09
Output Cell: Controlled by bit 144
123
09
Input Cell
124
08
Output Cell: Controlled by bit 144
125
08
Input Cell
126
OP
Output Cell: Controlled by bit 144
127
OP
Input Cell
Output Cell: Controlled by bit 144
128
07
129
07
Input Cell
130
06
Output Cell: Controlled by bit 144
131
06
Input Cell
132
05
Output Cell: Controlled by bit 144
133
05
Input Cell
134
04
Output Cell: Controlled by bit 144
135
04
Input Cell
136
03
Output Cell: Controlled by bit 144
137
03
Input Cell
138
02
Output Cell: Controlled by bit 144
139
02
Input Cell
Output Cell: Controlled by bit 144
140
01
141
01
Input Cell
142
00
. Output Cell: Controlled by bit 144
143
00
Input Cell
144
Control
Oirection Control. See Table 17.
145
STPLK#
Input Cell
146
FRCMC#
Input Cell
147
PEN#
Input Cell
148
IGNNE#
Input Cell
149
BF
Input Cell
150
INIT
Input Cell
151
SMI#
Input Cell
152
R/S#
Input Cell
153
NMI
Input Cell
154
INTR
Input Cell
155
A21
Output Cell: Controlled by bit 213
53
AM'D ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
54
Bit
Pin Name
Comments
156
A21
Input Cell
157
A22
Output Cell: Controlled by bit 213
158
A22
Input Cell
159
A23
Output Cell: Controlled by bit 213
160
A23
Input Cell
Output Cell: Controlled by bit 213
161
A24
162
A24
Input Cell
163
A25
Output Cell: Controlled by bit 213
164
A25
Input Cell
165
A26.
Output Cell: Controlled by bit 213
166
A26
Input Cell
167
A27
Output Cell: Controlled by bit 213
168
A27
Input Cell
169
A28
Output Cell: Controlled by bit 213
170
A28
Input Cell
171
A29
Output Cell: Controlled by bit 213
172
A29
Input Cell
Output Cell: Controlled by bit 213
173
A30
174
A30
Input Cell
175
A31
Output Cell: Controlled by bit 213
176
A31
Input Cell
177
A3
Output Cell: Controlled by bit 213
178
A3
Input Cell
179
A4
Output Cell: Controlled by bit 213
180
A4
Input Cell
Output Cell: Controlled by bit 213
181
AS
182
AS
Input Cell
183
A6
Output Cell: Controlled by bit 213
184
A6
Input Cell
185
A7
Output Cell: Controlled by bit 213
186
A7
Input Cell
187
A8
Output Cell: Controlled by bit 213
188
A8
Input Cell
189
A9
Output Cell: Controlled by bit 213
AMD-K5™ Processor
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O:- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
AMD-K5™ Processor
Bit
Pin Name
190
A9
Comments
Input Cell
191
Al0
Output Cell: Controlled by bit 213
192
Al0
Input Cell
193
All
Output Cell: Controlled by bit 213
194
All
Input Cell
195
A12
Output Cell: Controlled by bit 213
196
A12
Input Cell
Output Cell: Controlled by bit 213
197
A13
198
A13
Input Cell
199
A14
Output Cell: Controlled by bit 213
200
A14
Input Cell
201
A15
Output Cell: Controlled by bit 213
202
A15
Input Cell
Output Cell: Controlled by bit 213
203
A16
204
A16
Input Cell
205
A17
Output Cell: Controlled by bit 213
206
A17
Input Cell
207
A18
Output Cell: Controlled by bit 213
208
A18
Input Cell
209
A19
Output Cell: Controlled by bit 213
210
A19
Input Cell
211
A20
Output Cell: Controlled by bit 213
212
A20
Input Cell
213
Control
Direction Control. See Table 17.
214
SCVC
Output Cell: Controlled by bit 257
215
RESET
Input Cell
216
BE7#
Output Cell: Controlled by bit 257
217
BE6#
Output Cell: Controlled by bit 257
218
BE5#
Output Cell: Controlled by bit 257
219
BE4#
Output Cell: Controlled by bit 257
220
BE3#
Output Cell: Controlled by bit 257
221
BE2#
Output Cell: Controlled by bit 257
222
BE1#
Output Cell: Controlled by bit 257
223
BEO#
Output Cell: Controlled by bit 257
55
AM D~
Preliminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E!O- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
56
Bit
Pin Name
Comments
224
WjR#
Output Cell: Controlled by bit 257
Output Cell
225
HIT#
226
CLK
Clock
227
ADSC#
Output Cell: Controlled by bit 257
228
ADS#
Output Cell: Controlled by bit 257
229
CACHE#
Output Cell: Controlled by bit 257
230
BRDYC#
Input Cell
231
BRDY#
Input Cell
232
EADS#
Input Cell
233
PWT
Output Cell: Controlled by bit 257
234
LOCK#
Output Cell: Controlled by bit 257
235
PCD
Output Cell: Controlled by bit 257
236
WBfWT#
Input Cell
237
HITM#
Output Cell
238
KEN#
Input Cell
239
AHOLD
Input Cell
240
BOFF#
Input Cell
241
HLDA
Output Cell
242
HOLD
Input Cell
243
NA#
Input Cell
244
EWBE#
Input Cell
245
MjIO#
Output Cell: Controlled by bit 257
246
FLUSH#
Input Cell
247
A20M#
Input Cell
248
BUSCHK#
Input Cell
249
AP
Output Cell: Controlled by bit 213
250
AP
Input Cell
251
DjC#
Output Cell: Controlled by bit 257
252
BREQ
Output Cell
253
SMIA0#
Output Cell
254
PCHK#
Output Cell
255
APCHK#
Output Cell
256
PRDY
Output Cell
257
Control
Direction Control. See Table 17.
AMD-KSTM Processor
AMDl1
Preliminory Iniormotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 18. Boundary Scan Register Bit Definitions (continued)
Bit
258
Pin Name
Comments
INV
Input Cell
259
260
FERR#:
Output Cell
IERR#:
Output Cell
Hardware Debug Tool (HOT)
The Hardware Debug Tool (HDT)-sometimes referred to as
the debug port or Probe Mode-is a collection of signals,
registers, and processor microcode that is enabled when
external debug logic drives RIS Low or loads the processor's
Test Access Port (TAP) instruction register with the USEHDT
instruction.
AMD-KSTM Processor x86 Architecture Extensions
The AMD-K5 processor is compatible with the instruction set,
programming model, memory management mechanisms, and
other software infrastructure supported by the 486 and
Pentium (735\90, 815\100) processors. Operating system and
application software that runs on Pentium can be executed on
the AMD-K5. Because the AMD-K5 processor takes a
significantly different approach to implementing the x86
architecture, some subtle differences from Pentium may be
visible to system and code developers. These differences are
described in Appendix A of the AMD-KSTM Processor Technical
Reference Manual, order# 18524.
Call AMD at 1-800-222-9323 to order AMD-K5 support
documents.
Before implementing the AMD-K5 processor model-specific
features, check CPUID for supported feature flags. See
"CPUID" on page 86 for more information.
AMD-K5™ Processor
57
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Additions to the EFLAGS Register
The EFLAGS register on the AMD-KS processor defines new
bits in the upper 16 bits of the register to support extensions to
the operating modes. See "Virtual-8086 Mode Extensions
(VME)" on page 67 and "CPUID" on page 86 for additional
information.
Control Register 4 (CR4) Extensions
Control Register 4 (CR4) was added on the AMD-KS. The bits in
this register control the various architectural extensions. The
majority of the bits are reserved. The default state of CR4 is all
zeros. Figure 13 shows the register and describes the bits. The
architectural extensions are described in Table 19.
S 7 654 3 2 1 0
31
0--. Reserved
~
~
GPE
MCE
PSE
DE
TSD
PVI
VME
Global Page Extension
Machine Check Enable
Page Size Extensions
Debugging Extensions
Time Stamp Disable
Protected Virtual Interrupts
Virtual-SOS6 Mode Extensions
II
M_---...I
7
6
4
3
2
1
0
II
-------------'
---------------'
----------------'
---------------------'
---------------------'
Figure 13. Control Register 4 (CR4)
58
AMD-K5™ Processor
AMDl1
Preliminary Information
AMD K85™ Family BIOS and Software Tools Developers Guide
21 062EjO-June 1997
Table 19. Control Register 4 (CR4) Fields
Bit
Mnemonic
Description
7
GPE
Global Page
Extension*
6
MCE
Machine-Check Enable
4
PSE
Page Size
Extension
3
DE
Debugging
Extensions
2
TSD
Time Stamp
Disable
1
PVI
Protected Virtual
Interrupts
0
VME
Virtual-SOS6
Mode Extensions
Function
Enables retention of designated entries in the 4-Kbyte TLB or
4-Mbyte TLB during invalidations.
1 = enabled, 0 = disabled.
See "Global Pages" on page 65 for details.
Enables machine-check exceptions.
1 = enabled, 0 = disabled.
See "Machine-Check Exceptions" on page 60 for details.
Enables 4-Mbyte pages.
1 = enabled, 0 = disabled.
See "4-Mbyte Pages" on page 60 for details.
Enables I/O breakpoints in the DR7-DRO registers.
1 = enabled, 0 = disabled.
See "Debug Registers" on page 3S for details.
Selects privileged (CPL=O) or non-privileged (CPL>O) use of
the RDTSC instruction, which reads the Time Stamp Counter
(TSC).
1 = CPL must be 0, 0 =any CPL.
See "Time Stamp Counter (TSC)" on page Sl for details.
Enables hardware support for interrupt virtualization in
Protected mode.
1 = enabled, 0 = disabled.
See "Protected Virtual Interrupt (PVI) Extensions" on page 79
for details.
Enables hardware support for interrupt virtualization in
Virtual-SOS6 mode.
1 = enabled, 0 = disabled.
See "Virtual-SOS6 Mode Extensions (VME)" on page 67 for
details.
Note:
*
The AMD-KS processor supports global paging only on Models 1, 2, and 3, with a Stepping of 4 or greater.
AMD-K5™ Processor
59
AM D~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
Machine-Check
Exceptions
21 062E/O- June 1997
Bit 6 in CR4, the machine-check enable (MCE) bit, controls
generation of machine-check exceptions (12h). If enabled by
the MCE bit, these exceptions are generated when either of the
following occurs:
•
•
System logic asserts BUSCHK to identify a parity or other
type of bus-cycle error
The processor asserts PCHK while system logic asserts PEN
to identify an enabled parity error on the D63-DO data bus
Whether or not machine-check exceptions are enabled, the
processor performs the following functions when either type of
bus error occurs:
•
•
Latches the physical address of the failed cycle in its 64-bit
machine-check address register (MCAR)
Latches the cycle definition of the failed cycle in its 64-bit
machine-check type register (MCTR)
Software can read the MCAR and MCTR registers in the
exception handling routine with the RDMSR instruction, as
described on page 90. The format of the registers is shown in
Figures 20 and 21.
If system software has cleared the MCE bit in CR4 to 0 before a
bus-cycle error, the processor attempts to continue execution
without generating a machine-check exception. The processor
still latches the address and cycle type in MCAR and MCTR as
described in this section.
4-Mbyte Pages
60
The TLBs in the 486 and 386 processors support only 4-Kbyte
pages. However, large data structures, such as a video frame
buffer or non-paged operating system code, can consume many
pages and easily overrun the TLB. The AMD-K5 processor
accommodates large data structures by allowing the operating
system to specify 4-Mbyte pages as well as 4-Kbyte pages, and
by implementing a four-entry, fully-associative 4-Mbyte TLB
that is separate from the 128-entry, 4-Kbyte TLB. From a given
page directory, the processor can access both 4-Kbyte pages
and 4-Mbyte pages, and the page sizes can be intermixed within
a page directory. When the Page Size Extension (PSE) bit in
CR4 is set, the processor translates linear addresses using
either the 4-Kbyte TLB or the 4-Mbyte TLB, depending on the
state of the page size (PS) bit in the page-directory entry.
Figures 14 and 15 show how 4-Kbyte and 4-Mbyte page
translations work.
AMD-K5™ Processor
AMD~
Preliminary Information
AMD K86™ Family BIDS and Software Tools Developers Guide
21062E!O-June 1997
Page
Directory
4-Kbyte
Page
Frame
Page
Table
r--+
PTE
r---
~
r+
I
CR3
POE
Physical
Address
I'--
•I
31
22 21
Page-Directory
Offset
12 11
Page-Table
Offset
0
Page
Offset
Linear Address
Figure 14. 4-Kbyte Paging Mechanism
AMD-K5™ Processor
61
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
4-Mbyte Page
Frame
1
1
.
-r
Page
Directory
)
:
-.
r--+
I
CR3
PDE
Physical
Address
-
I
I
31
22 21
0
Page-Directory
Offset
Page
Offset
Linear Address
Figure 15. 4-Mbyte Paging Mechanism
To enable the 4-Mbyte paging option:
1. Set the Page Size Extension (PSE) bit in CR4 to 1.
2. Set the Page Size (PS) bit in the page-directory entry to 1.
3. Write the physical base addresses of 4-Mbyte pages in bits
31-22 of page-directory entries. (Bits 21-12 of these entries
must be cleared to 0 or the processor generates a page
fault.)
4. Load CR3 with the base address of the page directory that
contains these page-directory entries.
62
AMD-K5™ Processor
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
Figure 13 and Table 19 show the fields in CR4. Figure 16 and
Table 20 show the fields in a page-directory entry.
4-Kbyte page translation differs from 4-Mbyte page translation
in the following ways:
•
•
4-Kbyte Paging (Figl:;ire 14)-Bits 31-22 of the linear address
select an entry in a 4-Kbyte page directory in memory,
whose physical base address is stored in CR3. Bits 21-12 of
the linear address select an entry in a 4-Kbyte page table in
memory, whose physical base address is specified by bits
31-22 of the page-directory entry. Bits 11-0 of the linear
address select a byte in a 4-Kbyte page, whose physical base
address is specified by the page-table entry.
4-Mbyte Paging (Figure 15)-Bits 31-22 of the linear address
select an. entry in a 4-Mbyte page directory in memory,
whose physical base address is stored in CR3. Bits 21-0 of
the linear address select a byte in a 4-Mbyte page in
memory, whose physical base address is specified by bits
31-22 of the page-directory entry. Bits 21-12 of the
page-directory entry must be cleared to O.
31
12 11 10 9 8 7
Table Base Address
Symbol
AVL
G
PS
A
peD
PWT
U/S
W/R
P
Description
Available to Software
Global
Page Size 0 = 4 Kbytes
Reserved =0
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
A
V
L
P
G S
6 5 4 3
A
2
1 0
P P U W
W / / P
D T S R
e
l~----,IIII
5
4
3
2
o
Figure 16. Page-Directory Entry (POE)
AMD-KSTM Processor
63
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Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
Table 20. Page-Diredory Entry (PDE) Fields
Bit
Mnemonic
31-12
BASE
11-9
AVL
8
7
G
PS
6
0
5
A
·4
PCD
3
PWT
2
U/S
W/R
P
1
0
Description
Function
For 4-Kbyte pages, bits 31-12 contain the physical base address of
a 4-Kbyte page table.
Physical Base Address For 4-Mbyte pages, bits 31-22 contain the physical base address of
a 4-Mbyte page and bits 21-12 must be cleared to O. (The
processor generates a page fault if bits 21-12 are not cleared to 0.)
Software may use this field to store any type of information. When
Available to Software the page-directory entry is not present (P bit cleared), bits 31-1
become available to software.
Global*
0== local, 1 == global.
Page Size
o== 4-Kbyte, 1 == 4-Mbyte.
For 4-Kbyte pages, this bit is undefined and ignored. The
processor does not change it.
o== not written, 1 == written.
Dirty
For 4-Mbyte pages, the processor sets this bit to 1 during a write
to the page that is mapped by this page-directory entry.
o== not written, 1 == written.
The processor sets this bit to 1 during a read or write to any page
that is mapped by this page-directory entry.
Accessed
o== not read or written, 1 == read or written.
Specifies cacheability for all pages mapped by this page-directory
entry. Whether a location in a mapped page is actually cached
Page Cache Disable
also depends on several other factors.
0== cacheable page, 1 == non-cacheable.
. Specifies writeback or writethrough cache protocol for all pages
mapped by this page-directory entry. Whether a location in a
mapped page is actually cached in a writeback or writethrough
Page Writethrough
state also depends on several other factors.
o== writeback page, 1 == writethrough page.
User/Supervisor
0== user (any CPL), 1 == supervisor (CPL < 3).
o== read or execute, 1 == write, read, or execute.
Write/Read
Present
0== not valid, 1 == valid.
Note:
*
64
The AMD-K5 processor supports global paging only on Models I, 2, and 3, with a Stepping of 4 or greater.
AMD-K5™ Processor
Preiiminory informotion
21062E/O-June 1997
Global Pages
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
The AMD-K5 processor supports global paging only on Models
1,2, and 3, with a Stepping of 4 or greater.
The processor's performance can sometimes be improved by
making some pages global to all tasks and procedures. This can
be done for both 4-Kbyte pages and 4-Mbyte pages.
The processor invalidates (flushes) both the 4-Kbyte TLB and
the 4-Mbyte TLB whenever CR3 is loaded with the base address
of the new task's page directory. The processor loads CR3
automatically during task switches, and the operating system
can load CR3 at any other time. Unnecessary invalidation of
certain TLB entries can be avoided by specifying those entries
as global (a global TLB entry references a global page). This
improves performance after TLB flushes. Global entries remain
in the TLB and need not be reloaded. For example, entries may
reference operating system code and data pages that are
always required. The processor operates faster if these entries
are retained across task switches and procedure calls.
To specify individual pages as global:
1. Set the Global Page Extension (GPE) bit in CR4.
2. (Optional) Set the Page Size Extension (PSE) bit in CR4.
3. Set the relevant Global (G) bit for that page:
For 4-Kbyte pages-Set the G bit in both the page-directory
entry (shown in Figure 16 and Table 20) and the page-table
entry (shown in Figure 17 and Table 21).
For 4-Mbyte pages-(Optional) After the PSE bit in CR4 is
set, set the G bit in the page-directory entry (shown in
Figure 16 and Table 20).
4. Load CR3 with the base address of the page directory.
The INVLPG instruction clears both the V and G bits for the
referenced entry. To invalidate all entries in both TLBs,
including global-page entries:
1. Clear the Global Page Extension (GPE) bit in CR4.
2. Load CR3 with the base address of another (or same) page
directory.
AMD-K5™ Processor
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AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
31
22 21
12 11 10 9
Physical Page Base Address
Symbol
AVL
G
PS
A
PCD
PWT
U/S
W/R
P
Description
Available to Software
Global
Page Size 1= 4 Mbytes
Reserved =0
Accessed
Page Cache Disable
Page Writethrough
User/Supervisor
Write/Read
Present (valid)
21 062E/O- June 1997
Reserved
A
V
L
8
7
P
G S
6
5
4
3
2
1 0
P P U W
A C W / / P
D T S R
4
3
2
1
o
Figure 17. Page-Table Entry (PTE)
Table 21. Page-Table Entry (PTE) Fields
Bit
31-12
11-9
8
7
6
5
4
Description
Function
Mnemonic
BASE
Physical Base Address The physical base address of a 4-Kbyte page.
Software may use the field to store any type of information.
Available to Software When the page-table entry is not present (P bit cleared), bits 31-1
AVL
become available to software.
Global*
o= local, 1 = global.
G
This bit is ignored in page-table entries, although clearing it to 0
Page Size
preserves consistent usage of this bit between page-table and
PS
page-directory entries.
The processor sets this bit to 1 during a write to the page that is
mapped by this page-table entry.
Dirty
D
o= not written, 1 = written.
The processor sets this bit to 1 during a read or write to any page
that is mapped by this page-table entry.
Accessed
A
o= not read or written, 1 = read or written.
Specifies cacheability for all locations in the page mapped by this
page-table entry. Whether a location is actually cached also
PCD
Page Cache Disable
depends on several other factors.
0= cacheable page, 1 = non-cacheable.
Note:
*
66
The AMD-K5 processor supports global paging only on Models 1, 2, and 3, with a Stepping of 4 or greater.
AMD-K5™ Processor
Preliminary Information
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 21. Page-Table Entry (PTE) Fields (continued)
Bit
Mnemonic
3
PWT
Description
Page Writethrough
Function
Specifies writeback or writethrough cache protocol for alllocations in the page mapped by this page-table entry. Whether a
location is actually cached in a write back or writethrough state
also depends on several other factors.
o= write back, 1 = writethrough.
2
1
0
U/S
W/R
P
User/Supervisor
Write/Read
Present
0= user (any CPL), 1 = supervisor (CPL < 3).
o= read or execute, 1 = write, read, or execute.
o= not valid, 1 = valid.
Note:
*
The AMD-K5 processor supports global paging only on Models 1, 2, and 3, with a Stepping of 4 or greater.
Virtual-8086 Mode
Extensions (VME)
The Virtual-8086 Mode Extensions (VME) bit in CR4 (bit 0)
enable performance enhancements for 8086 programs running
as protected tasks in Virtual-8086 mode. These extensions
include:
•
•
Virtualizing maskable external interrupt control and
notification via the VIF and VIP bits in EFLAGS
Selectively intercepting software interrupts (INTn
instructions) via the Interrupt Redirection Bitmap (IRB) in
the Task State Segment (TSS)
Interrupt Redirection in Virtual-SOS6 Mode Without VME Extensions. 808 6
. programs expect to have full access to the interrupt flag (IF) in
the EFLAGS register, which enables maskable external
interrupts via the INTR signal. When 8086 programs run in
Virtual-8086 mode on a 386 or 486 processor, they run as
protected tasks and access to the IF flag must be controlled by
the operating system on a task-by-task basis to prevent
corruption of system resources.
Without the VME extensions available on the AMD-KS
processor, the operating system controls Virtual-8086 mode
access to the IF flag by trapping instructions that can read or
write this flag. These instructions include STI, CLI, PUSHF,
POPF, INTn, and IRET. This method prevents changes to the
real IF when the 1/0 privilege level (IOPL) in EFLAGS is less
than 3, the privilege level at which all Virtual-8086 tasks run.
The operating system maintains an image of the IF flag for each
Virtual-8086 program by emulating the instructions that read
or write IF. When an external maskable interrupt occurs, the
AMD-K5™ Processor
67
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Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO-June 1997
operating system checks the state of the IF image for the
current Virtual-8086 program to determine whether the
program is allowing interrupts. If the program has disabled
interrupts, the operating system saves the interrupt
information until the program attempts to re-enable interrupts.
The overhead for trapping and emulating the instructions that
enable and disable interrupts and the maintenance of virtual
interrupt flags for each Virtual-8086 program can degrade the
processor's performance. This performance can be regained by
running Virtual-8086 programs with IOPL set to 3, thus
allowing changes to the real IF flag from any privilege level,
but with a loss in protection.
In addition to the performance overhead caused by
virtualization of the IF flag in Virtual-8086 mode, software
interrupts (those caused by INTn instructions that vector
through interrupt gates) cannot be masked by the IF flag or
virtual copies of the IF flag. These flags only affect hardware
interrupts. Software interrupts in Virtual-8086 mode are
normally directed to the Real mode interrupt vector table
(IVT), but it may be desirable to redirect interrupts for certain
vectors to the Protected mode interrupt descriptor table (IDT).
The processor's Virtual-8086 mode extensions support both of
these cases-hardware (external) interrupts and software
interrupts-with mechanisms that preserve high performance
without compromising protection. Virtualization of hardware
interrupts is supported via the Virtual Interrupt Flag (VIF) and
Virtual Interrupt Pending (VIP) flag in the EFLAGS register.
Redirection of software interrupts is supported with the
Interrupt Redirection Bitmap (IRB) in the TSS of each
Virtual-8086 program.
Hardware Interrupts and the VIF and VIP Extensions.
When VME extensions are enabled, the IF-modifying
instructions that are normally trapped by the operating system
are allowed to execute, but they write and read the VIF bit
rather than the IF bit in EFLAGS. This operation leaves
maskable interrupts enabled for detection by the operating
system. It also indicates to the operating system whether the
Vir.tual-8086 program is able to, or expecting to, receive
interrupts.
68
AMD-K5™ Processor
Preliminary Information
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When an external interrupt occurs, the processor switches from
the Virtual-8086 program to the operating system, in the same
manner as on a 386 or 486 processor. If the operating system
determines the interrupt is for the Virtual-8086 program, it
checks the state of the VIF bit in the program's EFLAGS image
on the stack. If VIF has been set by the processor (during an
attempt by the program to set the IF bit), the operating system
permits access to the appropriate Virtual-8086 handler via the
interrupt vector table (IVT). If VIF has been cleared, the
operating system holds the interrupt pending. The operating
system can do this by saving appropriate information (such as
the interrupt vector), setting the program's VIP flag in the
EFLAGS image on the stack, and returning to the interrupted
program. When the program subsequently attempts to set IF,
the set VIP flag causes the processor to inhibit the instruction
and generate a general-protection exception with error code
zero, thereby notifying the operating system that the program
is now prepared to accept the interrupt.
Thus, when VME extensions are enabled, the VIF and VIP bits
are set and cleared as follows:
•
•
VIP-This bit is controlled by the processor and used by the
operating system to determine whether an external
maskable interrupt should be passed on to the program or
held pending. VIF is set and cleared for instructions that can
modify IF, and it is cleared during software interrupts
through interrupt gates. The original IF value is preserved
in the EFLAGS image on the stack.
VIP-This bit is set and cleared by the operating system via
the EFLAGS image on the stack. It is set when an interrupt
occurs for a Virtual-8086 program whose VIF bit is cleared.
The bit is checked by the processor when the program
subsequently attempts to set VIF.
Figure 18 and Table 22 show the VIF and VIP bits in the
EFLAGS register. The VME extensions support conventional
emulation methods for passing interrupts to Virtual-8086
programs, but they make it possible for the operating system to
avoid time-consuming emulation of most instructions that write
or read the IF.
The VIF and IF flags only affect the way the operating system
deals with hardware interrupts (the INTR signal). Software
interrupts are handled like machine-generated exceptions and
AMD-KSTM Processor
69
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
cannot be masked by real or virtual copies of IF (See "Software
Interrupts and the Interrupt Redirection' Bitmap (IRB)
Extension" on page 75). The VIF and VIP flags only ease the
software overhead associated with managing interrupts so that
virtual copies of the IF flag do not have to be maintained by the
operating system. Instead, each task's TSS holds its own copy of
these flags in its EFLAGS image.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
v V
I I I A V R
D P F C M F
D --.. Reserved
01
~
ID
VIP
VIF
AC
VM
RF
NT
10PL
OF
DF
IF
TF
SF
ZF
AF
PF
CF
N
T
I
0
P
L
0 D I T S Z
F F F F F F
A
F
P
F
C
F
lr~
Description
ID Flag
Virtual Interrupt Pending
Virtual Interrupt Flag
Alignment Check
18
Virtual-8086 Mode
17
Resume Fla g
16
Nested Task
14
I/O Privilege Level
13-12 - - - - - - - - - - '
.Overflow Flag
11
Direction Flag
10
Interrupt Flag
9
Trap Flag
8
Sign Flag
7
Zero Flag
6
Auxiliary Flag
4
Parity Flag
2
Carry Flag
o
Figure 18. EFLAGS Register
70
AMD-KSTM Processor
AM D~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
Table 22. Virtual-Interrupt Additions to EFLAGS Register
Bit
Mnemonic
20
VIP
Virtual Interrupt
Pending
19
VIF
Virtual Interrupt Flag
Description
Function
Set by the operating system (via the EFLAGS image on the stack)
when an external maskable interrupt (INTR) occurs for a
Virtual-8086 program whose VIF bit is cleared. The bit is checked
by the processor when the program subsequently attempts to
set VIF.
When the VME bit in CR4 is set, the VIF bit is modified by the
processor when a Virtual-8086 program running at less privilege
than the IOPl attempts to modify the IF bit. The VIF bit is used by
the operating system to determine whether a maskable interrupt
should be passed on to the program or held pending.
Tables 23 through 27 show the effects, in various x86-processor
modes, of instructions that read or write the IF and VIF flag.
The column headings in this table include the following values:
•
•
•
•
•
•
•
•
•
PE-Protection Enable bit in CRO (bit 0)
VM- Virtual-8086 Mode bit in EFLAGS (bit 17)
VME-Virtual Mode Extensions bit in CR4 (bit 0)
PVI-Protected-mode Virtual Interrupts bit in CR4 (bit 1)
IOPL-I/O Privilege Level bits in EFLAGS (bits 13-12)
Handler CPL-Code Privilege Level of the interrupt handler
GP(O) -General-protection exception, with error code = 0
IF-Interrupt Flag bit in EFLAGS (bit 9)
VIF- Virtual Interrupt Flag bit in EFLAGS (bit 19)
Table 23. Instructions that Modify the IF or VIF Flags-Real Mode
TYPE
CLI
STI
PUSHF
POPF
IRET
PE
0
0
0
0
0
VM
0
0
0
0
0
VME
0
0
0
0
0
PVI
0
0
0
0
0
IOPL
-
-
GP(O)
No
No
No
No
No
IF
VIF
IF~O
-
IF~1
-
Pushed
Popped
Popped
-
Note:
H_
H
Not applicable.
AMD-K5™ Processor
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Table 24. Instructions that Modify the IF or VIF Flags-Protected Mode
TYPE
PE
VM
VME
Cli
1
0
Cli
1
0
STI
1
0
STI
1
0
PUSHF
1
0
PUSHF
1
0
PUSHFD
1
0
-
0
~
PUSHFD
1
0
-
0
< CPL
-
0
~
0
< CPl
0
~
POPF
1
0
POPF
1
0
POPFD
1
0
PVI
IOPL
Handler
CPL
GP(O)
IF
VIF
0
~
CPL
-
No
IF~O
0
< CPL
-
Yes
-
-
0
~
-
No
IF~l
-
Yes
-
No
Pushed
-
No
Pushed
-
No
Pushed
Pushed
No
Pushed
Pushed
No
Popped
-
No
Not Popped
-
No
Popped
Not Popped
Not Popped
CPL
0
< CPL
0
~
0
< CPL
CPL
CPL
CPL
CPl
POPFD
1
0
-
0
< CPL
-
No
Not Popped
IRET
1
0
-
0
-
=0
No
Popped
-
IRET
1
0
-
0
~
CPl
>0
No*
Popped
-
IRET
1
0
<CPL
>0
No*
Not Popped
-
1
0
0
-
=0
No
Popped
Popped
IRETD
1
0
IRETD
Notes:
1
0
-
0
IRETD
0
~
CPL
>0
No*
Popped
Not Popped
0
<CPl
>0
No*
Not Popped
Not Popped
* GP(O), if the (PL of the task executing IRETD is greater than the (PL of the task to which it is returning.
"-" Not applicable.
72
AMD-KSTM Processor
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Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 25. Instructions that Modify the IF or VIF Flags-Virtual-8086 Mode
PE
VM
VME
PVI
IOPL
GP(O)
IF
VIF
CLI
TYPE
1
1
0
-
3
No
IF~O
No Change
CLI
1
1
0
-
<3
Yes
-
-
5TI
1
1
0
1
1
0
PU5HF
1
1
0
-
No Change
5TI
PU5HF
1
1
0
PU5HFD
1
1
0
PU5HFD
1
1
0
POPF
1
1
0
POPF
1
1
0
POPFD
1
1
0
POPFD
1
1
0
IRETD2
1
1
0
3
No
IF~l
<3
Yes
-
-
3
No
Pushed
<3
Yes
-
-
3
No
Pushed
Pushed
<3
Yes
-
-
3
No
Popped
<3
Yes
-
-
3
No
Popped
Not Popped
<3
Yes
-
-
-
No
Popped
Popped
Notes:
1. All Virtual-8086 mode tasks run at CPL =3.
2. All protected virtual interrupt handlers run at CPL
"_" Not applicable.
AMD-KSTM Processor
=o.
73
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Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
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Table 26. Instructions that Modify the IF or VIF Flags-Virtual-SOS6 Mode Interrupt
Extensions (VMEr
TYPE
IOPL
GP(O)
-
3
-
<3
PVI
IF
VIF
No
IF~O
No Change
No
No Change
PE
VM
VME
CLI
1
1
1
CLI
1
1
1
3
No
<3
No 3
No Change
VIF~l
3
No
Pushed
Not Pushed
<3
No
Not Pushed
Pushed into IF
3
No
Pushed
Pushed
<3
Yes
-
-
Popped
Not Popped
STI
1
1
1
-
STI
1
1
1
PUSHF
1
1
1
PUSHF
1
1
1
PUSHFD
1
1
1
PUSHFD
1
1
POPF
1
1
1
-
POPF
1
1
1
POPFD
1
1
1
1
IF~
1
VIF~O
No Change
3
No
<3
No
3
No
Popped
Not Popped
<3
Yes
-
-
Popped
Not Popped
POPFD
1
1
1
-
IRET from
V8G Mode
1
1
1
-
3
No
IRET from
V8G Mode
1
1
1
-
<3
No 3
IRETD from
V8G Mode
1
1
1
-
3
No
Popped
Not Popped
IRETD from
V8G Mode
1
1
1
-
<3
Yes
-
-
1
1
1
-
-
No3
Popped
Popped
IRETD from
Protected Mode2
Notes:
T.
2.
3.
" - 1/
74
Not Popped Popped from IF
Not Popped Popped from IF
All Virtual-8086 mode tasks run at (PL = 3.
All protected virtual interrupt handlers run at (PL = o.
CP(O) if an attempt is made to set VIF when VIP = T.
Not applicable.
AMD-K5™ Processor
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
Table 27. Instructions that Modify the IF or VIF Flags-Protected Mode Virtual
Interrupt Extensions (PVW
PE
VM
VME
PVI
IOPL
GP(O)
IF
VIF
CLI
TYPE
1
0
3
No
IF f-- 0
No Change
CLI
1
0
1
<3
No
No Change
VIF f-- 0
STI
1
0
-
1
1
3
No
IF f-- 1
No Change
STI
1
0
-
1
<3
No'
No Change
VIF f-- 1
PUSHF
1
0
-
1
3
No
Pushed
Not Pushed
PUSHF
1
0
-
1
<3
No
Pushed
Not Pushed
Pushed
PUSHFD
1
0
3
No
Pushed
1
0
-
1
PUSHFD
1
<3
No
Pushed
Pushed
POPF
1
0
-
1
3
No
Popped
Not Popped
POPF
1
0
-
1
<3
No
Not Popped
Not Popped
POPFD
1
0
-
1
3
No
Popped
Not Popped
POPFD
1
0
-
1
<3
No
Not Popped
Not Popped
IRETDl
Notes:
1
0
-
1
-
No'
Popped
Popped
1. All Protected mode virtual interrupt tasks run at (PL =3.
2. All protected mode virtual interrupt handlers run at (PL =O.
3. CP(O) if an attempt is made to set
when VIP =1.
"_" Not applicable.
vir
Software Interrupts and the Interrupt Redirection Bitmap (IRB) Extension.
In Virtual-8086 mode, software interrupts (INTn exceptions
that vector through interrupt gates) are trapped by the
operating system for emulation because they would otherwise
clear the real IF. When VME extensions are enabled, these
INTn instructions are allowed to execute normally, vectoring
directly to a Virtual-8086 service routine via the Virtual-8086
interrupt vector table (IVT) at address 0 of the task address
space. However, it may still be desirable for security or
performance reasons to intercept INTn instructions on a
vector-specific basis to allow servicing by Protected-mode
routines accessed through the interrupt descriptor table (IDT).
This is accomplished by an Interrupt Redirection Bitmap (IRB)
in the TSS, which is created by the operating system in a
manner similar to the 10 Permission Bitmap (IOPB) in the !SS.
AMD-KSTM Processor
75
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Figure 19 shows the format of the TSS with the Interrupt
Redirection Bitmap near the top. The IRB contains 256 bits, one
for each possible software-interrupt vector. The
most-significant bit of the IRB is located immediately below the
base of the IOPB. This bit controls interrupt vector 255. The
least-significant bit of the IRB controls interrupt vector O.
The bits in the IRB work as follows:
•
•
Set-If set to 1, the INTn instruction behaves as if the VME
extensions are not enabled. The interrupt vectors to a
Protected-mode routine if IOPL = 3, or it causes a
general-protection exception with error code zero if IOPL<3.
Cleared-If cleared to 0, the INTn instruction vectors
directly to the corresponding Virtual-8086 service routine
via the Virtual-8086 program's IVT.
Only software interrupts can be redirected via the IRB to a
Real mode IVT-hardware interrupts cannot. Hardware
interrupts are asynchronous events and do not belong to any
current virtual task. The processor thus has no way of deciding
which IVT (for which Virtual-8086 program) to direct a
hardware interrupt to. Hardware interrupts, therefore, always
require operating system intervention. The VIF and VIP bits
described in "Hardware Interrupts and the VIF and VIP
Extensions" on page 68 are provided to assist the operating
system in this intervention.
76
AMD-K5™ Processor
AM Dl1
Preliminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
o
31
1
j
I/O Permission Bitmap (lOPB)
(up to 8 Kbytes)
TSSLimit
fromTR
Interrupt Redirection Bitmap (lRB)
(eight 32-bit locations)
Operating System
Data Structure
r-
Base Address of 10PB
ooooh
ooooh
LDT Selector
ooooh
GS
FS
ooooh
OOOoh
IT
64h
DS
SS
CS
ooooh
ooooh
OOOoh
ES
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
EFLAGS
EIP
CR3
552
ooooh
ESP2
ooooh
551
ESP1
OOOOh
550
ESPO
ooooh
Link (Prior TSS Selector)
o
Figure 19. Task State Segment (TSS)
AMD-K5™ Processor
77
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
Table 28 compares the behavior of hardware and software
interrupts in various x86-processor operating modes. It also
shows which interrupt table is accessed: the Protected-mode
IDT or the Real- and Virtual-8086-mode IVT. The column
headings in this table include:
•
•
•
•
•
•
•
•
•
PE-Protection Enable bit in CRO (bit 0)
Vl\1- Virtual-8086 Mode bit in EFLAGS (bit 17)
Vl\1E- Virtual Mode Extensions bit in CR4 (bit 0)
PVI-Protected-Mode Virtual Interrupts bit in CR4 (bit 1)
IOPL-I10 Privilege Level bits in EFLAGS (bits 13-12)
IRB-Interrupt Redirection Bit for a task, from the
Interrupt Redirection Bitmap (IRB) in the tasks TSS
GP(O)-General-protection exception, with error code = 0
IDT-Protected-Mode Interrupt Descriptor Table
IVT-Real- and Virtual-8086 Mode Interrupt Vector Table
Table 28. Interrupt Behavior and Interrupt-Table Access
Mode
Interrupt
Type
Software
Hardware
Software
Protected mode
Hardware
Software
Virtual-SOS6
Software
mode*
Hardware
Software
Virtual-SOS6
Software
Mode Extensions
Software
(VME)*
Hardware
Software
Protected Virtual
Extensions (PVJ) Hardware
Real mode
PVI
IOPL
IRB
GP(O)
IDT
IVY
0
-
0
-
-
0
-
-
-
0
.t
.t
0
0
-
-
-
.I
1
0
0
-
1
1
0
-
=3
-
1
1
0
-
<3
No
Yes
No
No
No
Yes
No
No
No
.t
.t
.t
PE
VM
VME
0
0
0
0
1
1
1
0
-
-
-
1
1
1
0
-
0
1
1
1
0
=3
1
1
1
1
0
<3
1
1
1
1
0
1
0
1
1
1
0
1
1
-
-
-
.I
-
-
.t
.t
.t
.t
.t
.t
-
-
Notes:
All Virtual-8086 tasks run at CPL =3.
"-" Not applicable.
*
78
AMD-K5™ Processor
Preliminary Information
AMD K86™ Family BIDS and Software Tools Developers Guide
21062EjO-June 1997
Protected Virtual
Interrupt (PVI)
Extensions
AMD~
The Protected Virtual Interrupts (PVI) bit in CR4 enables
support for interrupt virtualization in Protected mode. In this
virtualization, the processor maintains program-specific VIF
and VIP flags in a manner similar to those in Virtual-8086 Mode
Extensions (VME). When a program is executed at CPL = 3, it
can set and clear its copy of the VIF flag without causing
general-protection exceptions.
The only differences between the VME and PVI extensions are
that, in PVI, selective INTn interception using the Interrupt
Redirection Bitmap in the TSS does not apply, and only the STI
and CLI instructions are affected by the extension.
Tables 23 through 28 show, among other things, the behavior of
hardware and software interrupts as well as instructions that
affect interrupts in Protected mode with the PVI extensions
enabled.
Model-Specific Registers (MSRs)
The processor supports MSRs that can be accessed with the
RDMSR and WRMSR instructions when CPL = o. The following
index values in the ECX register access specific MSRs:
•
•
•
•
•
•
•
Machine-Check Address Register (MCAR)-ECX =OOh
Machine-Check Type Register (MCTR)-ECX =Olh
Time Stamp Counter (TSC)-ECX = 10h
Array Access Register (AAR)-ECX = 82h
Hardware Configuration Register (HWCR)-ECX = 83h
Write Allocate Top-of-Memory and Control Register
(WATMCR)-ECX = 85h
Write Allocate Programmable Memory Range Register
(WAPMRR)-ECX =86h
Note: The AMD-K5 processor supports write allocate only on
Models 1, 2, and 3, wi,th a Stepping of 4 or greater.
The RDMSR and WRMSR instructions are described on page
90. The following sections describe the format of the registers.
AMD-KSTM Processor
79
AM D l1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
Machine-Check
Address Register
(MCAR)
21062EjO-June 1997
The processor latches the address of the current bus cycle in its
64-bit Machine-Check Address Register (MCAR) when a
bus-cycle error occurs. These errors are indicated either by (a)
system logic asserting BUSCHK, or (b) the processor asserting
PCHK while system logic asserts PEN.
The MCAR can be read with the RDMSR instruction when the
ECX register contains the value OOh. Figure 20 shows the
format of the MCAR register. The contents of the register can
be read with the RDMSR instruction.
If system software has set the MCE bit in CR4 before the
bus-cycle error, the processor also generates a machine-check
exception as described on page 60.
o
63
Physical Address of Last Failed Bus Cycle
Figure 20. Machine-Check Address Register (MCAR)
Machine-Check Type
Register (MCTR)
The processor latches the cycle definition and other
information about the current bus cycle in its 64-bit
Machine-Check Type Register (MCAR) at the same times that
the Machine-Check Address Register (MCAR) latches the cycle
address-when a bus-cycle error occurs. These errors are
indicated either by (a) system logic asserting BUSCHK, or (b)
the processor asserting PCHK while system logic asserts PEN.
The MCTR can be read with the RDMSR instruction when the
ECX register contains the value 01h. Figure 21 and Table 29
show the formats of the MCTR register. The contents of the
register can be read with the RDMSR instruction. The
processor clears the CHK bit (bit 0) in MCTR when the register
is read with the RDMSR instruction.
If system software has set the MCE bit in CR4 before the
bus-cycle error, the processor also generates a machine-check
exception as described on page 60.
80
AMD-K5™ Processor
AM Dl1
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E!O-June 1997
63
5 4
0-. Reserved
Symbol
LOCK
MilO
Description
Locked Cycle
Memory or I/O Cycle
Data or Code Cycle
Write or Read Cycle
Valid Machine-Check Data
DIC
WIR
CHK
3
2
1 0
r-----IIIII
o
Figure 21. Machine-Check Type Register (MCTR)
Table 29. Machine-Check Type Register (MCTR) Fields
Bit
Mnemonic
4
LOCK
Locked Cycle
Set to 1 if the processor was asserting LOCK# during the bus cycle.
3
M/IO#
Memory or I/O
1 =memory cycle, 0 =I/O cycle
2
D/C#
Data or Code
1 =data cycle, 0 =code cycle
1
W/R#
Write or Read
1 =write cycle, 0 =read cycle
CHK
The processor sets the CHK bit to 1 when both the MCTR and MCAR
Valid Machine-Check
registers contain valid information. The processor clears the CHK bit to
Data
owhen software reads the MCTR with the RDMSR instruction.
0
Description
Time Stamp Counter
(TSC)
Function
With each processor clock cycle, the processor increments a
64-bit time stamp counter (TSC) MSR. The counter can be
written or read using the WRMSR or RDMSR instructions when
the ECX register contains the value lOh and CPL = O. The
counter can also be read using the RDTSC instruction (see
page 89), but the required privilege level for this instruction is
determined by the Time Stamp Disable (TSD) bit in CR4. With
any of these instructions, the EDX and EAX registers hold the
upper and lower doublewords (dwords) of the 64-bit value to be
written to or read from the TSC, as
follows:
• EDX- Upper 32 bits of TSC
• EAX-Lower 32 bits of TSC
The TSC can be loaded with any arbitrary value.
AMD-KSTM Processor
81
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
Array Access Register
(AAR)
21 062E/O- June 1997
The Array Access Register (AAR) contains pointers for testing
the tag and data arrays for the instruction cache, data cache,
4-Kbyte TLB, and 4-Mbyte TLB. The AAR can be written or
read with the WRMSR or RDMSR instruction when the ECX
register contains the value 82h.
For details on the AAR, see "Cache and TLB Testing" on
page 27.
Hardware
Configuration
Register (HWCR)
The Hardware Configuration Register (HWCR) contains
configuration bits that control miscellaneous debugging
functions. The HWCR can be written or read with the WRMSR
or RDMSR instruction when the ECX register contains the
value 83h.
For details on the HWCR, see "Hardware Configuration
Register (HWCR)" on page 22.
Write Allocate
Registers
The AMD-KS processor supports write allocate only on Models
1, 2, and 3, with a Stepping of 4 or greater. Use the CPUID
instruction to determine if the proper revision of the processor
is present (See the AMD Processor Recognition Application Note,
order# 20734, located at http://www.amd.com.).
Two MSRs are defined to support write allocate. The MSRs are
accessed using the RDMSR and WRMSR instructions (see
"RDMSR and WRMSR" of the AMD-KSTM Processor Software
Development Guide, order# 20007). The following index values
in the ECX register access the MSRs:
•
•
Write Allocate Top-of-Memory and Control Register
(WATMCR)-ECX= 8Sh
Write Allocate Programmable Memory Range Register
(WAPMRR)-ECX = 86h
For more information about write allocate, see the
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326.
Three non-write-allocatable memory ranges are defined for use
with the write allocate feature-one fixed range and two
programmable ranges.
82
AMD-K5™ Processor
Preliminary Information
21062E/O-June 1997
AM 0 11
AMD KB6™ Family BIOS and Software Tools Developers Guide
Fixed Range. The fixed memory range is OOOA_OOOOhOOOF_FFFFh and can be enabled or disabled. When enabled,
write allocate can not be performed in this range.
This region of memory, which includes standard VGA and other
peripheral and BIOS access, is considered non-cache able.
Performing a write allocate in this area can cause compatibility
problems. It is recommended that this bit be enabled (set to 1)
to prevent write allocate to this range. Set bit 16 of WATMCR
to enable protection of this range.
Programmable Range. One programmable memory range is
xxxx_OOOOh-yyyy_FFFFh, where xxx x and yyyy are defined
using bits 15-0 and bits 31-16 of WAPMRR, respectively. Set
bit 17 of WATMCR to enable protection of this range. When
enabled, write allocate can not be performed in this range.
This programmable memory range exists because a small
number of uncommon memory-mapped liD adapters are
mapped to physical RAM locations. If a card like this exists in
the system configuration, it is recommended that the BIOS
program the 'memory hole' for the adapter into this
non-write-allocatable range.
Top of Memory. The other programmable memory range is
defined by the 'top-of-memory' field. The top of memory is
equal to zzzz_OOOOh, where zzzz is defined using bits 15-0 of
WATMCR. Addresses above zzzz_OOOOh are protected from
write allocate when bit 18 of WATMCR is enabled.
Once the BIOS determines the size of RAM installed in the
system, this size should also be used to program the top of
memory. For example, a system with 32 Mbytes of RAM
requires that the top-of-memory field be programmed with a
value of 0200h, which enables protection from write allocate
for memory above that value. Set bit 18 of WATMCR to enable
protection of this range.
Caching and write allocate are generally not performed for the
memory above the amount of physical RAM in the system.
Video frame buffers are usually mapped above physical RAM.
If write allocate were attempted in that memory area, there
could be performance degradation or compatibility problems.
AMD-K5™ Processor
8J
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E!O- June 1997
Bits 18-16 of WATMCR control the enabling or disabling of the
three memory ranges as follows:
•
Bit 18: Top-of-Memory Enable bit
o = disabled (default)
1 = enabled (write allocate can not be performed above Top
of Memory)
•
Bit 17: Programmable Range Enable bit
0= disabled (default)
1 = enabled (write allocate can not be performed in this
range)
•
Bit 16: Fixed Range Enable bit
0= disabled (default)
1 = enabled (write allocate can not be performed in this
range)
Figures 22 and 23 show the bit positions for these two new
registers.
63
19 18 17 '16 15
°
Top of Memory-uzz
I
D -.. Reserved
Protection Control Bits
Top-of-Memory Enable
Programmable Range Enable
Fixed Range Enable
TME
PRE
FRE
:~====:JJ
16 _ _ _ _ _ _ _- . 1
Figure 22. Write Allocate Top-of-Memory and Control Register (WATMCR)-MSR 8sh
63
32 31
f
16 15
Programmable Range-yyyy
(High - yyyyJFFFh)
°
Programmable Range-xxxx
(Low - xxxx_OOOOh)
D -.. Reserved
Figure 23. Write Allocate Programmable Memory Range Register (WAPMRR)-MSR 86h
84
AMD-KSTM Processor
Pre/iminory Informotion
AM D~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
Enable Write Allocate
Write allocate is enabled by setting bit 4 (WA) of the HWCR to
1. For more information on the HWCR, see "Hardware
Configuration Register (HWCR)" on page 22. Figure 2 on page
23 shows the revised definition of the Hardware Configuration
Register.
New AMO-K5™ Processor Instructions
In addition to supporting all the 486 processor instructions, the
AMD-KS processor implements the following instructions:
AMD-K5™ Processor
•
•
•
CPUID
CMPXCHG8B
MOV to and from CR4
•
•
•
RDTSC
RDMSR
WRMSR
•
•
RSM
lllegal instruction (reserved opcode)
85
AMD~
Preliminary Information
AMD K86™ Family BIDS and Software Tools Developers Guide
21 062E/O- June 1997
CPUID
mnemonic
opcode
description
CPUID
OF A2h
Identify processor and its feature set
Privilege:
Any level
Registers Affected:
EAX,EBX,ECX,EDX
Flags Affected:
None
Exceptions Generated: None
The CPUID instruction is an application-level instruction that software executes to
identify the processor and its feature set. This instruction offers multiple functions,
each providing a different set of information about the processor. The CPUID
instruction can be executed from any privilege level. Software can use the
information returned by this instruction to tune its functionality for the specific
processor and its features.
Not all processors implement the CPUID instruction. Therefore, software must test to
determine if the instruction is present on the processor. If the ID bit (21) in the
EFLAGS register is write able, the CPUID instruction is implemented.
The CPUID instruction supports multiple functions. The information associated with
each function is obtained by executing the CPUID instruction with the function
number in the EAX register. Functions are divided into two types: standard functions
and extended functions. Standard functions are found in the low function space,
OOOO_0000h-7FFF _FFFFh. In general, all x86 processors have the same standard
function definitions.
Extended functions are defined specifically for processors supplied by the vendor
listed in the vendor identification string. Extended functions are found in the high
function space, 8000_0000h-8FFF _FFFFh. Because not all vendors have defined
extended functions, software must test for their presence on the processor.
For more detailed information refer to the AMD Processor Recognition Application
Note, order# 20734, located at http://www.amd.com.
86
AMD-K5™ Processor
Preliminary Information
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
CMPXCHGBB
mnemonic
opcode
description
CMPXCHG8B rjm64
OFC7h
Compare and exchange a-byte operand
Privilege:
Any level
EAX,EBX,ECX,EDX
Registers Affected:
Flags Affected:
ZF
Exceptions Generated:
Virtual
Exception
Invalid opcode (6)
Stack exception (12)
General protection (13)
Page fault (14)
Alignment check (17)
Real
X
8086
X
X
Protected
X
X
X
X
X
X
X
X
Description
Invalid opcode if destination is a register.
During instruction execution, the stack segment limit was exceeded.
During instruction execution, the effective address of one of the segment
registers used for the operand points to an illegal memory location.
Apage fault resulted from the execution of the instruction.
An unaligned memory reference resulted from the instruction execution,
and the alignment mask bit (AM) of the control register (CRO) is set to 1.
(In Protected Mode, CPL =3.)
The CMPXCHG8B instruction is an 8-byte version of the 4-byte CMPXCHG
instruction supported by the 486 processor. CMPXCHG8B compares a value from
memory with a value in the EDX and EAX register, as follows:
•
•
EDX - Upper 32 bits of compare value
EAX - Lower 32 bits of compare value
If the memory value matches the value in EDX and EAX, the ZF flag is set to 1 and the
8-byte value in ECX and EBX is written to the memory location, as follows:
•
•
ECX - Upper 32 bits of exchange value
EBX - Lower 32 bits of exchange value
AMD-K5™ Processor
87
AMD~
Preliminary Information
M
AMD KB6f Family BIOS and Software Tools Developers Guide
21 062E/O-June 1997
MOV to and from CR4
mnemonic
opcode
description
MOVCR4,r32
MOVr32,CR4
OF22h
OF20h
Move to CR4 from register
Move to register from CR4
Privilege:
CPL=O
Registers Affected:
CR4, 32-bit general-purpose register
Rags Affected:
OF, SF, ZF, AF, PF, and CF are undefined
Exceptions Generated:
Virtual
Exception
Real
8086
X
General protection (13)
X
Protected Description
X
If 1 is written to any reserved bits.
Executing this instruction in Virtual 8086 mode.
X
If CPL not =o.
These instructions read and write control register 4 (CR4).
BB
AMD-K5™ Processor
Pre/iminDry /nformDtion
AM D~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO- June 1997
RDTse
mnemonic
opcode
description
ROTSC
OF 31h
Read time stamp counter
Privilege:
Selectable by TSO bit in CR4
Registers Affected:
EAX,EOX
Flags Affected:
none
Exceptions Generated:
Virtual
Exception
Real
General protection (13)
8086
Protected Description
Executing this instruction in Virtual 8086 mode.
X
X
If CPL not =0 when TSO bit of CR4 =1.
The AMD-KS processor's 64-bit time stamp counter (TSC) increments on each
processor clock. In Real or Protected mode, the counter can be read with the RDMSR
instruction and written with the WRMSR instruction when CPL = O. However, in
Protected mode, the RDTSC instruction can be used to read the counter at privilege
levels higher than CPL =o.
The required privilege level for using the RDTSC instruction is determined by the
Time Stamp Disable (TSD) bit in CR4, as follows:
•
•
CPL =0 - Set the TSD bit in CR4 to 1
Any CPL - Clear the TSD bit in CR4 to
0
The RDTSC instruction reads the counter value into the EDX and EAX registers as
follows:
•
EDX - Upper 32 bits of TSC
•
EAX - Lower 32 bits of TSC
The following example shows how the RDTSC instruction can be used. After this code
is executed, EAX and EDX contain the time required to execute the RDTSC
instruction.
mov
mov
mov
db
db
db
ecx.l0h
eax.OOOOOOOOh
edx.OOOOOOOOh
OFh. 30h
OFh. 31h
OFh. 31h
AMD-K5TU Processor
;Time Stamp Counter Access via MSRs
;Initialize the eax part of the Counter to zero
;Initialize the edx part of the Counter to zero
;WRMSR
;RDTSC
;RDTSC
89
AMD~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/0-June 1997
RDMSR and WRMSR
mnemonic
opcode
description
RDMSR
WRMSR
OF32h
OF30h
Read model-specific register (MSR)
Write model-specific register (MSR)
Privilege:
CPl=O
Registers Affected:
EAX,ECX,EDX
Flags Affected:
none
Exceptions Generated:
Exception
Real
Virtual
8086 Protected Description
X
General protection (13)
For unimplemented MSR address.
X
Executing this instruction in Virtual 8086 mode.
X
For unimplemented MSR address OR if CPL not =o.
. The RDMSR or WRMSR instructions can be used in Real or Protected mode to access
several 64-bit MSRs. These registers are addressed by the value in ECX, as follows:
•
•
•
•
•
•
•
90
OOh: Machine-Check Address Register (MCAR). This may contain the physical
address of the last bus cycle for which the BUSCHK or PCHK signal was asserted.
For details, see "Machine-Check Address Register (MCAR)" on page 80.
01h: Machine-Check Type Register (MCTR). This contains the cycle definition of
the last bus cycle for which the BUSCHK or PCHK signal was asserted. For details,
see "Machine-Check Type Register (MCTR)" on page 80. The processor clears the
CHK bit (bit 0) in MCTR when the register is read with the RDMSR instruction.
10h: Time Stamp Counter (TSC). This contains a time value. The TSC can be
initialized to any value with the WRMSR instruction, and it can be read with either
the RDMSR or RDTSC instruction. For details, see "Time Stamp Counter (TSC)"
on page 81.
82h: Array Access Register (AAR). This contains an array pointer and test data for
testing the processor's cache and TLB arrays. For details on the AAR, see "Cache
and TLB Testing" on page 27.
83h: Hardware Configuration Register (HWCR). This contains configuration bits
that control miscellaneous de bugging functions. For details, see "Hardware
Configuration Register (HWCR)" on page 22.
85h: Write Allocate Top-of-Memory and Control Register (WATMCR)
86h: Write Allocate Programmable Memory Range Register (WAPMRR)
Note: The AMD-K5 processor supports write allocate only on Models 1, 2, and 3,
with a Stepping of 4 or greater.
AMD-K5™ Processor
Preliminary Information
21062E/O-June 1997
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
The above values in ECX identify the register to be read or written. The EDX and
EAX registers contain the MSR values to be read or written, as follows:
•
•
EDX-Upper 32 bits of MSR. For the AAR, this contains the array pointer and (in
contrast to all other MSRs) its contents are not altered by a RDMSR instruction.
EAX-Lower 32 bits of MSR. For the AAR, this contains the data to be read/written.
All MSRs are 64 bits wide. However, the upper 32 bits of the AAR are write-only and
are not returned on a read. EDX remains unaltered, making it more convenient to
maintain the array pointer.
If an attempt is made to execute either the RDMSR or WRMSR instruction when CPL
is greater than 0, or to access an undefined MSR, the processor generates a
general-protection exception with error code zero.
Model-Specific Registers, as their name implies, mayor may not be implemented by
later models of the AMD-KS processor.
AMD-KSTM Processor
91
AM Dl1
Preliminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
RSM
mnemonic
opcode
description
RSM
OFAAh
Resume execution (exit System Management Mode)
Privilege:
Registers Affected:
CPl=O
CS, OS, ES, FS, GS, SS, EIP, EFLAGS, lOTR,
CR3, EAX, EBX, ECX, EOX, ESP, EBP, EOI, ESI
none
Flags Affected:
Exceptions Generated:
Virtual
Exception
Invalid apcade (6)
Real
X
8086
X
Protected Description
Invalid apcade if nat in SMM Made.
X
The RSM instruction should be the last instruction in an System Management Mode
(SMM) service routine. It restores the processor state that was saved when the SMI
interrupt was asserted. This instruction is only valid when the processor is in SMM. It
generates an invalid opcode exception at all other times.
The processor enters the Shutdown state if any of the following illegal conditions are
encountered during the execution of the RSM instruction:
•
•
•
•
92
the SMM base value is not aligned on a 32-Kbyte boundary
Any reserved bit of CR4 is set to 1
The PG bit is set while the PE is cleared in CRO
The NW bit is set while the CD bit is cleared in CRO
AMD-K5™ Processor
Preliminary Information
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
210G2E/O-June 1997
Illegal Instruction (Reserved Opcode)
mnemonic
opcode
description
(none)
OF FFh
Illegal instruction (reserved opcode)
Privilege:
Any level
Registers Affected:
none
Flags Affected:
none
Exceptions Generated:
Virtual
Exception
Invalid opcode (6)
Real
X
8086
X
Protected Description
X
Invalid opcode if executed.
This opcode always generates an invalid opcode exception. The opcode will not be
used in future AMD K86 processors.
AMD-KSTM Processor
93
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AMD-K5™ Processor
Preliminary Information
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062EjO-June 1997
4
AMD-K6™
MMrM Enhanced Processor
The following sections describe additional information
required by BIOS developers to properly incorporate the
AMD-K6 MMX enhanced processor into a system. The BIOS for
the AMD-K6 needs minimal changes in order to fully support
the AMD-K6 processor family.
BIOS Consideration Checklist
CPUID
•
•
•
Use the CPUID instruction to properly identify the AMD-K6
processor.
Determine the processor type, stepping and features using
functions OOOO_OOOlh and 8000_0001h of the CPUID
instruction.
Boot-up display: The processor name should be displayed as
'AMD-K6(tm)/XXX'. See "CPU Identification Algorithms"
on page 3 for more information.
AMD-K6™ MMJrM Enhanced Processor
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CPU Speed Detection
•
Use speed detection algorithms that do not rely on
repetitive instruction sequences.
• Use the Time Stamp Counter (TSC) to 'clock' a timed
operation and compare the result to the Real Time Clock
(RTC) to determine the operating frequency. See the
example of frequency-determination assembler code
available on the AMD website at http://www.amd.com.
• Display the P-Rating shown in Table 2, "Summary of
. AMD-K6™ :Ml.\1X™ Enhanced Processor CPU IDs and BIOS
Boot Strings," on page 4.
Model-Specific Registers (MSRs)
•
•
Only access MSRs implemented in the AMD-K6 processor.
Enable Write Allocation by programming the Write
Handling Control Register (WHCR). See "Write Handling
Control Register (WHCR)" on page 119 and the
Implementation of Write Allocate in the K86f M Processors
Application Note, order# 21326 for more information.
•
Use the AMD-K6 processor's BIST function to test internal
memories. See "Built-In Self-Test (BIST)" on page 106 for
more information. The AMD-K6 does not contain MSRs to
allow for cache testing.
•
The System Management Mode (SMM) functionality of the
AMD-K6 processor is identical to Pentium.
Implement the AMD-K6 processor SMM state-save area in
the same manner as Pentium except for the IDT Base and
possibly Pentium-reserved areas. See ''AMD-K6™ Processor
System Management Mode" on page 97 for more
information.
Cache Testing
SMM Issues
•
96
AMD-K6™ MMJrM Enhanced Processor
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Preiiminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E,10-June 1997
AMD-K6™ Processor System Management Mode
The System Management Mode (SMM) in the AMD-K6 MMX
enhanced processor is similar to the AMD-KS processor. This
section points out the differences. See "AMD-KSTM Processor
System Management Mode (SMM)" on page 7 for details on the
AMD-KS processor implementation of SMM.
Initial Register Values
The general purpose registers and DR6 are unmodified when
entering SMM. Table 30 shows the default register values when
entering SMM.
Table 30. Initial State of Registers in SMM
Register
Initial Contents
Selector
Base
Limit
CS
3000h
0003_0000h
4 Gbytes
DS
ooooh
OOOO_OOOOh
4 Gbytes
ES
ooooh
oooo_oOoOh
4 Gbytes
FS
ooooh
oooo_OOOOh
4 Gbytes
GS
ooooh
oooo_OOOOh
4 Gbytes
SS
ooooh
oooo_ooooh
4 Gbytes
General-Purpose Registers
Unmodified
EFLAGS
000o_0002h
EIP
OOOO_BOOOh
CRO
Bits 0, 2, 3, and 31 cleared (PE, EM, TS, and PG); remainder are unmodified.
CR4
OOOO_OOOOh
GDTR
Unmodified
LDTR
Unmodified
IDTR
Unmodified
TR
Unmodified
DR7
0000_0400h
DR6
Unmodified
AMD-K6™ MMJrM Enhanced Processor
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SMM State-Save Area
When the SMI# is recognized the AMD-K6 processor saves its
state to the state-save area shown in Table 31. If the SMI# has
been relocated, the state dump begins at CS Base + 7FFFh
(8000 + 7FFFh). The default CS Base is 30000h.
Table 31. AMD-K6™ Processor State-Save Map
Address Offset
AMD-K5™
AMD-K6™
FFFCh
CRO
CRO
FFF8h
CR3
CR3
FFF4h
EFLAGS
EFLAGS
FFFOh
ElP
EIP
FFECh
EDI
EDI
FFE8h
ESI
ESI
FFE4h
EBP
EBP
FFEOh
ESP
ESP
FFDCh
EBX
EBX
EDX
FFD8h
EDX
ECX
FFD4h
ECX
FFDOh
EAX
EAX
FFCCh
DR6
DR6
FFC8h
DR7
DR7
FFC4h
TR
TR
FFCoh
LDTR Base
LDTR Base
FFBCh
GS
GS
FFBBh
FS
FS
FFB4h
DS
DS
FFBOh
SS
SS
CS
FFACh
CS
ES
FFA8h
ES
FFA4h
I/O Trap Dword
I/O Trap Dword
FFAOh
FF9Ch
I/O Trap EIP *
I/O Trap EIP *
FF98h
Notes:
- No dump at that address.
* Only contains information if SMNF was asserted on a valid corresponding I/O.
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Table 31. AMD-K6™ Processor State-Save Map (continued)
AMO-KSTM
Address Offset
FF94h
FF90h
FF8Ch
FF88h
FF84h
FF80h
FF7Ch
FF78h
FF74h
FF70h
FFGCh
FFG8h
FFG4h
FFGOh
FF5Ch
FF58h
FF54h
FF50h
FF4Ch
FF48h
FF44h
FF40h
FF3Ch
FF38h
FF34h
FF30h
FF2Ch
FF28h
FF24h
FF20h
FF1Ch
AMO-K6™
-
-
IDT Base
IDT limit
GDT Base
GDT limit
TSS Attr
TSS Base
TSS limit
LDT Attr
LDT Base
LDT limit
GS Attr
GS Base
GS limit
FS Attr
FS Base
FS limit
DS Attr
DS Base
DS limit
55 Attr
55 Base
55 limit
CS Attr
CS Base
CS limit
ES Attr
ES Base
ES limit
lOT Base
IDT limit
GDTBase
GDTlimit
TSS Attr
TSS Base
TSS limit
-
LDTlow
LDT High
GS Attr
GS Base
GS limit
FS Attr
FS Base
FS limit
DS Attr
DS Base
DS limit
55 Attr
55 Base
55 limit
CS Attr
CS Base
CS limit
ES Attr
ES Base
ES limit
-
Notes:
:/<
No dump at that address.
Only contains information if SMNt= was asserted on a valid corresponding I/o.
AMD-K6™ MMJrM Enhanced Processor
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Table 31. AMO-K6™ Processor State-Save Map (continued)
AMO-K5™
Address Offset
FF1Sh
FF14h
FFI0h
FFOCh
FFOsh
FF04h
FF02h
FFOoh
FEFCh
FEFSh
FEF7-FEOoh
AMO-K6™
-
-
CR2
CR4
110 restart ESI*
110 restart ECX*
110 restart EDI*
HALT Restart Slot
110 Restart Slot
SMM RevlD
SMM BASE
CR2
CR4
110 restart ESI*
I/O restart ECX*
I/O restart EDI*
HALT Restart Slot
110 Restart Slot
SMM RevlD
SMM BASE
-
-
Notes:
No dump at that address.
-
* Only contains information if SMI# was asserted on a valid corresponding I/O.
SMM Revision Identifier
The SMJ.\1 Revision Identifier specifies the version of SMJ.\1 and
the extensions available on the processor. Table 32 defines the
bits associated with this register. A 1 present in either the 110
Trap Extension or the SMM Base Relocation indicates this
feature is available for use.
Table 32. SMM Revision Identifier
31-18
17
16
15-0
Reserved
0
SMM Base Relocation
1
110 Trap Extension
SMM Revision Level
ooo2h
1
SMM Base Address
This feature is compatible with the AMD-K5 processor and
Pentium. See "SMJ.\1 Base Address" on page 12.
100
AMD-K6™ MMJrM Enhanced Processor
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Auto Halt Restart
This feature is compatible with the AMD-K5 processor and the
Pentium processor. See "Auto Halt Restart Slot" on page 13.
1/0 Trap Dword
If the assertion of S::MI# is recognized on the boundary of an I/O
bus cycle, the I/O trap doubleword at offset FFA4h in the SMM
state-save area contains information about the associated I/O
instruction. The AMD-K6 processor provides additional
information at this offset when compared to the AMD-K5
processor. The AMD-K6 processor provides a bit to determine if
the I/O string operand is a REP string operation. The fields of
the I/O Trap Dword are configured as shown in Table 33.
Table 33. AMD-K6™ Processor 1/0 Trap Dword Configuration
31-16
15-4
3
2
1
0
I/O Port
Address
Reserved
Rep String
Operation
I/O String
Operation
Valid I/O
Instruction
Input or
Output
1/0 Trap Restart
This feature is compatible with the AMD-K5 processor. See "I/O
Trap Restart Slot" on page 14.
Exceptions and Interrupts Within SMM
This feature is compatible with the AMD-K5. See "Exceptions
and Interrupts in SMM" on page 16.
AMD-K6™ MMJrM Enhanced Processor
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AMD-K&TM Processor Reset State
Table 34 shows the state of all architecture registers and MSRs
after the processor has completed its initialization resulting
from the recognition of the assertion of RESET.
Table 34. State of the AMO-K6™ Processor After RESET
RESET State
Register
GOTR
IOTR
TR
LDTR
EIP
EFLAGS
base:OOOO_oooo limitOFFFFh
base:OOOO_Oooo IimitOFFFFh
ooooh
ooooh
FFFF_FFFOh
oOOO_OOO2h
oOOO_OOOOh
oooO_OOOOh
OoOO_OOOOh
OOOO_056xh
oOOO_OOOOh
oOOO_OOOOh
QOOO_OOOOh
OOOO_OOOOh
FOooh
OOOoh
OOOOh
OOOOh
ooooh
ooooh
OOOO_OOOO_OOOO_OOOO_OOOOh
o04oh
ooooh
5555h
EAX
ESX
ECX
EOX
ESI
EDI
ESP
ESP
CS
SS
OS
ES
FS
GS
FPU Stack R7-RO
FPU Control Word
FPU Status Word
FPU Tag Word
Notes
1
2
Notes:
1. The contents of EAX indicate if BISTwas successful. If EAX =OOOO_OOOOh, then BIST
was successful If EAX is non-zero, BIST failed.
2. fOX contains the AMD-K6 processor signature.
3. These Model-Specific Registers are desaibed in ''AMO-K6™ Processor x86 Architecture Extensions on page 117.
H
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Table 34. State of the AMD-K6™ Processor After RESET (continued)
Register
RESET State
FPU Instruction Pointer OOOO_OOOO_OOOOh
OOOO-,-OOOO_OOODh
FPU Data Pointer
FPU Opcode Register OOO_oooo_oooob
6000_0010h
CRO
oooo_oOOOh
CR2
oooo_oOOOh
CR3
OOOO_OOOOh
CR4
OOOO_0400h
DR7
FFFF_OFFOh
DR6
OOOO_OOOOh
DR3
OOOO_OOOOh
DR2
OOOO_OOOOh
DRl
OOOO_OOOOh
DRO
OOOO_OOoo_oooo_ooOOh
MCAR
OOOO_OOOO_OOOO_OOOOh
MaR
OOOO_OOOO_OOOO_OOOOh
TR12
OOOO_OOOO_oooo_oOOOh
TSC
OOOO_OOOO_OOOO_OOOOh
EFER
DOOO_OOOO_OOOO_DDDDh
STAR
OOOO_OOOO_OOOO_OOOOh
WHCR
Notes
3
3
3
Notes:
1. The contents of EAX indicate if BISTwas successful. If EAX =OOOO_OOOOh, then BIST
was successful. If EAX is non-zero, BIST failed
2. fOX contains the AMO-K6 processor signature.
3. These Model-Specific Registers are described in "AMO-K6n.t Processor x86 Architecture Extensions" on page 11 Z
Segment Register Attributes
See Table 10 on page 20 for segment register attribute initial
values.
'
AMD-K6™ MM)(TM Enhanced Processor
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Preliminllry Informlltion
AMD K86™ Family BIOS and Software Tools Developers Guide
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State of the AMD-K6™ Processor After INIT
The assertion of INIT causes the processor to empty its
pipelines, initialize most of its internal state, and branch to
address FFFF_FFFOh-the same instruction execution starting
point used after RESET. Unlike RESET, the processor
preserves the contents of its caches, the floating-point state, the
SMM base, the MMX state, MSRs, and the CD and NW bits of
the CRO register.
The edge-sensitive interrupts FLUSH# and SMI# are sampled
and preserved during the INIT process and are handled
accordingly after the initialization is complete. However, the
processor resets any pending NMI interrupt upon sampling
INIT asserted.
INIT can be used as an accelerator for 80286 code that requires
areset to exit from Protected mode back to Real mode.
AMD-K6™ Processor Cache
The internal Ll cache of the AMD-K6 MMX enhanced
processor consists of two separate caches-a 32-Kbyte
instruction cache and a 32-Kbyte data cache. The instruction
cache also incorporates a 20-Kbyte pre-decode cache in
addition to a 64-entry TLB. The data cache utilizes a 128-entry
TLB. The cache line is 32 bytes wide. Two adjacent cache lines
are associated with each tag (a 64-byte sector with two 32-byte
cache lines).
The AMD-KS processor uses the Array Access Register (AAR),
a MSR that allows for testing of the processor caches. The
AMD-K6 processor does not contain these features. The
AMD-K6 contains a built-in self-test (BIST) for all internal
memories. However, cache information can be provided by
utilizing the ,CPUID instruction. For more detailed information
refer to the AMD Processor Recognition Application Note, order#
20734, located at http://www.amd.com.
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AMD K86™ Family BIOS and Software Tools Developers Guide
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Function 8000_0005h of the CPUID instruction returns
processor cache information. Table 35 shows the information
returned by the CPUID instruction when EAX = 8000_0005h.
Table 35. Data Returned by the CPUID Instruction
Register
EBX
ECX
EDX
Field Bits
31-24
23-16
15-8
7-0
31-24
23-16
15-8
7-0
31-24
23-16
15-8
7-0
Field Description
Data TlB-Associativity
Data TlB-Number of entries
Instruction TlB-Associativity
Instruction TlB-Number of entries
L1 data cache-Size (Kbytes)
II data cache-Associativity
II data cache-Lines per tag
II data cache-Line size (bytes)
II instruction cache-Size (Kbytes)
II instruction cache-Associativity
II instruction cache-lines per tag
II instruction cache-line size (bytes)
Note:
Full associativity is indicated by a value of FFh.
AMD-K&TM Processor Test and Debug
The AMD-K6 MMX enhanced processor implements various
test and debug modes to enable the functional and
manufacturing testing of systems and boards that use the
processor. In addition, the debug features of the processor
allow designers to debug the instruction execution of software
components. This section describes the following test and
debug features:
•
•
•
Built-In Self-Test (BIST)-The BIST, which is invoked after
the falling transition of RESET, runs internal tests that
exercise most on-chip RAM and ROM structures.
Tri-State Test Mode-A test mode that causes the processor
to float its output and bidirectional pins.
Boundary-Scan Test Access Port (TAP)- The Joint Test Action
Group (JT AG) test access function defined by the IEEE
Standard Test Access Port and Boundary-Scan Architecture
(IEEE 1149.1-1990) specification.
AMD-K6™ MM)(fM Enhanced Processor
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•
•
21 062E/O- June 1997
Level-One (L1) Cache Inhibit-A feature that disables the
processor's internal Ll instruction and data caches.
Debug Support-Consists of all x86-compatible software
debug features, including the debug extensions.
Built-In Self-Test (liST)
Following the falling transition of RESET, the processor
unconditionally runs its BIST. The internal resources tested
during BIST include the following:
•
•
•
•
Ll instruction and data caches
Instruction and Data Translation Lookaside Buffers (TLBs)
Microcode Read-Only Memory (ROM)
Programmable Logic Arrays
The contents of the EAX general-purpose register after the
completion of RESET indicate if the BIST was successful. If
EAX contains OOOO_OOOOh, then BIST was successful. If EAX is
non-zero, the BIST failed. Following the completion of the BIST,
the processor jumps to address FFFF _FFFOh to start
instruction execution, regardless of the outcome of the BIST.
The BIST takes approximately 295,000 processor clocks to
complete.
Tri-State Test Mode
The Tri-State Test mode causes the processor to float its output
and bidirectional pins, which is useful for board-level
manufacturing testing. In this mode, the processor is
electrically isolated from other components on a system board,
allowing automated test equipment (ATE) to test those
components that drive the same signals as those the processor
floats.
If the FLUSH# signal is sampled Low during the falling
transition of RESET, the processor enters the Tri-State Test
mode. See the AMD-K6™ MMXTM Enhanced Processor Data
Sheet, order# 20695, for more information.
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AMD K86™ Family BIOS and Software Tools Developers Guide
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Boundary-Scan Test Access Port (TAP)
The boundary-scan Test Access Port (TAP) is an IEEE standard
that defines synchronous scanning test methods for complex logic
circuits, such as boards containing a processor. The AMD-K6
processor supports the TAP standard defined in the IEEE
Standard Test Access Port and Boundary-Scan Arch itecture (IEEE
1149.1-1990) specification.
Boundary scan testing uses a shift register consisting of the
serial interconnection of boundary-scan cells that correspond
to each I/O buffer of the processor. This non-inverting register
chain, called a Boundary Scan Register (BSR), is used to
capture the state of every processor pin and to drive every
processor output and bidirectional pin to a known state.
Each BSR of every component on a board that implements the
boundary-scan architecture can be serially interconnected to
enable component interconnect testing.
TAP Registers
The AMD-K6 processor provides an Instruction Register (IR) and
three Test Data Registers (TDR) to support the boundary-scan
architecture. The IR and one of the TDRs-the Boundary-Scan
Register (BSR)-consist of a shift register and an output register.
The shift register is loaded in parallel in the Capture states (See
the IEEE Standard TestAccess Port and Boundary-ScanArch itecture
(IEEE 1149.1-1990) specification for more information). In
addition, the shift register is loaded and shifted serially in the
Shift states. The output register is loaded in parallel from its
corresponding shift register in the Update states.
Instruction Register (IR). The IR isa 5-bit register, without parity,
that determines which instruction to run and which test data
register to select. When the TAP controller enters the
Capture-IR state, the processor loads the following bits into the
IR shift register:
• 01b-Loaded into the two least significant bits, as specified
by the IEEE 1149.1 standard
• OOOb-Loaded into the three most significant bits
Loading 0000lb into the IR shift register during the Capture-IR
state results in loading the SAMPLEIPRELOAD instruction.
For each entry into the Shift-IR state, the IR shift register is
serially shifted by one bit toward the TDO pin. During the shift,
the most significant bit of the IR shift register is loaded from
theTDIpin.
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The IR output register is loaded from the IR shift register in the
Update-IR state, and the current instruction is defined by the
IR output register. See "TAP Instructions" on page 111 for a
list and definition of the instructions supported by the
AMD-K6.
Boundary Scan Register (BSR). The BSR is a Test Data Register
consisting of the interconnection of 152 boundary-scan cells.
Each output and bidirectional pin of the processor requires a
two-bit cell, where one bit corresponds to the pin and the other
bit is the output enable for the pin. When a 0 is shifted into the
enable bit of a cell, the corresponding pin is floated, and when a
1 is shifted into the enable bit, the pin is driven valid. Each
input pin requires a one-bit cell that corresponds to the pin.
The last cell of the BSR is reserved and does not correspond to
any processor pin.
The total number of bits that comprise the BSR is 281. Table 36
on page 109 lists the order of these bits, where TDI is the input
to bit 280, and TDO is driven from the output of bit o. The
entries listed as pin_E (where pin is an output or bidirectional
signal) are the enable bits.
If the BSR is the register selected by the current instruction
and the TAP controller is in the Capture-DR state, the
processor loads the BSR shift register as follows:
•
•
If the current instruction is SAMPLE/PRELOAD, then the
current state of each input, output, and bidirectional pin is
loaded. A bidirectional pin is treated as an output if its
enable bit equals 1, and it is treated as an input if its enable
bit equals o.
If the current instruction is EXTEST, then the current state
of each input pin is loaded. A bidirectional pin is treated as
an input, regardless of the state of its enable.
While in the Shift-DR state, the BSR shift register is serially
shifted toward the TDO pin. During the shift, bit 280 of the BSR
is loaded from the TDI pin.
The BSR output register is loaded with the contents of the BSR
shift register in the Update-DR state. If the current instruction
is EXTEST, the processor's output pins, as well as those
bidirectional pins that are enabled as outputs, are driven with
their corresponding values from the BSR output register.
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Table 36. Boundary Scan Register Bit Definitions
Bit
280
279
278
277
276
275
274
273
272
271
270
269
268
267
266
265
264
263
262
261
260
259
258
257
256
255
254
253
252
251
250
249
248
Pin/Enable
D35_E
D35
D29_E
D29
D33_E
D33
D27_E
D27
DP3_E
DP3
D25_E
D25
DO_E
DO
D30_E
D30
DP2_E
DP2
D2_E
D2
D28_E
D28
D24_E
D24
D26_E
D26
D22_E
D22
D23_E
D23
D20_E
D20
D21_E
Bit
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
Pin/Enable
D21
D18_E
D18
D19_E
D19
D16_E
D16
D17_E
D17
D15_E
D15
DP1_E
DPl
D13_E
D13
D6_E
D6
D14_E
D14
Dll_E
Dll
Dl_E
Dl
D12_E
D12
DlO_E
Dl0
D7_E
D7
D8_E
D8
D9_E
D9
Bit
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
192
191
190
189
188
187
186
185
184
183
182
AMD-K6™ MM)(TM Enhanced Processor
Pin/Enable
D4_E
D4
DPO_E
DPO
HOLD
BOFF#
AHOLD
STPCLK#
INIT
IGNNE#
BFl
BF2
RESET
BFO
FLUSH#
INTR
NMI
SMI#
A25_E
A25
A23_E
A23
A26_E
A26
A29_E
A29
A28_E
A28
A27_E
A27
All_E
All
A3_E
Bit
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
Pin/Enable
A3
A31_E
A31
A21_E
A21
A30_E
A30
A7_E
A7
A24_E
A24
A18_E
A18
A5_E
AS
A22_E
A22
EADS#
A4_E
A4
HITM_E
HITM#
A9_E
A9
SCYC_E
SCYC
A8_E
A8
A19_E
A19
A6_E
A6
A20_E
Bit
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
Pin/Enable
A20
A13_E
A13
DP7_E
DP7
BE6_E
BE6
A12_E
A12
CLK
BE4_E
BE4
Al0_E
AlO
D63_E
D63
BE2_E
BE2
A15_E
A15
BRDY#
BE1_E
BEl
A14_E
A14
BRDYC#
BEO_E
BEO
A17_E
A17
KEN#
A20M#
A16_E
Bit
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
Pin/Enable
A16
FERR_E
FERR#
HIT_E
HIT#
BE7_E
BE7
NA#
ADSC_E
ADSC#
BE5_E
BE5#
WBjWT#
PWT_E
PWT
BE3_E
BE3#
BREQJ
BREQ
PCD_E
PCD
W_E
W/R#
SMIACT_E
SMIACT#
EWBE#
DC_E
D/C#
APCHK_E
APCHK#
CACHE_E
CACHE#
ADS_E
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Preliminary Information
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Table 36. Boundary Scan Register Bit Definitions (continued)
Bit
82
81
80
79
78
77
76
75
74
73
72
Pin/Enable
ADS#
AP_E
AP
INV
HLDA_E
HLDA
PCHK_E
PCHK#
LOCK_E
LOCK#
M_E
71 M/IO#
70 052_E
69 052
Bit
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Pin/Enable
DP6_E
DP6
D54_E
D54
D50_E
D50
D56_E
056
055_E
055
048_E
048 ,
057_E
057
Bit
54
53
52
51
50
49
48
47
46
45
44
43
42
41
Pin/Enable
D53_E
D53
D47_E
D47
D59_E
D59
D51_E
051
045_E
045
061_E
061
OP5_E
OP5
Bit
40
39
38
37
36
35
34
33
32
31
30
29
28
27
Pin/Enable
D43_E
D43
D62_E
D62
D49_E
D49
DP4_E
OP4
046_E
046
041_E
041
044_E
044
Bit
26
25
24
23
22
21
20
19
18
17
16
15
14
13
Pin/Enable Bit Pin/Enable
D38_E
12 D3_E
D38
11 D3
D58_E
10 D39_E
D58
9 D39
D42_E
8 D32_E
D42
7 D32
D36_E
6 05_E
036
5 05
060_E
4 037_E
060
3 037
040_E
2 031_E
040
1 031
D34_E
0 Reserved
034
Device Identification Register (DIR). The DIR is a 32-bit Test Data
Register selected during the execution of the IDCODE
instruction. The fields of the DIR and their values are shown in
Table 37 and are defined as follows:
•
•
•
•
Version Code-This 4-bit field is incremented by AMD
manufacturing for each major revision of silicon.
Part Number-This 16-bit field identifies the specific
processor model.
Manufacturer-This ii-bit field identifies the manufacturer
of the component (AMD).
LSB- The least significant bit (LSB) of the DIR is always set
to 1, as specified by the IEEE 1149.1 standard.
Table 37. AMD-K6™ Processor Device Identification Register
Version Code
(Bits 31-28)
Xh
Part Number
(Bits 27-12)
0560h
Manufacturer
(Bits 11-1)
oooooooooolb
LSB
(Bit 0)
1b
Bypass Register (BR). The BR is a Test Data Register consisting of
a i-bit shift register that provides the shortest path between
TDI and TDO. When the processor is not involved in a test
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operation, the BR can be selected by an instruction to allow the
transfer of test data through the processor without having to
serially scan the test data through the BSR. This functionality
preserves the state of the BSR and significantly reduces test
time.
The BR register is selected by the BYPASS and HIGHZ
instructions as well as by any instructions not supported by the
AMD-K6.
TAP Instructions
The processor supports the three instructions required by the
IEEE 1149.1 standard-EXTEST, SAMPLE/PRELOAD, and
BYPASS-as well as two additional optional instructionsIDCODE and HIGHZ.
Table 38 shows the complete set of TAP instructions supported
by the processor along with the 5-bit Instruction Register
encoding and the register selected by each instruction.
Table 38. Supported TAP Instructions
Instruction
EXTESr
SAMPLE / PRELOAD
IDCODE
HIGHZ
BYPASS2
BYPASS]
Encoding
ooooob
oooolb
ooo10b
000llb
oOloob-llll0b
ll111b
Register
BSR
BSR
DIR
BR
BR
BR
Description
Sample inputs and drive outputs
Sample inputs and outputs, then load the BSR
Read DIR
Float outputs and bidirectional pins
Undefined instruction, execute the BYPASS instruction
Connect TDI to TDO to bypass the BSR
Notes:
!.
2.
3.
Following the execution of the EXTEST instruction, the processor must be reset in order to return to normal non-test operation.
These instruction encodings are undefined on the AMD-K6 processor and default to the BYPASS instruction.
Because the TDI input contains an internal pullup, the BYPASS instruction is executed if the TDI input is not connected or open
during an instruction scan operation. The BYPASS instruction does not affect the normal operational state of the processor.
EXTEST. When the EXTEST instruction is executed, the
processor loads the BSR shift register with the current state of
the input and bidirectional pins in the Capture-DR state and
drives the output and bidirectional pins with the corresponding
values from the BSR output register in the Update-DR state.
AMD-K6™ MMJrM Enhanced Processor
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SAMPLE/PRELOAD. The SAMPLEIPRELOAD instruction performs
two functions. These functions are as follows:
•
•
During the Capture-DR state, the processor loads the BSR
shift register with the current state of every input, output,
and bidirectional pin.
During the Update-DR state, the BSR output register is
loaded from the BSR shift register in preparation for the
next EXTEST instruction.
The SAMPLEIPRELOAD instruction does not affect the normal
operational state of the processor.
BYPASS. The BYPASS instruction selects the BR register, which
reduces the boundary-scan length through the processor from
281 to one (TDI to BR to TDO). The BYPASS instruction does
not affect the normal operational state of the processor.
IDCODE. The IDCODE instruction selects the DIR register,
allowing the device identification code to be shifted out of the
processor. This instruction is loaded into the IR when the TAP
controller is reset. The IDCODE instruction does not affect the
normal operational state of the processor.
HIGHZ. The HIGHZ instruction forces all output and
bidirectional pins to be floated. During this instruction, the BR
is selected and the normal operational state of the processor is
not affected.
L1 Cache Inhibit
Purpose
The AMD-K6 MMX enhanced processor provides a means for
inhibiting the normal operation of its L1 instruction and data
caches while still supporting an external level-two (L2) cache.
This capability allows system designers to disable the L1 cache
during the testing and debug of an L2 cache.
If the Cache Inhibit bit (bit 3) of Test Register 12 (TR12) is set
to 0, the processor's L1 cache is enabled and operates as
described in the Cache Organization section of the AMD-K6fM
MMXTM Enhanced Processor Data Sheet, order# 20695. If the
Cache Inhibit bit is set to 1, the L1 cache is disabled and no new
cache lines are allocated. Even though new allocations do not
occur, valid L1 cache lines remain valid and are read by the
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processor when a requested address hits a cache line. In
addition, the processor continues to support inquire cycles
initiated by the system logic, including the execution of
writeback cycles when a modified cache line is hit.
While the Ll is inhibited, the processor continues to drive the
PCD output signal appropriately, which system logic can use to
control external L2 caching.
In order to completely disable the Ll cache so no valid lines
exist in the cache, the Cache Inhibit bit must be set to 1 and the
cache must be flushed in one of the following ways:
•
•
•
By asserting the FLUSH# input signal
By executing the WBINVD instruction
By executing the INVD instruction (modified cache lines are
not written back to memory)
Debug
The AMD-K6 processor implements the standard x86 debug
functions, registers, and exceptions. In addition, the processor
supports the I/O breakpoint debug extension. The debug
feature assists programmers and system designers during
software execution tracing by generating exceptions when one
or more events occur during processor execution. The
exception handler, or debugger, can be written to perform
various tasks, such as displaying the conditions that caused the
breakpoint to occur, displaying and modifying register or
memory contents, or single-stepping through program
execution.
The following sections describe the debug registers and the
various types of breakpoints and exceptions supported by the
processor.
For more details on the register definitions see the Test and
Debug chapter in 'the AMD-K6™ MMXTM Enhanced Processor
Data Sheet, order# 20695.
Debug Registers
Figures 24 through 27 show the 32-bit debug registers
supported by the processor. Table 39 provides LEN and RW
information for DR7 as displayed in Figure 24.
AMD-K6™ MMJrM Enhanced Processor
11~
AMDt'1
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AMD K86™ Family BIOS and Software Tools Developers Guide
~
r--------------------------------LEN3
21 062E/O-June 1997
Description
Length of Breakpoint #3
Type of Transaction(s) to Trap
Length of Breakpoint #2
Type of Transaction(s) to Trap
Length of Breakpoint #1
Type of Transaction(s) to Trap
Length of Breakpoint #0
Type ofTransaction(s) to Trap
~-----------------------WW3
IIIIF,~~
Bits
31-30
29-28
27-26
25-24
23-22
21-20
19-18
17-16
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LEN
3
WW
3
LEN
2
WW
2
LEN
1
WW
1
LEN
0
WW
0
0---. Reserved
Symbol
GO
GE
LE
G3
L3
G2
L2
G1
L1
GO
LO
Description
General Detect Enabled
Global Exact Breakpoint Enabled
Local Exact Breakpoint Enabled
Global Exact Breakpoint # 3 Enabled
Local Exact Breakpoint # 3 Enabled
Global Exact Breakpoint # 2 Enabled
Local Exact Breakpoint # 2 Enabled
Global Exact Breakpoint # 1 Enabled
Local Exact Breakpoint # 1 Enabled
Global Exact Breakpoint # 0 Enabled
Local Exact Breakpoint # 0 Enabled
Bit
G
0
G L G L L L G L G L
E E 3 3 2 2 1 1 0 0
:=U
13
1
9·
8
7
6
5
4
3
2
1
0
Figure 24. Debug Register DR7
Table 39. DR7 LEN and RW Definitions
LEN Bits!
RW Bits
Breakpoint
oob
oob
olb
llb
oob
O1b
llb
oob
olb
llb
oOb
Instruction Execution
One-byte Data Write
Two-byte Data Write
Four-byte Data Write
One-byte I/O Read or Write
Two-byte I/O Read or Write
Four-byte I/O Read or Write
One-byte Data Read or Write
Two-byte Data Read or Write
Four-byte Data Read or Write
2
Olb
lOb]
llb
Notes:
1. LEN bits equalto lob is undefined
2. When RWequals OOb, LEN must be equal to oob.
3. When RWequals lab, debugging extensions (DE) must be enabled (bit 3 of CR4 must be set to 1). If DE is set to 0, RWequal to lob is undefined
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AMD-K6™ MMXTM Enhanced Processor
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21 062tjO- June 1997
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4
D~ Reserved
SymQQ!
BT
BS
BD
B3
B2
Bl
BO
Description
Breakpoint Task Switch
Breakpoint Single Step
Breakpoint Debug Access Detected
Breakpoint #3 Condition Detected
Breakpoint #2 Condition Detected
Breakpoint #1 Condition Detected
Breakpoint #0 Condition Detected
3 2
1 0
M~
15
14
13
3
2
1
0
Figure 25. Debug Register DR6
DRS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7
6 5 4 3
2
1 0
I
Reserved
DR4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Reserved
8
765432
1 0
I
Figure 26. Debug Registers DRS and DR4
AMD-K6™ MMJrM Enhanced Processor
115
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OR3
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2
1 0
Breakpoint 3 32-bit Linear Address
I
OR2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8 7
6
5
4 3
2
1 0
Breakpoint 2 32-bit Linear Address
I
ORl
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5 4
3
2
1 0
I
Breakpoint 1 32-bit Linear Address
ORO
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Breakpoint 0 32-bit Linear Address
8
7
6
5
4
3 2
1 0
I
Figure 27. Debug Registers DR3, DR2, DR1, and DRO
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AMD-K6™ MMJrM Enhanced Processor
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AMD K86™ Family BIOS and Software Tools Developers Guide
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AMD-K6™ Processor x86 Architecture Extensions
This section documents the extensions that have been added to
the AMD-K6 MMX enhanced processor.
Model-Specific Registers (MSR)
The AMD-K6 processor provides the following six MSRs. The
contents of ECX selects the MSR to be addressed by the
RDMSR and WRMSR instruction.
•
•
•
•
•
•
•
Machine-Check Address Register (MCAR)-ECX = OOh
Machine-Check Type Register (MCTR)-ECX = 01h
Test Register 12 (TR12)-ECX =OEh
Time Stamp Counter (TSC)-ECX = 10h
Extended Feature Enable Register
(EFER)-ECX =COOO_0080h
SYSCALL Target Address Register
(STAR)-ECX =COOO_0081h
Write Handling Control Register
(WHCR)-ECX =COOO_0082h
These six MSRs are read and written by the RDMSR and
WRMSR instructions. (The TSC can also be read by the RDTSC
instruction.) The target register for the RDMSR and WRMSR
instructions is addressed by the contents of ECX. The only
values allowed in ECX by the AMD-K6 processor are OOh, 01h,
OEh, 10h, COOO_0080h, COOO_0081h, and COOO_0082h for the
MCAR, MCTR, TR12, TSC, EFER, STAR and WHCR registers
respectively. The usage of any other reserved value in ECX
results in a general protection exception.
Machine-Check
Address Register
(MCAR)
See Figure 20 on page 80 and "Machine Check Exception" on
page 122.
Machine-Check Type
Register (MCTR)
See Figure 21 on page 81 and "Machine Check Exception" on
page 122.
AMD-K6nA MM)(TIA Enhanced Processor
117
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Test Register 12
(TRI2)
The AMD-K6 processor also provides the 64-bit Test Register 12
(TR12), but only the function of the Cache Inhibit (CI) bit (bit 3
of TR12) is supported. All other bits in TR12 have no effect on
the processor's operation. The I/O Trap Restart function (bit 9
of TR12) is always enabled on the AMD-K6.
Time Stamp Counter
(TSC)
See "Time Stamp Counter (TSC)" on page 81.
Extended Feature
Enable Register
(EFER)
The Extended Feature Enable Register (EFER) contains the
control bits that enable the extended features of the AMD-K6
processor. Figure 28 shows the format of the EFER register,
and Table 40 defines the function of each bit of the EFER
register. The EFER register is MSR COOO_0080h.
1 0
63
D --.. Reserved
~
SCE
Description
System Call Extension
I
M
o ----------------------------------~.
Figure 28. Extended Feature Enable Register (EFER)
Table 40. Extended Feature Enable Register (EFER) Definition
Bit
Description
63-1
Reserved
0
System Call Extension (SCE)
SYSCALL Target
Address Register
(STAR)
118
RfW
Fundion
Writing a 1 to any reserved bit causes a general protection
R
fault to occur. All reserved bits are always read as O.
SCE must be set to 1to enable the usage of the SYSCALL and
R/W SYSRET instructions.
The SYSCALL Target Address Register (STAR) contains the
target EIP address used by the SYSCALL instruction, and
contains the 16-bit selector base used by the SYSCALL and
SYSRET instructions. Figure 29 shows the format of the STAR
register, and Table 41 defines the fields of the STAR register.
The STAR register is MSR COOO_0081h.
AMD-K6™ MMlfM Enhanced Processor
AM 0
Preliminary Information
~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062EjO-June 1997
63
o
32 31
48 47
CS Selector and SS Selector
Base
Target EIP Address
D -. Reserved
Figure 29. SYSCALL Target Address Register (STAR)
Table 41. SYSCALL Target Address Register (STAR) Definition
Bit
Description
31-0
Target EIP Address
47-32
CS and SS Selector Base
63-48
Reserved
Write Handling
Control Register
(WHCR)
RfW
Function
This address is copied into the EIP and points to the new
RfW starting address.
During the SYSCALL instruction, this field is copied into the
CS register and the contents of this field, plus 8, are copied
RfW into the SS register. During the SYSRET instruction, this field,
plus 16, is copied into the SS register, and bits 1-0 of the SS
register are set to 11 b.
Writing a 1 to any reserved bit causes a general protection
R
fault to occur. All reserved bits are always read as O.
The AMD-K6 processor contains a split level-one (L1) 64-Kbyte
writeback cache organized as a separate 32-Kbyte instruction
cache and a 32-Kbyte data cache with two-way set associativity.
The cache line size is 32 bytes, and lines are read from memory
using an efficient pipelined burst read cycle. Further
performance gains are achieved by the implementation of a
write allocation scheme.
For more information about write allocate, see the
Implementation of Write Allocate in the K86™ Processors
Application Note, order# 21326.
Write allocate, if enabled, occurs when the processor has a
pending memory write cycle to a cacheable line and the line
does not currently reside in the L1 cache. In this case, the
processor performs a burst read cycle to fetch the cache line
addressed by the pending write cycle. The data associated with
the pending write cycle is merged with the recently-allocated
data-cache line and stored in the processor's L1 data cache. The
AMD-K6™ MM)(fM Enhanced Processor
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final MESI state of the cache line depends on the state of the
WB/WT# and PWT signals during the burst read cycle and the
subsequent cache write hit.
Write Handling Control Register (WHCR). The Write Handling Control
Register (WHCR) is an MSR that contains three fields-the
WCDE bit, the Write Allocate Enable Limit (WAELIM) field,
and the Write Allocate Enable 15-to-16-Mbyte (WAE15M) bit
(See Figure 30).
8
63
Iii
7
0
WAELIM
III
D~Reserved
Symbol
WCDE
WAELIM
WAE15M
I
Description
Bits
Write Cacheability Detection Enable 8
Write Allocate Enable Limit
7-1 - - - - - - - - - - - - - - - - - '
Write Allocate Enable 15-to-16-Mbyte 0
I
Note: Hardware RESET initializes this MSR to all zeros.
Figure 30. Write Handling Control Register (WHCR)-MSR COOO_0082h
Write Cacheability Detection Enable. When the Write Cache ability
Detection Enable (WCDE) bit (bit 8) of the Write Handling
Control Register (WHCR) MSR is set to 1, this write allocate
mechanism is enabled. For more details on the Write
Cache ability Detection Mechanism, see the Cache Organization
chapter in the AMD-K6™ MMXTM Enhanced Processor Data
Sheet, order# 20695.
If the address is cache able, support of the Write Cache ability
Detection mechanism requires the system logic to assert KEN#
during a write cycle. Some chipsets assert KEN# during a write
cycle and some chipsets do not assert KEN# during a write
cycle. (Triton chipsets eventually generate a correct value for
KEN#, but not during the sample point. Therefore do not
enable WCDE in systems that use the Triton chipset.) If Write
Cache ability Detection is enabled, KEN# is sampled during
write cycles in the same manner it is sampled during read
cycles (KEN # is sampled on the clock edge on which the first
BRDY# or NA# of a cycle is sampled asserted). Future chip sets
may take advantage of this mechanism, but currently AMD
recommends setting this bit to zero (disabled).
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Write Allocate Enable Limit. The W AELIM field is 7 bits wide. This
field, multiplied by 4 Mbytes, defines an upper memory limit.
Any pending write cycle that addresses memory below this
limit causes the processor to perform a write allocate. Write
allocate is disabled for memory accesses at and above this
limit unless the processor determines a pending write cycle is
cacheable by means of one of the other Write Cache ability
Detection mechanisms. The maximum value of this limit is
«27-1) ·4 Mbytes) = 508 Mbytes. When all the bits in this
field are set to 0, all memory is above this limit and the write
allocate mechanism is disabled.
Write Allocate Enable 15-to-16-Mbyte. The WAE15M bit is used to
enable write allocations for the memory write cycles that
address the 1 Mbyte of memory between 15 Mbytes and 16
Mbytes. This bit must be set to 0 to prevent write allocates in
this memory area. This sub-mechanism of the W AELIM
provides a memory hole to prevent write allocates. This
memory hole is provided to account for a small number of
uncommon memory-mapped 110 adapters that use this
particular memory address space. If the system contains one of
these peripherals, the bit should be set to o. The WAE15M bit is
ignored if the value in the W AELIM field is set to less than 16
Mbytes.
By definition, write allocations in the AMD-K6 processor are
never performed in the memory area between 640 Kbytes and 1
Mbyte. It is not safe to perform write allocations between 640
Kbytes and 1 Mbyte (OOOA_OOOOh to OOOF_FFFFh) because it is
considered a non-cache able region of memory.
See the Software Environment section of the AMD-K6™
MMXTM Enhanced Processor Data Sheet, order# 20695, for more
information.
Note: The BIOS should enable the write allocate mechanisms only
after performing any memory sizing and typing algorithms.
AMD-K6™ MM)(TM Enhanced Processor
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Machine Check Exception
The AMD-K6 processor does not support the generation of a
machine check exception.
The processor provides a 64-bit Machine Check Address
Register (MCAR) and a 64-bit Machine Check Type Register
(MCTR), but because the processor does not support machine
check exceptions, the contents of the MCAR and MCTR are
only affected by the WRMSR instruction and by RESET being
sampled asserted (where all bits in each register are reset to 0).
The processor also provides the Machine Check Exception
(MCE) bit in Control Register 4 (CR4, bit 6) as a read-write bit.
However, the state of this bit has no effect on the operation of
the processor.
The processor does not provide the BUSCHK and PEN signals
provided by Pentium.
New AMD-K6™ Processor Instructions
This section documents and explains the new instructions
added to the AMD-K6 processor above and beyond the AMD-K5
processor.
•
•
•
SYSCALL
SYSRET
MMXTM Instructions-57 new instructions for multimedia
software. See "MMXTM Instructions" on page 127.
System Call Extensions
Setting bit 0 (SCE) in the Extended Feature Enable Register
(See "Extended Feature Enable Register (EFER)" on
page 118) enables the system call extensions. The system call
extensions consist of two new instructions, SYSCALL and
SYSRET, that allow OS vendors fast protection-level switching
to and from CPLO.
122
AMD-K6™ MMJrM Enhanced Processor
AMD ~
Preliminary Information
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
SYSCALL
mnemonic
opcode
description
SYSCALL
OFosh
Call operating system
Privilege:
Registers Affected:
Rags Affected:
Machine State Affected:
Exceptions Generated:
none
ECX, EIP, CS, SS
IF,VM
CPL, CS (base, limit, attr), SS (base, limit, attr)
Virtual
Exception
Invalid opcode (6)
Real
X
8086
X
Protected
X
Description
The System Call Extension bit (SCE) of the Extended Feature Enable Register
(EFER) is set to o. (The EFER register is MSR Cooo_ooaoh.)
The SYSCALL instruction provides a fast method for transferring control to a fixed
entry point in an operating system.
The EIP register is copied into the ECX register. Bits 31-0 of the 64-bit SYSCALL
Target Address Register (See "SYSCALL Target Address Register (STAR)" on
page llB) are copied into the EIP register. (The STAR register is Model-Specific
Register COOO_OOBlh.)
The IF and VM flags are set to 0 to disable interrupts and force the processor out of
Virtual-BOB6 mode.
New selectors are loaded with no checking performed as follows:
•
•
Bits 47-32 of the STAR register are copied into the CS register
(Bits 47-32 of the STAR register) + B are copied into the SS register
The CS and SS registers must not be modified by the operating system between the
execution of the SYSCALL instruction and its corresponding SYSRET instruction.
The processor's CPL is set to 0 regardless of the value of bits 33-32 of the STAR
register. There are no permission checks of the CPL, Real mode, or Virtual-BOB6
mode.
AMD-K6™ MMlF Enhanced Processor
121
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The following descriptors are loaded to specify fixed 4-Gbyte flat segments as follows:
•
•
•
•
The CS_base and the SS_base are both set to zero
The CS_limit and the SS_limit are both set to 4-Gbyte
The CS segment attributes are set to Read-only
The SS segment attributes are set to Read-Write and Expand-Up
The operating system must set the STAR register and the appropriate descriptor
table entries to reflect the values loaded by the processor during the SYSCALL
instruction.
Related Instructions
124
See the SYSRET instruction.
AMD-K6™ MMJrM Enhanced Processor
Preliminary Information
AM D ~
AMD K86™ Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
SYSRET
mnemonic
opcode
description
SYSRET
OF07h
Return from operating system
Privilege:
Registers Affected:
Flags Affected:
Machine State Affected:
Exceptions Generated:
CPL=O
EIP, CS, SS
IF
CPL, CS (base, limit, attr)
Exception
Invalid opcode (6)
General protection (13)
Real
Virtual
8086 Protected
X
X
X
X
X
X
Description
The System Call Extension bit (SCE) of the Extended Feature Enable Register
(EFER) is set to o. (The EFER register is MSR COOO_OOSOh.)
The CPL is not equal to o.
The SYSRET instruction is the return instruction used in conjunction with the
SYSCALL instruction to provide fast entry/exit to an operating system.
The ECX register, which points to the next sequential instruction after the
corresponding SYSCALL instruction, is copied into the EIP register.
The IF flag is set to 1 in order to enable interrupts.
New selectors are loaded without any checking as follows:
•
•
•
•
Bits 47-32 of the STAR register are copied into the CS register
Bits 1-0 of the CS register are set to llb (CPL of 3), regardless of the value of bits
33-32 of the STAR register
(Bits 47-32 of the STAR register) + 16 are copied into the SS register
Bits 1-0 of the SS register are set to llb (RPL of 3), regardless of the value of bits
33-32 of the STAR register
The CS and SS registers must not be modified by the operating system between the
execution of the SYSCALL instruction and its corresponding SYSRET instruction.
If the CPL is not equal to 0 when the SYSRET instruction is executed, a general
protection fault exception is generated with an error code of O.
AMD-K6™ MMJrM Enhanced Processor
125
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Preliminllry Informtdion
AMD K8fYM Family BIOS and Software Tools Developers Guide
21062E/O-June 1997
A new descriptor is loaded for CS to specify a fixed 4-Gbyte flat segment as follows:
•
•
•
The CS_base is set to zero
The CS_limit is set to 4-Gbyte
The CS segment attributes are set to Read-only
The operating system must set the STAR register and the appropriate descriptor
table entries to reflect the values loaded by the processor during the SYSCALL
instruction.
Related Instructions
126
See the SYSCALL instruction.
AMD-K6™ MMJrM Enhanced Processor
Pre/iminory Informotion
AMD ~
AMD K86™ Family BIOS and Software Tools Developers Guide
21 062E/O- June 1997
MMXTM Instructions
The AMD-K6 MMX enhanced processor implements the
complete MMX instruction set. For a detailed description refer
to AMD-K6™ MMXTM Enhanced Processor Multimedia
Technology, order# 20726, located at http://www.amd.com.
Table 42 lists the MMX instructions.
Table 42. MM)(TM Instructions and Descriptions
Instruction
EMMS
MOVD
MOVQ
PACKSSWB jPACKSSDW
PACKUSWB
PADDBjPADDWjPADDD
PADDSBjPADDSW
PADDUSBjPADDUSW
PAND
PANDN
PXOR
POR
PCMPEQBjPCMPEQWjPCMPEQD
PCMPGTBjPCMPGTWjPCMPGTD
PMADDWD
PMUllW
PMUlHW
PSllWjPSlLDjPSllQ
PSRAWjPSRAD
PSRlWjPSRLDjPSRlQ
PSUBBjPSUBWjPSUBD
PSUBSBjPSUBSW
PSUBUSBjPSUBSW
PUNPCKHBWjPUNPCKHWDjPUNPCKHDQ
PUNPCKlBWjPUNPCKlWDjPUNPCKLDQ
AMD-K6™ MM)(fM Enhanced Processor
Description
Empty MMX State
Move 32 Bits
Move 64 Bits
Pack with Signed Saturation
Pack with Unsigned Saturation
Packed Add
Packed Add with Saturation
Packed Add Unsigned with Saturation
Bitwise logical And
Bitwise logical And Not
Bitwise logical Exclusive OR
Bitwise logical OR
Packed Compare for Equal
Packed Compare for Greater Than
Packed Multiply and Add
Packed Multiply low
Packed Multiply High
Packed Shift left logical
Packed Shift Right Arithmetic
Packed Shift Right logical
Packed Subtract
Packed Subtract with Saturation
Packed Subtract Unsigned with Saturation
Unpack High Packed Data
Unpack low Packed Data
127
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Preliminllry Informlltion
AMD K86™ Family BIOS and Software Tools Developers Guide
128
21 062E/O- June 1997
AMD-K6™ MMJrM Enhanced Processor
Preliminary Information
21062EjO-June 1997
AMD~
AMD K86™ Family BIOS and Software Tools Developers Guide
Index
Numerics
4-Kbyte Paging .................................... 61
4-Mbyte Pages .................................. 60, 64
4-Mbyte Paging ........ ~ ........................... 62
A
Additions to the EFLAGS Register .................... 58
ALLO ............................................. 47
ALL!. ............................................ 47
A1dI)-K5 Processor .................................. 5
CPU IDs and BIOS boot strings ...................... 4
device identification register ...................... 45
110 trap dword ................................... 14
instructions ..................................... 85
RESET state .................................... 18
state-save area ................................... 10
system management mode (SMM) ................... 7
test and debug ................................... 21
x86 architecture extensions ........................ 57
A1dI)-K6 MMX Enhanced Processor ................... 95
cache ......................................... 104
CPU IDs and BIOS boot strings ................... _.. 4
device identification register ..................... 110
110 trap dword .................................. 101
instructions .................................... 122
RESET state ................................... 102
state-save area ................................... 98
system management mode (SMM) .................. 97
test and debug ................................. _105
x86 architecture extensions ....................... 117
Array Access Register (AAR) ..................... 28, 82
Array IDs in Array Pointers ......................... 29
Array Pointer ...... _........ _..................... 28
Array Test Data ................ _................ 28-29
Auto Halt Restart ............ _................. 13, 101
B
BIOS Consideration Checklist ............. :'........ 5, 95
BIST Error Bit Definition ........................... 25
Bits
DBP ............................................ 23
DC ............................................. 24
DDC ..................... _..................... 23
DE ............................................. 59
DIC ............................................ 23
DSPC .......................................... 24
G ........................................... 64,66
GPE ........................................... 59
MCE ........................................ 59-60
PS ...................... ; ................... 64,66
PSE ............................................ 59
PVI ...................... _ .................. 59, 79
TSC ............................................ 81
TSD ......................................... 59,81
VIF ......................................... 68, 71
VIP ......................................... 68,71
Vl\fE .................. _.. _ .................. 59, 67
Index
Boundary Scan .............. _..................... 41
architecture .............. _..................... 42
register (BSR) ............................... 44, 108
register bit definitions ....................... 49, 109
test access port (TAP) ...... _.................... 107
test functional description .. _..................... 42
Branch Tracing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 39
Built-In Self-Test (BIST) ........................ 24, 106
BUSCHK# ........................................ 17
BYPASS instruction .......... _................. 48, 112
Bypass Register (BR) ......... _................. 45, 110
c
Cache Testing ............ _................... 6,27, 96
Clocks, Disable Stopping ........................... 24
CMPXCHG8B instruction .. _........................ 87
Control Bit Definitions ............................. 49
Control Register 4 (CR4) ........................ 58-59
CPU Identification Algorithms ....................... 3
CPU Speed Detection ..... _...................... 6, 96
CPUID instruction .......... _............. 5, 86, 95, 105
CR4 ............................................. 88
D
DBP ............................................. 23
DC ..................... _ ........................ 24
DDC ............................................. 23
DE .............................................. 59
Debug .......................................... 113
branch tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 39
compatibility with the Pentium processor ........... 39
control. ................................. _...... 24
extensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 59
110 breakpoints ....• . . . . . . . . . . . . . . . . . . . . . . . . . . .. 38
port ........................................... 57
registers ............................... 38, 113-116
Device Identification Register (DIR) ............. 45, 110
DIC ............................................. 23
Disable Branch Prediction .......................... 23
Disable Data Cache ......... _...................... 23
Disable Instruction Cache .•.................. _ ...... 23
Disable Stopping Processor Clocks . . . . . . . . . . . . . . . . . .. 24
DSPC ............................................ 24
E
EFLAGS Register ........................ _ . . . . . . .. 70
Enable Write Allocate .............................. 85
Exceptions ............ _. . . . . . . . . . . . . . . . . . . . . . . . .. 75
in SMM .............. _......... _........... 16, 101
machine check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 60
summary ....................................... 17
Extensions
extended feature enable register (EFER) .......... 118
VIF and VIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 68
EXTEST instruction ........................... 46, 111
129
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Preiiminory Informotion
AMD K86™ Family BIOS and Software Tools Developers Guide
F
21 062EjO-June 1997
G
Interrupts
hardware ....................................... 68
in SMM .................................... 16, 101
interrupt-table access ............................ 78
IRB ............................................ 68
redirection .................................. 67, 75
software .......................... ~ . . . . . . . . . . .. 75
summary ....................................... 17
virtual ...................................... 68, 71
INTR ............................................ 17
IRB ........................................... 68,75
G ............................................. 64, 66
Global Page Extension ........................ 59, 64-66
Global Pages ................................... 64-66
GPE ............................................. 59
JTAG ........................................ 44, 105
H
L
Halt Restart Slot ............................... 13, 101
Halt State ......................................... 24
Hardware Configuration Register (HWCR) ....... 22-23,82
Hardware Debug Tool (HDT) ........................ 57
Hardware Interrupts ............................... 68
HDT ............................................. 57
HIGHZ instruction ............................. 47, 112
HWCR ..................................... 22-23,82
Ll Cache Inhibit ............................... " 112
Flags
VIF ......................................... 68,
VIP ......................................... 68,
Float Test .........................................
FLUSH# ..........................................
Functional-Redundancy Checking ....................
71
71
26
17
40
110
breakpoint extension ............................. 38
breakpoints ..................................... 38
trap dword .................................. 14, 101
trap restart Slot ........................... 14-15, 101
mCODE instruction ....... '" .................. 47,112
lliegal Instructions ................................. 93
INIT ............................................. 17
Initial Register Values ............................ 9, 97
Instruction Register (IR) ........................ 44, 107
Instructions ................................ _... 60, 85
BYPASS ........................................ 48
CMPXCHG8B ................................... 87
CPUID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 5, 86, 95
EXTEST ............................. '" .... 46,111
HIGHZ ..................................... 47,112
mCODE .................................... 47,112
illegal .......................................... 93
modification of the IF or VIF flags ............... 71-75
MOV to/from CR4 ................................ 88
public TAP ................................... 45-46
RDMSR ........................................ 90
RDTSC ......................................... 89
RSM ........................................... 92
RUNBIST ....................................... 48
SAMPLEIPRELOAD .............................. 46
SYSCALL .................................. 122-123
SYSRET ................................... 122, 125
USEHDT ....................................... 57
WRMSR ........................................ 90
Interrupt Redirection ............................... 67
Interrupt Redirection Bitmap (IRB) ................ 68, 75
130
J
M
Machine Check Exception ....................... " 122
Machine-Check Address Register (MCAR) ...... 60,80,117
Machine-Check Enable. . . . . . . . . . . . . . . . . . . . . . . . .. 59-60
Machine-Check Exception . . . . . . . . . . . . . . . . . . . . . . . . .. 60
Machine-Check Type Register (MCTR) ..... 60, 80-81, 117
MMX Instructions and Descriptions ............... " 127
Mode, Operating ................................... 7
Model·Specific Registers (MSRs) ............ 6, 79, 96, 117
MOV to/from CR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 88
MSRs ................................... 6,79,96,117
multimedia software ............................ " 127
N
NMI ............................................. 17
Normal BIST. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 25
o
Ope odes, Reserved ................................ 93
Operating Mode .................................... 7
Output-Float Test .................................. 26
p
Page Size ...................................... 64, 66
Page Size Extension ............................. 59-60
Page-Directory Entry (PDE) ...................... 63-64
Pages, 4-Mbyte ................................. 60, 64
Page-Table Entry (PTE) ............................ 66
Paging
global. ...................................... 64-66
page size ................................. '.' . 64, 66
page-directory entry .......................... 63-64
page-table entry ................................. 66
PDE .......................................... 63-64
Probe Mode ...................................... 57
Protected Mode
instructions that modify the IF or VIF flags. . . . . . . . .. 72
virtual interrupt extensions ....................... 75
Index
Pre/iminory Informotion
21062E/O- June 1997
AMD K86™ Family BIOS and Software Tools Developers Guide
Protected Virtual Interrupts ...................... 59, 79
PS ............................................ 64, 66
PSE .............................................. 59
PTE .............................................. 66
Public Instructions ................................. 45
Public TAP Instructions ................... , ......... 46
PVI ........................................... 59,79
R
RESET ..................................... 18, 102
SMI# ......... ' ................................. 17
STPCLK# ...................................... 17
SMM ............................ : ................ 7
base address ................................ 12, 100
exceptions and interrupts in SMM .............. 16, 101
halt restart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 13
110 restart ............................... 14-15, 101
110 trap dword .............................. 14, 101
initial state of registers ......................... 9, 97
RIS# .....•......•.••••.....•..................••. 17
RDMSR .......................................... 90
RDTSC ........................................... 89
Real Mode, Instructions That Modify the IF or VIF Flags. 71
Registers ......................................... 43
MSR 85h ....................................... 84
MSR 86h ....................................... 84
AAR ........................................... 28
BR ......................................... 45,110
CR4 ...................................... 58-59, 88
debug .................................. 38, 113-116
default values .................................... 7
DIR ........................................ 45,110
DRO ........................................... 116
DRl. .......................................... 116
DR2 ........................................... 116
DR3 ........................................... 116
DR4 ........................................... 115
DR5 ........................................... 115
DR6 ........................................... 115
DR7 ........................................... 114
DR7-DRO ....................................... 38
EFER ......................................... 118
EFLAGS ........................................ 70
HWCR ................................... 22-23,82
IR ......................................... 44,107
JTAG .......................................... 44
MCAR .................................. 60,80,117
MCTR .................................. 60,80,117
model·specific ......................... 6, 79, 96, 117
MSRs ................................ 6, 79,96, 117
SMM initial values ............................. 9, 97
STAR ......................................... 118
TR12 .......................................... 118
TSC ........................................... 118
WAPMRR ...................................... 84
WATMCR ....................................... 84
WHCR .................................... 119-120
Reserved Opcodes ................................. 93
RESET state .................................. 18, 102
RSM instruction ................................... 92
RUNBIST instruction ............................... 48
5
SAMPLEIPRELOAD instruction .................. 46, 112
Segment Register Attributes ..................... 20, 103
Signals
BUSCHK# ...................................... 17
FLUSH# ........................................ 17
INIT ........................................... 17
INTR ........................................... 17
NMI ............................................ 17
RlS# ........•...•..•.....................•....• 17
Index
AM D~
::':~~;: :::::::::::::::::::::::::::::::::::::.6: .9;
revision identifier ........................... 12, 100
RSM instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 92
state·save area ............................. 9-10, 98
Software Extensions
4·Mbyte pages ............................... 64, 66
branch tracing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 39
debug control ................................... 24
debugging extensions (DE) ........................ 59
disable branch prediction. . . . . . . . . . . . . . . . . . . . . . . .. 23
disable data cache ............................... 23
disable instruction cache ......................... 23
disable stopping processor Clocks .................. 24
global page extension (GPE) ................ 59, 64-66
110 breakpoints ................................. 38
interrupt redirection bitmap (IRB) ................. 75
machine check. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 59
machine check enable (MCE) ...................... 60
page size extension (PSE) ...................... 59-60
protected virtual interrupts (PVI) ............... 59, 79
system call ................................. 60, 122
time stamp disable (TSD) .................. 59, 81, 118
Virtual·8086 Mode extension (VME) ............. 59, 67
Software Interrupts ................................ 75
Standard Debug Functions .......................... 38
State
halt ........................................... 24
stop· grant . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 24
State of the AMD·K5 Processor After INIT. . . . . . . . . . . .. 20
State of the AMD·K5 Processor After RESET .......... 18
State of the AMD·K6 Processor After INIT ............ 104
State of the AMD·K6 Processor After RESET. . . . . . . .. 102
Stop·Grant State .................................. 24
STPCLK# ........................................ 17
SYSCALL instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 123
SYSCALL Target Address Register (STAR) ....... 118-119
SYSRET. instruction ......... . . . . . . . . . . . . . . . . . . . .. 125
System Call ................................... 60, 122
System Management Mode. See SMM
T
TAP Instructions ................................. 111
BYPASS ................................... 48, 112
HIGHZ ..................................... 47, 112
mCODE ................................... 47, 112
RUNBIST ...................................... 48
SAMPLEIPRELOAD ......................... 46, 112
TAP Instructions ................................. 111
TAP Registers ................................... 107
Task State Segment (TSS) .......................... 77
131
AMD ~
Pre/iminory /nformotion
AMD K86™ Family BIOS and Software Tools Developers Guide
Test
AAR ........................................... 28
arrays .......................................... 27
cache .......... : ............................... 27
float ........................................... 26
functional redundancy ............................ 40
HDT ........................................... 57
HWCR ................................... 22-23,82
TLB ................................... : ........ 27
Test Access Port (TAP) BIST ......................... 26
Test Formats
4·Kbyte TLB for All Models of the AMD·K5 Processor .. 36
4·Mbyte TLB for All Models of the AMD-K5 Processor. 37
Dcache Data for All Models of the AMD-K5 Processor . 32
Dcache Tags for the AMD-K5 Processor Model 0 ...... 30
Dcache Tags for the AMD-K5 Processor Model 1 and
Greater. .................................... 31
Icache Instructions for the AMD-K5 Processor Model O. 35
Icache Instructions for the AMD-K5 Processor Modell
and Greater ................................. 35
Icache Tags for the AMD-K5 Processor Model 0 ....... 33
Icache Tags for the AMD-K5 Processor Modell and
Greater ..................................... 34
Test Register 12 (TR12) ............................ 118
Time Stamp Counter (TSC) ............... 59, 81, 89, 118
Time Stamp Disable ........................ 59, 81, 118
TLB Testing ....................................... 27
Top of Memory...................................... 83
Tristate Test ...................................... 26
Tri-State Test Mode ............................... 106
TSC ................................... 59, 81, 89, 118
TSD ............................................ 59,81
ll2
21 062E/O- June 1997
U
USEHDT ......................................... 57
v
VIF ............................................ 68, 71
VIP ........................................... 68, 71
Virtual Interrupt Flag (VIF) ...................... 68, 71
Virtual Interrupt Pending (VIP) flag ............... 68, 71
Virtual·8086 Mode Extensions (VME) .............. 59, 67
Virtual-8086 Mode Interrupt Extensions (VME) ........ 74
Virtual-Interrupt Additions to EFLAGS Register ....... 71
VME ......................................... 59,67
w
Write Allocate
enable ......................................... 85
enable 15-to-16-Mbyte........................... 121
enable limit ................................... 121
fixed range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83
programmable memory range register (WAPMRR) . .. 84
programmable range. . . . . . . . . . . . . . . . . . . . . . . . . . . .. 83
registers .... _.............................. 82, 119
top-of-memory and control register (WATMCR) ...... 84
write cacheability detection enable ............... 120
Write Handling Control Register (WHCR) ...... " 119-120
WRMSR instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 90
Index
Sales Offices '
North American
ALABAMA ..................................................................... (205) 830-9192
ARIZONA ...................................................................... (602) 242-4400
CALIFORNIA,
Calabasas .....................•.......................................... (818) 878-9988
Irvine ................................... : .....................: .............. (714) 450-7500
Sacramento (Roseville) ........................................... (916) 786-6700
San Diego •................•.............................................. (619) 560-7030
San Jose .••.......................•....................................... (408) 922-0300
CANADA, Ontario,
Kanata ..................................................................... (613) 592-0060
Woodbridge ............•................................................ (905) 856-3377
COLORADO ......................•..........................................• (303) 741-2900
CONNECTICUT ............................................................ (203) 264-7800
FLORIDA,
Clearwater .........................•..................................... (813) 530-9971
Ft. Lauderdale ......................................................... (954) 938-9550
Or1ando (Longwood) ................................ :.............. (407) 862-9292
GEORGIA •.................................................................... (770) 449-7920
IDAHO .....•..................................................................... (208) 377-0393
ILLINOIS, Chicago (Itasca) .......................................... (708) 773-4422
KENTUCKy ................................................................... (606) 224-1353
MARYLAND .................................................................. (410) 381-3790
MASSACHUSETTS ..................................................... (617) 273-3970
MINNESOTA ................................................................. (612) 938-0001
NEW JERSEY,
Cherry Hill ................................................................ (609) 662-2900
Parsippany ............................................................... (201) 299-0002
NEW YORK,
Brewster ................................................................... (914) 279-8323
Rochester .....•.......................................................... (716) 425-8050
NORTH CAROLINA,
Charlotte ..................................•............................... (704) 875-3091
Raleigh ............................................•........................ (919) 878-8111
OHIO,
Columbus (Westerville) ........................................... (614) 891-6455
Dayton ..............................•...................................... (513) 439-0268
OREGON ...................................................................... (503) 245-0080
PENNSYLVANIA ........................................................... (610) 398-8006
TEXAS,
Austin ....................................................................... (512) 346-7830
Dallas ....................................................................... (214) 934-9099
Houston ................................................................... (713) 376-8084
International
AUSTRALIA, N Sydney ........ TEL ............................ (61) 29959-1937
FAX ............................ (61) 29959-1037
BELGIUM, Antwerpen .......... TEL ................................. (03) 248-4300
FAX ................................. (03) 248-4642
CHINA,
Beijing ............................. TEL ............................. (8610) 501-1566
FAX ............................. (8610) 465-1291
Shanghai ......................... TEL ........................... (8621) 6267-8857
TEL ........................... (8621) 6267-9883
FAX ........................... (8621) 6267-8110
FINLAND, Helsinki ............... TEL ............................ (358) 9 881 3117
FAX ............................ (358) 9 8041110
FRANCE, Paris .................... TEL ................................ (1) 49-75-1010
FAX ................................ (1) 49-75-1013
GERMANY,
Bad Homburg .................. TEL ................................ (06172) 92670
FAX ................................ (06172) 23195
MOnchen ......................... TEL .................................. (089) 450530
FAX .................................. (089) 406490
HONG KONG, Kowloon ....... TEL ............................. (852) 2956-0388
FAX ............................. (852) 2956-0588
ITALY, Milano ....................... TEL .................................... (02) 381961
FAX ............................... (02) 3810-3458
JAPAN,
Osaka ............................. TEL ................................. (06) 243-3250
FAX ................................. (06) 243-3253
Tokyo ............................... TEL ............................... (03) 3346-7600
FAX ............................... (03) 3346-5197
KOREA, Seoul ..................... TEL
FAX
SINGAPORE, Singapore ...... TEL
FAX
SCOTLAND, Stirling ............. TEL
FAX
SWITZERLAND, Geneva ..... TEL
FAX
SWEDEN,
Stockholm area ............... TEL
(Bromma)
FAX
TAIWAN, Taipei ................... TEL
FAX
UNITED KINGDOM,
London area .................... TEL
(Woking)
FAX
Manchester area ............. TEL
(Warrington)
FAX
............................... (82) 2784-0030
............................... (82) 2784-8014
................................. (65) 337-7033
................................. (65) 338-1611
........................... (44) 7186-450024
........................... (44) 1786-446188
............................ (41) 22-788-0251
............................ (41) 22-788-0617
................................. (08) 629-2850
................................... (08) 98-0906
............................. (886) 2715-3536
............................. (886) 2712-2182
.............................
.............................
.............................
.............................
(01483)
(01483)
(01925)
(01925)
74-0440
75-6196
83-0380
83-0204
North American Representatives
ARIZONA,
Scottsdale - THORSON DESERT STATES ...........
CALIFORNIA,
Chula Vista - SONIKA ELECTRONICA ..................
CANADA,
Burnaby, B.C. - DAVETEK MARKETING ...............
Dorval, Quebec - POLAR COMPONENTS ............
Kanata, Ontario - POLAR COMPONENTS ............
Woodbridge, Ontario - POLAR COMPONENTS ....
ILLINOIS,
Skokie -INDUSTRIAL REPS, INC .........................
INDIANA,
Kokomo - SCHILLINGER ASSOC .........................
IOWA,
Cedar Rapids - LORENZ SALES ...........................
KANSAS,
Merriam - LORENZ SALES ....................................
Wichita - LORENZ SALES .....................................
MEXICO,
Guadalajara - SONIKA ELECTRONICA ................
Mexico City - SONIKA ELECTRONICA .................
Monterrey - SONIKA ELECTRONICA ....................
MICHIGAN,
Brighton - COM-TEK SALES, INC .........................
Holland - COM-TEK SALES, INC ..........................
MINNESOTA,
Edina- MEL FOSTER TECH. SALES, INC ...........
MISSOURI,
St Louis - LORENZ SALES ....................................
NEBRASKA,
Lincoln - LORENZ SALES .....................................
NEW YORK,
Plainview - COMPONENT CONSULTANTS ..........
East Syracuse - NYCOM .......................................
Fairport - NYCOM ..................................................
OHIO,
Centerville - DOLFUSS ROOT & CO .....................
Powell- DOLFUSS ROOT & CO ...........................
Middleburg Hts - DOLFUSS ROOT & CO ..............
PUERTO RICO,
Caguas - COMP REP ASSOC, INC .......................
UTAH,
Murray - FRONT RANGE MARKETING ................
WASHINGTON,
Kirkland - ELECTRA TECHNICAL SALES .............
WISCONSIN,
Pewaukee -Industrial Representatives, Inc ...........
(602) 998-2444
(619) 498-8340
(604) 430-3680
(514) 683-3141
(613) 592-8807
(416) 410-3377
(847) 967-8430
(317) 457-7241
(319) 377-4666
(913) 469-1312
(316) 721-0500'
(523) 647-4250
(525) 754-6480
(528) 358-9280
(810) 227-0007
(616) 335-8418
(612) 941-9790
(314) 997-4558
(402) 475-4660
(516) 273-5050
(315) 437-8343
(716) 425-5120
(513) 433-6776
(614) 781-0725
(216) 816-1660
(787) 746-6550
(801) 288-2500
(206) 821-7442
(414) 574-9393
Advanced Micro Devices reserves the right to make changes in its product without notice in order to improve design or performance characteristics. The
performance characteristics listed in this document are guaranteed by specific tests, guard banding, design and other practices common to the industry. Forspecific
testing dotails, contact your local AMD sales representative. The company assumes no responsibility for the use of any circuits described herein.
~
RECYCLED &
RECYClABLE
©1997 Advanced Micro Devices. Inc.
01197
AMD~
One AMD Place
P.O. Box 3453
Sunnyvale,
California 94088-3453
408-732-2400
Toll Free 800-538-8450
TWX 910-339-9280
TELEX 34-6306
TECHNICAL SUPPORT &
LITERATURE ORDERING
USA 800-222-9323
USA PC CPU Technical Support 408-749-3060
JAPAN 03-3346-7550
Fax 03-3346-9628
FAR EAST Fax 852-2956-0599
EUROPE & UK 44-(0)-1276-803299
Fax 44-(0)-1276-803298
BBS 44-(0)-1276-803211
FRANCE 0590-8621
GERMANY 089-450-53199
ITALY 1678-77224
ARGENTINA 001-800-200-1111,
after tone 888-263-8500
BRAZIL 000-811-718-5573
CHILE 800-570-048
MEXICO 95-800-263-4758
PC CPU Technical Support E-mail: hwsupt@brahms.amd.com
Europe Technical Support E-mail: euro.tech@amd.com
Europe Literature Request E-mail: euro.lit@amd.com
http://www.amd.com
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