RM25C256C-L 256 Kbit 1.65V Minimum Non

RM25C256C-L
256 Kbit 1.65V Minimum
Non-volatile Serial EEPROM
SPI Bus
Preliminary Datasheet
Features
 Memory array: 256 Kbit non-volatile serial EEPROM memory
 Single supply voltage: 1.65V - 3.6V
 Serial peripheral interface (SPI) compatible
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-Supports SPI modes 0 and 3
1.6 MHz maximum clock rate for normal read
10 MHz maximum clock rate for fast read
Flexible Programming
- Byte/Page Program (1 to 64 Bytes)
- Page size: 64 Bytes
Low Energy Byte Write
-Byte Write consuming 50 nJ
Low power consumption
-0.25 mA active Read current (Typical)
-1 mA active Write current (Typical)
-2.2 µA power down current (Typical)
Fast Page Write
-Page Write in 3 ms (64 byte page)
-Byte Write within 60 µs
Industry’s lowest read cycle latency
Unlimited read cycles
Page or chip erase capability
8-lead SOIC, TSSOP and WLCSP packages
RoHS-compliant and halogen-free packaging
Data Retention: >40 years at 125°C
Endurance: 100,000 Write Cycles (for both byte and page write cycles)
- No degradation across temperature range
No data loss under UV exposure on bare die or WLCSP
Based on Adesto's proprietary CBRAM® technology
Description
The Adesto® RM25C256C-L is a 256 Kbit, serial EEPROM device that utilizes
Adesto's CBRAM® resistive memory technology. The memory devices use a single
low-voltage supply ranging from 1.65V to 3.6V.
The RM25C-Series family is accessed through a 4-wire SPI interface consisting of a
Serial Data Input (SDI), Serial Data Output (SDO), Serial Clock (SCK), and Chip
Select (CS). The maximum clock (SCK) frequency in normal read mode is 1.6 MHz. In
fast read mode the maximum clock frequency is 10 MHz.
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Writing into the device can be done from 1 to 64 bytes at a time. All writing is internally self-timed. The device also
features an Erase which can be performed on 64 byte pages or on the whole chip.
Adesto's EEPROM endurance can be as much as 40X higher than industry standard EEPROM devices operating in byte
write mode at 85°C. Unlike EEPROMs based on floating gate technology (which require read-modify-write on a whole
page for every write operation) CBRAM write endurance is based on the capability to write each byte individually,
irrespective of whether the user writes single bytes or an entire page. Additionally, unlike floating gate technology,
CBRAM does not experience any degradation of endurance across the full temperature range. By contrast, in order to
modify a single byte, most EEPROMs modify and write full pages of 32, 64 or 128 bytes. This provides significantly less
endurance for floating gate devices used in byte write mode when compared to page write mode.
The device has both Byte Write and Page Write capability. Page Write is 64 bytes. The Byte Write operation of CBRAM
consumes only 10% of the energy consumed by a Byte Write operation of EEPROM devices of similar size.
The Page Write operation of CBRAM is 4-6 times faster than the Page Write operation of similar EEPROM devices.
Both random and sequential reads are available. Sequential reads are capable of reading the entire memory in one
operation.
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Block Diagram
Figure 1-1. Block Diagram
VCC
Status
Registers
&
Control
Logic
I/O Buffers and Data
Latches
Page Buffer
SCK
SDI
SDO
CS
Y-Decoder
SPI
Interface
WP
HOLD
GND
Address
Latch
&
Counter
X-Decoder
1.
32 Kb - 512 Kb
CBRAM
Memory
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2.
Absolute Maximum Ratings
Table 2-1.
Absolute Maximum Ratings(1)
Parameter
Specification
Operating ambient temp range
-40°C to +85°C
Storage temperature range
-65°C to +150°C
Input supply voltage, VCC to GND
Voltage on any pin with respect to GND
- 0.3V to 3.6V
-0.5V to (VCC + 0.5V)
ESD protection on all pins (Human Body Model)
>2kV
Junction temperature
125°C
DC output current
5mA
1. CAUTION: Stresses greater than Absolute Maximum Ratings may cause permanent damage to the devices. These
are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in other
sections of this specification, is not implied. Exposure to absolute maximum rating conditions for extended periods
may reduce device reliability
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3.
Electrical Characteristics
3.1
DC Operating Characteristics
Applicable over recommended operating range: TA = -40°C to +85° C, VCC = 1.65V to 3.6V
Symbol
Parameter
Condition
Min
Typ
Max
Units
3.6
V
1.55
V
1.0
3
mA
0.25
0.5
mA
1
3
mA
@25C
80
90
@85C
100
120
@25C
45
55
@85C
65
75
@25C
2.2
3
@85C
11
17
@25C
2.2
3
@85C
11
17
@25C
1.6
2.5
@85C
11
17
TA = ‐40°C to +85° C, VCC = 1.65V to 3.6V
VCC
Supply Range
1.65
VVccI
VCC Inhibit
ICC1
Supply current, Fast
Read
ICC2
Supply Current,
Read Operation
VCC= 3.3V SCK at 1.0 MHz
SDO = Open, Read
ICC3
Supply Current,
Program or Erase
VCC= 3.3V, CS = VCC
VCC= 3.3V SCK at 10 MHz
SDO = Open, Read
Supply Current,
Standby, LPSE=0
ICC4
Supply Current,
Standby, LPSE=1
VCC= 3.3V, CS = VCC
Supply Current, Standby,
Auto Power Down
enabled
µA
ICC5
Supply Current,
Power Down
VCC= 3.3V Power Down
ICC6
Supply Current,
Ultra Deep Power Down
Vcc = 3.3V,
Ultra Deep Power Down
IIL
Input Leakage
SCK, SDI, CS, HOLD, WP
VIN=0V to VCC
1
µA
IOL
Output Leakage
SDO , CS = VCC VIN=0V to VCC
1
µA
VIL
Input Low Voltage
SCK, SDI, CS, HOLD, WP
-0.3
VCC x 0.3
V
VIH
Input High Voltage
SCK, SDI, CS, HOLD, WP
VCC x 0.7
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 3.0mA
0.4
V
VOH
Output High Voltage
IOH = -100µA
VCC - 0.2
µA
µA
V
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3.2
AC Operating Characteristics
Applicable over recommended operating range: TA = -40°C to +85° C, VCC = 1.65V to 3.6V
CL = 1 TTL Gate plus 10pF (unless otherwise noted)
Symbol
Parameter
Min
fSCKF
SCK Clock Frequency for Fast Read Mode
fSCK
Typ
Max
Units
0
10
MHz
SCK Clock Frequency for Normal Read Mode
0
1.6
MHz
fAPD
SCK Clock Frequency for Auto Power Down Mode
0
1.0
MHz
tRI
SCK Input Rise Time
1
µs
tFL
SCK Input Fall Time
1
µs
tSCKH
SCK High Time
7.5
ns
tSCKL
SCK Low Time
7.5
ns
tCS
CS High Time
100
ns
tCSS
CS Setup Time
10
ns
tCSH
CS Hold Time
10
ns
tDS
Data In Setup Time
4
ns
tDH
Data In Hold Time
4
ns
tHS
HOLD Setup Time
30
ns
tHD
HOLD Hold Time
30
ns
tOV
Output Valid
tOH
Output Hold Time Normal Mode
0
tLZ
HOLD to output Low Z
0
tHZ
6.5
ns
ns
200
ns
HOLD to output High Z
200
ns
tDIS
Output Disable Time
100
ns
tPW
Page Write Cycle Time, 64 byte page (up to 30K write cycles)
3
Page Write Cycle Time, 64 byte page (up to 100K write cycles)
18
Byte Write Cycle Time
60
tBP
(1)
5
ms
100
µs
75
µs
tPUD
Vcc Power-up Delay
tRPD
Exit Power Down Time
50
µs
tCSLU
Minimum Chip Select Low to Exit
Ultra-Deep Power-Down
20
ns
tXUDPD
Exit Ultra-Deep Power Down Time
70
µs
tRDPD
Chip Select High to Standby Mode
8
µs
CIN
SCK, SDI, CS, HOLD, WP
VIN=0V
6
pf
COUT
SDO VIN=0V
8
pf
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Symbol
Parameter
Min
Typ
Endurance
Max
Units
100,000(2)
Write
Cycles
Unlimited
Read
Cycles
40
Years
Retention
Notes: 1. VCC must be within operating range.
2. Adesto memory products based on CBRAM technology are “Direct‐Write” memories. Endurance cycle calculations follow JEDEC specification JESD22‐A117B. Endurance data characterized at 2.5V, +85° C. Endurance specification is identical for both byte and page write (unlike current EEPROM technologies where byte write operations result in lower endurance).
3.3
AC Test Conditions
Timing Measurement
Reference Level
AC Waveform
VLO = 0.2V
VHI = 3.4V
CL = 30pF (for 1.6 MHz SCK)
Input
0.5 Vcc
Output
0.5 Vcc
CL = 10pF (for 10 MHz SCK)
4.
Timing Diagrams
Figure 4-1. Synchronous Data Timing with HOLD high
CS
VIH
tCS
VIL
tCSS
t CSH
VIH
SCK
tSCKH
tDS
SDI
tSCKL
VIL
t DH
VIH
VALID IN
VIL
tOV
VIH
SDO
HI-Z
tOH
tDIS
HI-Z
VIL
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Figure 4-2. Hold Timing
CS
t HD
t HD
SCK
t HS
t HS
HOLD
t HZ
SDO
t LZ
Figure 4-3. Power-up Timing
VCC
VCCmax
Program, Read, Erase and Write Commands Rejected
VCCmin
VVCCI
Device Fully
Accessible
Device in Reset
tPUD
TIME
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5.
Pin Descriptions and Pin-out
Table 5-1.
Mnemonic
Pin Descriptions
Pin Number
Pin Name
Description
CS
1
Chip Select
Making CS low activates the internal circuitry for device operation.
Making CS high deselects the device and switches into standby
mode to reduce power. When the device is not selected (CS high),
data is not accepted via the Serial Data Input pin (SDI) and the
Serial Data Output pin (SDO) remains in a high-impedance state.
SDO
2
Serial Data Out
Sends read data or status on the falling edge of SCK.
WP
3
Write Protect
N/A
GND
4
Ground
SDI
5
Serial Data In
Device data input; accepts commands, addresses, and data on the
rising edge of SCK.
SCK
6
Serial Clock
Provides timing for the SPI interface. SPI commands, addresses,
and data are latched on the rising edge on the Serial Clock signal,
and output data is shifted out on the falling edge of the Serial Clock
signal.
HOLD
7
Hold
When pulled low, serial communication with the master device is
paused, without resetting the serial sequence.
Vcc
8
Power
Power supply pin.
Figure 5-1. PInouts
S
SOIC, UDFN and TSSOP
WLCSP (Bottom View)
Pin 1
CS
SDO
1
8
2
VCC
7
HOLD
SPI
6.
WP
3
6
SCK
GND
4
5
SDI
A
Vcc
SCK
B
GND
SDI
C
CS
SDO
1
2
SPI Modes Description
Multiple Adesto SPI devices can be connected onto a Serial Peripheral Interface (SPI) serial bus controlled by an SPI
master, such as a microcontroller, as shown in Figure 6-1,
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Figure 6-1. Connection Diagram, SPI Master and SPI Slaves
SDO
SPI Interface with
Mode 0 or Mode 3
SDI
SCK
SCK SDO
SPI Master
(i.e. Microcontroller)
SDI
SPI Memory
Device
CS3
CS2
SCK SDO
SDI
SCK SDO
SPI Memory
Device
SDI
SPI Memory
Device
CS1
CS
CS
CS
The Adesto RM25C family supports two SPI modes: Mode 0 (0, 0) and Mode 3 (1, 1). The difference between these two
modes is the clock polarity when the SPI master is in standby mode (CS high). In Mode 0, the Serial Clock (SCK) stays
at 0 during standby. In Mode 3, the SCK stays at 1 during standby. An example sequence for the two SPI modes is
shown in Figure 6-2. For both modes, input data (on SDI) is latched in on the rising edge of Serial Clock (SCK), and
output data (SDO) is available beginning with the falling edge of Serial Clock (SCK).
Figure 6-2. SPI Modes
CS
Mode 0 (0,0) SCK
Mode 3 (1,1) SCK
SDI
SDO
MSB
MSB
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7.
Registers
7.1
Instruction Register
The Adesto RM25C family uses a single 8-bit instruction register. The instructions and their operation codes are listed in
Table 7-1. All instructions, addresses, and data are transferred with the MSB first, and begin transferring with the first
low-to-high SCK transition after the CS pin goes low.
Table 7-1.
Instruction
7.2
Device Operating Instructions
Description
Operation
Code
Address
Cycles
Dummy
Cycles
Data
Cycles
WRSR
Write Status
Register
01H
0
0
1
WR
Write 1 to 64 bytes
02H
2
0
1-64
READ
Read data from
memory array
03H
2
0
1 to ∞
FREAD
Fast Read data
from data memory
0BH
2
1
1 to ∞
WRDI
Write Disable
04H
0
0
0
RDSR
Read Status
Register
05H
0
0
1 to ∞
WREN
Write Enable
06H
0
0
0
PERS
Page Erase
64 bytes
42H
2
0
0
CERS
Chip Erase
60H
0
0
0
C7H
0
0
0
PD
Power Down
B9H
0
0
0
UDPD
Ultra Deep Power
Down
79H
0
0
0
RES
Resume from
Power Down
ABH
0
0
0
Status Register
The Adesto RM25C family uses a single 8-bit Status Register. The Write In Progress (WIP) and Write Enable (WEL)
status of the device can be determined by reading this register.
The Status Register format is shown in Table 7-2 The Status Register bit definitions are shown in Table 7-3.
Table 7-2.
Status Register Format
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SRWD
APDE
LPSE
0
BP1
BP0
WEL
WIP
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Table 7-3.
Bit
Status Register Bit Definitions
Name
Description
R/W
Non-Volatile Bit
R
No
0
WIP
Write In Progress
“0” indicates the device is ready
“1” indicates that the program/erase cycle
is in progress and the device is busy
1
WEL
Write Enable Latch
“0” Indicates that the device is disabled
“1” indicates that the device is enabled
R/W
No
2
BP0
3
BP1
Block Protection Bits. "0" indicates the
specific blocks are not protected.
"1" indicates that the specific blocks are
protected.
R/W
Yes
4
N/A
N/A
No
R/W
Yes
R/W
Yes
R/W
Yes
Reserved. Read as “0”
Low Power Standby Enable.
5
8.
LPSE
"0" indicates that the device will not use
Low Power Standby Mode.
"1" indicates that the device will use Low
Power Standby Mode.
6
APDE
Auto Power Down Enable.
"0" indicates that the device will use
Standby Mode.
"1" indicates that the device will use Power
Down Mode instead of Standby Mode.
7
SRWD
WP pin enable. See Table 8-1.
Write Protection
The Adesto RM25C family has two protection modes: hardware write protection, via the WP pin associated with the
SRWD bit in the Status Register, and software write protection in the form of the SRWD, WEL, BP0, and BP1 bits in the
Status Register.
8.1
Hardware Write Protection
There are three hardware write protection features:
•
All write instructions must have the appropriate number of clock cycles before CS goes high or the write instruction
will be ignored.
•
If the VCC is below the VCC Inhibit Voltage (VVccI, see DC Characteristics), all Read, Write, and Erase sequence
instructions will be ignored.
•
The WP pin provides write protection for the Status Register. When WP is low, the Status Register is write
protected if the SRWD bit in the Status Register is High. When WP is high, the Status Register is writable independent of
the SRWD bit. See Table 8-1.
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Table 8-1.
8.2
Hardware Write Protection on Status Register
SRWD
WP
Status
Register
0
Low
Writable
1
Low
Protected
0
High
Writable
1
High
Writable
Software Write Protection
There are two software write protection features:
•
Before any program, erase, or write status register instruction, the Write Enable Latch (WEL) bit in the Status
Register must be set to a one by execution of the Write Enable (WREN) instruction. If the WEL bit is not enabled, all
program, erase, or write register instructions will be ignored.
•
The Block Protection bits (BP0 and BP1) allow a part or the whole memory area to be write protected.
See Table 8-2.
Table 8-2.
BP1
8.3
Block Write Protect Bits
BP0
Protected
Region
RM25C256C-L
Protected
Address
Protected
Area Size
0
0
None
None
0
0
1
Top ¼
30003FFF
4K
bytes
1
0
Top ½
20003FFF
8K
bytes
1
1
All
03FFF
All
Reducing Energy Consumption
In normal operation, when the device is idle, (CS is high, no Write or Erase operation in progress), the device is in
Standby Mode, waiting for the next command. To reduce device energy consumption, the Power Down or Ultra-Deep
Power Down modes may be used.
8.3.1
Power Down mode
Power Down mode allows the user to reduce the power of the device to its lowest power consumption state. The PD
command is used to instruct the device to enter Power Down mode.
All instructions given during the Power Down mode are ignored except the Resume From Power Down (RES) instruction.
Therefore this mode can be used as an additional software write protection feature.
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8.3.2
Ultra-Deep Power Down mode
The Ultra-Deep Power Down mode allows the device to further reduce its energy consumption compared to the existing
Standby and Power Down modes by shutting down additional internal circuitry. The UDPD command is used to instruct
the device to enter Ultra-Deep Power Down mode.
When the device is in the Ultra-Deep Power Down mode, all commands including the Read Status Register and Resume
From Power Down commands will be ignored. Since all commands will be ignored, the mode can be used as an extra
protection mechanism against inadvertent or unintentional program and erase operations.
Only the Exit Ultra-Deep Power Down signal sequences described in section 8-13 will bring the device out of the UltraDeep Power Down mode.
8.3.3
Auto Power Down Enable.
For frequencies lower than fAPD (see AC Operating Characteristics), the APDE bit in the Status Register may be enabled.
The device will then automatically enter Power Down mode instead of Standby mode when idle. (CS is high, no Write or
Erase operation in progress).
In this mode, the device will behave normally to all commands, and will leave Power Down mode once CS is pulled down.
If Auto Power Down is enabled, and the SCK Clock Frequency is increased to a speed higher than fAPD, the device may
not react as expected to the command. Before changing SCK frequency, the APDE bit in the Status Register must be
disabled.
Note that the PD or UDPD commands may still be used as additional software write protection features when Auto Power
Down is enabled. Note that if the PD command is issued while Auto Power Down is enabled, the device will enter Power
Down mode, and all instructions given will be ignored except the Resume From Power Down (RES) instruction. The
device will not wake up immediately after CS is pulled down.
8.3.4
Low Power Standby Enable.
For frequencies lower than fAPD (see AC Operating Characteristics), the LPSE bit in the Status Register may be enabled.
The device will then automatically enter Low Power Standby mode when idle. (CS is high, no Write or Erase operation in
progress).
In this mode, the device will behave normally to all commands, and will leave Low Power Standby mode once CS is
pulled down.
If Low Power Standby Mode is enabled, and the SCK Clock Frequency is increased to a speed higher than fAPD, the
device may not react as expected to the command. Before changing SCK frequency, the LPSE bit in the Status Register
must be disabled.
Note that the PD or UDPD commands may still be used as additional software write protection features when Low Power
Standby Mode is enabled. Note that if the PD command is issued while Low Power Standby Mode is enabled, the device
will enter Power Down mode, and all instructions given will be ignored except the Resume From Power Down (RES)
instruction. The device will not wake up immediately after CS is pulled down.
9.
Command Descriptions
9.1
WREN (Write Enable):
The device powers up with the Write Enable Latch set to zero. This means that no write or erase instructions can be
executed until the Write Enable Latch is set using the Write Enable (WREN) instruction. The Write Enable Latch is also
set to zero automatically after any non-read instruction. Therefore, all page programming instructions and erase
instructions must be preceded by a Write Enable (WREN) instruction. The sequence for the Write Enable instruction is
shown in Figure 9-1.
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Figure 9-1. WREN Sequence (06h)
CS
0
1
2
3
4
5
6
7
0
0
0
0
0
1
1
0
SCK
SDI
HI-Z
SDO
Table 9-1 is a list of actions that will automatically set the Write Enable Latch to zero when successfully executed. If an
instruction is not successfully executed, for example if the CS pin is brought high before an integer multiple of 8 bits is
clocked, the Write Enable Latch will not be reset.
Table 9-1.
Write Enable Latch to Zero
Instruction/Operation
Power-Up
WRDI (Write Disable)
WR (Write)
PERS (Page Erase)
CERS (Chip Erase)
PD (Power Down)
9.2
WRDI (Write Disable):
To protect the device against inadvertent writes, the Write Disable instruction disables all write modes. Since the Write
Enable Latch is automatically reset after each successful write instruction, it is not necessary to issue a WRDI instruction
following a write instruction. The WRDI instruction is independent of the status of the WP pin. The WRDI sequence is
shown in Figure 9-2.
Figure 9-2. WRDI Sequence (04h)
CS
0
1
2
3
4
5
6
7
0
0
0
0
0
1
0
0
SCK
SDI
SDO
9.3
HI-Z
RDSR (Read Status Register):
The Read Status Register instruction provides access to the Status Register and indication of write protection status of
the memory.
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Caution:
The Write In Progress (WIP) and Write Enable Latch (WEL) indicate the status of the device. The RDSR sequence is
shown in Figure 9-3.
Figure 9-3. RDSR Sequence (05h)
CS
0
1
2
3
4
5
6
7
0
0
0
0
0
1
0
1
8
9
10
11
12
13
14
15
5
4
3
2
1
0
SCK
SDI
HI-Z
SDO
7
6
WEL WIP
9.4
WRSR (Write Status Register):
The Write Status Register (WRSR) instruction allows the user to select one of three levels of protection. The memory
array can be block protected (see Table 8-2) or have no protection at all. The SRWD bit (in conjunction with the WP pin)
sets the write status of the Status Register (see Table 8-1).
Only the BP0, BP1, APDE, LPSE and SRWD bits are writable and are nonvolatile cells. When the WP pin is low, and the
SRWD bit in the Status Register is a one, a zero cannot be written to SRWD to allow the part to be writable. To set the
SRWD bit to zero, the WP pin must be high. The WRSR sequence is shown in Figure 9-4.
Figure 9-4. WRSR Sequence (01h)
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
3
2
1
0
SCK
INSTRUCTION
SDI
SDO
9.5
0
0
0
0
STATUS
0
0
0
1
7
6
5
4
HI-Z
READ (Read Data):
Reading the Adesto RM25C family via the Serial Data Output (SDO) pin requires the following sequence: First the CS
line is pulled low to select the device; then the READ op-code is transmitted via the SDI line, followed by the address to
be read (A15-A0). Although not all 16 address bits are used, a full 2 bytes of address must be transmitted to the device.
For the 256 Kb device, only address A0 to A14 are used; the rest are don't cares and must be set to “0”.
Once the read instruction and address have been sent, any further data on the SDI line will be ignored. The data (D7-D0)
at the specified address is then shifted out onto the SDO line. If only one byte is to be read, the CS line should be driven
high after the byte of data comes out. This completes the reading of one byte of data.
The READ sequence can be automatically continued by keeping the CS low. At the end of the first data byte the byte
address is internally incremented and the next higher address data byte will be shifted out. When the highest address is
reached, the address counter will roll over to the lowest address (00000), thus allowing the entire memory to be read in
one continuous read cycle. The READ sequence is shown in Figure 9-5.
RM25C256C
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Figure 9-5. Single Byte READ Sequence (03h)
CS
0
1
2
3
4
5
0
0
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
SDI
0
0
0
0
2 BYTE ADDRESS
1
1
15 14 13
3
2
1
0
DATA OUT
HI-Z
9.6
7
6
5
4
3
2
1
0
FREAD (Fast Read Data):
The Adesto RM25C family also includes the Fast Read Data command, which facilitates reading memory data at higher
clock rates, up to 10 MHz. After the CS line is pulled low to select the device, the FREAD op-code is transmitted via the
SDI line. This is followed by the 2-byte address to be read (A15-A0) and then a 1-byte dummy. For the 256-Kbit device,
only address A0 to A14 are used; the rest are don't cares and must be set to "0".
The next 8 bits transmitted on the SDI are dummy bits. The data (D7-D0) at the specified address is then shifted out onto
the SDO line. If only one byte is to be read, the CS line should be driven high after the data comes out. This completes
the reading of one byte of data.
The FREAD sequence can be automatically continued by keeping the CS low. At the end of the first data byte, the byte
address is internally incremented and the next higher address data byte is then shifted out. When the highest address is
reached, the address counter rolls over to the lowest address (00000), allowing the entire memory to be read in one
continuous read cycle. The FREAD sequence is shown in Figure 9-6.
Figure 9-6. Two Byte FREAD Sequence (0Bh)
CS
0
1
2
3
4
5
6
7
8
9
10
20
21 22
23
SCK
INSTRUCTION
SDI
0
0
0
0
2 BYTE ADDRESS
1
0
1
1
30
31 32
1
0
15 14
13
3
2
1
36
37 38
0
HI-Z
SDO
CS
24
25 26
7
6
27
28 29
33
34 35
39
40 41
42
43 44
45
46 47
2
1
SCK
DUMMY BYTE
SDI
5
4
3
2
DATA BYTE 1 OUT
SDO
HI-Z
7
6
5
4
3
2
DATA BYTE 2 OUT
1
0
7
6
5
4
3
0
RM25C256C
DS-RM25C256C–078C–11/2017
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9.7
WRITE (WR):
Product
Density
Page Size (bytes)
RM25C256C-L
256 Kbit
64
The Write (WR) instruction allows bytes to be written to the memory. But first, the device must be write-enabled via the
WREN instruction. The CS pin must be brought high after completion of the WREN instruction; then the CS pin can be
brought back low to start the WR instruction. The CS pin going high at the end of the WR input sequence initiates the
internal write cycle. During the internal write cycle, all commands except the RDSR instruction are ignored.
A WR instruction requires the following sequence: After the CS line is pulled low to select the device, the WR op-code is
transmitted via the SDI line, followed by the byte address (A15-A0) and the data (D7-D0) to be written. For the 256Kb
device, only address A0 to A14 are used; the rest are don't cares and must be set to “0”. The internal write cycle
sequence will start after the CS pin is brought high. The low-to-high transition of the CS pin must occur during the SCK
low-time immediately after clocking in the D0 (LSB) data bit.
The Write In Progress status of the device can be determined by initiating a Read Status Register (RDSR) instruction
and monitoring the WIP bit. If the WIP bit (Bit 0) is a “1”, the write cycle is still in progress. If the WIP bit is “0”, the write
cycle has ended. Only the RDSR instruction is enabled during the write cycle. The sequence of a one-byte WR is shown
in Figure 9-7.
Figure 9-7. One Byte Write Sequence (0Bh)
CS
0
1
2
0
0
0
3
4
5
6
7
8
9
10 11 20 21 22 23 24 25 26 27 28 29 30 31
SCK
INSTRUCTION
SDI
SDO
0
0
0
2 BYTE ADDRESS
1
0
15 14 13
3
2
1
DATA IN
0
7
6
5
4
3
2
1
0
HI-Z
The Adesto RM25C family is capable of a 64-byte write operation.
For the RM25C256C-L: After each byte of data is received, the six low-order address bits (A5-A0) are internally
incremented by one; the high-order bits of the address will remain constant. All transmitted data that goes beyond the
end of the current page are written from the start address of the same page (from the address whose 6 least significant
bits [A5-A0] are all zero). If more than 64 bytes are sent to the device, previously latched data are discarded and the last
64 data bytes are ensured to be written correctly within the same page. If less than 64 data bytes are sent to the device,
they are correctly written at the requested addresses without having any effects on the other bytes of the same page.
The Adesto RM25C256C-L is automatically returned to the write disable state at the completion of a program cycle. The
sequence for a 64 byte WR is shown in Figure 9-8. Note that the Multi-Byte Write operation is internally executed by
sequentially writing the words in the Page Buffer.
NOTE: If the device is not write enabled (WREN) previous to the Write instruction, the device will ignore the write instruction and
return to the standby state when CS is brought high. A new CS falling edge is required to re initiate the serial communication.
RM25C256C
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Figure 9-8. WRITE Sequence (02h)
CS
0
1
0
0
2
3
4
5
6
7
8
9
10
11
20
21
22
23
24
25
0
7
6
26
27
28
29
30
31
2
1
0
SCK
INSTRUCTION
SDI
0
0
0
2 BYTE ADDRESS
0
1
0
15 14
13
3
2
DATA BYTE 1
1
5
4
3
HI-Z
SDO
CS
32
33
7
6
34
35
36
37
38
39
40
41
2
1
0
7
6
42
43
44
45
46
47
2
1
0
SCK
DATA BYTE 2
SDI
5
3
DATA BYTE 3
5
4
3
DATA BYTE N (N= 32,64)
7
6
5
4
3
2
1
0
HI-Z
SDO
9.8
4
PER (Page Erase 64 bytes):
Page Erase sets all bits inside the addressed 64 byte page to a 1. A Write Enable (WREN) instruction is required prior to
a Page Erase. After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.
The Page Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code, then 2 address
bytes. Any address inside the page to be erased is valid. This means the bottom six bits (A5-A0) of the address are
ignored. Once the address is shifted in, the CS pin is brought high, which initiates the self-timed Page Erase function.
The WIP bit in the Status Register can be read, using the RDSR instruction, to determine when the Page Erase cycle is
complete.
The sequence for the PER is shown in Figure 9-9.
Figure 9-9. PERS Sequence (42h)
CS
0
1
2
3
4
5
6
7
8
9
10
11
20
21
22
23
1
0
SCK
INSTRUCTION
SDI
SDO
9.9
0
1
0
0
2 BYTE ADDRESS
0
0
1
0
15
14
13
3
2
HI-Z
CERS (Chip Erase):
Chip Erase sets all bits inside the device to a 1. A Write Enable (WREN) instruction is required prior to a Chip Erase.
After the WREN instruction is shifted in, the CS pin must be brought high to set the Write Enable Latch.
The Chip Erase sequence is initiated by bringing the CS pin low; this is followed by the instruction code. There are two
different instruction codes for CER, 60h and C7h. Either instruction code will initiate the Chip Erase sequence. No
RM25C256C
DS-RM25C256C–078C–11/2017
19
address bytes are needed. Once the instruction code is shifted in, the CS pin is brought high, which initiates the selftimed Chip Erase function. The WIP bit in the Status Register can be read, using the RDSR instruction, to determine
when the Chip Erase cycle is complete.
The sequence for the 60h CER instruction is shown in Figure 9-10. The sequence for the C7h CER instruction is shown
in Figure 9-11.
Figure 9-10. CERS Sequence (60h)
CS
0
1
2
3
4
5
6
7
0
1
1
0
0
0
0
0
SCK
SDI
HI-Z
SDO
Figure 9-11. CERS Sequence (C7h)
CS
0
1
2
3
4
5
6
7
1
1
0
0
0
1
1
1
SCK
SDI
HI-Z
SDO
9.10
PD (Power Down):
Power Down mode allows the user to reduce the power of the device to its lowest power consumption state.
All instructions given during the Power Down mode are ignored except the Resume from Power down (RES) instruction.
Therefore this mode can be used as an additional software write protection feature.
The Power Down sequence is initiated by bringing the CS pin low; this is followed by the instruction code. Once the
instruction code is shifted in the CS pin is brought high, which initiates the PD mode. The sequence for PD is shown in
Figure 9-12.
Figure 9-12. PD Sequence
CS
0
1
2
3
4
5
6
7
1
0
1
1
1
0
0
1
SCK
SDI
SDO
HI-Z
RM25C256C
DS-RM25C256C–078C–11/2017
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9.11
RES (Resume from Power Down):
The Resume from Power Down mode is the only command that will wake the device up from the Power Down mode. All
other commands are ignored.
In the simple instruction command, after the CS pin is brought low, the RES instruction is shifted in. At the end of the
instruction, the CS pin is brought back high.
The rising edge of the SCK clock number 7 (8th rising edge) initiates the internal RES instruction. The device becomes
available for Read and Write instructions 75μS after the 8th rising edge of the SCK (tPUD, see AC Characteristics). The
sequence for simple RES instruction is shown in Figure 9-13.
Figure 9-13. Simple RES Sequence (ABh)
CS
0
1
2
3
4
5
1
0
6
7
SCK
INSTRUCTION
SDI
1
0
SDO
1
0
1
1
HI-Z
tRPD
9.12
UDPD (Ultra-Deep Power Down):
The Ultra-Deep Power Down mode allows the device to further reduce its energy consumption compared to the existing
Standby and Power Down modes by shutting down additional internal circuitry. When the device is in the Ultra-Deep
Power Down mode, all commands including the Read Status Register and Resume from Deep Power Down commands
will be ignored. Since all commands will be ignored, the mode can be used as an extra protection mechanism against
inadvertent or unintentional program and erase operations. Entering the Ultra-Deep Power Down mode is accomplished
by simply asserting the CS pin, clocking in the opcode 79h, and then deasserting the CS pin. Any additional data clocked
into the device after the opcode will be ignored. When the CS pin is deasserted, the device will enter the Ultra-Deep
Power Down mode within the maximum time of tEUDPD.
The complete opcode must be clocked in before the CS pin is deasserted; otherwise, the device will abort the operation
and return to the standby mode once the CS pin is deasserted. In addition, the device will default to the standby mode
after a power cycle. The Ultra-Deep Power Down command will be ignored if an internally self-timed operation such as a
program or erase cycle is in progress. The sequence for UDPD is shown in Figure 9-14.
RM25C256C
DS-RM25C256C–078C–11/2017
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Figure 9-14. Ultra-Deep Power Down (79h)
CS
tEUDPD
0
1
2
3
4
5
6
7
SCK
Opcode
SI
0
1
1
1
1
0
0
1
MSB
High-impedance
SO
Active Current
ICC
Standby Mode Current
Ultra-Deep Power-Down Mode Current
9.13
Exit Ultra-Deep Power Down
To exit from the Ultra-Deep Power Down mode, any one of three operations can be performed:
9.13.1 Chip Select Toggle
The CS pin must simply be pulsed by asserting the CS pin, waiting the minimum necessary tCSLU time, and then
deasserting the CS pin again. To facilitate simple software development, a dummy byte opcode can also be entered
while the CS pin is being pulsed; the dummy byte opcode is simply ignored by the device in this case. After the CS pin
has been deasserted, the device will exit from the Ultra-Deep Power Down mode and return to the standby mode within
a maximum time of tXUDPD If the CS pin is reasserted before the tXUDPD time has elapsed in an attempt to start a new
operation, then that operation will be ignored and nothing will be performed.
Figure 9-15. Exit Ultra-Deep Power Down (Chip Select Toggle)
CS
tCSLU
tXUDPD
SO
High-impedance
Active Current
ICC
Standby Mode Current
Ultra-Deep Power-Down Mode Current
9.13.2 Chip Select Low
By asserting the CS pin, waiting the minimum necessary tXUDPD time, and then clocking in the first bit of the next Opcode
command cycle. If the first bit of the next command is clocked in before the tXUDPD time has elapsed, the device will exit
Ultra Deep Power Down, however the intended operation will be ignored.
RM25C256C
DS-RM25C256C–078C–11/2017
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Figure 9-16. Exit Ultra-Deep Power Down (Chip Select Low)
CS
tXUDPD
SO
High-impedance
Active Current
ICC
Ultra-Deep Power-Down Mode Current
9.13.3 Power Cycling
The device can also exit the Ultra Deep Power Mode by power cycling the device. The system must wait for the device to
return to the standby mode before normal command operations can be resumed. Upon recovery from Ultra Deep Power
Down all internal registers will be at there Power-On default state.
10.
Typical Characteristics
Figure 10-1. Icc4 , Auto Powerdown
Average Icc Standby (Icc4, Auto Pow erdown, uA) vs Temperature (C), by Vcc
3.60 3.30 2.70
1.65
12
Voltage
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
Current
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
0
23
55
85
Temperature
RM25C256C
DS-RM25C256C–078C–11/2017
23
Figure 10-2. Icc4, Mode 0
Average Icc Standby (Icc4, Mode 0, uA) vs Temperature (C), by Vcc
Voltage
3.60
3.30
2.70
110
105
1.65
100
95
90
85
80
75
70
65
Current
60
55
50
45
40
35
30
25
20
15
10
5
0
-40
0
23
55
85
Temperature
Figure 10-3. Icc4, Mode 1
Average Icc Standby (Icc4, Mode 1, uA) vs Temperature (C), by Vcc
110
105
100
95
90
Voltage
85
3.60
3.30
80
2.70
75
70
1.65
65
60
Current 55
50
45
40
35
30
25
20
15
10
5
0
-40
0
23
55
85
Temperature
RM25C256C
DS-RM25C256C–078C–11/2017
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Figure 10-4. Icc5
Average PD (Icc5) Current (uA) vs Temperature (C), Lines by Vcc
3.60 3.30 2.70
12
1.65
Voltage
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
Current
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
0
23
55
85
Temperature
Figure 10-5. Icc6
Average UDPD (Icc6) Current (uA) vs Temperature (C), Lines by Vcc
3.60 3.30 2.70 1.65
12
Voltage
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
Current
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
-40
0
23
55
85
Temperature
RM25C256C
DS-RM25C256C–078C–11/2017
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11.
Ordering Information
11.1
Ordering Detail
RM25C256C-LSNI-T
Device Type
Shipping Carrier Option
RM25C = SPI serial access EEPROM
B = Tube
T = Tape & Reel
Density
Grade & Temperature
256 = 256Kbit
I = Green, NiPd Au lead finish,
Industrial temperature (-40-85°C)
Package Option
SN = 8 lead 0.150” SOIC, Narrow
TA = 8 lead TSSOP
MA = 8 pad, 2 x 3 x 0.6 mm UDFN
CS = Wafer Level Chip Scale
Device/Die Revision
C
Operating Voltage
L = 1.65V to 3.6V
11.2
Ordering Codes
Ordering Code
Package
RM25C256C-LSNI-B
RM25C256C-LSNI-T
RM25C256C-LTAI-B
RM25C256C-LTAI-T
1.
Density
Operating
Voltage
fSCK
Device
Grade
SN
TA
RM25C256C-LMAI-T
MA
RM25C256C-LCSI-T (1)
CS6
256 Kbit
1.65V to 3.6V
10 MHz
Commercial
(-40C to 85C)
Ship
Carrier
Qty.
Carrier
Tube
100
Reel
4000
Tube
100
Reel
6000
Reel
5000
Contact Factory
Contact Adesto for availability.
Package Type
SN
8-lead 0.150" wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
TA
8-lead 3 x 4.4 mm, Thin Shrink Small Outline Package
MA
8-pad, 2 x 3 x 0.6mm, Thermally Enhanced Plastic Ultra Thin Dual Flat No Lead Package (UDFN)
CS6
6-Ball Wafer Level Chip Scale Package
RM25C256C
DS-RM25C256C–078C–11/2017
26
12.
Package Information
12.1
SN (JEDEC SOIC)
C
1
E
E1
L
N
Ø
TOP VIEW
END VIEW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
A1
D
SIDE VIEW
SYMBOL
MIN
A
1.35
–
1.75
A1
0.10
–
0.25
b
0.31
–
0.51
C
0.17
–
0.25
D
4.80
–
5.05
E1
3.81
–
3.99
E
5.79
–
6.20
e
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
MAX
NOM
NOTE
1.27 BSC
L
0.40
–
1.27
Ø
0°
–
8°
8/20/14
TITLE
Package Drawing Contact:
contact@adestotech.com
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC)
GPC
SWB
DRAWING NO.
8S1
REV.
G
RM25C256C
DS-RM25C256C–078C–11/2017
27
MA – 2x3 UDFN
8
7
6
5
5
8
E2
D2
E
12.2
Chamfer or half-circle
notch for Pin 1 indicator.
PIN 1 ID
L3
L
L1
1
2
3
4
1
4
D
COMMON DIMENSIONS
(Unit of Measure = mm)
eee
SYMBOL
MIN
A
0.45
A1
0.00
A3
b
E2
0.05
0.20
0.30
2.00 BSC
1.50
E
Notes: 1. All dimensions are in mm. Angles in degrees.
2. Bilateral coplanarity zone applies to the exposed heat
sink slug as well as the terminals.
0.60
0.150 REF
D
D2
1.60
1.70
3.00 BSC
0.10
e
0.20
0.30
0.50 BSC
L
0.40
0.45
L1
0.00
0.10
L3
0.30
eee
MAX
NOM
–
0.50
0.50
–
0.08
8/26/14
®
Package Drawing Contact:
contact@adestotech.com
GPC
TITLE
8MA3, 8-pad, 2 x 3 x 0.6 mm Body, 0.5 mm Pitch,
1.6 x 0.2 mm Exposed Pad, Saw Singulated
YCQ
Thermally Enhanced Plastic Ultra Thin Dual
Flat No Lead Package (UDFN/USON)
DRAWING NO.
8MA3
RM25C256C
DS-RM25C256C–078C–11/2017
REV.
GT
28
12.3
TA-TSSOP
C
1
Pin 1 indicator
this corner
E1
E
L1
H
N
L
Top View
End View
A
b
A1
e
A2
MIN
NOM
MAX
A
-
-
1.20
A1
0.05
-
0.15
A2
0.80
1.00
1.05
D
2.90
3.00
3.10
2, 5
4.40
4.50
3, 5
–
0.30
4
SYMBOL
D
Side View
Notes:
COMMON DIMENSIONS
(Unit of Measure = mm)
1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
E
6.40 BSC
E1
4.30
b
0.19
e
L
0.65 BSC
0.45
L1
C
NOTE
0.60
0.75
1.00 REF
0.09
-
0.20
12/8/11
®
Package Drawing Contact:
contact@adestotech.com
TITLE
TA, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP)
GPC
TNR
DRAWING NO.
8X
REV.
E
RM25C256C
DS-RM25C256C–078C–11/2017
29
12.4
CS6- 6-Ball WLCSP
0.015 C
4X
0.075
C
A
C
D
Pin 1
A
B
A1
C
0.015
0.05
C
C A B
C
B
Øb
Pin 1
A
1
1
E
e
2
2
A2
d2
d
A
TOP VIEW
SIDE VIEW
BALL SIDE
* Dimensions are NOT to scale.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
B
C
1
VCC
GND
CS
2
SCK
SDI
SDO
PCB Land Pad Diameter Recommendation:
Description
Value
Non-soldermask defined (NSMD)
225um
Soldermask defined (SMD)
250um
TYP
A
0.35
A1
0.08
A2
0.27
E
1.28
e
0.4
Pin Assignment Matrix
A
MIN
d
0.8
d2
0.4
D
1.47
MAX
NOTE
2/29/16
®
Package Drawing Contact:
contact@adestotech.com
TITLE
CS-6, 6-ball (3x3 Array) Wafer Level Chip Scale
Package, WLCSP
GPC
DRAWING NO.
REV.
GCL
CS6-SP
0A
RM25C256C
DS-RM25C256C–078C–11/2017
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13.
Revision History
Doc. Rev.
Date
Comments
RM25C256C-L-078A
3/2016
Initial document release. Document status changed to Preliminary.
RM25C256C-L-078B
11/2016
Updated Endurance and Data Retention specifications. Updated TPW and TBW
specifications.
RM25C256C-L-078C
11/2017
Added patent information.
RM25C256C
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Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2017 Adesto Technologies. All rights reserved. / Rev.: DS-RM25C256C–078C–11/2017
Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective
owners. Adesto products in this datasheet are covered by certain Adesto patents registered in the United States and potentially other countries. Please refer to
http://www.adestotech.com/patents for details.
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.
For Release Only Under Non-Disclosure Agreement (NDA)
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