Access line, 16 MHz STM8S 8-bit MCU, up to 8

STM8S103K3
STM8S103F3 STM8S103F2
Access line, 16 MHz STM8S 8-bit MCU, up to 8 Kbytes Flash,
data EEPROM,10-bit ADC, 3 timers, UART, SPI, I²C
Preliminary data
Features
Core
■
16 MHz advanced STM8 core with Harvard
architecture and 3-stage pipeline
■
Extended instruction set
LQFP32 7x7
Memories
■
■
■
TSSOP20
WFQFN20 3 x 3
Program memory: 8 Kbytes Flash; data
retention 20 years at 55 °C after 10 kcycles
■
Data memory: 640 bytes true data EEPROM;
endurance 300 kcycles
16-bit general purpose timer, with 3 CAPCOM
channels (IC, OC or PWM)
■
8-bit basic timer with 8-bit prescaler
RAM: 1 Kbytes
■
Auto wake-up timer
■
2 watchdog timers: Window watchdog and
independent watchdog
Clock, reset and supply management
■
2.95 to 5.5 V operating voltage
■
Flexible clock control, 4 master clock sources:
– Low power crystal resonator oscillator
– External clock input
– Internal, user-trimmable 16 MHz RC
– Internal low power 128 kHz RC
■
Clock security system with clock monitor
■
Power management:
– Low power modes (wait, active-halt, halt)
– Switch-off peripheral clocks individually
■
Permanently active, low consumption poweron and power-down reset
Interrupt management
■
Nested interrupt controller with 32 interrupts
■
Up to 27 external interrupts on 6 vectors
Timers
■
VFQFN32 5x5
Advanced control timer: 16-bit, 4 CAPCOM
channels, 3 complementary outputs, dead-time
insertion and flexible synchronization
April 2009
Communications interfaces
■
UART with clock output for synchronous
operation, Smartcard, IrDA, LIN master mode
■
SPI interface up to 8 Mbit/s
■
I2C interface up to 400 Kbit/s
Analog to digital converter (ADC)
■
10-bit, ±1 LSB ADC with up to 5 multiplexed
channels, scan mode and analog watchdog
I/Os
■
Up to 28 I/Os on a 32-pin package including 21
high sink outputs
■
Highly robust I/O design, immune against
current injection
■
Development support
– Embedded single wire interface module
(SWIM) for fast on-chip programming and
non intrusive debugging
Doc ID 15441 Rev 2
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to
change without notice.
1/95
www.st.com
1
Contents
STM8S103x
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4
Product overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5
4.1
Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.2
Single wire interface module (SWIM) and debug module (DM) . . . . . . . . 13
4.3
Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4
Flash program and data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . 14
4.5
Clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.6
Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.7
Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.8
Auto wakeup counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.9
Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.10
TIM1 - 16-bit advanced control timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.11
TIM2 - 16-bit general purpose timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.12
TIM4 - 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13
Analog-to-digital converter (ADC1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14.1
UART1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.2
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.14.3
I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.1
Alternate function remapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6
Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8
Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
2/95
Doc ID 15441 Rev 2
STM8S103x
9
Contents
8.1
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
8.2
Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1
10
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
9.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
9.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
9.3.1
VCAP external capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
9.3.2
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
9.3.3
External clock sources and timing characteristics . . . . . . . . . . . . . . . . . 60
9.3.4
Internal clock sources and timing characteristics . . . . . . . . . . . . . . . . . 62
9.3.5
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
9.3.6
I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9.3.7
Reset pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
9.3.8
SPI serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
9.3.9
I2C interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
9.3.10
10-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
9.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
10.1
10.2
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.1.1
LQFP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
10.1.2
QFN package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
10.1.3
TSSOP package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
10.1.4
WFQFPN20 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . 87
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.2.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
10.2.2
Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . . . 90
11
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
12
STM8 development tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Doc ID 15441 Rev 2
3/95
Contents
STM8S103x
12.1
Emulation and in-circuit debugging tools . . . . . . . . . . . . . . . . . . . . . . . . . 92
12.2
Software tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.3
13
4/95
12.2.1
STM8 toolset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
12.2.2
C and assembly toolchains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Programming tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 15441 Rev 2
STM8S103x
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
Table 47.
Table 48.
STM8S103x Access line features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers . . . . . . . . . . . . . . . 15
TIM timer features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Legend/abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VQFN32/LQFP32 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
STM8S103F pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices . . . . . . . . . . . . . . . . . . 29
Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
STM8S103K alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM8S103F alternate function remapping bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
CPU/SWIM/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Total current consumption with code execution in run mode at VDD = 5 V. . . . . . . . . . . . . 51
Total current consumption with code execution in run mode at VDD = 3.3 V . . . . . . . . . . . 52
Total current consumption in wait mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Total current consumption in wait mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Total current consumption in active halt mode at VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in active halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . 54
Total current consumption in halt mode at VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption in halt mode at VDD = 3.3 V . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Wakeup times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Total current consumption and timing in forced reset state . . . . . . . . . . . . . . . . . . . . . . . . 56
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
HSE user external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Output driving current (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
ADC accuracy with RAIN < 10 kΩ , VDD = 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Doc ID 15441 Rev 2
5/95
List of tables
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
6/95
STM8S103x
EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
32-pin low profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
32-lead very thin fine pitch quad flat no-lead package mechanical data . . . . . . . . . . . . . . 85
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data . . . . . . . . . . . . . . . . . . . . 86
20-lead, very, very thin, fine pitch quad flat no-lead package (3 x 3)
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Doc ID 15441 Rev 2
STM8S103x
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Flash memory organisation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
STM8S103K VQFN32/LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
STM8S103F TSSOP 20-pin pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8S103F WFQFPN package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
fCPUmax versus VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
External capacitor CEXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 57
Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . 57
Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . 58
Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . 58
Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
HSE external clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical HSI frequency variation at VDD = 5 V vs 5 temperatures . . . . . . . . . . . . . . . . . . . . 62
Typical HSI frequency variation vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical LSI frequency variation vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . 63
Typical VIL and VIH vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical pull-up resistance vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typical pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Typ. VOL @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Typ. VOL @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typ. VOL @ VDD = 3.3 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typ. VOL @ VDD = 5 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Typ. VOL @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VOL @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VDD - VOH @ VDD = 3.3 V (standard ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typ. VDD - VOH @ VDD = 5 V (standard ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typ. VDD - VOH @ VDD = 3.3 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typ. VDD - VOH @ VDD = 5 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical NRST VIL and VIH vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Typical NRST pull-up resistance vs VDD @ 4 temperatures. . . . . . . . . . . . . . . . . . . . . . . . 71
Typical NRST pull-up current vs VDD @ 4 temperatures . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Recommended reset pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SPI timing diagram - slave mode and CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Typical application with ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
32-pin low profile quad flat package (7 x 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
32-lead very thin fine pitch quad flat no-lead package (5 x 5) . . . . . . . . . . . . . . . . . . . . . . 85
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
20-lead, very, very thin, fine pitch quad flat no-lead package outline (3 x 3) . . . . . . . . . . . 87
Recommended footprint for on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Doc ID 15441 Rev 2
7/95
List of figures
Figure 49.
8/95
STM8S103x
Recommended footprint without on-board emulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Doc ID 15441 Rev 2
STM8S103x
1
Introduction
Introduction
This datasheet contains the description of the STM8S103x Access line features, pinout,
electrical characteristics, mechanical data and ordering information.
●
For complete information on the STM8S microcontroller memory, registers and
peripherals, please refer to the STM8S microcontroller family reference manual
(RM0016).
●
For information on programming, erasing and protection of the internal Flash memory
please refer to the STM8S Flash programming manual (PM0051).
●
For information on the debug and SWIM (single wire interface module) refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
●
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
Doc ID 15441 Rev 2
9/95
Description
2
STM8S103x
Description
The STM8S103x Access line 8-bit microcontrollers offer 8 Kbytes Flash program memory,
plus integrated true data EEPROM. They are referred to as low-density devices in the
STM8S microcontroller family reference manual (RM0016). They provide the following
benefits:
●
Reduced system cost
●
–
High system integration level with internal clock oscillators, watchdog and brownout reset
Performance and robustness
–
16 MHz CPU clock frequency
–
Robust I/O, independent watchdogs with separate clock source
–
Clock security system
●
Full documentation and a wide choice of development tools
●
Advanced core and peripherals made in a state-of-the art technology
STM8S103K3 32
STM8S103F3 20
STM8S103F2 20
28
16
16
27
16
16
7
7
7
3
0
0
4
5
5
21
12
12
8K
8K
4K
640(1) 1K
640(1) 1K
640(1) 1K
1. No read-while-write (RWW) capability
10/95
RAM (bytes)
Data EEPROM (bytes)
Low density
Flash program memory
(bytes)
High sink I/Os
A/D converter channels
Timer complemetarty outputs
Timer CAPCOM channels
Ext. interrupt pins
STM8S103x Access line features
No. of maximum GPIO
(I/O)
Device
Integrated true data EEPROM for up to 300 k write/erase cycles
Pin count
Table 1.
–
Doc ID 15441 Rev 2
Peripheral set
Multipurpose timer (TIM1),
SPI, I2C, UART
window WDG,
independent WDG,
ADC
PWM timer (TIM2)
8-bit timer (TIM4)
STM8S103x
Block diagram
Figure 1.
Block diagram
Reset block
XTAL 1-16 MHz
Clock controller
Reset
Reset
RC int. 16 MHz
Detector
POR
BOR
RC int. 128 kHz
Clock to peripherals and core
Window WDG
STM8 core
Independent WDG
Single wire
debug interf.
8 Kbytes
Debug/SWIM
program
Flash
640 bytes
data EEPROM
400 Kbit/s
8 Mbit/s
LIN master
SPI emul.
I2C
SPI
Address and data bus
3
Block diagram
1 Kbytes
RAM
16-bit advanced control
timer (TIM1)
UART1
16-bit general purpose
Timer (TIM2)
Up to
4 CAPCOM
channels
+ 3 complementary
outputs
Up to
3 CAPCOM
channels
8-bit basic timer
Up to 5
channels
1/2/4 kHz
beep
ADC1
(TIM4)
Beeper
AWU timer
Doc ID 15441 Rev 2
11/95
Product overview
4
STM8S103x
Product overview
The following section intends to give an overview of the basic features of the STM8S103x
Access line functional modules and peripherals.
For more detailed information please refer to the corresponding family reference manual
(RM0016).
4.1
Central processing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing and 80 instructions.
Architecture and registers
●
Harvard architecture
●
3-stage pipeline
●
32-bit wide program memory bus - single cycle fetching for most instructions
●
X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
●
8-bit accumulator
●
24-bit program counter - 16-Mbyte linear memory space
●
16-bit stack pointer - access to a 64 K-level stack
●
8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
●
20 addressing modes
●
Indexed indirect addressing mode for look-up tables located anywhere in the address
space
●
Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
12/95
●
80 instructions with 2-byte average instruction size
●
Standard data movement and logic/arithmetic functions
●
8-bit by 8-bit multiplication
●
16-bit by 8-bit and 16-bit by 16-bit division
●
Bit manipulation
●
Data transfer between stack and accumulator (push/pop) with direct stack access
●
Data transfer using the X and Y registers or direct memory-to-memory transfers
Doc ID 15441 Rev 2
STM8S103x
4.2
Product overview
Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time incircuit debugging and fast memory programming.
SWIM
Single wire interface module for direct access to the debug module and memory
programming. The interface can be activated in all device operation modes. The maximum
data transmission speed is 145 bytes/ms.
Debug module
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, also CPU operation can be monitored in realtime by means of shadow registers.
4.3
●
R/W to RAM and peripheral registers in real-time
●
R/W access to all resources by stalling the CPU
●
Breakpoints on all program-memory instructions (software breakpoints)
●
2 advanced breakpoints, 23 predefined configurations
Interrupt controller
●
Nested interrupts with 3 software priority levels
●
32 interrupt vectors with hardware priority
●
Up to 27 external interrupts on 6 vectors including TLI
●
Trap and reset interrupts
Doc ID 15441 Rev 2
13/95
Product overview
4.4
STM8S103x
Flash program and data EEPROM memory
●
●
●
8 Kbytes of Flash program single voltage Flash memory
640 bytes true data EEPROM
User option byte area
Write protection (WP)
Write protection of Flash program memory and data EEPROM is provided to avoid
unintentional overwriting of memory that could result from a user software malfunction.
There are two levels of write protection. The first level is known as MASS (Memory Access
Security System). MASS is always enabled and protects the main Flash program memory,
data EEPROM and option bytes.
To perform In-Application Programming (IAP), this write protection can be removed by
writing a MASS key sequence in a control register. This allows the application to write to
data EEPROM, modify the contents of main program memory or the device option bytes.
A second level of write protection, can be enabled to further protect a specific area of
memory known as UBC (user boot code). Refer to Figure 2.
The size of the UBC is programmable through the UBC option byte (Table 10), in increments
of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
This divides the program memory into two areas:
●
Main program memory: Up to 8 Kbytes minus UBC
●
User-specific boot code (UBC): Configurable up to 8 Kbytes
The UBC area remains write-protected during in-application programming. This means that
the MASS keys do not unlock the UBC area. It protects the memory used to store the boot
program, specific code libraries, reset and interrupt vectors, the reset routine and usually the
IAP and communication routines.
Figure 2.
Flash memory organisation
Data
EEPROM
memory
Data memory area ( 640 bytes)
Option bytes
UBC area
Remains write protected during IAP
Low density
Flash program memory
(8 Kbytes)
Program memory area
Write access possible for IAP
14/95
Doc ID 15441 Rev 2
Programmable area from 64 bytes
(1 page) up to 8 Kbytes
(in 1 page steps)
STM8S103x
Product overview
Read-out protection (ROP)
The read-out protection blocks reading and writing the Flash program memory and data
EEPROM memory in ICP mode (and debug mode). Once the read-out protection is
activated, any attempt to toggle its status triggers a global erase of the program and data
memory. Even if no protection can be considered as totally unbreakable, the feature
provides a very high level of protection for a general purpose microcontroller.
4.5
Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low power modes and
ensures clock robustness.
Features
●
Clock prescaler: to get the best compromise between speed and current consumption
the clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler
●
Safe clock switching: Clock sources can be changed safely on the fly in run mode
through a configuration register. The clock signal is not switched until the new clock
source is ready. The design guarantees glitch-free switching.
●
Clock management: To reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
●
Master clock sources: 4 different clock sources can be used to drive the master clock:
–
1-16 MHz high-speed external crystal (HSE)
–
Up to 16 MHz high-speed user-external clock (HSE user-ext)
–
16 MHz high-speed internal RC oscillator (HSI)
–
128 kHz low-speed internal RC (LSI)
●
Startup clock: After reset, the microcontroller restarts by default with an internal 2
MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the
application program as soon as the code execution starts.
●
Clock security system (CSS): This feature can be enabled by software. If an HSE
clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS
and an interrupt can optionally be generated.
●
Configurable main clock output (CCO): This outputs an external clock for use by the
application.
Table 2.
Bit
Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Peripheral
clock
Peripheral
clock
Bit
Bit
Peripheral
clock
Bit
Peripheral
clock
PCKEN17
TIM1
PCKEN13
UART1
PCKEN27
Reserved
PCKEN23
ADC
PCKEN16
TIM2
PCKEN12
Reserved
PCKEN26
Reserved
PCKEN22
AWU
PCKEN15
TIM3
PCKEN11
SPI
PCKEN25
Reserved
PCKEN21
Reserved
PCKEN14
TIM4
PCKEN10
I2C
PCKEN24
Reserved
PCKEN20
Reserved
Doc ID 15441 Rev 2
15/95
Product overview
4.6
STM8S103x
Power management
For efficent power management, the application can be put in one of four different low-power
modes. You can configure each mode to obtain the best compromise between lowest power
consumption, fastest start-up time and available wakeup sources.
4.7
●
Wait mode: in this mode, the CPU is stopped, but peripherals are kept running. The
wakeup is performed by an internal or external interrupt or reset.
●
Active halt mode with regulator on: in this mode, the CPU and peripheral clocks are
stopped. An internal wakeup is generated at programmable intervals by the auto wake
up unit (AWU). The main voltage regulator is kept powered on, so current consumption
is higher than in active halt mode with regulator off, but the wakeup time is faster.
Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
●
Active halt mode with regulator off: this mode is the same as active halt with
regulator on, except that the main voltage regulator is powered off, so the wake up time
is slower.
●
Halt mode: in this mode the microcontroller uses the least power, CPU and peripheral
clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by
external event or reset.
Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
Activation of the watchdog timers is controlled by option bytes or by software. Once
activated, the watchdogs cannot be disabled by the user program without performing a
reset.
Window watchdog timer
The window watchdog is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
The window function can be used to trim the watchdog behavior to match the application
perfectly.
The application software must refresh the counter before time-out and during a limited time
window.
A reset is generated in two situations:
16/95
1.
Timeout: At 16 MHz CPU clock the time-out period can be adjusted between 75 µs up
to 64 ms.
2.
Refresh out of window: The downcounter is refreshed before its value is lower than the
one stored in the window register.
Doc ID 15441 Rev 2
STM8S103x
Product overview
Independent watchdog timer
The independent watchdog peripheral can be used to resolve processor malfunctions due to
hardware or software failures.
It is clocked by the 128 kHZ LSI internal RC clock source, and thus stays active even in case
of a CPU clock failure
The IWDG time base spans from 60 µs to 1 s.
4.8
4.9
Auto wakeup counter
●
Used for auto wakeup from active halt mode
●
Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
●
Can be internally connected to TIM1 input capture channel 1 for calibration
Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
4.10
TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver
4.11
●
16-bit up, down and up/down autoreload counter with 16-bit prescaler
●
Four independent capture/compare channels (CAPCOM) configurable as input
capture, output compare, PWM generation (edge and center aligned mode) and single
pulse mode output
●
Synchronization module to control the timer with external signals
●
Break input to force the timer outputs into a defined state
●
Three complementary outputs with adjustable dead time
●
Encoder mode
●
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
TIM2 - 16-bit general purpose timer
●
16-bit autoreload (AR) up-counter
●
15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
●
3 individually configurable capture/compare channels
●
PWM mode
●
Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
Doc ID 15441 Rev 2
17/95
Product overview
4.12
Table 3.
STM8S103x
TIM4 - 8-bit basic timer
●
8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
●
Clock source: CPU clock
●
Interrupt source: 1 x overflow/update
TIM timer features
Timer
Counter
size (bits)
Prescaler
TIM1
16
Any integer from
1 to 65536
Up/down
4
3
Yes
TIM2
16
Any power of 2 from 1
to 32768
Up
3
0
No
TIM4
8
Any power of 2 from 1
to 128
Up
0
0
No
4.13
Ext.
trigger
Timer
synchronization/
chaining
No
Analog-to-digital converter (ADC1)
●
4.14
Counting CAPCOM Complem.
mode
channels
outputs
STM8S103x Access line products contain a 10-bit successive approximation A/D
converter (ADC1) with up to 5 external and 1 internal multiplexed input channels and
the following main features:
–
Input voltage range: 0 to VDD
–
Conversion time: 14 clock cycles
–
Single and continuous and buffered continuous conversion modes
–
Buffer size (n x 10 bits) where x = number of input channels
–
Scan mode for single and continuous conversion of a sequence of channels
–
Analog watchdog capability with programmable upper and lower thresholds
–
Analog watchdog interrupt
–
External trigger input
–
Trigger from TIM1 TRGO
–
End of conversion (EOC) interrupt
Communication interfaces
The following communication interfaces are implemented:
18/95
●
UART1: Full feature UART, synchronous mode, SPI master mode, Smartcard mode,
IrDA mode, single wire mode, LIN2.1 master capability
●
SPI : Full and half-duplex, 8 Mbit/s
●
I²C: Up to 400 Kbit/s
Doc ID 15441 Rev 2
STM8S103x
4.14.1
Product overview
UART1
Main features
●
One Mbit/s full duplex SCI
●
SPI emulation
●
High precision baud rate generator
●
Smartcard emulation
●
IrDA SIR encoder decoder
●
LIN master mode
●
Single wire half duplex mode
Asynchronous communication (UART mode)
●
Full duplex communication - NRZ standard format (mark/space)
●
Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of
following any standard baud rate regardless of the input frequency
●
Separate enable bits for transmitter and receiver
●
Two receiver wakeup modes:
–
Address bit (MSB)
–
Idle line (interrupt)
●
Transmission error detection with interrupt generation
●
Parity control
Synchronous communication
●
Full duplex synchronous transfers
●
SPI master operation
●
8-bit data communication
●
Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16)
LIN master mode
4.14.2
●
Emission: Generates 13-bit synch break frame
●
Reception: Detects 11-bit break frame
SPI
●
Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
●
Full duplex synchronous transfers
●
Simplex synchronous transfers on 2 lines with a possible bidirectional data line
●
Master or slave operation - selectable by hardware or software
●
CRC calculation
●
1 byte Tx and Rx buffer
●
Slave/master selection input pin
Doc ID 15441 Rev 2
19/95
Product overview
4.14.3
I2C
●
●
20/95
STM8S103x
I2C master features:
–
Clock generation
–
Start and stop generation
I2C
slave features:
–
Programmable I2C address detection
–
Stop bit detection
●
Generation and detection of 7-bit/10-bit addressing and general call
●
Supports different communication speeds:
–
Standard speed (up to 100 kHz)
–
Fast speed (up to 400 kHz)
Doc ID 15441 Rev 2
STM8S103x
Pinout and pin description
STM8S103K VQFN32/LQFP32 pinout
PD7 (HS)/TLI [TIM1_CH4]
PD6 (HS)/UART1_RX
PD5 (HS)/UART1_TX
PD4 (HS)/BEEP/TIM2_CH1
PD3 (HS)/TIM2_CH2/ADC_ETR
PD2 (HS) [TIM2_CH3]
PD1 (HS)/SWIM
PD0 (HS)/ TIM1_BKIN [CLK_CCO]
Figure 3.
NRST
OSCIN/PA1
OSCOUT/PA2
VSS
VCAP
VDD
[SPI_NSS] TIM2_CH3/(HS)PA3
PF4
1
2
3
4
5
6
7
8
32 31 30 29 28 27 26 25
24
23
22
21
20
19
18
17
9 10 11 12 13 14 1516
PC7 (HS)/SPI_MISO
PC6 (HS)/SPI_MOSI
PC5 (HS)/SPI_SCK
PC4 (HS)/TIM1_CH4/CLK_CCO
PC3 (HS)/TIM1_CH3
PC2 (HS)/TIM1_CH2
PC1 (HS)/TIM1_CH1/UART1_CK
PE5 (HS)/SPI_NSS
PB7
PB6
I2C_SDA/ (T) PB5
I2C_SCL/(T) PB4
TIM1_ETR/AIN3/(HS) PB3
TIM1_CH3N/ AIN2/(HS) PB2
TIM1_CH2N/ AIN1/(HS) PB1
TIM1_CH1N/AIN0/(HS) PB0
5
Pinout and pin description
Refer to Table 7 for pin-to-pin comparison with STM8S105K
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
Doc ID 15441 Rev 2
21/95
Pinout and pin description
Table 4.
STM8S103x
Legend/abbreviations
Type
I= Input, O = Output, S = Power supply
Level
Input
CM = CMOS
Output
HS = High sink
Output speed
O1 = Slow (up to 2 MHz)
O2 = Fast (up to 10 MHz)
O3 = Fast/slow programmability with slow as default state after reset
O4 = Fast/slow programmability with fast as default state after reset
Port and control Input
configuration
Output
float = floating, wpu = weak pull-up
T = True open drain, OD = Open drain, PP = Push pull
Reset state is shown in bold.
PP
OD
High sink(1)
Output
Ext. interrupt
wpu
Pin name
floating
Pin
no.
Type
Input
X
Main function
(after reset)
VQFN32/LQFP32 pin description
Speed
Table 5.
Default alternate
function
1
NRST
I/O
2
PA1/OSCIN(2)
I/O
X
X
X
O1
X
X
Port A1
Resonator/
crystal in
3
PA2/OSCOUT
I/O
X
X
X
O1
X
X
Port A2
Resonator/crystal
out
4
VSS
S
9Digital ground
5
VCAP
S
1.8 V regulator capacitor
6
VDD
S
Digital power supply
7
PA3/TIM2_CH3
[SPI_NSS]
I/O
X
X
8
PF4
I/O
X
X
9
PB7
I/O
X
X
10 PB6
I/O
X
11 PB5/I2C_SDA
I/O
12 PB4/I2C_SCL
Reset
HS O3
X
X Port A3
O1
X
X
Port F4
X
O1
X
X
Port B7
X
X
O1
X
X
Port B6
X
X
X
O1 T(3)
Port B5 I2C data
I/O
X
X
X
O1 T(3)
Port B4 I2C clock
13 PB3/AIN3/TIM1_ETR
I/O
X
X
X
HS O3
X
X
Analog input 3/
Port B3 Timer 1 external
trigger
14 PB2/AIN2/TIM1_CH3N
I/O
X
X
X
HS O3
X
X
Analog input 2/
Port B2 Timer 1 - inverted
channel 3
22/95
Alternate
function
after
remap
[option
bit]
X
Doc ID 15441 Rev 2
Timer 2 channel 3
SPI
master/
slave
select
[AFR1]
STM8S103x
VQFN32/LQFP32 pin description (continued)
Ext. interrupt
High sink(1)
Speed
OD
PP
15 PB1/AIN1/TIM1_CH2N
I/O
X
X
X
HS O3
X
X
Analog input 1/
Port B1 Timer 1 - inverted
channel 2
16 PB0/AIN0/TIM1_CH1N
I/O
X
X
X
HS O3
X
X
Analog input 0/
Port B0 Timer 1 - inverted
channel 1
17 PE5/SPI_NSS
I/O
X
X
X
HS O3
X
X
Port E5
SPI master/slave
select
PC1/TIM1_CH1/
UART1_CK
I/O
X
X
X
HS O3
X
X
Port C1
Timer 1 - channel 1
UART1 clock
19 PC2/TIM1_CH2
I/O
X
X
X
HS O3
X
X
Port C2 Timer 1 - channel 2
20 PC3/TIM1_CH3
I/O
X
X
X
HS O3
X
X
Port C3 Timer 1 - channel 3
PC4/TIM1_CH4/
CLK_CCO
I/O
X
X
X
HS O3
X
X
Timer 1 - channel 4
Port C4 /configurable clock
output
22 PC5/SPI_SCK
I/O
X
X
X
HS O3
X
X
Port C5 SPI clock
23 PC6/SPI_MOSI
I/O
X
X
X
HS O3
X
X
Port C6
SPI master out/
slave in
24 PC7/SPI_MISO
I/O
X
X
X
HS O3
X
X
Port C7
SPI master in/
slave out
Pin
no.
18
21
Pin name
Default alternate
function
I/O
X
X
X
HS O3
X
X
Port D0
Timer 1 - break
input
26 PD1/SWIM
I/O
X
X
X
HS O4
X
X
Port D1
SWIM data
interface
27 PD2 [TIM2_CH3]
I/O
X
X
X
HS O3
X
X
Port D2
PD3/TIM2_CH2/
ADC_ETR
I/O
X
X
X
HS O3
X
X
Timer 2 - channel
Port D3 2/ADC external
trigger
29 PD4/TIM2_CH1/BEEP
I/O
X
X
X
HS O3
X
X
Port D4
Timer 2 - channel
1/BEEP output
30 PD5/UART1_TX
I/O
X
X
X
HS O3
X
X
Port D5
UART1 data
transmit
25
28
PD0/TIM1_BKIN
[CLK_CCO]
Type
wpu
Output
floating
Input
Main function
(after reset)
Table 5.
Pinout and pin description
Doc ID 15441 Rev 2
Alternate
function
after
remap
[option
bit]
Configurable
clock
output
[AFR5]
Timer 2 channel 3
[AFR1]
23/95
Pinout and pin description
VQFN32/LQFP32 pin description (continued)
Ext. interrupt
High sink(1)
Speed
OD
PP
31 PD6/UART1_RX
I/O
X
X
X
HS O3
X
X
Port D6
32 PD7/TLI [TIM1_CH4]
I/O
X
X
X
HS O3
X
X
Port D7 Top level interrupt
Pin
no.
Pin name
Type
wpu
Output
floating
Input
Main function
(after reset)
Table 5.
STM8S103x
Default alternate
function
Alternate
function
after
remap
[option
bit]
UART1 data
receive
Timer 1 channel 4
[AFR6]
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Table 17: Current characteristics).
2. When the MCU is in halt/active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if halt/active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
24/95
Doc ID 15441 Rev 2
STM8S103x
Pinout and pin description
Figure 4.
STM8S103F TSSOP 20-pin pinout
UART1_CK/TIM2_CH1/BEEP/(HS)PD4
UART1_TX/AIN5/(HS) PD5
1
20
2
19
UART1_RX/AIN6/(HS) PD6
3
18
PD1(HS)/SWIM
NRST
4
17
PC7 (HS)/SPI_MISO [TIM1_CH2]
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD2 (HS) [AIN3] [TIM2_CH3]
OSCIN/PA1
5
16
PC6 (HS)/SPI_MOSI [TIM1_CH1]
OSCOUT/PA2
6
15
PC5 (HS)/SPI_SCK [TIM2_CH1]
VSS
7
14
PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
VCAP
VDD
8
13
PC3 (HS)/TIM1_CH3 [TLI] [TIM1_CH1N]
9
12
10
11
PB4 (T)/I2C_SCL [ADC_ETR]
PB5 (T)/ I2C_SDA [TIM1_BKIN]
[SPI_NSS] TIM2_CH3/(HS) PA3
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option.
Doc ID 15441 Rev 2
25/95
Pinout and pin description
26/95
PD2 (HS) [AIN3] [TIM2_CH3]
20 19 18 17
16
PD5 (HS)/AIN5/UART1_TX
PD3 (HS)/AIN4/TIM2_CH2/ADC_ETR
PD4 (HS)/BEEP / TIM2_CH1/UART1_CK
STM8S103F WFQFPN package pinout
PD6 (HS)/AIN6/UART1_RX
Figure 5.
STM8S103x
14
PC7 (HS)/SPI_MISO [TIM1_CH2]
OSCOUT/PA2
3
13
PC6 (HS)/SPI_MOSI [TIM1_CH1]
VSS
4
12
PC5 (HS)/SPI_SCK [TIM2_CH1]
VCAP
5
11
PC4 (HS)/TIM1_CH4/CLK_CCO [AIN2] [TIM1_CH2N]
6
7
8
9
10
[TIM1_CH1N] [TLI] TIM1_CH3 /(HS)PC3
2
[ADC_ETR] I2C_SCL / (T)PB4
PD1(HS)/SWIM
OSCIN/PA1
[TIM1_BKIN] I2C_SDA/(T)PB5
15
VDD
1
[SPI_NSS] TIM2_CH3/(HS) PA3
NRST
1.
(HS) high sink capability.
2.
(T) True open drain (P-buffer and protection diode to VDD not implemented).
3.
[ ] alternate function remapping option.
Doc ID 15441 Rev 2
STM8S103x
STM8S103F pin description
Output
Alternate
Default alternate function after
function
remap
[option bit]
X HS O3 X
Analog input 5/
X Port D5 UART1 data
transmit
3
20 PD6/AIN6/UART1_RX
I/O X
X
X HS O3 X
Analog input 6/
X Port D6 UART1 data
receive
4
1 NRST
I/O
X
5
2 PA1/OSCIN(2)
I/O X
X
X
O1 X
X Port A1
Resonator/
crystal in
6
3 PA2/OSCOUT
I/O X
X
X
O1 X
X Port A2
Resonator/crystal
out
7
4 VSS
S
Digital ground
8
5 VCAP
S
1.8 V regulator capacitor
9
6 VDD
S
Digital power supply
10
7
PA3/TIM2_CH3
[SPI_NSS]
I/O X
X
X HS O3 X
11
8
PB5/I2C_SDA
[TIM1_BKIN]
I/O X
X
X
O1 T(3)
Port B5 I2C data
Timer 1 - break
input [AFR4]
12
9 PB4/I2C_SCL
I/O X
X
X
O1 T(3)
Port B4 I2C clock
ADC external
trigger
[AFR4]
13 10
PC3/TIM1_CH3 [TLI]
[TIM1_CH1N]
PC4/CLK_CCO/
14 11 TIM1_CH4 [AIN2]
[TIM1_CH2N]
I/O X
I/O X
X
X
PP
X
OD
I/O X
Speed
19 PD5/AIN5/UART1_TX
2
PD4/BEEP/TIM2_CH1/
UART1_CK
High sink(1)
Timer 2 - channel
X Port D4 1/BEEP output/
UART1 clock
18
floating
X HS O3 X
1
Pin name
Type
X
WFQFPN20
I/O X
TSSPOP20
Ext. interrupt
Input
wpu
Pin no.
Main function
(after reset)
Table 6.
Pinout and pin description
Reset
SPI master/
X Port A3 Timer 2 channel 3 slave select
[AFR1]
X HS O3 X
Top level
interrupt
[AFR3]
Timer 1 - channel
X Port C3
Timer 1 3
inverted
channel 1
[AFR7]
X HS O3 X
Configurable
clock output/
X Port C4
Timer 1 - channel
4
Doc ID 15441 Rev 2
Analog input 2
[AFR2]
Timer 1 inverted
channel 2
[AFR7]
27/95
Pinout and pin description
STM8S103F pin description (continued)
Output
Alternate
Default alternate function after
function
remap
[option bit]
PC6/SPI_MOSI
[TIM1_CH1]
I/O X
X
X HS O3 X
X Port C6
SPI master out/
slave in
Timer 1 channel 1
[AFR0]
17 14
PC7/SPI_MISO
[TIM1_CH2]
I/O X
X
X HS O3 X
X Port C7
SPI master in/
slave out
Timer 1 channel 2
[AFR0]
I/O X
X
X HS O4 X
X Port D1
SWIM data
interface
18 15 PD1/SWIM
19 16 PD2 [AIN3] [TIM2_CH3]
PD3/AIN4/TIM2_CH2/
20 17
ADC_ETR
I/O X
I/O X
X
X
PP
16 13
OD
X Port C5 SPI clock
Speed
X HS O3 X
High sink(1)
X
floating
I/O X
Pin name
Type
PC5/SPI_SCK
[TIM2_CH1]
WFQFPN20
15 12
TSSPOP20
Ext. interrupt
Input
wpu
Pin no.
Main function
(after reset)
Table 6.
STM8S103x
X HS O3 X
X Port D2
X HS O3 X
Analog input 4/
Timer 2 - channel
X Port D3
2/ADC external
trigger
Timer 2 channel 1
[AFR0]
Analog input 3
[AFR2]
Timer 2 channel 3
[AFR1]
1. I/O pins used simultaneously for high current source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings ( see Table 17: Current characteristics).
2. When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull up and cannot be used for
waking up the device. In this mode, the output state of PA1 is not driven. It is recommended to use PA1 only in input mode
if Halt/Active-halt is used in the application.
3. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer and protection diode to VDD are not
implemented)
28/95
Doc ID 15441 Rev 2
STM8S103x
Table 7.
Pin
No.
Pinout and pin description
Pin-to-pin comparison of pin 7 to 12 in 32-pin access line devices
STM8S105K (see seperate datasheet)
Pin name
STM8S103K (see Figure 3)
Comment
Pin name
Comment
7
VDDIO
Dedicated power supply for I/Os.
PA3/TIM2_CH3
[SPI_NSS]
VDDIO pad bonded to VDD,
pin 7 bonded to GPIO port
A3.
Can be used for TIM2
channel 3 or SPI
master/slave select.
8
PF4/ AIN12
GPIO port F4. Can be used as
ADC input channel 12.
PF4
GPIO port F4.
No ADC input capability.
9
VDDA
Dedicated supply and reference
voltage for ADC
PB7
VDDA pad bonded to VDD, pin
9 bonded to GPIO port B7.
10
VSSA
Dedicated ground for ADC
PB6
VSSA pad bonded to VSS, pin
9 bonded to GPIO port B6.
11
GPIO port B5. Can be used as
PB5/AIN5/I2C_SDA
PB5/I2C_SDA
ADC input channel 5 or I2C data
12
5.1
PB4/I2C_SCL
GPIO port B4. Can be used as
ADC input channel 4 or I2C
clock
PB5/I2C_SDA
GPIO port B5.
Can be used for I2C data.
True open drain capability.
No ADC input capability.
GPIO port B4.
Can be used for I2C clock.
True open drain capability.
No ADC input capability.
Alternate function remapping
As shown in the rightmost column of the pin description table, some alternate functions can
be remapped at different I/O ports by programming one of 8 AFR (alternate function remap)
option bits. Refer to Section 7: Option bytes. When the remapping option is active, the
default alternate function is no longer available.
To use an alternate function, the corresponding peripheral must be enabled in the peripheral
registers.
Alternate function remapping does not effect GPIO capabilities of the I/O ports (see GPIO
section of the family reference manual, RM0016).
Doc ID 15441 Rev 2
29/95
Interrupt vector mapping
STM8S103x
6
Interrupt vector mapping
Table 8.
Interrupt mapping
IRQ
no.
Source
block
RESET
TRAP
Wakeup from
halt mode
Wakeup from
active-halt mode
Vector address
Yes
Yes
0x00 8000
Software interrupt
-
-
0x00 8004
External top level Interrupt
-
-
0x00 8008
Yes
0x00 800C
-
0x00 8010
Yes(1)
0x00 8014
Description
Reset
0
TLI
1
AWU
Auto wake up from halt
-
2
CLK
Clock controller
Yes
(1)
3
EXTI0
Port A external interrupts
4
EXTI1
Port B external interrupts
Yes
Yes
0x00 8018
5
EXTI2
Port C external interrupts
Yes
Yes
0x00 801C
6
EXTI3
Port D external interrupts
Yes
Yes
0x00 8020
7
EXTI4
Port E external interrupts
Yes
Yes
0x00 8024
8
Reserved
-
-
0x00 8028
9
Reserved
-
-
0x00 802C
Yes
Yes
0x00 8030
10
SPI
End of transfer
11
TIM1
TIM1
update/overflow/underflow/trigger/b
reak
-
-
0x00 8034
12
TIM1
TIM1 capture/compare
-
-
0x00 8038
13
TIM2
TIM2 update /overflow
-
-
0x00 803C
14
TIM2
TIM2 capture/compare
-
-
0x00 8040
15
Reserved
-
-
0x00 8044
16
Reserved
-
-
0x00 8048
17
UART1
Tx complete
-
-
0x00 804C
18
UART1
Receive register DATA FULL
-
-
0x00 8050
19
2
Yes
Yes
0x00 8054
I C
2
I C interrupt
20
Reserved
-
-
0x00 8058
21
Reserved
-
-
0x00 805C
22
ADC1
ADC1 end of conversion/analog
watchdog interrupt
-
-
0x00 8060
23
TIM4
TIM4 update/overflow
-
-
0x00 8064
24
FLASH
EOP/WR_PG_DIS
-
-
0x00 8068
0x00 806C to
0x00 807C
Reserved
1. Except PA1
30/95
Doc ID 15441 Rev 2
STM8S103x
7
Option bytes
Option bytes
Option bytes contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated block of the memory. Except for the
ROP (read-out protection) byte, each option byte has to be stored twice, in a regular form
(OPTx) and a complemented one (NOPTx) for redundancy.
Option bytes can be modified in ICP mode (via SWIM) by accessing the EEPROM address
shown in Table 9: Option bytes below.
Option bytes can also be modified ‘on the fly’ by the application in IAP mode, except the
ROP option that can only be modified in ICP mode (via SWIM).
Refer to the STM8S Flash programming manual (PM0051) and STM8 SWIM
communication protocol and debug module user manual (UM0470) for information on SWIM
programming procedures.
Table 9.
Addr.
Option bytes
Option
name
Option
byte
no.
Option bits
7
6
5
4
3
2
1
0
Factory
default
setting
Read-out
0x4800
protection
OPT0
ROP[7:0]
00h
UBC[7:0]
00h
NUBC[7:0]
FFh
(ROP)
0x4801
User boot
OPT1
0x4802
code(UBC)
NOPT1
Alternate
OPT2
0x4803
AFR7
AFR6
AFR5
AFR4
AFR3
AFR2
AFR1
AFR0
00h
NAFR7
NAFR6
NAFR5
NAFR4
NAFR3
NAFR2
NAFR1
NAFR0
FFh
function
0x4804
remapping
NOPT2
(AFR)
OPT3
Reserved
HSITRIM
0x4806
NOPT3
Reserved
NHSITRIM
0x4807
OPT4
Reserved
NOPT4
Reserved
0x4805h
Miscellaneous
option
LSI
IWDG
WWDG
WWDG
_EN
_HW
_HW
_HALT
NLSI
NIWDG_H
NWWDG
NWWG
_EN
W
_HW
_HALT
EXT
CKAWU
PRS
PRS
CLK
SEL
C1
C0
NEXT
NCKAWUS
NPR
NPR
CLK
EL
SC1
SC0
00h
FFh
00h
Clock option
0x4808
0x4809
HSE clock
OPT5
0x480A
startup
NOPT5
FFh
HSECNT[7:0]
00h
NHSECNT[7:0]
FFh
Doc ID 15441 Rev 2
31/95
Option bytes
STM8S103x
Table 10.
Option byte description
Option byte no.
Description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Enable readout protection (write access via SWIM protocol)
Note: Refer to the family reference manual (RM0016) section on
Flash/EEPROM memory readout protection for details.
OPT1
UBC[7:0] User boot code area
0x00: no UBC, no write-protection
0x01: Page 0 defined as UBC, memory write-protected
0x02: Pages 0 to 1 defined as UBC, memory write-protected. Page 0 and
1 contain the interrupt vectors.
...
0x7F: Pages 0 to 126 defined as UBC, memory write-protected
Other values: Pages 0 to 127 defined as UBC, memory write-protected
Note: Refer to the family reference manual (RM0016) section on Flash
write protection for more details.
OPT2
AFR[7:0]
For 32 pin devices, refer to Table 11: STM8S103K alternate function
remapping bits on page 33. For 20-pin devices refer to Table 12:
STM8S103F alternate function remapping bits on page 34
HSITRIM: High speed internal clock trimming register size
0: 3-bit trimming supported in CLK_HSITRIMR register
1: 4-bit trimming supported in CLK_HSITRIMR register
LSI_EN: Low speed internal clock enable
0: LSI clock is not available as CPU clock source
1: LSI clock is available as CPU clock source
OPT3
IWDG_HW: Independent watchdog
0: IWDG Independent watchdog activated by software
1: IWDG Independent watchdog activated by hardware
WWDG_HW: Window watchdog activation
0: WWDG window watchdog activated by software
1: WWDG window watchdog activated by hardware
WWDG_HALT: Window watchdog reset on halt
0: No reset generated on halt if WWDG active
1: Reset generated on halt if WWDG active
32/95
Doc ID 15441 Rev 2
STM8S103x
Option bytes
Table 10.
Option byte description (continued)
Option byte no.
Description
EXTCLK: External clock selection
0: External crystal connected to OSCIN/OSCOUT
1: External clock signal on OSCIN
OPT4
CKAWUSEL: Auto wake-up unit/clock
0: LSI clock source selected for AWU
1: HSE clock with prescaler selected as clock source for for AWU
PRSC[1:0] AWU clock prescaler
0x: 16 MHz to 128 kHz prescaler
10: 8 MHz to 128 kHz prescaler
11: 4 MHz to 128 kHz prescaler
OPT5
Table 11.
HSECNT[7:0]: HSE crystal oscillator stabilization time
0x00: 2048 HSE cycles
0xB4: 128 HSE cycles
0xD2: 8 HSE cycles
0xE1: 0.5 HSE cycles
STM8S103K alternate function remapping bits
Description(1)
Option byte no.
OPT2
AFR7 Alternate function remapping option 7
Reserved
AFR6 Alternate function remapping option 6
0: Port D7 alternate function = TLI
1: Port D7 alternate function = TIM1_CH4
AFR5 Alternate function remapping option 5
0: Port D0 alternate function = TIM1_BKIN
1: Port D0 alternate function = CLK_CCO
AFR[4:2] Alternate function remapping options 4:2
Reserved
AFR1 Alternate function remapping option 1
0: Port A3 alternate function = TIM2_CH3
1: Port A3 alternate function = SPI_NSS, port D2 alternate function =
TIM2_CH3
AFR0 Alternate function remapping option 0
Reserved
1. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0.
Doc ID 15441 Rev 2
33/95
Option bytes
STM8S103x
Table 12.
STM8S103F alternate function remapping bits
Option byte no.
Description(1)
OPT2
AFR7Alternate function remapping option 7
0: Port C3 alternate function = TIM1_CH3, Port C4 alternate function =
TIM1_CH4, AIN2 or CLK_CCO
1: Port C3 alternate function = TIM1_CH1N, port C4 alternate function =
TIM1_CH2N
AFR6 Alternate function remapping option 6
Reserved
AFR5 Alternate function remapping option 5
Reserved
AFR4 Alternate function remapping option 4
0: Port B4 alternate function = I2C_SCL, port B5 alternate function =
I2C_SDA,
1: Port B4 alternate function = ADC_ETR, port B5 alternate function =
TIM1_BKIN
AFR3 Alternate function remapping option 3
0: Port C3 alternate function = TIM1_CH3
1: Port C3 alternate function = TLI
AFR2 Alternate function remapping option 2
0: AIN2 and AIN3 not mapped on Port C4 and Port D2.
1: Port C4 alternate function = AIN2, Port D2 alternate function = AIN3
AFR1 Alternate function remapping option 1(1)
0: Port A3 alternate function = TIM2_CH3
1: Port A3 alternate function = SPI_NSS, port D2 alternate function =
TIM2_CH3
AFR0 Alternate function remapping option 0(1)
0: Port C5 alternate function = SPI_SCK, port C6 alternate function =
SPI_MOSI, port C7 alternate function = SPI_MISO
1: Port C5 alternate function = TIM2_CH1, port C6 alternate function =
TIM1_CH1, port C7 alternate function = TIM1_CH2
1. Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
AFR0.
34/95
Doc ID 15441 Rev 2
STM8S103x
Memory and register map
8
Memory and register map
8.1
Memory map
Figure 6.
Memory map
0x00 0000
0x00 03FF
RAM
(1 Kbyte)
512 bytes stack
Reserved
0x00 4000
0x00 427F
0x00 4280
0x00 47FF
0x00 4800
0x00 480A
0x00 480B
640 bytes data EEPROM
Reserved
Option bytes
Reserved
0x00 4FFF
0x00 5000
0x00 57FF
0x00 5800
GPIO and periph. reg.
(see Table 13 and
Reserved
0x00 7EFF
0x00 7F00
0x00 7FFF
0x00 8000
0x00 807F
0x00 9FFF
0x00 A000
CPU/SWIM/Debug/ITC
Registers (see Table 15 )
32 interrupt vectors
Flash program memory
(8 Kbytes)
Reserved
0x02 7FFF
Doc ID 15441 Rev 2
35/95
Memory and register map
8.2
Register map
Table 13.
I/O port hardware register map
Register label
Register name
Reset
status
0x00 5000
PA_ODR
Port A data output latch register
0x00
0x00 5001
PA_IDR
Port A input pin value register
0x00
PA_DDR
Port A data direction register
0x00
0x00 5003
PA_CR1
Port A control register 1
0x00
0x00 5004
PA_CR2
Port A control register 2
0x00
0x00 5005
PB_ODR
Port B data output latch register
0x00
0x00 5006
PB_IDR
Port B input pin value register
0x00
PB_DDR
Port B data direction register
0x00
0x00 5008
PB_CR1
Port B control register 1
0x00
0x00 5009
PB_CR2
Port B control register 2
0x00
0x00 500A
PC_ODR
Port C data output latch register
0x00
0x00 500B
PB_IDR
Port C input pin value register
0x00
PC_DDR
Port C data direction register
0x00
0x00 500D
PC_CR1
Port C control register 1
0x00
0x00 500E
PC_CR2
Port C control register 2
0x00
0x00 500F
PD_ODR
Port D data output latch register
0x00
0x00 5010
PD_IDR
Port D input pin value register
0x00
PD_DDR
Port D data direction register
0x00
0x00 5012
PD_CR1
Port D control register 1
0x00
0x00 5013
PD_CR2
Port D control register 2
0x00
0x00 5014
PE_ODR
Port E data output latch register
0x00
0x00 5015
PE_IDR
Port E input pin value register
0x00
PE_DDR
Port E data direction register
0x00
0x00 5017
PE_CR1
Port E control register 1
0x00
0x00 5018
PE_CR2
Port E control register 2
0x00
0x00 5019
PF_ODR
Port F data output latch register
0x00
0x00 501A
PF_IDR
Port F input pin value register
0x00
PF_DDR
Port F data direction register
0x00
0x00 501C
PF_CR1
Port F control register 1
0x00
0x00 501D
PF_CR2
Port F control register 2
0x00
Address
0x00 5002
0x00 5007
0x00 500C
0x00 5011
0x00 5016
0x00 501B
36/95
STM8S103x
Block
Port A
Port B
Port C
Port D
Port E
Port F
Doc ID 15441 Rev 2
STM8S103x
Memory and register map
0x
Table 14.
General hardware register map
Address
Block
Register label
0x00 501E
to
0x00 5059
Register name
Reset
status
Reserved area (60 bytes)
0x00 505A
FLASH_CR1
Flash control register 1
0x00
0x00 505B
FLASH_CR2
Flash control register 2
0x00
0x00 505C
FLASH_NCR2
Flash complementary control
register 2
0xFF
FLASH _FPR
Flash protection register
0x00
0x00 505E
FLASH _NFPR
Flash complementary protection
register
0xFF
0x00 505F
FLASH _IAPSR
Flash in-application programming
status register
0x00
0x00 505D
Flash
0x00 5060
to
0x00 5061
0x00 5062
Reserved area (2 bytes)
Flash
FLASH _PUKR
0x00 5063
0x00 5064
Flash Program memory unprotection
register
0x00
Reserved area (1 byte)
Flash
FLASH _DUKR
0x00 5065
to
0x00 509F
Data EEPROM unprotection register
0x00
Reserved area (59 bytes)
0x00 50A0
EXTI_CR1
External interrupt control register 1
0x00
EXTI_CR2
External interrupt control register 2
0x00
ITC
0x00 50A1
0x00 50A2
to
0x00 50B2
0x00 50B3
Reserved area (17 bytes)
RST
RST_SR
0x00 50B4
to
0x00 50BF
Reset status register
xx
Reserved area (12 bytes)
0x00 50C0
CLK_ICKR
Internal clock control register
0x01
CLK_ECKR
External clock control register
0x00
CLK
0x00 50C1
0x00 50C2
Reserved area (1 byte)
Doc ID 15441 Rev 2
37/95
Memory and register map
Table 14.
STM8S103x
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 50C3
CLK_CMSR
Clock master status register
0xE1
0x00 50C4
CLK_SWR
Clock master switch register
0xE1
0x00 50C5
CLK_SWCR
Clock switch control register
0bxxxx
0000
0x00 50C6
CLK_CKDIVR
Clock divider register
0x18
CLK_PCKENR1
Peripheral clock gating register 1
0xFF
CLK_CSSR
Clock security system register
0x00
0x00 50C9
CLK_CCOR
Configurable clock control register
0x00
0x00 50CA
CLK_PCKENR2
Peripheral clock gating register 2
0xFF
0x00 50CB
CLK_CANCCR
CAN clock control register
0x00
0x00 50CC
CLK_HSITRIMR
HSI clock calibration trimming register
xx
0x00 50CD
CLK_SWIMCCR
SWIM clock control register
x0
Address
Block
0x00 50C7
0x00 50C8
CLK
0x00 50CE
to
0x00 50D0
Reserved area (3 bytes)
0x00 50D1
WWDG_CR
WWDG control register
0x7F
WWDG_WR
WWDR window register
0x7F
WWDG
0x00 50D2
0x00 50D3
to
00 50DF
Reserved area (13 bytes)
0x00 50E0
0x00 50E1
IWDG
0x00 50E2
IWDG_KR
IWDG key register
-
IWDG_PR
IWDG prescaler register
0x00
IWDG_RLR
IWDG reload register
0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 bytes)
0x00 50F0
0x00 50F1
AWU
0x00 50F2
0x00 50F3
0x00 50F4
to
0x00 50FF
38/95
BEEP
AWU_CSR1
AWU control/status register 1
0x00
AWU_APR
AWU asynchronous prescaler buffer
register
0x3F
AWU_TBR
AWU timebase selection register
0x00
BEEP_CSR
BEEP control/status register
0x1F
Reserved area (12 bytes)
Doc ID 15441 Rev 2
STM8S103x
Memory and register map
Table 14.
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5200
SPI_CR1
SPI control register 1
0x00
0x00 5201
SPI_CR2
SPI control register 2
0x00
0x00 5202
SPI_ICR
SPI interrupt control register
0x00
SPI_SR
SPI status register
0x02
0x00 5204
SPI_DR
SPI data register
0x00
0x00 5205
SPI_CRCPR
SPI CRC polynomial register
0x07
0x00 5206
SPI_RXCRCR
SPI Rx CRC register
0xFF
0x00 5207
SPI_TXCRCR
SPI Tx CRC register
0xFF
Address
Block
0x00 5203
SPI
0x00 5208
to
0x00 520F
Reserved area (8 bytes)
I2C control register 1
I2C_CR1
0x00 5210
0x00 5211
I2C_CR2
I
2C
0x00
control register 2
0x00
frequency register
0x00
0x00 5212
I2C_FREQR
0x00 5213
I2C_OARL
I2C Own address register low
0x00
I2C_OARH
2C
0x00
0x00 5214
I
2C
I
Own address register high
0x00 5215
Reserved
0x00 5216
0x00 5217
0x00 5218
0x00 5219
I2C
I2C_DR
I2C data register
0x00
I2C_SR1
I2C status register 1
0x00
I2C_SR2
I
2C
status register 2
0x00
I2C_SR3
I2C
status register 3
0x0x
interrupt control register
0x00
0x00 521A
I2C_ITR
0x00 521B
I2C_CCRL
I2C Clock control register low
0x00
I2C_CCRH
I2C
0x00
0x00 521C
0x00 521D
0x00 521E
0x00 521F
to
0x00 522F
I
2C
2
I C TRISE register
I2C_TRISER
I2C_PECR
Clock control register high
I
2C
packet error checking register
0x02
0x00
Reserved area (17 bytes)
Doc ID 15441 Rev 2
39/95
Memory and register map
Table 14.
STM8S103x
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5230
UART1_SR
UART1 status register
C0h
0x00 5231
UART1_DR
UART1 data register
xxh
0x00 5232
UART1_BRR1
UART1 baud rate register 1
00h
0x00 5233
UART1_BRR2
UART1 baud rate register 2
00h
0x00 5234
UART1_CR1
UART1 control register 1
00h
UART1_CR2
UART1 control register 2
00h
0x00 5236
UART1_CR3
UART1 control register 3
00h
0x00 5237
UART1_CR4
UART1 control register 4
00h
0x00 5238
UART1_CR5
UART1 control register 5
00h
0x00 5239
UART1_GTR
UART1 guard time register
00h
0x00 523A
UART1_PSCR
UART1 prescaler register
00h
Address
0x00 5235
Block
UART1
0x00 523B
to
0x00 523F
Reserved area (21 bytes)
0x00 5250
TIM1_CR1
TIM1 control register 1
0x00
0x00 5251
TIM1_CR2
TIM1 control register 2
0x00
0x00 5252
TIM1_SMCR
TIM1 slave mode control register
0x00
0x00 5253
TIM1_ETR
TIM1 external trigger register
0x00
0x00 5254
TIM1_IER
TIM1 interrupt enable register
0x00
0x00 5255
TIM1_SR1
TIM1 status register 1
0x00
0x00 5256
TIM1_SR2
TIM1 status register 2
0x00
0x00 5257
TIM1_EGR
TIM1 event generation register
0x00
0x00 5258
TIM1_CCMR1
TIM1 capture/compare mode register
1
0x00
0x00 5259
TIM1_CCMR2
TIM1 capture/compare mode register
2
0x00
0x00 525A
TIM1_CCMR3
TIM1 capture/compare mode register
3
0x00
0x00 525B
TIM1_CCMR4
TIM1 capture/compare mode register
4
0x00
0x00 525C
TIM1_CCER1
TIM1 capture/compare enable register
1
0x00
0x00 525D
TIM1_CCER2
TIM1 capture/compare enable register
2
0x00
0x00 525E
TIM1_CNTRH
TIM1 counter high
0x00
TIM1
40/95
Doc ID 15441 Rev 2
STM8S103x
Memory and register map
Table 14.
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 525F
TIM1_CNTRL
TIM1 counter low
0x00
0x00 5260
TIM1_PSCRH
TIM1 prescaler register high
0x00
0x00 5261
TIM1_PSCRL
TIM1 prescaler register low
0x00
0x00 5262
TIM1_ARRH
TIM1 auto-reload register high
0xFF
0x00 5263
TIM1_ARRL
TIM1 auto-reload register low
0xFF
0x00 5264
TIM1_RCR
TIM1 repetition counter register
0x00
0x00 5265
TIM1_CCR1H
TIM1 capture/compare register 1 high
0x00
TIM1_CCR1L
TIM1 capture/compare register 1 low
0x00
TIM1_CCR2H
TIM1 capture/compare register 2 high
0x00
0x00 5268
TIM1_CCR2L
TIM1 capture/compare register 2 low
0x00
0x00 5269
TIM1_CCR3H
TIM1 capture/compare register 3 high
0x00
0x00 526A
TIM1_CCR3L
TIM1 capture/compare register 3 low
0x00
0x00 526B
TIM1_CCR4H
TIM1 capture/compare register 4 high
0x00
0x00 526C
TIM1_CCR4L
TIM1 capture/compare register 4 low
0x00
0x00 526D
TIM1_BKR
TIM1 break register
0x00
0x00 526E
TIM1_DTR
TIM1 dead-time register
0x00
0x00 526F
TIM1_OISR
TIM1 output idle state register
0x00
Address
Block
0x00 5266
0x00 5267
TIM1
cont’d
0x00 5270
to
0x00 52FF
Reserved area (147 bytes)
0x00 5300
TIM2_CR1
TIM2 control register 1
0x00 5301
Reserved
0x00 5302
Reserved
0x00
0x00 5303
TIM2_IER
TIM2 Interrupt enable register
0x00
0x00 5304
TIM2_SR1
TIM2 status register 1
0x00
0x00 5305
TIM2_SR2
TIM2 status register 2
0x00
TIM2_EGR
TIM2 event generation register
0x00
0x00 5307
TIM2_CCMR1
TIM2 capture/compare mode register
1
0x00
0x00 5308
TIM2_CCMR2
TIM2 capture/compare mode register
2
0x00
0x00 5309
TIM2_CCMR3
TIM2 capture/compare mode register
3
0x00
0x00 530A
TIM2_CCER1
TIM2 capture/compare enable register
1
0x00
0x00 5306
TIM2
Doc ID 15441 Rev 2
41/95
Memory and register map
Table 14.
STM8S103x
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 530B
TIM2_CCER2
TIM2 capture/compare enable register
2
0x00
00 530C0x
TIM2_CNTRH
TIM2 counter high
0x00
0x00 530D
TIM2_CNTRL
TIM2 counter low
0x00
0x00 530E
TIM2_PSCR
TIM2 prescaler register
0x00
TIM2_ARRH
TIM2 auto-reload register high
0xFF
TIM2_ARRL
TIM2 auto-reload register low
0xFF
0x00 5311
TIM2_CCR1H
TIM2 capture/compare register 1 high
0x00
0x00 5312
TIM2_CCR1L
TIM2 capture/compare register 1 low
0x00
0x00 5313
TIM2_CCR2H
TIM2 capture/compare reg. 2 high
0x00
0x00 5314
TIM2_CCR2L
TIM2 capture/compare register 2 low
0x00
0x00 5315
TIM2_CCR3H
TIM2 capture/compare register 3 high
0x00
0x00 5316
TIM2_CCR3L
TIM2 capture/compare register 3 low
0x00
Address
Block
0x00 530F
0x00 5310
TIM2
cont’d
0x00 5317
to
0x00 533F
Reserved area (43 bytes)
0x00 5340
TIM4_CR1
0x00 5341
Reserved
0x00 5342
Reserved
0x00 5343
0x00
TIM4_IER
TIM4 interrupt enable register
0x00
TIM4_SR
TIM4 status register
0x00
0x00 5345
TIM4_EGR
TIM4 event generation register
0x00
0x00 5346
TIM4_CNTR
TIM4 counter
0x00
0x00 5347
TIM4_PSCR
TIM4 prescaler register
0x00
0x00 5348
TIM4_ARR
TIM4 auto-reload register
0xFF
0x00 5344
TIM4
0x00 5349
to
0x00 53DF
0x00 53E0
to
0x00 53F3
0x00 53F4
to
0x00 53FF
42/95
TIM4 control register 1
Reserved area (153 bytes)
ADC1
ADC _DBxR
ADC data buffer registers
Reserved area (12 bytes)
Doc ID 15441 Rev 2
0x00
STM8S103x
Memory and register map
Table 14.
General hardware register map (continued)
Register label
Register name
Reset
status
0x00 5400
ADC _CSR
ADC control/status register
0x00
0x00 5401
ADC_CR1
ADC configuration register 1
0x00
0x00 5402
ADC_CR2
ADC configuration register 2
0x00
0x00 5403
ADC_CR3
ADC configuration register 3
0x00
0x00 5404
ADC_DRH
ADC data register high
0x00
0x00 5405
ADC_DRL
ADC data register low
0x00
0x00 5406
ADC_TDRH
ADC Schmitt trigger disable register
high
0x00
0x00 5407
ADC_TDRL
ADC Schmitt trigger disable register
low
0x00
ADC_HTRH
ADC high threshold register high
0x03
0x00 5409
ADC_HTRL
ADC high threshold register low
0xFF
0x00 540A
ADC_LTRH
ADC low threshold register high
0x00
0x00 540B
ADC_LTRL
ADC low threshold register low
0x00
0x00 540C
ADC_AWSRH
ADC analog watchdog status register
high
0x00
0x00 540D
ADC_AWSRL
ADC analog watchdog status register
low
0x00
0x00 540E
ADC _AWCRH
ADC analog watchdog control register
high
0x00
0x00 540F
ADC_AWCRL
ADC analog watchdog control register
low
0x00
Address
0x00 5408
0x00 5410 to 0x00
57FF
Block
ADC1
Reserved area (1008 bytes)
Doc ID 15441 Rev 2
43/95
Memory and register map
Table 15.
STM8S103x
CPU/SWIM/debug module/interrupt controller registers
Register label
Register name
Reset
status
0x00 7F00
A
Accumulator
0x00
0x00 7F01
PCE
Program counter extended
0x00
0x00 7F02
PCH
Program counter high
0x00
0x00 7F03
PCL
Program counter low
0x00
XH
X index register high
0x00
XL
X index register low
0x00
0x00 7F06
YH
Y index register high
0x00
0x00 7F07
YL
Y index register low
0x00
0x00 7F08
SPH
Stack pointer high
0x03
0x00 7F09
SPL
Stack pointer low
0xFF
0x00 7F0A
CCR
Condition code register
0x28
Address
Block
0x00 7F04
0x00 7F05
CPU
(1)
0x00 7F0B to
0x00 7F5F
0x00 7F60
Reserved area (85 bytes)
CPU
CFG_GCR
Global configuration register
0x00
0x00 7F70
ITC_SPR1
Interrupt Software priority register 1
0xFF
0x00 7F71
ITC_SPR2
Interrupt Software priority register 2
0xFF
0x00 7F72
ITC_SPR3
Interrupt Software priority register 3
0xFF
ITC_SPR4
Interrupt Software priority register 4
0xFF
0x00 7F74
ITC_SPR5
Interrupt Software priority register 5
0xFF
0x00 7F75
ITC_SPR6
Interrupt Software priority register 6
0xFF
0x00 7F76
ITC_SPR7
Interrupt Software priority register 7
0xFF
0x00 7F77
ITC_SPR8
Interrupt Software priority register 8
0xFF
0x00 7F73
ITC
0x00 7F78
to
0x00 7F79
0x00 7F80
0x00 7F81
to
0x00 7F8F
44/95
Reserved area (2 bytes)
SWIM
SWIM_CSR
SWIM control status register
Reserved area (15 bytes)
Doc ID 15441 Rev 2
0x00
STM8S103x
Table 15.
Memory and register map
CPU/SWIM/debug module/interrupt controller registers (continued)
Register label
Register name
Reset
status
0x00 7F90
DM_BK1RE
DM Breakpoint 1 register extended byte
0xFF
0x00 7F91
DM_BK1RH
DM Breakpoint 1 register high byte
0xFF
0x00 7F92
DM_BK1RL
DM Breakpoint 1 register low byte
0xFF
0x00 7F93
DM_BK2RE
DM Breakpoint 2 register extended byte
0xFF
0x00 7F94
DM_BK2RH
DM Breakpoint 2 register high byte
0xFF
DM_BK2RL
DM Breakpoint 2 register low byte
0xFF
0x00 7F96
DM_CR1
DM Debug module control register 1
0x00
0x00 7F97
DM_CR2
DM Debug module control register 2
0x00
0x00 7F98
DM_CSR1
DM Debug module control/status register 1
0x10
0x00 7F99
DM_CSR2
DM Debug module control/status register 2
0x00
0x00 7F9A
DM_ENFCTR
DM Enable function register
0xFF
Address
0x00 7F95
Block
DM
0x00 7F9B
to
0x00 7F9F
Reserved area (5 bytes)
1. Accessible by debug module only
Doc ID 15441 Rev 2
45/95
Electrical characteristics
STM8S103x
9
Electrical characteristics
9.1
Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
9.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100 % of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ± 3 Σ).
9.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 5 V. They are given
only as design guidelines and are not tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ± 2 Σ).
9.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
9.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7.
Figure 7.
Pin loading conditions
STM8 PIN
50 pF
46/95
Doc ID 15441 Rev 2
STM8S103x
9.1.5
Electrical characteristics
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
Figure 8.
Pin input voltage
STM8 PIN
VIN
9.2
Absolute maximum ratings
Stresses above those listed as ‘absolute maximum ratings’ may cause permanent damage
to the device. This is a stress rating only and functional operation of the device under these
conditions is not implied. Exposure to maximum rating conditions for extended periods may
affect device reliability.
Table 16.
Voltage characteristics
Symbol
VDDx - VSS
Ratings
Supply voltage (1)
Input voltage on true open drain
VIN
Input voltage on any other
pins(2)
pin(2)
Min
Max
-0.3
6.5
VSS - 0.3
6.5
VSS - 0.3
VDD + 0.3
|VDDx - VDD| Variations between different power pins
50
|VSSx - VSS| Variations between all the different ground pins
50
VESD
Electrostatic discharge voltage
Unit
V
mV
see Absolute maximum
ratings (electrical
sensitivity) on page 81
1. All power (VDD) and ground (VSS) pins must always be connected to the external power supply
2. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
Doc ID 15441 Rev 2
47/95
Electrical characteristics
Table 17.
STM8S103x
Current characteristics
Symbol
Max.(1)
Ratings
IVDD
Total current into VDD power lines (source)(2)
IVSS
(2)
IIO
Unit
100
Total current out of VSS ground lines (sink)
80
Output current sunk by any I/O and control pin
20
Output current source by any I/Os and control pin
- 20
Injected current on NRST pin
±4
mA
IINJ(PIN)(3)(4)
Injected current on OSCIN pin
±4
(5)
ΣIINJ(PIN)(3)
Injected current on any other pin
±4
Total injected current (sum of all I/O and control pins)(5)
± 20
1. Data based on characterization results, not tested in production.
2. All power (VDD) and ground (VSS) pins must always be connected to the external supply.
3. IINJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
cannot be respected, the injection current must be limited externally to the IINJ(PIN) value. A positive
injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. For true open-drain pads,
there is no positive injection current, and the corresponding VIN maximum must always be respected
4. Negative injection disturbs the analog performance of the device. See note in Section 9.3.10: 10-bit ADC
characteristics on page 77.
5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values). These results are based on
characterization with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device.
Table 18.
48/95
Thermal characteristics
Symbol
Ratings
Value
TSTG
Storage temperature range
-65 to +150
TJ
Maximum junction temperature
150
Unit
°C
Doc ID 15441 Rev 2
STM8S103x
9.3
Electrical characteristics
Operating conditions
Table 19.
General operating conditions
Symbol
Parameter
Conditions
fCPU
Internal CPU clock frequency
VDD/
Standard operating voltage
CEXT
VCAP external capacitor(1)
Power dissipation at
TA= 85° C for suffix 6
Power dissipation at
TA= 125° C for suffix 3
TJ
Max
Unit
0
16
MHz
2.95
5.5
V
470
1000
nF
LQFP32
330
VFQFN32
550
TSSOP20
240
WFQFN20
220
LQFP32
83
VFQFN32
110
TSSOP20
59
WFQFN20
55
mW
PD
TA
0.05 ≤ ESR ≤ 0.2 Ω at
1 MHz
Min
Ambient temperature for 6
suffix version
Maximum power dissipation
-40
85
Ambient temperature for 3
suffix version
Maximum power dissipation
-40
125
6 suffix version
-40
105
3 suffix version
-40
130
°C
Junction temperature range
1. Care should be taken when selecting the capacitor, due to its tolerance, as well as its dependency on
temperature, DC bias and frequency in addition to other factors
Figure 9.
fCPUmax versus VDD
fCPU [MHz]
FUNCTIONALITY
NOT GUARANTEED
IN THIS AREA
16
FUNCTIONALITY
GUARANTEED
@ TA -40 to 125 ¬
12
8
4
0
2.95
4.0
5.0
5.5
SUPPLY VOLTAGE [V]
Doc ID 15441 Rev 2
49/95
Electrical characteristics
Table 20.
Symbol
tVDD
STM8S103x
Operating conditions at power-up/power-down
Parameter
Conditions
VDD rise time rate
(1)
VDD fall time rate
tTEMP
Reset release
delay
VIT+
Power-on reset
threshold
VIT-
Brown-out reset
threshold
VHYS(BOR)
Brown-out reset
hysteresis
Min
Typ
Max
2
∞
2
∞
VDD rising
1.7
2.6
2.7
Unit
µs/V
ms
2.85
V
2.5
2.65
2.8
70
mV
1. Reset is always generated after a tTEMP delay. The application must ensure that VDD is still above the
minimum ooperating voltage (VDD min) when the tTEMP delay has elapsed.
9.3.1
VCAP external capacitor
Stabilization for the main regulator is achieved connecting an external capacitor CEXT to the
VCAP pin. CEXT is specified in Table 19. Care should be taken to limit the series inductance
to less than 15 nH.
Figure 10. External capacitor CEXT
ESR
C
Where:
ESR is the equivalent series resistance
Rleak
ESL is the equivalent inductance
50/95
Doc ID 15441 Rev 2
ESL
STM8S103x
9.3.2
Electrical characteristics
Supply current characteristics
The current consumption is measured as described in Figure 8 on page 47.
Total current consumption in run mode
The MCU is placed under the following conditions:
●
All I/O pins in input mode with a static value at VDD or VSS (no load)
●
All peripherals are disabled (clock stopped by peripheral clock gating registers) except
if explicitly mentioned.
Subject to general operating conditions for VDD and TA.
Table 21.
Symbol
Total current consumption with code execution in run mode at VDD = 5 V
Parameter
Conditions
HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
HSE user ext. clock (16 MHz)
Supply
current in run f
CPU = fMASTER/128 =
mode, code
125 kHz
executed from
RAM
fCPU = fMASTER/128 =
15.625 kHz
fCPU = fMASTER =
128 kHz
IDD(RUN)
fCPU = fMASTER =
16 MHz
Supply
fCPU = fMASTER =
current in run 2 MHz
mode, code
=f
/128 =
f
executed from CPU MASTER
125 kHz
Flash
fCPU = fMASTER/128 =
15.625 kHz
fCPU = fMASTER =
128 kHz
Typ
Max(1)
Unit
2.3
2
2.35
HSI RC osc. (16 MHz)
1.7
2
HSE user ext. clock (16 MHz)
0.86
HSI RC osc. (16 MHz)
0.7
0.87
HSI RC osc. (16 MHz/8)
0.46
0.58
LSI RC osc. (128 kHz)
0.41
0.55
HSE crystal osc. (16 MHz)
4.5
HSE user ext. clock (16 MHz)
4.3
4.75
HSI RC osc. (16 MHz)
3.7
4.5
HSI RC osc. (16 MHz/8)(2)
0.84
1.05
HSI RC osc. (16 MHz)
0.72
0.9
HSI RC osc. (16 MHz/8)
0.46
0.58
LSI RC osc. (128 kHz)
0.42
0.57
mA
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Doc ID 15441 Rev 2
51/95
Electrical characteristics
Table 22.
Symbol
STM8S103x
Total current consumption with code execution in run mode at VDD = 3.3 V
Parameter
Conditions
HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
HSE user ext. clock (16 MHz)
HSI RC osc. (16 MHz)
Supply
current in run f
HSE user ext. clock (16 MHz)
CPU = fMASTER/128 = 125
mode, code
kHz
HSI RC osc. (16 MHz)
executed
from RAM
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)
15.625 kHz
fCPU = fMASTER =
128 kHz
IDD(RUN)
LSI RC osc. (128 kHz)
HSE crystal osc. (16 MHz)
fCPU = fMASTER =
16 MHz
2
2.3
1.5
2
0.81
0.7
0.87
0.46
0.58
0.41
0.55
4
mA
4.7
HSI RC osc. (16 MHz)
3.7
4.5
0.84
1.05
0.72
0.9
0.46
0.58
0.42
0.57
LSI RC osc. (128 kHz)
2. Default clock configuration measured with all peripherals off.
Doc ID 15441 Rev 2
Unit
1.8
3.9
1. Data based on characterization results, not tested in production.
52/95
Max(1)
HSE user ext. clock (16 MHz)
fCPU = fMASTER =
Supply
HSI RC osc. (16 MHz/8)(2)
current in run 2 MHz
mode, code
fCPU = fMASTER/128 = 125
executed
HSI RC osc. (16 MHz)
kHz
from Flash
fCPU = fMASTER/128 =
HSI RC osc. (16 MHz/8)
15.625 kHz
fCPU = fMASTER =
128 kHz
Typ
STM8S103x
Electrical characteristics
Total current consumption in wait mode
Table 23.
Symbol
Total current consumption in wait mode at VDD = 5 V
Parameter
Conditions
Max(1)
HSE crystal osc. (16 MHz)
1.6
HSE user ext. clock (16 MHz)
1.1
1.3
HSI RC osc. (16 MHz)
0.89
1.1
fCPU = fMASTER/128 =
125 kHz
HSI RC osc. (16 MHz)
0.7
0.88
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
0.45
0.57
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.4
0.54
Typ
Max (1)
fCPU = fMASTER =
16 MHz
Supply
IDD(WFI) current in
wait mode
Typ
Unit
mA
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Table 24.
Symbol
Total current consumption in wait mode at VDD = 3.3 V
Parameter
Conditions
HSE crystal osc. (16 MHz)
1.1
HSE user ext. clock (16 MHz)
1.1
1.3
HSI RC osc. (16 MHz)
0.89
1.1
fCPU = fMASTER/128 =
125 kHz
HSI RC osc. (16 MHz)
0.7
0.88
fCPU = fMASTER/128 =
15.625 kHz
HSI RC osc. (16 MHz/8)(2)
0.45
0.57
fCPU = fMASTER =
128 kHz
LSI RC osc. (128 kHz)
0.4
0.54
fCPU = fMASTER =
16 MHz
Supply
IDD(WFI) current in
wait mode
Unit
mA
1. Data based on characterization results, not tested in production.
2. Default clock configuration measured with all peripherals off.
Doc ID 15441 Rev 2
53/95
Electrical characteristics
STM8S103x
Total current consumption in active halt mode
Table 25.
Total current consumption in active halt mode at VDD = 5 V
Conditions
Symbol
Parameter
Main voltage
regulator
(MVR)(2)
Flash
mode(3)
Operating
mode
Clock
source
Typ
HSE crystal osc.
(16 MHz)
1030
LSI RC osc.
(128 kHz)
200
Max at
85 °C(1)
Max at
125 °C(1)
260
300
Unit
On
IDD(AH)
HSE crystal osc.
Power-down (16 MHz)
mode
LSI RC osc.
Supply
current in
active halt
mode
(128 kHz)
Operating
mode
Off
LSI RC osc.
Power-down (128 kHz)
mode
970
µA
150
200
230
66
85
110
10
20
40
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
Table 26.
Total current consumption in active halt mode at VDD = 3.3 V
Conditions
Symbol
Parameter
Main voltage
regulator
(MVR)(2)
Flash
mode(3)
Operating
mode
Clock
source
Typ
HSE crystal osc.
(16 MHz)
550
LSI RC osc.
(128 kHz)
200
HSE crystal osc.
(16 MHz)
970
LSI RC osc.
(128 kHz)
Max at
Max at
85 °C(1) 125 °C(1)
260
290
150
200
230
66
80
105
10
18
35
Unit
On
IDD(AH)
Supply
current in
active halt
mode
Power-down
mode
Operating
mode
Off
Power-down
mode
µA
LSI RC osc.
(128 kHz)
1. Data based on characterization results, not tested in production
2. Configured by the REGAH bit in the CLK_ICKR register.
3. Configured by the AHALT bit in the FLASH_CR1 register.
54/95
Doc ID 15441 Rev 2
STM8S103x
Electrical characteristics
Total current consumption in halt mode
Table 27.
Symbol
IDD(H)
Total current consumption in halt mode at VDD = 5 V
Parameter
Conditions
Typ
Flash in operating mode, HSI clock after wakeup
Supply current in
Flash in power-down mode, HSI clock after
halt mode
wakeup
Max at Max at
Unit
85 °C(1) 125 °C(1)
63
75
105
6.0
15
35
µA
1. Data based on characterization results, not tested in production
Table 28.
Total current consumption in halt mode at VDD = 3.3 V
Symbol
Parameter
IDD(H)
Supply current in
halt mode
Conditions
Typ
Max at Max at
Unit
85 °C(1) 125 °C(1)
Flash in operating mode, HSI clock after wakeup
60
75
100
Flash in power-down mode, HSI clock after wakeup
4.5
12
30
µA
1. Data based on characterization results, not tested in production
Low power mode wakeup times
Table 29.
Wakeup times
Symbol
Parameter
tWU(WFI)
Wakeup time from wait
mode to run mode(3)
Conditions
Typ
0.56
Flash in operating
mode(5)
Wakeup time active halt
mode to run mode(3)
MVR Voltage
regulator ON(4) Flash in
powerdown
mode(5)
Flash in operating
mode(5)
MVR Voltage
regulator OFF(4) Flash in
powerdown
mode(5)
tWU(H)
Wakeup time from halt
mode to run mode(3)
Unit
See
note(2)
fCPU = fMASTER = 16 MHz.
tWU(AH)
Max(1)
1(6)
2(6)
3(6)
HSI (after
wakeup)
µs
48(6)
50(6)
Flash in operating mode(5)
52
Flash in powerdown mode(5)
54
1. Data guaranteed by design, not tested in production.
2. tWU(WFI) = 2 x 1/fmaster + 6 x 1/fCPU.
3. Measured from interrupt event to interrupt vector fetch.
4. Configured by the REGAH bit in the CLK_ICKR register.
5. Configured by the AHALT bit in the FLASH_CR1 register.
6. Plus 1 LSI clock depending on synchronization.
Doc ID 15441 Rev 2
55/95
Electrical characteristics
STM8S103x
Total current consumption and timing in forced reset state
Table 30.
Total current consumption and timing in forced reset state
Symbol
Parameter
IDD(R)
Supply current in reset state(2)
tRESETBL
Reset pin release to vector fetch
Conditions
Max(1)
Typ
VDD = 5 V
400
VDD = 3.3 V
300
Unit
µA
150
µs
1. Data guaranteed by design, not tested in production.
2. Characterized with all I/Os tied to VSS.
Current consumption of on-chip peripherals
Subject to general operating conditions for VDD and TA.
HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V
Table 31.
Peripheral current consumption
Symbol
Parameter
Typ.
IDD(TIM1)
TIM1 supply current(1)
210
IDD(TIM2)
TIM2 supply current(1)
130
IDD(TIM4)
TIM4 timer supply current(1)
50
IDD(UART1)
UART1 supply
current(2)
120
IDD(SPI)
SPI supply
current(2)
45
IDD(I2C)
I2C supply current(2)
65
IDD(ADC1)
ADC1 supply current when converting(3)
Unit
µA
1000
1. Data based on a differential IDD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral when kept under reset and
not clocked and the on-chip peripheral when clocked and not kept under reset. No I/O pads toggling. Not
tested in production.
3. Data based on a differential IDD measurement between reset configuration and continuous A/D
conversions. Not tested in production.
56/95
Doc ID 15441 Rev 2
STM8S103x
Electrical characteristics
Current consumption curves
Figure 11 to Figure 16 show typical current consumption measured with code executing in
RAM.
Figure 11. Typ IDD(RUN) vs. VDD HSE user external clock, fCPU = 16 MHz
25˚C
85˚C
125˚C
-45˚C
2.3
2.25
2.2
IDD run HSE (mA)
2.15
2.1
2.05
TBD
2
1.95
1.9
1.85
1.8
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Figure 12. Typ IDD(RUN) vs. fCPU HSE user external clock, VDD = 5 V
25˚C
85˚C
125˚C
-45˚C
2.5
IDD_run_HSE (mA)
2
1.5
TBD
1
0.5
0
2
4
6
8
10
12
14
16
18
Fext (MHz)
Doc ID 15441 Rev 2
57/95
Electrical characteristics
STM8S103x
Figure 13. Typ IDD(RUN) vs. VDD HSI RC osc, fCPU = 16 MHz
25˚C
85˚C
125˚C
-45˚C
2
1.95
IDD run HSI 16MHz (mA)
1.9
1.85
1.8
1.75
TBD
1.7
1.65
1.6
1.55
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Figure 14. Typ IDD(WFI) vs. VDD HSE user external clock, fCPU = 16 MHz
25˚C
85˚C
125˚C
-45˚C
1.8
1.6
IDD WFI HSE (mA)
1.4
1.2
1
TBD
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Figure 15. Typ IDD(WFI) vs. fCPU HSE user external clock, VDD = 5 V
25˚C
85˚C
125˚C
-45˚C
1.8
1.6
IDD_WFI_HSE (mA)
1.4
1.2
1
TBD
0.8
0.6
0.4
0.2
0
2
4
6
8
10
Fext (MHz)
58/95
Doc ID 15441 Rev 2
12
14
16
18
STM8S103x
Electrical characteristics
Figure 16. Typ IDD(WFI) vs. VDD HSI RC osc, fCPU = 16 MHz
25˚C
85˚C
125˚C
-45˚C
1.8
1.6
IDD_WFI_HSE (mA)
1.4
1.2
1
TBD
0.8
0.6
0.4
0.2
0
2
2.5
3
3.5
4
4.5
5
5.5
6
Fext (MHz)
Doc ID 15441 Rev 2
59/95
Electrical characteristics
9.3.3
STM8S103x
External clock sources and timing characteristics
HSE user external clock
Subject to general operating conditions for VDD and TA.
Table 32.
HSE user external clock characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
MHz
fHSE_ext
User external clock source
frequency
0
16
VHSEH(1)
OSCIN input pin high level
voltage
0.7 x VDD
VDD + 0.3 V
V
VHSEL
OSCIN input pin low level
voltage
(1)
ILEAK_HSE
OSCIN input leakage current
VSS < VIN < VDD
VSS
0.3 x VDD
-1
+1
µA
1. Data based on characterization results, not tested in production.
Figure 17. HSE external clock source
VHSEH
VHSEL
fHSE
External clock
source
OSCIN
STM8
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and start-up stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
60/95
Doc ID 15441 Rev 2
STM8S103x
Table 33.
Electrical characteristics
HSE oscillator characteristics
Symbol
Conditions
External high speed oscillator
frequency
fHSE
Min
C(1)
gm
Unit
16
MHz
kΩ
(2)
20
pF
C = 20 pF,
fOSC = 16 MHz
6 (startup)
1.6
(stabilized)(3)
C = 10 pF,
fOSC =16 MHz
6 (startup)
1.2
(stabilized)(3)
HSE oscillator power consumption
mA
Oscillator transconductance
(4)
Max
220
Recommended load capacitance
IDD(HSE)
Typ
1
Feedback resistor
RF
tSU(HSE)
Parameter
5
Startup time
mA/V
VDD is stabilized
1
ms
1. C is approximately equivalent to 2 x crystal Cload.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Data based on characterization results, not tested in production.
4.
tSU(HSE) is the start-up time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
Figure 18. HSE oscillator circuit diagram
fHSE to core
Rm
Lm
RF
CO
CL1
OSCIN
Cm
gm
Resonator
Consumption
control
Resonator
STM8
OSCOUT
CL2
HSE oscillator critical gm formula
f
2
g mcrit = ( 2 × Π × HSE ) × R m ( 2Co + C )
2
Rm: Notional resistance (see crystal specification)
Lm: Notional inductance (see crystal specification)
Cm: Notional capacitance (see crystal specification)
Co: Shunt capacitance (see crystal specification)
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
Doc ID 15441 Rev 2
61/95
Electrical characteristics
9.3.4
STM8S103x
Internal clock sources and timing characteristics
Subject to general operating conditions for VDD and TA.
High speed internal RC oscillator (HSI)
Table 34.
Symbol
fHSI
HSI oscillator characteristics
Parameter
Conditions
Min
Frequency
Typ
Max
16
Accuracy of HSI oscillator
ACCHSI
Accuracy of HSI oscillator
(factory calibrated)
User-trimmed with
CLK_HSITRIMR register
for given VDD and TA
conditions(1)
HSI oscillator wakeup time
including calibration
IDD(HSI)
HSI oscillator power
consumption
MHz
1(4)
%
VDD = 5 V, TA = 25°C(2)
-2.5(3)
1.3(3)
%
VDD = 5 V,
25 °C ≤TA ≤85 °C
-2.5(3)
2(3)
%
4.5(2)(3)
3(2)(3)
%
1(4)
µs
250(2)
µA
2.95 ≤ VDD ≤ 5.5 V,
-40 °C ≤TA ≤125 °C
tsu(HSI)
170
1. Refer to application note.
2. Data based on characterization results, not tested in production
3. Subject to further characterization to give better results
4. Guaranteeed by design, not tested in production.
Figure 19. Typical HSI frequency variation at VDD = 5 V vs 5 temperatures
3.00%
2.00%
1.00%
0.00%
max
-1.00%
TBD
min
-2.00%
-3.00%
-4.00%
-5.00%
-40
62/95
Unit
0
25
Doc ID 15441 Rev 2
85
125
STM8S103x
Electrical characteristics
Figure 20. Typical HSI frequency variation vs VDD @ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
1.00%
RC16M check div8 (MHz)
0.50%
0.00%
TBD
-0.50%
-1.00%
-1.50%
-2.00%
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Low speed internal RC oscillator (LSI)
Subject to general operating conditions for VDD and TA.
Table 35.
LSI oscillator characteristics
Symbol
fLSI
Parameter
Conditions
Frequency
tsu(LSI)
LSI oscillator wake-up time
IDD(LSI)
LSI oscillator power consumption
Min
Typ
Max
Unit
110
128
150
kHz
7
µs
5
µA
Figure 21. Typical LSI frequency variation vs VDD @ 4 temperatures
25˚C
85˚C
125˚C
-45˚C
5.00%
4.00%
RC16M check div8 (MHz)
3.00%
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
-4.00%
-5.00%
2
2.5
3
3.5
4
4.5
5
5.5
6
VDD (V)
Doc ID 15441 Rev 2
63/95
Electrical characteristics
9.3.5
STM8S103x
Memory characteristics
RAM and hardware registers
Table 36.
RAM and hardware registers
Symbol
Parameter
Conditions
Min
VRM
Data retention mode(1)
Halt mode (or reset)
2.8 V(2)
Typ
Max
Unit
V
1. Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design, not tested in production.
2. Refer to Table 20 on page 50 for the value of VIT-max
Flash program memory/data EEPROM memory
Table 37.
Symbol
VDD
tprog
terase
NRW
Flash program memory/data EEPROM memory
Parameter
Operating voltage
(all modes, execution/write/erase)
IDD
fCPU ≤ 16 MHz
Min(1) Typ
2.95
Max
Unit
5.5
V
Standard programming time
(including erase) for byte/word/block
(1 byte/4 bytes/64 bytes)
6
6.6
Fast programming time for 1 block (64
bytes)
3
3.33
Erase time for 1 block (64 bytes)
3
3.33
ms
Erase/write cycles(2)
(program memory)
TA = +85 °C
10 k
TA = +125 °C
300 k
Data retention (program and data
memory) after 10k erase/write cycles
at TA = +55 °C
TRET = 55°C
20
Data retention (data memory) after
300k erase/write cycles
at TA = +125 °C
TRET=85°C
Erase/write cycles (data
tRET
Conditions
memory)(2)
cycles
1M
years
Supply current (Flash programming or
erasing for 1 to 128 bytes)
1
2
1. Data based on characterization results, not tested in production.
2. The physical granularity of the memory is 4 bytes, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
64/95
Doc ID 15441 Rev 2
mA
STM8S103x
9.3.6
Electrical characteristics
I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 38.
Symbol
I/O static characteristics
Parameter
VIL
Input low level
voltage
VIH
Input high level
voltage
Vhys
Hysteresis(1)
Rpu
Pull-up resistor
tR, tF
Rise and fall time
(10% - 90%)
Ilkg
Conditions
VDD = 5 V
Min
Typ
Max
Unit
-0.3 V
0.3 x VDD
V
0.7 x VDD
VDD + 0.3 V
V
700
VDD = 5 V, VIN = VSS
60
kΩ
Fast I/Os
Load = 50 pF
20
ns
Standard and high sink I/Os
Load = 50 pF
125
ns
±1
µA
Digital input leakage
VSS ≤ VIN ≤ VDD
current
Ilkg ana
Analog input
leakage current
VSS ≤ VIN ≤ VDD
Ilkg(inj)
Leakage current in
adjacent I/O
Injection current ±4 mA
30
45
mV
±250
±1
1. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested in production.
Doc ID 15441 Rev 2
65/95
Electrical characteristics
STM8S103x
Figure 22. Typical VIL and VIH vs VDD @ 4 temperatures
-40˚C
6
25˚C
85˚C
5
VIL / VIH [V]
125˚C
4
TBD
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 23. Typical pull-up resistance vs VDD @ 4 temperatures
-40˚C
25˚C
60
85˚C
Pull-up resistance [kΩ]
55
125˚C
50
TBD
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 24. Typical pull-up current vs VDD @ 4 temperatures
140
Pull-up current [µA]
120
100
80
Alain to send
60
-40˚C
25˚C
40
85˚C
125˚C
20
0
0
1
2
3
VDD [V]
66/95
Doc ID 15441 Rev 2
4
5
6
STM8S103x
Table 39.
Symbol
VOL
VOH
Electrical characteristics
Output driving current (standard ports)
Parameter
Conditions
Min
Output low level with 4 pins sunk
IIO = 4 mA, VDD = 3.3 V
Output low level with 8 pins sunk
IIO= 10 mA, VDD = 5 V
Output high level with 4 pins sourced
IIO = 4 mA, VDD = 3.3 V
Output high level with 8 pins sourced
IIO = 10 mA, VDD = 5 V
Max
Unit
1(1)
2
V
(1)
2.1
2.8
1. Data based on characterization results, not tested in production
Table 40.
Symbol
Output driving current (true open drain ports)
Parameter
Conditions
Min
Max
1.5(1)
IIO = 10 mA, VDD = 3.3 V
VOL
Output low level with 2 pins sunk
Unit
IIO = 10 mA, VDD = 5 V
1
IIO = 20 mA, VDD = 5 V
2(1)
V
1. Data based on characterization results, not tested in production
Table 41.
Symbol
VOL
VOH
Output driving current (high sink ports)
Parameter
Conditions
Min
Max
Output low level with 4 pins sunk
IIO = 10 mA, VDD = 3.3 V
1(1)
Output low level with 8 pins sunk
IIO = 10 mA, VDD = 5 V
0.8
Output low level with 4 pins sunk
IIO = 20 mA, VDD = 5 V
1.5(1)
Output high level with 4 pins sourced
IIO = 10 mA, VDD = 3.3 V
Output high level with 8 pins sourced
IIO = 10 mA, VDD = 5 V
4.0
Output high level with 4 pins sourced
IIO = 20 mA, VDD = 5 V
3.3(1)
Unit
V
2.1(1)
1. Data based on characterization results, not tested in production
Figure 25. Typ. VOL @ VDD = 3.3 V (standard ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
TBD
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
IOL [mA]
Doc ID 15441 Rev 2
67/95
Electrical characteristics
STM8S103x
Figure 26. Typ. VOL @ VDD = 5 V (standard ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL [V]
1
TBD
0.75
0.5
0.25
0
0
2
4
6
8
10
12
IOL [mA]
Figure 27. Typ. VOL @ VDD = 3.3 V (true open drain ports)
-40˚C
2
25˚C
1.75
85˚C
1.5
125˚C
VOL[V]
1.25
1
Alain
to send
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
IOL [mA]
Figure 28. Typ. VOL @ VDD = 5 V (true open drain ports)
-40˚C
2
25˚C
1.75
85˚C
1.5
125˚C
VOL[V]
1.25
TBD
1
0.75
0.5
0.25
0
0
5
10
15
IOL [mA]
68/95
Doc ID 15441 Rev 2
20
25
STM8S103x
Electrical characteristics
Figure 29. Typ. VOL @ VDD = 3.3 V (high sink ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL[V]
1
TBD
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
IOL [mA]
Figure 30. Typ. VOL @ VDD = 5 V (high sink ports)
-40˚C
1.5
25˚C
85˚C
1.25
125˚C
VOL[V]
1
Alain to send
0.75
0.5
0.25
0
0
5
10
15
20
25
IOL [mA]
Figure 31. Typ. VDD - VOH @ VDD = 3.3 V (standard ports)
-40˚C
2
VDD - VOH[V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
TBD
1
0.75
0.5
0.25
0
0
1
2
3
4
5
6
7
IOH [mA]
Doc ID 15441 Rev 2
69/95
Electrical characteristics
STM8S103x
Figure 32. Typ. VDD - VOH @ VDD = 5 V (standard ports)
-40˚C
2
VDD - VOH[V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
TBD
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
IOH [mA]
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
-40˚C
2
VDD - VOH[V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
Alain to send
1
0.75
0.5
0.25
0
0
2
4
6
8
10
12
14
IOH [mA]
Figure 34. Typ. VDD - VOH @ VDD = 5 V (high sink ports)
-40˚C
2
VDD - VOH[V]
25˚C
1.75
85˚C
1.5
125˚C
1.25
Alain to send
1
0.75
0.5
0.25
0
0
5
10
15
IOH [mA]
70/95
Doc ID 15441 Rev 2
20
25
STM8S103x
Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified.
Table 42.
Symbol
NRST pin characteristics
Parameter
Conditions
Min
Typ
Max
VIL(NRST)
NRST Input low level voltage (1)
-0.3 V
0.3 x VDD
VIH(NRST)
NRST Input high level voltage (1)
0.7 x
VDD
VDD +
0.3
VOL(NRST)
NRST Output low level voltage (1)
RPU(NRST)
tIFP(NRST)
NRST Pull-up resistor
IOL=2 mA
30
(3)
NRST output pulse
40
(3)
tINFP(NRST) NRST Input not filtered pulse (3)
tOP(NRST)
Unit
V
0.5
(2)
NRST Input filtered pulse
60
kΩ
75
ns
500
ns
20
µs
1. Data based on characterization results, not tested in production.
2. The RPU pull-up equivalent resistor is based on a resistive transistor
3.
Data guaranteed by design, not tested in production.
Figure 35. Typical NRST VIL and VIH vs VDD @ 4 temperatures
-40˚C
6
25˚C
85˚C
5
125˚C
VIL / VIH [V]
4
TBD
3
2
1
0
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Figure 36. Typical NRST pull-up resistance vs VDD @ 4 temperatures
-40˚C
25˚C
60
85˚C
55
NRESET pull-up resistance [kΩ]
9.3.7
Electrical characteristics
125˚C
50
TBD
45
40
35
30
2.5
3
3.5
4
4.5
5
5.5
6
VDD [V]
Doc ID 15441 Rev 2
71/95
Electrical characteristics
STM8S103x
Figure 37. Typical NRST pull-up current vs VDD @ 4 temperatures
140
NRESET Pull-Up current
120
100
80
TBD
60
-40˚C
25˚C
40
85˚C
20
125˚C
0
0
1
2
3
VDD [V]
4
5
6
The reset network shown in Figure 38 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin can go below the VIL max. level specified in
Table 38. Otherwise the reset is not taken into account internally.
Figure 38. Recommended reset pin protection
STM8
VDD
RPU
External
reset
circuit
(optional)
72/95
NRST
0.01¬
Doc ID 15441 Rev 2
Filter
Internal reset
STM8S103x
Electrical characteristics
SPI serial peripheral interface
9.3.8
Unless otherwise specified, the parameters given in Table 43 are derived from tests
performed under ambient temperature, fMASTER frequency and VDD supply voltage
conditions. tMASTER = 1/fMASTER.
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (NSS, SCK, MOSI, MISO).
Table 43.
Symbol
fSCK
1/tc(SCK)
tr(SCK)
tf(SCK)
SPI characteristics
Conditions(1)
Parameter
Min
Max
Master mode
0
8
Slave mode
0
TBD(2)
SPI clock frequency
SPI clock rise and fall time Capacitive load: C = 30 pF
NSS setup time
Slave mode
4*tMASTER
th(NSS)(3)
NSS hold time
Slave mode
70
SCK high and low time
Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz
110
tsu(MI) (3)
tsu(SI)(3)
Data input setup time
th(MI) (3)
th(SI)(3)
Data input hold time
(3)(4)
Master mode
5
Slave mode
5
Master mode
7
Slave mode
10
Data output access time
Slave mode
tdis(SO)(3)(5) Data output disable time
Slave mode
ta(SO)
(3)
Data output valid time
Slave mode (after enable edge)
tv(MO)(3)
Data output valid time
Master mode (after enable edge)
tv(SO)
th(SO)(3)
th(MO)(3)
140
ns
3*tMASTER
25
TBD(2)
30
Slave mode (after enable edge)
TBD(2)
Master mode (after enable edge)
TBD(2)
Data output hold time
MHz
25
tsu(NSS)(3)
tw(SCKH)(3)
tw(SCKL)(3)
Unit
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Data characterization in progress.
3. Values based on design simulation and/or characterization results, and not tested in production.
4. Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data.
5. Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi-Z.
Doc ID 15441 Rev 2
73/95
Electrical characteristics
STM8S103x
Figure 39. SPI timing diagram - slave mode and CPHA = 0
NSS input
SCK Input
tSU(NSS)
CPHA= 0
CPOL=0
tc(SCK)
th(NSS)
tw(SCKH)
tw(SCKL)
CPHA= 0
CPOL=1
tv(SO)
ta(SO)
MISO
OUT P UT
tr(SCK)
tf(SCK)
th(SO)
MS B O UT
BI T6 OUT
tdis(SO)
LSB OUT
tsu(SI)
MOSI
I NPUT
M SB IN
LSB IN
B I T1 IN
th(SI)
ai14134
Figure 40. SPI timing diagram - slave mode and CPHA = 1
NSS input
SCK Input
tSU(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tc(SCK)
tw(SCKH)
tw(SCKL)
tv(SO)
ta(SO)
MISO
OUT P UT
MS B O UT
tsu(SI)
MOSI
I NPUT
th(NSS)
th(SO)
BI T6 OUT
tr(SCK)
tf(SCK)
tdis(SO)
LSB OUT
th(SI)
B I T1 IN
M SB IN
LSB IN
ai14135
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7 VDD.
74/95
Doc ID 15441 Rev 2
STM8S103x
Electrical characteristics
Figure 41. SPI timing diagram - master mode(1)
High
NSS input
SCK Input
SCK Input
tc(SCK)
CPHA= 0
CPOL=0
CPHA= 0
CPOL=1
CPHA=1
CPOL=0
CPHA=1
CPOL=1
tsu(MI)
MISO
INP UT
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
MS BIN
BI T6 IN
LSB IN
th(MI)
MOSI
OUTUT
M SB OUT
B I T1 OUT
tv(MO)
LSB OUT
th(MO)
ai14136
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7 VDD.
Doc ID 15441 Rev 2
75/95
Electrical characteristics
9.3.9
STM8S103x
I2C interface characteristics
Table 44.
I2C characteristics
Standard mode I2C Fast mode I2C(1)
Symbol
Parameter
Min(2)
Max(2)
Min(2)
Max(2)
Unit
tw(SCLL)
SCL clock low time
4.7
1.3
tw(SCLH)
SCL clock high time
4.0
0.6
tsu(SDA)
SDA setup time
250
100
th(SDA)
SDA data hold time
0(3)
0(4)
tr(SDA)
tr(SCL)
SDA and SCL rise time
1000
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
300
300
th(STA)
START condition hold time
4.0
0.6
tsu(STA)
Repeated START condition setup time
4.7
0.6
tsu(STO)
STOP condition setup time
4.0
0.6
µs
STOP to START condition time (bus
free)
4.7
1.3
µs
tw(STO:STA)
Cb
µs
900(3)
µs
Capacitive load for each bus line
1. fMASTER, must be at least 8 MHz to achieve max fast
400
I 2C
400
speed (400kHz)
2. Data based on standard I2C protocol requirement, not tested in production
3. The maximum hold time of the start condition has only to be met if the interface does not stretch the low
time
4. The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
undefined region of the falling edge of SCL
76/95
ns
Doc ID 15441 Rev 2
pF
STM8S103x
9.3.10
Electrical characteristics
10-bit ADC characteristics
Subject to general operating conditions for VDD, fMASTER, and TA unless otherwise specified.
Table 45.
Symbol
fADC
ADC characteristics
Parameter
Conditions
Min
Typ
Max
VDD = 2.95 to 5.5 V
1
4
VDD = 4.5 to 5.5 V
1
6
VSS
VDD
ADC clock frequency
Unit
MHz
VAIN
Conversion voltage range(1)
CADC
Internal sample and hold
capacitor
tS(1)
Minimum sampling time
tSTAB
Wake-up time from standby
tCONV
Minimum total conversion time
(including sampling time, 10-bit
resolution)
3
fADC = 4 MHz
0.75
fADC = 6 MHz
0.5
V
pF
µs
7
µs
fADC = 4 MHz
3.5
µs
fADC = 6 MHz
2.33
µs
14
1/fADC
1. During the sample time the input capacitance CAIN (3 pF max) can be charged/discharged by the external
source. The internal resistance of the analog source must allow the capacitance to reach its final voltage
level within tS. After the end of the sample time tS, changes of the analog input voltage have no effect on
the conversion result. Values for the sample clock tS depend on programming.
Doc ID 15441 Rev 2
77/95
Electrical characteristics
Table 46.
Symbol
|ET|
|EO|
|EG|
|ED|
|EL|
STM8S103x
ADC accuracy with RAIN < 10 kΩ , VDD = 5 V
Parameter
Total unadjusted error
Offset error
(2)
(2)
Gain error (2)
Differential linearity
Integral linearity
error (2)
error (2)
Conditions
Typ
Max(1)
fADC = 2 MHz
1.6
TBD
fADC = 4 MHz
2.2
TBD
fADC = 6 MHz
2.4
TBD
fADC = 2 MHz
1.1
TBD
fADC = 4 MHz
1.5
TBD
fADC = 6 MHz
1.8
TBD
fADC = 2 MHz
1.5
TBD
fADC = 4 MHz
2.1
TBD
fADC = 6 MHz
2.2
TBD
fADC = 2 MHz
0.7
TBD
fADC = 4 MHz
0.7
TBD
fADC = 6 MHz
0.7
TBD
fADC = 2 MHz
0.6
TBD
fADC = 4 MHz
0.8
TBD
fADC = 6 MHz
0.8
TBD
Unit
LSB
1. Data characterization in progress.
2. ADC accuracy vs. negative injection current: Injecting negative current on any of the analog input pins
should be avoided as this significantly reduces the accuracy of the conversion being performed on another
analog input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may
potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
Table 47.
Symbol
ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
Parameter
|ET|
Total unadjusted error(2)
|EO|
Offset error(2)
|EG|
Gain error(2)
|ED|
Differential linearity error(2)
|EL|
Integral linearity error(2)
Conditions
Typ
Max(1)
fADC = 2 MHz
1.6
TBD
fADC = 4 MHz
1.9
TBD
fADC = 2 MHz
1
TBD
fADC = 4 MHz
1.5
TBD
fADC = 2 MHz
1.3
TBD
fADC = 4 MHz
2
TBD
fADC = 2 MHz
0.7
TBD
fADC = 4 MHz
0.7
TBD
fADC = 2 MHz
0.6
TBD
fADC = 4 MHz
0.8
TBD
1. Data characterization in progress.
78/95
Doc ID 15441 Rev 2
Unit
LSB
STM8S103x
Electrical characteristics
Figure 42. ADC accuracy characteristics
EG
1023
1022
1021
1LSB
IDEAL
V
–V
DDA
SSA
= ----------------------------------------1024
(2)
ET
7
(3)
(1)
6
5
EO
4
EL
3
ED
2
1 LSBIDEAL
1
0
1
VSSA
2
3
4
5
6
7
1021102210231024
VDD
1. Example of an actual transfer curve.
2. The ideal transfer curve
3. End point correlation line
ET = Total unadjusted error: maximum deviation between the actual and the ideal transfer curves.
EO = Offset error: deviation between the first actual transition and the first ideal one.
EG = Gain error: deviation between the last ideal transition and the last actual one.
ED = Differential linearity error: maximum deviation between actual steps and the ideal one.
EL = Integral linearity error: maximum deviation between any actual transition and the end point correlation
line.
Figure 43. Typical application with ADC
VDD
STM8
VT
0.6V
RAIN
AINx
VAIN
CAIN
10-bit A/D
conversion
VT
0.6V
Doc ID 15441 Rev 2
IL
¬
CADC
79/95
Electrical characteristics
9.3.11
STM8S103x
EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
While executing a simple application (toggling 2 LEDs through I/O ports), the product is
stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
●
ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms with the IEC 1000-4-2
standard.
●
FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
●
Corrupted program counter
●
Unexpected reset
●
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
recovered by applying a low state on the NRST pin or the oscillator pins for 1 second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Table 48.
Symbol
80/95
EMS data
Parameter
Conditions
Level/class
VFESD
VDD = 3.3 V, TA = +25 °C,
Voltage limits to be applied on any I/O pin
fMASTER = 16 MHz (HSI clock),
to induce a functional disturbance
conforms to IEC 1000-4-2
TBD
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD= 3.3 V, TA = +25 °C,
fMASTER = 16 MHz (HSI clock)
conforms to IEC 1000-4-4
TBD
Doc ID 15441 Rev 2
STM8S103x
Electrical characteristics
Electromagnetic interference (EMI)
Emission tests conform to the SAE J 1752/3 standard for test software, board layout and pin
loading.
Table 49.
EMI data
Conditions
Symbol
Max fHSE/fCPU(1)
Parameter
General conditions
Peak level
SEMI
Monitored
frequency band
16 MHz/
8 MHz
16 MHz/
16 MHz
2
2
10
9
3
4
2.5
2.5
0.1MHz to 30 MHz
VDD = 5 V,
30 MHz to 130 MHz
TA = +25 °C,
LQFP32 package
130 MHz to 1 GHz
conforming to SAE J 1752/3
SAE EMI level
Unit
dBµV
1. Data based on characterization results, not tested in production.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (3 positive then 3 negative pulses separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This test
conforms to the JESD22-A114A/A115A standard. For more details, refer to the application
note AN1181.
Table 50.
Symbol
ESD absolute maximum ratings
Ratings
Conditions
Class
Maximum
Unit
value(1)
VESD(HBM)
Electrostatic discharge voltage
(Human body model)
TA = +25°C, conforming
to JESD22-A114
A
4000
V
VESD(CDM)
Electrostatic discharge voltage
(Charge device model)
TA LQFP32 package =
+25°C, conforming to
SD22-C101
IV
1000
V
1. Data based on characterization results, not tested in production
Doc ID 15441 Rev 2
81/95
Electrical characteristics
STM8S103x
Static latch-up
Two complementary static tests are required on 10 parts to assess the latch-up
performance.
●
A supply overvoltage (applied to each power supply pin) and
●
A current injection (applied to each input, output and configurable I/O pin) are
performed on each sample.
This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the
application note AN1181.
Table 51.
Symbol
LU
Electrical sensitivities
Parameter
Static latch-up class
Conditions
Class(1)
TA = +25 °C
A
TA = +85 °C
A
TA = +125 °C
A
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the
JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
82/95
Doc ID 15441 Rev 2
STM8S103x
10
Package characteristics
Package characteristics
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
Doc ID 15441 Rev 2
83/95
Package characteristics
STM8S103x
10.1
Package mechanical data
10.1.1
LQFP package mechanical data
Figure 44. 32-pin low profile quad flat package (7 x 7)
ccc C
D
D1
D3
24
A
A2
17
16
25
L1
b
E3
32
Pin 1
identification
E1 E
9
L
A1
1
K
c
8
5V_ME
Table 52.
32-pin low profile quad flat package mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.600
A1
0.050
A2
1.350
b
0.300
c
0.090
D
8.800
D1
6.800
D3
Max
0.0630
0.150
0.0020
1.400
1.450
0.0531
0.0551
0.0571
0.370
0.450
0.0118
0.0146
0.0177
0.200
0.0035
9.000
9.200
0.3465
0.3543
0.3622
7.000
7.200
0.2677
0.2756
0.2835
5.600
0.0059
0.0079
0.2205
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
5.600
0.2205
e
0.800
0.0315
L
0.450
L1
k
ccc
0.600
0.750
0.0177
1.000
0.0°
3.5°
0.0236
0.0295
0.0394
7.0°
0.0°
0.100
1. Values in inches are converted from mm and rounded to 4 decimal digits
84/95
Typ
Doc ID 15441 Rev 2
3.5°
7.0°
0.0039
STM8S103x
10.1.2
Package characteristics
QFN package mechanical data
Figure 45. 32-lead very thin fine pitch quad flat no-lead package (5 x 5)
Seating plane
C
ddd
C
A
A1
A3
D
e
16
9
17
8
E
b
E2
24
1
L
32
Pin # 1 ID
R = 0.30
D2
L
Bottom view
Table 53.
42_ME
32-lead very thin fine pitch quad flat no-lead package mechanical data
inches(1)
mm
Dim.
Min
Typ
Max
Min
Typ
Max
A
0.80
0.90
1.00
0.0315
0.0354
0.0394
A1
0
0.02
0.05
0.0008
0.0020
A3
0.20
0.0079
b
0.18
0.25
0.30
0.0071
0.0098
0.0118
D
4.85
5.00
5.15
0.1909
0.1969
0.2028
D2
3.20
3.45
3.70
0.1260
E
4.85
5.00
5.15
0.1909
0.1969
0.2028
E2
3.20
3.45
3.70
0.1260
0.1358
0.1457
e
L
ddd
0.50
0.30
0.40
0.1457
0.0197
0.50
0.0118
0.08
0.0157
0.0197
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits
Doc ID 15441 Rev 2
85/95
Package characteristics
10.1.3
STM8S103x
TSSOP package mechanical data
Figure 46. TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch
D
20
11
c
E1
1
E
10
k
aaa CP
A1
A
L
A2
L1
b
e
YA_ME
Table 54.
TSSOP 20-pin, 4.40 mm body, 0.65 mm pitch mechanical data
inches(1)
mm
Dim.
Min
Typ
A
Max
Min
1.200
A1
0.050
A2
0.800
b
Max
0.0472
0.150
0.0020
1.050
0.0315
0.190
0.300
0.0075
0.0118
c
0.090
0.200
0.0035
0.0079
D
6.400
6.500
6.600
0.2520
0.2559
0.2598
E
6.200
6.400
6.600
0.2441
0.2520
0.2598
E1
4.300
4.400
4.500
0.1693
0.1732
0.1772
e
L
k
aaa
1.000
0.650
0.450
L1
0.600
0.750
0.0177
1.000
0.0°
0.0059
0.0394
0.0413
0.0256
0.0236
0.0295
0.0394
8.0°
0.0°
0.100
1. Values in inches are converted from mm and rounded to 4 decimal digits
86/95
Typ
Doc ID 15441 Rev 2
8.0°
0.0039
STM8S103x
10.1.4
Package characteristics
WFQFPN20 package mechanical data
Figure 47. 20-lead, very, very thin, fine pitch quad flat no-lead package outline (3 x 3)
ddd
D
e
5
A2
10
11
b
A3
e
E
1
15
L1
L2
20
16
A1
A
C0_ME
1. Drawing is not to scale
Figure 48. Recommended footprint for on-board emulation
0.5mm
0.8mm
[0.032"]
4mm
[0.157"]
0.5mm
1.65mm [0.065"]
0.9mm
[0.035"]
0.3mm [0.012"]
4mm [0.157"]
ai15319
Bottom view
1. Drawing is not to scale
Doc ID 15441 Rev 2
87/95
Package characteristics
STM8S103x
Figure 49. Recommended footprint without on-board emulation
1. Drawing is not to scale
2. Dimensions are in millimeters
Table 55.
20-lead, very, very thin, fine pitch quad flat no-lead package (3 x 3)
package mechanical data
inches(1)
mm
Dim.
A
Min
Typ
Max
Min
Typ
Max
0.65
0.75
0.85
0.0256
0.0295
0.0335
0.01
0.05
0.0004
0.002
A1
A2
0.45
0.55
0.65
0.0177
0.0217
0.0256
A3
0.19
0.22
0.24
0.0075
0.0087
0.0094
b
0.2
0.25
0.3
0.0079
0.0098
0.0118
D
2.9
3
3.1
0.1142
0.1181
0.122
E
2.9
3
3.1
0.1142
0.1181
0.122
e
0.5
0.0197
L1
0.3
0.4
0.5
0.0118
0.0157
0.0197
L2
0.25
0.35
0.45
0.0098
0.0138
0.0177
ddd
0.08
0.0031
Number of pins
N
20
1. Values in inches are converted from mm and rounded to 4 decimal digits.
88/95
Doc ID 15441 Rev 2
STM8S103x
10.2
Package characteristics
Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 19: General operating conditions on page 49.
The maximum chip-junction temperature, TJmax, in degrees Celsius, may be calculated
using the following equation:
TJmax = TAmax + (PDmax x ΘJA)
Where:
●
TAmax is the maximum ambient temperature in ° C
●
ΘJA is the package junction-to-ambient thermal resistance in ° C/W
●
PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
●
PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
●
PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the
application.
Table 56.
Thermal characteristics(1)
Symbol
Parameter
Value
Unit
ΘJA
Thermal resistance junction-ambient
LQFP 32 - 7 x 7 mm
60
°C/W
ΘJA
Thermal resistance junction-ambient
VFQFN 32 - 5 x 5 mm
22
°C/W
ΘJA
Thermal resistance junction-ambient
TSSOP20 - 4.4 mm
84
°C/W
ΘJA
Thermal resistance junction-ambient
WFQFN20 - 3 x 3 mm
90
°C/W
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
10.2.1
Reference document
JESD51-2 integrated circuits thermal test method environment conditions - natural
convection (still air). Available from www.jedec.org.
Doc ID 15441 Rev 2
89/95
Package characteristics
10.2.2
STM8S103x
Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see
Section 11: Ordering information on page 91).
The following example shows how to calculate the temperature range needed for a given
application.
Assuming the following application conditions:
Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2),
IDDmax = 8 mA, VDD = 5 V, maximum 20 I/Os used at the same time in output at low
level with IOL = 8 mA, VOL= 0.4 V
PINTmax = 8 mA x 5 V= 400 mW
PIOmax = 20 x 8 mA x 0.4 V = 64 mW
This gives: PINTmax = 400 mW and PIOmax 64 mW:
PDmax = 400 mW + 64 mW
Thus: PDmax = 464 mW
Using the values obtained in Table 56: Thermal characteristics on page 89 TJmax is
calculated as follows:
–
For LQFP32 59°C/W
TJmax = 75° C + (59° C/W x 464 mW) = 75°C + 27°C = 102° C
This is within the range of the suffix 6 version parts (-40 < TJ < 105° C).
In this case, parts must be ordered at least with the temperature range suffix 6.
90/95
Doc ID 15441 Rev 2
STM8S103x
11
Ordering information
Ordering information
STM8S103x Access line ordering information scheme
Example:
STM8
S
103
K
3
T
6
C
TR
Product class
STM8 microcontroller
Family type
S = Standard
Sub-family type
103 = Access line 103 sub-family
Pin count
K = 32 pins
F = 20 pins
Program memory size
3 = 8 Kbytes
2 = 4 Kbytes
Package type
P = TSSOP
T = LQFP
U = VFQFPN or WFQFPN
Temperature range
3 = -40 °C to 125 °C
6 = -40 °C to 85 °C
Package pitch
No character = 0.5 mm
B = 0.65 mm
C = 0.8 mm
Packing
No character = Tray or tube
TR = Tape and reel
1. For a list of available options (e.g. memory size, package) and orderable part numbers or for further
information on any aspect of this device, please go to www.st.com or contact the ST Sales Office nearest to
you.
Doc ID 15441 Rev 2
91/95
STM8 development tools
12
STM8S103x
STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation
system supported by a complete software tool package including C compiler, assembler and
integrated development environment with high-level language debugger. In addition, the
STM8 is to be supported by a complete range of tools including starter kits, evaluation
boards and a low-cost in-circuit debugger/programmer.
12.1
Emulation and in-circuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging
features on a platform that is designed for versatility and cost-effectiveness. In addition,
STM8 application development is supported by a low-cost in-circuit debugger/programmer.
The STice is the fourth generation of full featured emulators from STMicroelectronics. It
offers new advanced debugging capabilities including profiling and coverage to help detect
and eliminate bottlenecks in application execution and dead code when fine tuning an
application.
In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via
the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an
application while it runs on the target microcontroller.
For improved cost effectiveness, STice is based on a modular design that allows you to
order exactly what you need to meet your development requirements and to adapt your
emulation system to support existing and future ST microcontrollers.
STice key features
92/13
●
Occurrence and time profiling and code coverage (new features)
●
Advanced breakpoints with up to 4 levels of conditions
●
Data breakpoints
●
Program and data trace recording up to 128 KB records
●
Read/write on the fly of memory during emulation
●
In-circuit debugging/programming via SWIM protocol
●
8-bit probe analyzer
●
1 input and 2 output triggers
●
Power supply follower managing application voltages between 1.62 to 5.5 V
●
Modularity that allows you to specify the components you need to meet your
development requirements and adapt to future requirements
●
Supported by free software tools that include integrated development environment
(IDE), programming software interface and assembler for STM8.
Doc ID 15441 Rev 2
STM8S103x
12.2
STM8 development tools
Software tools
STM8 development tools are supported by a complete, free software package from
STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual
Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic
and Raisonance C compilers for STM8, which are available in a free version that outputs up
to 16 Kbytes of code.
12.2.1
STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming
software is available for free download at www.st.com/mcu. This package includes:
ST visual develop – Full-featured integrated development environment from ST, featuring
●
Seamless integration of C and ASM toolsets
●
Full-featured debugger
●
Project management
●
Syntax highlighting editor
●
Integrated programming interface
●
Support of advanced emulation features for STice such as code profiling and coverage
ST visual programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read,
write and verify of your STM8 microcontroller’s Flash program memory, data EEPROM and
option bytes. STVP also offers project mode for saving programming configurations and
automating programming sequences.
12.2.2
C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated
development environment, making it possible to configure and control the building of your
application directly from an easy-to-use graphical interface.
Available toolchains include:
12.3
●
Cosmic C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.cosmic-software.com.
●
Raisonance C compiler for STM8 – Available in a free version that outputs up to
16 Kbytes of code. For more information, see www.raisonance.com.
●
STM8 assembler linker – Free assembly toolchain included in the STVD toolset,
which allows you to assemble and link your application source code.
Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash
microcontroller on your application board via the SWIM protocol. Additional tools are to
include a low-cost in-circuit programmer as well as ST socket boards, which provide
dedicated programming platforms with sockets for programming your STM8.
For production environments, programmers will include a complete range of gang and
automated programming solutions from third-party tool developers already supplying
programmers for the STM8 family.
Doc ID 15441 Rev 2
93/95
Revision history
13
STM8S103x
Revision history
Table 57.
Document revision history
Date
Revision
02-Mar-2009
1
Initial revision
2
Added Table 2 on page 15.
Updated Section 4.8: Auto wakeup counter on page 17.
Modified description of PB4 and PB5 (removed X in PP column) and
added footnote concerning HS I/Os in Table 5 and Table 6.
Removed TIM3 and UART from Table 8: Interrupt mapping
Updated VCAP specifications in Section 9.3.1 on page 50.
Corrected block size in Table 37: Flash program memory/data
EEPROM memory.
Updated Section 9: Electrical characteristics.
Updated Table 56: Thermal characteristics.
10-Apr-2009
94/95
Changes
Doc ID 15441 Rev 2
STM8S103x
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2009 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
Doc ID 15441 Rev 2
95/95
Download PDF
Similar pages