HFBR-53A5VEMZ/HFBR-53A5VFMZ
3.3 V 1 x 9 Fiber Optic Transceivers
for Gigabit Ethernet Low Voltage
Data Sheet
Description
Features
The HFBR-53A5VEMZ transceivers from Avago Technologies allow the system designer to implement a range of
solutions for multimode Gigabit Ethernet applications.
• Compliant with specifications for IEEE- 802.3z Gigabit
Ethernet
• Industry standard mezzanine height 1 x 9 package style
with integral duplex SC connector
• PerformanceHFBR-53A5VEMZ/FMZ:
– 220 m links in 62.5/125 µm MMF 160 MHz* km
cables
– 275 m links in 62.5/125 µm MMF 200 MHz* km
cables
– 500 m links in 50/125 µm MMF 400 MHz* km cables
– 550 m links in 50/125 µm MMF 500 MHz* km cables
• IEC 60825-1 Class 1/CDRH Class I laser eye safe
• Single +3.3 V power supply operation with PECL compatible logic interfaces and TTL Signal Detect
• Wave solder and aqueous wash process compatible
• RoHS compliant
The overall Avago transceiver prod­uct consists of three
sections: the transmitter and receiver optical subassemblies, an electrical subassembly, and the package housing which incorporates a duplex SC connector
receptacle.
Transmitter Section
The transmitter section of the HFBR-53A5VEMZ/FMZ
consists of an 850 nm Vertical Cavity Surface Emitting
Laser (VCSEL) in an optical subassembly (OSA), which
mates to the fiber cable. The OSA is driven by a custom, silicon bipolar IC which converts differential PECL
compatible logic signals into an analog laser diode
drive current. The high speed output lines are internally accoupled and differen-tially terminate with a 100 Ω resistor.
Receiver Section
The receiver of the HFBR-53A5VEMZ/FMZ includes a
GaAs PIN photo-diode mounted together with a custom,
silicon bipolar transimpedance preamplifier IC in an
OSA. This OSA is mated to a custom silicon bipolar circuit
that provides post-amplification and quantization.
The post-amplifier also includes a Signal Detect circuit
which pro­vides a TTL logic-high output upon detection of
a usable input optical signal level. The high speed output
lines are internally ac-coupled.
Patent - www.avagotech.com/patents
Applications
• Switch-to-switch interface
• Switched backbone applications
• High speed interface for file servers
• High performance desktops
Related Products
• Physical layer ICs available for optical or copper interface
(HDMP-1636A/1646A)
• Quad SerDes IC available for high-density interface
• Versions of this transceiver module also available for +5
V operation (AFBR-53D5XZ/HFCT-53D5XXZ)
• MT-RJ SFF fiber optic transceivers for Gigabit Ethernet (HFBR/HFCT-5912EZ)
• Gigabit Interface Converters (GBIC) Gigabit Ethernet
SX-AFBR-5601Z/LX-AFCT-5611Z
Package and Handling Instructions
Flammability
The HFBR-53A5VEMZ/FMZ transceiver housing is made
of high strength, heat resistant, chemically resistant,
and UL 94V‑0 flame retardant plastic.
Recommended Solder and Wash Process
The HFBR-53A5VEMZ/FMZ is compatible with industrystandard wave or hand solder processes.
Process Plug
This transceiver is supplied with a process plug
(HFBR-5000) for protection of the optical ports within
the duplex SC connector receptacle. This process
plug prevents contamination during wave solder and
aqueous rinse as well as during handling, shipping
and storage. It is made of a high-temperature, molded
sealing material that can withstand 80°C and a rinse
pressure of 110 lbs per square inch.
Recommended Solder Fluxes
Solder fluxes used with the HFBR-53A5VEMZ/FMZ
should be water-soluble, organic fluxes. Recom­mended
solder fluxes include Lonco 3355-11 from London
Chemical West, Inc. of Burbank, CA, and 100 Flux from
Alpha-Metals of Jersey City, NJ.
Recommended Cleaning/Degrading Chemicals
Alcohols: methyl, isopropyl, isobutyl.
Aliphatics: hexane, heptane.
Other: soap solution, naphtha.
Do not use partially halogenated hydrocarbons such
as 1,1.1 trichloroethane, ketones such as MEK, acetone, chloroform, ethyl acetate, methylene dichloride,
phenol, methylene chloride, or N-methylpyrolldone.
Also, Avago does not recommend the use of cleaners
that use halogenated hydrocarbons because of their
potential environmental harm.
Regulatory Compliance
(See the Regulatory Compliance Table for transceiver
performance)
The overall equipment design will determine the
certification level. The transceiver performance is
offered as a figure of merit to assist the designer in
considering their use in equipment designs.
2
Electrostatic Discharge (ESD)
There are two design cases in which immunity to ESD
damage is important.
The first case is during handling of the transceiver prior
to mounting it on the circuit board. It is important to
use normal ESD handling precautions for ESD sensitive
devices. These pre­cautions include using grounded
wrist straps, work benches, and floor mats in ESD
controlled areas. The transceiver perform­ance has been
shown to provide adequate performance in typical
industry production environments.
The second case to consider is static discharges to
the exterior of the equipment chassis containing the
transceiver parts. To the extent that the duplex SC
connector receptacle is exposed to the outside of
the equipment chassis it may be subject to whatever
system-level ESD test criteria that the equipment is intended to meet. The transceiver performance is more robust
than typical industry equipment requirements of today.
Electromagnetic Interference (EMI)
Most equipment designs utilizing these high-speed
transceivers from Avago will be required to meet the
requirements of FCC in the United States, CENELEC
EN55022 (CISPR 22) in Europe and VCCI in Japan.
Refer to EMI section (page 4) for more details.
Immunity
Equipment utilizing these transceivers will be subject
to radio-frequency electromagnetic fields in some environments. These transceivers have good immunity to
such fields due to their shielded design.
Eye Safety
These laser-based transceivers are classified as AEL Class
I (U.S. 21 CFR(J) and AEL Class 1 per EN 60825-1 (+A11).
They are eye safe when used within the data sheet
limits per CDRH. They are also eye safe under normal operating conditions and under all reasonably
forseeable single fault conditions per EN60825-1.
Avago has tested the transceiver design for compliance with the requirements listed below under
normal operating conditions and under single fault
conditions where applicable. TUV Rheinland has
granted certification to these transceivers for laser eye
safety and use in EN 60950 and EN 60825-2 applications.
Their performance enables the transceivers to be used
without concern for eye safety up to maximum volts
transmitter VCC.
CAUTION:
There are no user serviceable parts nor any maintenance
required for the HFBR-53A5VEMZ/FMZ. All adjustments are made at the factory before shipment to our
customers. Tampering with or modifying the
performance of the HFBR-53A5VEMZ/FMZ will result in
voided product warranty. It may also result in improper
operation of the HFBR-53A5VEMZ/FMZ circuitry, and
possible overstress of the laser source. Device
degradation or product failure may result.
Connection of the HFBR-53A5VEMZ/FMZ to a nonapproved optical source, operating above the recom­
mended absolute maximum conditions or operating the
HFBR-53A5VEMZ/FMZ in a manner inconsistent with its
design and function may result in hazardous radiation
exposure and may be considered an act of modifying
or manufacturing a laser product. The person(s) performing such an act is required by law to recertify
and reidentify the laser product under the provisions of
U.S. 21 CFR (Subchapter J).
Regulatory Compliance
Feature
Test Method
Performance
Electrostatic Discharge
MIL-STD-883C
Class 1 (>1500 V).
(ESD) to the
Method 3015.7
Electrical Pins
Electrostatic Discharge
Variation of IEC 61000-4-2
Typically withstand at least 15 kV without
(ESD) to the
damage when the duplex SC connector
Duplex SC Receptacle
receptacle is contacted by a Human Body
Model probe.
Electromagnetic
FCC Class B
Margins are dependent on customer board and
Interference (EMI)
CENELEC EN55022 Class B
chassis designs.
(CISPR 22A)
VCCI Class I
Immunity
Variation of IEC 61000-4-3
Typically show no measurable effect from a
10 V/m field swept from 80 to 1000 MHz applied
to the transceiver without a chassis enclosure.
Laser Eye Safety
US 21 CFR, Subchapter J
AEL Class I, FDA/CDRH
and Equipment Type
per Paragraphs 1002.10
HFBR-53A5V*MZ Accession #9720151
Testing
and 1002.12
EN 60825-1: 1994 + A1 + A2
AEL Class 1, TUV Rheinland of North America
EN 60825-2: 2000
HFBR-53A5V*MZ:
EN 60950: 2000
Certificate #R72040311
Protection Class III
Component
Underwriters Laboratories and UL File E173874
Recognition
Canadian Standards Association Joint Component Recognition for Information Technology Equipment Including Electrical Business Equipment.
RoHS Compliance
Reference to EU RoHS
Directive 2002/95/EC
3
APPLICATION SUPPORT
Optical Power Budget and Link Penalties
The worst-case Optical Power Budget (OPB) in dB for
a fiber-optic link is determined by the difference between the minimum transmitter output optical power
(dBm avg) and the lowest receiver sensitivity (dBm
avg). This OPB provides the necessary optical signal
range to establish a working fiber-optic link. The OPB is
allocated for the fiber-optic cable length and the
corre­
s ponding link penalties. For proper link
performance, all penalties that affect the link
performance must be accounted for within the link
optical power budget. The Gigabit Ethernet IEEE 802.3z
standard identifies, and has modeled, the contributions
of these OPB penalties to establish the link length
requirements for 62.5/125 µm and 50/125 µm
multimode fiber usage. Refer to the IEEE 802.3z
standard and its supplemental documents that develop
the model, empirical results and final specifications.
Data Line Interconnections
Avago’s HFBR-53A5VEMZ/FMZ fiber-optic transceiver
is designed for compatible PECL signals. The transmitter inputs are internally ac-coupled to the laser driver
circuit from the transmitter input pins (pins 7, 8). The
transmitter driver circuit for the laser light source is an
ac-coupled circuit. This circuit regulates the output
optical power. The regulated light output will maintain
a constant output optical power provided the data
pattern is reasonably balanced in duty factor. If the
data duty factor has long, con­tinu­ous state times (low
or high data duty factor), then the output optical power
will gradually change its average output optical power
level to its pre-set value.
The receiver section is internally AC-coupled between
the pre-amplifier and the post-amplifier stages. The
actual Data and Data-bar outputs of the post-amplifier
are ac-coupled to their respective output pins (pins 2, 3).
Signal Detect is a single-ended, TTL output signal that
is dc-coupled to pin 4 of the module. Signal Detect
should not be AC-coupled externally to the follow-on
circuits because of its infrequent state changes.
Caution should be taken to account for the proper
intercon­n ec­tion between the supporting Physical
Layer integrated circuits and this HFBR-53A5VEMZ/
FMZ transceiver. Figure 3 illustrates a recommended
interface circuit for interconnecting to a DC PECL
compatible fiber-optic transceiver.
4
Eye Safety Circuit
For an optical transmitter device to be eye-safe in the
event of a single fault failure, the trans­mit­ter must either
maintain normal, eye-safe operation or be disabled.
In the HFBR-53A5VEMZ/FMZ there are three key
elements to the laser driver safety circuitry: a monitor
diode, a window detec­tor circuit, and direct control of
the laser bias. The window detection circuit monitors
the average optical power using the monitor diode. If
a fault occurs such that the transmitter DC regulation
circuit cannot maintain the preset bias conditions for
the laser emitter within ±20%, the transmitter will
automatically be disabled. Once this has occurred,
only an electrical power reset will allow an attempted
turn-on of the transmitter.
Signal Detect
The Signal Detect circuit provides a deasserted output
signal that implies the link is open or the transmitter
is OFF as defined by the Gigabit Ethernet specification
IEEE 802.3z, Table 38.1. The Signal Detect threshold is
set to transition from a high to low state between the
minimum receiver input optional power and –30 dBm
avg. input optical power indicating a definite optical
fault (e.g., unplugged connector for the receiver or
transmitter, broken fiber, or failed far-end transmitter or
data source). A Signal Detect indicating a working link
is functional when receiving encoded 8B/10B
characters. The Signal Detect does not detect receiver
data error or error-rate. Data errors are determined
by Signal processing following the transceiver.
Electromagnetic Interference (EMI)
One of a circuit board designer’s foremost concerns is
the control of electromagnetic emissions from electronic equipment. Success in controlling generated Electromagnetic Interference (EMI) enables the
designer to pass a governmental agency’s EMI regulatory
standard; and more importantly, it reduces the
possibility of interference to neighboring equipment.
The EMI performance of an enclosure using these
transceivers is dependent on the chassis design. Avago
encourages using standard RF suppression practices
and avoiding poorly EMI-sealed enclosures.
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each
parameter in isolation, all other parameters having values within the recommended operating conditions. It should not
be assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure
to the absolute maximum ratings for extended periods can adversely affect device reliability.
Parameter
Symbol Min.Typ. Max. Unit Reference
Storage Temperature
TS
–40
+100°C
Supply Voltage
VCC –0.5
5.0 V
1
Transmitter Differential Input Voltage
VD 2.2V
Relative Humidity
RH
5
95
%
TTL Signal Detect Current – Low
IOL, MAX–5
mA
TTL Signal Detect Current – High
IOH, MAX
4.0 mA
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Case Temperature
Supply Voltage
Power Supply Rejection
Transmitter Differential Input Voltage
Data Output Load
TTL Signal Detect Output Current
TTL Signal Detect Output Current
Symbol Min. Typ. Max.Unit Reference
TA 0 70
°C
TC80
°C2
VCC 3.14 3.3 3.47V
PSR
100
mVP–P3
VD 0.4
1.6V
RDL 50 Ω
IOL
1.0
mA
IOH
–400
µA
Process Compatibility
Parameter
Hand Lead Soldering Temperature/Time
Wave Soldering and Aqueous Wash
Symbol
Min.Typ. Max. Unit Reference
TSOLD/tSOLD
+260/10
°C/s
TSOLD/tSOLD
+260/10
°C/s4
Notes:
1. The transceiver is class 1 eye safe up to VCC = 5.0 V.
2. Case temperature measurement referenced to the center top of the internal metal transmitter shield.
3. Tested with a 100 mVP–P sinusoidal signal in the frequency range from 10 Hz to 2 MHz on the VCC supply with the recommended power supply filter in place. Typically less than a 1 dB change in sensitivity is experienced.
4. Aqueous wash pressure < 110 psi.
5
HFBR-53A5VEMZ/FMZ, 850 nm VCSEL
Transmitter Electrical Characteristics
(TA = 0 °C to +70 °C, VCC = 3.14 V to 3.47 V)
Parameter
Supply Current
Power Dissipation
Laser Reset Voltage
Symbol Min.Typ. Max. Unit Reference
ICCT 5575mA
PDIST 0.180.26W
VCCT–reset 2.52.0V 1
Receiver Electrical Characteristics
(TA = 0 °C to +70 °C, VCC = 3.14 V to 3.47 V)
Parameter
Supply Current
Power Dissipation
Data Output Voltage – Peak to Peak
Differential
Data Output Rise Time
Data Output Fall Time
Signal Detect Output Voltage – Low
Signal Detect Output Voltage – High
Signal Detect Assert Time
Signal Detect Deassert Time
Symbol Min. Typ.Max.UnitReference
ICCR
80 135mA
PDISR
0.260.47 W
VOPP
0.4
2
V
2
tr 0.40ns 3
tf 0.40ns 3
VOL 0.6V 4
VOH 2.2 V 4
tSDA 100µs
tSDD 350µs
Notes:
1. The Laser Reset Voltage is the voltage level below which the VCCT voltage must be lowered to cause the laser driver circuit to reset from an
electrical/optical shutdown condition to a proper electrical/optical operating condition. The maximum value corresponds to the worst-case
highest VCC voltage necessary to cause a reset condition to occur. The laser safety shutdown circuit will operate properly with transmitter VCC
levels of 2.5 Vdc ≤ VCC ≤ 5.0 Vdc.
2. These outputs are compatible with 10 K, 10 KH, and 100 K ECL and PECL inputs.
3. These are 20-80% values.
4. Under recommended operating conditions.
6
HFBR-53A5VEMZ/FMZ, 850 nm VCSEL
Transmitter Optical Characteristics
(TA = 0°C to +70°C, VCC = 3.14 V to 3.47 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Output Optical Power
POUT
–9.5
–4
dBm avg.
50/125 µm, NA = 0.20 Fiber
Output Optical Power
POUT
–9.5
–4
dBm avg.
62.5/125 µm, NA = 0.275 Fiber
Optical Extinction Ratio
9
dB
Center Wavelength
λC
830850860nm
Spectral Width – rms
σ0.85
nm rms
Optical Rise/Fall Time
tr/tf
0.26
ns
RIN12–117
dB/Hz
Coupled Power Ratio
CPR
9
dB
Total Transmitter Jitter 227
ps
Added at TP2
Reference
1
1
2
3, 4, Figure 1
5
6
Receiver Optical Characteristics
(TA = 0°C to +70°C, VCC = 3.14 V to 3.47 V)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Reference
Input Optical Power PIN
–17
0
dBm avg.
7
Stressed Receiver Sensitivity
62.5 µm–12.5
dBm avg.
8
50 µm–13.5
dBm avg.
8
Stressed Receiver Eye 201
ps
6, 9
Opening at TP4
Receive Electrical 3 dB
1500
MHz
10
Upper Cutoff Frequency
Operating Center Wavelength
λC 770
860 nm
Return Loss
12
dB
11
Signal Detect – Asserted
PA–17
dBm avg.
12
Signal Detect – Deasserted
PD
–30
dBm avg.
12
Signal Detect – Hysteresis
PA – PD1.5
dB
12
Notes:
1. The maximum Optical Output Power complies with the IEEE 802.3z specification, and is class 1 laser eye safe.
2. Optical Extinction Ratio is defined as the ratio of the average optical power of the transmitter in the high (“1”) state to the low (“0”) state. Extinction Ratio shall be measured using the methods specified in TIA/EIA.526.4A. This measurement may be made with the node transmitting
a 36A.3 data pattern. The Saturation Ratio is measured under fully modulated conditions with worst case reflections. A36A.3 data pattern is a
repeating K28.7 data pattern, which generates a 125 mHz square wave.
3. These are unfiltered 20-80% values.
4. Laser transmitter pulse response characteristics are specified by an eye diagram (Figure 1). The characteristics include rise time, fall time,
pulse overshoot, pulse undershoot, and ringing, all of which are controlled to prevent excessive degradation of the receiver sensitivity. These
parameters are specified by the referenced Gigabit Ethernet eye diagram using the required filter. The output optical waveform complies with
the requirements of the eye mask discussed in section 38.6.5 and Fig. 38-2 of IEEE 802.3z.
5. CPR is measured in accordance with EIA/TIA-526-14A as referenced in 802.3z, section 38.6.10.
6. TP refers to the compliance point specified in 802.3z, section 38.2.1.
7. The receive sensitivity is measured using a worst case extinction ratio penalty while sampling at the center of the eye.
8. The stressed receiver sensitivity is measured using the conformance test signal defined in 802.3z, section 38.6.11. The conformance test signal
is conditioned by applying deterministic jitter and intersymbol interference.
9. The stressed receiver jitter is measured using the conformance test signal defined in 802.3z, section 38.6.11 and set to an average optical
power 0.5 dB greater than the specified stressed receiver sensitivity.
10.The 3 dB electrical bandwidth of the receiver is measured using the technique outlined in 802.3z, section 38.6.12.
11.Return loss is defined as the minimum attenuation (dB) of received optical power for energy reflected back into the optical fiber.
12.With valid 8B/10B encoded data.
7
Table 1. Pinout Table
Pin
Symbol
Mounting Pins
1
VEER
2
RD+
3
RD–
4
SD
5
VCCR
6
VCCT
7
TD–
8
TD+
9
VEET
Functional Description
The mounting pins are provided for transceiver mechanical attachment to the circuit board. They are embedded in the nonconductive plastic housing and are not connected to the trans
ceiver internal circuit, nor is there a guaranteed connection to the metallized housing in the EM and FM versions. They should be soldered into plated‑through holes on the printed circuit board.
Receiver Signal Ground
Directly connect this pin to receiver signal ground plane. (VEER = VEET)
Receiver Data Out
AC coupled – PECL compatible.
Receiver Data Out Bar
AC coupled – PECL compatible.
Signal Detect
Signal Detect is a single‑ended TTL output. If Signal Detect output is not used, leave it open‑circuited.
Normal optical input levels to the receiver result in a logic “1” output, VOH, asserted.
Low input optical levels to the receiver result in a fault condition indicated by a logic “0” output VOL, deasserted.
Receiver Power Supply
Provide +3.3 Vdc via the recommended receiver power supply filter circuit.
Locate the power supply filter circuit as close as possible to the VCCR pin.
Transmitter Power Supply
Provide +3.3 Vdc via the recommended transmitter power supply filter circuit.
Locate the power supply filter circuit as close as possible to the VCCT pin.
Transmitter Data In-Bar
AC coupled – PECL compatible. Internally terminated differentially with 100 Ω.
Transmitter Data In
AC coupled – PECL compatible. Internally terminated differentially with 100 Ω.
Transmitter Signal Ground
Directly connect this pin to the transmitter signal ground plane.
NORMALIZED AMPLITUDE
1 = VEER
2 = RD+
1.3
1.0
4 = SD
0.8
5 = VCCR
7 = TD8 = TD+
0.2
9 = VEET
0
0
0.22
0.375
0.625 0.78
NORMALIZED TIME
Figure 1. Transmitter optical eye diagram mask
8
RX
6 = VCCT
0.5
-0.2
NIC
3 = RD-
TX
NIC
TOP VIEW
1.0
NIC = NO INTERNAL CONNECTION (MOUNTING PINS)
Figure 2. Pin-out
+
LASER
DRIVER
CIRCUIT
PECL
INPUT
9
VEET 8
TD+
50 Ω
TD- 7
50 Ω
100 W
VCCT 6
TDR13
150
L2
C2
0.1
µF
1 µH
0.1 µF
HFBR-53A5VEMZ/FMZ
FIBER-OPTIC
TRANSCEIVER
VCCR 5
C1
+ C8*
SD 4
3.3 V
GND
CLOCK
SYNTHESIS
CIRCUIT
PARALLEL
TO SERIAL
CIRCUIT
HDMP-1636A/-1646A
SERIAL/DE-SERIALIZER
(SERDES - 10 BIT
TRANSCEIVER)
10
µF
C3
1 µH
10 µF*
OUTPUT
DRIVER
R12
150
+ C4
L1
0.1
µF
SIGNAL
DETECT
CIRCUIT
0.1
µF
TO SIGNAL DETECT (SD)
INPUT AT UPPER-LEVEL-IC
50 Ω
RD- 3
PREAMPLIFIER
VCC2 VEE2
TD+
3.3 Vdc
RDR14
POSTAMPLIFIER
RD+ 2
VEER 1
50 Ω
100
RD+
INPUT
BUFFER
CLOCK
RECOVERY
CIRCUIT
SERIAL TO
PARALLEL
CIRCUIT
SEE HDMP-1636A/-1646A DATA SHEET FOR
DETAILS ABOUT THIS TRANSCEIVER IC.
NOTES:
USE SURFACE-MOUNT COMPONENTS FOR OPTIMUM HIGH-FREQUENCY PERFORMANCE.
USE 50 Ω MICROSTRIP OR STRIPLINE FOR SIGNAL PATHS.
LOCATE 50 Ω TERMINATIONS AT THE INPUTS OF RECEIVING UNITS.
Figure 3. Recommended Gigabit/sec Ethernet HFBR-53A5VEMZ/FMZ fiber-optic transceiver and HDMP-1636A/1646A SerDes integrated circuit transceiver interface and power
supply filter circuits
(2×)ø 1.9 ± 0.1
0.075 ± 0.004
Ø0.000 M A
20.32
0.800
0.8 ± 0.1
0.032 ± 0.004
Ø0.000 M A
20.32
0.800
(8×)
(9×) ø
2.54
0.100
TOP VIEW
Figure 4. Recommended board layout hole pattern
9
–A–
A
TX
XXXX-XXXX
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
RX
KEY:
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = HFBR-53xx
ZZZZ = 850 nm
29.6 UNCOMPRESSED
(1.16)
39.6
(1.56) MAX.
4.7
(0.185)
AREA
RESERVED
FOR
PROCESS
PLUG
A
25.4
(1.00) MAX.
12.7
(0.50)
12.7
(0.50)
SLOT WIDTH 2.0 ± 0.1
(0.079 ± 0.004)
0.25 +0.1
-0.05
(0.010 +0.004 )
-0.002
2.09 UNCOMPRESSED
(0.08)
10.2 MAX.
(0.40)
9.8 MAX.
(0.386)
1.3
(0.05)
3.3 ± 0.38
(0.130 ± 0.015)
0.47 +0.18
-0.06
9× ∅
(0.019 +0.007 )
-0.002
23.8
(0.937)
20.32
(0.800)
20.32
(0.80)
8× 2.54
(0.100)
1.3
2× ∅ (0.051)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ± 0.025 mm, UNLESS OTHERWISE SPECIFIED.
Figure 5. Package outline for HFBR-53A5VEMZ
10
15.8 ± 0.15
(0.622 ± 0.006)
2× ∅
1.27 +0.25
-0.05
(0.050 +0.010 )
-0.002
20.32
(0.800)
A
1.014
0.8
2× (0.032)
0.8
2× (0.032)
10.9 + 0.5
– 0.25
+ 0.02
( 0.43 – 0.01 )
9.4
(0.374)
5.35
(0.25)
MODULE
PROTRUSION
PCB BOTTOM VIEW
Figure 6. Suggested module positioning and panel cut-out for HFBR-53A5VEMZ
11
27.4 ± 0.50
(1.08 ± 0.02)
A
TX
XXXX-XXXX
ZZZZZ LASER PROD
21CFR(J) CLASS 1
COUNTRY OF ORIGIN YYWW
RX
KEY:
YYWW = DATE CODE
FOR MULTIMODE MODULE:
XXXX-XXXX = HFBR-53xx
ZZZZ = 850 nm
39.6
(1.56) MAX.
12.7
(0.50)
4.7
(0.185)
1.01
(0.40)
AREA
RESERVED
FOR
PROCESS
PLUG
A
25.4
(1.00) MAX.
25.8 MAX.
(1.02)
0.25 +0.1
-0.05
(0.010 +0.004 )
-0.002
0.47 +0.18
-0.06
9× ∅
(0.019 +0.007 )
-0.002
23.8
(0.937)
20.32
(0.800)
2× ∅
22.0
(0.87)
20.32
(0.800)
1.3
(0.051)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ±0.025 mm UNLESS OTHERWISE SPECIFIED.
12
SLOT WIDTH 2.0 ± 0.1
(0.079 ± 0.004)
SLOT DEPTH 2.2
(0.09)
14.4
(0.57)
8× 2.54
(0.100)
Figure 7. Package outline for HFBR-53A5VFMZ
12.7
(0.50)
10.2 MAX.
(0.40)
9.8 MAX.
(0.386)
3.3 ± 0.38
(0.130 ± 0.015)
29.7
(1.17)
15.8 ± 0.15
(0.622 ± 0.006)
2× ∅
AREA
RESERVED
FOR
PROCESS
PLUG
1.27 +0.25
-0.05
(0.050 +0.010 )
-0.002
20.32
(0.800)
A
DIMENSION SHOWN FOR MOUNTING MODULE FLUSH TO PANEL.
1.98 THICKER PANEL WILL RECESS MODULE.
(0.078) THINNER PANEL WILL PROTRUDE MODULE.
1.27 OPTIONAL SEPTUM
(0.05)
30.2
(1.19)
0.36
(0.014)
KEEP OUT ZONE
10.82
(0.426)
13.82
(0.544)
BOTTOM SIDE OF PCB
1.82
(0.072)
26.4
(1.04)
12.0
(0.47)
DIMENSIONS ARE IN MILLIMETERS (INCHES).
ALL DIMENSIONS ARE ± 0.025 mm UNLESS OTHERWISE SPECIFIED.
Figure 8. Suggested module positioning and panel cut-out for HFBR-53A5VFMZ
Ordering Information
850 nm VCSEL
(SX – Short Wavelength Laser)
HFBR-53A5VEMZ HFBR-53A5VFMZ Extended shield, metal housing.
Flush shield, metal housing.
For product information and a complete list of distributors, please go to our website:
www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2013 Avago Technologies. All rights reserved. Obsoletes AV01-0386EN
AV02-1268EN - March 29, 2013
14.73
(0.58)
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
Avago Technologies:
HFBR-53A5VEMZ
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