Intel® Xeon® E3-1125C v2, E3-1105C v2,
Intel® Pentium® Processor B925C, and
Intel® Core™ i3-3115C Processors for
Communications Infrastructure
- Volume 1 of 2
Supporting:
Intel® Xeon® Processor E3-1125C v2
Intel® Xeon® Processor E3-1105C v2
Intel® Core™ Processor i3-3115C
Intel® Pentium® Processor B925C
Mobile/Desktop 3rd Generation Intel® Core™ Processor Family Datasheet, Volume 2,
completes the documentation set and contains additional product information.
November 2013
Order Number: 329374-002US
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Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
2
Order Number: 329374-002US
Contents—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Contents
1.0
Introduction ............................................................................................................ 10
1.1
Purpose / Scope / Audience ................................................................................ 10
1.2
Related Documents ........................................................................................... 10
1.3
Terminology ..................................................................................................... 12
2.0
Product Overview .................................................................................................... 14
2.1
Processor Feature Details ................................................................................... 16
2.1.1 Supported Technologies .......................................................................... 16
2.2
Interface Features ............................................................................................. 16
2.2.1 System Memory Support ......................................................................... 16
2.2.2 PCI Express* ......................................................................................... 17
2.2.3 Direct Media Interface (DMI).................................................................... 19
2.2.4 Platform Environment Control Interface (PECI) ........................................... 20
2.3
Power Management Support ............................................................................... 20
2.3.1 Processor Core....................................................................................... 20
2.3.2 System ................................................................................................. 20
2.3.3 Memory Controller.................................................................................. 20
2.3.4 PCI Express* ......................................................................................... 20
2.3.5 DMI...................................................................................................... 20
2.4
Thermal Management Support ............................................................................ 20
2.5
Package ........................................................................................................... 21
2.6
Processor Compatibility ...................................................................................... 21
3.0
Interfaces................................................................................................................ 22
3.1
System Memory Interface .................................................................................. 22
3.1.1 System Memory Configurations Supported................................................. 22
3.1.2 System Memory Timing Support............................................................... 25
3.1.3 System Memory Organization Modes......................................................... 26
3.1.4 Rules for Populating Memory Slots ............................................................ 27
3.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA).......... 27
3.1.6 Data Scrambling .................................................................................... 28
3.1.7 DRAM Clock Generation........................................................................... 28
3.1.8 DDR3 Reference Voltage Generation ......................................................... 28
3.2
PCI Express* Interface....................................................................................... 29
3.2.1 PCI Express* Architecture ....................................................................... 29
3.2.2 PCI Express* Configuration Mechanism ..................................................... 31
3.2.3 PCI Express* Port Bifurcation................................................................... 32
3.2.4 PCI Express* Lanes Connection ................................................................ 34
3.2.5 Configuring PCIe* Lanes ......................................................................... 35
3.2.6 Lane Reversal on PCIe* Interface ............................................................. 36
3.3
Direct Media Interface........................................................................................ 36
3.3.1 DMI Error Flow....................................................................................... 36
3.3.2 DMI Link Down ...................................................................................... 36
3.4
Platform Environment Control Interface (PECI) ...................................................... 36
3.5
Interface Clocking ............................................................................................. 37
3.5.1 Internal Clocking Requirements................................................................ 37
4.0
Technologies ........................................................................................................... 39
4.1
Intel® Virtualization Technology .......................................................................... 39
4.1.1 Intel® VT-x Objectives ............................................................................ 39
4.1.2 Intel® VT-x Features .............................................................................. 39
4.1.3 Intel® VT-d Objectives ............................................................................ 40
4.1.4 Intel® VT-d Features .............................................................................. 40
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
3
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—Contents
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.1.5 Intel® VT-d Features Not Supported..........................................................41
Intel® Trusted Execution Technology (Intel® TXT) .................................................41
Intel® Hyper-Threading Technology .....................................................................42
Intel® Advanced Vector Extensions (Intel® AVX)....................................................42
Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) ...................42
4.5.1 PCLMULQDQ Instruction ..........................................................................42
4.5.2 RDRAND Instruction ................................................................................43
Intel® 64 Architecture x2APIC .............................................................................43
Supervisor Mode Execution Protection (SMEP) .......................................................44
Power Aware Interrupt Routing (PAIR)..................................................................44
5.0
Processor SKUs ........................................................................................................45
5.1
SKU Features ....................................................................................................45
6.0
Power Management .................................................................................................46
6.1
ACPI States Supported .......................................................................................47
6.1.1 System States........................................................................................47
6.1.2 Processor Core/Package Idle States...........................................................47
6.1.3 Integrated Memory Controller States .........................................................47
6.1.4 PCIe* Link States ...................................................................................48
6.1.5 DMI States ............................................................................................48
6.1.6 Interface State Combinations ...................................................................48
6.2
Processor Core Power Management ......................................................................49
6.2.1 Enhanced Intel SpeedStep® Technology ....................................................49
6.2.2 Low-Power Idle States.............................................................................49
6.2.3 Requesting Low-Power Idle States ............................................................51
6.2.4 Core C-States ........................................................................................51
6.2.5 Package C-States ...................................................................................53
6.3
IMC Power Management .....................................................................................55
6.3.1 Disabling Unused System Memory Outputs.................................................56
6.3.2 DRAM Power Management and Initialization ...............................................56
6.3.3 DDR Electrical Power Gating (EPG) ............................................................59
6.4
PCIe* Power Management ..................................................................................59
6.5
DMI Power Management .....................................................................................59
6.6
Intel® Rapid Memory Power Management (RMPM) (Also Known as CxSR) .................59
6.7
Thermal Power Management ...............................................................................59
7.0
Thermal Management ..............................................................................................61
7.1
Thermal Considerations ......................................................................................61
7.2
Thermal and Power Specifications ........................................................................62
7.3
Thermal Management Features............................................................................63
7.3.1 Adaptive Thermal Monitor ........................................................................63
7.3.2 Processor Core Specific Thermal Features ..................................................68
7.3.3 Memory Controller Specific Thermal Features .............................................68
7.3.4 Memory Thermal Management..................................................................68
7.3.5 Platform Environment Control Interface (PECI) ...........................................69
8.0
Signal Description ....................................................................................................70
8.1
System Memory Interface ...................................................................................71
8.2
Memory Reference and Compensation ..................................................................73
8.3
Reset and Miscellaneous Signals ..........................................................................74
8.4
PCI Express* Based Interface Signals ...................................................................75
8.5
DMI .................................................................................................................75
8.6
PLL Signals .......................................................................................................75
8.7
TAP Signals.......................................................................................................76
8.8
Error and Thermal Protection...............................................................................77
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
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Contents—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
8.9
8.10
8.11
8.12
9.0
Power Sequencing ............................................................................................. 78
Processor Power and Ground Signals.................................................................... 78
Sense Pins ....................................................................................................... 79
Processor Internal Pull Up/Pull Down.................................................................... 79
Electrical Specifications ........................................................................................... 80
9.1
Power and Ground Pins ...................................................................................... 80
9.2
Decoupling Guidelines ........................................................................................ 80
9.2.1 Voltage Rail Decoupling........................................................................... 80
9.3
Processor Clocking (BCLK, BCLK#) ...................................................................... 81
9.3.1 PLL Power Supply ................................................................................... 81
9.4
Serial Voltage Identification (SVID)...................................................................... 81
9.5
System Agent (SA) Vcc VID ................................................................................ 88
9.6
Reserved or Unused Signals................................................................................ 89
9.7
Signal Groups ................................................................................................... 89
9.8
Test Access Port (TAP) Connection....................................................................... 91
9.9
Storage Conditions Specifications ........................................................................ 91
9.10 DC Specifications .............................................................................................. 92
9.10.1 Voltage and Current Specifications............................................................ 92
9.10.2 Platform Environmental Control Interface DC Specifications ......................... 99
10.0 Processor Ball and Package Information ............................................................... 101
10.1 Processor Ball Assignments............................................................................... 101
10.2 Package Mechanical Information........................................................................ 128
11.0 Processor Configuration Registers ......................................................................... 130
11.1 ERRSTS - Error Status ..................................................................................... 131
11.2 ERRCMD - Error Command ............................................................................... 132
11.3 SMICMD - SMI Command ................................................................................. 132
11.4 SCICMD - SCI Command .................................................................................. 133
11.5 ECCERRLOG0_C0 - ECC Error Log 0 ................................................................... 133
11.6 ECCERRLOG1_C0 - ECC Error Log 1 ................................................................... 135
11.7 ECCERRLOG0_C1 - ECC Error Log 0 ................................................................... 135
11.8 ECCERRLOG1_C1 - ECC Error Log 1 ................................................................... 136
11.9 MAD_DIMM_CH0 - Address Decode Channel 0..................................................... 136
11.10 MAD_DIMM_CH1 - Address Decode Channel 1..................................................... 138
11.11 Error Detection and Correction .......................................................................... 138
Figures
2-1
2-2
3-1
3-2
3-3
3-4
3-5
3-6
6-1
6-2
6-3
6-4
7-1
9-1
Platform Example Block Diagram .......................................................................... 15
Processor Compatibility Diagram .......................................................................... 21
Intel® Flex Memory Technology Operation ............................................................ 27
PCI Express* Layering Diagram............................................................................ 30
Packet Flow through the Layers............................................................................ 30
PCI Express* Related Register Structures .............................................................. 32
PCI Express* PCI Port Bifurcation ......................................................................... 33
PCIe* Typical Operation 16 Lanes Mapping ............................................................ 34
Power States ..................................................................................................... 46
Idle Power Management Breakdown of the Processor Cores ..................................... 50
Thread and Core C-State Entry and Exit ................................................................ 50
Package C-State Entry and Exit ............................................................................ 54
Frequency and Voltage Ordering........................................................................... 64
Example of PECI Host-Client Connection................................................................ 99
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
5
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—Contents
9-2
10-1
10-2
10-3
10-4
10-5
Input Device Hysteresis ..................................................................................... 100
Ball Map (Bottom View, Upper Left Side).............................................................. 124
Ball Map (Bottom View, Upper Right Side)............................................................ 125
Ball Map (Bottom View, Lower Left Side).............................................................. 126
Ball Map (Bottom View, Lower Right Side)............................................................ 127
Processor Mechanical Package ............................................................................ 129
Tables
1-1
1-2
1-3
1-4
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-9
5-1
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
6-11
7-1
7-2
8-1
8-2
8-3
8-4
8-5
8-6
8-7
8-8
8-9
8-10
8-11
8-12
8-13
8-14
9-1
9-2
9-3
9-4
9-5
9-6
Processor Documents ..........................................................................................10
Intel® Communications Chipset 89xx Documents ....................................................10
Public Specifications............................................................................................11
Terminology.......................................................................................................12
Supported UDIMM Module Configurations1, 3 .........................................................23
Supported DDR3/DDR3L SO-DIMM Module Configurations1,2 ...................................24
Supported Maximum Memory Size Per SODIMM ......................................................25
Supported Memory Down Configurations 1 .............................................................25
DDR3 System Memory Timing Support ..................................................................26
Hardware Straps for PCIe* Controller Enabling (Port 1 Only) ....................................35
Hardware Straps for Normal/Reversed Operation of PCIe* Lanes...............................36
Reference Clock..................................................................................................37
Base Features by SKU .........................................................................................45
System States....................................................................................................47
Processor Core/Package State Support ..................................................................47
Integrated Memory Controller States.....................................................................47
PCIe* Link States ...............................................................................................48
DMI States ........................................................................................................48
G, S and C State Combinations.............................................................................48
D, S, and C State Combination .............................................................................48
Coordination of Thread Power States at the Core Level ............................................50
P_LVLx to MWAIT Conversion ...............................................................................51
Coordination of Core Power States at the Package Level...........................................53
Targeted Memory State Conditions........................................................................58
TDP Specifications ..............................................................................................62
Junction Temperature Specification (All SKUs) ........................................................62
Signal Description Buffer Types ............................................................................70
Memory Channel A..............................................................................................71
Memory Channel B..............................................................................................72
Memory Reference and Compensation ...................................................................73
Reset and Miscellaneous Signals ...........................................................................74
PCI Express* Interface Signals .............................................................................75
DMI - Processor to PCH Serial Interface .................................................................75
PLL Signals ........................................................................................................75
TAP Signals........................................................................................................76
Error and Thermal Protection................................................................................77
Power Sequencing ..............................................................................................78
Processor Power Signals ......................................................................................78
Sense Pins .........................................................................................................79
Processor Internal Pull Up/Pull Down .....................................................................79
IMVP7 Voltage Identification Definition ..................................................................81
VCCSA Configuration...........................................................................................88
Signal Groups ....................................................................................................89
Storage Condition Ratings....................................................................................92
Processor Core (VCC) DC Voltage and Current Specifications ....................................93
Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications ...................95
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
6
Order Number: 329374-002US
Contents—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
9-7
9-8
9-9
9-10
9-11
9-12
9-13
10-1
10-2
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications.................. 95
System Agent (VCCSA) Supply DC Voltage and Current Specifications ....................... 95
Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications ...................... 96
DDR3/DDR3L Signal Group DC Specifications ......................................................... 96
Control Sideband and TAP Signal Group DC Specifications........................................ 97
PCI Express* DC Specifications ............................................................................ 98
PECI DC Electrical Limits ................................................................................... 100
Alphabetical Ball Listing..................................................................................... 102
Alphabetical Signal Listing ................................................................................. 113
Register Terminology ........................................................................................ 130
Register Terminology Attribute Modifiers ............................................................. 131
Error Status Register ........................................................................................ 132
Error Command Registers.................................................................................. 132
SMI Command Registers ................................................................................... 133
SCI Command Registers.................................................................................... 133
Channel 0 ECC Error Log 0 ................................................................................ 134
Channel 0 ECC Error Log 1 ................................................................................ 135
Channel 1 ECC Error Log 0 ................................................................................ 135
Channel 1 ECC Error Log 1 ................................................................................ 136
Address Decode Channel 0 ................................................................................ 136
Address Decode Channel 1 ................................................................................ 138
Error Syndrome - ERRSYND............................................................................... 139
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
7
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—Revision History
Revision History
Date
Revision
November 2013
002
Description
SKU table changes
August 2013
001
Initial release
§§
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—1.0
1.0
Introduction
1.1
Purpose / Scope / Audience
This document contains the following processor information:
• DC electrical specifications
• Pinout and signal definitions
• Interface functional descriptions
• Additional product feature information
• Configuration registers pertinent to the implementation and operation of the
processor on its respective platform.
For register details, see the Mobile 3rd Generation Intel® Core™ Processor Family,
Intel® Pentium® Processor Family, and Intel® Celeron® Processor Family Datasheet,
Volume 2 of 2
1.2
Related Documents
See the following documents for additional information.
Table 1-1.
Processor Documents
Document
Mobile 3rd Generation Intel® Core™ Processor Family, Intel® Pentium®
Processor Family, and Intel® Celeron® Processor Family Datasheet, Volume 2
of 2
Table 1-2.
Document Number/
Location
326769 https://wwwssl.intel.com/content/www/
us/en/processors/core/3rdgen-core-family-mobile-vol2-datasheet.html
Intel® Communications Chipset 89xx Documents
Document
Intel® Communications Chipset 89xx Series Datasheet
®
Intel Communications Chipset 89xx Series Thermal/Mechanical Design Guide
(TMDG)
Document Number/
Location
327879
328012
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Datasheet
November 2013
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1.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Table 1-3.
Public Specifications
Document
Document Number/ Location
Advanced Configuration and Power Interface Specification 3.0
http://www.acpi.info/
PCI Local Bus Specification 3.0
http://www.pcisig.com/
specifications
PCI Express Base Specification, Rev. 2.0
http://www.pcisig.com
DDR3 SDRAM Specification
http://www.jedec.org
Intel
•
•
•
•
•
®
64 and IA-32 Architectures Software Developer's Manuals:
Volume
Volume
Volume
Volume
Volume
1: Basic Architecture
2A: Instruction Set Reference, A-M
2B: Instruction Set Reference, N-Z
3A: System Programming Guide
3B: System Programming Guide
http://www.intel.com/products/
processor/manuals/index.htm
• 253665
• 253666
• 253667
• 253668
• 253669
Intel® 64 and IA-32 Architectures Software Developer's Manual
Documentation Changes
http://www.intel.com/content/
www/us/en/architecture-andtechnology/64-ia-32-architecturessoftware-developers-manual.html
Intel® Virtualization Technology Specification for Directed I/O
Architecture Specification
http://download.intel.com/
technology/computing/vptech/
Intel(r)_VT_for_Direct_IO.pdf
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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November 2013
Datasheet
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Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—1.0
1.3
Terminology
Table 1-4.
Terminology (Sheet 1 of 2)
Term
BLT
Description
Block Level Transfer
BMC
Baseboard Management Controller
DDR3
Third-generation Double Data Rate SDRAM memory technology
DMA
Direct Memory Access
DMI
Direct Media Interface
DPC
DIMMs Per Channel
DTS
Digital Thermal Sensor
ECC
Error Correction Code
Enhanced Intel SpeedStep®
Technology
Technology that provides power management capabilities to laptops.
Execute Disable Bit
The Execute Disable bit allows memory to be marked as executable or nonexecutable, when combined with a supporting operating system. If code
attempts to run in non-executable memory the processor raises an error to
the operating system. This feature can prevent some classes of viruses or
worms that exploit buffer overrun vulnerabilities and can thus help improve
the overall security of the system. See the Intel® 64 and IA-32
Architectures Software Developer's Manuals for more detailed information.
EU
Execution Unit
HFM
High Frequency Mode
IMC
Intel
Integrated Memory Controller
®
64 Technology
64-bit memory extensions to the IA-32 architecture
Intel® DPST
Intel® Display Power Saving Technology
Intel® TXT
Intel® Trusted Execution Technology is a versatile set of hardware
extensions to Intel® processors and chipsets that enhance the digital office
platform with security capabilities such as measured launch and protected
execution. Intel® Trusted Execution Technology provides hardware-based
mechanisms that help protect against software-based attacks and protects
the confidentiality and integrity of data stored or created on the client PC.
Intel® VT-d
Intel® Virtualization Technology (Intel® VT) for Directed I/O. Intel® VT-d is
a hardware assist, under system software (Virtual Machine Manager or OS)
control, for enabling I/O device virtualization. Intel VT-d also brings robust
security by providing protection from errant DMAs by using DMA
remapping, a key feature of Intel VT-d.
Intel® Virtualization Technology
Processor virtualization which when used in conjunction with Virtual
Machine Monitor software enables multiple, robust independent software
environments inside a single platform.
IOV
I/O Virtualization
ITPM
Integrated Trusted platform Module
LFM
Low Frequency Mode
NCTF
Non-Critical to Function. NCTF locations are typically redundant ground or
non-critical reserved, so the loss of the solder joint continuity at end of life
conditions will not affect the overall product functionality.
ODT
On-Die termination
PCH
Platform Controller Hub. The new, 2009 chipset with centralized platform
capabilities including the main I/O interfaces along with power
management, manageability, security and storage features.
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Table 1-4.
Terminology (Sheet 2 of 2)
Term
Description
PCLMULQDQ
Single Instruction Multiple Data (SIMD) instruction that computes the 128bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries.
PECI
Platform Environment Control Interface.
Processor
The 64-bit, single-core or multi-core component (package).
Processor Core
The term “processor core” refers to Si die itself which can contain multiple
execution cores. Each execution core has an instruction cache, data cache,
and 256-KB L2 cache. All execution cores share the L3 cache.
PCU
Power Control Unit
Rank
A unit of DRAM corresponding four to eight devices in parallel, ignoring
ECC. These devices are usually, but not always, mounted on a single side of
a DIMM.
SCI
System Control Interrupt. Used in ACPI protocol.
Storage Conditions
A non-operational state. The processor may be installed in a platform, in a
tray, or loose. Processors may be sealed in packaging or exposed to free air.
Under these conditions, processor landings should not be connected to any
supply voltages, have any I/Os biased or receive any clocks. Upon exposure
to “free air” (i.e., unsealed packaging or a device removed from packaging
material) the processor must be handled in accordance with moisture
sensitivity labeling (MSL) as indicated on the packaging material.
SVID
Serial Voltage Identification
System Agent
Consists of all the uncore functions within the processor other than the
cores and cache. This includes the integrated memory controller, PCIe
controller, PCU, etc.
TAC
Thermal Averaging Constant
TDP
Thermal Design Power.
TDC
Thermal Design Current is the maximum current that the VR must be
thermally capable of sustaining indefinitely in the worst-case thermal
environment defined for the platform.
TLP
Transaction Layer Packets
TPM
Trusted Platform Module
VCC
Processor core power supply.
VSS
Processor ground.
VTT
L3 shared cache, memory controller, and processor I/O power rail.
VDDQ
DDR3 power rail.
VCCSA
System Agent (memory controller, DMI and PCIe controllers) power supply
VCCIO
High Frequency I/O logic power supply
VCCPLL
PLL power supply
VLD
Variable Length Decoding
x1
Refers to a Link or Port with one Physical Lane.
x4
Refers to a Link or Port with four Physical Lanes.
x8
Refers to a Link or Port with eight Physical Lanes.
x16
Refers to a Link or Port with sixteen Physical Lanes.
§§
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
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13
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—2.0
2.0
Product Overview
The Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and
Intel® Core™ i3-3115C Processors for Communications Infrastructure is a repackaging
of the 3rd Generation Intel® Core™ Mobile Processor. This document addresses pairing
the Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and
Intel® Core™ i3-3115C Processors for Communications Infrastructure processor with
Intel® Communications Chipset 89xx SeriesPlatform Controller Hub (known as the
PCH). This platform was developed to provide flexible design options, powerful
processor performance, and acceleration services that include Intel® QuickAssist
Technology. Figure 2-1 shows a block diagram of the platform.
This publication provides DC electrical specifications, signaling specifications, pinout
and signal definitions, interface functional descriptions, thermal specifications, and
additional feature information pertinent to the implementation and operation of the
processor.
The processor is offered in a Quad Core or Dual Core 1284-ball FC-BGA (Flip Chip Ball
Grid Array) package. Each of the processor offerings are fully pin-compatible and
provided in the same 37.5 x 37.5 mm FCBGA package size with a ball pitch of
1.016 mm. The processor is a 64-bit, multi-core processor built on 22-nanometer
process technology. It supports DDR3/DDR3L with Error Correction Code (ECC) and up
to 20 PCI Express* lanes. The processor is based on Intel® micro-architecture and is
designed for a two-chip platform.
Included in the processor is an integrated memory controller (IMC) and integrated I/O
(PCI Express* and DMI) on a single silicon die. This single die solution is known as a
monolithic processor. The integration of the memory and PCI Express* controllers into
the processor silicon will benefit I/O intensive applications in the communications
segments.
Note:
Some processor features are not available on all platforms. See Table 5-1 for list of
processor SKUs.
Note:
The processors for this platform do not include the Integrated Display Engine or the
Graphics Processor Unit (GPU). Disregard references to graphics and Intel® Turbo
Boost in the Mobile 3rd Generation Intel® Core™ Processor Family, Intel® Pentium®
Processor Family, and Intel® Celeron® Processor Family Datasheet, Volume 2 of 2.
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
14
Order Number: 329374-002US
Ch B
XDP0
Ch A
Clock IC
CK420BQ
DRAM
DDR3 (Ch B)
PS2
37.5x37.5
1284 balls
Processor
x4 DMI
DRA
SIO
M
SERIAL
SMBus
PECI
PCIe Gen1 x1
PCIe Gen1 x1
PCIe Gen1 x1
PCIe Gen1 x1
PCIe Gen2 x4
2
PCH
LPC
3.0Gbs
SATA
480Mbs
USB
1.25Gbs/lane
SGMII
SPI
PCIe Gen2
PCIe Gen3
Port
80
TPM
2 SATA
Conn(s)
USB
PCH
JTAG
4 ports – Rear
Panel
2 ports – Front
HDR.
System BIOS
FLASH
FLASH (2 Devices)
QUAD
GbE
PHY
PCH ITP
XDP1
GbE
DDR3 (Ch A)
PCIe Gen3/Gen2 x16
GbE
GbE
Figure 2-1.
GbE
1066, & 1333MTS.
2.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Platform Example Block Diagram
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
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Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—2.0
2.1
Processor Feature Details
• Four, two, or single execution cores (4C, 2C, or 1C respectively)
• 32-KB data first-level cache (L1) for each core, parity protected
• 32-KB instruction first-level cache (L1) for each core, ECC protected
• 256-KB shared instruction/data second-level cache (L2) for each core, ECC
protected
• Up to 8-MB shared instruction/data third-level cache (L3) across all cores, ECC
protected
2.1.1
Supported Technologies
• Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
• Intel® Virtualization Technology (Intel® VT-x)
• Intel® Trusted Execution Technology (Intel® TXT)
• Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
• Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
• Intel® Hyper-Threading Technology
• Intel® 64 Architecture
• Execute Disable Bit
• Intel® Advanced Vector Extensions (Intel® AVX)
• Advanced Encryption Standard New Instructions (AES-NI)
• PCLMULQDQ Instruction
• RDRAND instruction for random number generation
• SMEP – Supervisor Mode Execution Protection
• PAIR – Power Aware Interrupt Routing
2.2
Interface Features
2.2.1
System Memory Support
• One or two channels of DDR3/DDR3L memory with a maximum of two UDIMMs or
two SO-DIMMs per channel
• ECC Memory Down topology of up to eighteen x8 SDRAM devices per channel
• Non-ECC Memory Down topology of up to eight x16 DDR3/DDR3L SDRAM devices
per channel
• Single- and dual-channel memory organization modes
• Memory capacity supported from 512 MB up to 32 GB
• Using 4-Gb device technologies, the largest total memory capacity possible is
32 GB, assuming Dual Channel Mode with four x8, double-sided, dual-ranked
unbuffered DIMM memory configuration
• 1-Gb, 2-Gb, and 4-Gb DDR3/DDR3L DRAM technologies are supported for x8 and
x16 devices
• Processor on-die Reference Voltage (VREF) generation for both DDR3 Read
(RDVREF) and Write (VREFDQ)
• Data burst length of eight for all memory organization modes
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
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2.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
• Memory DDR3/DDR3L data transfer rates of 1333 MT/s and 1600 MT/s.
• 72-bit wide channels, 64-bit data + 8-bit ECC
• 64-bit wide channels, without ECC option
• System Memory Interface I/O Voltage of 1.35V and 1.5V
• DDR3 and DDR3L DIMMs/DRAMs running at 1.5V
• DDR3L DIMMs/DRAMs running at 1.35V
• Supports memory configurations that mix DDR3 DIMMs/DRAMs with DDR3L
DIMMs/DRAMs running at 1.5V
• Supports ECC and non-ECC, unbuffered DDR3 DIMMs
— Mixing of ECC and Non-ECC DIMMS is not supported
• Theoretical maximum memory bandwidth of:
— 21.3 GB/s in dual-channel mode assuming DDR3 1333 MT/s
— 25.6 GB/s in dual-channel mode assuming DDR3 1600 MT/s
• Up to 64 simultaneous open pages, 32 per channel (assuming 8 ranks of 8 bank
devices)
• Memory organizations:
— Single-channel modes
— Dual-channel modes - Intel® Flex Memory Technology: Dual-channel
symmetric (Interleaved)
• Command launch modes of 1n/2n
• On-Die Termination (ODT)
• Intel® Fast Memory Access (Intel® FMA):
— Just-in-Time Command Scheduling
— Command Overlap
— Out-of-Order Scheduling
2.2.2
PCI Express*
The PCI Express* Port 1 is fully-compliant to the PCI Express Base Specification, Rev.
3.0 including support for 8.0 GT/s transfer speeds.
The PCI Express* Port 2 is fully-compliant to the PCI Express Base Specification, Rev.
2.0 including support for 5.0 GT/s transfer speeds.
Ivy Bridge Gladden processor with Cave Creek PCH configurations:
Configuration 1
— One 16-lane PCI Express* port intended to connect Processor Root Port to
EndPoint
— One 4-lane PCI Express* port intended for I/O
— Four single-lane PCI Express* ports intended for I/O via the PCH
Configuration 2
— One 8-lane PCI Express* port intended to connect Processor Root Port to
EndPoint
— One 8-lane PCI Express* port intended for I/O
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
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17
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—2.0
— One 4-lane PCI Express* port intended for I/O
— Four single-lane PCI Express* ports intended for I/O via the PCH
Configuration 3
— One 4-lane PCI Express* port intended to connect Processor Root Port to
EndPoint
— Three 4-lane PCI Express* port intended for I/O
— Four single-lane PCI Express* ports intended for I/O via the PCH
• PCI Express* 1 x16 port is mapped to PCI Device 1.
— One 16-lane/Two 8-lane/One 8-lane and Two 4-lane PCI Express* port
• PCI Express* 1 x4 port is mapped to PCI Device 6.
• The port may negotiate down to narrower widths.
— Support for x16/x8/x4/x1 widths for a single PCI Express* mode.
• 2.5 GT/s 5.0 GT/s and 8.0 GT/s PCI Express* frequencies are supported.
• Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 4 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.
• Gen2 Raw bit-rate on the data pins of 5.0 Gb/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 8 GB/s in each direction
simultaneously, for an aggregate of 8 GB/s when x16 Gen 2.
• Gen 3 raw bit-rate on the data pins of 8.0 GT/s, resulting in a real bandwidth per
pair of 800 MB/s using 128b/130b encoding to transmit data across this interface.
This also does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on the interface of 16 GB/s in each direction
simultaneously, for an aggregate of 32 GB/s when x16 Gen 3.
• Hierarchical PCI-compliant configuration mechanism for downstream devices.
• Traditional PCI style traffic (asynchronous snooped, PCI ordering).
• PCI Express* extended configuration space. The first 256 bytes of configuration
space aliases directly to the PCI Compatibility configuration space. The remaining
portion of the fixed 4-KB block of memory-mapped space above that (starting at
100h) is known as extended configuration space.
• PCI Express* Enhanced Access Mechanism. Accessing the device configuration
space in a flat memory mapped fashion.
• Automatic discovery, negotiation, and training of link out of reset.
• Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).
• Peer segment destination posted write traffic (no peer-to-peer read traffic) in
Virtual Channel 0:
— DMI -> PCI Express* Port 1
— DMI -> PCI Express* Port 2
— PCI Express* Port 1 -> DMI
— PCI Express* Port 2 -> DMI
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
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2.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Re-issues configuration cycles that have been previously completed with the
Configuration Retry status.
• PCI Express* reference clock is 100-MHz differential clock.
• Power Management Event (PME) functions.
• Dynamic width capability
• Message Signaled Interrupt (MSI and MSI-X) messages.
• Polarity inversion.
• Static lane numbering reversal
— Does not support dynamic lane reversal, as defined (optional) by the PCI
Express Base Specification, Rev. 2.0.
• Supports Half Swing “low-power/low-voltage” mode.
Note:
The processor does not support PCI Express* Hot-Plug.
2.2.3
Direct Media Interface (DMI)
• DMI 2.0 support.
• Four lanes in each direction.
• 2.5 GT/s and 5.0 GT/s DMI interface to PCH
• Gen1 Raw bit-rate on the data pins of 2.5 GT/s, resulting in a real bandwidth per
pair of 250 MB/s given the 8b/10b encoding used to transmit data across this
interface. Does not account for packet overhead and link maintenance.
• Gen2 Raw bit-rate on the data pins of 5.0 GT/s, resulting in a real bandwidth per
pair of 500 MB/s given the 8b/10b encoding used to transmit data across this
interface. Does not account for packet overhead and link maintenance.
• Maximum theoretical bandwidth on interface of 2 GB/s in each direction
simultaneously, for an aggregate of 4 GB/s when DMI x4.
• Shares 100-MHz PCI Express* reference clock.
• 64-bit downstream address format, but the processor never generates an address
above 64 GB (Bits 63:36 will always be zeros).
• 64-bit upstream address format, but the processor responds to upstream read
transactions to addresses above 64 GB (addresses where any of Bits 63:36 are
nonzero) with an Unsupported Request response. Upstream write transactions to
addresses above 64 GB will be dropped.
• Supports the following traffic types to or from the PCH:
— DMI -> DRAM
— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)
— Processor core -> DMI
• APIC and MSI interrupt messaging support:
— Message Signaled Interrupt (MSI and MSI-X) messages
• Downstream SMI, SCI and SERR error indication.
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
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19
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—2.0
• Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters.
• DC coupling – no capacitors between the processor and the PCH.
• Polarity inversion.
• PCH end-to-end lane reversal across the link.
• Supports Half Swing “low-power/low-voltage”.
2.2.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (the processor) and a PECI master. The processors support the PECI 3.0
Specification.
2.3
Power Management Support
2.3.1
Processor Core
• Full support of ACPI C-states as implemented by the following processor C-states:
C0, C1, C1E, C3, C6, C7
• Enhanced Intel SpeedStep® Technology
2.3.2
System
Full support of the ACPI S-states as implemented by system S-states S0, S3, S4, S5
2.3.3
Memory Controller
• Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))
• Dynamic power-down
2.3.4
PCI Express*
• L0s and L1 ASPM power management capability
2.3.5
DMI
• L0s and L1 ASPM power management capability
2.4
Thermal Management Support
• Digital Thermal Sensor
• Intel® Adaptive Thermal Monitor
• THERMTRIP# and PROCHOT# support
• On-Demand Mode
• Open and Closed Loop Throttling
• Memory Thermal Throttling
• External Thermal Sensor (TS-on-DIMM and TS-on-board)
• Fan speed control with DTS
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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2.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
2.5
Package
• The processor is available in one package size:
— A 37.5 x 37.5 mm 1284-ball FCBGA package (BGA1284)
— 1.016 mm ball pitch
2.6
Processor Compatibility
The 3rd Generation Intel® Core™ Processor For Communications Infrastructure family
has specific platform requirements that differentiate it from a 2nd Generation Intel®
Core™ Processor For Communications Infrastructure family. Platforms that are to
support both processor families need to address the platform compatibility
requirements detailed in Figure 2-2.
VCCIO
VR
Processor Compatibility Diagram
VDDQ
VR
VCore
VR
DDR3
DDR3/3L
SVID
Figure 2-2.
PCIe*
Gen 1, 2, 3
VCCSA
VR
PEG AC Coupling
PEG Gen 1,2 – 100 nF
PEG Gen 1,2,3 – 220 nF
2G_Core: 1.5 V
3G_Core: 1.5 V or
1.35 V
2G_Core: 1.05 V
3G_Core: 1.05 V
Processor
VCCSA_VID
PROC_SELECT#
Notes:
1.
2G_Core = 2nd Generation Intel® Core™ Processor For Communications Infrastructure
2.
3G_Core = 3rd Generation Intel® Core™ Processor For Communications Infrastructure
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
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21
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—3.0
3.0
Interfaces
This chapter describes the interfaces supported by the processor.
3.1
System Memory Interface
3.1.1
System Memory Configurations Supported
The Integrated Memory Controller (IMC) of the processor supports DDR3/DDR3L
protocols with two independent, 72-bit wide channels. These two memory channels are
capable of running speeds up to 1600 MT/s. Each channel consists of 64 data and 8
ECC bits. In the dual-channel configuration, it supports DIMMs on both channels, or
DIMMs on one channel and memory down configuration on the other channel, or
memory down configuration on both channels. The processor supports up to two
DIMMs per channel.
Note:
Very Low Profile (VLP) UDIMMs are supported wherever UDIMMs are supported.
However, VLP UDIMMs have not been fully validated.
Note:
Mixing of ECC and Non-ECC DIMMs is not supported.
• DDR3/DDR3L at 1.5 V Data Transfer Rates:
— 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)
• DDR3L at 1.35 V Data Transfer Rates:
— 1333 MT/s (PC3-10600), 1600 MT/s (PC3-12800)
• DDR3/DDR3L DRAM Device Technology:
— Standard 1-Gb, 2-Gb, and 4-Gb technologies and addressing are supported for
x16 and x8 devices. There is no support for memory modules with different
technologies or capacities on opposite sides of the same memory module. If
one side of a memory module is populated the other side is either identical or
empty.
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
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3.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
3.1.1.1
UDIMM Configurations
This section describes the UDIMM modules supported. The following DDR3/DDR3L Data
Transfer Rates are supported:
• 1333 MT/s (PC3-10600), and 1600 MT/s (PC3-12800)
• DDR3/DDR3L UDIMM Modules:
— Raw Card A - Single Sided x8 unbuffered non-ECC
— Raw Card B - Double Sided x8 unbuffered non-ECC
— Raw Card C - Single Sided x16 unbuffered non-ECC
— Raw Card D - Single Sided x8 unbuffered ECC
— Raw Card E - Double Sided x8 unbuffered ECC
Table 3-1.
Raw
Card
Version
Supported UDIMM Module Configurations1, 3
DIMM
Capacity
DRAM Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of Row/
Col Address
Bits
# of
Banks
Inside
DRAM
Page Size
Unbuffered/Non-ECC Supported DIMM Module Configurations
A
B
C
1 GB
1 Gb
128 M X 8
8
2
14/10
8
8K
2 GB
2 Gb
128 M X 16
16
2
14/10
8
16 K
2 GB
1 Gb
128 M X 8
16
2
14/10
8
8K
4 GB
2 Gb
256 M X 8
16
2
15/10
8
8K
8 GB
4Gb
512 M X 8
16
2
16/10
8
8K
512 MB
1 Gb
64 M X 16
4
1
13/10
8
16 K
1 GB
2 Gb
128 M X 16
4
1
14/10
8
16 K
Unbuffered/ECC Supported DIMM Module Configurations
D
E
1 GB
1 Gb 2
128 M X 8
9
1
14/10
8
8K
2 GB
2 Gb 2
256 M X 8
9
1
15/10
8
8K
2 GB
1 Gb
128 M X 8
18
2
14/10
8
8K
4 GB
2 Gb
256 M X 8
18
2
15/10
8
8K
8 GB
4 Gb
512 M X 8
18
2
16/10
8
8K
Notes:
1.
DIMM module support is based on availability and is subject to change
2.
Supported but not fully validated.
3.
Interface does not support DDR3U DIMMs.
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—3.0
3.1.1.2
SO-DIMM Configurations
The processor supports SO-DIMM and ECC SO-DIMM designs. Table 3-2 details the SODIMM modules that are supported. However, these have not been fully validated.
Table 3-2.
Raw
Card
Version
Supported DDR3/DDR3L SO-DIMM Module Configurations1,2
DIMM
Capacity
DRAM Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of
Row/Col
Address
Bits
# of
Banks
Inside
DRAM
Page Size
Unbuffered/Non-ECC Supported SO-DIMM Module Configurations
A
B
C
F
1 GB
1 Gb
64 M X 16
8
2
13/10
8
8K
2 GB
2 Gb
128 M X 16
8
2
14/10
8
8K
4 GB
4 Gb
256 M X 16
8
2
15/10
8
8K
1 GB
1 Gb
128 M X 8
8
1
14/10
8
8K
2GB
2 Gb
256 M X 8
8
1
15/10
8
8K
4 GB
4 Gb
512 M X 8
8
1
16/10
8
8K
512 MB
1 Gb
64 M X 16
4
1
13/10
8
8K
1 GB
2 Gb
128 M X 16
4
1
14/10
8
8K
2 GB
4 Gb
256 M X 16
4
1
15/10
8
8K
2 GB
1 Gb
128 M X 8
16
2
14/10
8
8K
4 GB
2 Gb
256 M X 8
16
2
15/10
8
8K
4 Gb
512 M X 8
16
2
16/10
8
8K
8 GB
Unbuffered/ECC Supported SO-DIMM Module Configurations
D
E
Notes:
1.
2.
3.
4.
1 GB
1 Gb
128 M X 8
9
1
14/10
8
8K
2 GB
2 Gb
256 M X 8
9
1
15/10
8
8K
2 GB
1 Gb
128 M X 8
18
2
14/10
8
8K
4 GB
2 Gb
256 M X 8
18
2
15/10
8
8K
8 GB
4 Gb
512 M X 8
18
2
16/10
8
8K
DIMM module support is based on availability and is subject to change.
Interface does not support DDR3U SO-DIMMs.
Supported, but not fully validated on Intel® Xeon® and Intel® Core Processors for Communication Infrastructure.
Fully validated on 2nd Generation Intel® Core™ Mobile Processor
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3.1.1.3
Supported Maximum Memory Size Per SODIMM
Table 3-3.
Supported Maximum Memory Size Per SODIMM
Max Size Per Configuration [GB]
Memory
Max Size per
DIMM [GB]
SODIMM RC A
1 Ch
1 DPC
1 Ch
2 DPC
2 Ch
1 DPC
2 Ch
2 DPC
4
4
8
8
16
SODIMM RC B
4
4
8
8
16
SODIMM RC C
2
2
4
4
8
SODIMM RC F
8
8
16
16
32
3.1.1.4
Memory Down Configurations
The processor supports the following Memory Down configurations.
Table 3-4.
Raw Card
Equivalent
Supported Memory Down Configurations 1
Memory
Capacity
DRAM
Device
Technology
DRAM
Organization
# of
DRAM
Devices
# of
Physical
Device
Ranks
# of
Row/Col
Address
Bits
# of
Banks
Inside
DRAM
Page Size
Unbuffered/Non-ECC Supported Memory Down Configurations
A
B
C
F
1 GB
1 Gb 2
64 M X 16
8
2
13/10
8
8K
2 GB
2 Gb 2
128 M X 16
8
2
14/10
8
8K
1 GB
1 Gb
2
128 M X 8
8
1
14/10
8
8K
2GB
2 Gb 2
256 M X 8
8
1
15/10
8
8K
512 MB
1 Gb
2
64 M X 16
4
1
13/10
8
8K
128 M X 16
4
1
14/10
8
8K
2 GB
1 Gb
2
128 M X 8
16
2
14/10
8
8K
4 GB
2 Gb 2
256 M X 8
16
2
15/10
8
8K
8 GB
2
512 M X 8
16
2
16/10
8
8K
1 GB
2 Gb 2
4 Gb
Unbuffered/ECC Supported Memory Down Configurations
D
E
1 GB
1 Gb 2
128 M X 8
9
1
14/10
8
8K
2 GB
2 Gb 2
256 M X 8
9
1
15/10
8
8K
2 GB
1 Gb
2
128 M X 8
18
2
14/10
8
8K
4 GB
2 Gb 2
256 M X 8
18
2
15/10
8
8K
8 GB
2
512 M X 8
18
2
16/10
8
8K
4 Gb
Notes:
1.
Interface does not support memory devices running DDR3U (1.25 V) Voltage Levels.
2.
Supported, but not fully validated.
3.1.2
System Memory Timing Support
The processor supports the following DDR3/DDR3L Speed Bin, CAS Write Latency
(CWL), and command signal mode timings on the main memory interface:
• tCL = CAS Latency
• tRCD = Activate Command to READ or WRITE Command delay
• tRP = PRECHARGE Command Period
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• CWL = CAS Write Latency
• Command Signal modes = 1n indicates a new command may be issued every clock
and 2n indicates a new command may be issued every 2 clocks. Command launch
mode programming depends on the transfer rate and memory configuration.
Table 3-5.
DDR3 System Memory Timing Support
Processor
SKUs
DIMMs Per
Channel
(DPC)
Transfer
Rate
(MT/s)
tCL
(tCK)
tRCD
(tCK)
tRP
(tCK)
CWL
(tCK)
1333
9
9
9
7
1600
11
11
11
8
1
4-Core or 2Core SKUs
2
1
Note:
3.1.3
CMD
Mode
1N/2N
2N
1N/2N
System memory timing support is based on availability and is subject to change.
System Memory Organization Modes
The processor supports two memory organization modes, single-channel and dualchannel. Depending upon how the DIMM Modules are populated in each memory
channel, a number of different configurations can exist.
3.1.3.1
Single-Channel Mode
In this mode, all memory cycles are directed to a single-channel. Single-channel mode
is used when either Channel A or Channel B DIMM connectors are populated in any
order, but not both.
3.1.3.2
Dual-Channel Mode - Intel® Flex Memory Technology Mode
The processor supports Intel® Flex Memory Technology Mode. Memory is divided into a
symmetric and an asymmetric zone. The symmetric zone starts at the lowest address
in each channel and is contiguous until the asymmetric zone begins or until the top
address of the channel with the smaller capacity is reached. In this mode, the system
runs with one zone of dual-channel mode and one zone of single-channel mode,
simultaneously, across the whole memory array.
Note:
Channels A and B can be mapped for physical channels 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
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Figure 3-1.
Intel® Flex Memory Technology Operation
TOM
C
N o n in te r le a v e d
access
B
C
D ual channel
in te r le a v e d a c c e s s
B
B
CH A
CH B
B
B – T h e la rg e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o ry m o d u le
C – T h e r e m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la rg e r s iz e m e m o ry m o d u le
3.1.3.2.1
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, IMC
operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
3.1.4
Rules for Populating Memory Slots
In all modes, the frequency of system memory is the lowest frequency of all memory
modules placed in the system, as determined through the SPD registers on the
memory modules. The system memory controller supports one or two DIMM
connectors per channel. The usage of DIMM modules with different latencies is allowed.
For dual-channel modes both channels must have a DIMM connector populated and for
single-channel mode only a single-channel can have an DIMM connector populated.
3.1.5
Technology Enhancements of Intel® Fast Memory Access
(Intel® FMA)
The following sections describe the Just-in-Time Scheduling, Command Overlap, and
Out-of-Order Scheduling Intel® FMA technology enhancements.
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3.1.5.1
Just-in-Time Command Scheduling
The memory controller has an advanced command scheduler where all pending
requests are examined simultaneously to determine the most efficient request to be
issued next. The most efficient request is picked from all pending requests and issued
to system memory Just-in-Time to make optimal use of Command Overlapping. Thus,
instead of having all memory access requests go individually through an arbitration
mechanism forcing requests to be executed one at a time, they can be started without
interfering with the current request allowing for concurrent issuing of requests. This
allows for optimized bandwidth and reduced latency while maintaining appropriate
command spacing to meet system memory protocol.
3.1.5.2
Command Overlap
Command Overlap allows the insertion of the DRAM commands between the Activate,
Precharge, and Read/Write commands normally used, as long as the inserted
commands do not affect the currently executing command. Multiple commands can be
issued in an overlapping manner, increasing the efficiency of system memory protocol.
3.1.5.3
Out-of-Order Scheduling
While leveraging the Just-in-Time Scheduling and Command Overlap enhancements,
the IMC continuously monitors pending requests to system memory for the best use of
bandwidth and reduction of latency. If there are multiple requests to the same open
page, these requests would be launched in a back to back manner to make optimum
use of the open memory page. This ability to reorder requests on the fly allows the IMC
to further reduce latency and increase bandwidth efficiency.
3.1.5.4
Memory Type Range Registers (MTRRs) Enhancement
In this processor there are additional 2 MTRRs (total 10 MTRRs). These additional
MTRRs are especially important in supporting system memory beyond 4 GB.
3.1.6
Data Scrambling
The memory controller incorporates a DDR3 Data Scrambling feature to minimize the
impact of excessive di/dt on the platform DDR3 VRs due to successive 1's and 0's on
the data bus. Past experience has demonstrated that traffic on the data bus is not
random and can have energy concentrated at specific spectral harmonics creating high
di/dt which is generally limited by data patterns that excite resonance between the
package inductance and on die capacitances. As a result the memory controller uses a
data scrambling feature to create pseudo-random patterns on the DDR3 data bus to
reduce the impact of any excessive di/dt.
3.1.7
DRAM Clock Generation
Every supported DIMM has two differential clock pairs. There are total of four clock
pairs driven directly by the processor to two DIMMs.
3.1.8
DDR3 Reference Voltage Generation
The processor memory controller has the capability of generating the DDR3 Reference
Voltage (VREF) internally for both read (RDVREF) and write (VREFDQ) operations. The
generated VREF can be changed in small steps, and an optimum VREF value is
determined for both during a cold boot through advanced DDR3 training procedures in
order to provide the best voltage and signal margins.
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3.2
PCI Express* Interface
This section describes the PCI Express* interface capabilities of the processor. See the
PCI Express Base Specification for PCI Express* details. The processor has a total of 20
PCI Express* lanes. Port 1 lanes are fully compliant with PCI Express Base
Specification, Rev. 3.0. Port 2 lanes are fully compliant with PCI Express Base
Specification, Rev. 2.0. This section will discuss how these 20 PCI Express* lanes can
be utilized in various configurations on the platform.
The processor has four PCI Express* controllers that can be independently configured
to either Gen 1, Gen 2, or Gen 3 allowing operation at 2.5 GT/s (giga-transfers per
second) 5.0 GT/s or 8.0 GT/s data rates. These four PCIe* devices operate
simultaneously which are configurable in the following combinations:
• 1 x16 PCI Express* port with 1 x4 PCI Express port
• 2 x8 PCI Express* ports with 1 x4 PCI Express* port
• 1 x8 PCI Express* ports with 3 x4 PCI Express* ports
3.2.1
PCI Express* Architecture
Compatibility with the PCI addressing model is maintained to ensure that all existing
applications and drivers operate unchanged.
The PCI Express* configuration uses standard mechanisms as defined in the PCI
Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in
2.5 Gb/s/direction, which provides a 250 MB/s communications channel in each
direction (500 MB/s total), nearly twice the data rate of classic PCI. The fact that 8b/
10b encoding is used accounts for the 250 MB/s where quick calculations would imply
300 MB/s.
PCI Express* Port 1 supports Gen 3 speed. At 8 GT/s, Gen 3 operation results in twice
as much bandwidth per lane as compared to the Gen 2 operation. The 16-lane PCI
Express * port can operate at 2.5 GT/s, 5 GT/s, or 8 GT/s.
PCI Express* Port 2 supports Gen 2 speed. At 5.0 GT/s, Gen 2 operation results in
double the bandwidth per lane as compared to Gen 1 operation. When operating with
two PCI Express* controllers, each controller can operate at 2.5 GT/s or 5.0 GT/s.
PCI Express* Gen 3 uses a 128/130b encoding scheme, eliminating nearly all of the
overhead of the 8b/10b encoding as much bandwidth per lane as compared to the
Gen 1 operation.
The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link
Layer, and Physical Layer. The partitioning in the component is not necessarily along
these same boundaries. See Figure 3-2 for the PCI Express* layering diagram.
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Figure 3-2.
PCI Express* Layering Diagram
PCI Express* uses packets to communicate information between components. Packets
are formed in the Transaction and Data Link Layers to carry the information from the
transmitting component to the receiving component. As the transmitted packets flow
through the other layers, they are extended with additional information necessary to
handle packets at those layers. At the receiving side, the reverse process occurs and
packets get transformed from their Physical Layer representation to the Data Link
Layer representation and finally (for Transaction Layer Packets) to the form that can be
processed by the Transaction Layer of the receiving device.
Figure 3-3.
Packet Flow through the Layers
3.2.1.1
Transaction Layer
The upper layer of the PCI Express* architecture is the Transaction Layer. The
Transaction Layer's primary responsibility is the assembly and disassembly of
Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as
read and write, as well as certain types of events. The Transaction Layer also manages
flow control of TLPs.
3.2.1.2
Data Link Layer
The middle layer in the PCI Express* stack, the Data Link Layer, serves as an
intermediate stage between the Transaction Layer and the Physical Layer.
Responsibilities of Data Link Layer include link management, error detection, and error
correction.
The transmission side of the Data Link Layer accepts TLPs assembled by the
Transaction Layer, calculates and applies data protection code and TLP sequence
number, and submits them to Physical Layer for transmission across the Link. The
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receiving Data Link Layer is responsible for checking the integrity of received TLPs and
for submitting them to the Transaction Layer for further processing. On detection of TLP
error(s), this layer is responsible for requesting retransmission of TLPs until information
is correctly received, or the Link is determined to have failed. The Data Link Layer also
generates and consumes packets which are used for link management functions.
3.2.1.3
Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and
input buffers, parallel-to-serial, and serial-to-parallel conversion, PLL(s), and
impedance matching circuitry. It also includes logical functions related to interface
initialization and maintenance. The Physical Layer exchanges data with the Data Link
Layer in an implementation-specific format, and is responsible for converting this to an
appropriate serialized format and transmitting it across the PCI Express* Link at a
frequency and width compatible with the remote device.
3.2.2
PCI Express* Configuration Mechanism
All of the PCI Express* controllers are mapped through a PCI-to-PCI bridge structure.
PCI Express* extends the configuration space to 4096 bytes per-device/function, as
compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express*
configuration space is divided into a PCI-compatible region (that consists of the first
256 bytes of a logical device’s configuration space) and an extended PCI Express*
region (that consists of the remaining configuration space). The PCI-compatible region
can be accessed using either the mechanisms defined in the PCI specification of using
the enhanced PCI Express configuration access mechanism described in the PCI
Express Enhanced Configuration Mechanism section.
The PCI Express* Host Bridge is required to translate the memory-mapped PCI
Express* configuration space accesses from the host processor to PCI Express
configuration cycles. To maintain compatibility with PCI configuration addressing
mechanisms, it is recommended that systems software access the enhanced
configuration space using 32-bit operation (32-bit aligned) only. See the PCI Express*
Base Specification for details of both the PCI-compatible and PCI Express* Enhanced
configuration mechanisms and transaction rules.
The controllers for the 16 lanes (Port 1) are mapped to the root port of Device 1:
• The x16 controller is mapped to Function 0
• The x8 controller is mapped to Function 1
• The x4 controller is mapped to Function 2
The additional x4 controller (Port 2) is PCIe* Gen1/Gen2 compatible and is mapped to
Device 6 Function 0.
Three of the four controllers create Port 1 and can automatically operate on lower lane
width modes allowing up to three simultaneous operating devices on these 16 lanes.
Bifurcation details are described in Section 3.2.3, “PCI Express* Port Bifurcation”, and
the hardware straps required to enable the x16, x8 and the x4 controllers are described
in Section 3.2.4, “PCI Express* Lanes Connection”.
The fourth controller is a single dedicated controller, which creates the x4 Port 2 that
enumerates on Device 6. Port 2 can be configured to operate in 1x4, 1x2, or 1x1 mode,
but there are no hardware straps.
Note:
The controllers in Port 1 cannot be used to function with the controller in Port 2.
Therefore, the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2.
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Figure 3-4.
PCI Express* Related Register Structures
PCI Express
Device
Port 1
PCI Express
Device
Port 2
PCI-PCI Bridge
representing root
PCI Express port
(Device 1)
(Function 0,1,2)
PCI Compatible
Host Bridge Device
(Device 0)
PCI-PCI Bridge
representing root
PCI Express port
(Device 6)
DMI
3.2.3
PCI Express* Port Bifurcation
Only the three controllers on Port 1 can be bifurcated. When bifurcated, the wires which
had previously been assigned to lanes [15:8] of the single x16 primary port are
reassigned to lanes [7:0] of the x8 secondary controller (Function 1). This assignment
applies whether the lane numbering is reversed or not. Further bifurcation of Port 1 is
possible through the third contoller (Function 2) to create two x4 PCI Express*.
When Port 1 is not bifurcated, Function 1 and Function 2 are hidden from the discovery
mechanism used in PCI enumeration.
The controls for Port 2 and the associated virtual PCI-to-PCI bridge can be found in PCI
Device 6, which provides an additional x4 port.
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Figure 3-5.
PCI Express* PCI Port Bifurcation
Port 1
Port 2
PCIe
PCIe
Transaction
Transaction
Link
Link
Physical
Physical
0 …7
8 …11
124…7
… 15
0 …3
X8
X8
X4
X4
X4
X4
X4
Port 1a
Port 1b
Port 1c
X8
X8
X8X8
Port 1a
Port 1b
Port 2
X16
Port 1
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3.2.4
PCI Express* Lanes Connection
Figure 3-6 demonstrates the PCIe* lanes mapping.
Figure 3-6.
PCIe* Typical Operation 16 Lanes Mapping
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3.2.5
Configuring PCIe* Lanes
Note:
The controllers in Port 1 cannot be used to function with the controller in Port 2.
Therefore, the x16 lanes of Port 1 must not be combined with the x4 lanes of Port 2.
The following details apply to the three controllers in Port 1; Port 2 cannot be
bifurcated.
The configuration of the PCIe* bus is statically determined by the pre-boot software
prior to initialization. The pre-boot software determines the configuration by looking at
the two configuration pins, CFG[6:5], that determine whether the additional two
controllers of the 16 lanes need to be enabled or not. These strap values are read upon
power up and the pre-boot software enables the appropriate number of controllers in
use as follows:
Table 3-6.
Hardware Straps for PCIe* Controller Enabling (Port 1 Only)
CFG [6:5]
Mode
00
1x8 +2x4
01
Reserved
10
2x8
11 (default)
1x16
No strapping is required to enable the additional four lanes (lanes [16-19]) in any of
the permissible modes because it has a single dedicated controller.
The CFG[6:5] inputs have a default value of [1:1] if they are not terminated on the
board. By default, a single x16 controller is enabled. When a logic 0 is required on the
strap, it is recommended that they be pulled down to ground with a 1 K Ohm resistor.
Note:
If the x16 controller is enabled by the hardware strapping and a x8 device is plugged
in, the controller automatically operates in the x8 mode. The same is true for any
controller that is connected to a device operating at narrower lane widths.
Hot plug is not supported on these PCIe* interfaces. If a device is not present at power
up, it is not detected when it is plugged in after power up. The strap values are read
upon power up and the pre-boot software enables the appropriate controller based on
the value read on CFG[6:5]. Hence, if a device of lower lane width than the width of the
controller that is enabled is plugged in before power up, then it is automatically
detected. But if a device with higher lane width is plugged in, then the device is not
detected. The same is true for the number of controllers enabled. If a single controller
is enabled at power up, then a single device of any width equal to or lower than the
width of the controller is detected.
For example, if upon power up, the value on CFG [6:5] is [1:1], then the 1x16
controller is enabled. A single device of width x16 will be detected upon power up. But
if two devices of any lower width are plugged in; only the device connected to Device 1,
Function 0 will be detected.
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3.2.6
Lane Reversal on PCIe* Interface
The PCI Express* lanes can be reversed for ease of design and layout. Lane reversal is
done statically, which means that the BIOS needs to configure the reversal before the
relevant root port is enabled. For the x16 configuration, only one reversal option is
supported allowing either a straight or a rotated CPU on the motherboard. No other
combination of partial slot reversal is permitted. The reversal on x8 and x4
configurations are applied in a similar fashion.
The normal or reversed configuration is determined by the configuration pins CFG[2]
for PCI express lanes on Port 1 and CFG[3] for lanes on Port 2. A value of '1' on these
inputs would indicate normal operation and a '0' would indicate reversed mode of
operation.
Table 3-7.
Hardware Straps for Normal/Reversed Operation of PCIe* Lanes
PCI-e Lanes
Normal
Reversed
Port 1
CFG [2] =1
CFG [2] =0
Port 2
CFG [3] =1
CFG [3] =0
Note:
Performance estimates on early silicon have shown that bandwidth in x16 mode for
Gen 2 is approximately twice the bandwidth in x8 mode for read, write and read-write
transaction.
3.3
Direct Media Interface
DMI connects the processor and the PCH. Next generation DMI 2.0 is supported.
Note:
Only DMI x4 configuration is supported.
3.3.1
DMI Error Flow
DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or
GPE. Any DMI related SERR activity is associated with Device 0.
3.3.2
DMI Link Down
The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to
data link down after the link was up, then the DMI link hangs the system by not
allowing the link to retrain to prevent data corruption. The PCH controls this link
behavior.
Downstream transactions that had been successfully transmitted across the link prior
to the link going down may be processed as normal. No completions from downstream,
non-posted transactions are returned upstream over the DMI link after a link down
event.
3.4
Platform Environment Control Interface (PECI)
The PECI is a one-wire interface that provides a communication channel between a
PECI client (processor) and a PECI master. The processor implements a PECI interface
to:
• Allow communication of processor thermal and other information to the PECI
master.
• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.
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3.5
Interface Clocking
3.5.1
Internal Clocking Requirements
Table 3-9.
Reference Clock
Reference Input Clock
BCLK/BCLK#
Input Frequency
100 MHz
Associated PLL
Processor/Memory/PCIe/DMI
§§
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4.0
Technologies
4.1
Intel® Virtualization Technology
Intel® Virtualization Technology (Intel® VT) makes a single system appear to software
as multiple independent systems. This allows multiple, independent operating systems
to run simultaneously on a single system. Intel® VT comprises technology components
to support virtualization of platforms based on Intel architecture microprocessors and
chipsets. Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel®
Architecture (Intel® VT-x) added hardware support in the processor to improve the
virtualization performance and robustness. Intel® Virtualization Technology for
Directed I/O (Intel® VT-d) adds chipset hardware implementation to support and
improve I/O virtualization performance and robustness.
Intel® VT-x specifications and functional descriptions are included in the Intel® 64 and
IA-32 Architectures Software Developer’s Manual, Volume 3B and available at
http://www.intel.com/products/processor/manuals/index.htm
The Intel® VT-d spec and other Intel® VT documents can be referenced at
http://www.intel.com/technology/platform-technology/virtualization/index.htm
4.1.1
Intel® VT-x Objectives
Intel® VT-x provides hardware acceleration for virtualization of IA platforms. Virtual
Machine Monitor (VMM) can use Intel® VT-x features to provide improved reliable
virtualized platform. By using Intel® VT-x, a VMM is:
• Robust: VMMs no longer need to use paravirtualization or binary translation. This
means that they will be able to run off-the-shelf OSs and applications without any
special steps.
• Enhanced: Intel® VT enables VMMs to run 64-bit guest operating systems on IA
x86 processors.
• More reliable: Due to the hardware support, VMMs can now be smaller, less
complex, and more efficient. This improves reliability and availability and reduces
the potential for software conflicts.
• More secure: The use of hardware transitions in the VMM strengthens the isolation
of VMs and further prevents corruption of one VM from affecting others on the
same system.
4.1.2
Intel® VT-x Features
The processor core supports the following Intel® VT-x features:
• Extended Page Tables (EPT)
— EPT is hardware assisted page table virtualization
— It eliminates VM exits from guest OS to the VMM for shadow page-table
maintenance
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• Virtual Processor IDs (VPID)
— Ability to assign a VM ID to tag processor core hardware structures (e.g., TLBs)
— This avoids flushes on VM transitions to give a lower-cost VM transition time
and an overall reduction in virtualization overhead.
• Guest Preemption Timer
— Mechanism for a VMM to preempt the execution of a guest OS after an amount
of time specified by the VMM. The VMM sets a timer value before entering a
guest
— The feature aids VMM developers in flexibility and Quality of Service (QoS)
guarantees
• Descriptor-Table Exiting
— Descriptor-table exiting allows a VMM to protect a guest OS from internal
(malicious software based) attack by preventing relocation of key system data
structures like IDT (interrupt descriptor table), GDT (global descriptor table),
LDT (local descriptor table), and TSS (task segment selector).
— A VMM using this feature can intercept (by a VM exit) attempts to relocate
these data structures and prevent them from being tampered by malicious
software.
4.1.3
Intel® VT-d Objectives
The key Intel® VT-d objectives are domain-based isolation and hardware-based
virtualization. A domain can be abstractly defined as an isolated environment in a
platform to which a subset of host physical memory is allocated. Virtualization allows
for the creation of one or more partitions on a single system. This could be multiple
partitions in the same operating system, or there can be multiple operating system
instances running on the same system, offering benefits like system consolidation,
legacy migration, activity partitioning, or security.
4.1.4
Intel® VT-d Features
The processor supports the following Intel® VT-d features:
• Memory controller complies with Intel® VT-d 1.2 specification.
• Intel® VT-d DMA remap engines.
— DMI (non-high def audio)
— PCI Express*
• Support for root entry, context entry and default context
• 39-bit guest physical address and host physical address widths
• Support for 4K page sizes only
• Support for register-based fault recording only (for single entry only) and support
for MSI interrupts for faults
• Support for both leaf and non-leaf caching
• Support for boot protection of default page table
• Support for non-caching of invalid page table entries
• Support for hardware based flushing of translated but pending writes and pending
reads, on IOTLB invalidation
• Support for page-selective IOTLB invalidation
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• MSI cycles (MemWr to address FEEx_xxxxh) not translated
— Translation faults result in cycle forwarding to VBIOS region (byte enables
masked for writes). Returned data may be bogus for internal agents, PEG/DMI
interfaces return unsupported request status
• Interrupt Remapping is supported
• Queued invalidation is supported
• VT-d translation bypass address range is supported (Pass Through)
• Support for ARI (Alternative Requester ID - a PCI SIG ECR for increasing the
function number count in a PCIe device) to support IOV devices
4.1.5
Intel® VT-d Features Not Supported
The following features are not supported by the processor with Intel® VT-d:
• No support for PCISIG endpoint caching (ATS)
• No support for Intel® VT-d read prefetching/snarfing i.e. translations within a
cacheline are not stored in an internal buffer for reuse for subsequent translations.
• No support for advance fault reporting
• No support for super pages
• No support for Intel® VT-d translation bypass address range (such usage models
need to be resolved with VMM help in setting up the page tables correctly)
4.2
Intel® Trusted Execution Technology (Intel® TXT)
Intel Trusted Execution Technology (Intel® TXT) defines platform-level enhancements
that provide the building blocks for creating trusted platforms.
The Intel® TXT platform helps to provide the authenticity of the controlling
environment such that those wishing to rely on the platform can make an appropriate
trust decision. The Intel® TXT platform determines the identity of the controlling
environment by accurately measuring and verifying the controlling software.
Another aspect of the trust decision is the ability of the platform to resist attempts to
change the controlling environment. The Intel® TXT platform will resist attempts by
software processes to change the controlling environment or bypass the bounds set by
the controlling environment.
Intel® TXT is a set of extensions designed to provide a measured and controlled launch
of system software that will then establish a protected environment for itself and any
additional software that it may execute.
These extensions enhance two areas:
• The launching of the Measured Launched Environment (MLE)
• The protection of the MLE from potential corruption
The enhanced platform provides these launch and control interfaces using Safer Mode
Extensions (SMX)
The SMX interface includes the following functions:
• Measured/Verified launch of the MLE
• Mechanisms to ensure the above measurement is protected and stored in a secure
location
• Protection mechanisms that allow the MLE to control attempts to modify itself
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For more information, see the Intel® TXT Measured Launched Environment Developer’s
Guide in http://www.intel.com/content/www/us/en/software-developers/intel-txtsoftware-development-guide.html.
4.3
Intel® Hyper-Threading Technology
The processor supports Intel® Hyper-Threading Technology (Intel® HT Technology),
which allows an execution core to function as two logical processors. While some
execution resources such as caches, execution units, and buses are shared, each
logical processor has its own architectural state with its own set of general-purpose
registers and control registers. This feature must be enabled via the BIOS and requires
operating system support.
Intel recommends enabling Hyper-Threading Technology with Microsoft Windows 7*,
Microsoft Windows Vista*, Microsoft Windows* XP Professional/Windows* XP Home,
and disabling Hyper-Threading Technology via the BIOS for all previous versions of
Windows operating systems. For more information on Hyper-Threading Technology, see
http://www.intel.com/technology/platform-technology/hyper-threading/.
4.4
Intel® Advanced Vector Extensions (Intel® AVX)
Intel® Advanced Vector Extensions (Intel® AVX) is the latest expansion of the Intel
instruction set. It extends the Intel® Streaming SIMD Extensions (SSE) from 128-bit
vectors into 256-bit vectors. Intel® AVX addresses the continued need for vector
floating-point performance in mainstream scientific and engineering numerical
applications, visual processing, recognition, data-mining/synthesis, gaming, physics,
cryptography and other areas of applications.
The enhancement in Intel® AVX allows for improved performance due to wider vectors,
new extensible syntax, and rich functionality including the ability to better manage,
rearrange, and sort data. For more information on Intel® AVX, see
http://www.intel.com/software/avx.
4.5
Intel® Advanced Encryption Standard New Instructions
(Intel® AES-NI)
The processor supports Advanced Encryption Standard New Instructions (Intel® AESNI), which are a set of Single Instruction Multiple Data (SIMD) instructions that enable
fast and secure data encryption and decryption based on the Advanced Encryption
Standard (AES). Intel® AES-NI are valuable for a wide range of cryptographic
applications, for example: applications that perform bulk encryption/decryption,
authentication, random number generation, and authenticated encryption. AES is
broadly accepted as the standard for both government and industry applications, and is
widely deployed in various protocols.
Intel® AES-NI consists of six Intel® SSE instructions. Four instructions, namely
AESENC, AESENCLAST, AESDEC, and AESDELAST facilitate high performance AES
encryption and decryption. The other two, namely AESIMC and AESKEYGENASSIST,
support the AES key expansion procedure. Together, these instructions provide a full
hardware for support AES, offering security, high performance, and a great deal of
flexibility.
4.5.1
PCLMULQDQ Instruction
The processor supports the carry-less multiplication instruction, PCLMULQDQ.
PCLMULQDQ is a Single Instruction Multiple Data (SIMD) instruction that computes the
128-bit carry-less multiplication of two, 64-bit operands without generating and
propagating carries. Carry-less multiplication is an essential processing component of
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several cryptographic systems and standards. Hence, accelerating carry-less
multiplication can significantly contribute to achieving high speed secure computing
and communication.
4.5.2
RDRAND Instruction
The processor introduces a software visible random number generation mechanism
supported by a high quality entropy source. This capability will be made available to
programmers through the new RDRAND instruction. The resultant random number
generation capability is designed to comply with existing industry standards in this
regard (ANSI X9.82 and NIST SP 800-90).
Some possible usages of the new RDRAND instruction include cryptographic key
generation as used in a variety of applications including communication, digital
signatures, secure storage, and so on.
4.6
Intel® 64 Architecture x2APIC
The x2APIC architecture extends the xAPIC architecture which provides key mechanism
for interrupt delivery. This extension is intended primarily to increase processor
addressability.
Specifically, x2APIC:
• Retains all key elements of compatibility to the xAPIC architecture:
— delivery modes
— interrupt and processor priorities
— interrupt sources
— interrupt destination types
• Provides extensions to scale processor addressability for both the logical and
physical destination modes.
• Adds new features to enhance performance of interrupt delivery.
• Reduces complexity of logical destination mode interrupt delivery on link based
architectures.
The key enhancements provided by the x2APIC architecture over xAPIC are the
following:
• Support for two modes of operation to provide backward compatibility and
extensibility for future platform innovations.
— In xAPIC compatibility mode, APIC registers are accessed through memory
mapped interface to a 4K-Byte page, identical to the xAPIC architecture.
— In x2APIC mode, APIC registers are accessed through Model Specific Register
(MSR) interfaces. In this mode, the x2APIC architecture provides significantly
increased processor addressability and some enhancements on interrupt
delivery.
• Increased range of processor addressability in x2APIC mode:
— Physical xAPIC ID field increases from 8 bits to 32 bits, allowing for interrupt
processor addressability up to 4G-1 processors in physical destination mode. A
processor implementation of x2APIC architecture can support fewer than 32bits in a software transparent fashion.
— Logical xAPIC ID field increases from 8 bits to 32 bits. The 32-bit logical x2APIC
ID is partitioned into two sub-fields: a 16-bit cluster ID and a 16-bit logical ID
within the cluster. Consequently, ((2^20) -16) processors can be addressed in
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logical destination mode. Processor implementations can support fewer than 16
bits in the cluster ID sub-field and logical ID sub-field in a software agnostic
fashion.
• More efficient MSR interface to access APIC registers.
— To enhance inter-processor and self directed interrupt delivery as well as the
ability to virtualize the local APIC, the APIC register set can be accessed only
through MSR based interfaces in the x2APIC mode. The Memory Mapped IO
(MMIO) interface used by xAPIC is not supported in the x2APIC mode.
• The semantics for accessing APIC registers have been revised to simplify the
programming of frequently-used APIC registers by system software. Specifically
the software semantics for using the Interrupt Command Register (ICR) and End Of
Interrupt (EOI) registers have been modified to allow for more efficient delivery
and dispatching of interrupts.
The x2APIC extensions are made available to system software by enabling the local
x2APIC unit in the “x2APIC” mode. In order to benefit from x2APIC capabilities, a new
Operating System and a new BIOS are both needed, with special support for the
x2APIC mode.
The x2APIC architecture provides backward compatibility to the xAPIC architecture and
forward extendibility for future Intel platform innovations.
Note:
Intel x2APIC technology may not be available on all SKUs.
For more information see the Intel® 64 Architecture x2APIC specification at
http://www.intel.com/products/processor/manuals/
4.7
Supervisor Mode Execution Protection (SMEP)
The processor introduces a new mechanism that provides next level of system
protection by blocking malicious software attacks from user mode code when the
system is running in the highest privilege level.
This technology helps to protect from virus attacks and unwanted code to harm the
system.
For more information see Intel® 64 and IA-32 Architectures Software Developer’s
Manual, Volume 3A at: http://www.intel.com/Assets/PDF/manual/253668.pdf.
4.8
Power Aware Interrupt Routing (PAIR)
The processor added enhanced power-performance technology which routes interrupts
to threads or cores based on their sleep states. For example concerning energy
savings, it routes the interrupt to the active cores without waking the deep idle cores.
For Performance, it routes the interrupt to the idle (C1) cores without interrupting the
already heavily loaded cores. This enhancement is mostly beneficial for high interrupt
scenarios like Gigabit LAN, WLAN peripherals, and so on.
§§
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5.0
Processor SKUs
This section details the features of the various processor SKUs. The mix of SKUs are
chosen to span cost, performance, temperature environment, and power consumption.
5.1
SKU Features
Table 5-1 outlines the available SKUs.
Table 5-1.
Base Features by SKU
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Product Name
Target Core Speed (GHz)
Active Cores
1
TDP (Watts)
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
2.5
1.8
2.5
2.0
4
4
2
2
40
25
25
15
L3 Cache (MB)
8
8
4
4
Memory Channels
2
2
2
2
ECC Memory
Yes
PCI-Express* (lanes)
20
PCI-Express* (root)
1x16 +1x4 or 2x8 +1x4 or 1x8 +3x4
Junction Temperature
TJ-Min = 0oC, TJ-MAX = 100oC
Intel® Virtualization
Technology
Yes
Intel® Hyper-Threading
Technology
Yes
Intel® Trusted Execution
Technology
Yes
Graphics
No
Intel® Turbo Boost
No
Notes:
1.
Thermal Design Power (TDP) is a system design target associated with the maximum component
operating temperature specifications. TDP values are determined based on typical DC electrical
specification and maximum component temperature for a realistic-case application running at
maximum utilization.
§§
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6.0
Power Management
This chapter provides information on the following power management topics:
• ACPI States
• Processor Core
• Integrated Memory Controller (IMC)
• PCI Express*
• Direct Media Interface (DMI)
Figure 6-1.
Power States
G0 – Working
S0 – CPU Fully powered on
C0 – Active mode
P0
Pn
C1 – Auto halt
C1E – Auto halt, low freq, low voltage
C3 – L1/L2 caches flush, clocks off
C6 – save core states before shutdown
C7 – similar to C6, L3 flush
G1 – Sleeping
S3 cold – Sleep – Suspend To Ram (STR)
S4 – Hibernate – Suspend To Disk (STD),
Wakeup on PCH
S5 – Soft Off – no power,
Wakeup on PCH
G3 – Mechanical Off
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6.1
ACPI States Supported
This section describes the ACPI states supported by the processor
6.1.1
System States
Table 6-1.
System States
State
G0/S0
G1/S3-Cold
Description
Full On
Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the
processor).
G1/S4
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5
Soft off. All power lost (except wakeup on PCH). Total reboot.
G3
Mechanical off. All power (AC and battery) removed from system.
6.1.2
Processor Core/Package Idle States
Table 6-2.
Processor Core/Package State Support
State
C0
Description
Active mode, processor executing code.
C1
AutoHALT state.
C1E
AutoHALT state with lowest frequency and voltage operating point.
C3
Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to
the L3 shared cache. Clocks are shut off to each core.
C6
Execution cores in this state save their architectural state before removing core
voltage.
C7
Execution cores in this state behave similarly to the C6 state. if all execution cores
request C7, L3 cache ways are flushed until it is cleared.
6.1.3
Integrated Memory Controller States
Table 6-3.
Integrated Memory Controller States
State
Power up
Pre-charge Power-down
Active Power-down
Self-Refresh
Description
CKE asserted. Active mode.
CKE deasserted (not self-refresh) with all banks closed.
CKE deasserted (not self-refresh) with minimum one bank active.
CKE deasserted using device self-refresh.
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6.1.4
PCIe* Link States
Table 6-4.
PCIe* Link States
State
Description
L0
Full on – Active transfer state.
L0s
First Active Power Management low power state – Low exit latency.
L1
Lowest Active Power Management – Longer exit latency.
L3
Lowest power state (power-off) – Longest exit latency.
6.1.5
DMI States
Table 6-5.
DMI States
State
Description
L0
Full on – Active transfer state.
L0s
First Active Power Management low power state – Low exit latency.
L1
Lowest Active Power Management - Longer exit latency.
L3
Lowest power state (power-off) – Longest exit latency.
6.1.6
Interface State Combinations
Table 6-6.
G, S and C State Combinations
Global (G)
State
Table 6-7.
Sleep
(S) State
Processor
Core
(C) State
Processor
State
System Clocks
Description
G0
S0
C0
Full On
On
Full On
G0
S0
C1/C1E
Auto-Halt
On
Auto-Halt
G0
S0
C3
Deep Sleep
On
Deep Sleep
Deep Powerdown
On
Deep Power Down
G0
S0
C6/C7
G1
S3
Power off
Off, except RTC
Suspend to RAM
G1
S4
Power off
Off, except RTC
Suspend to Disk
G2
S5
Power off
Off, except RTC
Soft Off
G3
NA
Power off
Power off
Hard off
D, S, and C State Combination (Sheet 1 of 2)
Graphics Adapter
(D) State
Sleep (S) State
Package (C) State
D0
S0
C0
D0
S0
C1/C1E
D0
S0
C3
Deep sleep, Displaying
D0
S0
C6
Deep Power Down, Displaying
Description
Full On, Displaying
Auto-Halt, Displaying
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Table 6-7.
6.2
D, S, and C State Combination (Sheet 2 of 2)
Graphics Adapter
(D) State
Sleep (S) State
Package (C) State
D3
S0
Any
Not displaying
D3
S3
N/A
Not displaying, Graphics Core
is powered off
D3
S4
N/A
Not displaying, suspend to disk
Description
Processor Core Power Management
While executing code, Enhanced Intel SpeedStep® Technology optimizes the
processor’s frequency and core voltage based on workload. Each frequency and voltage
operating point is defined by ACPI as a P-state. When the processor is not executing
code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower
power C-states have longer entry and exit latencies.
6.2.1
Enhanced Intel SpeedStep® Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on the selected frequency and the number of active
processor cores.
— If the target frequency is higher than the current frequency, VCC is ramped up
in steps to an optimized voltage. This voltage is signaled by the SVID bus to the
voltage regulator. Once the voltage is established, the PLL locks on to the
target frequency.
— If the target frequency is lower than the current frequency, the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID bus.
— All active processor cores share the same frequency and voltage. In a multicore processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. If a previous
transition is in progress, the new transition is deferred until the previous
transition is completed.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per-second are possible.
6.2.2
Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occur at the
thread, processor core, and processor package level. Thread-level C-states are
available if Intel Hyper-Threading Technology is enabled.
Note:
Long term reliability cannot be assured unless all the Low Power Idle States are
enabled.
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Figure 6-2.
Idle Power Management Breakdown of the Processor Cores
Thread 0
Thread 1
Thread 0
Core 0 State
Thread 1
Core 1 State
Processor Package State
Entry and exit of the C-States at the thread and core level are shown in Figure 6-3.
Figure 6-3.
Thread and Core C-State Entry and Exit
C0
MWAIT(C1), HLT
MWAIT(C1), HLT
(C1E Enabled)
C1
MWAIT(C3),
P_LVL2 I/O Read
C1E
MWAIT(C7),
P_LVL4 I/O Read
MWAIT(C6),
P_LVL3 I/O Read
C3
C6
C7
While individual threads can request low power C-states, power saving actions only
take place once the core C-state is resolved. Core C-states are automatically resolved
by the processor. For thread and core C-states, a transition to and from C0 is required
before entering any other C-state.
Table 6-8.
Coordination of Thread Power States at the Core Level
Processor Core
C-State
C0
C1
C3
C6
C7
C0
C0
C0
C0
C0
C1
C0
C11
C11
C11
C11
C3
C0
C11
C3
C3
C3
C0
C1
1
C3
C6
C6
C1
1
C3
C6
C7
Thread 0
C0
C6
C7
1.
Thread 1
C0
If enabled, the core C-state will be C1E if all active cores have also resolved a core C1 state or higher.
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6.2.3
Requesting Low-Power Idle States
The primary software interfaces for requesting low power idle states are through the
MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).
However, software may make C-state requests using the legacy method of I/O reads
from the ACPI-defined processor clock control registers, referred to as P_LVLx. This
method of requesting C-states provides legacy support for operating systems that
initiate C-state transitions via I/O reads.
For legacy operating systems, P_LVLx I/O reads are converted within the processor to
the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in
I/O reads to the system. The feature, known as I/O MWAIT redirection, must be
enabled in the BIOS.
Note:
The P_LVLx I/O Monitor address must be set up before using the P_LVLx I/O read
interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as shown in
Table 6-9.
Table 6-9.
P_LVLx to MWAIT Conversion
P_LVLx
MWAIT(Cx)
Notes
P_LVL2
MWAIT(C3)
The P_LVL2 base address is defined in the PMG_IO_CAPTURE MSR,
P_LVL3
MWAIT(C6)
C6. No sub-states allowed.
P_LVL4
MWAIT(C7)
C7. No sub-states allowed.
P_LVL5+
MWAIT(C7)
C7. No sub-states allowed.
The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict
the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any
P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like
request. They fall through like a normal I/O instruction.
Note:
When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The
MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O
redirections enable the MWAIT 'break on EFLAGS.IF’ feature which triggers a wakeup
on an interrupt even if interrupts are masked by EFLAGS.IF.
6.2.4
Core C-States
The following are general rules for all core C-states:
• A core C-State is determined by the lowest numerical thread state (e.g., Thread 0
requests C1E while Thread 1 requests C3, resulting in a core C1E state). See
Table 6-6, “G, S and C State Combinations”.
• A core transitions to C0 state when:
— An interrupt occurs
— There is an access to the monitored address if the state was entered via an
MWAIT instruction
• For core C1/C1E, and core C3, and core C6/C7, an interrupt directed toward a
single thread wakes only that thread. However, since both threads are no longer at
the same core C-state, the core resolves to C0.
• A system reset re-initializes all processor cores.
6.2.4.1
Core C0 State
The normal operating state of a core where code is being executed.
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6.2.4.2
Core C1/C1E State
C1/C1E is a low power state entered when all threads within a core execute a HLT or
MWAIT(C1/C1E) instruction.
A System Management Interrupt (SMI) handler returns execution to either Normal
state or the C1/C1E state. See the Intel® 64 and IA-32 Architecture Software
Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.
While a core is in C1/C1E state, it processes bus snoops and snoops from other
threads. For more information on C1E, see Section 6.2.5.2, “Package C1/C1E”.
6.2.4.3
Core C3 State
Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to
the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its
L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while
maintaining its architectural state. All core clocks are stopped at this point. Because the
core’s caches are flushed, the processor does not wake any core that is in the C3 state
when either a snoop is detected or when another core accesses cacheable memory.
6.2.4.4
Core C6 State
Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an
MWAIT(C6) instruction. Before entering core C6, the core will save its architectural
state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero
volts. During exit, the core is powered on and its architectural state is restored.
6.2.4.5
Core C7 State
Individual threads of a core can enter the C7 state by initiating a P_LVL4 I/O read to
the P_BLK or by an MWAIT(C7) instruction. The core C7 state exhibits the same
behavior as the core C6 state unless the core is the last one in the package to enter the
C7 state. If it is, that core is responsible for flushing L3 cache ways. The processor
supports the C7s substate. When an MWAIT(C7) command is issued with a C7s
sub-state hint, the entire L3 cache is flushed one step as opposed to flushing the L3
cache in multiple steps.
Note:
Core C7 state support is available for quad core and dual core processors. Single core
processors do not support the Core C7 state.
6.2.4.6
C-State Auto-Demotion
In general, deeper C-states such as C6 or C7 have long latencies and have higher
energy entry/exit costs. The resulting performance and energy penalties become
significant when the entry/exit frequency of a deeper C-state is high. Therefore
incorrect or inefficient usage of deeper C-states have a negative impact on power. In
order to increase residency and improve power in deeper C-states, the processor
supports C-state auto-demotion.
There are two C-state auto-demotion options:
• C7/C6 to C3
• C7/C6/C3 To C1
The decision to demote a core from C6/C7 to C3 or C3/C6/C7 to C1 is based on each
core’s immediate residency history. Upon each core C6/C7 request, the core C-state is
demoted to C3 or C1 until a sufficient amount of residency has been established. At
that point, a core is allowed to go into C3/C6 or C7. Each option can be run
concurrently or individually.
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This feature is disabled by default. BIOS must enable it in the
PMG_CST_CONFIG_CONTROL register. The auto-demotion policy is also configured by
this register.
6.2.5
Package C-States
The processor supports C0, C1/C1E, C3, C6, and C7 power states. The following is a
summary of the general rules for package C-state entry. These apply to all package Cstates unless specified otherwise:
• A package C-state request is determined by the lowest numerical core C-state
amongst all cores.
• A package C-state is automatically resolved by the processor depending on the
core idle power states and the status of the platform components.
— Each core can be at a lower idle power state than the package if the platform
does not grant the processor permission to enter a requested package C-state.
— The platform may allow additional power savings to be realized in the
processor.
— For package C-states, the processor is not required to enter C0 before entering
any other C-state.
The processor exits a package C-state when a break event is detected. Depending on
the type of break event, the processor does the following:
• If a core break event is received, the target core is activated and the break event
message is forwarded to the target core.
— If the break event is not masked, the target core enters the core C0 state and
the processor enters package C0.
• If the break event was due to a memory access or snoop request.
— But the platform did not request to keep the processor in a higher package Cstate, the package returns to its previous C-state.
— And the platform requests a higher power C-state, the memory access or snoop
request is serviced and the package remains in the higher power C-state.
Table 6-10 shows package C-state resolution for a dual-core processor. Figure 6-4
summarizes package C-state transitions.
Table 6-10. Coordination of Core Power States at the Package Level
Core 1
Core 0
Package
C-State
C0
C1
C3
C6
C7
C0
C0
C0
C0
C0
C0
C1
C0
C11
C11
C11
C11
C3
C0
C11
C3
C3
C3
C6
C0
C11
C3
C6
C6
C7
C0
C11
C3
C6
C7
Notes:
1.
If enabled, the package C-state will be C1E if all actives cores have also resolved a core C1 state or
higher.
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Figure 6-4.
Package C-State Entry and Exit
C0
C3
C6
C1
6.2.5.1
C7
Package C0
The normal operating state for the processor. The processor remains in the normal
state when at least one of its cores is in the C0 or C1 state or when the platform has
not granted permission to the processor to go into a low power state. Individual cores
may be in lower power idle states while the package is in C0.
6.2.5.2
Package C1/C1E
No additional power reduction actions are taken in the package C1 state. However, if
the C1E sub-state is enabled, the processor automatically transitions to the lowest
supported core clock frequency, followed by a reduction in voltage.
The package enters the C1 low power state when:
• At least one core is in the C1 state.
• The other cores are in a C1 or lower power state.
The package enters the C1E state when:
• All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint.
• All cores are in a power state lower that C1/C1E but the package low power state is
limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR.
• All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is
enabled in IA32_MISC_ENABLES.
No notification to the system occurs upon entry to C1/C1E.
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6.2.5.3
Package C3 State
A processor enters the package C3 low power state when:
• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been
granted permission by the platform.
• The platform has not granted a request to a package C6/C7 state but has allowed a
package C6 state.
In package C3-state, the L3 shared cache is valid.
6.2.5.4
Package C6 State
A processor enters the package C6 low power state when:
• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been
granted permission by the platform.
• The platform has not granted a package C7 request but has allowed a C6 package
state.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable
in this state. The processor remains in package C6 state as long as any part of the L3
cache is active.
6.2.5.5
Package C7 State
The processor enters the package C7 low power state when all cores are in the C7 state
and the L3 cache is completely flushed. The last core to enter the C7 state begins to
shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows
further power savings.
Core break events are handled the same way as in package C3 or C6. However, snoops
are not sent to the processor in package C7 state because the platform, by granting the
package C7 state, has acknowledged that the processor possesses no snoopable
information. This allows the processor to remain in this low power state and maximize
its power savings.
Upon exit of the package C7 state, the L3 cache is not immediately re-enabled. It
re-enables once the processor has stayed out of the C6 or C7 for an preset amount of
time. Power is saved since this prevents the L3 cache from being re-populated only to
be immediately flushed again.
6.2.5.6
Dynamic L3 Cache Sizing
Upon entry into the package C7 state, the L3 cache is reduced by N-ways until it is
completely flushed. The number of ways, N, is dynamically chosen per concurrent C7
entry. Similarly, upon exit, the L3 cache is gradually expanded based on internal
heuristics.
6.3
IMC Power Management
The main memory is power managed during normal operation and in low-power ACPI
Cx states.
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6.3.1
Disabling Unused System Memory Outputs
Any system memory (SM) interface signal that goes to a memory module connector in
which it is not connected to any actual memory devices (such as DIMM connector is
unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM
signals are:
• Reduced power consumption.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor
I/O buffer receivers caused by reflections from potentially un-terminated
transmission lines.
When a given rank is not populated, the corresponding chip select and CKE signals are
not driven.
At reset, all rows must be assumed to be populated, until it can be proven that they are
not populated. This is due to the fact that when CKE is tristated with an DIMM present,
the DIMM is not guaranteed to maintain data integrity.
SCKE tristate should be enabled by BIOS where appropriate, since at reset all rows
must be assumed to be populated.
6.3.2
DRAM Power Management and Initialization
The processor implements extensive support for power management on the SDRAM
interface. There are four SDRAM operations associated with the Clock Enable (CKE)
signals, which the SDRAM controller supports. The processor drives four CKE pins to
perform these operations.
The CKE is one of the power-save means. When CKE is off the internal DDR clock is
disabled and the DDR power is reduced. The power-saving differs according to the
selected mode and the DDR type used. For more information, see the IDD table in the
DDR specification.
The DDR specification defines three levels of power-down that differ in power-saving
and in wakeup time:
1. Active power-down (APD): This mode is entered if there are open pages when
deasserting CKE. In this mode the open pages are retained. Power-saving in this
mode is the lowest. Power consumption of DDR is defined by IDD3P. Exiting this
mode is defined by tXP – small number of cycles.
2. Precharged power-down (PPD): This mode is entered if all banks in DDR are
precharged when de-asserting CKE. Power-saving in this mode is intermediate –
better than APD, but less than DLL-off. Power consumption is defined by IDD2P1.
Exiting this mode is defined by tXP. Difference from APD mode is that when wakingup all page-buffers are empty.
3. DLL-off: In this mode the data-in DLLs on DDR are off. Power-saving in this mode is
the best among all power-modes. Power consumption is defined by IDD2P1. Exiting
this mode is defined by tXP, but also tXPDLL (10 – 20 according to DDR type) cycles
until first data transfer is allowed.
The processor supports six types of power-down. These different modes are the powerdown modes supported by DDR3 and combinations of these modes. The type of CKE
power-down is defined by the configuration. The options are:
1. No power-down.
2. APD: The rank enters power-down as soon as idle-timer expires, no matter what is
the bank status.
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3. PPD: When idle timer expires the MC sends PRE-all to rank and then enters
powerdown.
4. DLL-off: same as option (2) but DDR is configured to DLL-off.
5. APD, change to PPD (APD-PPD): Begins as option (1), and when all page-close
timers of the rank are expired, it wakes the rank, issues PRE-all, and returns to
PPD.
6. APD, change to DLL-off (APD_DLLoff) – Begins as option (1), and when all pageclose timers of the rank are expired, it wakes the rank, issues PRE-all and returns
to DLL-off power-down.
The CKE is determined per rank when it is inactive. Each rank has an idle-counter. The
idle-counter starts counting as soon as the rank has no accesses, and if it expires, the
rank may enter power-down while no new transactions to the rank arrive to queues.
The idle-counter begins counting at the last incoming transaction arrival.
It is important to understand that since the power-down decision is per rank, the MC
can find many opportunities to power-down ranks even while running memory
intensive applications, and savings are significant (may be a few watts, according to
the DDR specification). This is significant when each channel is populated with more
ranks.
Selection of power modes should be according to power-performance or thermal
tradeoffs of a given system:
• When trying to achieve maximum performance and power or thermal consideration
is not an issue: use no power-down.
• In a system that tries to minimize power-consumption, use the deepest powerdown mode possible – DLL-off or APD_DLLoff.
• In high-performance systems with dense packaging (that is, complex thermal
design) the power-down mode should be considered in order to reduce the heating
and avoid DDR throttling caused by the heating.
Control of the power-mode must be controlled through the BIOS – The BIOS selects
no-powerdown by default. There are knobs to change the power-down selected mode.
Another control is the idle timer expiration count. This is set through PM_PDWN_config
bits 7:0 (MCHBAR +4CB0). As this timer is set to a shorter time, the MC will have more
opportunities to put DDR in power-down. The minimum recommended value for this
register is 15. There is no BIOS hook to set this register. Customers who choose to
change the value of this register can do it by changing the BIOS. For experiments, this
register can be modified in real time if BIOS did not lock the MC registers.
Note:
In APD, APD-PPD, and APD_DLL-off, there is no point in setting the idle-counter in the
same range as page-close idle timer.
Another option associated with CKE power-down is the S_DLL-off. When this option is
enabled, the SBR I/O slave DLLs go off when all channel ranks are in power-down. (Do
not confuse it with the DLL-off mode in which the DDR DLLs are off). This mode
requires you to define the I/O slave DLL wakeup time.
6.3.2.1
Initialization Role of CKE
During power-up, CKE is the only input to the SDRAM that has its level is recognized
(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the
DDR controller to make sure the SDRAM components float DQ and DQS during powerup. CKE signals remain LOW (while any reset is active) until the BIOS writes to a
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configuration register. Using this method, CKE is guaranteed to remain inactive for
much longer than the specified 200 micro-seconds after power and clocks to SDRAM
devices are stable.
6.3.2.2
Conditional Self-Refresh
Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into
self-refresh in the package low-power states. RMPM functionality depends on graphics/
display state (relevant only when processor graphics is being used), as well as memory
traffic patterns generated by other connected I/O devices.
When entering the S3 - Suspend-to-RAM (STR) state or S0 conditional self-refresh, the
processor core flushes pending cycles and then enters all SDRAM ranks into self
refresh. the CKE signals remain LOW so the SDRAM devices perform self-refresh.
The target behavior is to enter self-refresh for the package states as long as there are
no memory requests to service.
Table 6-11. Targeted Memory State Conditions
Mode
Memory State with Processor Graphics
Memory State with External Graphics
C0, C1, C1E
Dynamic memory rank power down based on
idle conditions.
Dynamic memory rank power down based on
idle conditions.
If the processor graphics engine is idle and
there are no pending display requests, then
enter self-refresh. Otherwise use dynamic
memory rank power down based on idle
conditions.
If there are no memory requests, then enter
self-refresh. Otherwise use dynamic memory
rank power down based on idle conditions.
S3
Self-Refresh Mode.
Self-Refresh Mode.
S4
Memory power down (contents lost).
Memory power down (contents lost)
C3, C6, C7
6.3.2.3
Dynamic Power Down Operation
Dynamic power-down of memory is employed during normal operation. Based on idle
conditions, a given memory rank may be powered down. The IMC implements
aggressive CKE control to dynamically put the DRAM devices in a power down state.
The processor core controller can be configured to put the devices in active powerdown (CKE deassertion with open pages) or precharge power-down (CKE deassertion
with all pages closed). Precharge power-down provides greater power savings but has
a bigger performance impact, since all pages will first be closed before putting the
devices in power-down mode.
If dynamic power-down is enabled, all ranks are powered up before doing a refresh
cycle and all ranks are powered down at the end of refresh.
6.3.2.4
DRAM I/O Power Management
Unused signals should be disabled to save power and reduce electromagnetic
interference. This includes all signals associated with an unused memory channel.
Clocks can be controlled on a per DIMM basis. Exceptions are made for per DIMM
control signals such as CS#, CKE, and ODT for unpopulated DIMM slots.
The I/O buffer for an unused signal should be tri-stated (output driver disabled), the
input receiver (differential sense-amp) should be disabled, and any DLL circuitry
related ONLY to unused signals should be disabled. The input path must be gated to
prevent spurious results due to noise on the unused signals (typically handled
automatically when input receiver is disabled).
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6.3.3
DDR Electrical Power Gating (EPG)
The DDR I/O of the processor supports on-die Electrical Power Gating (DDR-EPG)
during normal operation (S0 mode) while the processor is at package C3 or deeper
power state.
During EPG, the VCCIO internal voltage rail will be powered down, while VDDQ and the
un-gated VCCIO will stay powered on.
The processor will transition in and out of DDR EPG mode on an as needed basis
without any external pins or signals.
There is no change to the signals driven by the processor to the DIMMs during DDR IO
EPG mode.
During EPG mode, all the DDR IO logic will be powered down, except for the Physical
Control registers that are powered by the un-gated VCCIO power supply.
Unlike S3 exit, at DDR EPG exit, the DDR will not go through training mode. Rather, it
will use the previous training information retained in the physical control registers and
will immediately resume normal operation.
6.4
PCIe* Power Management
• Active power management support using L0s, and L1 states.
• All inputs and outputs disabled in L2/L3 Ready state.
Note:
The PCIe* interface does not support Hot Plug. Power impact may be observed when
PCIe* link disable power management state is used.
6.5
DMI Power Management
Active power management support using L0s/L1 state.
6.6
Intel® Rapid Memory Power Management (RMPM) (Also
Known as CxSR)
The Intel® Rapid Memory Power Management puts rows of memory into self-refresh
mode during C3/C6 to allow the system to remain in the lower power states longer.
Processors routinely save power during runtime conditions by entering the C3, C6
state. Intel RMPM is an indirect method of power saving that can have a significant
effect on the system as a whole.
6.7
Thermal Power Management
See Section 7.0, “Thermal Management” on page 61 for thermal power managementrelated features.
§§
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7.0
Thermal Management
The thermal solution provides both the component-level and the system-level thermal
management. To allow for the optimal operation and long-term reliability of Intel
processor-based systems, the system/processor thermal solution should be designed
so that the processor:
• Remains below the maximum junction temperature (TJ-MAX) specification at the
maximum Thermal Design Power (TDP).
• Conforms to system constraints, such as system acoustics, system skintemperatures, and exhaust-temperature requirements.
Caution:
Thermal specifications given in this chapter are on the component and package level
and apply specifically to the processor. Operating the processor outside the specified
limits may result in permanent damage to the processor and potentially other
components in the system.
7.1
Thermal Considerations
The processor TDP is the maximum sustained power that should be used for design of
the processor thermal solution. TDP represents an expected maximum sustained power
from realistic applications. TDP may be exceeded for short periods of time or if running
a “power virus” workload.
The processor integrates multiple CPU on a single die. This may result in differences in
the power distribution across the die and must be considered when designing the
thermal solution. See the Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium®
Processor B925C, and Intel® Core™ i3-3115C Processors for Communications
Infrastructure Thermal and Mechanical Design Guide for details.
Thermal solutions and platform cooling that are designed to less than thermal design
guidance may experience thermal and performance issues since more applications will
tend to run at or near the maximum power limit for significant periods of time. See the
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Mechanical Design Guide for details.
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7.2
Thermal and Power Specifications
The following notes apply to Table 7-1 and Table 7-2.
Note
Table 7-1.
Table 7-2.
Definition
1
The TDPs given are not the maximum power the processor can generate. Analysis indicates that
real applications are unlikely to cause the processor to consume the theoretical maximum power
dissipation for sustained periods of time.
2
The thermal solution needs to ensure that the processor temperature does not exceed the
maximum junction temperature (Tj,max) limit, as measured by the DTS and the critical
temperature bit.
3
The processor junction temperature is monitored by Digital Temperature Sensors (DTS). For DTS
accuracy, see Section 7.3.1.2.1.
4
Digital Thermal Sensor (DTS) based fan speed control is required to achieve optimal thermal
performance. Intel recommends full cooling capability well before the DTS reading reaches Tj,Max.
An example is Tj,Max - 10ºC.
5
At Tj of Tj,max
6
For details see the Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C,
and Intel® Core™ i3-3115C Processors for Communications Infrastructure Thermal and
Mechanical Design Guide
7
LFM TDP is provided as a reference and not a validated specification.
TDP Specifications
SKU
State
CPU Core
Frequency
Thermal
Design Power
Intel® Xeon®
Processor E3-1125C
v2
HFM
2.5 GHz
40
LFM
800 MHz
22
Intel® Xeon®
Processor E3-1105C
v2
HFM
1.8 GHz
25
LFM
800 MHz
22
Intel® Core™ i3
Processor 3115C
HFM
2.5GHz
25
LFM
800 MHz
13
Intel® Pentium®
Processor B925C
HFM
2.0 GHz
15
LFM
800 MHz
13
Units
Notes
W
1,5,6,7
W
1,5,6,7
W
1,5,6,7
W
1,5,6,7
Junction Temperature Specification (All SKUs)
Symbol
Min
Default
Max
Units
Notes
TJ
0
-
100
C
2,3,4,6
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7.3
Thermal Management Features
Thermal management features for the entire processor complex (including the
processor core, and integrated memory controller hub) will be referred to as “processor
package” or “the package.”
Occasionally the package will operate in conditions that exceed its maximum allowable
operating temperature. This can be due to internal overheating or due to overheating in
the entire system. To protect processor package and the system from thermal failure,
several thermal management features exist to reduce package power consumption and
thereby temperature in order to remain within normal operating limits. Furthermore,
the processor supports several methods to reduce memory power.
7.3.1
Adaptive Thermal Monitor
The purpose of the Adaptive Thermal Monitor is to reduce processor core power
consumption and temperature until it operates at or below its maximum operating
temperature. Processor core power reduction is achieved by:
• Adjusting the operating frequency (using the core ratio multiplier) and input
voltage (using the SVID bus).
• Modulating (starting and stopping) the internal processor core clocks (duty cycle).
The Adaptive Thermal Monitor can be activated when any package temperature,
monitored by a digital thermal sensor (DTS), meets or exceeds its maximum junction
temperature specification (TJ,max) and asserts PROCHOT#. The assertion of PROCHOT#
activates the thermal control circuit (TCC), and causes the processor core to reduce
frequency and voltage adaptively. The TCC will remain active as long as any package
temperature exceeds its specified limit. Therefore, the Adaptive Thermal Monitor will
continue to reduce the package frequency and voltage until the TCC is de-activated.
The temperature at which the Adaptive Thermal Monitor activates the thermal control
circuit is factory calibrated and is not user configurable. The default value is software
visible in the TMEMPERATURE_TARGET (1A2h) MSR, bits 23:16. The Adaptive Thermal
Monitor does not require any additional hardware, software drivers, or interrupt
handling routines. The Adaptive Thermal Monitor is not intended as a mechanism to
maintain processor TDP. The system design should provide a thermal solution that can
maintain TDP within its intended usage range.
Note:
Adaptive Thermal Monitor protection is always enabled.
7.3.1.1
TCC Activation Offset
TCC Activation Offset can be used to activate the TCC at temperatures lower than
TJ,max. It is the preferred thermal protection mechanism. An offset (in degrees Celsius)
can be written to = []\TEMPERATURE_TARGET (1A2h) MSR, bits 27:24. This value will
be subtracted from the value found in bits 23:16. The default offset is 0 °C, where
throttling will occur at TJ,max. The offset should be set lower than any other protection
such as ACPI _PSV trip points.
7.3.1.1.1
Frequency/Voltage Control
Upon TCC activation, the processor core attempts to dynamically reduce processor core
power by lowering the frequency and voltage operating point. The operating points are
automatically calculated by the processor core itself and do not require the BIOS to
program them as with previous generations of Intel processors. The processor core
scales the operating points so that:
• The voltage is optimized according to the temperature, the core bus ratio, and
number of cores in deep C-states.
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• The core power and temperature are reduced while minimizing performance
degradation.
Once the temperature has dropped below the maximum operating temperature, the
operating frequency and voltage transition back to the normal system operating point.
This is illustrated in Figure 7-1.
Figure 7-1.
Frequency and Voltage Ordering
Once a target frequency/bus ratio is resolved, the processor core transitions to the new
target automatically.
• On an upward operating point transition, the voltage transition precedes the
frequency transition.
• On a downward transition, the frequency transition precedes the voltage transition.
When transitioning to a target core operating voltage, a new SVID code to the voltage
regulator is issued. The voltage regulator must support dynamic SVID steps to support
this method.
During the voltage change:
• It is necessary to transition through multiple SVID steps to reach the target
operating voltage.
• Each step is 5 mV for Intel MVP-7.0 compliant VRs.
• The processor continues to execute instructions. However, the processor halts
instruction execution for frequency transitions.
If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition
(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are
two possible outcomes:
• If the P-state target frequency is higher than the processor core optimized target
frequency, the p-state transition is deferred until the thermal event has been
completed.
• If the P-state target frequency is lower than the processor core optimized target
frequency, the processor transitions to the P-state operating point.
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7.3.1.1.2
Clock Modulation
If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor
event, the Adaptive Thermal Monitor utilizes clock modulation. Clock modulation is
done by alternately turning the clocks off and on at a duty cycle (ratio between clock
“on” time and total time) specific to the processor. The duty cycle is factory configured
to 25% on and 75% off and cannot be modified. The period of the duty cycle is
configured to 32 microseconds when the TCC is active. Cycle times are independent of
processor frequency. A small amount of hysteresis has been included to prevent
excessive clock modulation when the processor temperature is near its maximum
operating temperature. Once the temperature has dropped below the maximum
operating temperature, and the hysteresis timer has expired, the TCC goes inactive and
clock modulation ceases. Clock modulation is automatically engaged as part of the TCC
activation when the frequency/voltage targets are at their minimum settings. Processor
performance decreases by the same amount as the duty cycle when clock modulation is
active. Snooping and interrupt processing are performed in the normal manner while
the TCC is active.
7.3.1.2
Digital Thermal Sensor
Each processor execution core has an on-die Digital Thermal Sensor (DTS) which
detects the core’s instantaneous temperature. The DTS is the preferred method of
monitoring processor die temperature because:
• It is located near the hottest portions of the die.
• It can accurately track the die temperature and ensure that the Adaptive Thermal
Monitor is not excessively activated.
Temperature values from the DTS can be retrieved through:
• A software interface via processor Model Specific Register (MSR).
• A processor hardware interface as described in Section 7.3.5, “Platform
Environment Control Interface (PECI)”.
Note:
The temperature retrieved by the processor MSR is the instantaneous temperature of
the given core. The temperature retrieved via PECI is the average of the highest DTS
temperature in the package over a 256 ms time window. Intel recommends using the
PECI-reported temperature for platform thermal control that benefits from averaging,
such as fan speed control. The average DTS temperature may not be a good indicator
of package Adaptive Thermal Monitor activation or rapid increases in temperature that
triggers the Out of Specification status bit within the PACKAGE_THERM_STATUS MSR
01B1h and IA32_THERM_STATUS MSR 19Ch.
Note:
Code execution is halted in C1-C7. Therefore temperature cannot be read via the
processor MSR without bringing a core back into C0. However, the temperature can still
be monitored through PECI in lower C-states except for C7.
Unlike traditional thermal devices, the DTS outputs a temperature relative to the
maximum supported operating temperature of the processor (TJ-MAX), regardless of
TCC activation offset. It is the responsibility of software to convert the relative
temperature to an absolute temperature. The absolute reference temperature is
readable in the TEMPERATURE_TARGET MSR 1A2h. The temperature returned by the
DTS is an implied negative integer indicating the relative offset from TJ-MAX. The DTS
does not report temperatures greater than TJ-MAX.
The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor
trigger point. When a package DTS indicates that it has reached the TCC activation (a
reading of 0x0, except when the TCC activation offset is changed), the TCC activates
and indicates an Adaptive Thermal Monitor event. A TCC activation lowers the IA core
frequency, voltage or both.
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Changes to the temperature can be detected via two programmable thresholds located
in the processor thermal MSRs. These thresholds have the capability of generating
interrupts via the core's local APIC. See the Intel® 64 and IA-32 Architectures Software
Developer's Manual for specific register and programming details.
7.3.1.2.1
Digital Thermal Sensor Accuracy (Taccuracy)
The error associated with DTS measurement does not exceed ±5°C at TJ-MAX. The
DTS measurement within the entire operating range meets a ±5°C accuracy.
7.3.1.3
Fan Speed Control with Digital Thermal Sensor
Digital Thermal Sensor based fan speed control (TFAN) is a recommended feature to
achieve optimal thermal performance. At the TFAN temperature, Intel recommends full
cooling capability well before the DTS reading reaches Tj,max. An example is TFAN =
Tj,max – 10 ºC.
7.3.1.4
PROCHOT# Signal
PROCHOT# (processor hot) is asserted when the processor core temperature has
reached its maximum operating temperature (TJ-MAX). See Figure 7-1 for a timing
diagram of the PROCHOT# signal assertion relative to the Adaptive Thermal Response.
Only a single PROCHOT# pin exists at a package level. When any core arrives at the
TCC activation point, the PROCHOT# signal is asserted. PROCHOT# assertion policies
are independent of Adaptive Thermal Monitor enabling.
Note:
Bus snooping and interrupt latching are active while the TCC is active.
Note:
For the package C7 state, PROCHOT# may de-assert for the duration of the C7 state
residency, even if the processor enters the idle state operating at the TCC activation
temperature. The PECI interface is fully operational during all C-states and it is
expected that the platform continues to manage processor package thermals, even
during idle states by regularly polling for thermal data over PECI.
7.3.1.4.1
Bi-Directional PROCHOT#
By default, the PROCHOT# signal is defined as an output only. However, the signal may
be configured as bi-directional. When configured as a bi-directional signal, PROCHOT#
can be used for thermally protecting other platform components should they overheat
as well. When PROCHOT# is driven by an external device:
• The package immediately transitions to the minimum operation points (voltage and
frequency) supported by the processor cores. This is contrary to the internallygenerated Adaptive Thermal Monitor response.
• Clock modulation is not activated.
The TCC remains active until the system deasserts PROCHOT#. The processor can be
configured to generate an interrupt upon assertion and deassertion of the PROCHOT#
signal. See the VR12/IMVP7 SVID Protocol for details on implementing the bidirectional PROCHOT# feature.
Note:
Toggling PROCHOT# more than once in 1.5 ms period results in constant Pn state of
the processor.
7.3.1.4.2
Voltage Regulator Protection Versus PROCHOT#
PROCHOT# may be used for thermal protection of voltage regulators (VR). System
designers can create a circuit to monitor the VR temperature and activate the TCC
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low)
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and activating the TCC, the VR cools down as a result of reduced processor power
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermal
design current (ICCTDC) instead of maximum current. Systems should still provide
proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case
of system cooling failure. Overall, the system thermal design should allow the power
delivery circuitry to operate within its temperature specification even while the
processor is operating at its TDP.
7.3.1.4.3
Thermal Solution Design and PROCHOT# Behavior
With a properly designed and characterized thermal solution, it is anticipated that
PROCHOT# is only asserted for very short periods of time when running the most
power intensive applications. The processor performance impact due to these brief
periods of TCC activation is expected to be so minor that it would be immeasurable.
However, an under-designed thermal solution that is not able to prevent excessive
assertion of PROCHOT# in the anticipated ambient environment may:
• Cause a noticeable performance loss.
• Result in prolonged operation at or above the specified maximum junction
temperature and affect the long-term reliability of the processor.
• May be incapable of cooling the processor even when the TCC is active continuously
(in extreme situations).
See the Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C,
and Intel® Core™ i3-3115C Processors for Communications Infrastructure Thermal and
Mechanical Design Guide for information on implementing the bi-directional PROCHOT#
feature and designing a compliant thermal solution.
7.3.1.4.4
Low-Power States and PROCHOT# Behavior
If the processor enters a low-power package idle state such as C3 or C6/C7 with
PROCHOT# asserted, PROCHOT# remains asserted until:
• The processor exits the low-power state
• The processor junction temperature drops below the thermal trip point
For the package C7 state, PROCHOT# may deassert for the duration of C7 state
residency even if the processor enters the idle state operating at the TCC activation
temperature. The PECI interface is fully operational during all C-states and it is
expected that the platform continues to manage processor (“package”) core thermals
even during idle states by regularly polling for thermal data over PECI.
7.3.1.4.5
THERMTRIP# Signal
Regardless of enabling the automatic or on-demand modes, in the event of a
catastrophic cooling failure, the package automatically shuts down when the silicon has
reached an elevated temperature that risks physical damage to the product. At this
point the THERMTRIP# signal is active.
7.3.1.4.6
Critical Temperature Detection
Critical Temperature detection is performed by monitoring the package temperature.
This feature is intended for graceful shutdown before the THERMTRIP# is activated,
however, the processor execution is not guaranteed between critical temperature and
THERMTRIP#. If the package's Adaptive Thermal Monitor is triggered and the
temperature remains high, a critical temperature status and sticky bit are latched in the
PACKAGE_THERM_STATUS MSR 1B1h and also generates a thermal interrupt if
enabled.
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7.3.2
Processor Core Specific Thermal Features
7.3.2.1
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption via clock modulation. This mechanism is
referred to as “On-Demand” mode and is distinct from Adaptive Thermal Monitor and
bi-directional PROCHOT#. Processor platforms must not rely on software usage of this
mechanism to limit the processor temperature. On-Demand Mode can be done via
processor MSR or chipset I/O emulation.
On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor.
However, if the system software tries to enable On-Demand mode at the same time the
TCC is engaged, the factory configured duty cycle of the TCC overrides the duty cycle
selected by the On-Demand mode. If the I/O based and MSR-based On-Demand modes
are in conflict, the duty cycle selected by the I/O emulation-based On-Demand mode
takes precedence over the MSR-based On-Demand Mode.
7.3.2.1.1
MSR Based On-Demand Mode
If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor immediately
reduces its power consumption via modulation of the internal core clock, independent
of the processor temperature. The duty cycle of the clock modulation is programmable
via Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this mode, the duty cycle
can be programmed in either 12.5% or 6.25% increments (discoverable via CPU ID).
Thermal throttling using this method modulates each processor core’s clock
independently.
7.3.2.1.2
I/O Emulation-Based On-Demand Mode
I/O emulation-based clock modulation provides legacy support for operating system
software that initiates clock modulation through I/O writes to ACPI defined processor
clock control registers on the chipset (PROC_CNT). Thermal throttling using this
method modulates all processor cores simultaneously.
7.3.3
Memory Controller Specific Thermal Features
The memory controller provides the ability to initiate memory throttling based upon
memory temperature. The memory temperature can be provided to the memory
controller via PECI or can be estimated by the memory controller based upon memory
activity. The temperature trigger points are programmable by memory mapped IO
registers.
7.3.3.1
Programmable Trip Points
This memory controller provides programmable critical, hot and warm trip points.
Crossing a critical trip point forces a system shutdown. Crossing a hot or warm trip
point initiates throttling. The amount of memory throttle at each trip point is
programmable.
7.3.4
Memory Thermal Management
The integrated memory controller (IMC) provides thermal protection for system
memory DIMMs using memory bandwidth throttling. Like processor package throttling,
memory throttling is initiated based on temperature. The IMC offers two levels of
throttling (warm and hot). The temperature and the amount of bandwidth reduced
while throttling is programmable for the warm and hot trip points through memory
mapped I/O registers.
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Memory temperature can be read directly by a physical thermal sensor on the DIMM
(TS-on-DIMM) or a physical temperature sensor placed on the motherboard (TS-onBoard). Memory throttling based on physical temperature sensor readings is known as
Closed Loop Thermal Throttling (CLTT). The memory temperature readings are
reported from the platform to the memory controller using PECI.
If no physical thermal sensor is available, the memory controller can estimate the
temperature based on memory activity. Memory thermal throttling that is initiated with
no direct temperature reading is known as Open Loop Thermal Throttling (OLTT). The
processor features the Virtual Temperature Sensor (VTS) for OLTT. For more details on
the TS-on-DIMM, TS-on-Board, and the VTS enabling see the Intel® Xeon® E3-1125C
v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C
Processors for Communications Infrastructure Thermal and Mechanical Design Guide.
7.3.5
Platform Environment Control Interface (PECI)
The Platform Environment Control Interface (PECI) is a one-wire interface that provides
a communication channel between Intel processor and chipset components to external
monitoring devices. The processor implements a PECI interface to allow communication
of processor thermal information to other devices on the platform. The processor
provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at
the factory to provide a digital representation of relative processor temperature.
Averaged DTS values are read via the PECI interface.
The PECI physical layer is a self-clocked one-wire bus that begins each bit with a
driven, rising edge from an idle level near zero volts. The duration of the signal driven
high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes
variable data transfer rate established with every message. The single wire interface
provides low board routing overhead for the multiple load connections in the congested
routing area near the processor and chipset components. Bus speed, error checking,
and low protocol overhead provides adequate link bandwidth and reliability to transfer
critical device operating conditions and configuration information.
7.3.5.1
Processor Thermal Data Sample Rate and Filtering
For additional PECI feature details, see the Ivy Bridge Processor - Platform
Environment Control Interface 3.0 - Implementation Guide.
§§
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8.0
Signal Description
This chapter describes the processor signals. They are arranged in functional groups
according to their associated interface or category. The following notations are used to
describe the signal type:
Notations
Signal Type
I
Input Pin
O
Output Pin
I/O
Bi-directional Input/Output Pin
The signal description also includes the type of buffer used for the particular signal.
Table 8-1.
Signal Description Buffer Types
Signal
Description
PCI Express*
PCI Express* interface signals. These signals are compatible with PCI Express* 2.0/
PCI Express* 3.0 Signalling Environment AC Specifications and are AC coupled. The
buffers are not 3.3-V tolerant. See the PCIe* specification.
DMI
Direct Media Interface signals. These signals are compatible with PCI Express* 2.0
Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3V tolerant.
CMOS
CMOS buffers. 1.1-V tolerant
DDR3
DDR3 buffers. 1.5-V tolerant
DDR3L
DDR3L buffers. 1.35-V tolerant
A
Analog reference or output. May be used as a threshold voltage or for buffer
compensation
Ref
Voltage reference signal
Asynchronous1
Signal has no timing relationship with any reference clock
Notes:
1.
Qualifier for a buffer type.
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8.1
System Memory Interface
Table 8-2.
Memory Channel A (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
Bank Select: These signals define which banks
are selected within each SDRAM rank.
O
DDR3
SA_WE#
Write Enable Control Signal: Used with
SA_RAS# and SA_CAS# (along with SA_CS#) to
define the SDRAM Commands.
O
DDR3
SA_RAS#
RAS Control Signal: Used with SA_CAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
DDR3
SA_CAS#
CAS Control Signal: Used with SA_RAS# and
SA_WE# (along with SA_CS#) to define the SRAM
Commands.
O
DDR3
SA_DQS[7:0]
SA_DQS#[7:0]
Data Strobes: SA_DQS[7:0] and its complement
signal group make up a differential strobe pair.
The data is captured at the crossing point of
SA_DQS[7:0] and its SA_DQS#[7:0] during read
and write transactions.
I/O
DDR3
SA_DQS[8]
SA_DQS#[8]
Data Strobes: SA_DQS[8] is the data strobe for
the ECC check data bits SA_DQ[71:64].
SA_DQS#[8] is the complement strobe for the
ECC check data bits SA_DQ[71:64]
The data is captured at the crossing point of
SA_DQS[8:0] and its SA_DQS#[8:0] during read
and write transactions.
Note: Not required for non-ECC mode
I/O
DDR3
SA_DQ[63:0]
Data Bus: Channel A data signal interface to the
SDRAM data bus.
I/O
DDR3
SA_ECC_CB[7:0]
ECC Data Lines: Data Lines for ECC Check Byte
for Channel A.
Note: Not required for non-ECC mode
I/O
DDR3
SA_MA[15:0]
Memory Address: These signals are used to
provide the multiplexed row and column address
to the SDRAM.
O
DDR3
SA_CK[3:0]
SDRAM Differential Clock: Channel A SDRAM
Differential clock signal pair. The crossing of the
positive edge of SA_CK and the negative edge of
its complement SA_CK# are used to sample the
command and control signals on the SDRAM.
Signals 3:2 are used only for two DPC system.
O
DDR3
SA_CK#[3:0]
SDRAM Inverted Differential Clock: Channel A
SDRAM Differential clock signal-pair complement.
Signals 3:2 are used only for two DPC system.
O
DDR3
SA_BS[2:0]
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Table 8-2.
Memory Channel A (Sheet 2 of 2)
Signal Name
Table 8-3.
Description
Direction/Buffer
Type
SA_CKE[3:0]
Clock Enable: (one per rank) Used to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of selfrefresh during STR.
Signals 3:2 are used only for two DPC system.
O
DDR3
SA_CS#[3:0]
Chip Select: (one per rank) Used to select
particular SDRAM components during the active
state. There is one Chip Select for each SDRAM
rank.
Signals 3:2 are used only for two DPC system.
O
DDR3
SA_ODT[3:0]
On Die Termination: Active Termination Control.
Signals 3:2 are used only for two DPC system.
O
DDR3
Memory Channel B (Sheet 1 of 2)
Signal Name
Description
Direction/Buffer
Type
SB_BS[2:0]
Bank Select: These signals define which banks are
selected within each SDRAM rank.
O
DDR3
SB_WE#
Write Enable Control Signal: Used with
SB_RAS# and SB_CAS# (along with SB_CS#) to
define the SDRAM Commands.
O
DDR3
SB_RAS#
RAS Control Signal: Used with SB_CAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
O
DDR3
SB_CAS#
CAS Control Signal: Used with SB_RAS# and
SB_WE# (along with SB_CS#) to define the SRAM
Commands.
O
DDR3
SB_DQS[7:0]
SB_DQS#[7:0]
Data Strobes: SB_DQS[7:0] and its complement
signal group make up a differential strobe pair. The
data is captured at the crossing point of
SB_DQS[7:0] and its SB_DQS#[7:0] during read
and write transactions.
I/O
DDR3
SB_DQS[8]
SB_DQS#[8]
Data Strobes: SB_DQS[8] is the data strobe for
the ECC check data bits SB_DQ[71:64].
SB_DQS#[8] is the complement strobe for the ECC
check data bits SB_DQ[71:64]
The data is captured at the crossing point of
SB_DQS[8:0] and its SB_DQS#[8:0] during read
and write transactions.
Note: Not required for non-ECC mode
I/O
DDR3
SB_DQ[63:0]
Data Bus: Channel B data signal interface to the
SDRAM data bus.
I/O
DDR3
SB_ECC_CB[7:0]
ECC Data Lines: Data Lines for ECC Check Byte
for Channel B.
Note: Not required for non-ECC mode
I/O
DDR3
Memory Address: These signals are used to
provide the multiplexed row and column address to
the SDRAM.
O
DDR3
SB_MA[15:0]
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Table 8-3.
Memory Channel B (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type
SB_CK[3:0]
SDRAM Differential Clock: Channel B SDRAM
Differential clock signal pair. The crossing of the
positive edge of SB_CK and the negative edge of its
complement SB_CK# are used to sample the
command and control signals on the SDRAM.
Signals 3:2 are used for two DPC system.
O
DDR3
SB_CK#[3:0]
SDRAM Inverted Differential Clock: Channel B
SDRAM Differential clock signal-pair complement.
Signals 3:2 are used for two DPC system.
O
DDR3
SB_CKE[3:0]
Clock Enable: (1 per rank) Used to:
• Initialize the SDRAMs during power-up.
• Power-down SDRAM ranks.
• Place all SDRAM ranks into and out of selfrefresh during STR.
Signals 3:2 are used for two DPC system.
O
DDR3
SB_CS#[3:0]
Chip Select: (1 per rank) Used to select particular
SDRAM components during the active state. There
is one Chip Select for each SDRAM rank.
Bits [3:2] are used only for two DPC system.
O
DDR3
SB_ODT[3:0]
On Die Termination: Active Termination Control.
Bits [3:2] are used only for two DPC system.
O
DDR3
8.2
Memory Reference and Compensation
Table 8-4.
Memory Reference and Compensation
Signal Name
SM_RCOMP[2:0]
Description
System Memory Impedance Compensation:
• SM_RCOMP[0] Pull Down to VSS via 140 Ω ±1%
• SM_RCOMP[1] Pull Down to VSS via 25.5 Ω ±1%
• SM_RCOMP[2] Pull Down to VSS via 200 Ω ±1%
Direction/Buffer
Type
I/Analog
SM_VREF
DDR3 Reference Voltage: This provides reference
voltage to the DDR3 interface and is defined as VDDQ/
2
I/Analog
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Memory Channel A/B DIMM DQ Voltage
Reference: These pins are not connected and are not
supported.
O/Analog
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8.3
Reset and Miscellaneous Signals
Table 8-5.
Reset and Miscellaneous Signals
Signal Name
Description
Direction/Buffer
Type
Configuration Signals:
The CFG signals have a default value of '1' if not
terminated on the board.
• CFG[1:0]: Reserved configuration ball. A test
point may be placed on the board for this ball.
• CFG[2]: PCI Express* Static x16 Lane (Port1)
Numbering Reversal.
•
CFG[17:0]
•
•
— 1 = Normal operation (default)
— 0 = Lane numbers reversed
CFG[3]: PCI Express* Static x4 Lane (Port2)
Numbering Reversal.
— 1 = Normal operation (default)
— 0 = Lane numbers reversed
CFG[4]: Reserved configuration ball. A test
point may be placed on the board for this ball.
CFG[6:5]: PCI Express* Bifurcation:
I
CMOS
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[17:7]: Reserved configuration balls. A test
point may be placed on the board for these balls.
Note: These strap values are read upon power up
and the pre-boot software enables the
appropriate number of controllers and lane
orientation. See Section 3.2.5,
“Configuring PCIe* Lanes” and Section
3.2.6, “Lane Reversal on PCIe* Interface”.
PM_SYNC
RESET#
SM_DRAMRST#
Power Management Sync: A sideband signal to
communicate power management status from the
platform to the processor.
I
CMOS
Platform Reset pin driven by the PCH
I
CMOS
DDR3 DRAM Reset: Reset signal from processor
to DRAM devices. One common to all channels.
0
CMOS
RSVD_[21:1],RSVD_[32:23],
RSVD_[43:34],RSVD_[57:45]
RESERVED: All signals in this group are RSVD pins
which must be left unconnected.
RSVD_22, RSVD_33, RSVD_44
Terminated RESERVED: These pins must be
shorted together and tied to VCCP through 24.9 Ω
±1% resistor.
No Connect
I
CMOS
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8.4
PCI Express* Based Interface Signals
Table 8-6.
PCI Express* Interface Signals
Signal Name
PCIE_ICOMPI
PCIE_ICOMPO
PCIE_RCOMPO
Description
PCI Express* Compensation.
These pins must be shorted together and tied to VCCIO
through 24.9 Ω ±1% resistor.
Direction/Buffer
Type
I/Analog
PCIE1_RX[15:0]
PCIE1_RX#[15:0]
PCI Express* Receive Differential Pair.
I/PCI Express*
PCIE1_TX[15:0]
PCIE1_TX#[15:0]
PCI Express* Transmit Differential Pair.
O/PCI Express*
PCIE2_RX[3:0]
PCIE2_RX#[3:0]
PCI Express* Receive Differential Pair.
x4 Port
I/PCI Express*
PCIE2_TX[3:0]
PCIE2_TX#[3:0]
PCI Express* Transmit Differential Pair.
x4 Port
O/PCI Express*
8.5
DMI
Table 8-7.
DMI - Processor to PCH Serial Interface
Signal Name
Description
Direction/Buffer
Type
DMI_RX[3:0]
DMI_RX#[3:0]
DMI Input from PCH: Direct Media Interface
receive differential pair.
I
DMI
DMI_TX[3:0]
DMI_TX#[3:0]
DMI Output to PCH: Direct Media Interface
transmit differential pair.
O
DMI
8.6
PLL Signals
Table 8-8.
PLL Signals
Signal Name
Description
Direction/Buffer
Type
BCLK
BCLK#
Differential bus clock input to the processor and PCI
Express*.
I
Diff Clk
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8.7
TAP Signals
Table 8-9.
TAP Signals
Signal Name
Description
Direction/Buffer
Type
BPM#[7:0]
Breakpoint and Performance Monitor Signals:
Outputs from the processor that indicate the status
of breakpoints and programmable counters used
for monitoring processor performance.
I/O
CMOS
PRDY#
PRDY# is a processor output used by debug tools
to determine processor debug readiness.
O
Asynchronous CMOS
PREQ#
PREQ# is used by debug tools to request debug
operation of the processor.
I
Asynchronous CMOS
TCK
TCK (Test Clock): Provides the clock input for the
processor Test Bus (also known as the Test Access
Port). TCK must be driven low or allowed to float
during power on Reset.
I
CMOS
TDI
TDI (Test Data In): Transfers serial test data into
the processor. TDI provides the serial input needed
for JTAG specification support.
I
CMOS
TDO
TDO (Test Data Out) transfers serial test data out
of the processor. TDO provides the serial output
needed for JTAG specification support.
O
Open Drain
TMS
TMS (Test Mode Select): A JTAG specification
support signal used by debug tools.
I
CMOS
TRST# (Test Reset) resets the Test Access Port
(TAP) logic. TRST# must be driven low during
power on Reset.
I
CMOS
TRST#
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8.8
Error and Thermal Protection
Table 8-10. Error and Thermal Protection
Signal Name
Description
Direction/Buffer
Type
CATERR#
Catastrophic Error: This signal indicates that the
system has experienced a catastrophic error and
cannot continue to operate. The processor sets this
for non-recoverable machine check errors or other
unrecoverable internal errors. External agents are
allowed to assert this pin which causes the
processor to take a machine check exception.
CATERR# is used for signaling the following types
of errors:
• Legacy MCERR’s, CATERR# is asserted for 16
BCLKs.
• Legacy IERR’s, CATERR# remains asserted
until warm or cold reset.
O
CMOS
PECI
PECI (Platform Environment Control
Interface): A serial sideband interface to the
processor, it is used primarily for thermal, power,
and error management.
I/O
Asynchronous
PROCHOT#
Processor Hot: PROCHOT# goes active when the
processor temperature monitoring sensor(s)
detects that the processor has reached its
maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit
(TCC) has been activated, if enabled. This signal
can also be driven to the processor to activate the
TCC.
CMOS Input/
Open-Drain Output
THERMTRIP#
Thermal Trip: The processor protects itself from
catastrophic overheating by use of an internal
thermal sensor. This sensor is set well above the
normal operating temperature to ensure that there
are no false trips. The processor stops all execution
when the junction temperature exceeds
approximately 130°C. This is signaled to the
system by the THERMTRIP# pin.
O
Asynchronous CMOS
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8.9
Power Sequencing
Table 8-11. Power Sequencing
Signal Name
SM_DRAMPWROK
UNCOREPWRGOOD
8.10
Description
Direction/Buffer
Type
SM_DRAMPWROK Processor Input: Connects to
PCH DRAMPWROK.
I
Asynchronous
CMOS
The processor requires this input signal to be a clean
indication that the VCCSA, VCCIO, and VDDQ, power
supplies are stable and within specifications. This
requirement applies regardless of the S-state of the
processor. 'Clean' implies that the signal remains low
(capable of sinking leakage current), without glitches,
from the time that the power supplies are turned on
until they come within specification. The signal must
then transition monotonically to a high state. This is
connected to the PCH PROCPWRGD signal.
I
Asynchronous
CMOS
PROC_DETECT#
PROC_DETECT (Processor Detect): pulled to
ground on the processor package. There is no
connection to the processor silicon for this signal.
System board designers may use this signal to
determine if the processor is present.
PROC_SELECT#
Processor Select: This signal is an output that
indicates if the processor used is 2nd Generation
Intel® Core™ processor family or 3rd Generation
Intel® Core™ processor family. For 2nd Generation
Intel® Core™ processor family, the output will be high.
For 3rd Generation Intel® Core™ processor family the
output will be low.
N/A
O
Processor Power and Ground Signals
Table 8-12. Processor Power Signals (Sheet 1 of 2)
Signal Name
VCC
Description
Direction/Buffer
Type
Processor core power rail
Ref
VCCIO
Processor power for I/O
Ref
VDDQ
Processor I/O supply voltage for DDR3.
Ref
VCCPLL provides isolated power for internal
processor PLLs.
Ref
System Agent power supply
Ref
VCCPLL
VCCSA
VIDSOUT
VIDSCLK
VIDALERT#
VIDALERT#, VIDSCLK, and VIDSOUT comprise a
three signal serial synchronous interface used to
transfer power management information between
the processor and the voltage regulator controllers.
This serial VID (SVID) interface replaces the
parallel VID interface on previous processors.
I/O
O
I
CMOS
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Table 8-12. Processor Power Signals (Sheet 2 of 2)
Signal Name
Description
Direction/Buffer
Type
VCCSA_VID
Voltage selection for VCCSA: For 2nd Generation
Intel® Core™ processor family, the output will be
low. For 3rd Generation Intel® Core™ processor
family, the output may be high or low, and may
change dynamically.
O
CMOS
VSS
Note:
8.11
Processor ground node
GND
The VCCSA_VID can toggle at most once in 500 µS; The slew rate of VCCSA_VID is 1 V/nS.
Sense Pins
Table 8-13. Sense Pins
8.12
Signal Name
Description
Direction/Buffer
Type
VCC_SENSE
VSS_SENSE
VCC_SENSE and VSS_SENSE provide an isolated,
low impedance connection to the processor core
voltage and ground. They can be used to sense or
measure voltage near the silicon.
O
Analog
VCCIO_SENSE
VSS_SENSE_VCCIO
VCCIO_SENSE and VSS_SENSE_VCCIO provide an
isolated, low impedance connection to the
processor VCCIO voltage and ground. They can be
used to sense or measure voltage near the silicon.
O
Analog
VCCSA_VCCSENCE
VCCSA_VSSSENCE
VCCSA_VCCSENCE and VCCSA_VSSSENCE provide
an isolated, low impedance connection to the
processor system agent voltage. It can be used to
sense or measure voltage near the silicon.
O
Analog
Processor Internal Pull Up/Pull Down
Table 8-14. Processor Internal Pull Up/Pull Down
Signal Name
BPM[7:0]
Pull Up/Pull Down
Pull Up
Rail
VCCIO
Value
65-165 Ω
PRDY#
Pull Up
VCCIO
65-165 Ω
PREQ#
Pull Up
VCCIO
65-165 Ω
TCK
Pull Down
VSS
5-15 kΩ
TDI
Pull Up
VCCIO
5-15 kΩ
TMS
Pull Up
VCCIO
5-15 kΩ
TRST#
Pull Up
VCCIO
5-15 kΩ
CFG[17:0]
Pull Up
VCCIO
5-15 kΩ
§§
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9.0
Electrical Specifications
9.1
Power and Ground Pins
The processor has VCC, VCCIO, VDDQ, VCCPLL, VCCSA and VSS (ground) inputs for on-chip
power distribution. All power pins must be connected to their respective processor
power planes, while all VSS pins must be connected to the system ground plane. Use of
multiple power and ground planes is recommended to reduce I*R drop. The VCC pins
must be supplied with the voltage determined by the processor Serial Voltage
IDentification (SVID) interface. Table 9-1 specifies the voltage level for the various
VIDs.
9.2
Decoupling Guidelines
Due to its large number of transistors and high internal clock speeds, the processor is
capable of generating large current swings between low- and full-power states. To keep
voltages within specification, output decoupling must be properly designed.
Caution:
Design the board to ensure that the voltage provided to the processor remains within
the specifications listed in Table 9-5. Failure to do so can result in timing violations or
reduced lifetime of the processor.
9.2.1
Voltage Rail Decoupling
The voltage regulator solution must:
• Provide sufficient decoupling to compensate for large current swings generated
during different power mode transitions.
• Provide low parasitic resistance from the regulator to the socket.
• Meet voltage and current specifications as defined in Table 9-5.
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9.3
Processor Clocking (BCLK, BCLK#)
The processor utilizes a differential clock to generate the processor core(s) operating
frequency, memory controller frequency, and other internal clocks. The processor core
frequency is determined by multiplying the processor core ratio by 100 MHz. Clock
multiplying within the processor is provided by an internal phase locked loop (PLL),
which requires a constant frequency input, with exceptions for Spread Spectrum
Clocking (SSC).
The processor’s maximum core frequency is configured during power-on reset by using
its manufacturing default value. This value is the highest core multiplier at which the
processor can operate. If lower maximum speeds are desired, the appropriate ratio can
be configured via the FLEX_RATIO MSR.
9.3.1
PLL Power Supply
An on-die PLL filter solution is implemented on the processor.
9.4
Serial Voltage Identification (SVID)
The SVID specifications for the processor VCC is defined in the VR12 / IMVP7 SVID
Protocol. The processor uses three signals for the serial voltage identification interface
to support automatic selection of voltages. Table 9-1 specifies the voltage level
corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this table
refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage
regulation circuit cannot supply the voltage that is requested, the voltage regulator
must disable itself. VID signals are CMOS push/pull drivers. The VID codes change due
to temperature and/or current load changes in order to minimize the power of the part.
A voltage range is provided in Table 9-1. The specifications are set so that one voltage
regulator can operate with all supported frequencies.
Individual processor VID values may be set during manufacturing so that two devices
at the same core frequency may have different default VID settings. This is shown in
the VID range values in Table 9-5. The processor provides the ability to operate while
transitioning to an adjacent VID and its associated voltage. This represents a DC shift
in the loadline.
Note:
Transitions above the maximum specified VID are not permitted. Table 9-5 includes VID
step sizes and DC shift ranges. Minimum and maximum voltages must be maintained.
At condition outside functional operation condition limits, neither functionality nor long
term reliability can be expected. If a device is returned to conditions within functional
operation limits after having been subjected to conditions outside these limits, but
within the absolute maximum and minimum ratings, the device may be functional, but
with its lifetime degraded on exposure to conditions exceeding the functional operation
condition limits.
The VR utilized must be capable of regulating its output to the value defined by the new
VID values issued. DC specifications for dynamic VID transitions are included in
Table 9-5.
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 1 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
0
0
0
0
0
0
0
0
0
0
0.00000
0
0
0
0
0
0
0
1
0
1
0.25000
0
0
0
0
0
0
1
0
0
2
0.25500
0
0
0
0
0
0
1
1
0
3
0.26000
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Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 2 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
0
0
0
0
0
1
0
0
0
4
0.26500
0
0
0
0
0
1
0
1
0
5
0.27000
0
0
0
0
0
1
1
0
0
6
0.27500
0
0
0
0
0
1
1
1
0
7
0.28000
0
0
0
0
1
0
0
0
0
8
0.28500
0
0
0
0
1
0
0
1
0
9
0.29000
0
0
0
0
1
0
1
0
0
A
0.29500
0
0
0
0
1
0
1
1
0
B
0.30000
0
0
0
0
1
1
0
0
0
C
0.30500
0
0
0
0
1
1
0
1
0
D
0.31000
0
0
0
0
1
1
1
0
0
E
0.31500
0
0
0
0
1
1
1
1
0
F
0.32000
0
0
0
1
0
0
0
0
1
0
0.32500
0
0
0
1
0
0
0
1
1
1
0.33000
0
0
0
1
0
0
1
0
1
2
0.33500
0
0
0
1
0
0
1
1
1
3
0.34000
0
0
0
1
0
1
0
0
1
4
0.34500
0
0
0
1
0
1
0
1
1
5
0.35000
0
0
0
1
0
1
1
0
1
6
0.35500
0
0
0
1
0
1
1
1
1
7
0.36000
0
0
0
1
1
0
0
0
1
8
0.36500
0
0
0
1
1
0
0
1
1
9
0.37000
0
0
0
1
1
0
1
0
1
A
0.37500
0
0
0
1
1
0
1
1
1
B
0.38000
0
0
0
1
1
1
0
0
1
C
0.38500
0
0
0
1
1
1
0
1
1
D
0.39000
0
0
0
1
1
1
1
0
1
E
0.39500
0
0
0
1
1
1
1
1
1
F
0.40000
0
0
1
0
0
0
0
0
2
0
0.40500
0
0
1
0
0
0
0
1
2
1
0.41000
0
0
1
0
0
0
1
0
2
2
0.41500
0
0
1
0
0
0
1
1
2
3
0.42000
0
0
1
0
0
1
0
0
2
4
0.42500
0
0
1
0
0
1
0
1
2
5
0.43000
0
0
1
0
0
1
1
0
2
6
0.43500
0
0
1
0
0
1
1
1
2
7
0.44000
0
0
1
0
1
0
0
0
2
8
0.44500
0
0
1
0
1
0
0
1
2
9
0.45000
0
0
1
0
1
0
1
0
2
A
0.45500
0
0
1
0
1
0
1
1
2
B
0.46000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 3 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
0
0
1
0
1
1
0
0
2
C
0.46500
0
0
1
0
1
1
0
1
2
D
0.47000
0
0
1
0
1
1
1
0
2
E
0.47500
0
0
1
0
1
1
1
1
2
F
0.48000
0
0
1
1
0
0
0
0
3
0
0.48500
0
0
1
1
0
0
0
1
3
1
0.49000
0
0
1
1
0
0
1
0
3
2
0.49500
0
0
1
1
0
0
1
1
3
3
0.50000
0
0
1
1
0
1
0
0
3
4
0.50500
0
0
1
1
0
1
0
1
3
5
0.51000
0
0
1
1
0
1
1
0
3
6
0.51500
0
0
1
1
0
1
1
1
3
7
0.52000
0
0
1
1
1
0
0
0
3
8
0.52500
0
0
1
1
1
0
0
1
3
9
0.53000
0
0
1
1
1
0
1
0
3
A
0.53500
0
0
1
1
1
0
1
1
3
B
0.54000
0
0
1
1
1
1
0
0
3
C
0.54500
0
0
1
1
1
1
0
1
3
D
0.55000
0
0
1
1
1
1
1
0
3
E
0.55500
0
0
1
1
1
1
1
1
3
F
0.56000
0
1
0
0
0
0
0
0
4
0
0.56500
0
1
0
0
0
0
0
1
4
1
0.57000
0
1
0
0
0
0
1
0
4
2
0.57500
0
1
0
0
0
0
1
1
4
3
0.58000
0
1
0
0
0
1
0
0
4
4
0.58500
0
1
0
0
0
1
0
1
4
5
0.59000
0
1
0
0
0
1
1
0
4
6
0.59500
0
1
0
0
0
1
1
1
4
7
0.60000
0
1
0
0
1
0
0
0
4
8
0.60500
0
1
0
0
1
0
0
1
4
9
0.61000
0
1
0
0
1
0
1
0
4
A
0.61500
0
1
0
0
1
0
1
1
4
B
0.62000
0
1
0
0
1
1
0
0
4
C
0.62500
0
1
0
0
1
1
0
1
4
D
0.63000
0
1
0
0
1
1
1
0
4
E
0.63500
0
1
0
0
1
1
1
1
4
F
0.64000
0
1
0
1
0
0
0
0
5
0
0.64500
0
1
0
1
0
0
0
1
5
1
0.65000
0
1
0
1
0
0
1
0
5
2
0.65500
0
1
0
1
0
0
1
1
5
3
0.66000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
83
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—9.0
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 4 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
0
1
0
1
0
1
0
0
5
4
0.66500
0
1
0
1
0
1
0
1
5
5
0.67000
0
1
0
1
0
1
1
0
5
6
0.67500
0
1
0
1
0
1
1
1
5
7
0.68000
0
1
0
1
1
0
0
0
5
8
0.68500
0
1
0
1
1
0
0
1
5
9
0.69000
0
1
0
1
1
0
1
0
5
A
0.69500
0
1
0
1
1
0
1
1
5
B
0.70000
0
1
0
1
1
1
0
0
5
C
0.70500
0
1
0
1
1
1
0
1
5
D
0.71000
0
1
0
1
1
1
1
0
5
E
0.71500
0
1
0
1
1
1
1
1
5
F
0.72000
0
1
1
0
0
0
0
0
6
0
0.72500
0
1
1
0
0
0
0
1
6
1
0.73000
0
1
1
0
0
0
1
0
6
2
0.73500
0
1
1
0
0
0
1
1
6
3
0.74000
0
1
1
0
0
1
0
0
6
4
0.74500
0
1
1
0
0
1
0
1
6
5
0.75000
0
1
1
0
0
1
1
0
6
6
0.75500
0
1
1
0
0
1
1
1
6
7
0.76000
0
1
1
0
1
0
0
0
6
8
0.76500
0
1
1
0
1
0
0
1
6
9
0.77000
0
1
1
0
1
0
1
0
6
A
0.77500
0
1
1
0
1
0
1
1
6
B
0.78000
0
1
1
0
1
1
0
0
6
C
0.78500
0
1
1
0
1
1
0
1
6
D
0.79000
0
1
1
0
1
1
1
0
6
E
0.79500
0
1
1
0
1
1
1
1
6
F
0.80000
0
1
1
1
0
0
0
0
7
0
0.80500
0
1
1
1
0
0
0
1
7
1
0.81000
0
1
1
1
0
0
1
0
7
2
0.81500
0
1
1
1
0
0
1
1
7
3
0.82000
0
1
1
1
0
1
0
0
7
4
0.82500
0
1
1
1
0
1
0
1
7
5
0.83000
0
1
1
1
0
1
1
0
7
6
0.83500
0
1
1
1
0
1
1
1
7
7
0.84000
0
1
1
1
1
0
0
0
7
8
0.84500
0
1
1
1
1
0
0
1
7
9
0.85000
0
1
1
1
1
0
1
0
7
A
0.85500
0
1
1
1
1
0
1
1
7
B
0.86000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
84
Order Number: 329374-002US
9.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 5 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
0
1
1
1
1
1
0
0
7
C
0.86500
0
1
1
1
1
1
0
1
7
D
0.87000
0
1
1
1
1
1
1
0
7
E
0.87500
0
1
1
1
1
1
1
1
7
F
0.88000
1
0
0
0
0
0
0
0
8
0
0.88500
1
0
0
0
0
0
0
1
8
1
0.89000
1
0
0
0
0
0
1
0
8
2
0.89500
1
0
0
0
0
0
1
1
8
3
0.90000
1
0
0
0
0
1
0
0
8
4
0.90500
1
0
0
0
0
1
0
1
8
5
0.91000
1
0
0
0
0
1
1
0
8
6
0.91500
1
0
0
0
0
1
1
1
8
7
0.92000
1
0
0
0
1
0
0
0
8
8
0.92500
1
0
0
0
1
0
0
1
8
9
0.93000
1
0
0
0
1
0
1
0
8
A
0.93500
1
0
0
0
1
0
1
1
8
B
0.94000
1
0
0
0
1
1
0
0
8
C
0.94500
1
0
0
0
1
1
0
1
8
D
0.95000
1
0
0
0
1
1
1
0
8
E
0.95500
1
0
0
0
1
1
1
1
8
F
0.96000
1
0
0
1
0
0
0
0
9
0
0.96500
1
0
0
1
0
0
0
1
9
1
0.97000
1
0
0
1
0
0
1
0
9
2
0.97500
1
0
0
1
0
0
1
1
9
3
0.98000
1
0
0
1
0
1
0
0
9
4
0.98500
1
0
0
1
0
1
0
1
9
5
0.99000
1
0
0
1
0
1
1
0
9
6
0.99500
1
0
0
1
0
1
1
1
9
7
1.00000
1
0
0
1
1
0
0
0
9
8
1.00500
1
0
0
1
1
0
0
1
9
9
1.01000
1
0
0
1
1
0
1
0
9
A
1.01500
1
0
0
1
1
0
1
1
9
B
1.02000
1
0
0
1
1
1
0
0
9
C
1.02500
1
0
0
1
1
1
0
1
9
D
1.03000
1
0
0
1
1
1
1
0
9
E
1.03500
1
0
0
1
1
1
1
1
9
F
1.04000
1
0
1
0
0
0
0
0
A
0
1.04500
1
0
1
0
0
0
0
1
A
1
1.05000
1
0
1
0
0
0
1
0
A
2
1.05500
1
0
1
0
0
0
1
1
A
3
1.06000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
85
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—9.0
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 6 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
1
0
1
0
0
1
0
0
A
4
1.06500
1
0
1
0
0
1
0
1
A
5
1.07000
1
0
1
0
0
1
1
0
A
6
1.07500
1
0
1
0
0
1
1
1
A
7
1.08000
1
0
1
0
1
0
0
0
A
8
1.08500
1
0
1
0
1
0
0
1
A
9
1.09000
1
0
1
0
1
0
1
0
A
A
1.09500
1
0
1
0
1
0
1
1
A
B
1.10000
1
0
1
0
1
1
0
0
A
C
1.10500
1
0
1
0
1
1
0
1
A
D
1.11000
1
0
1
0
1
1
1
0
A
E
1.11500
1
0
1
0
1
1
1
1
A
F
1.12000
1
0
1
1
0
0
0
0
B
0
1.12500
1
0
1
1
0
0
0
1
B
1
1.13000
1
0
1
1
0
0
1
0
B
2
1.13500
1
0
1
1
0
0
1
1
B
3
1.14000
1
0
1
1
0
1
0
0
B
4
1.14500
1
0
1
1
0
1
0
1
B
5
1.15000
1
0
1
1
0
1
1
0
B
6
1.15500
1
0
1
1
0
1
1
1
B
7
1.16000
1
0
1
1
1
0
0
0
B
8
1.16500
1
0
1
1
1
0
0
1
B
9
1.17000
1
0
1
1
1
0
1
0
B
A
1.17500
1
0
1
1
1
0
1
1
B
B
1.18000
1
0
1
1
1
1
0
0
B
C
1.18500
1
0
1
1
1
1
0
1
B
D
1.19000
1
0
1
1
1
1
1
0
B
E
1.19500
1
0
1
1
1
1
1
1
B
F
1.20000
1
1
0
0
0
0
0
0
C
0
1.20500
1
1
0
0
0
0
0
1
C
1
1.21000
1
1
0
0
0
0
1
0
C
2
1.21500
1
1
0
0
0
0
1
1
C
3
1.22000
1
1
0
0
0
1
0
0
C
4
1.22500
1
1
0
0
0
1
0
1
C
5
1.23000
1
1
0
0
0
1
1
0
C
6
1.23500
1
1
0
0
0
1
1
1
C
7
1.24000
1
1
0
0
1
0
0
0
C
8
1.24500
1
1
0
0
1
0
0
1
C
9
1.25000
1
1
0
0
1
0
1
0
C
A
1.25500
1
1
0
0
1
0
1
1
C
B
1.26000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
86
Order Number: 329374-002US
9.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
Table 9-1.
IMVP7 Voltage Identification Definition (Sheet 7 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
1
1
0
0
1
1
0
0
C
C
1.26500
1
1
0
0
1
1
0
1
C
D
1.27000
1
1
0
0
1
1
1
0
C
E
1.27500
1
1
0
0
1
1
1
1
C
F
1.28000
1
1
0
1
0
0
0
0
D
0
1.28500
1
1
0
1
0
0
0
1
D
1
1.29000
1
1
0
1
0
0
1
0
D
2
1.29500
1
1
0
1
0
0
1
1
D
3
1.30000
1
1
0
1
0
1
0
0
D
4
1.30500
1
1
0
1
0
1
0
1
D
5
1.31000
1
1
0
1
0
1
1
0
D
6
1.31500
1
1
0
1
0
1
1
1
D
7
1.32000
1
1
0
1
1
0
0
0
D
8
1.32500
1
1
0
1
1
0
0
1
D
9
1.33000
1
1
0
1
1
0
1
0
D
A
1.33500
1
1
0
1
1
0
1
1
D
B
1.34000
1
1
0
1
1
1
0
0
D
C
1.34500
1
1
0
1
1
1
0
1
D
D
1.35000
1
1
0
1
1
1
1
0
D
E
1.35500
1
1
0
1
1
1
1
1
D
F
1.36000
1
1
1
0
0
0
0
0
E
0
1.36500
1
1
1
0
0
0
0
1
E
1
1.37000
1
1
1
0
0
0
1
0
E
2
1.37500
1
1
1
0
0
0
1
1
E
3
1.38000
1
1
1
0
0
1
0
0
E
4
1.38500
1
1
1
0
0
1
0
1
E
5
1.39000
1
1
1
0
0
1
1
0
E
6
1.39500
1
1
1
0
0
1
1
1
E
7
1.40000
1
1
1
0
1
0
0
0
E
8
1.40500
1
1
1
0
1
0
0
1
E
9
1.41000
1
1
1
0
1
0
1
0
E
A
1.41500
1
1
1
0
1
0
1
1
E
B
1.42000
1
1
1
0
1
1
0
0
E
C
1.42500
1
1
1
0
1
1
0
1
E
D
1.43000
1
1
1
0
1
1
1
0
E
E
1.43500
1
1
1
0
1
1
1
1
E
F
1.44000
1
1
1
1
0
0
0
0
F
0
1.44500
1
1
1
1
0
0
0
1
F
1
1.45000
1
1
1
1
0
0
1
0
F
2
1.45500
1
1
1
1
0
0
1
1
F
3
1.46000
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
87
Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure—9.0
Table 9-1.
9.5
IMVP7 Voltage Identification Definition (Sheet 8 of 8)
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0
HEX
VCC_MAX
1
1
1
1
0
1
0
0
F
4
1.46500
1
1
1
1
0
1
0
1
F
5
1.47000
1
1
1
1
0
1
1
0
F
6
1.47500
1
1
1
1
0
1
1
1
F
7
1.48000
1
1
1
1
1
0
0
0
F
8
1.48500
1
1
1
1
1
0
0
1
F
9
1.49000
1
1
1
1
1
0
1
0
F
A
1.49500
1
1
1
1
1
0
1
1
F
B
1.50000
1
1
1
1
1
1
0
0
F
C
1.50500
1
1
1
1
1
1
0
1
F
D
1.51000
1
1
1
1
1
1
1
0
F
E
1.51500
1
1
1
1
1
1
1
1
F
F
1.52000
System Agent (SA) Vcc VID
The VccSA is configured by the processor output pin VCCSA_VID and PROC_SELECT#.
VCCSA_VID output may be a logic state “0” or “1”.
Note:
During boot, VCCSA is 0.8 volts.
Table 9-2 specifies the different VCCSA_VID configurations.
Table 9-2.
VCCSA Configuration
VCCSA_VID
PROC_SELECT#
Selected VCCSA
0
0
0.8 V
1
0
0.8 V
Note:
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9.6
Reserved or Unused Signals
The following are the general types of reserved (RSVD) signals and connection
guidelines:
• RSVD_22, RSVD_33 and RSVD_44 - These pins must be shorted together and tied
to VCCP through 24.9 ohm 1% resistor.
• RSVD_[21:1], RSVD_[32:23], RSVD_[43:34] and RSVD_[57:45] - these signals
should not be connected.
Arbitrary connection of these signals to VCC, VCCIO, VDDQ, VCCPLL, VCCSA, VSS, or to any
other signal (including each other) may result in component malfunction or
incompatibility with future processors. See Chapter 8.0, “Signal Description” for a pin
listing of the processor and the location of all reserved signals.
For reliable operation, always connect unused inputs or bi-directional signals to an
appropriate signal level. Unused active high inputs should be connected through a
resistor to ground (VSS). Unused outputs maybe left unconnected; however, this may
interfere with some Test Access Port (TAP) functions, complicate debug probing, and
prevent boundary scan testing. A resistor must be used when tying bi-directional
signals to power or ground. When tying any signal to power or ground, a resistor will
also allow for system testability. Resistor values should be within ±20% of the
impedance of the baseboard trace, unless otherwise noted in the appropriate platform
design guidelines. For details, see Table 8-14, “Processor Internal Pull Up/Pull Down”.
9.7
Signal Groups
Signals are grouped by buffer type and similar characteristics as listed in Table 9-3. The
buffer type indicates which signaling technology and specifications apply to the signals.
All the differential signals, and selected DDR3 and Control Sideband signals have OnDie Termination (ODT) resistors. Some signals do not have ODT and must be
terminated on the board.
Table 9-3.
Signal Groups (Sheet 1 of 3)
Signal Group1
Type
Signals
System Reference Clock
Differential
DDR3 Reference
CMOS Input
BCLK, BCLK#
DDR3 Output
SA_CK[3:0], SA_CK#[3:0]
SB_CK[3:0], SB_CK#[3:0]
DDR3 Output
SA_BS[2:0], SB_BS[2:0]
SA_WE#, SB_WE#
SA_RAS#, SB_RAS#
SA_CAS#, SB_CAS#
SA_MA[15:0], SB_MA[15:0]
DDR3 Output
SA_CS#[3:0], SB_CS#[3:0]
SA_ODT[3:0], SB_ODT[3:0]
SA_CKE[3:0], SB_CKE[3:0]
SM_DRAMRST#
Clocks2
Differential
DDR3 Command Signals2
Single Ended
DDR3 Control Signals2
Single Ended
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Table 9-3.
Signal Groups (Sheet 2 of 3)
Signal Group1
Type
Signals
DDR3 Data Signals2
Single ended
DDR3 Bi-directional
SA_DQ[63:0], SB_DQ[63:0]
SA_ECC_CB[7:0],
SB_ECC_CB[7:0]
Differential
DDR3 Bi-directional
SA_DQS[8:0], SA_DQS#[8:0]
SB_DQS[8:0], SB_DQS#[8:0]
Analog Bi-directional
SM_RCOMP[2:0]
Analog Input
SM_VREF
DDR3 Compensation
DDR3 Reference
TAP (ITP/XDP)
Single Ended
CMOS Input
TCK, TDI, TMS, TRST#
Single Ended
CMOS Open-Drain Output
TDO
Single Ended
Asynchronous CMOS Bi-directional
BPM#[7:0]
Single Ended
Asynchronous CMOS Output
PRDY#
Single Ended
Asynchronous CMOS Input
PREQ#
Control
Sideband3
Single Ended
CMOS Input
Single Ended
Asynchronous CMOS/Open Drain
Bi-directional
CFG[17:0]
PROCHOT#
Single Ended
Asynchronous CMOS Output
THERMTRIP#, CATERR#
Single Ended
Asynchronous CMOS Input
SM_DRAMPWROK,
UNCOREPWRGOOD4, PM_SYNC,
RESET#
Single Ended
Asynchronous Bi-directional
PECI
Single Ended
CMOS Input
VIDALERT#
Single Ended
Open Drain Output
VIDSCLK
Single Ended
CMOS Output
VCCSA_VID
Single Ended
Bi-directional CMOS Input/Open
Drain Output
VIDSOUT
Single Ended
Analog Output
VCCSA_VCCSENCE,
VCCSA_VSSSENCE,
Differential
Analog Output
VCC_SENSE, VSS_SENSE,
VCCIO_SENSE,
VSS_SENSE_VCCIO,
Power
VCC, VCCIO, VCCSA, VCCPLL, VDDQ
Ground
VSS
No Connect /Test Point
RSVD
Other
PROC_DETECT#
Voltage Regulator
Power/Ground/Other
Single Ended
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Table 9-3.
Signal Groups (Sheet 3 of 3)
Signal Group1
Type
Signals
PCI Express*
Differential
PCI Express* Input
PCIE_RX[15:0], PCIE_RX#[15:0]
PE_RX[3:0], PE_RX#[3:0]
Differential
PCI Express* Output
PCIE_TX[15:0], PCIE_TX#[15:0]
PE_TX[3:0], PE_TX#[3:0]
Single Ended
Analog Input
PCIE_ICOMP0, PCIE_ICOMPI,
PCIE_RCOMP0
Differential
DMI Input
DMI_RX[3:0], DMI_RX#[3:0]
Differential
DMI Output
DMI_TX[3:0], DMI_TX#[3:0]
DMI
Notes:
1.
See Chapter 8.0 for signal description details.
2.
SA and SB see DDR3 Channel A and DDR3 Channel B.
3.
All Control Sideband Asynchronous signals are required to be asserted/deasserted for at least 10
BCLKs with a maximum Trise/Tfall of 6 ns for the processor to recognize the proper signal state. See
Chapter 9.10 for the DC specifications.
4.
The maximum rise/fall time of UNCOREPWRGOOD is 20 ns.
9.8
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, Intel recommends the processor be first in the TAP chain, followed by any other
components within the system. A translation buffer should be used to connect to the
rest of the chain unless one of the other components is capable of accepting an input of
the appropriate voltage. Two copies of each signal may be required with each driving a
different voltage level.
The processor supports Boundary Scan (JTAG) IEEE 1149.1-2001 and IEEE 1149.62003 standards. Some small portion of the I/O pins may support only one of these
standards.
Note:
Some of the I/O pins may support only one of these standards.
9.9
Storage Conditions Specifications
Environmental storage condition limits define the temperature and relative humidity to
which the device is exposed to while being stored in a moisture barrier bag. The
specified storage conditions are for component level prior to board attach.
Table 9-4 specifies absolute maximum and minimum storage temperature limits which
represent the maximum or minimum device condition beyond which damage, latent or
otherwise, may occur. The table also specifies sustained storage temperature, relative
humidity, and time-duration limits. These limits specify the maximum or minimum
device storage conditions for a sustained period of time. Failure to adhere to the
following specifications can affect long term reliability of the processor.
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Table 9-4.
Storage Condition Ratings
Symbol
Parameter
Min
Max
Notes
Tabsolute storage
Device storage temperature when exceeded for
any length of time
-25 °C
125 °C
1,2,3,4
Tshort term storage
The ambient storage temperature and time for
up to 72 hours
-25 °C
85 °C
5,6,7
Tsustained storage time
and temp
The ambient storage temperature and time for
up to 30 months
-5 °C
40 °C
RHsustained storage
The maximum device storage relative humidity
for up to 30 months.
60% @ 24 °C
6,7
Notes:
1.
Refers to a component device that is not assembled in a board or socket and is not electrically
connected to a voltage re fence or I/O signal.
2.
Specified temperatures are not to exceed values based on data collected. Exceptions for surface
mount reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor
reliability.
3.
Tabsolute storage applies to the unassembled component only and does not apply to the shipping media,
moisture barrier bags, or desiccant.
4.
Component product device storage temperature qualification methods may follow JESD22-A119 (low
temp) and JESD22-A103 (high temp) standards when applicable for volatile memory.
5.
Intel® branded products are specified and certified to meet the following temperature and humidity
limits that are given as a example only (Non-Operating Temperature Limit: -40 °C to 70 °C and
Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28 °C.) Post board attach
storage temperature limits are not specified for non-Intel branded boards.
6.
The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture
sensitive devices removed from the moisture barrier bag.
7.
Nominal temperature and humidity conditions and durations are given and tested within the
constraints imposed by Tsustaind storage and customer shelf life in applicable Intel boxes and bags.
9.10
DC Specifications
The processor DC specifications in this section are defined at the processor pins, unless
noted otherwise. See Chapter 10.0 for the processor pin listings and Chapter 8.0 for
signal definitions.
The DC specifications for the DDR3 signals are listed in Table 9-10. Control Sideband
and Test Access Port (TAP) are listed in Table 9-11.
Table 9-5 through Table 9-9 list the DC specifications for the processor and are valid
only while meeting specifications for junction temperature, clock frequency, and input
voltages. Read all notes associated with each parameter.
AC tolerances for all DC rails include dynamic load currents at switching frequencies up
to 1 MHz.
9.10.1
Voltage and Current Specifications
Note:
Noise measurements on SENSE pins for all voltage supplies should be made with a 20MHz bandwidth oscilloscope.
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Note:
Noise measurements on SENSE pins for all voltage supplies should be made with a 20MHz bandwidth oscilloscope.
Table 9-5.
Processor Core (VCC) DC Voltage and Current Specifications (Sheet 1 of 2)
Symbol
Parameter
SKU
Min
HFM_VID
VID Range for Highest
Frequency Mode
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
LFM_VID
VID Range for Lowest
Frequency Mode
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
VCC
VCC for processor core
ICCMAX
Maximum Processor Core
ICC
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
ICC_TDC
Thermal Design ICC
ICC_LFM
Max
Unit
Note
0.8
0.8
0.75
0.70
1.35
1.35
1.3
1.2
V
1,2,7,9
0.65
0.65
0.65
0.65
0.95
0.95
0.90
0.90
V
1,2,9
V
2, 3, 4
57
33
30
23
A
1,5,7,9
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
35
22
18
13
A
1,6,7,
9,14
ICC at LFM
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
28
28
15
15
A
6
TDC_LFM
TDC at LFM
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
22
22
12
12
A
1,6
Icc_Dyn_VID1
Dynamic Current step
size in VID1
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
46
26
24
18
A
11, 12
didt
VCC ICC Slew Time
nS
13
mV
8, 10
mV
8,10
0.3-1.52
150
PS0
TOLVCC
Voltage Tolerance
PS1
PS2, PS3
Ripple
Ripple Tolerance
Typ
+/- 15
+/- 12
+/- 11.5
PS0 & Icc >
TDC+30%
+/- 15
PS0 & Icc <=
TDC+30%
+/- 10
PS1
+/- 13
PS2
- 7.5/+18.5
PS3
- 7.5/+27.5
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Table 9-5.
Symbol
VR Step
SLOPELL
Processor Core (VCC) DC Voltage and Current Specifications (Sheet 2 of 2)
Parameter
SKU
VID resolution
Processor Loadline Slope
E3-1125C v2
E3-1105C v2
i3-3115C
B925C
Min
Typ
Max
Unit
5
mV
-1.9
-1.9
-2.9
-2.9
mΩ
Note
Notes:
1.
Unless otherwise noted, all specifications in this table are based on post-silicon estimates and simulations or empirical
data.
2.
Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing
and cannot be altered. Individual maximum SVID values are calibrated during manufacturing such that two processors
at the same frequency may have different settings within the SVID range. This differs from the SVID employed by the
processor during a power or thermal management event (Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep
Technology, or Low Power States).
3.
The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE balls at the socket with a 100-MHz
bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1-MΩ minimum impedance. The maximum length of
ground wire on the probe should be less than 5 mm. Ensure external noise from the system is not coupled into the
oscilloscope probe.
4.
The processor should not be subjected to any VCC and ICC combination wherein VCC exceeds VCC_MAX for a given current.
5.
Processor core VR to be designed to electrically support this current
6.
Processor core VR to be designed to thermally support this current indefinitely.
7.
Measured at VCC_SENSE and VSS_SENSE processor pins.
8.
Long term reliability cannot be assured if tolerance, ripple, and core noise parameters are violated
9.
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
10.
PSx refers to the voltage regulator power state as set by the SVID protocol.
11.
Step is done in 150 ns
12.
Slew time for any transient step size.
13.
Simulated at platform processor pads. This parameter is not tested.
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Table 9-6.
Processor Uncore (VCCIO) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
1.05
-
V
VCCIO
Voltage for the memory controller and
shared cache defined at the motherboard
VCCIO_SENSE and VSS_SENSE_VCCIO
-
TOLCCIO
VCCIO Tolerance defined across VCCIO_SENSE
and VSS_SENSE_VCCIO
DC: ±2% including ripple
AC: ±3%
ICCMAX_VCCIO
Max Current for VCCIO Rail
ICCTDC_VCCIO
Thermal Design Current (TDC) for VCCIO Rail
di/dt
Step current
Slew Rate
Voltage Ramp rate (dV/dT)
-
8.5
-
8.5
2
0.5
10
Note
%
1
A
1
A
1
A
2, 3
mV/uS
1
Notes:
1.
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
2.
Step is done in 100 nS.
3.
di/dt values are for platform testing only. This parameter is not tested on Intel silicon. Testing should go up to and
include IccMax.
Table 9-7.
Memory Controller (VDDQ) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
VDDQ(DC+AC) DDR3
Processor I/O supply voltage for DDR3 (DC
+ AC specification)
-
1.5
-
V
VDDQ(DC + AC)
DDR3L
Processor I/O supply voltage for DDR3L (DC
+ AC specification)
TOLDDQ
VDDQ Tolerance
1.35
ICCMAX_VDDQ
Max Current for VDDQ Rail
Thermal Design Current (TDC) for VDDQ Rail
ICCAVG_VDDQ (Standby)
Average Current for VDDQ Rail during
Standby
Slew Rate
Voltage Ramp rate (dV/dT)
0.5
di/dt
Step current
7.5
Notes:
1.
2.
3.
4.
V
DC= ±3%
AC= ±2%
AC+DC= ±5%
ICCTDC_VDDQ
-
66
Note
%
3
5
A
1,2
5
A
1
133
mA
2
10
mV/uS
A
3,4
The current supplied to the DIMM modules is not included in this specification.
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
Step current between 1 amp through 8.5 amps is done in 150nS
di/dt values are for platform testing only. This parameter is not tested on Intel silicon. Testing should go up to and
include IccMax.
Table 9-8.
Symbol
System Agent (VCCSA) Supply DC Voltage and Current Specifications (Sheet 1
of 2)
Parameter
VCCSA
Voltage for the System Agent and
VCCSA_VCCSENCE
Min
Typ
Max
Unit
Note
-
0.80
-
V
1
TOLCCSA
VCCSA Tolerance
%
1
ICCMAX_VCCSA
Max Current for VCCSA Rail
-
6
A
1
ICCTDC_VCCSA
Thermal Design Current (TDC) for VCCSA
Rail
-
6
A
1
AC + DC = ± 5%
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Table 9-8.
System Agent (VCCSA) Supply DC Voltage and Current Specifications (Sheet 2
of 2)
Symbol
Parameter
Slew Rate
Voltage Ramp rate (dV/dT)
di/dt
Step current
Min
Typ
0.5
Max
Unit
10
mV/uS
1
A
2,3
2
Note
Notes:
1.
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
2.
Step current is done in 100nS
3.
di/dt values are for platform testing only. This parameter is not tested on Intel silicon. Testing should go up to and
include IccMax.
Table 9-9.
Processor PLL (VCCPLL) Supply DC Voltage and Current Specifications
Symbol
Parameter
Min
Typ
Max
Unit
-
1.8
-
V
VCCPLL
PLL supply voltage (DC + AC specification)
TOLCCPLL
VCCPLL Tolerance
ICCMAX_VCCPLL
Max Current for VCCPLL Rail
-
1.2
A
ICCTDC_VCCPLL
Thermal Design Current (TDC) for VCCPLL
Rail
-
1.2
A
Note:
Note
%
AC + DC = ± 5%
3
Long term reliability cannot be assured in conditions above or below Max/Min functional limits.
Table 9-10. DDR3/DDR3L Signal Group DC Specifications (Sheet 1 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes1
VIL
Input Low Voltage
—
—
SM_VREF -0.1
V
2, 4, 11
VIH
Input High Voltage
SM_VREF +
0.1
—
—
V
3, 11
VIL
Input Low Voltage
(SM_DRAMPWROK)
—
—
VDDQ*0.55 -0.1
V
10
VIH
Input High Voltage
(SM_DRAMPWROK)
VDDQ*0.55
+0.1
—
—
V
10
VOL
Output Low Voltage
—
(VDDQ / 2)* (RON /
(RON+RTERM))
—
VOH
Output High Voltage
—
VDDQ - ((VDDQ / 2)*
(RON/(RON+RTERM))
—
V
4, 6
RON_UP(DQ)
DDR3 Data Buffer pull-up
Resistance
20
28.6
40
Ω
5
RON_DN(DQ)
DDR3 Data Buffer pull-down
Resistance
20
28.6
40
Ω
5
RODT(DQ)
DDR3 On-die termination
equivalent resistance for data
signals
40
50
60
Ω
VODT(DC)
DDR3 On-die termination DC
working point (driver set to receive
mode)
0.4*VDDQ
0.5*VDDQ
0.6*VDDQ
V
20
26
40
Ω
RON_UP(CK)
DDR3 Clock Buffer pull-up
Resistance
6
5
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Table 9-10. DDR3/DDR3L Signal Group DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Typ
Max
Units
Notes1
RON_DN(CK)
DDR3 Clock Buffer pull-down
Resistance
20
26
40
Ω
5
RON_UP(CMD)
DDR3 Command Buffer pull-up
Resistance
15
20
25
Ω
5
RON_DN(CMD)
DDR3 Command Buffer pull-down
Resistance
15
20
27
Ω
5
RON_UP(CTL)
DDR3 Control Buffer pull-up
Resistance
15
20
25
Ω
5
RON_DN(CTL)
DDR3 Control Buffer pull-down
Resistance
15
20
27
Ω
5
ILI
Input Leakage Current (DQ, CK)
0V
0.2*VDDQ
0.8*VDDQ
VDDQ
—
—
± 0.75
± 0.55
± 0.9
± 1.4
mA
ILI
Input Leakage Current (CMD, CTL)
0V
0.2*VDDQ
0.8*VDDQ
VDDQ
—
—
±
±
±
±
mA
138.6
140
141.4
Ω
8
0.85
0.65
1.10
1.65
SM_RCOMP0
Command COMP Resistance
SM_RCOMP1
Data COMP Resistance
25.245
25.5
25.755
Ω
8
SM_RCOMP2
ODT COMP Resistance
198
200
202
Ω
8
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. VIL is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
3. VIH is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.
4. VIH and VOH may experience excursions above VDDQ. However, input signal drivers must comply with the signal quality
specifications.
5. This is the pull-up/pull-down driver resistance.
6. RTERM is the termination on the DIMM and in not controlled by the processor.
7. The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.
8. SM_RCOMPx resistance must be provided on the system board with 1% resistors. SM_RCOMPx resistors are to VSS.
9. SM_DRAMPWROK must have a maximum of 15 ns rise or fall time over VDDQ * 0.55± 200 mV and the edge must be
monotonic.
10. SM_VREF is defined as VDDQ/2.
11. Ron tolerance is preliminary and might be subject to change.
Table 9-11.Control Sideband and TAP Signal Group DC Specifications
Symbol
Parameter
VIL
Input Low Voltage
VIH
Input High Voltages
VOL
Output Low Voltage
Min
Max
VCCIO*0.3
VCCIO*0.7
VCCIO*0.1
Units
Notes
V
2
V
2,
V
2
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Symbol
Parameter
Min
VOH
Output High Voltage
VCCIO*0.9
VON
Buffer on Resistance
23
ILI
Input Leakage Currents
Max
Units
Notes
V
2,
73
Ω
±200
μA
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
The VCCIO referred to in these specifications refers to instantaneous VCCIO.
3.
For VIN between “0” V and VCCIO. Measured when the driver is tristated.
4.
VIH and VOH may experience excursions above VCCIO. However, input signal drivers must comply with the signal quality
specifications
.
Table 9-12. PCI Express* DC Specifications
Symbol
Parameter
ZTX-DIFF-DC
DC Differential Tx Impedance (Gen 1 Only)
ZTX-DIFF-DC
DC Differential Tx Impedance (Gen 2 and Gen 3)
ZRX-DC
Min
Typ
80
-
-
Max
Units
Notes1
120
Ω
1,
120
Ω
1,
DC Common Mode Rx Impedance
40
60
Ω
1,,
ZRX-DIFF-DC
DC Differential Rx Impedance (Gen1 Only)
80
120
Ω
1
VRX-DIFFp-p
Differential Rx Input Peak-to-Peak Voltage (Gen 1
only)
0.175
1.2
V
1,
VRX_CM-AC-p
Rx AC Peak Common Mode Input Voltage
150
mV
1,
PCIE_ICOMPO
Comp Resistance
24.75
25
25.25
Ω
,
PCIE_ICOMPI
Comp Resistance
24.75
25
25.25
Ω
,
PCIE_RCOMPO
Comp Resistance
24.75
25
25.25
Ω
,
Notes:
1.
See the PCI Express* Base Specification for details.
2.
VTX-AC-CM-PP and VTX-AC-CM-P are defined in the PCI Express Base Specification. Measurement is made over at least 10^6
UI.
3.
As measured with compliance test load. Defined as 2*|VTXD+ - VTXD- |.
4.
RMS value.
5.
Measured at Rx pins into a pair of 50-Ω terminations into ground. Common mode peak voltage is defined by the
expression: max{|(Vd+ - Vd-) - V-CMDC|}.
6.
DC impedance limits are needed to guarantee Receiver detect.
7.
The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that
the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the 15 Rx Common
Mode Impedance (constrained by RLRX-CM to 50 Ω ±20%) must be within the specified range by the time Detect is
entered.
8.
Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.
9.
This specification is the same as VRX-EYE.
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9.0—Intel® Xeon® and Intel® Core™ Processors for Communications Infrastructure
9.10.2
Platform Environmental Control Interface DC Specifications
Platform Environmental Control Interface (PECI) is an Intel proprietary interface that
provides a communication channel between Intel processors and chipset components
to external Adaptive Thermal Monitor devices. The processor contains a Digital Thermal
Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control
Circuit (TCC) activation temperature. Temperature sensors located throughout the die
are implemented as analog-to-digital converters calibrated at the factory. PECI
provides an interface for external devices to read the DTS temperature for thermal
management and fan speed control.
9.10.2.1
PECI Bus Architecture
The PECI architecture is based on a wired-OR bus, which the processor PECI can pull up
high (with strong drive strength). The idle state on the bus is near zero.
Figure 9-1 demonstrates PECI design and connectivity. The host/originator can be a
third-party PECI host, with one of the PECI clients being the processor PECI device.
Figure 9-1.
Example of PECI Host-Client Connection
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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9.10.2.2
PECI DC Characteristics
The PECI interface operates at a nominal voltage set by VCCIO. The set of DC electrical
specifications shown in Table 9-13 are used with devices normally operating from a
VCCIO interface supply. VCCIO nominal levels will vary between processor families. All
PECI devices will operate at the VCCIO level determined by the processor installed in the
system.
Table 9-13. PECI DC Electrical Limits
Symbol
Definition and Conditions
Rup
Output resistance
Min
Max
Units
Notes1
15
45
Ohm
3
Vin
Input Voltage Range
Vhysteresis
Hysteresis
Vn
Vp
Cbus
Bus Capacitance per Node
N/A
10
pF
Cpad
Pad Capacitance
0.7
1.8
pF
-0.15
VCCIO
V
0.1 * VCCIO
N/A
V
Negative-Edge Threshold Voltage
0.275 * VCCIO
0.500 * VCCIO
V
Positive-Edge Threshold Voltage
0.550 * VCCIO
0.725 * VCCIO
V
Ileak000
leakage current @ 0V
-
0.6
mA
Ileak025
leakage current @ 0.25*VCCIO
-
0.4
mA
Ileak050
leakage current @ 0.50*VCCIO
-
0.2
mA
Ileak075
leakage current @ 0.75*VCCIO
-
0.13
mA
Ileak100
leakage current @ VCCIO
-
0.10
mA
Notes:
1.
VCCIO supplies the PECI interface. PECI behavior does not affect VTT min/max specifications.
2.
The leakage specification applies to powered devices on the PECI bus.
3.
The PECI buffer internal pull up resistance measured at 0.75*VCCIO
9.10.2.3
Input Device Hysteresis
The input buffers in both client and host models must use a Schmitt-triggered input
design for improved noise immunity. Use Figure 9-2 as a guide for input buffer design.
Figure 9-2.
Input Device Hysteresis
VTTD
Maximum VP
PECI High Range
Minimum VP
Minimum
Hysteresis
Valid Input
Signal Range
Maximum VN
Minimum VN
PECI Low Range
PECI Ground
§§
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10.0
Processor Ball and Package Information
10.1
Processor Ball Assignments
• Table 10-1 lists all processor pins ordered alphabetically by ball name.
• Table 10-2 lists all processor pins ordered alphabetically by ball number.
• Figure 10-1, Figure 10-2, Figure 10-3, and Figure 10-4 show the bottom view of
the processor ballmap.
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Processor Ball and Package Information
Table 10-1. Alphabetical Ball Listing
Ball
Signal
Ball
Signal
Ball
Signal
VSS
B9
VSS
C13
VSS
A4
VSS
B10
PCIE2_RX#[2]
C14
VCC
A5
PCIE1_RX[6]
B11
PCIE2_RX[2]
C15
VCC
A6
PCIE1_RX#[6]
B12
VSS
C16
VSS
A7
VSS
B13
VSS
C17
VCC
A8
PCIE1_RX#[1]
B14
VCC
C18
VCC
A9
PCIE1_RX[1]
B15
VCC
C19
VSS
A10
VSS
B16
VSS
C20
VCC
A11
PCIE2_RX#[3]
B17
VCC
C21
VCC
A12
PCIE2_RX[3]
B18
VCC
C22
VSS
A13
VSS
B19
VSS
C23
VCC
A14
VCC
B20
VCC
C24
VCC
A15
VCC
B21
VCC
C25
VSS
A16
VSS
B22
VSS
C26
BPM#[2]
A17
VCC
B23
VCC
C27
BPM#[1]
A18
VCC
B24
VCC
C28
RSVD_42
A19
VSS
B25
VSS
C29
VSS
A20
VCC
B26
BPM#[5]
C30
VSS
A21
VCC
B27
RSVD_22
C31
RSVD_29
A22
VSS
B28
VSS
C32
RSVD_27
A23
VCC
B29
VSS
C33
RSVD_21
A24
VCC
B30
RSVD_12
C34
VSS
A25
VSS
B31
VSS
C35
RSVD_26
A26
BPM#[4]
B32
RSVD_53
C36
RSVD_23
A27
VSS
B33
VSS
D1
VSS
A28
RSVD_14
B34
RSVD_28
D2
PCIE1_RX#[11]
A29
RSVD_31
B35
RSVD_52
D3
PCIE1_RX[11]
A30
RSVD_13
C1
VSS
D4
VSS
A31
RSVD_30
C2
VSS
D5
PCIE1_RX[7]
A32
VSS
C3
PCIE1_RX#[10]
D6
PCIE1_RX#[7]
A33
RSVD_33
C4
PCIE1_RX[10]
D7
VSS
A34
RSVD_54
C5
VSS
D8
PCIE1_RX#[2]
B2
VSS
C6
PCIE1_RX[5]
D9
PCIE1_RX[2]
B3
VSS
C7
PCIE1_RX#[5]
D10
PCIE2_RX#[0]
B4
PCIE1_RX[9]
C8
VSS
D11
PCIE2_RX#[1]
B5
PCIE1_RX#[9]
C9
PCIE1_RX[0]
D12
PCIE2_RX[1]
B6
VSS
C10
PCIE1_RX#[0]
D13
VSS
B7
PCIE1_RX[4]
C11
VSS
D14
VCC
B8
PCIE1_RX#[4]
C12
PCIE_RCOMPO
D15
VCC
A3
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Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
D16
VSS
E21
VCC
F26
BPM#[7]
D17
VCC
E22
VSS
F27
RSVD_43
D18
VCC
E23
VCC
F28
PROC_DETECT#
D19
VSS
E24
VCC
F29
VSS
D20
VCC
E25
VSS
F30
TMS
D21
VCC
E26
BPM#[6]
F31
VSS
D22
VSS
E27
RSVD_41
F32
RSVD_19
D23
VCC
E28
PM_SYNC
F33
RSVD_16
D24
VCC
E29
VIDSCLK
F34
VSS
D25
VSS
E30
TDI
F35
RSVD_36
D26
BPM#[3]
E31
VIDALERT#
F36
RSVD_17
D27
VSS
E32
RSVD_37
G1
PCIE1_RX[15]
D28
BPM#[0]
E33
VSS
G2
PCIE1_RX#[14]
D29
RSVD_44
E34
RSVD_38
G3
PCIE1_RX[14]
D30
TCK
E35
RSVD_18
G4
VSS
D31
VSS
E36
VSS
G5
VSS
D32
VSS
F1
PCIE_ICOMPO
G6
PCIE1_TX[7]
D33
RSVD_39
F2
VSS
G7
VSS
D34
RSVD_20
F3
PCIE1_RX#[13]
G8
PCIE1_TX#[4]
D35
VSS
F4
PCIE1_RX[13]
G9
PCIE1_TX[4]
D36
RSVD_40
F5
VSS
G10
VSS
E1
PCIE1_RX#[12]
F6
VSS
G11
PCIE1_TX#[0]
E2
PCIE1_RX[12]
F7
VSS
G12
PCIE1_TX[0]
E3
VSS
F8
VSS
G13
VSS
E4
PCIE1_RX[8]
F9
VSS
G14
VCC
E5
PCIE1_RX#[8]
F10
VSS
G15
VCC
E6
VSS
F11
VSS
G16
VSS
E7
PCIE1_RX[3]
F12
VSS
G17
VCC
E8
PCIE1_RX#[3]
F13
VSS
G18
VCC
E9
VSS
F14
VCC
G19
VSS
E10
VSS
F15
VCC
G20
VCC
E11
PCIE2_RX[0]
F16
VSS
G21
VCC
E12
VSS
F17
VCC
G22
VSS
E13
VSS
F18
VCC
G23
VCC
E14
VCC
F19
VSS
G24
VCC
E15
VCC
F20
VCC
G25
VSS
E16
VSS
F21
VCC
G26
VIDSOUT
E17
VCC
F22
VSS
G27
VSS
E18
VCC
F23
VCC
G28
VSS
E19
VSS
F24
VCC
G29
PREQ#
E20
VCC
F25
VSS
G30
RSVD_11
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Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
G31
THERMTRIP#
H36
VSS
K5
PCIE1_TX#[9]
G32
VSS
J1
PCIE_ICOMPI
K6
PCIE1_TX[9]
G33
RSVD_34
J2
VSS
K7
VSS
G34
RSVD_32
J3
PCIE1_TX[10]
K8
PCIE1_TX#[3]
G35
VSS
J4
PCIE1_TX#[8]
K9
PCIE1_TX[3]
G36
RSVD_35
J5
PCIE1_TX[8]
K10
VSS
H1
PCIE1_RX#[15]
J6
PCIE1_TX#[6]
K11
PCIE2_TX#[3]
H2
VSS
J7
PCIE1_TX[6]
K12
PCIE2_TX[3]
H3
VSS
J8
VSS
K13
VSS
H4
VSS
J9
PCIE1_TX#[2]
K14
VCC
H5
PCIE1_TX#[7]
J10
PCIE1_TX[2]
K15
VCC
H6
VSS
J11
VSS
K16
VSS
H7
PCIE1_TX#[5]
J12
RSVD_7
K17
VCC
H8
PCIE1_TX[5]
J13
VSS
K18
VCC
H9
VSS
J14
VCC
K19
VSS
H10
PCIE1_TX[1]
J15
VCC
K20
VCC
H11
PCIE1_TX#[1]
J16
VSS
K21
VCC
H12
VSS
J17
VCC
K22
VSS
H13
VSS
J18
VCC
K23
VCC
H14
VCC
J19
VSS
K24
VCC
H15
VCC
J20
VCC
K25
VSS
H16
VSS
J21
VCC
K26
PRDY#
H17
VCC
J22
VSS
K27
VSS
H18
VCC
J23
VCC
K28
RSVD_46
H19
VSS
J24
VCC
K29
VSS
H20
VCC
J25
VSS
K30
CFG[0]
H21
VCC
J26
VCCSA_VID
K31
VSS
H22
VSS
J27
RSVD_48
K32
CFG[7]
H23
VCC
J28
VSS
K33
VSS
H24
VCC
J29
RSVD_47
K34
CFG[10]
H25
VSS
J30
RSVD_57
K35
VSS
H26
TRST#
J31
RSVD_45
K36
RSVD_24
H27
PROC_SELECT#
J32
VSS
L1
PCIE1_TX#[14]
H28
CATERR#
J33
PECI
L2
PCIE1_TX#[13]
H29
UNCOREPWRGOOD
J34
VSS
L3
VSS
H30
VSS
J35
RSVD_25
L4
PCIE1_TX#[11]
H31
RESET#
J36
RSVD_50
L5
PCIE1_TX[11]
H32
PROCHOT#
K1
VSS
L6
VSS
H33
VSS
K2
PCIE1_TX[13]
L7
PCIE2_TX[1]
H34
RSVD_15
K3
PCIE1_TX#[10]
L8
PCIE2_TX#[1]
H35
RSVD_51
K4
VSS
L9
VSS
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Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
L10
PCIE2_TX#[2]
M15
VCC
N20
VCC
L11
PCIE2_TX[2]
M16
VSS
N21
VCC
L12
RSVD_8
M17
VCC
N22
VSS
L13
VSS
M18
VCC
N23
VCC
L14
VCC
M19
VSS
N24
VCC
L15
VCC
M20
VCC
N25
VSS
L16
VSS
M21
VCC
N26
VCC
L17
VCC
M22
VSS
N27
VSS
L18
VCC
M23
VCC
N28
VCCIO
L19
VSS
M24
VCC
N29
VCCIO
L20
VCC
M25
VSS
N30
VSS
L21
VCC
M26
VCC_SENSE
N31
CFG[3]
L22
VSS
M27
VSS_SENSE
N32
CFG[6]
L23
VCC
M28
VSS
N33
CFG[8]
L24
VCC
M29
VSS
N34
CFG[2]
L25
VSS
M30
VSS
N35
CFG[12]
L26
RSVD_55
M31
VSS
N36
CFG[15]
L27
RSVD_56
M32
CFG[17]
P1
DMI_TX[0]
L28
RSVD_49
M33
VSS
P2
VSS
L29
TDO
M34
CFG[11]
P3
VSS
L30
CFG[1]
M35
VSS
P4
VSS
L31
CFG[4]
M36
CFG[14]
P5
VSS
L32
CFG[5]
N1
VSS
P6
BCLK
L33
CFG[16]
N2
RSVD_6
P7
BCLK#
L34
CFG[9]
N3
PCIE1_TX#[15]
P8
VSS
L35
CFG[13]
N4
PCIE1_TX#[12]
P9
VCCSA
L36
VSS
N5
PCIE1_TX[12]
P10
VSS
M1
PCIE1_TX[14]
N6
VSS
P11
VCCSA
M2
VSS
N7
VSS
P12
VCC
M3
PCIE1_TX[15]
N8
VCCIO
P13
VSS
M4
VSS
N9
VCCSA
P14
VCC
M5
VSS
N10
VCCIO
P15
VCC
M6
PCIE2_TX[0]
N11
VSS
P16
VSS
M7
PCIE2_TX#[0]
N12
VCC
P17
VCC
M8
VSS
N13
VSS
P18
VCC
M9
VCCSA_VSSSENSE
N14
VCC
P19
VSS
M10
VCCSA_VCCSENSE
N15
VCC
P20
VCC
M11
VCCIO
N16
VSS
P21
VCC
M12
VCCIO
N17
VCC
P22
VSS
M13
VSS
N18
VCC
P23
VCC
M14
VCC
N19
VSS
P24
VCC
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
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Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
P25
VSS
R30
VSS
T35
SA_DQ[57]
P26
VCC
R31
VSS
T36
SA_DQ[56]
P27
VSS
R32
SA_DQS[7]
U1
DMI_TX[1]
P28
VCCIO
R33
SA_DQ[59]
U2
DMI_TX[2]
P29
VCCIO
R34
SA_DQ[58]
U3
VSS
P30
VSS
R35
SA_DQ[62]
U4
DMI_RX[2]
P31
VSS
R36
SA_DQ[63]
U5
VSS
P32
VSS
T1
DMI_TX#[1]
U6
VSS
P33
VSS
T2
VSS
U7
VCCIO
P34
VSS
T3
DMI_RX#[0]
U8
VCCIO
P35
VSS
T4
DMI_RX#[1]
U9
VCCSA
P36
VSS
T5
VSS
U10
VSS
R1
DMI_TX#[0]
T6
RSVD_10
U11
VSS
R2
VSS
T7
VCCIO
U12
VCC
R3
DMI_RX[0]
T8
VCCSA
U13
VSS
R4
DMI_RX[1]
T9
VSS
U14
VCC
R5
VSS
T10
VCCIO
U15
VCC
R6
RSVD_9
T11
VCCSA
U16
VSS
R7
VCCIO
T12
VCC
U17
VCC
R8
VCCIO
T13
VSS
U18
VCC
R9
VCCSA
T14
VCC
U19
VSS
R10
VSS
T15
VCC
U20
VCC
R11
VCCSA
T16
VSS
U21
VCC
R12
VCC
T17
VCC
U22
VSS
R13
VSS
T18
VCC
U23
VCC
R14
VCC
T19
VSS
U24
VCC
R15
VCC
T20
VCC
U25
VSS
R16
VSS
T21
VCC
U26
VCC
R17
VCC
T22
VSS
U27
VSS
R18
VCC
T23
VCC
U28
VCCIO
R19
VSS
T24
VCC
U29
VCCIO
R20
VCC
T25
VSS
U30
VSS
R21
VCC
T26
VCC
U31
VSS
R22
VSS
T27
VCCIO
U32
VSS
R23
VCC
T28
VSS
U33
VSS
R24
VCC
T29
VCCIO
U34
VSS
R25
VSS
T30
VSS
U35
VSS
R26
VCC
T31
VSS
U36
VSS
R27
VCCIO
T32
SA_DQS#[7]
V1
DMI_TX#[3]
R28
VSS
T33
SA_DQ[60]
V2
DMI_TX#[2]
R29
VCCIO
T34
SA_DQ[61]
V3
VSS
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
106
Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
V4
DMI_RX#[2]
W9
VSS
Y14
VCC
V5
DMI_RX[3]
W10
VCCIO
Y15
VCC
V6
VSS
W11
VCCSA
Y16
VSS
V7
VCCIO
W12
VCC
Y17
VCC
V8
VCCIO
W13
VSS
Y18
VCC
V9
VCCSA
W14
VCC
Y19
VSS
V10
VSS
W15
VCC
Y20
VCC
V11
VCCSA
W16
VSS
Y21
VCC
V12
VCC
W17
VCC
Y22
VSS
V13
VSS
W18
VCC
Y23
VCC
V14
VCC
W19
VSS
Y24
VCC
V15
VCC
W20
VCC
Y25
VSS
V16
VSS
W21
VCC
Y26
VCC
V17
VCC
W22
VSS
Y27
VCCIO
V18
VCC
W23
VCC
Y28
VSS
V19
VSS
W24
VCC
Y29
VCCIO
V20
VCC
W25
VSS
Y30
VCCIO
V21
VCC
W26
VCC
Y31
VSS
V22
VSS
W27
VCCIO
Y32
VSS
V23
VCC
W28
VSS
Y33
VSS
V24
VCC
W29
VCCIO
Y34
VSS
V25
VSS
W30
VCCIO
Y35
VSS
V26
VCC
W31
VSS
Y36
VSS
V27
VSS
W32
SA_DQS#[6]
AA1
VCCIO
V28
VCCIO
W33
SA_DQ[52]
AA2
VCCIO
V29
VCCIO
W34
SA_DQ[53]
AA3
VCCIO
V30
VCCIO
W35
SA_DQ[49]
AA4
VCCIO
V31
VSS
W36
SA_DQ[48]
AA5
VCCIO
V32
SA_DQS[6]
Y1
VCCIO
AA6
VCCIO
V33
SA_DQ[51]
Y2
VCCIO
AA7
VCCIO
V34
SA_DQ[50]
Y3
VCCIO
AA8
VSS
V35
SA_DQ[54]
Y4
VCCIO
AA9
VCCSA
V36
SA_DQ[55]
Y5
VCCIO
AA10
VSS
W1
DMI_TX[3]
Y6
VCCIO
AA11
VSS
W2
VSS
Y7
VCCIO
AA12
VCC
W3
VSS
Y8
VCCIO
AA13
VSS
W4
VSS
Y9
VCCSA
AA14
VCC
W5
DMI_RX#[3]
Y10
VSS
AA15
VCC
W6
VSS
Y11
VCCSA
AA16
VSS
W7
VCCIO
Y12
VCC
AA17
VCC
W8
VCCSA
Y13
VSS
AA18
VCC
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
107
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
AA19
VSS
AB24
VCCIO
AC29
VCCIO
AA20
VCC
AB25
VSS
AC30
VCCIO
AA21
VCC
AB26
VCCIO
AC31
VSS
AA22
VSS
AB27
VCCIO
AC32
VSS
AA23
VCC
AB28
VCCIO
AC33
VSS
AA24
VCC
AB29
VCCIO
AC34
VSS
AA25
VSS
AB30
VCCIO
AC35
VSS
AA26
VCC
AB31
VSS
AC36
VSS
AA27
VSS
AB32
SA_DQS#[5]
AD1
SB_DQ[6]
AA28
VCCIO
AB33
SA_DQ[44]
AD2
SB_DQ[7]
AA29
VCCIO
AB34
SA_DQ[45]
AD3
SB_DQ[2]
AA30
VCCIO
AB35
SA_DQ[41]
AD4
SB_DQ[3]
AA31
VSS
AB36
SA_DQ[40]
AD5
SB_DQS[0]
AA32
SA_DQS[5]
AC1
SB_DQ[1]
AD6
VSS
AA33
SA_DQ[43]
AC2
SB_DQ[5]
AD7
VSS
AA34
SA_DQ[42]
AC3
SB_DQ[0]
AD8
VSS
AA35
SA_DQ[46]
AC4
SB_DQ[4]
AD9
VSS
AA36
SA_DQ[47]
AC5
SB_DQS#[0]
AD10
VCCIO
AB1
VSS
AC6
VSS
AD11
VCCIO
AB2
VSS
AC7
VCCIO
AD12
VSS
AB3
VSS
AC8
VCCIO
AD13
VDDQ
AB4
VSS
AC9
VCCIO
AD14
VDDQ
AB5
VSS
AC10
VCCIO
AD15
VDDQ
AB6
VSS
AC11
VCCIO
AD16
VSS
AB7
VCCIO
AC12
VCCIO
AD17
VDDQ
AB8
VCCIO
AC13
VCCIO
AD18
VDDQ
AB9
VCCSA
AC14
VCCIO
AD19
VSS
AB10
VCCIO
AC15
VCCIO
AD20
VSS
AB11
VSS
AC16
VCCIO
AD21
VDDQ
AB12
VCCIO
AC17
VCCIO
AD22
VSS
AB13
VSS
AC18
VCCIO
AD23
VSS
AB14
VCCIO
AC19
VCCIO
AD24
VSS
AB15
VCCIO
AC20
VCCIO
AD25
VDDQ
AB16
VSS
AC21
VCCIO
AD26
VSS
AB17
VCCIO
AC22
VCCIO
AD27
VSS
AB18
VCCIO
AC23
VCCIO
AD28
VCCIO_SENSE
AB19
VSS
AC24
VCCIO
AD29
VSS_SENSE_VCCIO
AB20
VCCIO
AC25
VCCIO
AD30
VSS
AB21
VCCIO
AC26
VCCIO
AD31
SB_DQ[60]
AB22
VSS
AC27
VCCIO
AD32
SB_DQS[7]
AB23
VCCIO
AC28
VCCIO
AD33
SB_DQ[59]
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
108
Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
AD34
SB_DQ[58]
AF3
SA_DQ[0]
AG8
SB_DQ[9]
AD35
SB_DQ[62]
AF4
SA_DQ[4]
AG9
VSS
AD36
SB_DQ[63]
AF5
SA_DQS#[0]
AG10
SA_DQ[16]
AE1
VSS
AF6
VSS
AG11
SA_DQ[17]
AE2
VSS
AF7
SB_DQ[12]
AG12
VSS
AE3
VSS
AF8
SB_DQ[13]
AG13
SB_ECC_CB[0]
AE4
VSS
AF9
VSS
AG14
SB_ECC_CB[1]
AE5
VSS
AF10
SA_DQ[20]
AG15
VSS
AE6
VSS
AF11
SA_DQ[21]
AG16
SB_CKE[1]
AE7
VSS
AF12
VSS
AG17
VSS
AE8
VSS
AF13
SB_ECC_CB[4]
AG18
SB_MA[11]
AE9
VSS
AF14
SB_ECC_CB[5]
AG19
SB_MA[7]
AE10
VSS
AF15
VSS
AG20
VSS
AE11
VSS
AF16
SB_CKE[2]
AG21
SB_CK[3]
AE12
VSS
AF17
VDDQ
AG22
SB_CK#[3]
AE13
VSS
AF18
RSVD_1
AG23
VSS
AE14
VSS
AF19
SM_DRAMPWROK
AG24
SB_WE#
AE15
VDDQ
AF20
VDDQ
AG25
SB_CS#[0]
AE16
VDDQ
AF21
SA_MA[4]
AG26
VSS
AE17
VDDQ
AF22
SA_MA[2]
AG27
SB_ODT[1]
AE18
VDDQ
AF23
VDDQ
AG28
SB_ODT[3]
AE19
VDDQ
AF24
VDDQ
AG29
VSS
AE20
VDDQ
AF25
VSS
AG30
SA_DQ[38]
AE21
VDDQ
AF26
VDDQ
AG31
SA_DQ[39]
AE22
VDDQ
AF27
VSS
AG32
VSS
AE23
VDDQ
AF28
VSS
AG33
SB_DQS[6]
AE24
VDDQ
AF29
VSS
AG34
SB_DQ[50]
AE25
VDDQ
AF30
SA_DQ[34]
AG35
SB_DQ[55]
AE26
VDDQ
AF31
SA_DQ[35]
AG36
SB_DQ[54]
AE27
VDDQ
AF32
VSS
AH1
VSS
AE28
VDDQ
AF33
VSS
AH2
VSS
AE29
VSS
AF34
VSS
AH3
VSS
AE30
VSS
AF35
VSS
AH4
VSS
AE31
VSS
AF36
SB_DQ[51]
AH5
VSS
AE32
SB_DQS#[7]
AG1
SA_DQ[6]
AH6
VSS
AE33
SB_DQ[61]
AG2
SA_DQ[7]
AH7
SB_DQS#[1]
AE34
SB_DQ[56]
AG3
SA_DQ[2]
AH8
SB_DQS[1]
AE35
SB_DQ[57]
AG4
SA_DQ[3]
AH9
VSS
AE36
VSS
AG5
SA_DQS[0]
AH10
SA_DQS#[2]
AF1
SA_DQ[1]
AG6
VSS
AH11
SA_DQS[2]
AF2
SA_DQ[5]
AG7
SB_DQ[8]
AH12
VSS
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
109
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
AH13
SB_DQS#[8]
AJ18
SB_MA[8]
AK23
VDDQ
AH14
SB_DQS[8]
AJ19
SB_MA[5]
AK24
SA_WE#
AH15
VSS
AJ20
VSS
AK25
SA_CS#[0]
AH16
SB_BS[2]
AJ21
SB_CK[1]
AK26
VDDQ
AH17
VDDQ
AJ22
SB_CK#[2]
AK27
SA_CS#[3]
AH18
SB_MA[6]
AJ23
VSS
AK28
SA_ODT[3]
AH19
SB_MA[4]
AJ24
SB_BS[1]
AK29
VSS
AH20
VDDQ
AJ25
SB_BS[0]
AK30
SA_DQ[32]
AH21
SB_CK[0]
AJ26
VSS
AK31
SA_DQ[36]
AH22
SB_CK#[0]
AJ27
SB_ODT[0]
AK32
VSS
AH23
VDDQ
AJ28
SB_MA[13]
AK33
SB_DQ[43]
AH24
SB_MA[10]
AJ29
VSS
AK34
SB_DQ[42]
AH25
SB_RAS#
AJ30
SA_DQ[33]
AK35
SB_DQ[47]
AH26
VDDQ
AJ31
SA_DQ[37]
AK36
VSS
AH27
SB_CS#[1]
AJ32
VSS
AL1
VSS
AH28
SB_CS#[3]
AJ33
VSS
AL2
VSS
AH29
VSS
AJ34
VSS
AL3
VSS
AH30
SA_DQS#[4]
AJ35
VSS
AL4
VSS
AH31
SA_DQS[4]
AJ36
SB_DQ[52]
AL5
VSS
AH32
VSS
AK1
SA_DQ[14]
AL6
VSS
AH33
SB_DQS#[6]
AK2
SA_DQ[15]
AL7
VSS
AH34
SB_DQ[53]
AK3
SA_DQ[10]
AL8
VSS
AH35
SB_DQ[48]
AK4
SA_DQ[11]
AL9
VSS
AH36
SB_DQ[49]
AK5
SA_DQS[1]
AL10
VSS
AJ1
SA_DQ[9]
AK6
VSS
AL11
VSS
AJ2
SA_DQ[8]
AK7
SB_DQ[11]
AL12
VSS
AJ3
SA_DQ[13]
AK8
SB_DQ[10]
AL13
VSS
AJ4
SA_DQ[12]
AK9
VSS
AL14
VSS
AJ5
SA_DQS#[1]
AK10
SA_DQ[18]
AL15
SB_CKE[0]
AJ6
VSS
AK11
SA_DQ[19]
AL16
SA_DIMM_VREFDQ
AJ7
SB_DQ[15]
AK12
VSS
AL17
VSS
AJ8
SB_DQ[14]
AK13
SB_ECC_CB[2]
AL18
SA_MA[14]
AJ9
VSS
AK14
SB_ECC_CB[3]
AL19
SA_MA[8]
AJ10
SA_DQ[22]
AK15
VSS
AL20
VSS
AJ11
SA_DQ[23]
AK16
SB_DIMM_VREFDQ
AL21
VSS
AJ12
VSS
AK17
VDDQ
AL22
SA_CK#[0]
AJ13
SB_ECC_CB[6]
AK18
SA_CKE[2]
AL23
VSS
AJ14
SB_ECC_CB[7]
AK19
SA_MA[11]
AL24
SA_CK[3]
AJ15
VSS
AK20
VDDQ
AL25
SA_MA[10]
AJ16
SB_MA[15]
AK21
SB_CK#[1]
AL26
VSS
AJ17
VSS
AK22
SB_CK[2]
AL27
SA_ODT[0]
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
110
Processor Ball and Package Information
Ball
Signal
Ball
Signal
Ball
Signal
AL28
SA_ODT[1]
AM33
VSS
AP2
VSS
AL29
VSS
AM34
VSS
AP3
SB_DQ[18]
AL30
VSS
AM35
VSS
AP4
VSS
AL31
VSS
AM36
SB_DQS#[5]
AP5
VSS
AL32
VSS
AN1
VSS
AP6
VSS
AL33
SB_DQ[46]
AN2
SB_DQ[22]
AP7
SB_DQ[29]
AL34
SB_DQ[45]
AN3
SB_DQ[23]
AP8
SB_DQ[26]
AL35
SB_DQ[41]
AN4
SB_DQS[2]
AP9
VSS
AL36
SB_DQS[5]
AN5
SB_DQ[19]
AP10
SA_DQ[29]
AM1
SB_DQ[20]
AN6
VSS
AP11
SA_DQ[26]
AM2
SB_DQ[17]
AN7
SB_DQ[28]
AP12
VSS
AM3
SB_DQ[16]
AN8
SB_DQ[27]
AP13
SA_ECC_CB[5]
AM4
SB_DQS#[2]
AN9
VSS
AP14
SA_ECC_CB[2]
AM5
SB_DQ[21]
AN10
SA_DQ[28]
AP15
VSS
AM6
VSS
AN11
SA_DQ[27]
AP16
SM_VREF
AM7
SB_DQS#[3]
AN12
VSS
AP17
VDDQ
AM8
SB_DQS[3]
AN13
SA_ECC_CB[4]
AP18
SA_CKE[1]
AM9
VSS
AN14
SA_ECC_CB[3]
AP19
SA_MA[15]
AM10
SA_DQS#[3]
AN15
VSS
AP20
VDDQ
AM11
SA_DQS[3]
AN16
SM_DRAMRST#
AP21
SA_MA[6]
AM12
VSS
AN17
VSS
AP22
SA_MA[3]
AM13
SA_DQS#[8]
AN18
SA_MA[12]
AP23
VDDQ
AM14
SA_DQS[8]
AN19
SA_MA[7]
AP24
SA_CK#[2]
AM15
VSS
AN20
VSS
AP25
VSS
AM16
SA_CKE[3]
AN21
SA_CK[1]
AP26
VDDQ
AM17
VDDQ
AN22
SA_CK#[1]
AP27
SA_RAS#
AM18
SA_BS[2]
AN23
VSS
AP28
SA_CS#[2]
AM19
SA_MA[9]
AN24
SA_CK[2]
AP29
VDDQ
AM20
VDDQ
AN25
SA_MA[0]
AP30
VSS
AM21
SA_MA[1]
AN26
VSS
AP31
SB_DQ[32]
AM22
SA_CK[0]
AN27
SA_CAS#
AP32
SB_DQ[34]
AM23
VDDQ
AN28
SA_CS#[1]
AP33
VSS
AM24
SA_CK#[3]
AN29
VSS
AP34
VSS
AM25
SA_BS[1]
AN30
VSS
AP35
VSS
AM26
VDDQ
AN31
SB_DQ[36]
AP36
VSS
AM27
SA_ODT[2]
AN32
SB_DQ[35]
AR2
VSS
AM28
SA_MA[13]
AN33
VSS
AR3
VSS
AM29
VDDQ
AN34
SB_DQ[44]
AR4
VCCPLL
AM30
VSS
AN35
SB_DQ[40]
AR5
VCCPLL
AM31
SB_DQS#[4]
AN36
VSS
AR6
VSS
AM32
SB_DQS[4]
AP1
VSS
AR7
SB_DQ[24]
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
111
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Ball
Signal
Ball
Signal
AR8
SB_DQ[31]
AT16
SB_CKE[3]
AR9
VSS
AT17
VDDQ
AR10
SA_DQ[24]
AT18
SB_MA[14]
AR11
SA_DQ[31]
AT19
SB_MA[12]
AR12
VSS
AT20
VDDQ
AR13
SA_ECC_CB[0]
AT21
SB_MA[3]
AR14
SA_ECC_CB[7]
AT22
SB_MA[2]
AR15
VSS
AT23
VDDQ
AR16
SM_VREF
AT24
SM_RCOMP[1]
AR17
VSS
AT25
VDDQ
AR18
SA_CKE[0]
AT26
VDDQ
AR19
SB_MA[9]
AT27
SB_CS#[2]
AR20
VSS
AT28
SB_CAS#
AR21
SA_MA[5]
AT29
SM_RCOMP[0]
AR22
SB_MA[1]
AT30
SM_RCOMP[2]
AR23
VSS
AT31
SB_DQ[37]
AR24
SB_MA[0]
AT32
SB_DQ[39]
AR25
VSS
AT33
VSS
AR26
VSS
AT34
VSS
AR27
SA_BS[0]
AR28
SB_ODT[2]
AR29
VSS
AR30
RSVD_3
AR31
SB_DQ[33]
AR32
SB_DQ[38]
AR33
RSVD_2
AR34
VSS
AR35
VSS
AT3
VSS
AT4
VCCPLL
AT5
VCCPLL
AT6
VSS
AT7
SB_DQ[25]
AT8
SB_DQ[30]
AT9
VSS
AT10
SA_DQ[25]
AT11
SA_DQ[30]
AT12
VSS
AT13
SA_ECC_CB[1]
AT14
SA_ECC_CB[6]
AT15
VSS
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
112
Processor Ball and Package Information
Table 10-2. Alphabetical Signal Listing
Signal
Ball
Signal
Ball
Signal
Ball
BCLK
P6
DMI_TX#[0]
R1
PCIE1_TX[10]
BCLK#
P7
DMI_TX#[1]
T1
PCIE1_TX[11]
L5
BPM#[0]
D28
DMI_TX#[2]
V2
PCIE1_TX[12]
N5
BPM#[1]
C27
DMI_TX#[3]
V1
PCIE1_TX[13]
K2
BPM#[2]
C26
PCIE_ICOMPI
J1
PCIE1_TX[14]
M1
BPM#[3]
D26
PCIE_ICOMPO
F1
PCIE1_TX[15]
M3
BPM#[4]
A26
PCIE_RCOMPO
C12
PCIE1_TX[2]
J10
BPM#[5]
B26
PCIE1_RX[0]
C9
PCIE1_TX[3]
K9
BPM#[6]
E26
PCIE1_RX[1]
A9
PCIE1_TX[4]
G9
BPM#[7]
F26
PCIE1_RX[10]
C4
PCIE1_TX[5]
H8
CATERR#
H28
PCIE1_RX[11]
D3
PCIE1_TX[6]
J7
CFG[0]
K30
PCIE1_RX[12]
E2
PCIE1_TX[7]
G6
CFG[1]
L30
PCIE1_RX[13]
F4
PCIE1_TX[8]
J5
CFG[10]
K34
PCIE1_RX[14]
G3
PCIE1_TX[9]
K6
CFG[11]
M34
PCIE1_RX[15]
G1
PCIE1_TX#[0]
G11
CFG[12]
N35
PCIE1_RX[2]
D9
PCIE1_TX#[1]
H11
CFG[13]
L35
PCIE1_RX[3]
E7
PCIE1_TX#[10]
K3
CFG[14]
M36
PCIE1_RX[4]
B7
PCIE1_TX#[11]
L4
CFG[15]
N36
PCIE1_RX[5]
C6
PCIE1_TX#[12]
N4
CFG[16]
L33
PCIE1_RX[6]
A5
PCIE1_TX#[13]
L2
CFG[17]
M32
PCIE1_RX[7]
D5
PCIE1_TX#[14]
L1
CFG[2]
N34
PCIE1_RX[8]
E4
PCIE1_TX#[15]
N3
CFG[3]
N31
PCIE1_RX[9]
B4
PCIE1_TX#[2]
J9
CFG[4]
L31
PCIE1_RX#[0]
C10
PCIE1_TX#[3]
K8
CFG[5]
L32
PCIE1_RX#[1]
A8
PCIE1_TX#[4]
G8
CFG[6]
N32
PCIE1_RX#[10]
C3
PCIE1_TX#[5]
H7
CFG[7]
K32
PCIE1_RX#[11]
D2
PCIE1_TX#[6]
J6
CFG[8]
N33
PCIE1_RX#[12]
E1
PCIE1_TX#[7]
H5
CFG[9]
L34
PCIE1_RX#[13]
F3
PCIE1_TX#[8]
J4
DMI_RX[0]
R3
PCIE1_RX#[14]
G2
PCIE1_TX#[9]
K5
DMI_RX[1]
R4
PCIE1_RX#[15]
H1
PCIE2_RX[0]
E11
DMI_RX[2]
U4
PCIE1_RX#[2]
D8
PCIE2_RX[1]
D12
DMI_RX[3]
V5
PCIE1_RX#[3]
E8
PCIE2_RX[2]
B11
DMI_RX#[0]
T3
PCIE1_RX#[4]
B8
PCIE2_RX[3]
A12
DMI_RX#[1]
T4
PCIE1_RX#[5]
C7
PCIE2_RX#[0]
D10
DMI_RX#[2]
V4
PCIE1_RX#[6]
A6
PCIE2_RX#[1]
D11
DMI_RX#[3]
W5
PCIE1_RX#[7]
D6
PCIE2_RX#[2]
B10
DMI_TX[0]
P1
PCIE1_RX#[8]
E5
PCIE2_RX#[3]
A11
DMI_TX[1]
U1
PCIE1_RX#[9]
B5
PCIE2_TX[0]
M6
DMI_TX[2]
U2
PCIE1_TX[0]
G12
PCIE2_TX[1]
L7
W1
PCIE1_TX[1]
H10
PCIE2_TX[2]
L11
DMI_TX[3]
J3
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
113
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
PCIE2_TX[3]
K12
RSVD_35
G36
SA_CKE[2]
AK18
PCIE2_TX#[0]
M7
RSVD_36
F35
SA_CKE[3]
AM16
PCIE2_TX#[1]
L8
RSVD_37
E32
SA_CS#[0]
AK25
PCIE2_TX#[2]
L10
RSVD_38
E34
SA_CS#[1]
AN28
PCIE2_TX#[3]
K11
RSVD_39
D33
SA_CS#[2]
AP28
PECI
J33
RSVD_40
D36
SA_CS#[3]
AK27
PM_SYNC
E28
RSVD_41
E27
SA_DIMM_VREFDQ
AL16
PRDY#
K26
RSVD_42
C28
SA_DQ[0]
AF3
PREQ#
G29
RSVD_43
F27
SA_DQ[1]
AF1
PROC_DETECT#
F28
RSVD_44
D29
SA_DQ[10]
AK3
PROC_SELECT#
H27
RSVD_45
J31
SA_DQ[11]
AK4
PROCHOT#
H32
RSVD_46
K28
SA_DQ[12]
AJ4
RESET#
H31
RSVD_47
J29
SA_DQ[13]
AJ3
RSVD_1
AF18
RSVD_48
J27
SA_DQ[14]
AK1
RSVD_10
T6
RSVD_49
L28
SA_DQ[15]
AK2
RSVD_11
G30
RSVD_50
J36
SA_DQ[16]
AG10
RSVD_12
B30
RSVD_51
H35
SA_DQ[17]
AG11
RSVD_13
A30
RSVD_52
B35
SA_DQ[18]
AK10
RSVD_14
A28
RSVD_53
B32
SA_DQ[19]
AK11
RSVD_15
H34
RSVD_54
A34
SA_DQ[2]
AG3
RSVD_16
F33
RSVD_55
L26
SA_DQ[20]
AF10
RSVD_17
F36
RSVD_56
L27
SA_DQ[21]
AF11
RSVD_18
E35
RSVD_57
J30
SA_DQ[22]
AJ10
RSVD_19
F32
RSVD_6
N2
SA_DQ[23]
AJ11
RSVD_2
AR33
RSVD_7
J12
SA_DQ[24]
AR10
RSVD_20
D34
RSVD_8
L12
SA_DQ[25]
AT10
RSVD_21
C33
RSVD_9
R6
SA_DQ[26]
AP11
RSVD_22
B27
SA_BS[0]
AR27
SA_DQ[27]
AN11
RSVD_23
C36
SA_BS[1]
AM25
SA_DQ[28]
AN10
RSVD_24
K36
SA_BS[2]
AM18
SA_DQ[29]
AP10
RSVD_25
J35
SA_CAS#
AN27
SA_DQ[3]
AG4
RSVD_26
C35
SA_CK[0]
AM22
SA_DQ[30]
AT11
RSVD_27
C32
SA_CK[1]
AN21
SA_DQ[31]
AR11
RSVD_28
B34
SA_CK[2]
AN24
SA_DQ[32]
AK30
RSVD_29
C31
SA_CK[3]
AL24
SA_DQ[33]
AJ30
RSVD_3
AR30
SA_CK#[0]
AL22
SA_DQ[34]
AF30
RSVD_30
A31
SA_CK#[1]
AN22
SA_DQ[35]
AF31
RSVD_31
A29
SA_CK#[2]
AP24
SA_DQ[36]
AK31
RSVD_32
G34
SA_CK#[3]
AM24
SA_DQ[37]
AJ31
RSVD_33
A33
SA_CKE[0]
AR18
SA_DQ[38]
AG30
RSVD_34
G33
SA_CKE[1]
AP18
SA_DQ[39]
AG31
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
114
Processor Ball and Package Information
Signal
Signal
Ball
Ball
Signal
Ball
SA_DQ[4]
AF4
SA_DQS#[2]
AH10
SB_CK[0]
AH21
SA_DQ[40]
AB36
SA_DQS#[3]
AM10
SB_CK[1]
AJ21
SA_DQ[41]
AB35
SA_DQS#[4]
AH30
SB_CK[2]
AK22
SA_DQ[42]
AA34
SA_DQS#[5]
AB32
SB_CK[3]
AG21
SA_DQ[43]
AA33
SA_DQS#[6]
W32
SB_CK#[0]
AH22
SA_DQ[44]
AB33
SA_DQS#[7]
T32
SB_CK#[1]
AK21
SA_DQ[45]
AB34
SA_DQS#[8]
AM13
SB_CK#[2]
AJ22
SA_DQ[46]
AA35
SA_ECC_CB[0]
AR13
SB_CK#[3]
AG22
SA_DQ[47]
AA36
SA_ECC_CB[1]
AT13
SB_CKE[0]
AL15
SA_DQ[48]
W36
SA_ECC_CB[2]
AP14
SB_CKE[1]
AG16
SA_DQ[49]
W35
SA_ECC_CB[3]
AN14
SB_CKE[2]
AF16
SA_DQ[5]
AF2
SA_ECC_CB[4]
AN13
SB_CKE[3]
AT16
SA_DQ[50]
V34
SA_ECC_CB[5]
AP13
SB_CS#[0]
AG25
SA_DQ[51]
V33
SA_ECC_CB[6]
AT14
SB_CS#[1]
AH27
SA_DQ[52]
W33
SA_ECC_CB[7]
AR14
SB_CS#[2]
AT27
SA_DQ[53]
W34
SA_MA[0]
AN25
SB_CS#[3]
AH28
SA_DQ[54]
V35
SA_MA[1]
AM21
SB_DIMM_VREFDQ
AK16
SA_DQ[55]
V36
SA_MA[10]
AL25
SB_DQ[0]
AC3
SA_DQ[56]
T36
SA_MA[11]
AK19
SB_DQ[1]
AC1
SA_DQ[57]
T35
SA_MA[12]
AN18
SB_DQ[10]
AK8
SA_DQ[58]
R34
SA_MA[13]
AM28
SB_DQ[11]
AK7
SA_DQ[59]
R33
SA_MA[14]
AL18
SB_DQ[12]
AF7
SA_DQ[6]
AG1
SA_MA[15]
AP19
SB_DQ[13]
AF8
SA_DQ[60]
T33
SA_MA[2]
AF22
SB_DQ[14]
AJ8
SA_DQ[61]
T34
SA_MA[3]
AP22
SB_DQ[15]
AJ7
SA_DQ[62]
R35
SA_MA[4]
AF21
SB_DQ[16]
AM3
SA_DQ[63]
R36
SA_MA[5]
AR21
SB_DQ[17]
AM2
SA_DQ[7]
AG2
SA_MA[6]
AP21
SB_DQ[18]
AP3
SA_DQ[8]
AJ2
SA_MA[7]
AN19
SB_DQ[19]
AN5
SA_DQ[9]
AJ1
SA_MA[8]
AL19
SB_DQ[2]
AD3
SA_DQS[0]
AG5
SA_MA[9]
AM19
SB_DQ[20]
AM1
SA_DQS[1]
AK5
SA_ODT[0]
AL27
SB_DQ[21]
AM5
SA_DQS[2]
AH11
SA_ODT[1]
AL28
SB_DQ[22]
AN2
SA_DQS[3]
AM11
SA_ODT[2]
AM27
SB_DQ[23]
AN3
SA_DQS[4]
AH31
SA_ODT[3]
AK28
SB_DQ[24]
AR7
SA_DQS[5]
AA32
SA_RAS#
AP27
SB_DQ[25]
AT7
SA_DQS[6]
V32
SA_WE#
AK24
SB_DQ[26]
AP8
SA_DQS[7]
R32
SB_BS[0]
AJ25
SB_DQ[27]
AN8
SA_DQS[8]
AM14
SB_BS[1]
AJ24
SB_DQ[28]
AN7
SA_DQS#[0]
AF5
SB_BS[2]
AH16
SB_DQ[29]
AP7
SA_DQS#[1]
AJ5
SB_CAS#
AT28
SB_DQ[3]
AD4
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
115
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
SB_DQ[30]
AT8
SB_DQS[1]
AH8
SB_ODT[0]
AJ27
SB_DQ[31]
AR8
SB_DQS[2]
AN4
SB_ODT[1]
AG27
SB_DQ[32]
AP31
SB_DQS[3]
AM8
SB_ODT[2]
AR28
SB_DQ[33]
AR31
SB_DQS[4]
AM32
SB_ODT[3]
AG28
SB_DQ[34]
AP32
SB_DQS[5]
AL36
SB_RAS#
AH25
SB_DQ[35]
AN32
SB_DQS[6]
AG33
SB_WE#
AG24
SB_DQ[36]
AN31
SB_DQS[7]
AD32
SM_DRAMPWROK
AF19
SB_DQ[37]
AT31
SB_DQS[8]
AH14
SM_DRAMRST#
AN16
SB_DQ[38]
AR32
SB_DQS#[0]
AC5
SM_RCOMP[0]
AT29
SB_DQ[39]
AT32
SB_DQS#[1]
AH7
SM_RCOMP[1]
AT24
SB_DQ[4]
AC4
SB_DQS#[2]
AM4
SM_RCOMP[2]
AT30
SB_DQ[40]
AN35
SB_DQS#[3]
AM7
SM_VREF
AP16
SB_DQ[41]
AL35
SB_DQS#[4]
AM31
SM_VREF
AR16
SB_DQ[42]
AK34
SB_DQS#[5]
AM36
TCK
D30
SB_DQ[43]
AK33
SB_DQS#[6]
AH33
TDI
E30
SB_DQ[44]
AN34
SB_DQS#[7]
AE32
TDO
L29
SB_DQ[45]
AL34
SB_DQS#[8]
AH13
THERMTRIP#
G31
SB_DQ[46]
AL33
SB_ECC_CB[0]
AG13
TMS
F30
SB_DQ[47]
AK35
SB_ECC_CB[1]
AG14
TRST#
H26
SB_DQ[48]
AH35
SB_ECC_CB[2]
AK13
UNCOREPWRGOOD
H29
SB_DQ[49]
AH36
SB_ECC_CB[3]
AK14
VCC
A14
SB_DQ[5]
AC2
SB_ECC_CB[4]
AF13
VCC
A15
SB_DQ[50]
AG34
SB_ECC_CB[5]
AF14
VCC
A17
SB_DQ[51]
AF36
SB_ECC_CB[6]
AJ13
VCC
A18
SB_DQ[52]
AJ36
SB_ECC_CB[7]
AJ14
VCC
A20
SB_DQ[53]
AH34
SB_MA[0]
AR24
VCC
A21
SB_DQ[54]
AG36
SB_MA[1]
AR22
VCC
A23
SB_DQ[55]
AG35
SB_MA[10]
AH24
VCC
A24
SB_DQ[56]
AE34
SB_MA[11]
AG18
VCC
B14
SB_DQ[57]
AE35
SB_MA[12]
AT19
VCC
B15
SB_DQ[58]
AD34
SB_MA[13]
AJ28
VCC
B17
SB_DQ[59]
AD33
SB_MA[14]
AT18
VCC
B18
SB_DQ[6]
AD1
SB_MA[15]
AJ16
VCC
B20
SB_DQ[60]
AD31
SB_MA[2]
AT22
VCC
B21
SB_DQ[61]
AE33
SB_MA[3]
AT21
VCC
B23
SB_DQ[62]
AD35
SB_MA[4]
AH19
VCC
B24
SB_DQ[63]
AD36
SB_MA[5]
AJ19
VCC
C14
SB_DQ[7]
AD2
SB_MA[6]
AH18
VCC
C15
SB_DQ[8]
AG7
SB_MA[7]
AG19
VCC
C17
SB_DQ[9]
AG8
SB_MA[8]
AJ18
VCC
C18
SB_DQS[0]
AD5
SB_MA[9]
AR19
VCC
C20
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
116
Processor Ball and Package Information
Signal
Signal
Ball
Ball
Signal
Ball
VCC
C21
VCC
H23
VCC
N23
VCC
C23
VCC
H24
VCC
N24
VCC
C24
VCC
J14
VCC
N26
VCC
D14
VCC
J15
VCC
P12
VCC
D15
VCC
J17
VCC
P14
VCC
D17
VCC
J18
VCC
P15
VCC
D18
VCC
J20
VCC
P17
VCC
D20
VCC
J21
VCC
P18
VCC
D21
VCC
J23
VCC
P20
VCC
D23
VCC
J24
VCC
P21
VCC
D24
VCC
K14
VCC
P23
VCC
E14
VCC
K15
VCC
P24
VCC
E15
VCC
K17
VCC
P26
VCC
E17
VCC
K18
VCC
R12
VCC
E18
VCC
K20
VCC
R14
VCC
E20
VCC
K21
VCC
R15
VCC
E21
VCC
K23
VCC
R17
VCC
E23
VCC
K24
VCC
R18
VCC
E24
VCC
L14
VCC
R20
VCC
F14
VCC
L15
VCC
R21
VCC
F15
VCC
L17
VCC
R23
VCC
F17
VCC
L18
VCC
R24
VCC
F18
VCC
L20
VCC
R26
VCC
F20
VCC
L21
VCC
T12
VCC
F21
VCC
L23
VCC
T14
VCC
F23
VCC
L24
VCC
T15
VCC
F24
VCC
M14
VCC
T17
VCC
G14
VCC
M15
VCC
T18
VCC
G15
VCC
M17
VCC
T20
VCC
G17
VCC
M18
VCC
T21
VCC
G18
VCC
M20
VCC
T23
VCC
G20
VCC
M21
VCC
T24
VCC
G21
VCC
M23
VCC
T26
VCC
G23
VCC
M24
VCC
U12
VCC
G24
VCC
N12
VCC
U14
VCC
H14
VCC
N14
VCC
U15
VCC
H15
VCC
N15
VCC
U17
VCC
H17
VCC
N17
VCC
U18
VCC
H18
VCC
N18
VCC
U20
VCC
H20
VCC
N20
VCC
U21
VCC
H21
VCC
N21
VCC
U23
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
117
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
VCC
U24
VCC
AA26
VCCIO
Y29
VCC
U26
VCC_SENSE
M26
VCCIO
Y30
VCC
V12
VCCIO
M11
VCCIO
AA1
VCC
V14
VCCIO
M12
VCCIO
AA2
VCC
V15
VCCIO
N8
VCCIO
AA3
VCC
V17
VCCIO
N10
VCCIO
AA4
VCC
V18
VCCIO
N28
VCCIO
AA5
VCC
V20
VCCIO
N29
VCCIO
AA6
VCC
V21
VCCIO
P28
VCCIO
AA7
VCC
V23
VCCIO
P29
VCCIO
AA28
VCC
V24
VCCIO
R7
VCCIO
AA29
VCC
V26
VCCIO
R8
VCCIO
AA30
VCC
W12
VCCIO
R27
VCCIO
AB7
VCC
W14
VCCIO
R29
VCCIO
AB8
VCC
W15
VCCIO
T7
VCCIO
AB10
VCC
W17
VCCIO
T10
VCCIO
AB12
VCC
W18
VCCIO
T27
VCCIO
AB14
VCC
W20
VCCIO
T29
VCCIO
AB15
VCC
W21
VCCIO
U7
VCCIO
AB17
VCC
W23
VCCIO
U8
VCCIO
AB18
VCC
W24
VCCIO
U28
VCCIO
AB20
VCC
W26
VCCIO
U29
VCCIO
AB21
VCC
Y12
VCCIO
V7
VCCIO
AB23
VCC
Y14
VCCIO
V8
VCCIO
AB24
VCC
Y15
VCCIO
V28
VCCIO
AB26
VCC
Y17
VCCIO
V29
VCCIO
AB27
VCC
Y18
VCCIO
V30
VCCIO
AB28
VCC
Y20
VCCIO
W7
VCCIO
AB29
VCC
Y21
VCCIO
W10
VCCIO
AB30
VCC
Y23
VCCIO
W27
VCCIO
AC7
VCC
Y24
VCCIO
W29
VCCIO
AC8
VCC
Y26
VCCIO
W30
VCCIO
AC9
VCC
AA12
VCCIO
Y1
VCCIO
AC10
VCC
AA14
VCCIO
Y2
VCCIO
AC11
VCC
AA15
VCCIO
Y3
VCCIO
AC12
VCC
AA17
VCCIO
Y4
VCCIO
AC13
VCC
AA18
VCCIO
Y5
VCCIO
AC14
VCC
AA20
VCCIO
Y6
VCCIO
AC15
VCC
AA21
VCCIO
Y7
VCCIO
AC16
VCC
AA23
VCCIO
Y8
VCCIO
AC17
VCC
AA24
VCCIO
Y27
VCCIO
AC18
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
118
Processor Ball and Package Information
Signal
Signal
Ball
Ball
Signal
Ball
VCCIO
AC19
VDDQ
AD17
VDDQ
AT17
VCCIO
AC20
VDDQ
AD18
VDDQ
AT20
VCCIO
AC21
VDDQ
AD21
VDDQ
AT23
VCCIO
AC22
VDDQ
AD25
VDDQ
AT25
VCCIO
AC23
VDDQ
AE15
VDDQ
AT26
VCCIO
AC24
VDDQ
AE16
VIDALERT#
E31
VCCIO
AC25
VDDQ
AE17
VIDSCLK
E29
VCCIO
AC26
VDDQ
AE18
VIDSOUT
G26
VCCIO
AC27
VDDQ
AE19
VSS
A3
VCCIO
AC28
VDDQ
AE20
VSS
A4
VCCIO
AC29
VDDQ
AE21
VSS
A7
VCCIO
AC30
VDDQ
AE22
VSS
A10
VCCIO
AD10
VDDQ
AE23
VSS
A13
VCCIO
AD11
VDDQ
AE24
VSS
A16
VCCIO_SENSE
AD28
VDDQ
AE25
VSS
A19
VCCPLL
AR4
VDDQ
AE26
VSS
A22
VCCPLL
AR5
VDDQ
AE27
VSS
A25
VCCPLL
AT4
VDDQ
AE28
VSS
A27
VCCPLL
AT5
VDDQ
AF17
VSS
A32
VCCSA
N9
VDDQ
AF20
VSS
B2
VCCSA
P9
VDDQ
AF23
VSS
B3
VCCSA
P11
VDDQ
AF24
VSS
B6
VCCSA
R9
VDDQ
AF26
VSS
B9
VCCSA
R11
VDDQ
AH17
VSS
B12
VCCSA
T8
VDDQ
AH20
VSS
B13
VCCSA
T11
VDDQ
AH23
VSS
B16
VCCSA
U9
VDDQ
AH26
VSS
B19
VCCSA
V9
VDDQ
AK17
VSS
B22
VCCSA
V11
VDDQ
AK20
VSS
B25
VCCSA
W8
VDDQ
AK23
VSS
B28
VCCSA
W11
VDDQ
AK26
VSS
B29
VCCSA
Y9
VDDQ
AM17
VSS
B31
VCCSA
Y11
VDDQ
AM20
VSS
B33
VCCSA
AA9
VDDQ
AM23
VSS
C1
VCCSA
AB9
VDDQ
AM26
VSS
C2
VCCSA_VCCSENSE
M10
VDDQ
AM29
VSS
C5
VCCSA_VID
J26
VDDQ
AP17
VSS
C8
VCCSA_VSSSENSE
M9
VDDQ
AP20
VSS
C11
VDDQ
AD13
VDDQ
AP23
VSS
C13
VDDQ
AD14
VDDQ
AP26
VSS
C16
VDDQ
AD15
VDDQ
AP29
VSS
C19
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
119
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
VSS
C22
VSS
F22
VSS
J32
VSS
C25
VSS
F25
VSS
J34
VSS
C29
VSS
F29
VSS
K1
VSS
C30
VSS
F31
VSS
K4
VSS
C34
VSS
F34
VSS
K7
VSS
D1
VSS
G4
VSS
K10
VSS
D4
VSS
G5
VSS
K13
VSS
D7
VSS
G7
VSS
K16
VSS
D13
VSS
G10
VSS
K19
VSS
D16
VSS
G13
VSS
K22
VSS
D19
VSS
G16
VSS
K25
VSS
D22
VSS
G19
VSS
K27
VSS
D25
VSS
G22
VSS
K29
VSS
D27
VSS
G25
VSS
K31
VSS
D31
VSS
G27
VSS
K33
VSS
D32
VSS
G28
VSS
K35
VSS
D35
VSS
G32
VSS
L3
VSS
E3
VSS
G35
VSS
L6
VSS
E6
VSS
H2
VSS
L9
VSS
E9
VSS
H3
VSS
L13
VSS
E10
VSS
H4
VSS
L16
VSS
E12
VSS
H6
VSS
L19
VSS
E13
VSS
H9
VSS
L22
VSS
E16
VSS
H12
VSS
L25
VSS
E19
VSS
H13
VSS
L36
VSS
E22
VSS
H16
VSS
M2
VSS
E25
VSS
H19
VSS
M4
VSS
E33
VSS
H22
VSS
M5
VSS
E36
VSS
H25
VSS
M8
VSS
F2
VSS
H30
VSS
M13
VSS
F5
VSS
H33
VSS
M16
VSS
F6
VSS
H36
VSS
M19
VSS
F7
VSS
J2
VSS
M22
VSS
F8
VSS
J8
VSS
M25
VSS
F9
VSS
J11
VSS
M28
VSS
F10
VSS
J13
VSS
M29
VSS
F11
VSS
J16
VSS
M30
VSS
F12
VSS
J19
VSS
M31
VSS
F13
VSS
J22
VSS
M33
VSS
F16
VSS
J25
VSS
M35
VSS
F19
VSS
J28
VSS
N1
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
120
Processor Ball and Package Information
Signal
Signal
Ball
Ball
Signal
Ball
VSS
N6
VSS
T5
VSS
W6
VSS
N7
VSS
T9
VSS
W9
VSS
N11
VSS
T13
VSS
W13
VSS
N13
VSS
T16
VSS
W16
VSS
N16
VSS
T19
VSS
W19
VSS
N19
VSS
T22
VSS
W22
VSS
N22
VSS
T25
VSS
W25
VSS
N25
VSS
T28
VSS
W28
VSS
N27
VSS
T30
VSS
W31
VSS
N30
VSS
T31
VSS
Y10
VSS
P2
VSS
U3
VSS
Y13
VSS
P3
VSS
U5
VSS
Y16
VSS
P4
VSS
U6
VSS
Y19
VSS
P5
VSS
U10
VSS
Y22
VSS
P8
VSS
U11
VSS
Y25
VSS
P10
VSS
U13
VSS
Y28
VSS
P13
VSS
U16
VSS
Y31
VSS
P16
VSS
U19
VSS
Y32
VSS
P19
VSS
U22
VSS
Y33
VSS
P22
VSS
U25
VSS
Y34
VSS
P25
VSS
U27
VSS
Y35
VSS
P27
VSS
U30
VSS
Y36
VSS
P30
VSS
U31
VSS
AA8
VSS
P31
VSS
U32
VSS
AA10
VSS
P32
VSS
U33
VSS
AA11
VSS
P33
VSS
U34
VSS
AA13
VSS
P34
VSS
U35
VSS
AA16
VSS
P35
VSS
U36
VSS
AA19
VSS
P36
VSS
V3
VSS
AA22
VSS
R2
VSS
V6
VSS
AA25
VSS
R5
VSS
V10
VSS
AA27
VSS
R10
VSS
V13
VSS
AA31
VSS
R13
VSS
V16
VSS
AB1
VSS
R16
VSS
V19
VSS
AB2
VSS
R19
VSS
V22
VSS
AB3
VSS
R22
VSS
V25
VSS
AB4
VSS
R25
VSS
V27
VSS
AB5
VSS
R28
VSS
V31
VSS
AB6
VSS
R30
VSS
W2
VSS
AB11
VSS
R31
VSS
W3
VSS
AB13
VSS
T2
VSS
W4
VSS
AB16
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
121
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Signal
Ball
Signal
Ball
Signal
Ball
VSS
AB19
VSS
AE31
VSS
AJ23
VSS
AB22
VSS
AE36
VSS
AJ26
VSS
AB25
VSS
AF6
VSS
AJ29
VSS
AB31
VSS
AF9
VSS
AJ32
VSS
AC6
VSS
AF12
VSS
AJ33
VSS
AC31
VSS
AF15
VSS
AJ34
VSS
AC32
VSS
AF25
VSS
AJ35
VSS
AC33
VSS
AF27
VSS
AK6
VSS
AC34
VSS
AF28
VSS
AK9
VSS
AC35
VSS
AF29
VSS
AK12
VSS
AC36
VSS
AF32
VSS
AK15
VSS
AD6
VSS
AF33
VSS
AK29
VSS
AD7
VSS
AF34
VSS
AK32
VSS
AD8
VSS
AF35
VSS
AK36
VSS
AD9
VSS
AG6
VSS
AL1
VSS
AD12
VSS
AG9
VSS
AL2
VSS
AD16
VSS
AG12
VSS
AL3
VSS
AD19
VSS
AG15
VSS
AL4
VSS
AD20
VSS
AG17
VSS
AL5
VSS
AD22
VSS
AG20
VSS
AL6
VSS
AD23
VSS
AG23
VSS
AL7
VSS
AD24
VSS
AG26
VSS
AL8
VSS
AD26
VSS
AG29
VSS
AL9
VSS
AD27
VSS
AG32
VSS
AL10
VSS
AD30
VSS
AH1
VSS
AL11
VSS
AE1
VSS
AH2
VSS
AL12
VSS
AE2
VSS
AH3
VSS
AL13
VSS
AE3
VSS
AH4
VSS
AL14
VSS
AE4
VSS
AH5
VSS
AL17
VSS
AE5
VSS
AH6
VSS
AL20
VSS
AE6
VSS
AH9
VSS
AL21
VSS
AE7
VSS
AH12
VSS
AL23
VSS
AE8
VSS
AH15
VSS
AL26
VSS
AE9
VSS
AH29
VSS
AL29
VSS
AE10
VSS
AH32
VSS
AL30
VSS
AE11
VSS
AJ6
VSS
AL31
VSS
AE12
VSS
AJ9
VSS
AL32
VSS
AE13
VSS
AJ12
VSS
AM6
VSS
AE14
VSS
AJ15
VSS
AM9
VSS
AE29
VSS
AJ17
VSS
AM12
VSS
AE30
VSS
AJ20
VSS
AM15
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
122
Processor Ball and Package Information
Signal
Ball
Signal
Ball
VSS
AM30
VSS
AR26
VSS
AM33
VSS
AR29
VSS
AM34
VSS
AR34
VSS
AM35
VSS
AR35
VSS
AN1
VSS
AT3
VSS
AN6
VSS
AT6
VSS
AN9
VSS
AT9
VSS
AN12
VSS
AT12
VSS
AN15
VSS
AT15
VSS
AN17
VSS
AT33
VSS
AN20
VSS
AT34
VSS
AN23
VSS_SENSE
M27
VSS
AN26
VSS_SENSE_VCCIO
AD29
VSS
AN29
VSS
AN30
VSS
AN33
VSS
AN36
VSS
AP1
VSS
AP2
VSS
AP4
VSS
AP5
VSS
AP6
VSS
AP9
VSS
AP12
VSS
AP15
VSS
AP25
VSS
AP30
VSS
AP33
VSS
AP34
VSS
AP35
VSS
AP36
VSS
AR2
VSS
AR3
VSS
AR6
VSS
AR9
VSS
AR12
VSS
AR15
VSS
AR17
VSS
AR20
VSS
AR23
VSS
AR25
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
Datasheet
November 2013
123
Intel Confidential
Order Number: 329374-002US
Processor Ball and Package Information
Figure 10-1. Ball Map (Bottom View, Upper Left Side)
A
B
1
2
VSS
3
VSS
4
VSS
VSS
C
VSS
VSS
VSS
PCIE1_
RX#[11
]
PCIE1_
PCIE1_
RX#[10
RX[11]
]
PCIE1_ PCIE1_
RX[9] RX[10]
5
PCIE1_ PCIE1_
RX[6] RX#[9]
6
PCIE1_
RX#[6]
7
VSS
VSS
VSS
PCIE1_ PCIE1_
RX#[1] RX#[4]
9
PCIE1_
RX[1]
10
VSS
VSS
VSS
E
F
G
VSS
VSS
VSS
14
VCC
VCC
15
VCC
16
V
VSS
BCLK
VCCIO VCCIO VCCIO VCCIO
VCCIO
VSS
VCCIO VCCSA VCCIO VCCIO
VSS
PCIE1_ PCIE1_
TX#[4] TX[5]
VSS
13
U
PCIE2_ PCIE2_
TX[1] TX#[0]
PCIE1_ PCIE1_
RX#[2] RX#[3]
PCIE2_ PCIE2_
RX#[1] RX[0]
VSS
PCIE1_ PCIE1_
TX#[5] TX[6]
VSS
VSS
VSS
PCIE1_ PCIE1_
TX#[2] TX[3]
PCIE1_ PCIE1_
TX[1] TX[2]
VSS
PCIE1_ PCIE2_
TX#[3] TX#[1]
VSS
VSS
PCIE1_ PCIE1_
TX#[0] TX#[1]
VSS
VSS
PCIE1_
TX[0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
17
VCC
VCC
VCC
VCC
VCC
VCC
18
VCC
VCC
VCC
VCC
VCC
VCC
PCIE_R PCIE2_
COMPO RX[1]
T
BCLK#
VSS
VSS
VSS
R
VSS
VSS
VSS
PCIE2_
RX[3]
P
PCIE2_
TX[0]
PCIE1_
RX[3]
PCIE2_ PCIE1_ PCIE2_
RX#[2] RX#[0] RX#[0]
12
N
PCIE1_ PCIE1_
TX#[6] TX[9]
PCIE1_
TX[7]
PCIE1_
TX[4]
VSS
M
VSS
VSS
VSS
PCIE2_ PCIE2_
RX#[3] RX[2]
L
PCIE1_
TX[12]
VSS
VSS
11
K
VSS
VSS
VSS
J
PCIE1_ PCIE1_ PCIE1_ PCIE1_
TX#[7] TX[8] TX#[9] TX[11]
VSS
PCIE1_ PCIE1_
RX[0] RX[2]
VSS
H
PCIE1_
PCIE1_
PCIE1_
PCIE_I PCIE1_
PCIE_I
PCIE1_
DMI_T DMI_T DMI_T DMI_T DMI_T
RX#[12
RX#[15
VSS TX#[14
VSS
COMPO RX[15]
COMPI
TX[14]
X[0]
X#[0] X#[1]
X[1]
X#[3]
]
]
]
PCIE1_
PCIE1_
PCIE1_
RSVD_
DMI_T DMI_T
PCIE1_
VSS
TX#[13 VSS
VSS
VSS
VSS
VSS RX#[14 VSS
TX[13]
6
X[2]
X#[2]
RX[12]
]
]
PCIE1_
PCIE1_
PCIE1_
PCIE1_
DMI_R DMI_R
PCIE1_
PCIE1_
TX#[10 VSS
TX#[15 VSS
VSS
VSS
VSS RX#[13
VSS
TX[15]
X[0]
X#[0]
RX[14]
TX[10]
]
]
]
PCIE1_
PCIE1_
PCIE1_ PCIE1_
PCIE1_
DMI_R DMI_R DMI_R DMI_R
VSS
VSS
VSS TX#[11 VSS TX#[12 VSS
RX[8] RX[13]
TX#[8]
X[1]
X#[1]
X[2]
X#[2]
]
]
PCIE1_ PCIE1_
RX[7] RX#[8]
PCIE1_ PCIE1_
RX[5] RX#[7]
PCIE1_ PCIE1_
RX[4] RX#[5]
8
D
VSS
VSS
RSVD_ RSVD_
9
10
VSS
DMI_R
X[3]
VSS
VSS
VCCSA
_VSSS VCCSA VCCSA VCCSA
VSS
VCCSA VCCSA
ENSE
VCCSA
PCIE2_
_VCCS VCCIO
VSS
VSS
VCCIO
VSS
VSS
TX#[2]
ENSE
VSS
PCIE2_ PCIE2_
TX#[3] TX[2]
VCC
VSS
RSVD_ PCIE2_ RSVD_
7
TX[3]
8
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VCCSA VCCSA VCCSA
VSS
VCCSA
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
Intel® Xeon® E3-1125C v2, E3-1105C v2, Intel® Pentium® Processor B925C, and Intel® Core™ i3-3115C Processors for
Communications Infrastructure
November 2013
Datasheet
Order Number: 329374-002US
Intel Confidential
124
Processor Ball and Package Information
Figure 10-2. Ball Map (Bottom View, Upper Right Side)
W
Y
DMI_TX
VCCIO
[3]
AA
AB
AC
AD
AE
AF
AG
AH
VCCIO
VSS
SB_DQ[ SB_DQ[
1]
6]
VSS
SA_DQ[ SA_DQ[
1]
6]
VSS
AJ
AK
AL
AM
AN
AP
SA_DQ[ SA_DQ[
9]
14]
VSS
SB_DQ[
20]
VSS
VSS
AR
AT
1
VSS
VCCIO
VCCIO
VSS
SB_DQ[ SB_DQ[
5]
7]
VSS
SA_DQ[ SA_DQ[
5]
7]
VSS
SA_DQ[ SA_DQ[
8]
15]
VSS
SB_DQ[ SB_DQ[
17]
22]
VSS
VCCIO
VCCIO
VSS
SB_DQ[ SB_DQ[
0]
2]
VSS
SA_DQ[ SA_DQ[
0]
2]
VSS
SA_DQ[ SA_DQ[
13]
10]
VSS
SB_DQ[ SB_DQ[ SB_DQ[
16]
23]
18]
VSS
VCCIO
VCCIO
VSS
SB_DQ[ SB_DQ[
4]
3]
VSS
SA_DQ[ SA_DQ[
4]
3]
VSS
SA_DQ[ SA_DQ[
12]
11]
VSS
SB_DQ SB_DQ
S#[2]
S[2]
VSS
VCCPLL VCCPLL
4
DMI_RX
VCCIO
#[3]
VCCIO
VSS
SB_DQ SB_DQ
S#[0]
S[0]
VSS
SA_DQ SA_DQ
S#[0]
S[0]
VSS
SA_DQ SA_DQ
S#[1]
S[1]
VSS
SB_DQ[ SB_DQ[
21]
19]
VSS
VCCPLL VCCPLL
5
VSS
VSS
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VSS
VSS
SB_DQ[ SB_DQ[ SB_DQ SB_DQ[ SB_DQ[
12]
8]
S#[1]
15]
11]
VSS
SB_DQ SB_DQ[ SB_DQ[ SB_DQ[ SB_DQ[
S#[3]
28]
29]
24]
25]
7
VCCSA
VCCIO
VSS
VCCIO
VCCIO
VSS
VSS
SB_DQ[ SB_DQ[ SB_DQ SB_DQ[ SB_DQ[
13]
9]
S[1]
14]
10]
VSS
SB_DQ SB_DQ[ SB_DQ[ SB_DQ[ SB_DQ[
S[3]
27]
26]
31]
30]
8
VCCSA VCCSA VCCSA
VCCIO
VSS
VSS
VCCIO
VSS
VCCSA VCCSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
6
VSS
VSS
VSS
3
VSS
VSS
VSS
VSS
VCCIO
VSS
VSS
VSS
VCCIO
VSS
VSS
2
VSS
VSS
VSS
VSS
VSS
VSS
9
VSS
VCCIO
VCCIO
VCCIO
VSS
SA_DQ[ SA_DQ[ SA_DQ SA_DQ[ SA_DQ[
20]
16]
S#[2]
22]
18]
VSS
SA_DQ SA_DQ[ SA_DQ[ SA_DQ[ SA_DQ[
S#[3]
28]
29]
24]
25]
10
VSS
VSS
VCCIO
VCCIO
VSS
SA_DQ[ SA_DQ[ SA_DQ SA_DQ[ SA_DQ[
21]
17]
S[2]
23]
19]
VSS
SA_DQ SA_DQ[ SA_DQ[ SA_DQ[ SA_DQ[
S[3]
27]
26]
31]
30]
11
VSS
VCC
VCC
VCCIO
VCCIO
VSS
VSS
VSS
VSS
VSS
VSS
VCCIO
VCCIO
VSS
SB_ECC SB_ECC SB_DQ SB_ECC SB_ECC
_CB[4] _CB[0] S#[8] _CB[6] _CB[2]
VSS
SA_DQ SA_ECC SA_ECC SA_ECC SA_ECC
S#[8] _CB[4] _CB[5] _CB[0] _CB[1]
13
VCC
VCC
VCC
VCCIO
VCCIO
VCCIO
VSS
SB_ECC SB_ECC SB_DQ SB_ECC SB_ECC
_CB[5] _CB[1]
S[8] _CB[7] _CB[3]
VSS
SA_DQ SA_ECC SA_ECC SA_ECC SA_ECC
S[8]
_CB[3] _CB[2] _CB[7] _CB[6]
14
VCC
VCC
VCC
VCCIO
VCCIO
VDDQ
VDDQ
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SB_CKE
[0]
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
12
VCC
VSS
SM_DR
SB_DIM SA_DIM
SA_CKE
SM_VR SM_VR SB_CKE
SB_CKE SB_CKE SB_BS[ SB_MA[
AMRST
M_VREF M_VREF
[3]
EF
EF
[3]
[2]
[1]
2]
15]
DQ
#
DQ
VSS
VSS
VSS
VSS
VCCIO
VSS
VDDQ
VCC
VCC
VCC
VCCIO
VCCIO
VDDQ
VDDQ
VCC
VCC
VCC
VCCIO
VCCIO
VDDQ
VDDQ RSVD_1
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
VSS
VDDQ
SB_MA[ SB_MA[ SB_MA[ SA_CKE SA_MA[ SA_BS[ SA_MA[ SA_CKE SA_CKE SB_MA[
11]
6]
8]
[2]
14]
2]
12]
[1]
[0]
14]
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15
16
17
18
Processor Ball and Package Information
Figure 10-3. Ball Map (Bottom View, Lower Left Side)
19
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
20
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
21
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
22
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
23
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
24
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCSA_ PRDY# RSVD_5 VCC_SE
BPM#[4 BPM#[5 BPM#[2 BPM#[3 BPM#[6 BPM#[7 VIDSOU
PRDY
TRST#
5
NSE
VID
]
]
]
]
]
]
T
VCC
VCC
VCC
VCC
VCC
VCC
RSVD_5 VSS_SE
6
NSE
VSS
VSS
VCCIO
VCCIO
VSS
VSS
VSS
VCCIO
VCCIO
VSS
VSS
VCCIO
VCCIO
VSS
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VSS
VSS
VSS
VSS
VSS
VSS
VCCIO
VSS
CFG[3]
VSS
VSS
VSS
VSS
VSS
CFG[17
CFG[6]
]
VSS
SA_DQ SA_DQ
S[7]
S#[7]
VSS
SA_DQ
S[6]
CFG[8]
VSS
SA_DQ[ SA_DQ[
59]
60]
VSS
SA_DQ[
51]
CFG[10
CFG[11
CFG[9]
CFG[2]
]
]
VSS
SA_DQ[ SA_DQ[
58]
61]
VSS
SA_DQ[
50]
CFG[12
]
VSS
SA_DQ[ SA_DQ[
62]
57]
VSS
SA_DQ[
54]
CFG[14 CFG[15
]
]
VSS
SA_DQ[ SA_DQ[
63]
56]
VSS
SA_DQ[
55]
U
V
26
RSVD_4 RSVD_4
1
3
VSS
PROC_S RSVD_4
ELECT#
8
RSVD_4 BPM#[0 PM_SY PROC_D
2
]
NC
ETECT#
VSS
CATERR
#
RSVD_2 BPM#[1
2
]
27
VSS
28
RSVD_1
4
VSS
29
RSVD_3
1
VSS
30
RSVD_1 RSVD_1
3
2
31
RSVD_3
0
32
VSS
33
RSVD_3
3
34
RSVD_5 RSVD_2
4
8
VSS
RSVD_4 VIDSCL
4
K
VSS
UNCORE
RSVD_4
PREQ#
PREQ PWRGO
7
OD
TCK
TDI
TMS
RSVD_1
1
RSVD_2
9
VSS
VIDALE
RT#
VSS
THERM
RSVD_4
RESET#
TRIP#
5
RSVD_5 RSVD_2
3
7
VSS
RSVD_3 RSVD_1
7
9
VSS
VSS
RSVD_2 RSVD_3
1
9
VSS
B
C
VSS
RSVD_2 RSVD_3
0
8
VSS
RSVD_2 RSVD_4
3
0
36
A
VSS
VSS
RSVD_5 RSVD_2
2
6
35
VSS
D
RSVD_1 RSVD_3
6
4
VSS
RSVD_1 RSVD_3
8
6
VSS
E
VSS
VSS
VSS
VSS
PECI
G
VSS
RSVD_5 RSVD_2
1
5
VSS
H
RSVD_4 RSVD_4
6
9
VSS
TDO
RSVD_5
CFG[0] CFG[1]
7
PROCH
OT#
RSVD_3 RSVD_1
2
5
RSVD_1 RSVD_3
7
5
F
VSS
VSS
VSS
CFG[7] CFG[5]
VSS
VSS
RSVD_5 RSVD_2
0
4
J
CFG[4]
K
CFG[16
]
CFG[13
]
VSS
L
VSS
VSS
M
N
P
R
T
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Figure 10-4. Ball Map (Bottom View, Lower Right Side)
VCCIO
VSS
SM_DR
SB_MA SB_MA SB_MA SA_MA SA_MA SA_MA SA_MA SA_MA SB_MA SB_MA
VDDQ AMPWR
[7]
[4]
[5]
[11]
[8]
[9]
[7]
[15]
[9]
[12]
OK
19
VCC
VCCIO VCCIO
VSS
VDDQ
VDDQ
VDDQ
VSS
VDDQ
VDDQ
20
VCC
VCC
VCCIO VCCIO
VDDQ
VDDQ
SA_MA SB_CK[ SB_CK[ SB_CK[ SB_CK
[4]
3]
0]
1]
#[1]
VSS
SA_MA SA_CK[ SA_MA SA_MA SB_MA
[1]
1]
[6]
[5]
[3]
21
VSS
VSS
VSS
VCCIO
VSS
VDDQ
SA_MA SB_CK SB_CK SB_CK SB_CK[ SA_CK SA_CK[ SA_CK SA_MA SB_MA SB_MA
[2]
#[3]
#[0]
#[2]
2]
#[0]
0]
#[1]
[3]
[1]
[2]
22
VCC
VCC
VCC
VCCIO VCCIO
VSS
VDDQ
VDDQ
23
VCC
VCC
VCC
VCCIO VCCIO
VSS
VDDQ
VDDQ
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VCC
VCC
VCC
VCCIO VCCIO
VSS
VDDQ
VDDQ
VSS
VCCIO VCCIO
VSS
VDDQ
VCCIO_
VDDQ
SENSE
VSS
VSS
VSS
VCC
VCC
VCC
VCCIO VCCIO
VSS
VSS
VSS
VSS
VSS
VCCIO
VCCIO VCCIO VCCIO
VSS_S
VCCIO VCCIO VCCIO VCCIO VCCIO ENSE_
VCCIO
VSS
VCCIO VCCIO VCCIO VCCIO VCCIO
VSS
VSS
VSS
SB_DQ
[60]
VSS
VSS
VSS
VDDQ
VDDQ
VSS
VSS
VDDQ
VSS
VDDQ
VSS
VSS
VDDQ
VDDQ
VSS
VSS
VDDQ
SB_WE SB_MA SB_BS[ SA_WE SA_CK[ SA_CK SA_CK[ SA_CK SB_MA SM_RC
#
[10]
1]
#
3]
#[3]
2]
#[2]
[0]
OMP[1]
24
SB_CS SB_RA SB_BS[ SA_CS SA_MA SA_BS[ SA_MA
#[0]
S#
0]
#[0]
[10]
1]
[0]
VSS
VSS
VDDQ
25
VDDQ
VSS
VDDQ
26
VSS
SB_OD SB_CS SB_OD SA_CS SA_OD SA_OD SA_CA SA_RA SA_BS[ SB_CS
T[1]
#[1]
T[0]
#[3]
T[0]
T[2]
S#
S#
0]
#[2]
27
VSS
SB_OD SB_CS SB_MA SA_OD SA_OD SA_MA SA_CS SA_CS SB_OD SB_CA
T[3]
#[3]
[13]
T[3]
T[1]
[13]
#[1]
#[2]
T[2]
S#
28
SM_RC
OMP[0]
29
RSVD_ SM_RC
3
OMP[2]
30
VSS
VSS
VSS
VDDQ
VSS
VSS
VSS
VDDQ
VSS
VSS
VDDQ
VSS
VSS
VDDQ
VSS
VDDQ
VSS
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
[34]
[38]
S#[4]
[33]
[32]
VSS
VSS
VSS
VSS
SA_DQ SA_DQ SA_DQ SA_DQ SA_DQ
[35]
[39]
S[4]
[37]
[36]
VSS
SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ
S#[4]
[36]
[32]
[33]
[37]
31
VSS
SB_DQ SB_DQ SB_DQ SB_DQ SB_DQ
S[4]
[35]
[34]
[38]
[39]
32
VSS
VSS
SA_DQ
S#[6]
VSS
SA_DQ SA_DQ
S[5]
S#[5]
VSS
SB_DQ SB_DQ
S[7]
S#[7]
VSS
SA_DQ
[52]
VSS
SA_DQ SA_DQ
[43]
[44]
VSS
SB_DQ SB_DQ
[59]
[61]
VSS
SB_DQ SB_DQ
S[6]
S#[6]
VSS
SB_DQ SB_DQ
[43]
[46]
VSS
VSS
VSS
RSVD_
2
VSS
33
SA_DQ
[53]
VSS
SA_DQ SA_DQ
[42]
[45]
VSS
SB_DQ SB_DQ
[58]
[56]
VSS
SB_DQ SB_DQ
[50]
[53]
VSS
SB_DQ SB_DQ
[42]
[45]
VSS
SB_DQ
[44]
VSS
VSS
VSS
34
SA_DQ
[49]
VSS
SA_DQ SA_DQ
[46]
[41]
VSS
SB_DQ SB_DQ
[62]
[57]
VSS
SB_DQ SB_DQ
[55]
[48]
VSS
SB_DQ SB_DQ
[47]
[41]
VSS
SB_DQ
[40]
VSS
VSS
SA_DQ
[48]
VSS
SA_DQ SA_DQ
[47]
[40]
VSS
SB_DQ
[63]
VSS
VSS
VSS
W
Y
AC
AD
AE
AN
AP
AA
VSS
VSS
AB
VSS
VSS
VSS
SB_DQ SB_DQ SB_DQ SB_DQ
[51]
[54]
[49]
[52]
AF
AG
AH
AJ
VSS
VSS
AK
SB_DQ SB_DQ
S[5]
S#[5]
AL
AM
35
36
AR
AT
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10.2
Package Mechanical Information
The following section contains the mechanical drawings for the processor. The
processor utilizes a 37.5 x 37.5 mm, FC-BGA package.
Figure 10-5 shows the die size and other mechanical details related to this processor.
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Figure 10-5. Processor Mechanical Package
§§
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11.0
Processor Configuration Registers
This section contains register information that is specific to the this processor. For other
register details see the Mobile 3rd Generation Intel® Core™ Processor Family, Intel®
Pentium® Processor Family, and Intel® Celeron® Processor Family Datasheet, Volume
2 of 2
Note:
The processor does not include the Integrated Display Engine or the Graphics Processor
Unit (GPU). Disregard references to graphics and Intel® Turbo Boost in the Mobile 3rd
Generation Intel® Core™ Processor Family, Intel® Pentium® Processor Family, and
Intel® Celeron® Processor Family Datasheet
Table 11-1 lists the register-related terminology and access attributes that are used in
this chapter. Table 11-2 provides the attribute modifiers.
Table 11-1. Register Terminology
Item
Description
RO
Read Only: These bits can only be read by software, writes have no effect. The value of
the bits is determined by the hardware only.
RW
Read/Write: These bits can be read and written by software.
RW1C
Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a '1' to a
bit will clear it, while writing a '0' to a bit has no effect. Hardware sets these bits.
RW0C
Read/Write 0 to Clear: These bits can be read and cleared by software. Writing a ‘0’ to a
bit will clear it, while writing a ‘1’ to a bit has no effect. Hardware sets these bits.
RW1S
Read / Write 1 to Set: These bits can be read and set by software. Writing a ‘1’ to a bit will
set it, while writing a ‘0’ to a bit has no effect. Hardware clears these bits.
RsvdP
Reserved and Preserved: These bits are reserved for future RW implementations and their
value must not be modified by software. When writing to these bits, software must
preserve the value read. When SW updates a register that has RsvdP fields, it must read
the register value first so that the appropriate merge between the RsvdP and updated
fields will occur.
RsvdZ
Reserved and Zero: These bits are reserved for future RW1C implementations. SW must
use 0 for writes.
WO
Write Only: These bits can only be written by software, reads return zero.
NOTE: Use of this attribute type is deprecated and can only be used to describe bits
without persistent state.
RC
Read Clear: These bits can only be read by software, but a read causes the bits to be
cleared. Hardware sets these bits.
NOTE: Use of this attribute type is only allowed on legacy functions, as side-effects on
reads are not desirable
RSW1C
Read Set / Write 1 to Clear: These bits can be read and cleared by software. Reading a bit will
set the bit to ‘1’. Writing a ‘1’ to a bit will clear it, while writing a ‘0’ to a bit has no effect.
RCW
Read Clear / Write: These bits can be read and written by software, but a read causes the
bits to be cleared.
NOTE: Use of this attribute type is only allowed on legacy functions, as side-effects on
reads are not desirable.
Table 11-2 lists the modifiers used in conjunction with attributes that are included in
the register tables throughout this chapter.
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Table 11-2. Register Terminology Attribute Modifiers
Attribute
Modifier
Applicable
Attribute
RO (w/ -V)
S
RW
Description
Sticky: These bits are only re-initialized to their Reset Value by a
"Power Good Reset".
Note: Does not apply to RO (constant) bits.
RW1C
RW1S
-K
RW
RW
-L
WO
RW
-O
11.1
WO
Key: These bits control the ability to write other bits (identified
with a 'Lock' modifier)
Lock: Hardware can make these bits "Read Only" using a separate
configuration bit or other logic.
Mutually exclusive with 'Once' modifier.
Once: After reset, these bits can only be written by software once,
after which they become "Read Only".
Mutually exclusive with 'Lock' modifier and does not make sense
with 'Variant' modifier.
-FW
RO
Firmware Write: The value of these bits can be updated by
firmware (PCU, TAP, and so on).
-V
RO
Variant: The value of these bits can be updated by hardware.
Note: RW1C and RC bits are variant by definition and therefore
do not need to be modified.
ERRSTS - Error Status
This register is used to report various error conditions via the SERR DMI messaging
mechanism. The SERR DMI message is generated on a zero to one transition of any of
these flags (if enabled by the ERRCMD and PCICMD registers).
These bits are set regardless of whether or not the SERR is enabled and generated.
After the error processing is complete, the error logging mechanism can be unlocked by
clearing the appropriate status bit by software writing a '1' to it.
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Table 11-3. Error Status Register
15:2
1
0
11.2
RO
RW1CS
RW1CS
0h
Reserved (RSVD)
0b
Powergood
Multiple-bit DRAM ECC Error Flag (DMERR)
If this bit is set to 1, a memory read data transfer had an
uncorrectable multiple-bit error. When this bit is set, the column,
row, bank, and rank that caused the error, and the error
syndrome, are logged in the ECC Error Log register in the
channel where the error occurred. Once this bit is set, the
ECCERRLOGx fields are locked until the processor clears this bit
by writing a 1. Software uses bits [1:0] to detect whether the
logged error address is for a Single-bit or a Multiple-bit error.
This bit is reset on PWROK.
Powergood
Single-bit DRAM ECC Error Flag (DSERR)
If this bit is set to 1, a memory read data transfer had a singlebit correctable error and the corrected data was returned to the
requesting agent. When this bit is set the column, row, bank, and
rank where the error occurred and the syndrome of the error are
logged in the ECC Error Log register in the channel where the
error occurred. Once this bit is set the ECCERRLOGx fields are
locked to further single-bit error updates until the processor
clears this bit by writing a 1. A multiple bit error that occurs after
this bit is set will overwrite the ECCERRLOGx fields with the
multiple-bit error signature and the DMERR bit will also be set. A
single bit error that occurs after a multibit error will set this bit
but will not overwrite the other fields.
This bit is reset on PWROK.
0b
ERRCMD - Error Command
This register controls the Host Bridge responses to various system errors. Since the
Host Bridge does not have an SERR# signal, SERR messages are passed from the
Processor to the PCH over DMI.
When a bit in this register is set, a SERR message will be generated on DMI whenever
the corresponding flag is set in the ERRSTS register. The actual generation of the SERR
message is globally enabled for Device 0 via the PCI Command register.
Table 11-4. Error Command Registers
15:2
1
0
11.3
RO
RW
RW
0h
Reserved (RSVD)
0b
Uncore
SERR Multiple-Bit DRAM ECC Error (DMERR)
1 = The Host Bridge generates an SERR message over DMI when
it detects a multiple-bit error reported by the DRAM
controller.
0 = Reporting of this condition using SERR messaging is
disabled.
For systems not supporting ECC, this bit must be disabled.
Uncore
SERR on Single-bit ECC Error (DSERR)
1 = The Host Bridge generates an SERR special cycle over DMI
when the DRAM controller detects a single bit error.
0 = Reporting of this condition using SERR messaging is
disabled.
For systems that do not support ECC, this bit must be disabled.
0b
SMICMD - SMI Command
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively.
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Note:
Only one message type can be enabled.
Table 11-5. SMI Command Registers
15:2
1
0
11.4
RO
RW
RW
0h
Reserved (RSVD)
0b
Uncore
SMI on Multiple-Bit DRAM ECC Error (DMESMI)
1 = The Host generates an SMI DMI message when it detects a
multiple-bit error reported by the DRAM controller.
0 = Reporting of this condition using SMI messaging is disabled.
For systems not supporting ECC, this bit must be disabled.
Uncore
SMI on Single-bit ECC Error (DSESMI)
1 = The Host generates an SMI DMI special cycle when the
DRAM controller detects a single bit error.
0 = Reporting of this condition using SMI messaging is disabled.
For systems that do not support ECC, this bit must be disabled.
0b
SCICMD - SCI Command
This register enables various errors to generate an SMI DMI special cycle. When an
error flag is set in the ERRSTS register, it can generate an SERR, SMI, or SCI DMI
special cycle when enabled in the ERRCMD, SMICMD, or SCICMD registers,
respectively.
Note:
Only one message type can be enabled.
Table 11-6. SCI Command Registers
15:2
1
0
11.5
RO
RW
RW
0h
Reserved (RSVD)
0b
Uncore
SCI on Multiple-Bit DRAM ECC Error (DMESCI)
1 = The Host generates an SCI DMI message when it detects a
multiple-bit error reported by the DRAM controller.
0 = Reporting of this condition using SCI messaging is disabled.
For systems not supporting ECC, this bit must be disabled.
Uncore
SCI on Single-bit ECC Error (DSESCI)
1 = The Host generates an SCI DMI special cycle when the
DRAM controller detects a single bit error.
0 = Reporting of this condition using SCI messaging is disabled.
For systems that do not support ECC, this bit must be disabled.
0b
ECCERRLOG0_C0 - ECC Error Log 0
This Channel 0 register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank and bank address
information of the address block of main memory of which an error (single bit or multibit error) has occurred. The address fields represent the address of the first single or
the first multiple bit error occurrence after the error flag bits in the ERRSTS register
have been cleared by software. A multiple bit error will overwrite a single bit error.
Once the error flag bits are set as a result of an error, this bit field is locked and doesn't
change as a result of a new error until the error flag is cleared by software. Same is the
case with error syndrome field.
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Table 11-7. Channel 0 ECC Error Log 0
31:29
ROS-V
000b
Powergood
Error Bank (ERRBANK)
This field holds the Bank Address of the read transaction that
had the ECC error.
28:27
ROS-V
00b
Powergood
Error Rank (ERRRANK)
This field holds the Rank ID of the read transaction that had the
ECC error.
26:24
ROS-V
000b
Powergood
Error Chunk (ERRCHUNK)
Holds the chunk number of the error stored in the register.
23:16
ROS-V
00h
15:2
RO
0h
Reserved (RSVD)
0b
Powergood
Uncorrectable Error Status (MERRSTS)
This bit is set when an uncorrectable multiple-bit error occurs
on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also
logged and they are locked until this bit is cleared.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
Powergood
Correctable Error Status (CERRSTS)
This bit is set when a correctable single-bit error occurs on a
memory read data transfer. When this bit is set, the address
that caused the error and the error syndrome are also logged
and they are locked to further single bit errors, until this bit is
cleared.
A multiple bit error that occurs after this bit is set will override
the address/error syndrome information.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
1
0
ROS-V
ROS-V
0b
Powergood
Error Syndrome (ERRSYND)
This field contains the error syndrome. A value of FFh indicates
that the error is due to poisoning.
Note: For ERRSYND definition see Table 11-13, “Error
Syndrome - ERRSYND”
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11.6
ECCERRLOG1_C0 - ECC Error Log 1
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the row and column address
information of the address block of main memory of which an error (single bit or multibit error) has occurred.
Table 11-8. Channel 0 ECC Error Log 1
11.7
31:16
ROS-V
0000h
Powergood
Error Column (ERRCOL)
This field holds the DRAM column address of the read
transaction that had the ECC error.
15:0
ROS-V
0000h
Powergood
Error Row (ERRROW)
This field holds the DRAM row (page) address of the read
transaction that had the ECC error.
ECCERRLOG0_C1 - ECC Error Log 0
This Channel 1 register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the rank and bank address
information of the address block of main memory of which an error (single bit or multibit error) has occurred. The address fields represent the address of the first single or
the first multiple bit error occurrence after the error flag bits in the ERRSTS register
have been cleared by software. A multiple bit error will overwrite a single bit error.
Once the error flag bits are set as a result of an error, this bit field is locked and doesn't
change as a result of a new error until the error flag is cleared by software. Same is the
case with error syndrome field.
Table 11-9. Channel 1 ECC Error Log 0
31:29
ROS-V
000b
Powergood
Error Bank (ERRBANK)
This field holds the Bank Address of the read transaction that
had the ECC error.
28:27
ROS-V
00b
Powergood
Error Rank (ERRRANK)
This field holds the Rank ID of the read transaction that had
the ECC error.
26:24
ROS-V
000b
Powergood
Error Chunk (ERRCHUNK)
Holds the chunk number of the error stored in the register.
Powergood
Error Syndrome (ERRSYND)
This field contains the error syndrome. A value of FFh indicates
that the error is due to poisoning.
For ERRSYND definition see Table 11-13, “Error Syndrome ERRSYND”
23:16
ROS-V
00h
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15:2
1
0
11.8
RO
ROS-V
ROS-V
0h
Reserved (RSVD)
0b
Powergood
Uncorrectable Error Status (MERRSTS)
This bit is set when an uncorrectable multiple-bit error occurs
on a memory read data transfer. When this bit is set, the
address that caused the error and the error syndrome are also
logged and they are locked until this bit is cleared.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
Powergood
Correctable Error Status (CERRSTS)
This bit is set when a correctable single-bit error occurs on a
memory read data transfer. When this bit is set, the address
that caused the error and the error syndrome are also logged
and they are locked to further single bit errors, until this bit is
cleared.
A multiple bit error that occurs after this bit is set will override
the address/error syndrome information.
This bit is cleared when the corresponding bit in
0.0.0.PCI.ERRSTS is cleared.
0b
ECCERRLOG1_C1 - ECC Error Log 1
This register is used to store the error status information in ECC enabled
configurations, along with the error syndrome and the row and column address
information of the address block of main memory of which an error (single bit or multibit error) has occurred.
Table 11-10. Channel 1 ECC Error Log 1
11.9
31:16
ROS-V
0000h
Powergood
Error Column (ERRCOL)
This field holds the DRAM column address of the read
transaction that had the ECC error.
15:0
ROS-V
0000h
Powergood
Error Row (ERRROW)
This field holds the DRAM row (page) address of the read
transaction that had the ECC error.
MAD_DIMM_CH0 - Address Decode Channel 0
This register defines channel characteristics - number of DIMMs, number of ranks, size,
ECC, interleave options and ECC options.
Table 11-11. Address Decode Channel 0
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR_MCMAIN
5004–5007h
00600000h
RW-L
32 bits
00h
Access
Reset
Value
31:26
RO
0h
Reserved (RSVD)
23
RO
0h
Reserved (RSVD)
22
RW-L
1b
Bit
RST/
PWR
Uncore
Description
Enhanced Interleave mode (Enh_Interleave)
0 = off
1 = on
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B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR_MCMAIN
5004–5007h
00600000h
RW-L
32 bits
00h
Bit
Access
Reset
Value
RST/
PWR
21
RW-L
1b
Uncore
Rank Interleave (RI)
0 = off
1 = on
20
RW-L
0b
Uncore
DIMM B DDR width (DBW)
0 = X8 chips
1 = X16 chips
19
RW-L
0b
Uncore
DIMM A DDR width (DAW)
0 = X8 chips
1 = X16 chips
18
RW-L
0b
Uncore
DIMM B number of ranks (DBNOR)
0 = single rank
1 = dual rank
17
RW-L
0b
Uncore
DIMM A number of ranks (DANOR)
0 = single rank
1 = dual rank
Description
16
RW-L
0b
Uncore
DIMM A select (DAS)
Selects which of the DIMMs is DIMM A – should be the larger
DIMM:
0 = DIMM 0
1 = DIMM 1
15:8
RW-L
00h
Uncore
Size of DIMM B (DIMM_B_Size)
Size of DIMM B in 256 MB multiples
7:0
RW-L
00h
Uncore
Size of DIMM A (DIMM_A_Size)
Size of DIMM A in 256 MB multiples
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11.10
MAD_DIMM_CH1 - Address Decode Channel 1
This register defines channel characteristics - number of DIMMs, number of ranks, size,
ECC, interleave options and ECC options.
Table 11-12. Address Decode Channel 1
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
0/0/0/MCHBAR_MCMAIN
5008–500Bh
00600000h
RW-L
32 bits
00h
Bit
Access
Reset
Value
RST/
PWR
31:26
RO
0h
Reserved (RSVD)
23
RO
0h
Reserved (RSVD)
22
RW-L
1b
Uncore
Enhanced Interleave mode (Enh_Interleave)
0 = off
1 = on
21
RW-L
1b
Uncore
Rank Interleave (RI)
0 = off
1 = on
20
RW-L
0b
Uncore
DIMM B DDR width (DBW)
0 = X8 chips
1 = X16 chips
19
RW-L
0b
Uncore
DIMM A DDR width (DAW)
0 = X8 chips
1 = X16 chips
18
RW-L
0b
Uncore
DIMM B number of ranks (DBNOR)
0 = single rank
1 = dual rank
17
RW-L
0b
Uncore
DIMM A number of ranks (DANOR)
0 = single rank
1 = dual rank
Description
16
RW-L
0b
Uncore
DIMM A select (DAS)
Selects which of the DIMMs is DIMM A – should be the larger DIMM.
0 = DIMM 0
1 = DIMM 1
15:8
RW-L
00h
Uncore
Size of DIMM B (DIMM_B_Size)
Size of DIMM B in 256 MB multiples
7:0
RW-L
00h
Uncore
Size of DIMM A (DIMM_A_Size)
Size of DIMM A in 256 MB multiples
Note:
This document supplements or overrides the Mobile 3rd Generation Intel® Core™
Processor Family, Intel® Pentium® Processor Family, and Intel® Celeron® Processor
Family Datasheet, Volume . For additional information, see the Mobile 3rd Generation
Intel® Core™ Processor Family, Intel® Pentium® Processor Family, and Intel®
Celeron® Processor Family Datasheet, Volume 2.
11.11
Error Detection and Correction
If ECC is enabled and DIMMS with ECC are used, through an Error Correction Code
algorithm the memory controller is able to detect and correct single bit errors or detect
multiple bit errors. ECC increases the reliability of the DRAM devices by allowing single
bit errors to be fixed and detecting multi-bit errors but it requires additional bits to
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store the error correction code. The ECC algorithm requires an 8-bit error correction
code. DIMMs with ECC are 72 bits wide, the first 64 bits are for data and the last 8 bits
are for the Check Bits.
Detection of correctable or uncorrectable errors are reported in the “ERRSTS - Error
Status” register. When either Single-bit correctable or Multi-bit uncorrectable errors are
detected, the column, row, bank, and rank that caused the error, and the error
syndrome, are logged in the ECC Error Log registers in the channel where the error
occurred. Channel 0 and Channel 1 errors are detailed in Section 11.5,
“ECCERRLOG0_C0 - ECC Error Log 0”, Section 11.6, “ECCERRLOG1_C0 - ECC Error Log
1”, Section 11.7, “ECCERRLOG0_C1 - ECC Error Log 0” and Section 11.8,
“ECCERRLOG1_C1 - ECC Error Log 1” respectively. If an uncorrectable error occurs
after a correctable error, then the address and syndrome information will be replaced
with the uncorrectable error information.
During the write cycle, ECC check bits are generated 1 per 8 bits of data by XORing a
particular combination of the written bits with an associated Check Bit. The result of
this function creates a syndrome byte that is visible via “Error Syndrome (ERRSYND)”,
(“ECCERRLOG0_C0 - ECC Error Log 0” or “ECCERRLOG0_C1 - ECC Error Log 0”).
Table 11-13 provides a lookup of the ERRSYND and defines the failing data bit.
Table 11-13. Error Syndrome - ERRSYND (Sheet 1 of 3)
Syndrome
(ERRSYND)
Bit Locator
0x00
DQ/CB
Locator
No Error
0x01
64
CB0
0x02
65
CB1
0x04
66
CB2
0x07
60
DQ60
0x08
67
CB3
0x0B
36
DQ36
0x0D
27
DQ27
0x0E
3
DQ3
0x10
68
CB4
0x13
55
DQ55
0x15
10
DQ10
0x16
29
DQ29
0x19
45
DQ45
0x1A
57
DQ57
0x1C
0
DQ0
0x1F
15
DQ15
0x20
69
CB5
0x23
39
DQ39
0x25
26
DQ26
0x26
46
DQ46
0x29
61
DQ61
0x2A
9
DQ9
0x2C
16
DQ16
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Table 11-13. Error Syndrome - ERRSYND (Sheet 2 of 3)
Syndrome
(ERRSYND)
Bit Locator
DQ/CB
Locator
0x2F
23
DQ23
0x31
63
DQ63
0x32
47
DQ47
0x34
14
DQ14
0x38
30
DQ30
0x40
70
CB6
0x43
6
DQ6
0x45
42
DQ42
0x46
62
DQ62
0x49
12
DQ12
0x4A
25
DQ25
0x4C
32
DQ32
0x4F
51
DQ51
0x51
2
DQ2
0x52
18
DQ18
0x54
34
DQ34
0x58
50
DQ50
0x61
21
DQ21
0x62
38
DQ38
0x64
54
DQ54
0x68
5
DQ5
0x70
52
DQ52
0x80
71
CB7
0x83
22
DQ22
0x85
58
DQ58
0x86
13
DQ13
0x89
28
DQ28
0x8A
41
DQ41
0x8C
48
DQ48
0x8F
43
DQ43
0x91
37
DQ37
0x92
53
DQ53
0x94
4
DQ4
0x98
20
DQ20
0xA1
49
DQ49
0xA2
1
DQ1
0xA4
17
DQ17
0xA8
33
DQ33
0xB0
44
DQ44
0xC1
8
DQ8
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Table 11-13. Error Syndrome - ERRSYND (Sheet 3 of 3)
Syndrome
(ERRSYND)
Bit Locator
DQ/CB
Locator
0xC2
24
DQ24
0xC4
40
DQ40
0xC8
56
DQ56
0xD0
19
DQ19
0xE0
11
DQ11
0xF1
7
DQ7
0xF2
31
DQ31
0xF4
59
DQ59
35
DQ35
0xF8
0xFF
Error reported is due to
poisoning
All Other
Values
Unrecoverable Multi-bit
errors
§§
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