NCP81278T
Compact 2-Phase
Synchronous Buck
Controller with Integrated
Gate Drivers and PWM VID
Interface
The NCP81278T, a general−purpose two−phase synchronous buck
controller, integrates gate drivers and PWM VID interface in a QFN20
package and provides a compact−footprint power management
solution for new generation computing processors. It has a
programmable power save interface (PSI) and is able to operate in
1−phase diode emulation mode to obtain high efficiency in light−load
condition. Operating in high switching frequency up to 800 kHz
allows employing small size inductors and capacitors. The part is able
to support all−ceramic−capacitor applications.
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QFN20
CASE 485BC
MARKING DIAGRAM
NCP81
278T
ALYWG
G
Features
3.6 V to 24 V Input Voltage Range
Output Voltage up to 2.0 V with PWM VID Interface
Differential Output Voltage Sense
Integrated Gate Drivers
200 kHz ~ 800 kHz Switching Frequency
Power Saving Interface (PSI)
Support both 3.3 V and 1.8 V VID
Power Good Output
Programmable Over Current Protection
Over Voltage Protection
Under Voltage Protection
Thermal Shutdown Protection
QFN20, 3x3 mm, 0.4 mm Pitch Package
NCP81278T = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
PH1
LG1
PVCC
LG2
PH2
•
•
•
•
•
•
•
•
•
•
•
•
•
1
BST1
HG1
EN
PSI
VID
Typical Applications
VIDBUF
REFIN
VREF
FS
FBRTN
• GPU and CPU Power
• Graphics Card Applications
• Desktop and Notebook Applications
GND
BST2
HG2
PGOOD
COMP/ILMT
FB
(Top View)
ORDERING INFORMATION
Device
Package
Shipping†
NCP81278TMNTXG
QFN20
(Pb−Free)
4,000 /
Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2017
July, 2017 − Rev. 0
1
Publication Order Number:
NCP81278T/D
NCP81278T
VIN
+5V
18
PVCC
21
GND
HG1
2
BST1
1
PH1
20
LG1
19
VOUT
3.3V/1.8V
VIN
EN
3
EN
PSI
4
PSI
PG
13
5
VID
PGOOD
HG2
14
BST2
15
PH2
16
LG2
17
FBRTN
10
FB
11
COMP/
ILMT
12
VID
8
VREF
7
REFIN
6
VIDBUF
9
NCP81278T
FS
Figure 1. Typical Application Circuit with PWM−VID Interface
VIN
+5V
18
PVCC
21
GND
HG1
2
BST1
1
PH1
20
LG1
19
VOUT
3.3V/1.8V
VIN
EN
3
EN
PSI
4
PSI
PG
13
5
PGOOD
HG2
14
BST2
15
PH2
16
LG2
17
FBRTN
10
FB
11
VID
8
VREF
7
REFIN
6
VIDBUF
9
NCP81278T
FS
COMP/
12
ILMT
Figure 2. Typical Application Circuit without PWM−VID Interface
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2
NCP81278T
PVCC
PVCC
3
13
EN
UVLO
&
PGOOD
BST1
FAULT
HG1
PGOOD
PWM1
PH1
Gate Drive
1
PVCC
Thermal
Shutdown
PSI
PSI
Control
Ramp
Generator
PH1
BST2
Protections
(OVP,UVP,OCP)
HG2
RAMP2
PWM2
8
5
6
VREF
Reference
Voltage
PVCC
GND
VID
VIDBUF
PWM1
PH1
REFIN
LG1
FB
CS2
PWM2
PH2
LG2
10
FBRTN
GND
GND
12
21
15
14
16
LG2
17
Current
Sense
11
PH2
Gate Drive
2
CS1
7
20
PVCC
&
FS
2
LG1
GND
PWM
Control
RAMP1
9
1
19
2/1 Phase
4
18
COMP/ILMT
Figure 3. Functional Block Diagram
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3
NCP81278T
PIN DESCRIPTION
Pin
Name
Type
Description
1
BST1
Analog Power
Bootstrap 1. Provides bootstrap voltage for the high−side gate drive of phase 1. A
0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH1 (pin 20).
2
HG1
Analog Output
High−Side Gate 1. Directly connected with the gate of the high−side power MOSFET of
phase 1.
3
EN
Logic Input
Enable. Logic high enables the device and logic low makes the device in standby mode.
4
PSI
Logic Input
Power Saving Interface. Logic high enables 2−phase CCM operation, mid−level enables 1−phase CCM operation, and logic low enables 1−phase auto CCM/DCM operation.
5
VID
Logic Input
Voltage ID. Voltage ID input from processor.
6
VIDBUF
Analog Output
7
REFIN
Analog Input
Reference Input. Reference voltage input for output voltage regulation. The pin is connected to a non−inverting input of internal error amplifier.
8
VREF
Analog Output
Output Reference Voltage. Precise 2 V reference voltage output. A 10 nF ceramic capacitor is required from this pin to GND.
9
FS
Analog Input
Frequency Selection. A resistor from this pin to ground programs switching frequency.
10
FBRTN
Analog Input
Voltage Feedback Return Input. An inverting input of internal error amplifier.
Feedback. An inverting input of internal error amplifier.
Voltage ID Buffer. VID PWM pulse output from an internal buffer.
11
FB
Analog Input
12
COMP/ILMT
Analog Output
Compensation / ILMT. Output pin of error amplifier. A resistor may be applied between
this pin and GND to program OCP threshold.
13
PGOOD
Logic Output
Power GOOD. Open−drain output. Provides a logic high valid power good output signal,
indicating the regulator’s output is in regulation window.
14
HG2
Analog Output
High−Side Gate 2. Connected with the gate of the high−side power MOSFET in phase 2.
15
BST2
Analog Power
Bootstrap 2. Provides bootstrap voltage for the high−side gate drive of phase 2. A
0.1 mF ~ 1 mF ceramic capacitor is required from this pin to PH2 (pin 16).
16
PH2
Analog Input
Phase Node 2. Connected to interconnection between high−side MOSFET and low−side
MOSFET in phase 2.
17
LG2
Analog Output
Low−Side Gate 2. Connected with the gate of the low−side power MOSFET in phase 2.
18
PVCC
Analog Power
Voltage Supply of Controller and Gate Driver. Power supply input pin of control circuit
and internal gate drivers. A 4.7 mF or larger ceramic capacitor bypasses this input to
ground. This capacitor should be placed as close as possible to this pin.
19
LG1
Analog Output
Low−Side Gate 1. Connected with the gate of the low−side power MOSFET in phase 1.
20
PH1
Analog Input
Phase Node 1. Connected to interconnection between high−side MOSFET and low−side
MOSFET in phase 1.
21
THERM/GND
Analog Ground
Thermal Pad and Ground. Common ground of internal control circuits and gate drivers.
Must be connected to the system ground.
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4
NCP81278T
MAXIMUM RATINGS
Value
Rating
PH to GND
Supply Voltage PVCC to GND
BST to GND
Symbol
Min
Max
Unit
VPH
−2
−8 (<100 ns)
30
V
VPVCC
−0.3
6.5
V
VBST_GND
−0.3
35
V
BST to PH
VBST_PH
−0.3
6.5
V
HG to PH
VHG
−0.3
−2 (<200 ns)
BST+0.3
V
LG to GND
VLG
−0.3
−2 (<200 ns)
MIN (PVCC+0.3, 6.5)
V
VFBRTN
−0.3
0.3
V
−0.3
MIN (VCC+0.3, 6.5)
V
ILU
−100
100
mA
Operating Junction Temperature Range (Notes 3 and 4)
TJ
−40
125
°C
Operating Ambient Temperature Range
TA
−40
125
°C
Storage Temperature Range
TSTG
−40
150
°C
Thermal Resistance Junction to Top Case (Note 5)
RΨJC
5
°C/W
Thermal Resistance Junction to Board (Note 5)
RΨJB
4
°C/W
Thermal Resistance Junction to Ambient (Note 4)
RθJA
40
°C/W
PD
2.5
W
MSL
1
−
FBRTN to GND
Other Pins to GND
Latch−up Current (Note 2)
Power Dissipation (Note 6)
Moisture Sensitivity Level (Note 7)
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device is ESD sensitive. Handling precautions are needed to avoid damage or performance degradation.
2. Latch up Current per JEDEC standard: JESD78 class II.
3. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
4. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM.
5. JEDEC standard JESD 51−7 (1S2P Direct−Attach Method) with 0 LFM. It is for checking junction temperature using external measurement.
6. The maximum power dissipation (PD) is dependent on input voltage, maximum output current and external components selected. Tambient
= 25°C, Tjunc_max = 125°C, PD = (Tjunc_max−T_amb)/Theta JA.
7. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
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5
NCP81278T
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 1.8 V, typical values are referenced to
TA = TJ = 25°C, Min and Max values are referenced to TA = TJ = −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Units
SUPPLY VOLTAGE
VIN Supply Voltage Range
(Note 8)
VIN
3.6
12
24
V
PVCC Supply Voltage Range
(Note 8)
VPCC
4.5
5
5.5
V
PVCC Under−Voltage (UVLO) Threshold
PVCC falling
VCCUV−
4.0
4.11
4.2
V
PVCC OK Threshold
PVCC rising
VCCOK
4.2
4.31
4.4
V
ICC
mA
SUPPLY CURRENT
PVCC Quiescent Current
PVCC Shutdown Current
EN high, no switching
PS0
−
4.6
7.5
PS1
−
4.65
7.5
PS2
−
4.59
7.5
12
50
mA
800
kHz
EN low
IsdPCC
−
PS0 Switching Frequency Range
(Note 8)
FSW
200
FS Voltage
RFS = 39.2 kW
VFS
SWITCHING FREQUENCY SETTING
2.0
V
VOLTAGE REFERENCE
VREF Reference Voltage
IREF = 1 mA
VVREF
1.98
2.0
2.02
V
Minimum On Time
(Note 8)
Ton_min
50
ns
Minimum Off Time
(Note 8)
Toff_min
250
ns
Open−Loop DC Gain
(Note 8)
GAINEA
80
dB
Unity Gain Bandwidth
(Note 8)
GBWEA
20
MHz
Slew Rate
(Note 8)
COMP Voltage Swing
ICOMP(source) = 2 mA
VmaxCOMP
3.1
3.4
−
V
ICOMP(sink) = 2 mA
VminCOMP
−
0.95
1.10
V
IFB
−400
PWM MODULATION
VOLTAGE ERROR AMPLIFIER
SRCOMP
FB, REFIN Bias Current
VFB = VREFIN = 1.0 V
Input Offset Voltage
VosEA = VREFIN − VFB (Note 8)
TJ = 25°C
TJ = −40°C to 125°C
REFIN Discharge Switch ON−Resistance
20
V/ms
400
VosEA
nA
mV
−0.65
−11
IREFIN (sink) = 2 mA
0.65
6.5
W
7.0
CURRENT−SENSE AMPLIFIER
Closed−Loop DC Gain
GAINCA
−4.9
V/V
−3 dB Gain Bandwidth
(Note 8)
BWCA
10
MHz
Input Offset Voltage
VosCS = VPH − VGND (Note 8)
VosCS
−500
−
500
mV
VhighEN
1.5
−
−
V
EN Low Logic Level
VlowEN
−
−
0.7
EN Hysteresis
VhysEN
ENABLE
EN High Logic Level
EN Input Bias Current
External 1 K pull−up to 1.8 V
350
IbiasEN
−
−
V
mV
1.0
mA
POWER SAVE INPUT
High Logic Level
PS0: 2−Phase CCM Mode
VhighPSI
1.5
Mid Logic Level
PS1: 1−Phase CCM Mode
VmidPSI
0.6
Low Logic Level
PS2: 1−Phase Auto CCM/DCM Mode
VlowPSI
Internal Pull High Resistance
PSI to internal 2.0 V
V
105
8. Guaranteed by design, not tested in production.
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6
1.2
V
0.3
V
kW
NCP81278T
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 1.8 V, typical values are referenced to
TA = TJ = 25°C, Min and Max values are referenced to TA = TJ = −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Units
POWER SAVE INPUT
PSI to GND
86
kW
Vout Startup Delay
From EN to Vout Start up (Note 8)
289
ms
Vout Startup Slew Rate
(Note 8)
0.643
V/ms
PGOOD Startup Delay
From EN to PGOOD assertion
1.85
ms
PGOOD Shutdown Delay
From EN to PGOOD de−assertion
PGOOD Low Voltage
IPGOOD= 4 mA (sink)
VlPGOOD
−
−
0.3
V
PGOOD Leakage Current
PGOOD = 5 V
IlkgPGOOD
−
−
1.0
mA
IILMT
9.5
10
10.5
mA
Internal Pull Low Resistance
SOFT START and PGOOD
125
ns
PROTECTION
Source Current of OCP Programming
Source out COMP pin
Minimum Programming Voltage in
COMP
RCOMP = 5 kW
50
mV
Maximum Programming Voltage in
COMP
RCOMP = 80 kW
800
mV
10
mV
Programming Voltage Resolution in
COMP
OCP Programming Gain
VCOMP / (VGND − VPH)
Fast Under Voltage Protection (FUVP)
Threshold
Voltage from FB to GND
4.9
Fast Under Voltage Protection (FUVP)
Delay
(Note 8)
1.0
ms
Slow Under Voltage Protection (SUVP)
Threshold
Voltage from COMP to GND
3.0
V
Slow Under Voltage Protection (SUVP)
Delay
(Note 8)
50
ms
Over Voltage Protection (OVP)
Threshold
Voltage from FB to GND
Over Voltage Protection (OVP) Delay
(Note 8)
Over Temperature Protection (OTP)
Threshold
(Note 8)
Tsd
Recovery Temperature Threshold
(Note 8)
Trec
Over Temperature Protection (OTP)
Delay
(Note 8)
0.15
1.85
140
0.2
2.0
V/V
0.25
2.15
V
V
1.0
ms
150
°C
125
°C
125
ns
5
kW
OUTPUT DISCHARGE
Output Discharge Resistance per Phase
Measured from PHx to GND when EN is
low (Note 8)
Rdischrg
PWM−VID BUFFER
Input High Logic Level
VhighVID
1.5
Input Mid Logic Level
VmidVID
0.6
Input Low Logic Level
VlowVID
V
1.2
V
0.3
V
Internal Pull High Resistance in VID Pin
VID to internal 2.0 V
105
kW
Internal Pull Low Resistance in VID Pin
VID to GND
86
kW
350
ns
3−State Shut−Off Time
TD_HOLD−
OFF
Buffer Output Rise Time
Tr
3
ns
Buffer Output Fall Time
Tf
3
ns
8. Guaranteed by design, not tested in production.
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7
NCP81278T
ELECTRICAL CHARACTERISTICS (VIN = 12 V, VPVCC = 5 V, VREFIN = 1.0 V, VPSI = 1.8 V, typical values are referenced to
TA = TJ = 25°C, Min and Max values are referenced to TA = TJ = −40°C to 125°C. unless other noted.)
Characteristics
Test Conditions
Symbol
Min
Typ
Max
Units
PWM−VID BUFFER
Propagation Delay
Tpd = TpHL =TpLH
Tpd
8
ns
INTERNAL HIGH−SIDE GATE DRIVE
Pull−High Drive ON Resistance
VBST – VPH = 5 V, IHG = 50 mA (source)
RDRV_HH
−
2.5
−
Pull−Low Drive ON Resistance
VBST – VPH = 5 V, IHG = 50 mA (sink)
RDRV_HL
−
1.0
−
HG Propagation Delay Time
From LG off to HG on
TpdHG
27
W
W
ns
INTERNAL LOW−SIDE GATE DRIVE
Pull−High Drive ON Resistance
VPVCC – VGND = 5 V, ILG = 50 mA
(source)
RDRV_LH
−
1.5
−
W
Pull−Low Drive ON Resistance
VPVCC – VGND = 5 V, ILG = 50 mA (sink)
RDRV_LL
−
0.6
−
W
LG Propagation Delay Time
From HG off to LG on
TpdLG
On Resistance of Rectifier Switch
VPVCC = 5 V, Id = 2 mA, TA = 25°C
RBST
30
50
75
W
Rectifier Switch Leakage Current
VPVCC = 5 V, EN = 0 V
IlkgBST
−
−
3
mA
26
ns
BOOTSTRAP
8. Guaranteed by design, not tested in production.
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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8
NCP81278T
DETAILED DESCRIPTION
General
regulator’s output voltage sense points via a Kelvin−sense
pair. The output voltage sense signal goes through a
compensation network and into the inverting input (FB pin)
of the error amplifier. The non−inverting input of the error
amplifier is connected to the reference input (REFIN pin).
The NCP81278T, a 2−phase synchronous buck controller,
integrates gate drivers and PWM VID interface in a QFN−20
package and provides a compact−footprint power
management solution for new generation computing
processors. It receives power save input (PSI) from
processors and operates in 1−phase diode emulation mode
to obtain high efficiency in light−load condition. Operating
in high switching frequency up to 800 kHz allows
employing small size inductors and capacitors. Introduction
of multi−phase current−mode RPM control results in fast
transient response and good dynamic current balance. It is
able to support all−ceramic−capacitor applications.
7
11
10
Operation Modes
21
The NCP81278T has total 3 power operation modes
responding to PSI levels as shown in Table 1. The operation
modes can be changed on the fly between two modes in an
allowed mode−change combination. There are only two
allowed mode−change combinations, which is either a
combination of PS0 and PS2 or a combination of PS1 and
PS2. In 1−phase operation, no switching in phase 2.
12
REFIN
FB
FBRTN
GND
COMP
Figure 4. Differential Error Amplifier
PWM VID
Table 1. POWER SAVING INTERFACE (PSI)
CONFIGURATIONS
PSI Level
Power Mode
Phase Configuration
High
PS0
2−Phase, CCM
Middle
PS1
1−Phase, CCM
Low
PS2
1−Phase, Auto CCM/DCM
The NCP81278T receives a PWMVID signal at VID pin
for the output voltage regulation. Figure 5 shows the
PWMVID dynamic voltage control circuit diagram. The
VID signal is decoded internally and passed to the VID
buffer output (VIDBUF), where the duty cycle is converted
to a corresponding PWM signal switching between 0 V and
2 V. The VIDBUF high level is derived from a precise 2.0 V
reference voltage VREF. The VIDBUF signal is then filtered
through an external low−pass filter constructed by
R_VIDBUF and C_REFIN. The filtered output is connected
to REFIN pin. REFIN is the voltage reference of the output
voltage regulator. The dynamic range of the circuit is
determined by the external resistor network. The resistor
network and capacitor C_REFIN function as a filter for the
PWMVID signal, and will affect ripple voltage and
transition slew rate in REFIN signal.
The NCP81278T is also able to support pure single−phase
applications without a need to stuff components for phase 2.
In this configuration, the four pins including BST2, HG2,
LG2, and PH2 can be float, but make sure the voltage at PSI
pin is never in high level.
Remote Voltage Sense
A high performance and high input impedance
differential error amplifier, as shown in Figure 4, provides
an accurate sense for the output voltage of the regulator. The
output voltage and FBRTN inputs should be connected to the
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9
NCP81278T
VREF = 2 V
R_VREF1
C_VREF
VIDBUF
R_VREF2
VID
C_REFIN
105 k
REFIN
86 k
R_VIDBUF
Figure 5. PWM VID Interface
Switching Frequency
Iout = 10 A for 1−phase operation and Iout = 20 A for
2−phase operation. It can be also found that the lower Rdson
of the low−side MOSFETs the smaller frequency difference
between 2−phase mode and 1−phase mode.
The switching frequency is also sensitive to PCB layout
especially in grounding. The exposed pad of the
NCP81278T must be directly connected to the ground
planes through multiple vias underneath.
Switching frequency is programmed by a resistor RFS
applied from the FS pin to ground. The typical frequency
range is from 200 KHz to 800 kHz. The FS pin provides
approximately 2 V out and the source current is mirrored
into the internal ramp generator.
To reduce output ripple in 1−phase operation, the
switching frequency in 1−phase CCM operation is set to be
higher than 2−phase CCM operation.
Figure 6 shows a measurement based on a typical
application under condition of Vin = 20 V, Vout = 0.8 V,
Figure 6. Switching Frequency Programmed by Resistor RFS at FS Pin
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10
NCP81278T
Soft Start
Under Voltage Protection (UVP)
The NCP81278T has a soft start function. The output
starts to ramp up following a system reset period after the
device is enabled. The device is able to start up smoothly
under an output pre−biased condition without discharging
the output before ramping up.
There are two under voltage protections implemented in
the NCP81278T, which are fast under voltage protection and
slow under voltage protection.
Fast under voltage protection (FUVP) protects converters
in case of an extreme short circuit in output by monitoring
FB voltage. Once FB voltage drops below 0.2 V for more
than 1 ms, the NCP81278T latches off, both the high−side
MOSFETs and the low−side MOSFETs in all phases are
turned off. The fault remains set until the system has either
VCC or EN toggled state. The FUVP function is disabled in
soft start.
Slow under voltage protection (SUVP) of the
NCP81278T is based on voltage detection at COMP pin. In
normal operation, COMP level is below 2.5 V. When the
output voltage drops below REFIN voltage for long time and
COMP rises to be over 3 V, an internal UV fault timer will
be triggered. If the fault still exists after 50 ms, the
NCP81278T latches off, both the high−side MOSFETs and
the low−side MOSFETs in all phases are turned off. The
fault remains set until the system has either VCC or EN
toggled state.
REFIN Discharge
An internal switch in REFIN pin starts to short REFIN to
GND just after EN is pulled high and it turns off just before
the beginning of the soft start. The typical on resistance of
the switch is 7.0 W.
Output Discharge in Shut Down
The NCP81278T has an output discharge function when
the device is in shutdown mode. The resistors (5 kW per
phase) from PH node to GND in both phases are active to
discharge the output capacitors.
Over Current Protection (OCP)
The NCP81278T protects converters from over current.
The current through each phase is monitored by voltage
sensing from phase node PHx to GND pin. The sense signal
is compared to a programmed voltage threshold VthOC.
Once over load happens, the inductor current is limited to an
average current per phase, which can be estimated by
I LMT(phase) +
*5
V O @ ǒV IN * V OǓ
@ R COMP
10
)
4.9 @ R DS(phase)
2 @ V IN @ L @ F SW
Over Voltage Protection (OVP)
Over voltage protection of the NCP81278T is based on
voltage detection at FB pin. Once FB voltage is over 2 V for
more than 1 ms, all the high−side MOSFETs are turned off
and all the low−side MOSFETs are latched on. The
NCP81278T latches off until the system has either VCC or
EN has toggled state.
(eq. 1)
where RDS(phase) is a total on conduction resistance of
low−side MOSFETs per phase, and RCOMP is the resistance
of the OCP programming resistor connected from the
COMP pin to ground. Normally, a continuous over load
event leads to a voltage drop in the output voltage and
possible to eventually trip under voltage protection.
The detection of OCP programming is done during the
289 ms startup delay time ahead of soft start. To assure
accurate resistance detection, the total capacitance from
COMP pin to FB pin should be less than 330 pF.
Thermal Shutdown (TSD)
The NCP81278T has a thermal shutdown protection to
protect the device from overheating when the die
temperature exceeds 150°C. Once the thermal protection is
triggered, the fault state can be ended by re−applying VCC
and/or EN if the temperature drops down below 125°C.
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11
NCP81278T
LAYOUT GUIDELINES
• Current Sense: The NCP81278T senses phase currents
Electrical Layout Considerations
Good electrical layout is a key to make sure proper
operation, high efficiency, and noise reduction.
• Power Paths: Use wide and short traces for power
paths to reduce parasitic inductance and
high−frequency loop area. It is also good for efficiency
improvement.
• Power Supply Decoupling: The power MOSFET
bridges should be well decoupled by input capacitors
and input loop area should be as small as possible to
reduce parasitic inductance, input voltage spike, and
noise emission. Place decoupling caps as close as
possible to the controller PVCC pin.
• Output Decoupling: The output capacitors should be
as close as possible to the load like a GPU. If the load is
distributed, the capacitors should also be distributed
and generally placed in greater proportion where the
load is more dynamic.
• Switching Nodes: Switching nodes between HS and
LS MOSFETs should be copper pours to carry high
current and dissipate heat, but compact because they are
also noise sources.
• Gate Drive: All the gate drive traces such as HGx,
LGx, PHx, and BSTx should be short, straight as
possible, and not too thin. The bootstrap cap and an
option resistor need to be very close and directly
connected between BSTx pin and PHx pin.
• Ground: It would be good to have more ground planes.
Ground planes are isolation between noisy power traces
and all the sensitive control circuits. Directly connect
the exposed pad (GND pin) to ground planes through
multiple vias underneath.
• Voltage Sense: Use Kelvin sense pair and arrange a
“quiet” path for the differential output voltage sense.
•
•
by monitoring voltages from phase nodes PHx to the
common ground GND pin. Ground planes should be
well underneath PHx trances. To get better current
balance between the two phases, try to make a layout as
symmetrical as possible and balance the current flow in
ground planes for the two phases.
Compensation Network: The compensation network
should be close to the controller. Keep FB trace short to
minimize their capacitance to ground planes.
PWM VID Circuit: The PWM VID is a high slew−rate
digital signal from GPU to the controller. The trace
routing of it should be done to avoid noise coupling
from the switching node and to avoid coupling to other
sensitive analog circuit as well. The RC network of the
PWM VID circuit needs to be close to the controller. A
10 nF ceramic cap is connected from VREF pin to
GND plane, and another small ceramic cap is connected
from REFIN pin to GND plane.
Thermal Layout Considerations
Good thermal layout helps high power dissipation from a
small−form factor VR with reduced temperature rise.
• The exposed pads of the controller and power
MOSFETs must be well soldered on the board.
• A four or more layers PCB board with solid ground
planes is preferred for better heat dissipation.
• More vias are welcome to be underneath the exposed
pads and surrounding the power devices to connect the
inner ground layers to reduce thermal resistances.
• Use large area copper pour to help thermal conduction
and radiation.
• Try distributing multiple heat sources to reduce
temperature rise in hot spots.
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12
NCP81278T
PACKAGE DIMENSIONS
QFN20 3x3, 0.4P
CASE 485BC
ISSUE O
ÍÍÍ
ÍÍÍ
ÍÍÍ
D
PIN ONE
REFERENCE
A B
L1
DETAIL A
E
ALTERNATE TERMINAL
CONSTRUCTIONS
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
2X
EXPOSED Cu
0.10 C
2X
TOP VIEW
DETAIL B
0.05 C
L
L
A3
ÇÇ
ÉÉ
A3
A1
DETAIL B
A
0.05 C
MOLD CMPD
ALTERNATE
CONSTRUCTIONS
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
MILLIMETERS
DIM
MIN
MAX
A
0.80
1.00
A1
--0.05
A3
0.20 REF
b
0.15
0.25
D
3.00 BSC
D2
1.70
1.90
E
3.00 BSC
E2
1.70
1.90
e
0.40 BSC
K
0.30 REF
L
0.20
0.40
L1
0.00
0.15
A1
NOTE 4
SEATING
PLANE
C
SIDE VIEW
SOLDERING FOOTPRINT*
20X
D2
DETAIL A
0.52
6
1
11
20X
K
E2
2X
3.30
2X
1.86
1
20X
L
e
16
20X
BOTTOM VIEW
b
0.07 C A
0.05 C
20X
0.26
B
0.40
PITCH
NOTE 3
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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