Intel®Server Boards S2400LP
Technical Product Specification
Intel order number G52803-002
Revision 2.0
December 2013
Platform Collaboration and Systems Division - Marketing
Revision History
Intel®Server Boards S2400LP TPS
Revision History
Date
May 2012
Revision
Number
1.0
Initial release.
December 2013
2.0
Added support for Intel Xeon processor E5-2400 v2 product family
ii
Modifications
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®
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Disclaimers
Disclaimers
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Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
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Table of Contents
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Table of Contents
1. Introduction ........................................................................................................................ 1
1.1
Section Outline ....................................................................................................... 1
1.2
Server Board Use Disclaimer ................................................................................. 2
2. Server Board Overview ...................................................................................................... 3
2.1
Server Board Connector and Component Layout ................................................... 5
2.1.1
Board Rear Connector Placement .......................................................................... 5
2.2
Server Board Mechanical Drawings ....................................................................... 6
3. Product Architecture Overview ......................................................................................... 8
3.1
High Level Product Features .................................................................................. 8
3.2
Processor Support ................................................................................................. 9
3.2.1
Processor Socket Assembly ................................................................................... 9
3.2.2
Processor Population Rules ................................................................................. 10
3.3
Processor Functions Overview ............................................................................. 13
3.3.1
Intel® QuickPath Interconnect ............................................................................... 13
3.3.2
Integrated Memory Controller (IMC) and Memory Subsystem .............................. 14
3.3.2.1 Supported Memory ............................................................................................ 15
3.3.2.2 Memory Population Rules .................................................................................. 17
3.3.2.3 Publishing System Memory ............................................................................... 18
3.3.2.4 RAS Features .................................................................................................... 18
3.3.3
Processor Integrated I/O Module (IIO) .................................................................. 19
3.3.3.1 Riser Card Support ............................................................................................ 20
3.3.3.2 Riser Types ....................................................................................................... 21
3.3.3.3 Network Interface .............................................................................................. 22
3.3.3.4 I/O Module Support ........................................................................................... 23
3.4
Intel® C600-A/B PCH Functional Overview ........................................................... 23
3.4.1
PCI Express* ........................................................................................................ 24
3.4.2
Universal Serial Bus (USB) .................................................................................. 24
3.4.3
Serial Attached SCSI(SAS) and Serial ATA(SATA) Controller.............................. 25
3.4.4
PCI Interface ........................................................................................................ 26
3.4.5
Low Pin Count (LPC) Interface ............................................................................. 26
3.4.6
Digital Media Interface (DMI) ................................................................................ 26
3.4.7
Serials Peripheral Interface (SPI) ......................................................................... 26
3.4.8
Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller) ..... 26
3.4.9
Advanced Programmable Interrupt Controller (APIC) ........................................... 27
3.4.10 Real Time Clock (RTC) ........................................................................................ 27
3.4.11 GPIO .................................................................................................................... 27
3.4.12 Enhanced Power Management ............................................................................ 27
3.4.13 Fan Speed Control ............................................................................................... 27
3.4.14 Intel® Virtualization Technology for Direct I/O (Intel® VT-d) ................................... 28
3.4.15 KVM/Serial Over LAN (SOL) Function .................................................................. 28
3.4.16 IDE-R Function..................................................................................................... 28
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3.4.17 Manageability ....................................................................................................... 28
3.4.18 System Management Bus (SMBus* 2.0) .............................................................. 29
3.4.19 Network Interface Controller (NIC) ....................................................................... 29
3.4.19.1 MAC Address Definition (TBD) ........................................................................ 30
3.4.19.2 LAN Manageability .......................................................................................... 30
3.4.19.3 Wake-On-LAN ................................................................................................. 31
3.4.19.4 LAN Connector Ordering ................................................................................. 31
3.4.19.5 Intel® I350 Thermal Sensor .............................................................................. 31
3.5
InfiniBand* Controller ........................................................................................... 31
3.5.1
Device Interfaces ................................................................................................. 32
3.5.2
Quad Small Form-factor Pluggable (QSFP) connector ......................................... 32
3.6
Baseboard Management Controller Overview ...................................................... 33
3.6.1
Super I/O Controller ............................................................................................. 35
3.6.1.1 Keyboard and Mouse Support ........................................................................... 35
3.6.1.2 Wake-up Control................................................................................................ 35
3.6.2
Graphics Controller and Video Support ................................................................ 35
3.6.3
Remote KVM ........................................................................................................ 36
4. Platform Management Functional Overview ................................................................... 38
4.1
Baseboard Management Controller (BMC) Firmware Feature Support................. 38
4.1.1
IPMI 2.0 Features................................................................................................. 38
4.1.2
Non IPMI Features ............................................................................................... 39
4.1.3
New Manageability Features ................................................................................ 40
4.2
Advanced Configuration and Power Interface (ACPI) ........................................... 41
4.3
Platform Management SMBus* and I2C Implementation....................................... 42
4.4
BMC Internal Timestamp Clock ............................................................................ 42
4.5
Sensor Monitoring ................................................................................................ 43
4.6
Messaging Interfaces ........................................................................................... 43
4.6.1
Channel Management .......................................................................................... 43
4.6.2
User Model ........................................................................................................... 44
4.6.3
Sessions .............................................................................................................. 44
4.6.4
BMC LAN Channels ............................................................................................. 45
4.6.4.1 Baseboard NICs ................................................................................................ 45
4.6.4.2 Dedicated Management Channel....................................................................... 46
4.6.4.3 Concurrent Server Management Use of Multiple Ethernet Controllers ............... 46
4.6.5
IPV6 Support ........................................................................................................ 47
4.6.5.1 LAN Failover ...................................................................................................... 47
4.7
System Event Log (SEL) ...................................................................................... 48
4.7.1
Servicing Events .................................................................................................. 48
4.7.2
SEL Entry Deletion ............................................................................................... 48
4.7.3
SEL Erasure ......................................................................................................... 48
4.7.4
SEL Extension Capabilities .................................................................................. 48
4.8
Sensor Data Record (SDR) Repository ................................................................ 49
4.9
Field Replaceable Unit (FRU) Inventory Device ................................................... 49
4.10
Diagnostics and Beep Code Generation............................................................... 49
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4.11
Diagnostics Interrupt (NMI)................................................................................... 50
4.12
BMC Basic and Advanced Management Features ............................................... 50
4.12.1 Enabling Advanced Manageability Features ......................................................... 51
4.12.1.1 Keyboard, Video and Mouse (KVM) Redirection .............................................. 51
4.12.1.2 Remote Console .............................................................................................. 52
4.12.1.3 Performance .................................................................................................... 52
4.12.1.4 Security ........................................................................................................... 52
4.12.1.5 Availability ....................................................................................................... 52
4.12.1.6 Timeout ........................................................................................................... 52
4.12.1.7 Usage .............................................................................................................. 53
4.12.2 Media Redirection .............................................................................................. 53
4.12.2.1 Availability ....................................................................................................... 54
4.12.2.2 Network Port Usage ........................................................................................ 54
4.12.3 Embedded Web server ....................................................................................... 54
4.12.4 Data Center management Interface (DCM) ........................................................ 55
4.12.5 Local Directory Authentication Protocol (LDAP) ................................................. 56
4.12.6 Platform/Chassis Management .......................................................................... 56
4.12.7 Thermal Control ................................................................................................. 56
4.12.7.1 Fan Speed Control .......................................................................................... 57
4.12.7.2 System Configuration Using FRUSDR Utility ................................................... 57
4.12.8 Node Power On/Off Control................................................................................ 57
4.13
Intel® Intelligent Power Node Manager ................................................................. 57
4.13.1 Overview .............................................................................................................. 57
4.13.2 Features ............................................................................................................... 58
4.14
Management Engine (ME).................................................................................... 58
4.14.1 Overview .............................................................................................................. 58
4.14.2 BMC – Management Engine (ME) Distributed Model ........................................... 59
4.14.3 ME System Management Bus (SMBus*) Interface ............................................... 60
4.14.4 BMC - Management Engine Interaction ................................................................ 60
4.14.5 ME Power and Firmware Startup.......................................................................... 61
4.14.6 SmaRT/CLST ....................................................................................................... 61
4.15
Other Platform Management ................................................................................ 62
4.15.1 Wake On LAN (WOL) ........................................................................................... 62
4.15.2 PCI Express* Power management ....................................................................... 62
4.15.3 PMBus* ................................................................................................................ 62
4.15.4 Node Power policies............................................................................................. 62
4.16
BIOS Password Protection ................................................................................... 62
4.17
Trusted Platform Module(TPM) Support ............................................................... 64
4.17.1 TPM Security BIOS .............................................................................................. 64
4.17.2 Physical Presence ................................................................................................ 64
4.17.3 TPM Security Setup Options ................................................................................ 65
4.17.4 Security Screen .................................................................................................... 65
5. BIOS Setup Interface ........................................................................................................ 66
5.1
HotKeys Supported During POST ........................................................................ 66
5.2
POST Logo/Diagnostic Screen ............................................................................. 66
5.3
BIOS Boot Pop-up Menu ...................................................................................... 67
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5.4
BIOS Setup Utility ................................................................................................ 67
5.4.1
BIOS Setup Operation.......................................................................................... 67
5.4.1.1 Setup Page Layout ............................................................................................ 68
5.4.1.2 Entering BIOS Setup ......................................................................................... 69
5.4.1.3 Setup Navigation Keyboard Commands ............................................................ 69
5.4.1.4 Setup Screen Menu Selection Bar ..................................................................... 70
5.4.2
BIOS Setup Utility Screens................................................................................... 70
5.4.2.1 Map of Screens and Functionality ...................................................................... 71
5.4.2.2 Main Screen (Tab) ............................................................................................. 73
5.4.2.3 Advanced Screen (Tab) ..................................................................................... 74
5.4.2.4 Processor Configuration .................................................................................... 75
5.4.2.5 Power and Performance Policy .......................................................................... 80
5.4.2.6 Memory Configuration ....................................................................................... 83
5.4.2.7 Memory RAS and Performance Configuration ................................................... 85
5.4.2.8 Mass Storage Controller Configuration .............................................................. 86
5.4.2.9 PCI Configuration .............................................................................................. 88
5.4.2.10 NIC configuration ............................................................................................. 90
5.4.2.11 Serial Port Configuration.................................................................................. 97
5.4.2.12 USB Configuration ........................................................................................... 97
5.4.2.13 System Acoustic and Performance Configuration ............................................ 99
5.4.2.14 Security Screen (Tab) .................................................................................... 102
5.4.2.15 Server Management Screen (Tab) ................................................................ 104
5.4.2.16 Console Redirection ...................................................................................... 106
5.4.2.17 System Information........................................................................................ 107
5.4.2.18 BMC LAN Configuration ................................................................................ 109
5.4.2.19 Boot Options Screen (Tab) ............................................................................ 112
5.4.2.20 Hard Disk Order............................................................................................. 114
5.4.2.21 Network Device Order ................................................................................... 114
5.4.2.22 Delete EFI Boot Option .................................................................................. 115
5.4.2.23 Boot Manager Screen (Tab) .......................................................................... 116
5.4.2.24 Error Manager Screen (Tab) .......................................................................... 116
5.4.2.25 Save and Exit Screen (Tab) ........................................................................... 117
5.5
Loading BIOS Defaults ....................................................................................... 118
6. Configuration Jumpers .................................................................................................. 119
6.1
Force BMC Update (J9C2) ................................................................................. 120
6.2
BIOS Recovery Mode (J9F2) ............................................................................. 120
6.3
Password Clear (J6E1) ...................................................................................... 122
6.4
Force ME Update (J6E1) .................................................................................... 122
6.5
Reset BIOS Settings (J6E1) ............................................................................... 123
7. Connector/Header Locations and Pin-out .................................................................... 124
7.1
Power Connectors .............................................................................................. 124
7.2
System Management Headers ........................................................................... 124
7.2.1
Intel® Remote Management Module 4 (Intel® RMM4 Lite) Connector ................. 124
7.3
Bridge Board Connector ..................................................................................... 124
7.3.1
Power Button...................................................................................................... 125
7.3.2
Reset Button ...................................................................................................... 126
7.3.3
Chassis Identify Button....................................................................................... 126
7.3.4
Power LED ......................................................................................................... 126
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7.3.5
System Status LED ............................................................................................ 126
7.3.6
Chassis ID LED .................................................................................................. 129
7.4
I/O Connectors ................................................................................................... 129
7.4.1
PCI Express* Connectors ................................................................................... 129
7.4.2
VGA Connector .................................................................................................. 133
7.4.3
NIC Connectors.................................................................................................. 134
7.4.4
SATA DOM Connectors ..................................................................................... 134
7.4.5
Storage Upgrade Key Connector........................................................................ 134
7.4.6
Serial Port Connectors ....................................................................................... 135
7.4.7
USB Connectors ................................................................................................ 135
7.4.8
QSFP for InfiniBand* .......................................................................................... 135
7.5
Fan Headers ...................................................................................................... 136
®
8. Intel Light-Guided Diagnostics .................................................................................... 137
8.1
Front Panel Support ........................................................................................... 137
8.1.1
System ID LED................................................................................................... 137
8.1.2
System Status LED ............................................................................................ 137
8.1.3
Network Link/Activity LED .................................................................................. 137
8.1.4
Dedicated InfiniBand* Link/Activity LED ............................................................. 138
8.2
POST Code Diagnostic LEDs ............................................................................. 138
9. Environmental Limits Specification .............................................................................. 140
9.1
Processor Thermal Design Power (TDP) Support .............................................. 140
10. Power Supply Specification Guidelines ........................................................................ 141
10.1
Power Supply DC Output Connector .................................................................. 141
10.2
Power Supply DC Output Specification .............................................................. 141
10.2.1 Output Power/Currents....................................................................................... 141
10.2.2 Standby Output .................................................................................................. 141
10.2.3 Voltage Regulation ............................................................................................. 141
10.2.4 Dynamic Loading ............................................................................................... 142
10.2.5 Capacitive Loading ............................................................................................. 142
10.2.6 Grounding .......................................................................................................... 142
10.2.7 Closed loop stability ........................................................................................... 142
10.2.8 Residual Voltage Immunity in Standby mode ..................................................... 142
10.2.9 Common Mode Noise......................................................................................... 143
10.2.10 Soft Starting ....................................................................................................... 143
10.2.11 Zero Load Stability Requirements ...................................................................... 143
10.2.12 Hot Swap Requirements .................................................................................... 143
10.2.13 Forced Load Sharing .......................................................................................... 143
10.2.14 Ripple/Noise ....................................................................................................... 143
10.2.15 Timing Reuqirement ........................................................................................... 143
Appendix A: Integration and Usage Tips ............................................................................ 146
Appendix B: Integrated BMC Sensor Tables....................................................................... 147
Appendix C: BIOS Sensors and SEL Data .......................................................................... 160
Appendix D: POST Code LED Decoder ............................................................................... 167
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Appendix E: Video POST Code Errors ................................................................................ 174
Glossary ................................................................................................................................ 178
Reference Documents .......................................................................................................... 181
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List of Figures
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List of Figures
Figure 1. Intel® Server Board S2400LP (Base SKU) ................................................................... 3
Figure 2. Intel® Server Board S2400LP Components .................................................................. 5
Figure 3. Rear Panel Connector Placement ................................................................................ 6
Figure 4. Intel® Server Board S2400LP – Mounting Holes Locations .......................................... 6
Figure 5. Intel® Server Boards S2400LP – Major Connector Pin-1 Locations .............................. 7
Figure 6. Intel® Server Boards S2400LP Functional Block Diagram ............................................ 9
Figure 7. Processor Socket Assembly ....................................................................................... 10
Figure 8. Processor with IMC Functional Block Diagram ........................................................... 14
Figure 9. Intel® Server Board S2400LP DIMM Slot Layout ........................................................ 18
Figure 10. PCI Express Lane Distribution Scheme .................................................................... 21
Figure 11. PCIe Riser for Slot 1 ................................................................................................ 22
Figure 12. PCIe Riser for Slot 2 ................................................................................................ 22
Figure 13. Intel® C600-A/B PCH connection.............................................................................. 23
Figure 14. 1GbE NIC port LED.................................................................................................. 30
Figure 15. ConnectX®-3 function block diagram ........................................................................ 31
Figure 16. Connection between ConnectX®-3 and QSFP .......................................................... 32
Figure 17. Integrated BMC implementation overview ................................................................ 33
Figure 18. BMC Functional Block Diagram................................................................................ 34
Figure 19. Management Engine Distribution Model ................................................................... 60
Figure 20. Main Screen ............................................................................................................. 73
Figure 21. Advanced Screen ..................................................................................................... 75
Figure 22. Processor Configuration Screen............................................................................... 76
Figure 23. Power and Performance Configuration Screen ........................................................ 81
Figure 24. Memory Configuration Screen .................................................................................. 83
Figure 25. Memory RAS and Performance Configuration Screen ............................................. 85
Figure 26. Mass Storage Controller Configuration Screen ........................................................ 87
Figure 27. PCI Configuration Screen......................................................................................... 88
Figure 28. NIC Configuration Screen Field ................................................................................ 91
Figure 29. Serial Port Configuration Screen .............................................................................. 97
Figure 30. USB Configuration Screen ....................................................................................... 98
Figure 31. System Acoustic and Performance Configuration..................................................... 99
Figure 32. Security Screen ...................................................................................................... 102
Figure 33. Server Management Screen .................................................................................. 104
Figure 34. Console Redirection Screen ................................................................................... 107
Figure 35. System Information Screen .................................................................................... 108
Figure 36. BMC LAN Configuration Screen ............................................................................. 110
Figure 37. Boot Options Screen .............................................................................................. 112
Figure 38. Hard Disk Order Screen ......................................................................................... 114
Figure 39. Network Device Order Screen ................................................................................ 115
Figure 40. Delete EFI Boot Option Screen .............................................................................. 115
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Figure 41. Boot Manager Screen ............................................................................................ 116
Figure 42. Error Manager Screen ............................................................................................ 117
Figure 43. Exit Screen............................................................................................................. 117
Figure 44. Jumper Blocks (J9C2, J9F2, J6E1, J6E1, J6E1, J6E1) .......................................... 119
Figure 45. System Status LED (A) and ID LED (B) ................................................................. 127
Figure 46. Rear Panel Diagnostic LEDs (Block A) ................................................................... 139
Figure 47. Turn On/Off Timing (Power Supply Signals) ........................................................... 145
Figure 48. Diagnostic LED Placement Diagram ...................................................................... 167
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List of Tables
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List of Tables
Table 1. Intel® Server Board S2400LP Feature Set ..................................................................... 3
Table 2. Intel® Server Board S2400LP Features ......................................................................... 8
Table 3. Mixed Processor Configurations .................................................................................. 11
Table 4. UDIMM Support Guidelines ......................................................................................... 15
Table 5. RDIMM Support Guidelines ......................................................................................... 16
Table 6. LRDIMM Support Guidelines ....................................................................................... 17
Table 7. CPU1 and CPU2 PCIe Connectivity ............................................................................ 21
Table 8. External RJ45 NIC Port LED Definition........................................................................ 23
Table 9. Intel® Server Board S2400LP SATA/SAS port ............................................................. 25
Table 10. Intel® RAID C600 Storage Upgrade Key Options for S2400LP .................................. 25
Table 11. NIC Status LED ......................................................................................................... 30
Table 12. Network Port Configuration ....................................................................................... 32
Table 13. Video Modes ............................................................................................................. 36
Table 14. Video mode ............................................................................................................... 36
Table 15. ACPI Power States.................................................................................................... 41
Table 16. Standard Channel Assignments ................................................................................ 43
Table 17. Default User Values .................................................................................................. 44
Table 18. Channel/Media-specific minimum number of sessions .............................................. 45
Table 19. BMC Beep Codes...................................................................................................... 49
Table 20. NMI Signal Generation and Event Logging ................................................................ 50
Table 21. Basic and Advanced Management Features ............................................................. 50
Table 22. Management features and Benefits ........................................................................... 51
Table 23. Fan Profile Mapping .................................................................................................. 57
Table 24. POST HotKeys Recognized ...................................................................................... 66
Table 25. BIOS Setup Page Layout ........................................................................................... 68
Table 26. BIOS Setup: Keyboard Command Bar ...................................................................... 69
Table 27. Screen Map ............................................................................................................... 71
Table 28. Setup Utility – Main Screen Fields ............................................................................. 73
Table 29. Setup Utility – Advanced Screen Display Fields ........................................................ 75
Table 30. Setup Utility — Processor Configuration Screen Fields ............................................. 76
Table 31. Setup Utility – Power and Performance Configuration Screen Fields......................... 81
Table 32. Power/Performance Profiles ...................................................................................... 81
Table 33. Setup Utility – Memory Configuration Screen Fields .................................................. 84
Table 34. Setup Utility – Memory RAS and Performance Configuration Fields .......................... 86
Table 35. Mass Storage Controller Configuration Fields ........................................................... 87
Table 36. Setup Utility – PCI Configuration Screen Fields ......................................................... 89
Table 37. Setup Utility - NIC Configuration Screen Field ........................................................... 91
Table 38. Setup Utility – Serial Ports Configuration Screen Fields ............................................ 97
Table 39. Setup Utility – USB Controller Configuration Screen Fields ....................................... 98
Table 40. Setup Utility – System Acoustic and Performance Configuration Screen Fields ...... 100
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Table 41. Setup Utility – Security Configuration Screen Fields ................................................ 103
Table 42. Setup Utility – Server Management Configuration Screen Fields............................. 104
Table 43. Setup Utility – Console Redirection Configuration Fields ......................................... 107
Table 44. Setup Utility – Server Management System Information Fields ............................... 108
Table 45. Setup Utility — BMC configuration Screen Fields .................................................... 111
Table 46. Setup Utility – Boot Options Screen Fields .............................................................. 113
Table 47. Setup Utility — Hard Disk Order Fields.................................................................... 114
Table 48. Setup Utility — Network Device Order Fields .......................................................... 115
Table 49. Setup Utility – Delete Boot Option Fields ................................................................. 115
Table 50. Setup Utility – Boot Manager Screen Fields ............................................................ 116
Table 51. Setup Utility — Error Manager Screen Fields .......................................................... 117
Table 52. Setup Utility — Exit Screen Fields ........................................................................... 118
Table 53. Server Board Jumpers (J9C2, J9F2, J6E1, J6E1, J6E1, J6E1) ............................... 119
Table 54. Force BMC Update Jumper ..................................................................................... 120
Table 55. BIOS Recovery Mode Jumper ................................................................................. 121
Table 56. Password Clear Jumper .......................................................................................... 122
Table 57. Force ME Update Jumper ....................................................................................... 122
Table 58. Reset BIOS Jumper ................................................................................................ 123
Table 59. Main Power Supply Connector 6-pin 2x3 Connector (J1D1 and J1A2) .................... 124
Table 60. Intel® RMM4 Lite Connector Pin-out (J7F2) ............................................................. 124
Table 61. Bridge Board Connector (J6A1)............................................................................... 124
Table 62. Power LED Indicator States .................................................................................... 126
Table 63. System Status LED ................................................................................................. 128
Table 64. Chassis ID LED Indicator States ............................................................................. 129
Table 65. PCI Express* x16 Riser Slot 1 Connector (J8F1)..................................................... 129
Table 66. PCI Express* x8 Riser Slot 2 Connector (J8A1) ...................................................... 131
Table 67. PCI Express* Riser ID Assignment .......................................................................... 133
Table 68. VGA External Video Connector (J9D1).................................................................... 133
Table 69. RJ-45 10/100/1000 NIC Connector Pin-out (JA9F1, JA9E1) ................................... 134
Table 70. SATA DOM Connector ............................................................................................ 134
Table 71. Storage Upgrade Key Connector (J9F1) ................................................................. 135
Table 72. Internal 9-pin Serial A (COM1) (J8F5)...................................................................... 135
Table 73. External USB port Connector (J9C1) ....................................................................... 135
Table 74. QSFP Pin Definition ................................................................................................ 135
Table 75. Baseboard Fan Connector (J1A1) ........................................................................... 136
Table 76. Network link/activity LED ......................................................................................... 138
Table 77. InfiniBand* link/activity LED ..................................................................................... 138
Table 78. Server Board Design Specifications ........................................................................ 140
Table 79. Power Supply DC Power Input Connector Pinout .................................................... 141
Table 80. Minimum Load Ratings ............................................................................................ 141
Table 81. Voltage Regulation Limits ........................................................................................ 142
Table 82. Transient Load Requirements ................................................................................. 142
Table 83. Capacitive Loading Conditions ................................................................................ 142
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Table 84. Ripples and Noise ................................................................................................... 143
Table 85. Timing Requirements .............................................................................................. 144
Table 86. BMC Sensor Table .................................................................................................. 149
Table 87. BIOS Sensor and SEL Data .................................................................................... 160
Table 88. POST Progress Code LED Example ....................................................................... 168
Table 89. Diagnostic LED POST Code Decoder ..................................................................... 169
Table 90. POST Error Messages and Handling....................................................................... 174
Table 91. Glossary .................................................................................................................. 178
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Intel®Server Boards S2400LP TPS
1.
Introduction
Introduction
The Intel® Server Board S2400LP is a half width, dual sockets server board using the Intel®
Xeon® Processor E5-2400 series processor, in combination with Intel® C600 chipset to provide
an outstanding feature set for high performance and high density computing.
This Technical Product Specification (TPS) provides board-specific information detailing the
features, functionality, and high-level architecture of the Intel® Server Boards S2400LP.
For design-level information of specific components or subsystems relevant to the server boards
described in this document, additional documents can be obtained through Intel®. The following
table lists documents used as reference to compile much of the data provided here. Some of the
listed documents are not publically available and must be ordered through your local Intel®
representative.
1.1
Section Outline
This document is divided into the following chapters:
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Revision 2.0
Chapter 1 – Introduction
Chapter 2 – Server Board Overview
Chapter 3 – Product Architecture Overview
Chapter 4 – Platform Management Functional Overview
Chapter 5 – BIOS Setup Interface
Chapter 6 – Configuration Jumpers
Chapter 7 – Connector/Header Locations and Pin-out
Chapter 8 – Intel® Light-Guided Diagnostics
Chapter 9 – Environmental Limits Specification
Chapter 10 – Power Supply Specification Guidelines
Appendix A – Integration and Usage Tips
Appendix B – Integrated BMC Sensor Tables
Appendix C – BIOS Sensors and SEL Data
Appendix D – POST Code LED Decoder
Appendix E – Video POST Code Errors
Glossary
Reference Documents
Intel order number G52803-002
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Introduction
1.2
Intel®Server Boards S2400LP TPS
Server Board Use Disclaimer
Intel Corporation server boards contain a number of high-density VLSI and power delivery
components that need adequate airflow to cool. Intel ensures through its own chassis
development and testing that when Intel server building blocks are used together, the fully
integrated system will meet the intended thermal requirements of these components. It is the
responsibility of the system integrator who chooses not to use Intel developed server building
blocks to consult vendor datasheets and operating parameters to determine the amount of air
flow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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Intel®Server Boards S2400LP TPS
2.
Server Board Overview
Server Board Overview
The Intel® Server Board S2400LP is a monolithic printed circuit board (PCB) with features
designed to support the high performance and high density computing markets. This server
board is designed to support the Intel® Xeon® processor E5-2400 product family. Previous
generation Intel® Xeon® processors are not supported. Many of the features and functions of the
server board family are common. A board will be identified by name when a described feature or
function is unique to it.
®
Figure 1. Intel Server Board S2400LP (Base SKU)
There are 3 board SKUs based on different hardware configuration:
 S2400LP: Base SKU
 S2400LPQ: Base SKU with InfiniBand* CX3 QDR populated
 S2400LPF: Base SKU with InfiniBand* CX3 FDR populated
The following table provides a high-level product feature list.
®
Table 1. Intel Server Board S2400LP Feature Set
Feature
Processors
Memory
Chipset
External I/O
Connections
Revision 2.0
Description
®
®
®
®
Support for one or two Intel Xeon processor E5-2400 or Intel Xeon processor E5-2400
v2 processor series processor(s)
®
®
 Up to 8.0 GT/s Intel QuickPath Interconnect (Intel QPI)
 LGA 1356 Socket B2
 Thermal Design Power (TDP) up to 95 watt
 12 DIMM slots total across six memory channels
 Unbuffered DDR3 and registered DDR3 with ECC DIMMs
 Memory DDR3 data transfer rates of 800/1066/1333/1600 MT/s
 Load Reduced DDR3 DIMM
 DDR3 standard I/O voltage of 1.5V(All Speed) and DDR3 Low Voltage of 1.35V(1333
MT/s or below)
®
Intel C600-A Platform Controller Hub(PCH) with support for optional Storage Upgrade Key
 DB-15 Video connectors
 Two RJ-45 Network Interface for 10/100/1000 LAN
 One stacked two port USB 2.0 (Port 0/1) connectors
 One InfiniBand* QDR QSFP port (SKU: S2400LPQ)
 One InfiniBand* FDR QSFP port (SKU: S2400LPF)
Intel order number G52803-002
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Server Board Overview
Feature
Internal I/O
connectors/headers
Power Connections
System Fan Support
Add-in Riser Support
Video
Hard Drive Support
RAID Support
Server Management
4
Intel®Server Boards S2400LP TPS
Description
Bridge Slot to extend board I/O
- SCU0 (Four SAS 3Gb/s ports) for backplane
- Front Control panel signals
- One SATA(Port 0) 6Gb/s port for DOM
 One 2x7pin header for system FAN module
 One DH-10 serial Port A connector
®
 One 2x4 pin header for Intel RMM4 Lite
 One 1x4 pin header for Storage Upgrade Key
 Two sets of 2x3 pin connector
 Three sets of dual rotor fan
 Two PCIe Gen III riser slots,
- Riser slot 1 support PCIe Gen III x16 Riser(PCIe Gen III x16 electrical bus from
CPU1 for S2400LP; PCIe Gen III x8 electrical bus from CPU1 for S2400LPQ
and S2400LPF)
- Riser slot 2 support PCIe Gen III x16 Riser(PCIe Gen III x8 electrical bus from
CPU1; PCIe Gen II x8 electrical bus from CPU1 for Intel®rIOM)
 One Bridge Slot for Board I/O expansion
 Integrated 2D Video Graphics controller
 128 MB DDR2 Memory
One SATA 6Gbps port (for DOM) and Four SATA/SAS ports (SCU0) are supported through
bridge board
®
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Intel RSTe RAID 0/1/10/5 for SATA mode
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LSI SW RAID 0/1/10/5
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Onboard ServerEngines* LLC Pilot III* Controller
®
Support for Intel Remote Management Module 4 Lite solutions
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Intel Light-Guided Diagnostics on field replaceable units
®
Support for Intel System Management Software
®
Support for Intel Intelligent Power Node Manager (Need PMBus*-compliant power
supply)
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
2.1
Server Board Overview
Server Board Connector and Component Layout
The following illustration provides a general overview of the server board, identifying key feature
and component locations. The majority of the items identified are common in the Intel® Server
Board S2400LP family. The accompanying table will identify variations when present.
A
CPU2 VR
I
USB x 2
Q
Storage Upgrade
Key
Y
ME Firmware Update
B
CPU1 DIMM(6
Total)
J
Status and ID LED
R
BIOS Recovery
Z
Reset BIOS
Configuration
C
Bridge Board
Connector
K
BMC
S
Serial Port A
AA
CPU1
D
PCH C600-A
L
VGA Out
T
TPM
AB
CPU1 VR
E
Riser Slot2 with
PCIe Gen3x16( with
x8 Electrical)
M
Dual Port 1Gbe
NIC
U
RMM4 Lite
AC
CPU2 DIMM(6 Total)
F
Infiniband* QDR
N
NIC Port 2
V
CMOS Battery
AD
2x3 PWR Connector
G
POST and QSFP
LED
O
NIC Port 1
W
SATA DOM
AE
CPU2
H
QSFP
P
Riser Slot 1 with
PCIe Gen3x16
(with x8 Electical)
X
Clear Password
AF
2x7 Fan Control
Connector
®
Figure 2. Intel Server Board S2400LP Components
2.1.1 Board Rear Connector Placement
The Intel® Server Board S2400LP has the following board rear connector placement:
Revision 2.0
Intel order number G52803-002
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Server Board Overview
Intel®Server Boards S2400LP TPS
A
Description
NIC port 1 (RJ45)
E
Status LED
Description
B
NIC port 2 (RJ45)
F
Dual port USB connector
C
DB15 video out
G
QSFP Connector
D
ID LED
H
InfiniBand* status and diagnostic
LED
Figure 3. Rear Panel Connector Placement
2.2
Server Board Mechanical Drawings
The following figures are mechanical drawings for the Intel® Server Board S2400LP.
®
Figure 4. Intel Server Board S2400LP – Mounting Holes Locations
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Intel®Server Boards S2400LP TPS
Server Board Overview
®
Figure 5. Intel Server Boards S2400LP – Major Connector Pin-1 Locations
Revision 2.0
Intel order number G52803-002
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Product Architecture Overview
3.
Intel®Server Boards S2400LP TPS
Product Architecture Overview
The Intel® Server Board S2400LP is a purpose build, rack-optimized server board used in a
high-density rack system. It is designed around the integrated features and functions of the
Intel® Xeon® processor E5-2400 product family , the Intel® C600-A chipset, and other supporting
components including the Integrated BMC, the Intel® I350 network interface controller and the
Mellanox* ConnectX®-3 InfiniBand* (depending on the board SKU).
The reduced board size allows four boards reside in a standard 2U Intel® Server Chassis
H2000LP for high-performance and high-density computing.
3.1
High Level Product Features
®
Table 2. Intel Server Board S2400LP Features
Board
8
S2400LP
S2400LPQ/S2400LPF
Form Factor
6.8"(172.7mm) x 16.6"(421.6mm)
CPU Socket
Socket B2, LGA1356
Chipset
Intel C600 Chipset PCH
Memory
12 DDR3 RDIMMs/LR-DIMMs/UDIMMs with ECC
Slots
Ethernet
2 PCI Express* Gen3 x16
2 PCI Express* Gen3 x16
connectors(one is x16 Electrical, one connectors(both are x8 Electrical)
is x8 Electrical)
One system bridge board connector
One system bridge board connector
®
Dual GbE, Intel I350 Gigabit Ethernet
InfiniBand*
N/A
Storage
One SATA III port (6Gb/s) for DOM
SAS
SCU0 through bridge board slot
SW RAID
LSI SW RAID 0,1,5,10 or Intel RSTe RAID 0,1,5 for SATA mode
Processor
Support
95 W maximum
Video
Integrated in BMC
iSMS
Integrated BMC w/IPMI 2.0 support
Chassis
H2000 family
Power Supply
12 V and 5 VS/B PMBus*
®
Single port of InfiniBand* QDR/FDR
®
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Product Architecture Overview
®
Figure 6. Intel Server Boards S2400LP Functional Block Diagram
3.2
Processor Support
The server board includes two Socket-B2 (LGA1356) processor sockets and can support one or
two of the Intel® Xeon® processor E5-2400 or Intel® Xeon® processor E5-2400 v2 product family
with a Thermal Design Power (TDP) of up to 95W processor.
Note: Previous generation Intel® Xeon® processors are NOT supported on the Intel® server
boards described in this document.
For a complete updated list of supported processors, see:
http://www.intel.com/p/en_US/support/highlights/server/S2400LP
On the Support tab, look for Compatibility and then Supported Processor List.
3.2.1 Processor Socket Assembly
Each processor socket of the server board is pre-assembled with an Independent Latching
Mechanism (ILM) and Back Plate which allow for secure placement of the processor and
processor heat to the server board.
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Product Architecture Overview
Intel®Server Boards S2400LP TPS
The illustration below identifies each sub-assembly component.
Figure 7. Processor Socket Assembly
3.2.2 Processor Population Rules
Note: Although the server board does support dual-processor configurations consisting of
different processors that meet the defined criteria below, Intel does not perform validation
testing of this configuration. For optimal system performance in dual-processor configurations,
Intel recommends that identical processors be installed.
When using a single processor configuration, the processor must be installed into the processor
socket labeled “CPU_1”.
When two processors are installed, the following population rules apply:
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Both processors must be of the same processor family.
Both processors must have the same cache size.
Processors with different speeds can be mixed in a system, given the prior rules are met.
If this condition is detected, all processor speeds are set to the lowest common
denominator (highest common speed) and an error is reported.
Processor stepping within a common processor family can be mixed as long as it is
listed in the processor specification updates published by Intel Corporation.
The following table describes mixed processor conditions and recommended actions for all
Intel® server boards and Intel server systems designed around the Intel® Xeon® processor E5-
10
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Product Architecture Overview
2400 product family and Intel® C600 chipset product family architecture. The errors fall into one
of the following two categories:
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
Fatal: If the system can boot, it goes directly to the Error Manager screen in BIOS Setup,
regardless of whether the “Post Error Pause” setup option is enabled or disabled.
Major: If the “POST Error Pause” option in BIOS Setup is disabled, the system will log
the error to the BIOS Setup Utility Error Manager and then continue to boot. No POST
error message is given. If the “POST Error Pause” option in BIOS Setup is enabled, the
error is logged and the system goes directly to the Error Manager in BIOS Setup.
Table 3. Mixed Processor Configurations
Error
Processor family not
identical
Severity
Fatal
System Action
The BIOS detects the error condition and responds as follows:
 Logs the error into the system event log (SEL).
 Alerts the Integrated BMC of the configuration error with an IPMI
command.
 Does not disable the processor.
 Displays “0194: Processor family mismatch detected”
message in the error manager.
 Halts the system.
Processor cache not
identical
Fatal
The BIOS detects the error condition and responds as follows:
 Logs the error into the SEL.
 Alerts the Integrated BMC of the configuration error with an IPMI
command.
 Does not disable the processor.
 Displays “0192: Cache size mismatch detected” message in
the error manager.
 Halts the system.
Processor frequency (speed)
not identical
Major
The BIOS detects the error condition and responds as follows:
 Adjusts all processor frequencies to lowest common
denominator.
 Continues to boot the system successfully.
If the frequencies for all processors cannot be adjusted to be the
same, then the BIOS:
 Logs the error into the SEL.
 Displays “0197: Processor speeds mismatched” message in
the error manager.
 Halts the system.
Processor microcode
missing
Fatal
The BIOS detects the error condition and responds as follows:
 Logs the error into the SEL.
 Alerts the Integrated BMC of the configuration error with an IPMI
command.
 Does not disable processor.
 Displays “816x: Processor 0x unable to apply microcode
update” message in the error manager.
 Pauses the system for user intervention.
Revision 2.0
Intel order number G52803-002
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Product Architecture Overview
Error
®
Processor Intel QuickPath
Interconnect speeds not
identical
Intel®Server Boards S2400LP TPS
Severity
Halt
System Action
The BIOS detects the error condition and responds as follows:
 Logs the error into the system event log (SEL).
 Alerts the Integrated BMC of the configuration error with an IPMI
command.
 Does not disable the processor.
 Displays “0195: Processor Front Side Bus speed mismatch
detected” message in the error manager.
 Halts the system.
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Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
3.3
Product Architecture Overview
Processor Functions Overview
With the release of the Intel® Xeon® processor E5-2400 product family, several key system
components, including the CPU, Integrated Memory Controller (IMC), and Integrated IO Module
(IIO), have been combined into a single processor package and feature per socket; One Intel®
QuickPath Interconnect point-to-point links capable of up to 8.0 GT/s, up to 24 lanes of Gen 3
PCI Express* links capable of 8.0 GT/s, and 4 lanes of DMI2/PCI Express* Gen 2 interface with
a peak transfer rate of 5.0 GT/s. The processor supports up to 46 bits of physical address space
and 48-bit of virtual address space.
The following sections will provide an overview of the key processor features and functions that
help to define the performance and architecture of the server board.
Processor Feature Details:
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Up to 8 execution cores (Intel® Xeon® processor E5-2400 product family)
Up to 10 execution cores (Intel® Xeon® processor E5-2400 v2 product family)
®
Each core supports two threads (Intel Hyper-Threading Technology)
46-bit physical addressing and 48-bit virtual addressing
1 GB large page support for server applications
A 32-KB instruction and 32-KB data first-level cache (L1) for each core
A 256-KB shared instruction/data mid-level (L2) cache for each core
Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
cache (LLC), shared among all cores
Supported Technologies:
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Intel® Virtualization Technology (Intel® VT)
Intel® Virtualization Technology for Directed I/O (Intel® VT-d)
Intel® Virtualization Technology “Sandy Bridge” Processor Extensions
Intel® Trusted Execution Technology (Intel® TXT)
Intel® 64 Architecture
Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1)
Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2)
Intel® Advanced Vector Extensions (Intel® AVX)
Intel® Hyper-Threading Technology
Execute Disable Bit
Intel® Turbo Boost Technology
Intel® Intelligent Power Technology
Enhanced Intel® SpeedStep Technology
3.3.1 Intel®QuickPath Interconnect
The Intel® QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
latency. The Intel® QuickPath Interconnect has an efficient architecture allowing more
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Product Architecture Overview
Intel®Server Boards S2400LP TPS
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built
into the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
The Intel® QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.3.2 Integrated Memory Controller (IMC) and Memory Subsystem
Figure 8. Processor with IMC Functional Block Diagram
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14
Unbuffered DDR3 and registered DDR3 DIMMs
LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher
capacity memory subsystem.
Independent channel mode or lockstep mode
Data burst length of eight cycles for all memory organization modes
Memory DDR3 data transfer rates of 800, 1066, 1333, and 1600 MT/s
64-bit wide channels plus 8-bits of ECC support for each channel
DDR3 standard I/O Voltage of 1.5 V for all speed
DDR3 Low Voltage of 1.35 V for 1333MT/s or below
1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Product Architecture Overview
UDIMM DDR3 – SR x8 and x16 data widths, DR x8 data width
RDIMM DDR3 – SR,DR, and QR – x4 and x8 data widths
LRDIMM DDR3 – QR x4 and x8 data widths with direct map or with rank
multiplication
Up to 8 ranks supported per memory channel, 1, 2 or 4 ranks per DIMM
Open with adaptive idle page close timer or closed page policy
Per channel memory test and initialization engine can initialize DRAM to all logical zeros
with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS)
Minimum memory configuration: independent channel support with 1 DIMM populated
Integrated dual SMBus* master controllers
Command launch modes of 1n/2n
RAS Support:
o Rank Level Sparing and Device Tagging
o Demand and Patrol Scrubbing
o DRAM Single Device Data Correction (SDDC) for any single x4 or x8 DRAM
device. Independent channel mode supports x4 SDDC. x8 SDDC requires
lockstep mode
o Lockstep mode where channels 0 and 1 and channels 2 and 3 are operated in
lockstep mode
o Data scrambling with address to ease detection of write errors to an incorrect
address.
o Error reporting through Machine Check Architecture
o Read Retry during CRC error handling checks by iMC
o Channel mirroring within a socket
- CPU1 Channel Mirror Pairs B and C
- CPU2 Channel Mirror Pairs E and F
o Error Containment Recovery
Improved Thermal Throttling with dynamic Closed Loop Thermal Throttling (CLTT)
Memory thermal monitoring support for DIMM temperature
o
o
o
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3.3.2.1 Supported Memory
Supported and Validated
Supported but not Validate
Table 4. UDIMM Support Guidelines
Ranks Per
DIMM and
Data Width
SRx8 NonECC
Revision 2.0
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3
Memory Capacity Per DIMM1
1GB
2GB
4GB
1 Slot per Channel
1DPC
1.35V
1.5V
n/a
1066, 1333
Intel order number G52803-002
2 Slots per Channel
1DPC
1.35V
n/a
2DPC
1.5V
1066,
1333
1.35V
1.5V
n/a
1066
15
Product Architecture Overview
Ranks Per
DIMM and
Data Width
DRx8 NonECC
SRx16 NonECC
Intel®Server Boards S2400LP TPS
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2,3
Memory Capacity Per DIMM1
1 Slot per Channel
1DPC
1.35V
1.5V
2 Slots per Channel
1DPC
1.35V
2GB
4GB
8GB
n/a
1066, 1333
n/a
512MB
1GB
2GB
n/a
1066, 1333
n/a
SRx8 ECC
1GB
2GB
4GB
DRx8 ECC
2GB
4GB
8GB
1066,
1333
1066,
1333
1066, 1333
1066, 1333
2DPC
1.5V
1066,
1333
1066,
1333
1066,
1333
1066,
1333
1066,
1333
1066,
1333
1.35V
1.5V
n/a
1066
n/a
1066
1066
1066
1066
1066
Notes:
1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel
2. Command Address Timing is 1N for 1DPC and 2N for 2DPC
3. No Support for 3DPC when using UDIMMs
Table 5. RDIMM Support Guidelines
Ranks Per
DIMM and Data
Width
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)2
Memory Capacity Per DIMM1
1 Slot per Channel
2 Slots per Channel
1DPC
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
1.35V
SRx8
1GB
2GB
4GB
1066,
1333
1066, 1333,
1600
1066,
1333
1066,
1333
1066,
1033
DRx8
2GB
4GB
8GB
1066,
1333
1066, 1333,
1600
1066,
1333
1066,
1333
1066,
1033
SRx4
2GB
4GB
8GB
1066,
1333
1066, 1333,
1600
1066,
1333
1066,
1333
1066,
1033
DRx4
4GB
8GB
16GB
1066,
1333
1066, 1333
1600
1066,
1333
1066,
1333
1066,
1033
QRx4
8GB
16GB
32GB
800
800
800
QRx8
4GB
8GB
16GB
800
800
800
800
800
1.5V
1066,
1333,
1600
1066,
1333,
1600
1066,
1333,
1600
1066,
1333,
1600
800
800
800
800
Notes:
1. Supported DRAM Densities are 1Gb, 2Gb, and 4Gb. Only 2Gb and 4Gb are validated by Intel
2. Command Address Timing is 1N
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Product Architecture Overview
Table 6. LRDIMM Support Guidelines
Ranks Per
DIMM and
Data Width1
QRx4
(DDP)6
QRx8
(P)6
Notes:
1.
2.
3.
4.
5.
6.
Memory Capacity
Per DIMM2
16GB
32GB
8GB
16GB
Speed (MT/s) and Voltage Validated by
Slot per Channel (SPC) and DIMM Per Channel (DPC)3,4,5
1 Slot per Channel
2 Slots per Channel
1DPC
1DPC
2DPC
1.35V
1.5V
1.35V
1.5V
1.35V
1.5V
1066
1066,
1066
1066, 1333
800
1066
1333
1333
1066
1066,
1066
1066, 1333
800
1066
1333
1333
Physical Rank is used to calculate DIMM Capacity
Supported and validated DRAM Densities are 2Gb and 4Gb
Command address timing is 1N
The speeds are estimated targets and will be verified through simulation
For 3SPC/3DPC – Rank Multiplication (RM) >=2
DDP – Dual Die Package DRAM stacking. P – Planar monolithic DRAM Dies.
3.3.2.2 Memory Population Rules
Note: Although mixed DIMM configurations are supported, Intel only performs platform
validation on systems that are configured with identical DIMMs installed
Each processor provides three channels of memory, each capable of supporting up to two
DIMMs.

DIMMs are organized into physical slots on DDR3 memory channels that belong to
processor sockets.

The memory channels from processor socket 1 are identified as Channel A, B and C.
The memory channels from processor socket 2 are identified as Channel D, E and F
The silk screened DIMM slot identifiers on the board provide information about the
channel, and therefore the processor to which they belong. For example, DIMM_A1 is
the first slot on Channel A on processor 1; DIMM_D1 is the first DIMM socket on
Channel D on processor 2.




The memory slots associated with a given processor are unavailable if the
corresponding processor socket is not populated.
A processor may be installed without populating the associated memory slots provided a
second processor is installed with associated memory. In this case, the memory is
shared by the processors. However, the platform suffers performance degradation and
latency due to the remote memory.
Processor sockets are self-contained and autonomous. However, all memory subsystem
support (such as Memory RAS, Error Management,) in the BIOS setup are applied
commonly across processor sockets.
On the Intel® Server Board S2400LP, a total of 12 DIMM slots is provided (two CPUs – 3
Channels/CPU, 2 DIMMs/Channel). The nomenclature for DIMM sockets is detailed in the
following figure:
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®
Figure 9. Intel Server Board S2400LP DIMM Slot Layout
The following are generic DIMM population requirements that generally apply to both the Intel®
Server Board S2400LP









All DIMMs must be DDR3 DIMMs
Unbuffered DIMMs can be ECC or non-ECC.
Mixing of Registered and Unbuffered DIMMs is not allowed per platform.
Mixing of LRDIMM with any other DIMM type is not allowed per platform.
Mixing of DDR3 voltages is not validated within a socket or across sockets by Intel. If
1.35V (DDR3L) and 1.50V (DDR3) DIMMs are mixed, the DIMMs will run at 1.50V.
Mixing of DDR3 operating frequencies is not validated within a socket or across sockets
by Intel. If DIMMs with different frequencies are mixed, all DIMMs will run at the common
lowest frequency.
Quad rank RDIMMs are supported but not validated by Intel.
A maximum of 8 logical ranks (ranks seen by the host) per channel is allowed.
Mixing of ECC and non-ECC DIMMs is not allowed per platform.
3.3.2.3 Publishing System Memory

The BIOS displays the “Total Memory” of the system during POST if Display Logo is
disabled in the BIOS setup. This is the total size of memory discovered by the BIOS
during POST, and is the sum of the individual sizes of installed DDR3 DIMMs in the
system.

The BIOS displays the “Effective Memory” of the system in the BIOS setup. The term
Effective Memory refers to the total size of all DDR3 DIMMs that are active (not disabled)
and not used as redundant units.

The BIOS provides the total memory of the system in the main page of the BIOS setup.
This total is the same as the amount described by the first bullet above.

If Display Logo is disabled, the BIOS displays the total system memory on the diagnostic
screen at the end of POST. This total is the same as the amount described by the first
bullet above.
3.3.2.4 RAS Features
The server board supports the following memory RAS modes:
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
Independent Channel Mode
 Rank Sparing Mode
 Mirrored Channel Mode
 Lockstep Channel Mode
Regardless of RAS mode, the requirements for populating within a channel given in the section
3.3.2.2 must be met at all times. Note that support of RAS modes that require matching DIMM
population between channels (Mirrored and Lockstep) require that ECC DIMMs be populated.
Independent Channel Mode is the only mode that supports non-ECC DIMMs in addition to ECC
DIMMs.
For RAS modes that require matching populations, the same slot positions across channels
must hold the same DIMM type with regards to size and organization. DIMM timings do not
have to match but timings will be set to support all DIMMs populated (that is, DIMMs with slower
timings will force faster DIMMs to the slower common timing modes).
Independent Channel Mode
Channels can be populated in any order in Independent Channel Mode. All four channels may
be populated in any order and have no matching requirements. All channels must run at the
same interface frequency but individual channels may run at different DIMM timings (RAS
latency, CAS Latency, and so forth).
Rank Sparing Mode
In Rank Sparing Mode, one rank is a spare of the other ranks on the same channel. The spare
rank is held in reserve and is not available as system memory. The spare rank must have
identical or larger memory capacity than all the other ranks (sparing source ranks) on the same
channel. After sparing, the sparing source rank will be lost.
Mirrored Channel Mode
In Mirrored Channel Mode, the memory contents are mirrored between Channel B and Channel
C and also between Channel E and Channel F. As a result of the mirroring, the total physical
memory available to the system is half of what is populated. Mirrored Channel Mode requires
that Channel B and Channel C, and Channel E and Channel F must be populated identically with
regards to size and organization. DIMM slot populations within a channel do not have to be
identical but the same DIMM slot location across Channel B and Channel C and across Channel
E and Channel F must be populated the same.
Lockstep Channel Mode
In Lockstep Channel Mode, each memory access is a 128-bit data access that spans Channel B
and Channel C, and Channel E and Channel F. Lockstep Channel mode is the only RAS mode
that allows SDDC for x8 devices. Lockstep Channel Mode requires that Channel B and Channel
C, and Channel E and Channel F must be populated identically with regards to size and
organization. DIMM slot populations within a channel do not have to be identical but the same
DIMM slot location across Channel B and Channel C and across Channel E and Channel F must
be populated the same.
3.3.3 Processor Integrated I/O Module (IIO)
The processor’s integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
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
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PCI Express* Interfaces: The integrated I/O module incorporates the PCI Express*
interface and supports up to 24 lanes of PCI Express*. Following are key attributes of
the PCI Express interface:
o Gen3 speed at 8 GT/s (no 8b/10b encoding)
o X16 interface bifurcated down to two x8 or four x4 (or combinations)
o X8 interface bifurcated down to two x4
DMI2 Interface to the PCH: The platform requires an interface to the legacy
Southbridge (PCH) which provides basic, legacy functions required for the server
platform and operating systems. Since only one PCH is required and allowed for the
system, any sockets which do not connect to PCH would use this port as a standard x4
PCI Express* 2.0 interface.
Integrated IOAPIC: Provides support for PCI Express* devices implementing legacy
interrupt messages without interrupt sharing
Non Transparent Bridge: PCI Express* non-transparent bridge (NTB) acts as a
gateway that enables high performance, low overhead communication between two
intelligent subsystems; the local and the remote subsystems. The NTB allows a local
processor to independently configure and control the local subsystem, provides isolation
of the local host memory domain from the remote host memory domain while enabling
status and data exchange between the two domains.
Intel® QuickData Technology: Used for efficient, high bandwidth data movement
between two locations in memory or from memory to I/O
The following sub-sections will describe the server board features that are directly supported by
the processor IIO module. These include the Riser Card Slots, Network Interface, and
connectors for the optional I/O modules and SAS Module. Features and functions of the Intel
C600 Series chipset will be described in its own dedicated section.
3.3.3.1 Riser Card Support
The server board provides two Riser card slots identified by Riser Slot 1 and Riser Slot 2. The
PCIe signals for each riser card slot are supported by CPU1. All 24 lanes routed to Riser Slot 1
and Riser Slot 2 is from CPU 1.
Following is the scope of I/O connection from processors on Intel® Server Board S2400LP.
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Figure 10. PCI Express Lane Distribution Scheme
Table 7. CPU1 and CPU2 PCIe Connectivity
CPU
CPU1
Port
DMI2
IOU
IOU2
X4
Width
Connection
PCH (lane reversal, no polarity inversion )
CPU1
PE3
IOU1
X8
QDR/FDR InfiniBand*
CPU1
PE3
IOU1
X16 on base
sku, x8 on IB
sku
Riser1
CPU1
PE1
IOU2
X8
Riser2(x8 for IOM on Riser)
CPU2
DMI2
IOU2
X4
Unused
CPU2
PE1
IOU2
X8
Unused
CPU2
PE3
IOU1
X16
Unused
Note: All Riser slots are defined sepcially for dedicated risers only. Plug in normal PCIe riser or
PCIe add-in card directly will casue danger and may burn out the add-in riser or card.
3.3.3.2 Riser Types
The riser connector will be a standard 164-pin x16 connector but pined out differently to create
enough unused pins to route the RGMII interface through Riser 2. It will have a x8 PCIe Gen 3
electrical interface. The placement of the rear IO connectors and layout of the components on
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the board must be made to support MD2, low profile card in the Riser1 and a rIOM mounted on
a riser carrier for Riser2.
To support GPU boards, each riser will need to provide 66w of 12V power as well as 10W of
3.3V power in the case of 2x8 boards being hosted in customized chassis. These riser would
need to generate 20W of power 3.3V, the number of 12amp pins on the riser have increased to
accommodate this.
Supported 1U riser cards include:

1U Riser for slot 1 with one PCIe slot – x16 signals(x8 signals for InfiniBand* SKU)
routed to a x16 PCIe Slot
Figure 11. PCIe Riser for Slot 1

1U Riser for Slot 2 with one PCIe slot – 1 sets of x8 signals routed to a x16 PCIe Slot ( 8
lanes for rIOM Carrier).
Figure 12. PCIe Riser for Slot 2
3.3.3.3 Network Interface
Network connectivity from processor is provided by means of an onboard Mellanox* ConnectX®
3 InfiniBand* Controller on board SKU S2400LPQ and S2400LPF, providing one
SDR/DDR/QDR/FDR InifiniBand* port in a QSFP interface. The Controller is supported by
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implementing x8 PCIe Gen3 signals from the IIO module of the CPU 1 processor. The on board
Intel® i350 Ethernet controller provide 2 10/100/1000Gbps Ethernet ports in 2 RJ45 ports.
Table 8. External RJ45 NIC Port LED Definition

LED Color
Green/Amber (Right)

Green (Left)





LED State
Off
Amber
Green
On
Blinking





NIC State
10 Mbps
100 Mbps
1000 Mbps
Active Connection
Transmit/Receive activity
3.3.3.4 I/O Module Support
To broaden the standard on-board feature set, the server board supports the option of adding a
single I/O module providing external ports for a variety of networking interfaces. The I/O module
attaches to a high density 80-pin connector of I/O module carrier on the Riser 2. Refer to Intel®
Server System H2000LP family Technical Product Specification (Intel Order Number G59328)
for more information
3.4
Intel®C600-A/B PCH Functional Overview
The following sub-sections will provide an overview of the key features and functions of the
Intel® C600-A chipset used on the server board. For more comprehensive chipset specific
information, refer to the Intel® C600 Series chipset documents listed in the Reference Document
list in Chapter 1.
®
Figure 13. Intel C600-A/B PCH connection
The Intel® C600-A/B PCH component provides extensive I/O support. Functions and
capabilities include:
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
PCI Express* Base Specification, Revision 2.0 support for up to eight ports with transfers
up to 5 GT/s.

PCI Local Bus Specification, Revision 2.3 support for 33 MHz PCI operations (supports
up to four Req/Gnt pairs).

ACPI Power Management Logic Support, Revision 4.0a

Enhanced DMA controller, interrupt controller, and timer functions

Integrated Serial Attached SCSI host controllers at transfer rate up to 3Gb/s on up to
eight ports.

Integrated Serial ATA host controllers with independent DMA operation on up to
six ports.

USB host interface with two EHCI high-speed USB 2.0 Host controllers and 2 rate
matching hubs provide support for support for up to fourteen USB 2.0 ports.

Integrated 10/100/1000 Gigabit Ethernet MAC with System Defense

System Management Bus (SMBus*) Specification, Version 2.0 with additional support for
I2C* devices

Supports Intel® High Definition Audio

Supports Intel® Rapid Storage Technology (Intel® RST)


Supports Intel® Virtualization Technology for Directed I/O (Intel VT-d)
Supports Intel® Trusted Execution Technology (Intel® TXT)

Low Pin Count (LPC) interface

Firmware Hub (FWH) interface support

Serial Peripheral Interface (SPI) support

Intel® Anti-Theft Technology (Intel® AT)

JTAG Boundary Scan support
3.4.1
PCI Express*
The Intel® C600 PCH provides up to 8 PCI Express* Root Ports, supporting the PCI Express*
Base Specification, Revision 2.0. Each Root Port x1 lane supports up to 5 Gb/s bandwidth in
each direction (10 Gb/s concurrent). PCI Express* Root Ports 1-4 or Ports 5-8 can
independently be configured to support four x1s, two x2s, one x2 and two x1s, or one x4 port
widths.
From PCH on Intel® Server Board S2400LP, PCIe Port8 x1 Gen2 is connected to BMC Gen1
Uplink. Ports 1-4 are connected to Intel® I350 GbE NIC. The remaining PCIe Gen2 interconnect
(Port 5-7, 1 based numbering) are unused.
3.4.2 Universal Serial Bus (USB)
There are fourteen USB 2.0 ports available from Intel® C600 PCH. All ports are high-speed, fullspeed and low-speed capable. A total of 4 USB 2.0 dedicated ports are used by Intel® Server
Board S2400LP. The USB port distribution is as follows:
24

ServerEngines* BMC PILOT III consumes two USB 2.0 ports (one USB1.1 and one
USB2.0).

Two rear USB 2.0 ports.
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Product Architecture Overview
Wake on USB is supported on the rear USB ports for S3.
3.4.3 Serial Attached SCSI(SAS) and Serial ATA(SATA) Controller
The Intel® C600-A/B chipset provides storage support through two integrated controllers: AHCI
and SCU. By default the server board will support up to 5 SATA ports: One single 6Gb/sec
SATA ports routed from the AHCI controller to one white SATA connector labeled “SATA DOM”
on mother board, and four 3Gb/sec SATA ports routed from the SCU to the multi-drive port
connector labeled “SAS/SATA 0-3” (grouped as SCU0).
Note: The Multi- drive port connector lableled “SAS/SATA 4-7” is NOT functional by default and
is only enabled with addition of an Intel® RAID C600 Storage Upgrade Key option supporting 8
SAS/SATA ports.
It supports the Serial ATA Specification, Revision 3.0, and several optional sections of the Serial
ATA II: Extensions to Serial ATA 1.0 Specification, Revision 1.0 (AHCI support is required for
some elements).
Intel® Server Board S2400LP implements five SATA/SAS ports. The implementation is
as follows:
®
Table 9. Intel Server Board S2400LP SATA/SAS port
Port#
Speed
Connector
0
6Gb/s SATA
On Server board
3Gb/s SATA(AHCI only); 3Gb/s
SATA/SAS(non-AHCI)
Bridge Board Slot
0
SCU0
1
2
3
There are two embedded software RAID options using the storage ports configured from the
SCU only:

Intel® Embedded Server RAID Technology 2 (ESRT2) based on LSI* MegaRAID SW
RAID technology supporting SATA RAID levels 0,1,10,5

Intel® Rapid Storage Technology (RSTe) supporting SATA RAID levels 0,1,5,10
The server board is capable of supporting additional chipset embedded SAS and RAID options
from the SCU controller when configured with one of several available Intel® RAID C600
Storage Upgrade Keys. Upgrade keys install onto a 4-pin connector on the server board labeled
“STOR UPG KEY”. The following table identifies available upgrade key options and their
supported features.
®
Table 10. Intel RAID C600 Storage Upgrade Key Options for S2400LP
Intel®RAID C600 Upgrade Key Options
(Intel Product Codes)
Default – No option key installed
N/A
4 Port SATA with Intel ESRT RAID 0,1,10 and Intel
RSTe RAID 0,1,5,10
RKSATA4R5
Black
4 Port SATA with Intel ESRT2 RAID 0,1, 5, 10 and
Revision 2.0
Key Color
Description
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®
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Intel®RAID C600 Upgrade Key Options
(Intel Product Codes)
Key Color
Description
®
Intel RSTe RAID 0,1,5,10
®
RKSATA8
Blue
8 Port SATA with Intel ESRT2 RAID 0,1, 10 and
®
Intel RSTe RAID 0,1,5,10
RKSATA8R5
White
8 Port SATA with Intel ESRT2 RAID 0,1, 5, 10 and
®
Intel RSTe RAID 0,1,5,10
RKSAS4
Green
4 Port SAS with Intel ESRT2 RAID 0,1, 10 and Intel
RSTe RAID 0,1,10
RKSAS4R5
Yellow
4 Port SAS with Intel ESRT2 RAID 0,1, 5, 10 and
®
Intel RSTe RAID 0,1,10
RKSAS8
Orange
8 Port SAS with Intel ESRT2 RAID 0,1, 10 and Intel
RSTe RAID 0,1,10
RKSAS8R5
Purple
8 Port SAS with Intel ESRT2 RAID 0,1, 5, 10 and
®
Intel RSTe RAID 0,1,10
®
®
®
®
®
®
®
Note: The 8-port Storage Upgrade Key can also implement the RAID function, but only 4 ports (SCU0) are user
®
accessible on Intel Server Board S2400LP.
Additional information for the on-board RAID features and functionality can be found in the Intel®
RAID Software User’s Guide (Intel Document Number D29305).
3.4.4 PCI Interface
The Intel® C600 PCH PCI Interface provides a 33 MHz, Revision 2.3 implementation. It
integrates a PCI arbiter that supports up to four external PCI bus masters in addition to the PCH
internal requests. This allows for combinations of up to four PCI down devices and PCI slots.
3.4.5 Low Pin Count (LPC) Interface
The Intel® C600 PCH implements an LPC Interface as described in the LPC 1.1 Specification.
The Low Pin Count (LPC) bridge function of the PCH resides in PCI Device 31: Function 0. In
addition to the LPC bridge interface function, D31:F0 contains other functional units including
DMA, interrupt controllers, timers, power management, system management, GPIO, and RTC.
3.4.6 Digital Media Interface (DMI)
Digital Media Interface (DMI) is the chip-to-chip connection between the processor and Intel®
C600 PCH. This high-speed interface integrates advanced priority-based servicing allowing for
concurrent traffic and true isochronous transfer capabilities. Base functionality is completely
software-transparent, permitting current and legacy software to operate normally.
3.4.7 Serials Peripheral Interface (SPI)
The Intel® C600 PCH implements an SPI Interface as an alternative interface for the BIOS flash
device. An SPI flash device can be used as a replacement for the FWH, and is required to
support Gigabit Ethernet and Intel® Active Management Technology. The PCH supports up to
two SPI flash devices with speeds up to 50 MHz, utilizing two chip select pins.
3.4.8 Compatibility Modules (DMA Controller, Timer/Counters, Interrupt Controller)
The DMA controller incorporates the logic of two 82C37 DMA controllers, with seven
independently programmable channels. Channels 0–3 are hardwired to 8-bit, count-by-byte
transfers, and channels 5–7 are hardwired to 16-bit, count-by-word transfers. Any two of the
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seven DMA channels can be programmed to support fast Type-F transfers. Channel 4 is
reserved as a generic bus master request.
The Intel® C600 PCH supports LPC DMA, which is similar to ISA DMA, through the PCH’s DMA
controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and
special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are
supported on the LPC interface.
The timer/counter block contains three counters that are equivalent in function to those found in
one 82C54 programmable interval timer. These three counters are combined to provide the
system timer function, and speaker tone. The 14.31818 MHz oscillator input provides the clock
source for these three counters.
The Intel® C600 PCH provides an ISA-Compatible Programmable Interrupt Controller (PIC) that
incorporates the functionality of two, 82C59 interrupt controllers. The two interrupt controllers
are cascaded so that 14 external and two internal interrupts are possible. In addition, the PCH
supports a serial interrupt scheme. All of the registers in these modules can be read and
restored. This is required to save and restore system state after power has been removed and
restored to the platform.
3.4.9 Advanced Programmable Interrupt Controller (APIC)
In addition to the standard ISA compatible Programmable Interrupt Controller (PIC) described in
the previous section, the Intel® C600 PCH incorporates the Advanced Programmable Interrupt
Controller (APIC).
3.4.10 Real Time Clock (RTC)
The Intel® C600 PCH contains a Motorola MC146818B-compatible real-time clock with 256
bytes of battery-backed RAM. The real-time clock performs two key functions: keeping track of
the time of day and storing system data, even when the system is powered down. The RTC
operates on a 32.768 KHz crystal and a 3 V battery. The RTC also supports two lockable
memory ranges. By setting bits in the configuration space, two 8-byte ranges can be locked to
read and write accesses. This prevents unauthorized reading of passwords or other system
security information. The RTC also supports a date alarm that allows for scheduling a wake up
event up to 30 days in advance, rather than just 24 hours in advance.
3.4.11 GPIO
Various general purpose inputs and outputs are provided for custom system design. The
number of inputs and outputs varies depending on the Intel® C600 PCH configuration.
3.4.12 Enhanced Power Management
The Intel® C600 PCH power management functions include enhanced clock control and various
low-power (suspend) states. A hardware-based thermal management circuit permits softwareindependent entrance to low-power states. The PCH contains full support for the Advanced
Configuration and Power Interface (ACPI) Specification, Revision 4.0a.
3.4.13 Fan Speed Control
The Intel® C600 PCH integrates four fan speed sensors (four TACH signals) and four fan speed
controllers (three Pulse Width Modulator signals), which enables monitoring and controlling up
to four fans on the system. With the new implementation of the single-wire Simple Serial
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Transport (SST) 1.0 bus and Platform Environmental Control Interface (PECI), the PCH
provides an easy way to connect to SST-based thermal sensors and access the processor
thermal data.
3.4.14 Intel®Virtualization Technology for Direct I/O (Intel®VT-d)
The Intel® Virtualization Technology is designed to support multiple software environments
sharing same hardware resources. Each software environment may consist of an OS and
applications. The Intel® Virtualization Technology can be enabled or disabled in the BIOS setup.
The default behavior is disabled.
Note: If the setup options are changed to enable or disable the Virtualization Technology setting
in the processor, the user must perform an AC power cycle for the changes to take effect
The chipset supports DMA remapping from inbound PCI Express* memory Guest Physical
Address (GPA) to Host Physical Address (HPA). PCI devices are directly assigned to a virtual
machine leading to a robust and efficient virtualization.
3.4.15 KVM/Serial Over LAN (SOL) Function
These functions support redirection of keyboard, mouse, and text screen to a terminal window
on a remote console. The keyboard, mouse, and text redirection enables the control of the client
machine through the network without the need to be physically near that machine. Text, mouse,
and keyboard redirection allows the remote machine to control and configure the client by
entering BIOS setup. The KVM/SOL function emulates a standard PCI serial port and redirects
the data from the serial port to the management console using LAN. KVM has additional
requirements of internal graphics and SOL may be used when KVM is not supported.
3.4.16 IDE-R Function
The IDE-R function is an IDE Redirection interface that provides client connection to
management console ATA/ATAPI devices. When booting from IDE-R, the IDE-R interface will
send the client’s ATA/ATAPI command to the management console. The management console
will then provide a response command back to the client. A remote machine can setup a
diagnostic SW or OS installation image and direct the client to boot from IDE-R. The IDE-R
interface is the same as the IDE interface and is compliant with ATA/ATAPI-6 specifications.
IDE-R does not conflict with the usage of PXE boot. The system can support both interfaces
and continue to boot from the PXE as with any other boot devices. However, during
management boot session the Intel® AMT solution will use IDE-R when remote boot is required.
The devices attached to the IDER channel are only visible to software during management boot
session. During normal boot session the IDE-R channel does not appear as a present device.
3.4.17 Manageability
Intel® C600 PCH integrates several functions designed to manage the system and lower the
total cost of ownership (TCO) of the system. These system management functions are designed
to report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller. The functionality provided by the SPS firmware is different from Intel®
Active Management Technology (Intel® AMT or AT) provided by the ME on client platforms.

28
TCO Timer: The Intel® C600 PCH’s integrated programmable TCO timer is used to
detect system locks. The first expiration of the timer generates an SMI# that the system
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can use to recover from a software lock. The second expiration of the timer causes a
system reset to recover from a hardware lock.

Processor Present Indicator: The Intel® C600 PCH looks for the processor to fetch the
first instruction after reset. If the processor does not fetch the first instruction, the PCH
will reboot the system.

ECC Error Reporting: When detecting an ECC error, the host controller has the ability
to send one of several messages to the Intel® C600 PCH. The host controller can
instruct the PCH to generate any of SMI#, NMI, SERR#, or TCO interrupt.

Function Disable: The Intel® C600 PCH provides the ability to disable the following
integrated functions: LAN, USB, LPC, Intel HD Audio, SATA, PCI Express* or SMBus*.
Once disabled, these functions no longer decode I/O, memory, or PCI configuration
space. Also, no interrupts or power management events are generated from the disabled
functions.

Intruder Detect: The Intel® C600 PCH provides an input signal (INTRUDER#) that can
be attached to a switch that is activated by the system case being opened. The Intel®
C600 PCH can be programmed to generate either SMI# or TCO interrupt due to an
active INTRUDER# signal.
3.4.18 System Management Bus (SMBus* 2.0)
The Intel® C600 PCH contains a SMBus* Host interface that allows the processor to
communicate with SMBus* slaves. This interface is compatible with most I2C devices. Special
I2C commands are implemented.
The Intel® C600 PCH’s SMBus* host controller provides a mechanism for the processor to
initiate communications with SMBus* peripherals (slaves). Also, the PCH supports slave
functionality, including the Host Notify protocol. Hence, the host controller supports eight
command protocols of the SMBus* interface (see System Management Bus (SMBus*)
Specification, Version 2.0): Quick Command, Send Byte, Receive Byte, Write Byte/Word, Read
Byte/Word, Process Call, Block Read/Write, and Host Notify.
The Intel® C600 PCH’s SMBus* also implements hardware-based Packet Error Checking for
data robustness and the Address Resolution Protocol (ARP) to dynamically provide address to
all SMBus* devices.
3.4.19 Network Interface Controller (NIC)
Network interface support is provided from the onboard Intel® I350 NIC, which is a dual-port,
compact component with two fully integrated GbE Media Access Control (MAC) and Physical
Layer (PHY) ports. The Intel® I350 NIC provides the server board with support for dual LAN
ports designed for 10/100/1000 Mbps operation. Refer to the Intel® I350 Gigabit Ethernet
Controller Datasheet for full details of the NIC feature set.
The NIC device provides a standard IEEE 802.3 Ethernet interface for 1000BASE-T, 100BASETX, and 10BASE-T applications (802.3, 802.3u, and 802.3ab) and is capable of transmitting and
receiving data at rates of 1000 Mbps, 100 Mbps, or 10 Mbps.
The Intel® I350 controller also requires the use of Intel® C600 PCH SMBus* interface during
Sleep states S4 and S5 as well as for ME Firmware. The Intel® I350 LAN controller will be on
standby power so that Wake on LAN and manageability functions can be supported.
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Product Architecture Overview
Intel®Server Boards S2400LP TPS
Intel® I350 will be used in conjunction with the Server Engines PILOT III BMC for in band
Management traffic. The BMC will communicate with Intel® I350 over a NC-SI interface (RMII
physical). The NIC will be on standby power so that the BMC can send management traffic over
the NC-SI interface to the network during sleep states S4 and S5.
The NIC supports the normal RJ-45 LINK/Activity speed LEDs as well as the Proset ID function.
These LEDs are powered from a Standby voltage rail.
The link/activity LED (at the right of the connector) indicates network connection when on, and
transmit/receive activity when blinking. The speed LED (at the left of the connector) indicates
1000-Mbps operation when green, 100-Mbps operation when amber, and 10-Mbps when off.
The following table provides an overview of the LEDs.
Figure 14. 1GbE NIC port LED
Table 11. NIC Status LED
LED Color
Green/Amber (B)
Green (A)
3.4.19.1
LED State
NIC State
Off
10 Mbps
Amber
100 Mbps
Green
1000 Mbps
On
Active Connection
Blinking
Transmit/Receive activity
MAC Address Definition (TBD)
®
The Intel Server Board S2400LP has the following four MAC addresses assigned to it at the
Intel factory:


NIC 1 MAC address
NIC 2 MAC address – Assigned the NIC 1 MAC address +1(Server Management
and WOL)
 Integrated BMC LAN Channel MAC address – Assigned the NIC 1 MAC address +2
 Intel® Remote Management Module 4 (Intel® RMM4) MAC address – Assigned the
NIC 1 MAC address +3
®
The Intel Server Board S2400LP has a white MAC address sticker included with the board.
The sticker displays the NIC 1 MAC address in both bar code and alphanumeric formats.
3.4.19.2
LAN Manageability
Port 2 of the Intel® I350 NIC will be used by the BMC firmware to send management traffic. In
standby in order to save power, Port2 will be the only port to support Wake on LAN. The
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Product Architecture Overview
EEPROM is programmed to turn off this feature from the other ports in order to maximize power
savings during sleep states.
3.4.19.3
Wake-On-LAN
WOL is supported on the Intel® I350 LAN controller for all supported Sleep states
3.4.19.4
LAN Connector Ordering
®
The Intel I350 NIC is connected to independent RJ-45 ports for NIC 1 and NIC 2.
3.4.19.5
Intel®I350 Thermal Sensor
Intel® I350 NIC will have an integrated digital thermal sensor accessible through CSR and
manageability registers. The thermal sensor can be programmed to trigger digital pins and
thermal throttling with hysteresis.
3.5
InfiniBand* Controller
Intel® Server Board S2400LPQ and S2400LPF are populated with a new generation
InfiniBand*/Ethernet adapter device. Mellanox* ConnectX®-3 supports Virtual Protocol
Interconnect® (VPI), providing 10/20/40 Gb/s InfiniBand* interfaces. The functional diagram is as
below:
®
Figure 15. ConnectX -3 function block diagram
Major features and functions include:
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Revision 2.0
Single InfiniBand* Port: SDR/DDR/QDR/FDR with port remapping in firmware
Performance optimization: achieving single port line-rate bandwidth
PCI Express* 3.0 x8 to achieve 2.5, 5 or 8GT/s link rate
Optimized for LOM: Small footprint, minimal peripherals, WOL, integrated sensors
and BMC interface
Low power consumption: 6.5Watt typical
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Product Architecture Overview
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3.5.1 Device Interfaces
Below is a list of major interfaces of Mellanox* ConnectX®-3 chip:

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Clock and Reset signals: include core clock input and chip reset signals
Uplink Bus: The PCI Express* bus is a high-speed uplink interface used to connect
ConnectX-3 to the host processor. The ConnectX-3 supports a PCI Express* 3.0 x8
uplink connection with transfer rates of 2.5GT/s, 5GT/s and 8GT/s per lane.
Throughout this document, the PCI Express* interface may also be referred to as the
“uplink” interface
Network Interface: Single network port connecting the device to a network fabric in
one of the configurations described in below table.
Table 12. Network Port Configuration

Flash interface: Chip initialization and host boot

I2C Compatible Interfaces: For chip, QSFP connector, and chassis configure
and monitor

Management Link: Connect to BMC through SMBus* and NC-SI
 Others including: MDIO, GPIO and JTAG
Two network ports connecting the device to a network fabric in one of the configurations
described in below table
3.5.2 Quad Small Form-factor Pluggable (QSFP) connector
Port of the Mellanox* ConnectX®-3 is connected to a single QSFP connector on Intel® Server
Board S2400LP (available on SKU: S2400LPQ and S2400LPF). Below is the application
reference between Mellanox* ConnectX®-3 and QSFP:
®
Figure 16. Connection between ConnectX -3 and QSFP
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Product Architecture Overview
The QSFP module and all pins shall withstand 500V electrostatic discharge based on Human
Body Model per JEDEC JESD22-A114-B.
The module shall meet ESD requirements given in EN61000-4-2, criterion B test specification
such that when installed in a properly grounded cage and chassis the units are subjected to
15KV air discharges during operation and 8KV direct contact discharges to the case.
3.6
Baseboard Management Controller Overview
The server board utilizes the Baseboard Management features of the Server Engines* Pilot-III
Server Management Controller. The following is an overview of the features as implemented on
the server board from each embedded controller.
Figure 17. Integrated BMC implementation overview
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Product Architecture Overview
Intel®Server Boards S2400LP TPS
Figure 18. BMC Functional Block Diagram
The Integrated BMC is provided by an embedded ARM9 controller and associated peripheral
functionality that is required for IPMI-based server management. Firmware usage of these
hardware features is platform dependent.
The following is a summary of the Integrated BMC management hardware features that
comprise the BMC:
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34
400MHz 32-bit ARM9 processor with memory management unit (MMU)
Two independent10/100/1000 Ethernet Controllers with RMII/RGMII support
DDR2/3 16-bit interface with up to 800 MHz operation
12 10-bit ADCs
Sixteen fan tachometers
Eight Pulse Width Modulators (PWM)
Chassis intrusion logic
JTAG Master
Eight I2C interfaces with master-slave and SMBus* timeout support. All interfaces are
SMBus* 2.0 compliant.
Parallel general-purpose I/O Ports (16 direct, 32 shared)
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Product Architecture Overview
Serial general-purpose I/O Ports (80 in and 80 out)
Three UARTs
Platform Environmental Control Interface (PECI)
Six general-purpose timers
Interrupt controller
Multiple SPI flash interfaces
NAND/Memory interface
Sixteen mailbox registers for communication between the BMC and host
LPC ROM interface
BMC watchdog timer capability
SD/MMC card controller with DMA support
LED support with programmable blink rate controls on GPIOs
Port 80h snooping capability
Secondary Service Processor (SSP), which provides the HW capability of offloading time
critical processing tasks from the main ARM core.
Server Engines* Pilot III contains an integrated SIO, KVMS subsystem and graphics controller
with the following features:
3.6.1 Super I/O Controller
The integrated super I/O controller provides support for the following features as implemented
on the server board:
 Keyboard Style/BT interface for BMC support
 Two Fully Functional Serial Ports, compatible with the 16C550
 Serial IRQ Support
 Up to 16 Shared GPIO available for host processor
 Programmable Wake-up Event Support
 Plug and Play Register Set
 Power Supply Control
3.6.1.1 Keyboard and Mouse Support
The server board does not support PS/2 interface keyboards and mice. However, the system
BIOS recognizes USB specification-compliant keyboard and mice.
3.6.1.2 Wake-up Control
The super I/O contains functionality that allows various events to power on and power off
the system.
3.6.2 Graphics Controller and Video Support
The integrated graphics controller provides support for the following features as implemented on
the server board:
 Integrated Graphics Core with 2D Hardware accelerator
 DDR-2/3 memory interface supports up to 256Mbytes of memory
 Supports all display resolutions up to 1600 x 1200 16bpp @ 60Hz
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Product Architecture Overview
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Intel®Server Boards S2400LP TPS
High speed Integrated 24-bit RAMDAC
The integrated video controller supports all standard IBM VGA modes. The following table
shows the 2D modes supported for both CRT and LCD:
Table 13. Video Modes
2D Mode
Refresh Rate (Hz)
8 bpp
Supported
2D Video Mode Support
16 bpp
32 bpp
Supported
Supported
640x480
60, 72, 75, 85, 90,
100, 120, 160, 200
800x600
60, 70, 72, 75, 85,
90, 100, 120,160
Supported
Supported
Supported
1024x768
60, 70, 72,
75,85,90,100
Supported
Supported
Supported
1152x864
43,47,60,70,75,80,85
Supported
Supported
Supported
1280x1024
60,70,74,75
Supported
Supported
Supported
1600x1200**
60
Supported
Supported
Supported
Note:
Video resolutions at 1600x1200 are only supported through the external video
connector located on the rear I/O section of the server board. Utilizing the optional
front panel video connector may result in lower video resolutions.
The server board provides two video interfaces. The primary video interface is accessed using a
standard 15-pin VGA connector found on the back edge of the server board. In addition, video
signals are routed to a 14-pin header labeled “FP_Video” on the leading edge of the server
board, allowing for the option of cabling to a front panel video connector. Attaching a monitor to
the front panel video connector will disable the primary external video connector on the back
edge of the board.
The BIOS supports dual-video mode when an add-in video card is installed.


In the single mode (dual monitor video = disabled), the on-board video controller is
disabled when an add-in video card is detected.
In the dual mode (on-board video = enabled, dual monitor video = enabled), the onboard video controller is enabled and is the primary video device. The add-in video card
is allocated resources and is considered the secondary video device. The BIOS Setup
utility provides options to configure the feature as follows:
Table 14. Video mode
On-board Video
Enabled
Disabled
Dual Monitor Video
Enabled
Shaded if on-board video is set to "Disabled"
Disabled
3.6.3 Remote KVM
The Integrated BMC contains a remote KVMS subsystem with the following features:


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USB 2.0 interface for Keyboard, Mouse and Remote storage such as CD/DVD ROM and
floppy
USB 1.1/USB 2.0 interface for PS2 to USB bridging, remote Keyboard and Mouse
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Product Architecture Overview
Hardware Based Video Compression and Redirection Logic
Supports both text and Graphics redirection
Hardware assisted Video redirection using the Frame Processing Engine
Direct interface to the Integrated Graphics Controller registers and Frame buffer
Hardware-based encryption engine.
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Platform Management Functional Overview
4.
Intel®Server Boards S2400LP TPS
Platform Management Functional Overview
Platform management functionality is supported by several hardware and software components
integrated on the server board that work together to control system functions, monitor and report
system health, and control various thermal and performance features in order to maintain (when
possible) server functionality in the event of component failure and/or environmentally stressed
conditions.
This chapter provides a high level overview of the platform management features and
functionality implemented on the server board. For more in depth and design level Platform
Management information, please reference the BMC Core Firmware External Product
Specification (EPS) and BIOS Core External Product Specification (EPS) for Intel® Server
products based on the Intel® Xeon® processor E5-2400 product families.
4.1
Baseboard Management Controller (BMC) Firmware Feature Support
The following sections outline general features that the Integrated BMC firmware can support.
Support and utilization for some features is dependent on the server platform in which the
server board is integrated and any additional system level components and options that may be
installed.
4.1.1 IPMI 2.0 Features
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Baseboard management controller (BMC)
IPMI Watchdog timer
Messaging support, including command bridging and user/session support
Chassis device functionality, including power/reset control and BIOS boot
flags support
Event receiver device: The BMC receives and processes events from other
platform subsystems.
Field Replaceable Unit (FRU) inventory device functionality: The BMC supports
access to system FRU devices using IPMI FRU commands.
System Event Log (SEL) device functionality: The BMC supports and provides
access to a SEL.
Sensor Data Record (SDR) repository device functionality: The BMC supports
storage and access of system SDRs.
Sensor device and sensor scanning/monitoring: The BMC provides IPMI
management of sensors. It polls sensors to monitor and report system health.
IPMI interfaces
Host interfaces include system management software (SMS) with receive message
queue support, and server management mode (SMM)
IPMB interface
LAN interface that supports the IPMI-over-LAN protocol (RMCP, RMCP+)
o Serial-over-LAN (SOL)
o
ACPI state synchronization: The BMC tracks ACPI state changes that are
provided by the BIOS.
o
BMC self test: The BMC performs initialization and run-time self-tests and makes
results available to external entities.
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Platform Management Functional Overview
See also the Intelligent Platform Management Interface Specification Second
Generation v2.0.
4.1.2 Non IPMI Features
The BMC supports the following non-IPMI features.
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Revision 2.0
In-circuit BMC firmware update
BMC FW reliability enhancements:
o Redundant BMC boot blocks to avoid possibility of a corrupted boot block
resulting in a scenario that prevents a user from updating the BMC.
o
BMC System Management Health Monitoring
o
Signed firmware images for increased security
Fault resilient booting (FRB): FRB2 is supported by the watchdog timer functionality.
Enable/Disable of System Reset Due CPU Errors
Chassis intrusion detection
Fan speed control
Fan redundancy monitoring and support
Hot-swap fan support
Power Supply Fan Sensors
System Airflow Monitoring
Exit Air Temperature Monitoring
Acoustic management: Support for multiple fan profiles
Ethernet Controller Thermal Monitoring
Global Aggregate Temperature Margin Sensor
Platform environment control interface (PECI) thermal management support
Memory Thermal Management
DIMM temperature monitoring: New sensors and improved acoustic management
using closed-loop fan control algorithm taking into account DIMM
temperature readings.
Power supply redundancy monitoring and support
Power unit management: Support for power unit sensor. The BMC handles powergood dropout conditions.
Intel® Intelligent Power Node Manager support
Signal testing support: The BMC provides test commands for setting and getting
platform signal states.
The BMC generates diagnostic beep codes for fault conditions.
System GUID storage and retrieval
Front panel management: The BMC controls the system status LED and chassis ID
LED. It supports secure lockout of certain front panel functionality and monitors
button presses. The chassis ID LED is turned on using a front panel button or
a command.
Power state retention
Power fault analysis
Intel® Light-Guided Diagnostics
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Platform Management Functional Overview
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Address Resolution Protocol (ARP): The BMC sends and responds to ARPs
(supported on embedded NICs).
Dynamic Host Configuration Protocol (DHCP): The BMC performs DHCP (supported
on embedded NICs).
E-mail alerting
Embedded web server
o Support for embedded web server UI in Basic Manageability feature set.
o
Human-readable SEL
o
Additional system configurability
o
Additional system monitoring capability
o
Enhanced on-line help
Integrated KVM
Integrated Remote Media Redirection
Local Directory Access Protocol (LDAP) support
Sensor and SEL logging additions/enhancements (for example additional thermal
monitoring capability)
SEL Severity Tracking and the Extended SEL
BMC Data Repository (Managed Data Region Feature)
Embedded platform debug feature which allows capture of detailed data for
later analysis.
Provisioning and inventory enhancements:
o Signed Firmware (improved security)
o
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Intel®Server Boards S2400LP TPS
Inventory data/system information export (partial SMBIOS table)
DCMI 1.1 compliance
Management support for PMBus* rev1.2 compliant power supplies
Energy Star Server Support
SmaRT/CLST
Power Supply Cold Redundancy
Power Supply FW Update for supported Intel® supplies
Power Supply Compatibility Check
4.1.3 New Manageability Features
The new generation PCSD server products offer a number of changes and additions to the
manageability features that are supported on the previous generation of servers. The following
is a list of the more significant changes that are common to all PCSD servers of this new
generation:
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40
Sensor and SEL logging additions/enhancements (for example, additional thermal
monitoring capability)
SEL Severity Tracking and the Extended SEL
Embedded platform debug feature which allows capture of detailed data for later
analysis.
Provisioning and inventory enhancements:
o Signed Firmware (improved security)
o Inventory data/system information export (partial SMBIOS table)
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Revision 2.0
Intel®Server Boards S2400LP TPS
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Enhancements to fan speed control.
DCMI 1.1 compliance.
Support for embedded web server UI in Basic Manageability feature set.
Enhancements to embedded web server
o Human-readable SEL
o Additional system configurability
o Additional system monitoring capability
o Enhanced on-line help
Enhancements to KVM redirection
o Support resolution up to 1600x1200
Management support for PMBus* rev1.2 compliant power supplies
BMC Data Repository (Managed Data Region Feature)
System Airflow Monitoring
Exit Air Temperature Monitoring
Ethernet Controller Thermal Monitoring
Global Aggregate Temperature Margin Sensor
Memory Thermal Management
Power Supply Fan Sensors
Enable/Disable of System Reset Due CPU Errors
Energy Star Server Support
SmaRT/CLST
Power Supply Cold Redundancy
Power Supply FW Update
Power Supply Compatibility Check
BMC FW reliability enhancements:
o Redundant BMC boot blocks to avoid possibility of a corrupted boot block
resulting in a scenario that prevents a user from updating the BMC.
o BMC System Management Health Monitoring
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4.2
Platform Management Functional Overview
Advanced Configuration and Power Interface (ACPI)
The server board has support for the following ACPI states:
Table 15. ACPI Power States
State
S0
Supported
Yes
Description
Working.

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The front panel power LED is on (not controlled by the BMC).
The fans spin at the normal speed, as determined by sensor inputs.
Front panel buttons work normally.
S1
Yes
Sleeping. Hardware context is maintained; equates to processor and chipset clocks being
stopped.

The front panel power LED blinks at a rate of 1 Hz with a 50% duty cycle (not controlled
by the BMC).

The watchdog timer is stopped.

The power, reset, front panel NMI, and ID buttons are unprotected.

Fan speed control is determined by available SDRs. Fans may be set to a fixed state, or
basic fan management can be applied.
The BMC detects that the system has exited the ACPI S1 sleep state when the BIOS SMI
handler notifies it.
S2
No
Not supported.
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Platform Management Functional Overview
State
S3
Supported
No
Description
Supported only on Workstation platforms. See appropriate Platform Specific Information for
more information.
S4
No
Not supported.
S5
Yes
Soft off
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Intel®Server Boards S2400LP TPS
The front panel buttons are not locked.
The fans are stopped.
The power-up process goes through the normal boot process.
The power, reset, front panel NMI, and ID buttons are unlocked.
Platform Management SMBus* and I2C Implementation
SMBus*/ I2C interconnections are a fundamental interface for various manageability
components. There are three buses that are used in a multi-master fashion.

Primary IPMB - An IPMB header is provided on the baseboard to support connectivity
with 3rd party management PCIe cards. This bus operates as 100 kHz bus.

Secondary IPMB - This is the SMLink0 bus that connects the BMC with the ME in the
SSB. This bus is considered a secondary IPMB. The ME and BMC communicate over
this bus using IPMB protocol messages. Any devices on the bus must be 400 kHz bus
tolerant.

PMBus* - This is the SMLink1 bus that both the ME and BMC use to communicate with
the power supplies. This bus operates as 100 kHz bus.
For all multi-master buses, the master that initiates a transaction is responsible for any bus
recovery sequence if the bus hangs.
The BMC acts as master for the other buses connected to it.
4.4
BMC Internal Timestamp Clock
The BMC maintains an internal timestamp clock that is used by various BMC subsystems, for
example, for time stamping SEL entries. As part of BMC initialization after AC power is applied
or the BMC is reset, the BMC initializes this internal clock to the value retrieved from the SSB
component’s RTC through a SMBus* slave read operation. This is the system RTC and is on
the battery power well so it maintains the current time even when there is no AC supplied to the
system.
The BMC reads the RTC using the same SMBus* (the “host SMBus*”) that is used by BIOS
during POST, so the BMC FW must not attempt to access the RTC between the time the
system is reset or powered-on and POST completes, as indicated by the assertion of the POSTcomplete signal. Additionally, the BMC should cancel any pending reads of the RTC if the
POST-complete signal deasserts (for example, due to a reset). Normally the BMC reads the
RTC when AC power is first applied and before the system is powered-on, so this is not a
concern. However, if AC power is applied and the power button is immediately pressed, it is
possible that POST would be in progress by the time the BMC is ready to read the RTC.
Another potential conflict can occur if the BMC gets reset and POST is in progress when the
BMC has re-initialized. For either of these cases, the BMC FW initializes its internal time clock
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Platform Management Functional Overview
to zero and begins counting up from there. When POST completes, BIOS will then update the
BMC’s time clock to the current system time.
The BMC’s internal timestamp clock is read and set using the Get SEL Time and Set SEL Time
commands, respectively. The Get SDR Time command can also be used to read the timestamp
clock. These commands and the IPMI time format are specified in the IPMI 2.0 specification.
Whenever the BMC receives the Set SEL Time command, it updates only its internal time clock.
Note that an update of this internal time clock does not result in a change to the system RTC.
4.5
Sensor Monitoring
The BMC monitors system hardware and reports system health. The information gathered from
physical sensors is translated into IPMI sensors as part of the “IPMI Sensor Model”. The BMC
also reports various system state changes by maintaining virtual sensors that are not
specifically tied to physical hardware.
4.6
Messaging Interfaces
The supported BMC communication interfaces include:
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Host SMS interface by means of low pin count (LPC)/keyboard controller style (KCS)
interface
Host SMM interface by means of low pin count (LPC)/keyboard controller style (KCS)
interface
Intelligent Platform Management Bus (IPMB) I2C interface
LAN interface using the IPMI-over-LAN protocols
4.6.1 Channel Management
Every messaging interface is assigned an IPMI channel ID by IPMI 2.0. Commands are
provided to configure each channel for privilege levels and access modes. Table 16 shows the
standard channel assignments:
Table 16. Standard Channel Assignments
Channel ID
Interface
Supports Sessions
0
Primary IPMB
No
1
LAN 1
Yes
2
LAN 2
3
1
LAN3 (Provided by the Intel Dedicated Server Management NIC)
Yes
4
Reserved
Yes
5
USB
No
6
Secondary IPMB
No
7
SMM
No
8 – 0Dh
Reserved
–
Yes
®
2
–
0Eh
Self
0Fh
SMS/Receive Message Queue
No
Notes:
1.
2.
Optional hardware supported by the server system.
Refers to the actual channel used to send the request.
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4.6.2 User Model
The BMC supports the IPMI 2.0 user model including User ID 1 support. 15 user IDs are
supported. These 15 users can be assigned to any channel. The following restrictions are
placed on user-related operations:
1. User names for User IDs 1 and 2 cannot be changed. These are always “” (Null/blank)
and “root” respectively.
a) A “CCh” error completion code is returned if a user attempts to modify these
names.
2. User 2 (“root”) always has the administrator privilege level.
a) A “CCh” error completion code is returned if a user attempts to modify this value.
b) Trying to set any parameter for User ID 2 (root user) with the Set User Access
command fails with a CCh completion code.
3. All user passwords (including passwords for 1 and 2) may be modified.
4. User IDs 3-15 may be used freely, with the condition that user names are unique.
Therefore, no other users can be named “” (Null), “root,” or any other existing
user name.
Resetting a user name to a value equivalent to its current value results in a 0xCC error code. A
list of default user values is given in Table 17.
Table 17. Default User Values
Users
User name
Password
Status
Default Privilege
Characteristics
User 1
[Null]
[Null]
Disabled
Admin
Password can be
changed.
This user may not be
used to access the
embedded web
server.
User 2
root
superuser
Disabled
Admin
Password can be
changed
User 3
test1
superuser
Disabled
Admin
User name and
password can be
changed
User 4
test2
superuser
Disabled
Admin
User name and
password can be
changed
User 5
test3
superuser
Disabled
Admin
User name and
password can be
changed
User 6-15
undefined
undefined
Disabled
Admin
User name and
password can be
changed
4.6.3 Sessions
The maximum number of IPMI-based sessions that can be supported by the BMC is returned as
the byte 3 (number of possible active sessions) of the IPMI Command Get Session Info (App,
3Dh). Embedded Web Server and Media Redirection are not IPMI-based sessions. KVM is a
type of payload in a RMCP+ Session.
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Table 18. Channel/Media-specific minimum number of sessions
Channels/Media type
1
®
LAN Channel , Intel
Dedicated Server
4
Management NIC
HTTP
5
____5
____1
Session Type
1
IPMI Over LAN
Minimum Number of Sessions
Embedded Web Server
Media Redirection
KVM
2
b
3
4
6,7
2
8,9
2
8
2
10
Notes:
1. Session type defined by the IPMI spec and includes RMCP and RMCP+ sessions (including all the
payloads supported)
2. KVM is a RMCP+ Payload Type. Not an IPMI session.
3. These sessions are not defined by IPMI Specification and are not based on IPMI protocol. Counting
them as IPMI Session violates the Specification.
®
4. If Intel Dedicated Server Management NIC is not present, the minimum number of sessions still
holds but only over LAN Channel 1.
5. It is not an IPMI Channel.
6. Maximum of 15 IPMI sessions are allowed per channel that is defined.
7. IPMI-based session and counted as an IPMI Session in all calculations.
8. These sessions are not counted as IPMI sessions. (For example, Get Session Info only returns values
based on IPMI Sessions).
9. This type of Non-IPMI session can open IPMI sessions as part of a normal operation and those IPMI
sessions are counted as IPMI sessions. For example, within a Web Session, one or more IPMI Over
LAN Session are opened to Get&Set IPMI parameters. But since these IPMI sessions are not over
®
®
LAN1 or Intel Dedicated Server Management NIC, they are not counted as LAN1 or Intel Dedicated
Server Management NIC IPMI channel sessions but are counted as IPMI sessions in limit calculations.
10. It is an IPMI Over LAN RMCP+ session and is included in counts as part of the larger IPMI Over LAN
group.
Note: The number of possible active session values returned by Get Session Info is the total
number of allocated memory session slots in BMC firmware for IPMI Sessions. The actual
number of IPMI sessions that can be established at any time is dependent on Channel and User
IPMI configuration parameters and in compliance with the IPMI Specification, which is always
less than the total available slots
4.6.4 BMC LAN Channels
The BMC supports three RMII/RGMII ports that can be used for communicating with Ethernet
devices. Two ports are used for communication with the on-board NICs and one is used for
communication with an Ethernet PHY located on an optional add-in card (or equivalent on-board
circuitry).
4.6.4.1 Baseboard NICs
The specific Ethernet controller (NIC) used on a server is platform-specific but all baseboard
device options provide support for an NC-SI manageability interface. This provides a sideband
high-speed connection for manageability traffic to the BMC while still allowing for a
simultaneous host access to the OS if desired.
The Network Controller Sideband Interface (NC-SI) is a DMTF industry standard protocol for the
side band management LAN interface. This protocol provides a fast multi-drop interface for
management traffic.
The baseboard NIC(s) are connected to a single BMC RMII/RGMII port that is configured for
RMII operation. The NC-SI protocol is used for this connection and provides a 100 Mb/s fullduplex multi-drop interface which allows multiple NICs to be connected to the BMC. The
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physical layer is based upon RMII, however RMII is a point-to-point bus whereas NC-SI allows 1
master and up to 4 slaves. The logical layer (configuration commands) is incompatible with RMII.
Multi-port baseboard NICs on some products will provide support for a dedicated management
channel than can be configured to be hidden from the host and only used by the BMC. This
mode of operation is configured through a BIOS setup option.
4.6.4.2 Dedicated Management Channel
An additional LAN channel dedicated to BMC usage and not available to host SW is supported
through an optional add-in card. There is only a PHY device present on the add-in card. The
BMC has a built-in MAC module that uses the RGMII interface to link with the card’s PHY.
Therefore, for this dedicated management interface, the PHY and MAC are located in different
devices.
The PHY on the card connects to the BMC’s other RMII/RGMII interface (that is, the one that is
not connected to the baseboard NICs). This BMC port is configured for RGMII usage.
In addition to the use of an add-in card for a dedicated management channel, on systems that
support multiple Ethernet ports on the baseboard, the system BIOS provides a setup option to
allow one of these baseboard ports to be dedicated to the BMC for manageability purposes.
When this is enabled, that port is hidden from the OS.
4.6.4.3 Concurrent Server Management Use of Multiple Ethernet Controllers
Provided the HW supports a management link between the BMC and a NIC port, the BMC FW
supports concurrent OOB LAN management sessions for the following combination:
2 on-board NIC ports
1 on-board NIC and the optional dedicated add-in management NIC.
2 on-board NICs and optional dedicated add-in management NIC.
All NIC ports must be on different subnets for the above concurrent usage models.
MAC addresses are assigned for management NICs from a pool of up to three MAC addresses
allocated specifically for manageability. The total number of MAC addresses in the pool is
dependent on the product HW constraints (for example a board with 2 NIC ports available for
manageability would have a MAC allocation pool of two addresses).
For these channels, support can be enabled for IPMI-over-LAN and DHCP.
For security reasons, embedded LAN channels have the following default settings:
IP Address: Static
All users disabled
Network failover mode must be used for IPMI capable interfaces that are on the same subnet.
Host-BMC communication over the same physical LAN connection – also known as “loopback”
– is not supported. This includes “ping” operations.
On baseboards with more than two onboard NIC ports, only the first two ports can be used as
BMC LAN channels. The remaining ports have no BMC connectivity.
Maximum bandwidth supported by BMC LAN channels are as follows:
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BMC LAN1 (Baseboard NIC port) ----- 100M (10M in DC off state)
BMC LAN 2 (Baseboard NIC port) ----- 100M (10M in DC off state)
BMC LAN 3 (Dedicated NIC) ----- 1000M
4.6.5 IPV6 Support
In addition to IPv4, the Intel® Server Board S2400LP supports IPv6 for manageability channels.
Configuration of IPv6 is provided by extensions to the IPMI Set and Get LAN Configuration
Parameters commands as well as through a Web Console IPv6 configuration web page.
The BMC supports IPv4 and IPv6 simultaneously so they are both configured separately and
completely independently. For example, IPv4 can be DHCP configured while IPv6 is statically
configured or vice versa. The parameters for IPv6 are similar to the parameters for IPv4 with the
following differences:



An IPv6 address is 16 bytes vs. 4 bytes for IPv4.
An IPv6 prefix is 0 to 128 bits whereas IPv4 has a 4 byte subnet mask.
The IPv6 Enable parameter must be set before any IPv6 packets will be sent or
received on that channel.
 There are two variants of automatic IP Address Source configuration against just
DHCP for IPv4.
The three possible IPv6 IP Address Sources for configuring the BMC are:
Static (Manual): The IP, Prefix, and Gateway parameters are manually configured by the user.
The BMC ignores any Router Advertisement messages received over the network.
DHCPv6: The IP comes from running a DHCPv6 client on the BMC and receiving the IP from
a DHCPv6 server somewhere on the network. The Prefix and Gateway are configured by
Router Advertisements from the local router. The IP, Prefix, and Gateway are read-only
parameters to the BMC user in this mode.
Stateless auto-config: The Prefix and Gateway are configured by the router through Router
Advertisements. The BMC derives its IP in two parts: the upper network portion comes from
the router and the lower unique portion comes from the BMC’s channel MAC address. The 6byte MAC address is converted into an 8-byte value per the EUI-64* standard. For example, a
MAC value of 00:15:17:FE:2F:62 converts into a EUI-64 value of 215:17ff:fefe:2f62. If the
BMC receives a Router Advertisement from a router at IP 1:2:3:4::1 with a prefix of 64, it
would then generate for itself an IP of 1:2:3:4:215:17ff:fefe:2f62. The IP, Prefix, and Gateway
are read-only parameters to the BMC user in this mode.
IPv6 can be used with the BMC’s Web Console, JViewer (remote KVM and Media), and
Systems Management Architecture for Server Hardware – Command Line Protocol (SMASHCLP) interface (ssh). There is no standard yet on how IPMI RMCP or RMCP+ should operate
over IPv6 so that is not currently supported.
4.6.5.1 LAN Failover
The BMC FW provides a LAN failover capability such that the failure of the system HW
associated with one LAN link will result in traffic being rerouted to an alternate link. This
functionality is configurable through IPMI methods as well as through the BMC’s Embedded UI,
allowing for user to specify the physical LAN links constitute the redundant network paths or
physical LAN links constitute different network paths. BMC will support only a all or nothing”
approach – that is, all interfaces bonded together, or none are bonded together.
The LAN Failover feature applies only to BMC LAN traffic. It bonds all available Ethernet
devices but only one is active at a time. When enabled, If the active connection’s leash is lost,
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one of the secondary connections is automatically configured so that it has the same IP address.
Traffic immediately resumes on the new active connection.
The LAN Failover enable/disable command may be sent at any time. After it has been enabled,
standard IPMI commands for setting channel configuration that specify a LAN channel other
than the first will return an error code.
4.7
System Event Log (SEL)
The BMC implements the system event log as specified in the Intelligent Platform Management
Interface Specification, Version 2.0. The SEL is accessible regardless of the system power state
through the BMC's in-band and out-of-band interfaces.
The BMC allocates 65,502 bytes (approx. 64 KB) of non-volatile storage space to store system
events. The SEL timestamps may not be in order. Up to 3,639 SEL records can be stored at a
time. Any command that results in an overflow of the SEL beyond the allocated space is
rejected with an “Out of Space” IPMI completion code (C4h).
4.7.1 Servicing Events
Events can be received while the SEL is being cleared. The BMC implements an event
message queue to avoid the loss of messages. Up to three messages can be queued before
messages are overwritten.
The BMC recognizes duplicate event messages by comparing sequence numbers and the
message source. For details, see the Intelligent Platform Management Interface Specification
Second Generation v2.0. Duplicate event messages are discarded (filtered) by the BMC after
they are read from the event message queue. The queue can contain duplicate messages.
4.7.2 SEL Entry Deletion
The BMC does not support individual SEL entry deletion. The SEL may only be cleared as a
whole.
4.7.3 SEL Erasure
SEL erasure is a background process. After initiating erasure with the Clear SEL command,
additional Clear SEL commands must be executed to get the erasure status and determine
when the SEL erasure is completed. This may take several seconds. SEL events that arrive
during the erasure process are queued until the erasure is complete and then committed to
the SEL.
SEL erasure generates an Event Logging Disabled (Log Area Reset/Cleared offset)
sensor event.
4.7.4 SEL Extension Capabilities
The BMC provides an OEM extension to all SEL entries. Each entry includes an additional 8
bytes for storing extra event data that will not fit into the original 3 data bytes provided by
standard IPMI SEL entries. The first extension byte is always valid for all SEL entries and
specifies the severity of the SEL event as well as the number of valid extension bytes following
the first one. That leaves up to 7 SEL extension data bytes that can be defined for each SEL
event entry.
All standard IPMI SEL commands work the same as if there were no SEL extensions.
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In order to store and access the extended SEL information, 5 OEM commands are implemented
that closely follow the standard IPMI SEL commands but provide support for the SEL Extension
data. These OEM commands are specified in the Intel General Application Commands table.
4.8
Sensor Data Record (SDR) Repository
The BMC implements the sensor data record (SDR) repository as specified in the Intelligent
Platform Management Interface Specification, Version 2.0. The SDR is accessible through the
BMC’s in-band and out-of-band interfaces regardless of the system power state The BMC
allocates 65,519 bytes of non-volatile storage space for the SDR.
4.9
Field Replaceable Unit (FRU) Inventory Device
The BMC implements the interface for logical FRU inventory devices as specified in the
Intelligent Platform Management Interface Specification, Version 2.0. This functionality provides
commands used for accessing and managing the FRU inventory information. These commands
can be delivered through all interfaces.
The BMC provides FRU device command access to its own FRU device and to the FRU
devices throughout the server. The FRU device ID mapping is defined in the Platform Specific
Information. The BMC controls the mapping of the FRU device ID to the physical device.
4.10 Diagnostics and Beep Code Generation
The BMC may generate beep codes upon detection of failure conditions. Beep codes are
sounded each time the problem is discovered (for example, on each power-up attempt), but are
not sounded continuously. Common supported codes are listed in Table 19.
Additional platform-specific beep codes can be found in the appropriate Platform Specific
Information. Each digit in the code is represented by a sequence of beeps whose count is equal
to the digit.
Table 19. BMC Beep Codes
Code
1-5-2-1
Reason for Beep
No CPUs installed or first CPU socket is
empty.
Associated Sensors
CPU Missing Sensor
Supported
Yes
1-5-2-4
MSID Mismatch.
MSID Mismatch Sensor.
Yes
1-5-4-2
Power fault: DC power is unexpectedly
lost (power good dropout).
Power unit – power unit failure
offset.
Yes
1-5-4-4
Power control fault (power good assertion
timeout).
Power unit – soft power control
failure offset.
Yes
1-5-1-2
VR Watchdog Timer sensor assertion
VR Watchdog Timer
1-5-1-4
The system does not power on or
unexpectedly powers off and a power
supply unit (PSU) is present that is an
incompatible model with one or more
other PSUs in the system
PSU Status
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4.11 Diagnostics Interrupt (NMI)
The BMC generates an NMI pulse under certain conditions. The BMC-generated NMI pulse
duration is at least 30 ms. Once an NMI has been generated by the BMC, the BMC does not
generate another NMI until the system has been reset or powered down.
The following actions cause the BMC to generate an NMI pulse:
a. Receiving a Chassis Control command to pulse the diagnostic interrupt. This command
does not cause an event to be logged in the SEL.
b. Detecting that the front panel diagnostic interrupt button has been pressed
c. Watchdog timer pre-timeout expiration with NMI/diagnostic interrupt pre-timeout action
enabled.
Below table shows behavior regarding NMI signal generation and event logging by the BMC.
Table 20. NMI Signal Generation and Event Logging
Causal Event
NMI (IA-32 Only)
Signal
Genera
tion
Chassis Control command (pulse
diagnostic interrupt)
X
–
Front panel diagnostic interrupt button
pressed
X
X
Watchdog Timer pre-timeout expiration
with NMI/diagnostic interrupt action
X
–
Front Panel Diag
Interrupt Sensor
Event Logging
Support
4.12 BMC Basic and Advanced Management Features
The Intel® Server Board S2400LP product includes support for an upgrade module to support
the advanced server management functionality.
Table 21. Basic and Advanced Management Features
50
Feature
IPMI 2.0 Feature Support
X
Basic*
X
In-circuit BMC Firmware Update
X
X
FRB 2
X
X
Chassis Intrusion Detection
X
X
Fan Redundancy Monitoring
X
X
Hot-Swap Fan Support
X
X
Acoustic Management
X
X
Diagnostic Beep Code Support
X
X
Power State Retention
X
X
ARP/DHCP Support
X
X
PECI Thermal Management Support
X
X
E-mail Alerting
X
X
Embedded Web Server
X
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Feature
Basic*
SSH Support
Advanced**
X
X
Integrated KVM
X
Integrated Remote Media Redirection
X
Local Directory Access Protocol (LDAP)
X
X
Intel Intelligent Power Node Manager
Support***
X
X
SMASH CLP
X
X
®
* Basic management features provided by BMC
®
**Advanced management features available with optional Intel Remote Management Module 4 Lite
®
***Intel Intelligent Power Node Manager Support requires PMBus*-compliant power supply
4.12.1 Enabling Advanced Manageability Features
The Advanced management features are to be delivered as part of the BMC FW image. The
BMC’s baseboard SPI flash contains code/data for both the Basic and Advanced features. An
optional module Intel® RMM4 Lite is used as the activation mechanism. When the BMC FW
initializes, it attempts to access the Intel® RMM4 lite. If the attempt to access Intel® RMM4 Lite is
successful, then the BMC activates the advanced features.
Advanced manageability features are supported over all NIC ports enabled for server
manageability. This includes baseboard NICs as well as the LAN channel provided by the
optional Dedicated NIC add-in card.
Table 22. Management features and Benefits
Manageability Hardware
Benefits
®
Comprehensive IPMI based base manageability
features
®
No dedicated NIC for management
Enables KVM and media redirection through onboard
NIC
®
Dedicated NIC for management traffic. Higher
bandwidth connectivity for KVM and media
Redirection with 1Gbe NIC.
Intel Integrated BMC
Intel Remote Management Module4 – Lite
Package contains one module –

Key for advance Manageability features.
Intel Remote Management4 Module
Package includes 2 modules –

Key for advance features

Dedicated NIC (1Gbe) for management
4.12.1.1 Keyboard, Video and Mouse (KVM) Redirection
The BMC firmware supports keyboard, video, and mouse redirection (KVM) over LAN. This
feature is available remotely from the embedded web server as a Java applet. This feature is
enabled when the Intel® RMM4 Lite is present. The client system must have a Java Runtime
Environment (JRE) version 5.0 or later to run the KVM or media redirection applets.
The BMC supports an embedded KVM application (Remote Console) that can be launched from
the embedded web server from a remote console. USB1.1 or USB 2.0 based mouse and
keyboard redirection are supported. It is also possible to use the KVM-redirection (KVM-r)
session concurrently with media-redirection (media-r). This feature allows a user to interactively
use the keyboard, video, and mouse (KVM) functions of the remote server as if the user were
physically at the managed server.
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The KVM-redirection feature automatically senses video resolution for best possible screen
capture and provides high-performance mouse tracking and synchronization. It allows remote
viewing and configuration in pre-boot POST and BIOS setup, once BIOS has initialized video.
Other attributes of this feature include:

Encryption of the redirected screen, keyboard, and mouse

Compression of the redirected screen
4.12.1.2 Remote Console
The Remote Console is the redirected screen, keyboard and mouse of the remote host system.
To use the Remote Console window of your managed host system, the browser must include a
Java* Runtime Environment plug-in. If the browser has no Java support, such as with a small
handheld device, the user can maintain the remote host system using the administration forms
displayed by the browser.
The Remote Console window is a Java Applet that establishes TCP connections to the BMC.
The protocol that is run over these connections is a unique KVM protocol and not HTTP or
HTTPS. This protocol uses ports #7578 for KVM, #5120 for CDROM media redirection, and
#5123 for Floppy/USB media redirection (both supporting encryption).
4.12.1.3 Performance
The remote display accurately represents the local display. The feature adapts to changes to the
video resolution of the local display and continues to work smoothly when the system transitions
from graphics to text or vice-versa. The responsiveness may be slightly delayed depending on
the bandwidth and latency of the network.
Enabling KVM and/or media encryption will degrade performance. Enabling video compression
provides the fastest response while disabling compression provides better video quality.
For the best possible KVM performance, a 2Mb/sec link or higher is recommended.
The redirection of KVM over IP is performed in parallel with the local KVM without affecting the
local KVM operation.
4.12.1.4 Security
The KVM redirection feature supports multiple encryption algorithms, including RC4 and AES.
The actual algorithm that is used is negotiated with the client based on the client’s capabilities.
4.12.1.5 Availability
The remote KVM session is available even when the server is powered-off (in stand-by mode).
No re-start of the remote KVM session shall be required during a server reset or power on/off.
An BMC reset (for example due to an BMC Watchdog initiated reset or BMC reset after BMC
firmware update) will require the session to be re-established.
KVM sessions persist across system reset, but not across an AC power loss.
4.12.1.6 Timeout
The remote KVM session will automatically timeout after a configurable amount of time (30
minutes is the default).
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The default inactivity timeout is 30 minutes, but may be changed through the embedded web
server. Remote KVM activation does not disable the local system keyboard, video, or mouse.
Remote KVM is not deactivated by local system input, unless the feature is disabled locally.
4.12.1.7 Usage
As the server is powered up, the remote KVM session displays the complete BIOS boot process.
The user is able interact with BIOS setup, change and save settings as well as enter and
interact with option ROM configuration screens.
At least two concurrent remote KVM sessions are supported. It is possible for at least two
different users to connect to same server and start remote KVM sessions
4.12.2 Media Redirection
The embedded web server provides a Java applet to enable remote media redirection. This may
be used in conjunction with the remote KVM feature, or as a standalone applet.
The media redirection feature is intended to allow system administrators or users to mount a
remote USB HDD or USB CD-ROM, floppy drive, or a USB flash disk as a remote device to the
server. Once mounted, the remote device appears just like a local device to the server, allowing
system administrators or users to install software (including operating systems), copy files,
update BIOS, and so on, or boot the server from this device.
The following capabilities are supported:

The operation of remotely mounted devices is independent of the local devices on the
server. Both remote and local devices are useable in parallel.

It is possible to boot all supported operating systems from the remotely mounted device
and to boot from disk IMAGE (*.IMG) and CD-ROM or DVD-ROM ISO files. See the
Tested/supported Operating System List for more information.

Media redirection shall support redirection for a minimum of two virtual devices
concurrently with any combination of devices. As an example, a user could redirect two
CD or two USB devices.

The media redirection feature supports multiple encryption algorithms, including RC4
and AES. The actual algorithm that is used is negotiated with the client based on the
client’s capabilities.

A remote media session is maintained even when the server is powered-off (in standby
mode). No restart of the remote media session is required during a server reset or power
on/off. An BMC reset (for example due to an BMC reset after BMC firmware update) will
require the session to be re-established

The mounted device is visible to (and useable by) managed system’s OS and BIOS in
both pre-boot and post-boot states.

The mounted device shows up in the BIOS boot order and it is possible to change the
BIOS boot order to boot from this remote device.

It is possible to install an operating system on a bare metal server (no OS present) using
the remotely mounted device. This may also require the use of KVM-r to configure the
OS during install.

USB storage devices will appear as floppy disks over media redirection. This allows for
the installation of device drivers during OS installation.
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If either a virtual floppy device is remotely attached during system boot, the virtual floppy
are presented as bootable devices. It is not possible to present only a single-mounted
device type to the system BIOS.
Note: When trying to attach a local floppy or local USB key drive, If it is in use by the operating
System or any other application it will fail to attach.
With Microsoft Windows 2008*, Microsoft Windows 2008 R2*, and Microsoft Windows 7* if a
“Windows Explorer” GUI is opened after the USB key has been installed in the local system,
you may not be able to attach the USB key as remote media.
With Microsoft Windows 2003*, and Microsoft Windows XP* if a “Windows Explorer” GUI is
opened after the USB Key has been installed in the local system and you then brower through
the USB Key, you may not be able to attach the USB Key as remote media.
4.12.2.1 Availability
The default inactivity timeout is 30 minutes and is not user-configurable.
Media redirection sessions persist across system reset but not across an AC power loss or
BMC reset.
4.12.2.2 Network Port Usage
The KVM and media redirection features use the following ports:

5120 – CD Redirection

5123 – FD Redirection

5124 – CD Redirection (Secure)

5127 – FD Redirection (Secure)

7578 – Video Redirection

7582 – Video Redirection (Secure)
4.12.3 Embedded Web server
Integrated BMC Base manageability provides an embedded web server and an OEMcustomizable web GUI which exposes the manageability features of the Integrated BMC base
feature set. It is supported over all on-board NICs that have management connectivity to the
Integrated BMC as well as an optional dedicated add-in management NIC. At least two
concurrent web sessions from up to two different users is supported. The embedded web user
interface shall support the following client web browsers:
54

Microsoft Internet Explorer 7.0*

Microsoft Internet Explorer 8.0*
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Microsoft Internet Explorer 9.0*

Mozilla Firefox 3.0*

Mozilla Firefox 3.5*

Mozilla Firefox 3.6*
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The embedded web user interface supports strong security (authentication, encryption, and
firewall support) since it enables remote server configuration and control. The user interface
presented by the embedded web user interface shall authenticate the user before allowing a
web session to be initiated. Encryption using 128-bit SSL is supported. User authentication is
based on user id and password.
The GUI presented by the embedded web server authenticates the user before allowing a web
session to be initiated. It presents all functions to all users but grays-out those functions that the
user does not have privilege to execute. (for example if a user does not have privilege to power
control, then the item shall be displayed in grey-out font in that user’s UI display). The web GUI
also provides a launch point for some of the advanced features, such as KVM and media
redirection. These features are grayed out in the GUI unless the system has been updated to
support these advanced features.
A partial list of additional features supported by the web GUI includes:

Presents all the Basic features to the users.

Power on/off/reset the server and view current power state.

Virtual front panel display and overall system health.

Provides embedded firmware version information.

Configuration of various IPMI parameters (LAN parameters, users, passwords, and so
on.)

Configuration of alerting (SNMP and SMTP).

Display system asset information for the product, board, and chassis.

Display of BMC-owned sensors (name, status, current reading, enabled thresholds),
including color-code status of sensors.

Automatic refresh of sensor data with a configurable refresh rate.

On-line help.

Display/clear SEL (display is in easily understandable human readable format).

Supports major industry-standard browsers (Internet Explorer and Mozilla Firefox).

Automatically logs out after user-configurable inactivity period.

The GUI session automatically times-out after a user-configurable inactivity period. By
default, this inactivity period is 30 minutes.

Embedded Platform Debug feature - Allow the user to initiate a “diagnostic dump” to a
file that can be sent to Intel® for debug purposes.

Display of power statistics (current, average, minimum, and maximum) consumed by
the server.
4.12.4 Data Center management Interface (DCM)
The DCMI Specification is an emerging standard that is targeted to provide a simplified
management interface for Internet Portal Data Center (IPDC) customers. It is expected to
become a requirement for server platforms which are targeted for IPDCs. DCMI is an IPMIbased standard that builds upon a set of required IPMI standard commands by adding a set of
DCMI-specific IPMI OEM commands. S2400LP platforms will be implementing the mandatory
DCMI features in the BMC FW (DCMI 1.1 Errata 1 compliance).
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4.12.5 Local Directory Authentication Protocol (LDAP)
The Lightweight Directory Access Protocol (LDAP) is an application protocol supported by the
BMC for the purpose of authentication and authorization. The BMC user connects with an LDAP
server for login authentication. This is only supported for non-IPMI logins including the
embedded web UI and SM-CLP. IPMI users/passwords and sessions are not supported
over LDAP.
LDAP can be configured (IP address of LDAP server, port, and so on.) through the BMC’s
Embedded Web UI. LDAP authentication and authorization is supported over the any NIC
configured for system management. The BMC uses a standard Open LDAP implementation for
Linux*.
4.12.6 Platform/Chassis Management
Within an IPMI 2.0 framework, the BMC Firmware provides functionality to support management
and control of several aspects of the platform operation. This includes:

Front Panel Support (for example, secure lock out of power and reset buttons and
System Status LED control)

Hardware/Sensor Monitoring (for example system voltages, thermal sensors, fans,
power supplies, and so on)

Power/Reset Control and Monitoring (for example, local and remote power/reset
control and power restore policy)

Hardware and Manufacturing Test Features

Asset Inventory and System Identification (for example, system GUID and FRU
management)

Thermal and Acoustics Management – The BMC firmware provides a comprehensive
set of fan control capabilities utilizing various system thermal sensors (for example CPU,
DIMMs, front panel thermal sensor). Additionally, the BMC participates in the memory
CLTT by pushing dim thermal data to the iMC in the CPU.

Power Management (Node Manager) Support – BMC firmware provides an external
(LAN) interface for a remote management console to communicate with the ME’s Node
Manager Functionality.
4.12.7 Thermal Control
The system shall support thermal management through open loop throttling (OLTT) or static
closed loop throttling (CLTT) of system memory based on availability of valid temperature
sensors on the installed memory DIMMs. The Integrated Memory Controller (IMC) dynamically
changes throttling levels to cap throttling based on memory and system thermal conditions as
determined by the system and DIMM power and thermal parameters. Support for CLTT on
mixed-mode DIMM populations (that is, some installed DIMMs have valid temp sensors and
some do not) is not supported. The BMC fan speed control functionality is related to the memory
throttling mechanism used.
The following terminology is used for the various memory throttling options:

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Static Open Loop Thermal Throttling (Static-OLTT): OLTT control registers are
configured by BIOS MRC remain fixed after post. The system does not change any of
the throttling control registers in the embedded memory controller during runtime.
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Static Closed Loop Thermal Throttling (Static-CLTT): CLTT control registers are
configured by BIOS MRC during POST. The memory throttling is run as a closed-loop
system with the DIMM temperature sensors as the control input. Otherwise, the system
does not change any of the throttling control registers in the embedded memory
controller during runtime.
4.12.7.1 Fan Speed Control
BIOS and BMC software work cooperatively to implement system thermal management support.
During normal system operation, the BMC will retrieve information from the BIOS and monitor
several platform thermal sensors to determine the required fan speeds.
In order to provide the proper fan speed control for a given system configuration, the BMC must
have the appropriate platform data programmed. Platform configuration data is programmed
using the FRUSDR utility during the system integration process and by System BIOS during
run time.
Table 23. Fan Profile Mapping
4.12.7.2 System Configuration Using FRUSDR Utility
The Field Replaceable Unit and Sensor Data Record Update Utility (FRUSDR utility) is a
program used to write platform-specific configuration data to NVRAM on the server board. It
allows the user to select which supported chassis (Intel® or Non-Intel) and platform chassis
configuration is used. Based on the input provided, the FRUSDR writes sensor data specific to
the configuration to NVRAM for the BMC controller to read each time the system is powered on.
4.12.8 Node Power On/Off Control
The BMC on each node will monitor its fans and temperature for a critical failure. When a critical
failure occurs the node will be powered down by BMC. When this occurs the node will need to
be manually powered on.
4.13 Intel®Intelligent Power Node Manager
4.13.1 Overview
Power management deals with requirements to manage processor power consumption and
manage power at the platform level to meet critical business needs. Node Manager (NM) is a
platform resident technology that enforces power capping and thermal-triggered power capping
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policies for the platform. These policies are applied by exploiting subsystem knobs (such as
processor P and T states) that can be used to control power consumption. NM enables data
center power management by exposing an external interface to management software through
which platform policies can be specified. It also implements specific data center power
management usage models such as power limiting, and thermal monitoring.
Note: Support for NM is product-specific, This section details how NM would be supported on
products that provide this capability.
The NM feature is implemented by a complementary architecture utilizing the ME, BMC, BIOS,
and an ACPI-compliant OS. The ME provides the NM policy engine and power control/limiting
functions (referred to as Node Manager or NM) while the BMC provides the external LAN link by
which external management software can interact with the feature. The BIOS provides system
power information utilized by the NM algorithms and also exports ASL code used by OSPM for
negotiating processor P and T state changes for power limiting. PMBus*-compliant power
supplies provide the capability to monitoring input power consumption, which is necessary to
support NM.
The NM architecture applicable to this generation of servers is defined by the NPTM
Architecture Specification v2.0. NPTM is an evolving technology that is expected to continue to
add new capabilities that will be defined in subsequent versions of the specification. The ME NM
implements the NPTM policy engine and control/monitoring algorithms defined in the
NPTM specification.
4.13.2 Features
NM provides feature support for policy management, monitoring and querying, alerts and
notifications, and an external interface protocol. The policy management features implement
specific IT goals that can be specified as policy directives for NM. Monitoring and querying
features enable tracking of power consumption. Alerts and notifications provide the foundation
for automation of power management in the data center management stack. The external
interface specifies the protocols that must be supported in this version of NM.
The role of BMC in Node Manager will include:

External communication links

Command passing through BMC

Alerting

BIOS-BMC-ME communication
4.14 Management Engine (ME)
4.14.1 Overview
The Intel® Server Platform Services (SPS) is a set of manageability services provided by the
firmware executing on an embedded ARC controller within the IOH. This management controller
is also commonly referred to as the Management Engine (ME). The functionality provided by the
SPS firmware is different from Intel® Active Management Technology (Intel® AMT or AT)
provided by the ME on client platforms.
Server Platform Services (SPS) are value-added platform management options that enhance
the value of Intel platforms and their component ingredients (CPUs, chipsets, and I/O
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components). Each service is designed to function independently wherever possible, or grouped
together with one or more features in flexible combinations to allow OEMs to differentiate
platforms.
4.14.2 BMC – Management Engine (ME) Distributed Model
The Intel® Server Board S2400LP covered in this specification will require Node Manager 2.0
(NM2.0) support. The following management architecture would need to be supported on the
baseboard to meet product and validation requirements. The NM 2.0 functionality is provided by
the Intel® C600 PCH Management Engine (ME).
The server management architecture is a partitioned model which places the Management
Engine, which is an embedded controller in the Intel® C600 PCH, in between the BMC and the
processors. In this architecture, the PCH Management Engine is the owner of the PECI 3.0 bus
and the ServerEngines* Pilot III BMC communicates with the ME through an SMBus*
connection (SMLINK 0.) The ME provides PECI proxy support that allows the ServerEngines*
Pilot III BMC firmware to access processor functions available on the PECI bus.
The primary function of ME is to implement the NM 2.0 feature set. In this architectural model,
the ServerEngines* Pilot III BMC provides the external (LAN) interface to ME in the form of IPMI
bridging. A remote Node Manager application would establish a management session with the
ServerEngines* Pilot III BMC which in turn would bridge IPMI commands through the secondary
IPMB to the ME. In this scenario, the ServerEngines* Pilot III BMC simply acts as a proxy for
this communication pipe. The ME may also generate alerts to the ServerEngines* Pilot III BMC,
which may log these into the system SEL and/or output them to the remote application in the
form of IPMI LAN alerts.
The ServerEngines* Pilot III BMC needs access to various system registers in the processor
core silicon and integrated memory controller subsystem. Examples include Processor core and
Memory DIMMs temperature information. The ServerEngines* Pilot III BMC requires this
information as input into its fan speed control algorithms. The ServerEngines* Pilot III BMC
accesses these registers through the secondary IPMB bus connection to ME. Depending on the
particular data or register access needed, this is done using either the ME’s PECI proxy
functionality or through an abstracted data construct provided by the ME.
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Also in this architecture, both the ServerEngines* Pilot III BMC and the ME are connected to the
system power supplies through a common PMBus* (SMBUS* physical) connection (SMLINK 1.)
The ME accesses the system power supplies in support of various NM 2.0 features. The
ServerEngines* Pilot III BMC monitors the power supplies in support of various power-related
telemetry and status information that is exposed as IPMI sensors.
Figure 19. Management Engine Distribution Model
4.14.3 ME System Management Bus (SMBus*) Interface

The ME uses the SMLink0 on the SSB in multi-master mode as a dedicated bus for
communication with the BMC using the IPMB protocol. The PCSD BMC FW considers
this a secondary IPMB bus and runs at 400 kHz.

The ME uses the SMLink1 on the SSB in multi-master mode bus for communication with
PMBus* devices in the power supplies for support of various NM-related features. This
bus is shared with the BMC, which polls these PMBus*power supplies for sensor
monitoring purposes (for example power supply status, input power, and so on.). This
bus runs at 100 KHz.

The Management Engine has access to the “Host SMBus*”.
4.14.4 BMC - Management Engine Interaction
Management Engine-BMC interactions include the following:
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
BMC stores sensor data records for ME-owned sensors.

BMC participates in ME firmware update.
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BMC initializes ME-owned sensors based on SDRs.

BMC receives platform event messages sent by the ME.

BMC notifies ME of POST completion.

BMC may be queried by the ME for inlet temperature readings.
4.14.5 ME Power and Firmware Startup
On Intel® Server Board S2400LP, the ME is on standby power. The ME FW will begin its startup
sequence at the same time that the BMC FW is booting. As the BMC FW is booting to a Linux
kernel and the ME FW uses an RTOS, the ME FW should always complete its basic
initialization before the BMC. The ME FW can be configured to send a notification message to
the BMC. After this point, the ME FW is ready to process any command requests from the BMC.
In S0/S1 power states, all ME FW functionality is supported. Some features, such as power
limiting, are not supported in S3/S4/S5 power states. Refer to ME FW documentation for details
on what is not supported while in the S3/S4/S5 states.
The ME FW uses a single operational image with a limited-functionality recovery image. In order
to upgrade an operational image, a boot to recovery image must be performed. The ME FW
does not support an IPMI update mechanism except for the case that the system is configured
with a dual-ME (redundant) image. In order to conserve flash space, which the ME FW shares
with BIOS, PCSD systems only support a single ME image. For this case, ME update is only
supported by means of BIOS performing a direct update of the flash component. The recovery
image only provides the basic functionality that is required to perform the update; therefore
other ME FW features are not functional therefore when the update is in progress.
4.14.6 SmaRT/CLST
The power supply optimization provided by SmaRT/CLST relies on a platform HW capability as
well as ME FW support. When a PMBus*-compliant power supply detects insufficient input
voltage, an over current condition, or an over-temperature condition, it will assert the SMBAlert#
signal on the power supply SMBus* (that is, the PMBus*). Through the use of external gates,
this results in a momentary assertion of the PROCHOT# and MEMHOT# signals to the
processors, thereby throttling the processors and memory. The ME FW also sees the
SMBAlert# assertion, queries the power supplies to determine the condition causing the
assertion, and applies an algorithm to either release or prolong the throttling, based on the
situation.
System power control modes include:

SmaRT: Low AC input voltage event; results in a onetime momentary throttle for
each event to the maximum throttle state.

Electrical Protection CLST: High output energy event; results in a throttling hiccup
mode with fixed maximum throttle time and a fix throttle release ramp time.

Thermal Protection CLST: High power supply thermal event; results in a throttling
hiccup mode with fixed maximum throttle time and a fix throttle release ramp time.
When the SMBAlert# signal is asserted, the fans will be gated by HW for a short period
(~100ms) to reduce overall power consumption. It is expected that the interruption to the fans
will be of short enough duration to avoid false lower threshold crossings for the fan tach sensors;
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however, this may need to be comprehended by the fan monitoring FW if it does have this sideeffect.
4.15 Other Platform Management
The platform supports the following sleep states, S1 and S5. Within S0, the platform supports
additional lower power states, such as C1e and C6, for the CPU.
4.15.1 Wake On LAN (WOL)

Wake On LAN (WOL) is supported on both LAN ports and IOM LAN modules for all
supported Sleep states.

Wake on Ring is supported on the external Serial port only for all supported Sleep
states.

Wake on USB is supported on the rear and front panel USB ports for S1 only.

Wake on RTC is supported for all supported Sleep states.

Wake IPMI command is supported (BMC function no additional hardware
requirement) for all supported Sleep states.
4.15.2 PCI Express* Power management
L0 and L3 power management states are supported on all PCI Express* slots and embedded
end points.
4.15.3 PMBus*
Power supplies that have PMBus* 1.1 are supported and required to support Intel® Dynamic
Power Node Manager. Intel® Server Board S2400LP supports the features of Intel® Dynamic
Power Node Manager version 1.5 except the inlet temperature sensor.
4.15.4 Node Power policies
When working with Intel® Server Chassis H2000LP, the BMC on each node will monitor its fans
and temperature for critical failures. When there is a fan failure and a critical temperature event
at the same time the node will be powered down. When this occurs the node will need to be
manually powered back on.
Additional on Intel® Server Board S2400LP, the BMC on node3 and node 4 will monitor for a
power supply over current condition or power supply over temperature condition. If either of
these occurs the node need to be manually powered back on but if the over current or over
temperature event is detected again the node will be powered back off.
The shutdown policy setting is only show on node 3 and node 4, and is disabled by default. But
can be enabled or disabled in the BIOS setup Server Management page or by using the set
shut down Policy command.
4.16 BIOS Password Protection
The BIOS uses passwords to prevent unauthorized tampering with the server setup. Passwords
can restrict entry to the BIOS Setup, restrict use of the Boot Popup menu, and suppress
automatic USB device reordering.
There is also an option to require a Power On password entry in order to boot the system. If the
Power On Password function is enabled in Setup, the BIOS will halt early in POST to request a
password before continuing POST.
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Both Administrator and User passwords are supported by the BIOS. An Administrator password
must be installed in order to set the User password. The maximum length of a password is
14 characters. A password can have alphanumeric (a-z, A-Z, 0-9) characters and it is case
sensitive. Certain special characters are also allowed, from the following set:
! @ # $ % ^ & * ( ) - _ + = ?
The Administrator and User passwords must be different from each other. An error message will
be displayed if there is an attempt to enter the same password for one as for the other.
The use of “Strong Passwords” is encouraged, but not required. In order to meet the criteria for
a “Strong Password”, the password entered must be at least 8 characters in length, and must
include at least one each of alphabetic, numeric, and special characters. If a “weak” password is
entered, a popup warning message will be displayed, although the weak password will be
accepted.
Once set, a password can be cleared by changing it to a null string. This requires the
Administrator password, and must be done through BIOS Setup or other explicit means of
changing the passwords. Clearing the Administrator password will also clear the User password.
Alternatively, the passwords can be cleared by using the Password Clear jumper if necessary.
Resetting the BIOS configuration settings to default values (by any method) has no effect on the
Administrator and User passwords.
Entering the User password allows the user to modify only the System Time and System Date in
the Setup Main screen. Other setup fields can be modified only if the Administrator password
has been entered. If any password is set, a password is required to enter the BIOS setup.
The Administrator has control over all fields in the BIOS setup, including the ability to clear the
User password and the Administrator password.
It is strongly recommended that at least an Administrator Password be set, since not having set
a password gives everyone who boots the system the equivalent of Administrative access.
Unless an Administrator password is installed, any User can go into Setup and change BIOS
settings at will.
In addition to restricting access to most Setup fields to viewing only when a User password is
entered, defining a User password imposes restrictions on booting the system. In order to
simply boot in the defined boot order, no password is required. However, the F6 Boot popup
prompts for a password, and can only be used with the Administrator password. Also, when a
User password is defined, it suppresses the USB Reordering that occurs, if enabled, when a
new USB boot device is attached to the system. A User is restricted from booting in anything
other than the Boot Order defined in the Setup by an Administrator.
As a security measure, if a User or Administrator enters an incorrect password three times in a
row during the boot sequence, the system is placed into a halt state. A system reset is required
to exit out of the halt state. This feature makes it more difficult to guess or break a password.
In addition, on the next successful reboot, the Error Manager displays a Major Error code 0048,
which also logs a SEL event to alert the authorized user or administrator that a password
access failure has occurred
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4.17 Trusted Platform Module(TPM) Support
Trusted Platform Module (TPM) option is a hardware-based security device that addresses the
growing concern on boot process integrity and offers better data protection. TPM protects the
system start-up process by ensuring it is tamper-free before releasing system control to the
operating system. A TPM device provides secured storage to store data, such as security keys
and passwords. In addition, a TPM device has encryption and hash functions. The server board
implements TPM as per TPM PC Client Specifications, revision 1.2, by the Trusted Computing
Group (TCG).
A TPM device is optionally installed onto a high density 14-pin connector labeled “TPM” and is
secured from external software attacks and physical theft. A pre-boot environment, such as the
BIOS and operating system loader, uses the TPM to collect and store unique measurements
from multiple factors within the boot process to create a system fingerprint. This unique
fingerprint remains the same unless the pre-boot environment is tampered with. Therefore, it is
used to compare to future measurements to verify the integrity of the boot process.
After the system BIOS completes the measurement of its boot process, it hands off control to
the operating system loader and in turn to the operating system. If the operating system is TPMenabled, it compares the BIOS TPM measurements to those of previous boots to make sure the
system was not tampered with before continuing the operating system boot process. Once the
operating system is in operation, it optionally uses TPM to provide additional system and data
security (for example, Microsoft Vista* supports Bitlocker drive encryption).
4.17.1 TPM Security BIOS
The BIOS TPM support conforms to the TPM PC Client Specific – Implementation Specification
for Conventional BIOS, version 1.2, and to the TPM Interface Specification, version 1.2. The
BIOS adheres to the Microsoft Vista* BitLocker requirement. The role of the BIOS for TPM
security includes the following:





Measures and stores the boot process in the TPM microcontroller to allow a TPM
enabled operating system to verify system boot integrity.
Produces EFI and legacy interfaces to a TPM-enabled operating system for using TPM.
Produces ACPI TPM device and methods to allow a TPM-enabled operating system to
send TPM administrative command requests to the BIOS.
Verifies operator physical presence. Confirms and executes operating system TPM
administrative command requests.
Provides BIOS Setup options to change TPM security states and to clear TPM
ownership.
For additional details, refer to the TCG PC Client Specific Implementation Specification, the
TCG PC Client Specific Physical Presence Interface Specification, and the Microsoft BitLocker*
Requirement documents.
4.17.2 Physical Presence
Administrative operations to the TPM require TPM ownership or physical presence indication by
the operator to confirm the execution of administrative operations. The BIOS implements the
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operator presence indication by verifying the setup Administrator password.
A TPM administrative sequence invoked from the operating system proceeds as follows:
1. User makes a TPM administrative request through the operating system’s security
software.
2. The operating system requests the BIOS to execute the TPM administrative command
through TPM ACPI methods and then resets the system.
3. The BIOS verifies the physical presence and confirms the command with the operator.
4. The BIOS executes TPM administrative command(s), inhibits BIOS Setup entry and
boots directly to the operating system which requested the TPM command(s).
4.17.3 TPM Security Setup Options
The BIOS TPM Setup allows the operator to view the current TPM state and to carry out
rudimentary TPM administrative operations. Performing TPM administrative options through the
BIOS setup requires TPM physical presence verification.
Using BIOS TPM Setup, the operator can turn ON or OFF TPM functionality and clear the TPM
ownership contents. After the requested TPM BIOS Setup operation is carried out, the option
reverts to No Operation.
The BIOS TPM Setup also displays the current state of the TPM, whether TPM is enabled or
disabled and activated or deactivated. Note that while using TPM, a TPM-enabled operating
system or application may change the TPM state independent of the BIOS setup. When an
operating system modifies the TPM state, the BIOS Setup displays the updated TPM state.
The BIOS Setup TPM Clear option allows the operator to clear the TPM ownership key and
allows the operator to take control of the system with TPM. You use this option to clear security
settings for a newly initialized system or to clear a system for which the TPM ownership security
key was lost.
4.17.4 Security Screen
To enter the BIOS Setup, press the F2 function key during boot time when the OEM or Intel logo
displays. The following message displays on the diagnostics screen and under the Quiet Boot
logo screen:
Press <F2> to enter setup
When the Setup is entered, the Main screen displays. The BIOS Setup utility provides the
Security screen to enable and set the user and administrative passwords and to lock out the
front panel buttons so they cannot be used.
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5.
BIOS Setup Interface
5.1
HotKeys Supported During POST
Certain “HotKeys” are recognized during POST. A HotKey a key or key combination that is
recognized as an unprompted command input, that is, the operator is not prompted to press the
HotKey and typically the HotKey will be recognized even while other processing is in progress.
The Intel® Server Board S2400LP Family BIOS recognizes a number of HotKeys during POST.
After the OS is booted, HotKeys are the responsibility of the OS and the OS defines its own set
of recognized HotKeys.
Following are the POST HotKeys with the functions they cause to be performed.
Table 24. POST HotKeys Recognized
HotKey Combination
<F2>
5.2
Function
Enter Setup
<F6>
Pop up BIOS Boot Menu
<F12>
Network boot
POST Logo/Diagnostic Screen
The logo/Diagnostic Screen displays in one of two forms:

If Quiet Boot is enabled in the BIOS setup, a logo splash screen displays. By default,
Quiet Boot is enabled in the BIOS setup. If the logo displays during POST, press <Esc>
to hide the logo and display the diagnostic screen.
 If a logo is not present in the flash ROM or if Quiet Boot is disabled in the system
configuration, the POST Diagnostic Screen is displayed with a summary of system
configuration information.
The diagnostic screen displays the following information:













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BIOS version (ID)
BMC firmware version
SDR version
ME firmware version
Platform ID
System memory detected (total size of all installed DDR3 DIMMs)
Current memory speed (currently configured memory operating frequency)
Processor information (Intel Brand String identifying type of processor and nominal
operating frequency, and number of physical processors identified)
Keyboards detected, if any attached
Mouse devices detected, if any attached
Instructions showing hotkeys for going to Setup, going to popup Boot Menu, starting
Network Boot
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5.3
BIOS Setup Interface
BIOS Boot Pop-up Menu
The BIOS Boot Specification (BBS) provides a Boot Pop-up menu that can be invoked by
pressing the <F6> key during POST. The BBS Pop-up menu displays all available boot devices.
The boot order in the pop-up menu is not the same as the boot order in the BIOS setup. The
pop-up menu simply lists all of the available devices from which the system can be booted, and
allows a manual selection of the desired boot device.
When an Administrator password is installed in Setup, the Administrator password will be
required in order to access the Boot Pop-up menu using the <F6> key. If a User password is
entered, the Boot Pop-up menu will not even appear – the user will be taken directly to the Boot
Manager in the Setup, where a User password allows only booting in the order previously
defined by the Administrator.
5.4
BIOS Setup Utility
The BIOS Setup utility is a text-based utility that allows the user to configure the system and
view current settings and environment information for the platform devices. The Setup utility
controls the platform's built-in devices, the boot manager, and error manager.
The BIOS Setup interface consists of a number of pages or screens. Each page contains
information or links to other pages. The advanced tab in Setup displays a list of general
categories as links. These links lead to pages containing a specific category’s configuration.
The following sections describe the look and behavior for the platform setup.
5.4.1 BIOS Setup Operation
The BIOS Setup utility has the following features:




Localization – The Intel® Server Board BIOS is only available in English. However, BIOS
Setup uses the Unicode standard and is capable of displaying data and input in Setup
fields in all languages currently included in the Unicode standard.
Console Redirection – BIOS Setup is functional through Console Redirection over
various terminal emulation standards. This may limit some functionality for compatibility,
for example, usage of colors or some keys or key sequences or support of pointing
devices.
Setup screens are designed to be displayable in an 80-character x 24-line format in
order to work with Console Redirection, although that screen layout should display
correctly on any format with longer lines or more lines on the screen.
Password protection – BIOS Setup may be protected from unauthorized changes by
setting an Administrative Password in the Security screen. When an Administrative
Password has been set, all selection and data entry fields in Setup (except System Time
and Date) are grayed out and cannot be changed unless the Administrative Password
has been entered.
Note: If an Administrative Password has not been set, anyone who boots the system to Setup
has access to all selection and data entry fields in Setup and can change any of them.
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5.4.1.1 Setup Page Layout
The Setup page layout is sectioned into functional areas. Each occupies a specific area of the
screen and has dedicated functionality. The following table lists and describes each
functional area.
The Setup page is designed to a format of 80 x 24 (24 lines of 80 characters each). The typical
display screen in a Legacy mode or in a terminal emulator mode is actually 80 characters by 25
lines, but with “line wrap” enabled (which it usually is) the 25th line cannot be used with the
Setup page.
Table 25. BIOS Setup Page Layout
Functional Area
Title (Tab) Bar
Description
The Title Bar is located at the top of the screen and displays “Tabs” with the titles of
the top-level pages, or screens that can be selected. Using the left and right arrow
keys moves from page to page through the Tabs.
When there are more Tabs than can be displayed on the Title (Tab) Bar, they will
scroll off to the left or right of the screen and temporarily disappear from the visible
Title Bar. Using the arrow keys will scroll them back onto the visible Title Bar. When
the arrow keys reach either end of the Title Bar, they will “wrap around” to the other
end of the Title Bar.
For multi-level hierarchies, this shows only the top-level page above the page which
the user is currently viewing. The Page Title gives further information.
Page Title
In a multi-level hierarchy of pages beneath one of the top-level Tabs, the Page Title
identifying the specific page which the user is viewing is located in the upper left
corner of the page. Using the <ESC> (Escape) key will return the user to the higher
level in the hierarchy, until the top-level Tab page is reached.
Setup Item List
The Setup Item List is a set of control entries and informational items. The list is
displayed in two columns. For each item in the list:

The left column of the list contains Prompt String (or Label String), a character
string which identifies the item. The Prompt String may be up to 34 characters
long in the 80 x 24 page format.

The right column contains a data field which may be an informational data
display, a data input field, or a multiple choice field. Data input or multiplechoice fields are demarcated by square brackets (“[....]”. This field may be up to
90 characters long, but only the first 22 characters can be displayed on the 80
x 24 page (24 characters for an informational display-only field).
The operator navigates up and down the right hand column through the available
input or choice fields.
A Setup Item may also represent a selection to open a new screen with a further
group of options for specific functionality. In this case, the operator navigates to the
desired selection and presses <Enter> to go to the new screen.
Item-Specific Help Area
The Item-specific Help Area is located on the right side of the screen and contains
Help Text specific to the highlighted Setup Item. Help information may include the
meaning and usage of the item, allowable values, effects of the options, and so on.
The Help Area is a 29 character by 11 line section of the 80 x 24 page. The Help
Text may have explicit line-breaks within it. When the text is longer than 29
characters, it is also broken to a new line, dividing the text at the last space (blank)
th
character before the 29 character. An unbroken string of more than 29 character
th
will be arbitrarily wrapped to a new line after the 29 character. Text that extends
th
beyond the end of the 11 line will not be displayed.
Keyboard Command Area
The Keyboard Command Area is located at the bottom right of the screen and
continuously displays help for keyboard special keys and navigation keys.
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BIOS Setup Interface
5.4.1.2 Entering BIOS Setup
To enter the BIOS Setup using a keyboard (or emulated keyboard), press the <F2> function key
during boot time when the OEM or Intel logo is displayed. The following message is displayed
on the diagnostics screen and under the Quiet Boot logo screen:
Press <F2> to enter setup
When the Setup Utility is entered, the Main screen is displayed. However, serious errors cause
the system to display the Error Manager screen instead of the Main screen.
It is also possible to cause a boot to Setup using an IPMI 2.0 command “Get/Set System Boot
Options”. For details on that capability, see the explanation in the IPMI description.
5.4.1.3 Setup Navigation Keyboard Commands
The bottom right portion of the Setup screen provides a list of commands that are used to
navigate through the Setup utility. These commands are displayed at all times.
Each Setup menu page contains a number of features. Each feature is associated with a value
field, except those used for informative purposes. Each value field contains configurable
parameters. Depending on the security option chosen and in effect by the password, a menu
feature’s value may or may not be changed. If a value cannot be changed, its field is made
inaccessible and appears grayed out.
Table 26. BIOS Setup: Keyboard Command Bar
Key
<Enter>
Option
Execute
Command
Description
The <Enter> key is used to activate submenus when the selected feature is a
submenu, or to display a pick list if a selected option has a value field, or to select a
subfield for multi-valued features like time and date. If a pick list is displayed, the
<Enter> key selects the currently highlighted item, undoes the pick list, and returns
the focus to the parent menu.
<Esc>
Exit
The <Esc> key provides a mechanism for backing out of any field. When the <Esc>
key is pressed while editing any field or selecting features of a menu, the parent
menu is re-entered.
When the <Esc> key is pressed in any submenu, the parent menu is re-entered.
When the <Esc> key is pressed in any major menu, the exit confirmation window is
displayed and the user is asked whether changes can be discarded. If “No” is
selected and the <Enter> key is pressed, or if the <Esc> key is pressed, the user is
returned to where they were before <Esc> was pressed, without affecting any
existing settings. If “Yes” is selected and the <Enter> key is pressed, the setup is
exited and the BIOS returns to the main System Options Menu screen.

Select Item
The up arrow is used to select the previous value in a pick list, or the previous
option in a menu item's option list. The selected item must then be activated by
pressing the <Enter> key.
Select Item
The down arrow is used to select the next value in a menu item’s option list, or a
value field’s pick list. The selected item must then be activated by pressing the
<Enter> key.
Select Menu
The left and right arrow keys are used to move between the major menu pages.
The keys have no effect if a sub-menu or pick list is displayed.
<Tab>
Select Field
The <Tab> key is used to move between fields. For example, <Tab> can be used
to move from hours to minutes in the time item in the main menu.
-
Change Value
The minus key on the keypad is used to change the value of the current item to the
previous value. This key scrolls through the values in the associated pick list
without displaying the full list.
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Key
Intel®Server Boards S2400LP TPS
+
Option
Change Value
Description
The plus key on the keypad is used to change the value of the current menu item
to the next value. This key scrolls through the values in the associated pick list
without displaying the full list. On 106-key Japanese keyboards, the plus key has a
different scan code than the plus key on the other keyboards, but will have the
same effect.
<F9>
Setup Defaults
Pressing the <F9> key causes the following to display:
Load Optimized Defaults?
Yes No
If “Yes” is highlighted and <Enter> is pressed, all Setup fields are set to their
default values. If “No” is highlighted and <Enter> is pressed, or if the <Esc> key is
pressed, the user is returned to where they were before <F9> was pressed without
affecting any existing field values.
<F10>
Save and Exit
Pressing the <F10> key causes the following message to display:
Save configuration and reset?
Yes
No
If “Yes” is highlighted and <Enter> is pressed, all changes are saved and the Setup
is exited. If “No” is highlighted and <Enter> is pressed, or the <Esc> key is
pressed, the user is returned to where they were before <F10> was pressed
without affecting any existing values.
5.4.1.4 Setup Screen Menu Selection Bar
The Setup Screen Menu selection bar is located at the top of the BIOS Setup Utility screen. It
displays tabs showing the major screen selections available to the user. By using the left and
right arrow keys, the user can select the listed screens. Some screen selections are out of the
visible menu space, and become available by scrolling to the left or right of the current
selections displayed.
5.4.2 BIOS Setup Utility Screens
The following sections describe the screens available in the BIOS Setup utility for the
configuration of the server platform.
For each of these screens, there is an image of the screen with a list of Field Descriptions which
describe the contents of each item on the screen. Each item on the screen is hyperlinked to the
relevant Field Description. Each Field Description is hyperlinked back to the screen image.
These lists follow the following guidelines:
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
The text heading for each Field Description is the actual text as displayed on the BIOS
Setup screen. This screen text is a hyperlink to its corresponding Field Description.

The text shown in the Option Values and Help Text entries in each Field Description are
the actual text and values are displayed on the BIOS Setup screens.

In the Option Values entries, the text for default values is shown with an underline.
These values do not appear underline on the BIOS Setup screen. The underlined text in
this document is to serve as a reference to which value is the default value.
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BIOS Setup Interface

The Help Text entry is the actual text which appears on the screen to accompany the
item when the item is the one in focus (active on the screen).

The Comments entry provides additional information where it may be helpful. This
information does not appear on the BIOS Setup screens.

Information enclosed in angular brackets (< >) in the screen shots identifies text that can
vary, depending on the option(s) installed. For example, <Amount of memory installed>
is replaced by the actual value for “Total Memory”.

Information enclosed in square brackets ([ ]) in the tables identifies areas where the user
must type in text instead of selecting from a provided option.

Whenever information is changed (except Date and Time), the systems requires a save
and reboot to take place in order for the changes to take effect. Alternatively, pressing
<ESC> discards the changes and resumes POST to continue to boot the system
according to the boot order set from the last boot.
5.4.2.1 Map of Screens and Functionality
There are a number of screens in the entire Setup collection. They are organized into major
categories. Each category has a hierarchy beginning with a top-level screen from which lowerlevel screens may be selected. Each top-level screen appears as a tab, arranged across the top
of the Setup screen image of all top-level screens.
There are more categories than will fit across the top of the screen, so at any given time there
will be some categories which will not appear until the user has scrolled across the tabs which
are present.
The categories and the screens included in each category are listed below, with links to each of
the screens named.
Table 27. Screen Map
Categories (Top Tabs)
Main Screen (Tab)
Second Level Screens
Third Level Screens
Advanced Screen (Tab)

Processor Configuration

Power and Performance

Memory Configuration


Mass Storage Controller
Configuration

PCI Configuration


Revision 2.0
Memory RAS and Performance
Configuration
NIC Configuration
Serial Port Configuration
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Categories (Top Tabs)

Second Level Screens
USB Configuration
Third Level Screens
System Acoustic and
Performance Configuration

Security Screen (Tab)
Server Management Screen
(Tab)

Console Redirection

System Information

BMC LAN Configuration
Boot Options Screen (Tab)

Hard Disk Order

Network Device Order

Delete EFI Boot Option
Boot Manager Screen (Tab)
Error Manager Screen (Tab)
Save and Exit Screen
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(Tab)
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BIOS Setup Interface
5.4.2.2 Main Screen (Tab)
The Main Screen is the first screen that appears when the BIOS Setup configuration utility is
entered, unless an error has occurred. If an error has occurred, the Error Manager Screen
appears instead.
Main
Advanced
Security
Server Management
Boot Options
Logged in as:
Administrator/User
Platform ID
<Platform Identification String>
Boot Manager
System BIOS
BIOS Version
<Platform.86B.xx.yy.zzzz>
Build Date
<MM/DD/YYYY>
Memory
Total Memory
<Amount of memory installed>
Quiet Boot
Enabled/Disabled
POST Error Pause
Enabled/Disabled
System Date
[Day MM/DD/YYYY]
System Time
[HH:MM:SS]
Figure 20. Main Screen
Table 28. Setup Utility – Main Screen Fields
Setup Item
Logged in as
Options
Help Text
Comments
Information only. Displays
password level that setup is
running in: Administrator or User.
With no passwords set,
Administrator is the default mode.
Information only. Displays the
Platform ID: S2400LP
Platform ID
System BIOS
Information only. Displays the
current BIOS version.
Version
xx = major release version
yy = minor release version
zzzz = release number
Information only. Displays the
current BIOS build date.
Build Date
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Setup Item
Memory
Intel®Server Boards S2400LP TPS
Options
Help Text
Information only. Displays the
total physical memory installed in
the system, in MB or GB. The term
physical memory indicates the total
memory discovered in the form of
installed DDR3 DIMMs.
Total Memory
Quiet Boot
Comments
Enabled
Disabled
[Enabled] – Display the logo screen
during POST.
[Disabled] – Display the diagnostic
screen during POST.
POST Error Pause
Enabled
Disabled
[Enabled] – Go to the Error
Manager for critical POST errors.
[Disabled] – Attempt to boot and do
not go to the Error Manager for
critical POST errors.
System Date
[Day of week
MM/DD/YYYY]
If enabled, the POST Error Pause
option takes the system to the error
manager to review the errors when
major errors occur. Minor and fatal
error displays are not affected by
this setting.
System Date has configurable
fields for Month, Day, and Year.
Use [Enter] or [Tab] key to select
the next field.
Use [+] or [-] key to modify the
selected field.
System Time
[HH:MM:SS]
System Time has configurable
fields for Hours, Minutes, and
Seconds.
Hours are in 24-hour format.
Use [Enter] or [Tab] key to select
the next field.
Use [+] or [-] key to modify the
selected field.
5.4.2.3 Advanced Screen (Tab)
The Advanced screen provides an access point to configure several groups of options. On this
screen, the user can select the option group to be configured. Configuration actions are
performed on the selected screen, and not directly on the Advanced screen.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Advanced screen is
selected.
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Main
Advanced
Security
BIOS Setup Interface
Server Management
Boot Options
Boot Manager
► Processor
► Power & Performance
► Memory Configuration
► Mass Storage Controller Configuration
► PCI Configuration
► Serial Port Configuration
► USB Configuration
► System Acoustic and Performance Configuration
Figure 21. Advanced Screen
Table 29. Setup Utility – Advanced Screen Display Fields
Setup Item
Processor Configuration
Help Text
View/Configure processor information and
settings.
Power and Performance
View/Configure power and performance
policy
Memory Configuration
View/Configure memory information and
settings.
Mass Storage Controller Configuration
View/Configure mass storage controller
information and settings.
View/Configure PCI information and
settings.
PCI Configuration
Serial Port Configuration
View/Configure serial port information and
settings.
USB Configuration
View/Configure USB information and
settings.
System Acoustic and Performance
Configuration
View/Configure system acoustic and
performance information and settings.
5.4.2.4 Processor Configuration
The Processor Configuration screen displays the processor identification and microcode level,
core frequency, cache sizes, Intel® QuickPath Interconnect information for all processors
currently installed. It also allows the user to enable or disable a number of processor options.
To access this screen from the Main screen, select Advanced > Processor Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
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Advanced
Processor Configuration
Processor ID
Processor ID
Processor 1 Version
Processor 2 Version
CPU 1
CPU 2
<CPUID>*
<CPUID>
<Proc Freq>
<Proc Freq>
<Rev data>
<Rev data>
<L1 Cache Size>
<L1 Cache Size>
<L2 Cache Size>
<L2 Cache Size>
<L3 Cache Size>
<L3 Cache Size>
<ID string from Processor 1>
<ID string from Processor 2>
Current Intel®QPI Link Speed
Intel®QPI Link Frequency
Intel®QPI Frequency Select
Intel®Turbo Boost Technology
Slow/Fast
Unknown GT/s/6.4 GT/s/7.2 GT/s/8.0 GT/s
Auto Max/6.4 GT/s/7.2 GT/s/8.0 GT/s
Enabled/Disabled
Processor Frequency
Microcode Revision
L1 Cache RAM
L2 Cache RAM
L3 Cache RAM
Enhanced Intel®SpeedStep®Tech
Processor C3
Processor C6
Intel®Hyper-Threading Tech
Active Processor Cores
Execute Disable Bit
Intel®Virtualization Technology
Intel®VT for Direct I/O
Interrupt Remapping
Coherency Support
ATS Support
Pass-through DMA Support
Enhanced Error Containment Mode
MLC Streamer
MLC Spatial Prefetcher
DCU Data Prefetcher
DCU Instruction Prefetcher
Direct Cache Access (DCA)
SMM Wait Timeout
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
All/1/2/3/4/5/6/7
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
[20 – 3000ms, 20 is default]
Figure 22. Processor Configuration Screen
Table 30. Setup Utility — Processor Configuration Screen Fields
Setup Item
Processor ID
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Options
Help Text
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Comments
Information only. Processor
CPUID
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Setup Item
Processor Frequency
BIOS Setup Interface
Options
Help Text
Comments
Information only. Current
frequency of the processor.
Microcode Revision
Information only. Revision of
the loaded microcode.
L1 Cache RAM
Information only. Size of the
Processor L1 Cache.
L2 Cache RAM
Information only. Size of the
Processor L2 Cache
L3 Cache RAM
Information only. Size of the
Processor L3 Cache.
Processor Version
Information only. ID string
from the Processor.
Processor 1 Version
Information only. Brand ID
string of processor with
CPUID instruction.
Processor 2 Version
Information only. Brand ID
string of processor with
CPUID instruction.
Current QPI Link Speed
Information only. Current
speed that the QPI Link is
using.
QPI Link Frequency
Information only. Current
frequency that the QPI Link is
operating.
Current QPI Frequency
Select
Auto Max
6.4 GT/s
7.2 GT/s
8.0 GT/s
®
Allows for selecting the Intel QuickPath
Interconnect Frequency. Recommended to
leave in [Auto Max] so that BIOS can select
®
the highest common Intel QuickPath
Interconnect frequency.
Lowering the QPI frequency
may improve performance per
watt for some processing
loads and on certain
benchmarks. [Auto Max] will
give the maximum QPI
performance available.
Note: Appears only on multisocket boards.
When a multi-socket board
has only one processor
installed, this will be grayed
out, with the previous value
remaining displayed.
Changes in QPI Link
Frequency will not take effect
until the system reboots, so
this will not immediately
change the QPI Link
Frequency display. Changing
QPI Link Frequency does not
affect the QPI Link Speed.
®
Intel Turbo Boost
Technology
Revision 2.0
Enabled
Disabled
®
Intel Turbo Boost Technology allows the
processor to automatically increase its
frequency if it is running below power,
temperature, and current specifications.
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This option is only visible if
the processor in the system
®
support Intel Turbo Boost
Technology.
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BIOS Setup Interface
Setup Item
Enhanced Intel
®
SpeedStep Technology
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Options
Enabled
Disabled
Help Text
®
Enhanced Intel SpeedStep Technology
allows the system to dynamically adjust
processor voltage and core frequency, which
can result in decreased average power
consumption and decreased average heat
production.
Comments
When Disabled, the
processor setting reverts to
running at Max TDP Core
Frequency (rated frequency).
Contact your OS vendor regarding OS
support of this feature.
Processor C3
Enabled
Disabled
Processor C6
Enabled
Disabled
®
Intel Hyper-Threading
Technology
Enabled
Disabled
Enable/Disable Processor C3 (ACPI C2/C3)
report to OS
This is normally Disabled,
but can be Enabled for
improved performance on
certain benchmarks and in
certain situations.
Enable/Disable Processor C6 (ACPI C3)
report to OS
This is normally Enabled but
can be Disabled for improved
performance on certain
benchmarks and in certain
situations.
®
Intel HT Technology allows multithreaded
software applications to execute threads in
parallel within each processor.
Contact your OS vendor regarding OS
support of this feature.
Active Processor Cores
All
1
Number of cores to enable in each
processor package.
The numbers of cores that
appear as selections
depends on the number of
cores available in the
processors installed. Boards
may have as many as 8
cores in each of 1, 2, or 4
processors. The same
number of cores must be
active in each processor
package.
Execute Disable Bit can help prevent certain
classes of malicious buffer overflow attacks.
This option is only visible if all
processors installed in the
system support the Execute
Disable Bit. The OS and
applications installed must
support this feature in order
for it to be enabled.
2
3
4
5
6
7
Execute Disable Bit
Enabled
Disabled
®
Intel Virtualization
Technology
Enabled
Disabled
®
Intel Virtualization Technology allows a
platform to run multiple operating systems
and applications in independent partitions.
Note: A change to this option requires the
system to be powered off and then back on
before the setting takes effect.
Enabled
®
Intel Virtualization
Technology for Directed
I/O
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Disabled
This option is only visible if all
processors installed in the
®
system support Intel HyperThreading Technology.
®
Enable/Disable Intel Virtualization
®
Technology for Directed I/O. (Intel VT-d)
Report the I/O device assignment to VMM
through DMAR ACPI Tables
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This option is only visible if all
processors installed in the
®
system support Intel VT. The
software configuration
installed on the system must
support this feature in order
for it to be enabled.
This option is only visible if all
processors installed in the
®
system support Intel VT-d.
The software configuration
installed on the system must
support this feature in order
for it to be enabled.
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Setup Item
Interrupt Remapping
Options
Enabled
Disabled
Coherency Support
Enabled
Disabled
ATS Support
Enabled
Disabled
Pass-through DMA
Support
Enabled
Enhanced Error
Containment Mode
Enabled
MLC Streamer
Enabled
Disabled
Help Text
®
Enable/Disable Intel VT-d Interrupt
Remapping support. For some processors,
this option may be "always enabled".
®
Enable/Disable Intel VT-d Coherency
support.
Comments
This option only appears when
®
Intel Virtualization
Technology for Directed I/O is
Enabled. For some processors
this will be enabled
unconditionally whenever
®
Intel VT-d is enabled. In that
case, this option will be shown
as "Enabled", and grayed out
and not changeable.
This option only appears
®
when Intel Virtualization
Technology for Directed I/O is
Enabled.
®
This option only appears
®
when Intel Virtualization
Technology for Directed I/O is
Enabled.
®
This option only appears
®
when Intel Virtualization
Technology for Directed I/O is
Enabled. For some
processors this will be
enabled unconditionally
®
whenever Intel VT-d is
enabled. In that case, this
option will be shown as
"Enabled", and grayed out
and not changeable.
Enable/Disable Intel VT-d Address
Translation Services (ATS) support.
Enable/Disable Intel VT-d Pass-through
DMA support. For some processors, this
option may be "always enabled".
Enhanced Error Containment
(Data Poisoning) is not
supported by all models of
processors, and this option
will not appear unless all
installed processors support
Enhanced Error Containment.
This option globally enables
or disables both Core and
Uncore Data Poisoning, for
processors which support
them
Disabled
Disabled
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MLC Streamer is a speculative prefetch unit
within the processor(s)
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MLC Streamer is normally
Enabled, for best efficiency in
L2 Cache and Memory
Channel use, but disabling it
may improve performance for
some processing loads and
on certain benchmarks.
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BIOS Setup Interface
Setup Item
MLC Spatial Prefetcher
Intel®Server Boards S2400LP TPS
Options
Enabled
Disabled
Help Text
[Enabled] – Fetches adjacent cache line
(128 bytes) when required data is not
currently in cache.
[Disabled] – Only fetches cache line with
data required by the processor (64 bytes).
DCU Data Prefetcher
Enabled
Disabled
The next cache line will be prefetched into
L1 data cache from L2 or system memory
during unused cycles if it sees that the
processor core has accessed several bytes
sequentially in a cache line as data.
[Disabled] – Only fetches cache line with
data required by the processor (64 bytes).
DCU Instruction
Prefetcher
Enabled
Direct Cache Access
(DCA)
Enabled
SMM Wait Timeout
20
Disabled
Disabled
Comments
MLC Spatial Prefetcher is
normally Enabled, for best
efficiency in L2 Cache and
Memory Channel use, but
disabling it may improve
performance for some
processing loads and on
certain benchmarks.
DCU Data Prefetcher is
normally Enabled, for best
efficiency in L1 Data Cache
and Memory Channel use,
but disabling it may improve
performance for some
processing loads and on
certain benchmarks.
The next cache line will be prefetched into
L1 instruction cache from L2 or system
memory during unused cycles if it sees that
the processor core has accessed several
bytes sequentially in a cache line as data.
DCU Data Prefetcher is
normally Enabled, for best
efficiency in L1 I Cache and
Memory Channel use, but
disabling it may improve
performance for some
processing loads and on
certain benchmarks.
Allows processors to increase the I/O
performance by placing data from I/O
devices directly into the processor cache.
System performance is
usually best with Direct
Cache Access Enabled. In
certain unusual cases,
disabling this may give
improved results.
Millisecond timeout waiting for BSP and SPs
to enter SMM. Range is 20ms to 3000ms
Amount of time to allow for
the SMI Handler to respond to
an SMI. If exceeded, BMC
generates an SMI Timeout
and resets the system
5.4.2.5 Power and Performance Policy
The Power and Performance screen allows the user to specify a profile which is optimized in the
direction of either reduced power consumption or increased performance.
To access this screen from the Main screen, select Advanced > Power and Performance. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
80
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Advanced
Power & Performance
CPU Power and Performance Policy
Performance / Balanced Performance /
Balanced Power / Power
[Performance] Optimization is strongly toward performance, even at the expense of energy efficiency.
[Balanced Performance] Weights optimization toward performance, while conserving energy.
[Balanced Power] Weights optimization toward energy conservation, with good performance.
[Power] Optimization is strongly toward energy efficiency, even at the expense of performance.
Figure 23. Power and Performance Configuration Screen
Table 31. Setup Utility – Power and Performance Configuration Screen Fields
Setup Item
Options
CPU Power and
Performance
Performance Policy
Comments
Optimization is strongly toward performance, even at the expense
of energy efficiency.
Balanced Performance
Weights optimization toward performance, while conserving energy.
Balanced Power
Weights optimization toward energy conservation, with good
performance
Power
Optimization is strongly toward energy efficiency, even at the
expense of performance.
When the user selects a “Power and Performance Policy” in Setup, there is a list of
complementary settings which are made. These can be individually overridden after the policy
setting has been selected and the profile settings performed. The profile settings are listed in
the following table.
Table 32. Power/Performance Profiles
BIOS Features
CPU Power and
Performance Policy
®
Intel QPI
Frequency Select
®
Intel Turbo Boost
Technology
Revision 2.0
Available Settings
Performance
Balanced
Balanced Power
Performance
Setup: Advanced > Power and Performance
Performance
Performance
(Balanced
Balanced
/Balanced
Performance)
Power
Performance
/Balanced Power
/Power
Setup: Advanced > Processor Configuration
Auto Max
(Auto Max)
(Auto Max)
(Auto Max)
/6.4 GT/s
/7.2 GT/s
/8.0 GT/s
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
Intel order number G52803-002
Power
Power
6.4 GT/s
(Enabled)
81
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
BIOS Features
Available Settings
®
Enabled/Disabled
Enhanced Intel
®
SpeedStep
Technology
Processor C3
Processor C6
®
Intel Hyper
Threading
Active Processor
Cores
MLC Streamer
MLC Spatial
Prefetcher
DCU Data
Prefetcher
DCU Instruction
Prefetcher
Direct Cache
Access (DCA)
Performance
(Enabled)
Balanced
Performance
(Enabled)
Balanced Power
Power
(Enabled)
(Enabled)
Enabled/Disabled
Enabled/Disabled
Enabled/Disabled
(Disabled)
(Enabled)
(Enabled)
(Disabled)
(Enabled)
(Enabled)
(Disabled)
(Enabled)
(Enabled)
(Disabled)
(Enabled)
(Enabled)
All/1/2/3/4/5/6/7
(All)
(All)
(All)
(All)
Enabled/Disabled
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Setup: Advanced > Memory Configuration
Auto/800/1067
(Auto)
(Auto)
(Auto)
(Auto)
/1333/1600
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Enabled/Disabled
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Power
(Performance
(Performance
(Performance
(Performance
Optimized/Perform Optimized)
Optimized)
Optimized)
Optimized)
ance Optimized
Setup: Advanced > Memory Configuration > Memory RAS and Performance Configuration
Enabled/Disabled
NUMA Optimized
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Setup: Advanced > System Acoustic and Performance Configuration
Auto/DCLTT
Set Throttling
(Auto)
(Auto)
(Auto)
(Auto)
Mode
/SCLTT/SOLTT
Performance
Set Fan Profile
(Performance)
(Performance)
(Performance)
(Performance)
/Acoustic
Enabled/Disabled
Quiet Fan Idle
(Disabled)
(Disabled)
(Disabled)
(Disabled)
Mode
Setup: Server Management
Enabled/Disabled
EuP LOT6 OFF(Disabled)
(Disabled)
(Disabled)
(Disabled)
Mode
Internal BIOS Settings not displayed in BIOS Setup
Auto/Enabled
QPI Link L0S
Disabled
(Auto)
(Auto)
(Auto)
enable
/Disabled
Auto/Enabled
CKE Throttling
Disabled
(Auto)
(Auto)
Enabled
/Disabled
Auto/1.5V/1.35V
Memory Voltage
1.5v
(Auto)
(Auto)
(Auto)
CPU PkgC State
Disabled/C6 with
Disabled
(C6 with
(C6 with
(C6 with
no retention/C6
Limit
retention)
retention)
retention)
with retention
Enabled/Disabled
Processor C1
(Enabled)
(Enabled)
(Enabled)
(Enabled)
mapped to ACPI
C1
Enabled/Disabled
Processor C6 with
(Enabled)
(Enabled)
(Enabled)
(Enabled)
retention mapped
to ACPI C2
Enabled/Disabled
ACPI C3
(Disabled)
(Disabled)
(Disabled)
(Disabled)
Enabled/Disabled
Processor C1/C3
(Enabled)
(Enabled)
(Enabled)
(Enabled)
Auto Demotion
Enabled/Disabled
Processor C1/C3
(Enabled)
(Enabled)
(Enabled)
(Enabled)
UnDemotion
Memory Operating
Speed Selection
Patrol Scrub
Demand Scrub
Memory Power
Optimization
82
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Features
ENERGY_PERF
_BIAS mode
BIOS Setup Interface
Available Settings
Performance/Bala
nced
Performance/Bala
nced Power/Power
Performance
Performance
Balanced
Performance
(Balanced
Performance)
Balanced Power
Balanced
Power
Power
Power
5.4.2.6 Memory Configuration
The Memory Configuration screen allows the user to view details about the DDR3 DIMMs that
are installed as system memory.
To access this screen from the Main screen, select Advanced > Memory Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
Advanced
Memory Configuration
Total Memory
<Total Physical Memory Installed in System>
Effective Memory
<Total Effective Memory>
Current Configuration
<Independent/Mirror/Lockstep>
Current Memory Speed
<Operational Memory Speed in MT/s>
Memory Operation Speed Selection
Auto/800/1066/1333/1600
Patrol Scrub
Enable/Disable
Demand Scrub
Enable/Disable
Correctable Error Threshold
20/10/5/Every
Memory Power Optimization
Performance Optimized/Power Optimized
► Memory RAS and Performance Configuration
DIMM Information
DIMM_A1
<DIMM size> Operational/Not Installed/Failed/Disabled
DIMM_B1
<DIMM size> Operational/Not Installed/Failed/Disabled
DIMM_C1
<DIMM size> Operational/Not Installed/Failed/Disabled
DIMM_D1
<DIMM size> Operational/Not Installed/Failed/Disabled
DIMM_E1
<DIMM size> Operational/Not Installed/Failed/Disabled
DIMM_F1
<DIMM size Operational/Not Installed/Failed/Disabled
DIMM_G1
<DIMM size Operational/Not Installed/Failed/Disabled
DIMM_H1
<DIMM size> Operational/Not Installed/Failed/Disabled
Figure 24. Memory Configuration Screen
Revision 2.0
Intel order number G52803-002
83
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Table 33. Setup Utility – Memory Configuration Screen Fields
Setup Item
Total Memory
Options
Comments
Information only. The amount of memory available in the system in
the form of installed DDR3 DIMMs in units of GB.
Effective Memory
Information only. The amount of memory available to the operating
system in MB or GB.
The Effective Memory is the difference between the Total Physical
Memory and the sum of all memory reserved for internal usage, RAS
redundancy and SMRAM. This difference includes the sum of all
DDR3 DIMMs that failed Memory BIST during POST, or were
disabled by the BIOS during memory discovery phase to optimize
memory configuration.
Current
Configuration
Independent Channel
Displays one of the following:
Mirror
Independent Channel – DIMMs are operating in Independent
Channel Mode, the default configuration when there is no RAS Mode
configured.
Lockstep
Mirror – Mirroring RAS Mode has been configured and is operational.
Lockstep – Lockstep RAS Mode has been configured and is
operational
Current Memory
Speed
Memory Operating
Speed Selection
Information only. Displays the speed the memory is running at.
Auto
800
1066
1333
1600
Allows the user to select a specific speed at which memory will
operate. Only speeds that are legitimate are available, that is, the
user can only specify speeds less than or equal to the auto-selected
Memory Operating Speed. The default Auto setting will select the
highest achievable Memory Operating Speed consistent with the
DIMMs and processors installed.
Patrol Scrub
Enabled
Disabled
When enabled, Patrol Scrub is initialized to read through all of
memory in a 24-hour period, correcting any Correctable ECC Errors it
encounters by writing back the corrected data to memory.
Demand Scrub
Enabled
Disabled
When enabled, Demand Scrub automatically corrects a Correctable
ECC Error encountered during a fetch from memory by writing back
the corrected data to memory.
Correctable Error
Threshold
20
Specifies how many Correctable Errors must occur before triggering
the logging of a SEL Correctable Error Event. Only the first threshold
crossing is logged, unless “All” is selected. “All” causes every CE that
occurs to be logged. “None” suppresses CE logging completely.
10
5
All
None
Memory Power
Optimized
Performance
Optimized
Power Optimized
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Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Setup Item
DIMM_ XY
Options
BIOS Setup Interface
Comments
Displays the state of each DIMM socket present on the board. Each
DIMM socket field reflects one of the following possible states:
Operational – There is a DDR3 DIMM installed and operational in
this slot.
Not Installed – There is no DDR3 DIMM installed in this slot.
Failed – The DIMM installed in this slot has failed during initialization.
Disabled – The DIMM installed in this slot was disabled during
initialization.
For each DIMM that is in an Operational status, the size in GB of that
DIMM is displayed.
Note: X denotes the Channel Identifier and Y denote the DIMM
Identifier within the Channel.
5.4.2.7 Memory RAS and Performance Configuration
The Memory RAS and Performance Configuration screen allows the user to customize several
memory configuration options, such as whether to use Memory Mirroring or Memory Sparing.
To access this screen from the Main screen, select Advanced > Memory Configuration >
Memory RAS and Performance Configuration. To move to another screen, press the <Esc>
key to return to the Memory Configuration screen, if necessary press the <Esc> key again to
return to the Advanced screen, then select the desired screen.
Advanced
Memory RAS and Performance Configuration
Capabilities
Memory Mirroring Possible
Yes/No
Memory Rank Sparing Possible
Yes/No
Memory Lockstep Possible
Yes/No
Select Memory RAS Configuration
Maximum Performance/Mirroring/Rank Sparing/Lockstep
NUMA Optimized
Disabled/ Enabled
Figure 25. Memory RAS and Performance Configuration Screen
Revision 2.0
Intel order number G52803-002
85
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Table 34. Setup Utility – Memory RAS and Performance Configuration Fields
Setup Item
Memory Mirroring
Possible
Options
Help Text
Yes
No
Comments
Information only. Displays
whether the current DIMM
configuration is capable of
Memory Mirroring.
Information only. Displays
whether the current DIMM
configuration is capable of
Rank Sparing.
Memory Rank Sparing
Possible
Yes
Memory Lockstep
Possible
Yes
Select Memory RAS
Configuration
Maximum Performance
NUMA Optimized
Enabled
No
Information only. Displays
whether the current DIMM
configuration is capable of
Memory Lockstep.
No
Mirroring
Rank Sparing
Lockstep
Disabled
Allows the user to select
the memory RAS
Configuration to be
applied for the next boot.
Available modes depend on
the current memory
population. Modes which are
not listed as “possible”
should not be available as
choices. If the only valid
choice is “Maximum
Performance”, then this
option should be grayed out
and unavailable.
If enabled, BIOS
includes ACPI tables that
are required for NUMAaware Operating
Systems.
This option is only present
for boards which have two or
more processor sockets.
When a multi-socket board
has only a single processor
installed, this option is
grayed out and set as
Disabled.
5.4.2.8 Mass Storage Controller Configuration
The Mass Storage Configuration screen allows the user to configure the Mass Storage
controllers that are integrated into the server board on which the BIOS is executing.
To access this screen from the Main screen, select Advanced > Mass Storage Controller
Configuration. To move to another screen, press the <Esc> key to return to the Advanced
screen, then select the desired screen.
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Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Advanced
Mass Storage Controller Configuration
AHCI Controller Configuration
2 ports of 6Gb/s SATA
SATA/SAS Controller Configuration
4 ports in SAS mode
AHCI Capable SATA Controller
Disable/Compatibility/Enhanced/AHCI/RAID Mode
SAS/SATA Capable Controller
DISABLED/INTEL®ESRT2(LSI*)/INTEL®RSTE
Intel®Storage Module
--- None / <Name of storage module detected >
SATA Port 0
Not Installed/<Drive Info.>
SATA Port 1
Not Installed/<Drive Info.>
Figure 26. Mass Storage Controller Configuration Screen
Table 35. Mass Storage Controller Configuration Fields
Setup Item
AHCI Controller
Configuration
Options
Help Text
SATA/SAS Controller
Configuration
AHCI Capable SATA
Controller
Information only
Disabled
Compatibility
Enhanced
AHCI
RAID Mode
SAS/SATA Capable
Controller
Disabled
®
Intel ESRT2
(LSI*)
®
Intel RSTe
®
Intel Storage Module
Revision 2.0
Comments
Information only
- Compatibility provides PATA
emulation on the SATA device
- Enhanced provides Native SATA
support
- AHCI enables the Advanced Host
Controller Interface, which provides
Enhanced SATA functionality
- RAID Mode provides host based
RAID support on the onboard SATA
ports
®
- Intel ESRT2: Provides host
based RAID 0/1/10 and optional
®
RAID 5. Uses Intel ESRT2 drivers
(based on LSI* MegaSR).
®
- Intel RSTe: Provides passthrough drive support. Also
provides host based RAID 0/1/10
support, and RAID 5 (in SATA
®
mode only). Uses Intel RSTe
iastor drivers.
This option configures
the onboard AHCIcapable SATA controller,
which is distinct from the
SCU.
This option selects the
RAID stack to be used
with the SCU. If Disabled
is selected, any drives
connected to the SCU
will not be usable.
Information Only
--- None
Intel order number G52803-002
87
BIOS Setup Interface
Setup Item
SATA Port x
Intel®Server Boards S2400LP TPS
Options
Not Installed
Help Text
Ports 0-1: 6Gb SATA capable port
Drive Info
Comments
Information only. This
is repeated for all 6
SATA Port for the
Onboard SATA
Controller. This section
for SATA Drive
Information does not
appear when the SATA
Mode is RAID Mode.
5.4.2.9 PCI Configuration
The PCI Configuration screen allows the user to configure the PCI memory space used for
onboard and add-in adapters, configure video options, and configure onboard adapter options. It
also displays the NIC MAC Addresses currently in use.
To access this screen from the Main screen, select Advanced > PCI Configuration. To move
to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
Advanced
PCI Configuration
Maximize Memory below 4GB
Enabled / Disabled
Memory Mapped I/O above 4GB
Enabled / Disabled
Onboard Video
Enabled / Disabled
Legacy VGA Socket
CPU Socket 1/CPU Socket 2
Dual Monitor Video
Enabled / Disabled
► NIC Configuration
Figure 27. PCI Configuration Screen
88
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Table 36. Setup Utility – PCI Configuration Screen Fields
Setup Item
Maximize Memory
below 4GB
Options
Enabled
Memory Mapped I/O
above 4GB
Enabled
Onboard Video
Legacy VGA Socket
Help Text
BIOS maximizes memory usage below 4GB
for an OS without PAE support, depending
on the system configuration. Only enable for
an OS without PAE support.
Comments
When this option is
enabled, BIOS makes as
much memory available as
possible in the 32-bit
(4GB) address space, by
limiting the amount of
PCI/PCIe Memory
Address Space and PCIe
Extended Configuration
Space. This option should
only be enabled for a 32bit OS without PAE
capability or without PAE
enabled.
Disabled
Enable or disable memory mapped I/O of 64bit PCI devices to 4 GB or greater address
space.
When enabled, PCI/PCIe
Memory Mapped I/O for
devices capable of 64-bit
addressing is allocated to
address space above
4GB, in order to allow
larger allocations and
avoid impacting address
space below 4GB.
Enabled
Onboard video controller.
Disabled
Warning: System video is completely
disabled if this option is disabled and an addin video adapter is not installed.
When disabled, the system
requires an add-in video
card in order for the video
to be seen.
CPU Spcket 1
Determines whether Legacy VGA video
output is enabled for PCIe slots attached to
Processor Socket 1 or 2. Socket 1 is the
default.
This option is necessary
when using an add-in
video card on a PCIe slot
attached to CPU Socket 2,
due to a limitation of the
processor IIO. The Legacy
video device can be
connected through either
socket, but there is a
setting that must be set on
only one of the two. This
option allows the switch to
using a video card in a slot
connected to CPU Socket
2.
If enabled. both the onboard video controller
and an add-in video adapter are enabled for
system video. The onboard video controller
becomes the primary video device.
This option must be
enabled to use an add-in
card as a secondary
POST Legacy Video
device while also
displaying on the Onboard
Video device.
Disabled
CPU Socket 2
Dual Monitor Video
Enabled
Disabled
If there is no add-in video
card in any PCIe slot
connected to CPU Socket
1, this options is set to
Disabled and grayed out
and unavailable.
Revision 2.0
Intel order number G52803-002
89
BIOS Setup Interface
Setup Item
NIC Configuration
5.4.2.10
Intel®Server Boards S2400LP TPS
Options
Help Text
View/Configure NIC information and settings
Comments
NIC configuration
The NIC configuration screen allows the user to configure on board NIC port1 and port2.
Advanced
NIC Configuration
90
Wake on LAN (PME)
Enabled / Disabled
PXE 1GbE Option ROM
Enabled / Disabled
PXE 10GbE Option ROM
Enabled / Disabled
FCoE 10GbE Option ROM
Enabled / Disabled
discs 1GbE/10GbE Option ROM
Enabled / Disabled
Onboard NIC1 Type
<Onboard NIC Description – Non-InfiniBand>
NIC1 Controller
Enabled / Disabled
NIC1 Port1
Enabled / Disabled
NIC1 Port2
Enabled / Disabled
NIC1 Port1 PXE
Enabled / Disabled
NIC1 Port2 PXE
Enabled / Disabled
NIC1 Port1 MAC Address
<MAC Address display>
NIC1 Port2 MAC Address
<MAC Address display >
Onboard NIC2 Type
<Onboard NIC Description – InfiniBand Only>
NIC2 InfiniBand Option ROM
Enabled / Disabled
NIC2 Port1 GUID
<GUID Display>
NIC2 Port1 MAC Address
<MAC Address display >
IO Module 1 Type
<IO Module Description – Non-InfiniBand>
IOM1 Port1 PXE
Enabled / Disabled
IOM1 Port2 PXE
Enabled / Disabled
IOM1 Port3 PXE
Enabled / Disabled
IOM1 Port4 PXE
Enabled / Disabled
IOM1 Port1 MAC Address
<MAC Address display >
IOM1 Port2 MAC Address
<MAC Address display >
IOM1 Port3 MAC Address
<MAC Address display >
IOM1 Port4 MAC Address
<MAC Address display >
IO Module 1 Type
<IO Module Description – InfiniBand Only>
IOM1 InfiniBand Option ROM
Enabled / Disabled
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
IOM1 Port1 GUID
<GUID Display>
IOM1 Port1 MAC Address
<MAC Address display >
Figure 28. NIC Configuration Screen Field
Table 37. Setup Utility - NIC Configuration Screen Field
Setup Item
Wake on LAN (PME)
Options
Enabled
Disabled
PXE 1GbE Option
ROM
Enabled
Disabled
Help Text
Enables or disables PCI PME function for
Wake on LAN capability from LAN adapters.
Comments
Enables/disables PCI/PCIe
PME# signal to generate
Power Management
Events (PME) and ACPI
Table entries required for
Wake on LAN (WOL).
However, note that this will
enable WOL only with an
ACPI-capable Operating
System which has the
WOL function enabled.
Enable/Disable Onboard/IOM NIC PXE
Option ROM Load.
This selection is to
enable/disable the 1GbE
PXE Option ROM that is
used by all Onboard and
IO Module 1 GbE
controllers.
This option is grayed out
and not accessible if the
discs Option ROM is
enabled. It can co-exist
with the 10 GbE PXE
Option ROM, the 10 GbE
FCoE Option ROM, or with
an InfiniBand* controller
Option ROM.
If the 1GbE PXE Option
ROM is disabled, and no
other Option ROM is
enabled, the system
cannot perform a Network
Boot and cannot respond
for Wake-on-LAN.
This 1GbE PXE option
does not appear unless
there is a 1 GbE NIC
installed in the system as
an Onboard or IO Module
NIC.
Revision 2.0
Intel order number G52803-002
91
BIOS Setup Interface
Setup Item
PXE 10GbE Option
ROM
Intel®Server Boards S2400LP TPS
Options
Enabled
Disabled
Help Text
Enable/Disable Onboard/IOM NIC PXE
Option ROM Load.
Comments
This selection is to
enable/disable the 10GbE
PXE Option ROM that is
used by all Onboard and
IO Module 10 GbE
controllers.
This option is grayed out
and not accessible if the
discs Option ROM is
enabled or the 10 GbE
FCoE Option ROM is
enabled. It can co-exist
with the 1 GbE PXE
Option ROM or with an
InfiniBand* controller
Option ROM.
If the 10GbE PXE Option
ROM is disabled, and no
other Option ROM is
enabled, the system
cannot perform a Network
Boot and cannot respond
for Wake-on-LAN.
This 10GbE PXE option
does not appear unless
there is a 10 GbE NIC
installed in the system as
an Onboard or IO Module
NIC.
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Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Setup Item
FCoE 10GbE Option
ROM
Options
Enabled
Disabled
BIOS Setup Interface
Help Text
Enable/Disable Onboard/IOM NIC FCoE
Option ROM Load.
Comments
This selection is to
enable/disable the 10GbE
FCoE Option ROM that is
used by all Onboard and
IO Module 10 GbE
controllers capable of
FCoE support. At the
present time, only the
®
Intel 82599 10 Gigabit
SFP+ NIC supports FCoE
for this family of server
boards.
This option is grayed out
and not accessible if the
10GbE PXE Option ROM
is enabled or if the discs
Option ROM is enabled. It
can co-exist with the 1GbE
PXE Option ROM or with
an InfiniBand* controller
Option ROM.
If the FCoE Option ROM is
disabled, and no other
Option ROM is enabled,
the system cannot perform
a Network Boot and
cannot respond for Wakeon-LAN.
This FCoE option does not
appear unless there is a
FCoE-capable 10GbE NIC
installed in the system as
an Onboard or IO Module
NIC.
Revision 2.0
Intel order number G52803-002
93
BIOS Setup Interface
Setup Item
Discs 1GbE/10GbE
Option ROM
Intel®Server Boards S2400LP TPS
Options
Enabled
Disabled
Help Text
Enable/Disable Onboard/IOM NIC discs
Option ROM Load.
Comments
This selection is to
enable/disable the discs
Option ROM that is used
by all Onboard and IO
Module 1 GbE and 10
GbE controllers.
This option is grayed out
and not accessible if the 1
GbE or 10GbE PXE
Option ROM is enabled or
if the 10 GbE FCoE Option
ROM is enabled. It can coexist with an InfiniBand*
controller Option ROM.
If the discs Option ROM is
disabled, and no other
Option ROM is enabled,
the system cannot perform
a Network Boot and
cannot respond for Wakeon-LAN.
This discs option does not
appear unless there is an
discs-capable NIC
installed in the system as
an Onboard or IO Module
NIC.
Onboard NIC1 Type
None
Onboard NIC2 Type
®
Intel 82574 Single-Port Gigabit Ethernet
Controller
®
Intel I350 Dual-Port Gigabit Ethernet
Controller
®
Intel I350 Quad-Port Gigabit Ethernet
Controller
®
Intel I540 Dual-Port X540 10 Gigabit RJ-45
Controller
Mellanox* ConnectX-3* Single-Port
InfiniBand* FD14 Controller
IO Module 1 Type
None
IO Nodule 2 Type
Intel I350 Quad-Port Gigabit Ethernet
Module
®
Intel I540 Dual-Port X540 10 Gigabit RJ-45
Module
®
Intel 82599 Dual-Port 10 Gigabit SFP+
Module
Mellanox* ConnectX-3* Single-Port
InfiniBand FD14 Module
94
Intel order number G52803-002
Information only
Information only
®
Revision 2.0
Intel®Server Boards S2400LP TPS
Setup Item
NIC1 Controller
Options
Enable
NIC2 Controller
Disable
BIOS Setup Interface
Help Text
Enable/Disable Onboard Network Controller
Comments
This will completely
disable Onboard Network
Controller NIC1 or NIC2,
along with all included NIC
Ports and their associated
options. That controller’s
NIC Ports, Port PXE
options, and Port MAC
Address displays will not
appear.
This option only appears
for onboard Ethernet
controllers. It does not
appear for onboard
InfiniBand controllers.
Ethernet controllers on IO
Modules do not have a
disabling function that can
be controlled by BIOS, so
there is no corresponding
controller enable/disable
option for an IOM Ethernet
controller.
NIC2 InfiniBand Option
ROM
Enable
Disable
Enable/Disable InfiniBand Controller Option
ROM and FlexBoot.
IOM1 InfiniBand
Option ROM
This option will control
whether the associated
InfiniBand Controller
Option ROM is executed
by BIOS during POST.
This will also control
whether the InfiniBand
controller FlexBoot
program appears in the list
of bootable devices.
This option only appears
for Onboard or IO Module
InfiniBand controllers. It
does not appear for
Ethernet controllers.
NIC2 Port1 GUID
Information Only
IOM1 Port1 GUID
Revision 2.0
Intel order number G52803-002
16 hex digits of the Port1
GUID of the InfiniBand
controller for NIC2, IOM1,
or IOM2.
95
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Setup Item
NIC1 Port1
Options
Enable
NIC1 Port2
Disable
Help Text
Enable/Disable Onboard NIC<n> Port<x>
NIC2 Port1
NIC2 Port2
Comments
This will enable or disable
Port<x, x = 1-4> of
Onboard Network
Controller<n, n = 1-2>,
including associated Port
PXE options. The NIC<n>
Port<x> PXE option and
MAC Address display will
not appear when that port
is disabled.
The associated port
enable/disable options will
not appear when NIC<n>
is disabled.
Only ports which actually
exist for a particular NIC
will appear in this section.
That is, Port1-Port4 will
appear for a quad-port
NIC, Port1-Port2 will
appear for a dual-port NIC,
and only Port1 will appear
for a single-port NIC.
Network controllers
installed on an IO Module
do not have a port
disabling function that is
controlled by BIOS, so
there are no corresponding
options for IO Module
NICs.
NIC1 Port1 PXE
Enable
NIC1 Port2 PXE
Disable
Enable/Disable Onboard/IOM NIC Port PXE
Boot
This option will not appear
for ports on a NIC which is
disabled, or for individual
ports when the
corresponding NIC Port is
disabled.
Information Only
12 hex digits of the MAC
address.
NIC2 Port1 PXE
NIC2 Port2 PXE
IOM1 Port1 PXE
IOM1 Port2 PXE
NIC1 Port1 MAC
Address
NIC1 Port2 MAC
Address
NIC2 Port1 MAC
Address
NIC2 Port2 MAC
Address
IOM1 Port1 MAC
Address
IOM1 Port2 MAC
Address
96
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
5.4.2.11
BIOS Setup Interface
Serial Port Configuration
The Serial Port Configuration screen allows the user to configure the Serial A [COM 1] and
Serial B [COM2] ports.
To access this screen from the Main screen, select Advanced > Serial Port Configuration. To
move to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
Advanced
Serial Port Configuration
Serial A Enable
Enabled/Disabled
Address
3F8h/2F8h/3E8h/2E8h
IRQ
3 or 4
Figure 29. Serial Port Configuration Screen
Table 38. Setup Utility – Serial Ports Configuration Screen Fields
Setup Item
Serial A
Enable
Options
Enabled
Address
3F8h
Help Text
Enable or Disable Serial port A.
Disabled
Select Serial port A base I/O address.
2F8h
3E8h
2E8h
IRQ
3
Select Serial port A interrupt request (IRQ) line.
4
5.4.2.12
USB Configuration
The USB Configuration screen allows the user to configure the USB controller options.
To access this screen from the Main screen, select Advanced > USB Configuration. To move
to another screen, press the <Esc> key to return to the Advanced screen, then select the
desired screen.
Revision 2.0
Intel order number G52803-002
97
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Advanced
USB Configuration
Detected USB Devices
<Total USB Devices in System>
USB Controller
Enabled/Disabled
Legacy USB Support
Enabled/Disabled/Auto
Port 60/64 Emulation
Enabled/Disabled
Make USB Devices Non-Bootable
Enabled/Disabled
USB Mass Storage Device Configuration
10 seconds/20 seconds/30 seconds/40 seconds
Device Reset timeout
Mass Storage Devices:
<Mass storage devices one line/device>
Auto/Floppy/Forced FDD/Hard Disk/CD-ROM
Figure 30. USB Configuration Screen
Table 39. Setup Utility – USB Controller Configuration Screen Fields
Setup Item
Detected USB
Devices
USB Controller
Options
Enabled
Disabled
Legacy USB
Support
Enabled
Port 60/64
Emulation
Enabled
Make USB
Devices NonBootable
Enabled
Disabled
98
Disabled
Auto
Disabled
Help Text
Comments
Information only. Shows
the number of USB
devices in the system.
[Enabled] - All onboard USB controllers are turned
on and accessible by the OS.
[Disabled] - All onboard USB controllers are turned
off and inaccessible by the OS.
USB device boot support and PS/2 emulation for
USB keyboard and USB mouse devices.
[Auto] - Legacy USB support is enabled if a USB
device is attached.
Grayed out if the USB
Controller is disabled.
I/O port 60h/64h emulation support.
Note: This may be needed for legacy USB keyboard
support when using an OS that is USB unaware.
Grayed out if the USB
Controller is disabled.
Exclude USB in Boot Table.
[Enabled] - This removes all USB Mass Storage
devices as Boot options.
[Disabled] - This allows all USB Mass Storage
devices as Boot options.
Grayed out if the USB
Controller is disabled.
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Setup Item
Device Reset
timeout
Options
10 sec
20 sec
30 sec
40 sec
One line for
each mass
storage device
in system
5.4.2.13
Auto
Floppy
Forced FDD
Hard Disk
CD-ROM
BIOS Setup Interface
Help Text
USB Mass Storage device Start Unit command
timeout.
Setting to a larger value provides more time for a
mass storage device to be ready, if needed.
Comments
Grayed out if the USB
Controller is disabled.
[Auto] - USB devices less than 530 MB are
emulated as floppies.
[Forced FDD] - HDD formatted drive are emulated
as a FDD (for example, ZIP drive).
Hidden if no USB Mass
storage devices are
installed.
Grayed out if the USB
Controller is disabled.
This setup screen can
show a maximum of eight
devices on this screen. If
more than eight devices
are installed in the
system, the USB Devices
Enabled shows the
correct count, but only
displays the first eight
devices here.
System Acoustic and Performance Configuration
The System Acoustic and Performance Configuration screen allows the user to configure the
thermal control behavior of the system with respect to what parameters are used in the system’s
Fan Speed Control algorithms.
To access this screen from the Main screen, select Advanced > System Acoustic and
Performance Configuration. To move to another screen, press the <Esc> key to return to the
Advanced screen, then select the desired screen.
Advanced
System Acoustic and Performance Configuration
Set Throttling Mode
Auto/DCLTT/SCLTT/SOLTT
Altitude
300m or less/301m-900m/901m – 1500m/Higher than 1500m
Set Fan Profile
Performance, Acoustic
Fan PWM Offset
0
Quiet Fan Idle Mode
Enabled/Disabled
Figure 31. System Acoustic and Performance Configuration
Revision 2.0
Intel order number G52803-002
99
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Table 40. Setup Utility – System Acoustic and Performance Configuration Screen Fields
Setup Item
Set Throttling
Mode
Options
Auto
Help Text
[Auto] – Auto Throttling mode.
SCLTT
[DCLTT] – Dynamic Closed Loop Thermal
Throttling
SOLTT
[SCLTT] – Static Closed Loop Thermal Throttling
DCLTT
[SOLTT] – Static Open Loop Thermal Throttling
Comments
DCLTT is the expected
mode for a board in an
Intel chassis with inlet
and outlet air
temperature sensors
and TSOD. The
firmware can update
the offset registers for
closed loop during
runtime, as BIOS
sends the dynamic
CLTT offset
temperature data.
SCLTT would be used
with an OEM chassis
and DIMMs with TSOD.
The firmware does not
change the offset
registers for closed
loop during runtime,
although the
Management Engine
can do so.
SOLTT is intended for
a system with UDIMMs
which do not have
TSOD. The thermal
control registers are
configured during
POST, and the
firmware does not
change them.
Altitude
300m or less
[300m or less] (980ft or less)
301m-900m
Optimal performance setting near sea level.
901m-1500m
[301m - 900m] (980ft - 2950ft)
Higher than 1500m Optimal performance setting at moderate
elevation.
[901m – 1500m] (2950ft – 4920ft)
This option sets an
altitude value in order
to choose a Fan Profile
that is optimized for the
air density at the
current altitude at
which the system is
installed.
Optimal performance setting at high elevation.
[Higher than 1500m] (4920ft or greater)
Optimal performance setting at the highest
elevations.
100
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Setup Item
Set Fan
Profile
Options
Performance
Acoustics
BIOS Setup Interface
Help Text
[Performance] - Fan control provides primary
system cooling before attempting to throttle
memory.
[Acoustic] - The system will favor using throttling of
memory over boosting fans to cool the system if
thermal thresholds are met.
Comments
This option allows the
user to choose a Fan
Profile that is optimized
for maximizing
performance or for
minimizing acoustic
noise.
When Performance is
selected, the thermal
conditions in the
system are controlled
by raising fan speed
when necessary to
raise cooling
performance. This
provides cooling
without impacting
system performance,
but may impact system
acoustic performance –
fans running faster are
typically louder.
When Acoustic is
selected, then rather
than increasing fan
speed for additional
cooling, the system will
attempt first to control
thermal conditions by
throttling memory to
reduce heat production.
This regulates the
system’s thermal
condition without
changing the acoustic
performance, but
throttling memory may
impact system
performance.
Fan PWM
Offset
Revision 2.0
0
Valid Offset 0 - 100. This number is added to the
calculated PWM value to increase Fan Speed.
Intel order number G52803-002
This is a percentage by
which the calculated
fan speed will be
increased. The user
can apply positive
offsets that result in
increasing the
minimum fan speeds.
101
BIOS Setup Interface
Setup Item
Quiet Fan Idle
Mode
Intel®Server Boards S2400LP TPS
Options
Disabled
Help Text
Enabling this option allows the system fans to
operate in Quiet ‘Fan off’ mode while still
maintaining sufficient system cooling. In this mode,
fan sensors become unavailable and cannot be
monitored. There will be limited fan related event
generation.
Enabled
Comments
When enabled, this
option allows fans to
idle or turn off when
sufficient thermal
margin is available,
decreasing the acoustic
noise produced by the
system and decreasing
system power
consumption. Fans will
run as needed to
maintain thermal
control. The actual
decrease in fan speed
depends on the system
thermal loading, which
in turn depends on
system configuration
and workload.
While Quiet Fan Idle
Mode is engaged, fan
sensors become
unavailable and are not
monitored by the BMC.
5.4.2.14
Security Screen (Tab)
The Security screen allows the user to enable and set the user and administrative password
and to lock out the front panel buttons so they cannot be used. This screen also allows the user
to enable and activate the Trusted Platform Module (TPM) security settings on those boards
that support TPM.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Security screen is
selected.
Main
Advanced
Security
Server Management
Boot Options
Administrator Password Status
<Installed/Not Installed>
User Password
<Installed/Not Installed>
Boot Manager
Set Administrator Password
Set User Password
[123aBcD]
Power ON Password
Enabled/Disabled
Front Panel Lockout
Enabled/Disabled
Figure 32. Security Screen
102
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Table 41. Setup Utility – Security Configuration Screen Fields
Setup Item
Administrator
Password Status
Options
Help Text
Installed
Not Installed
User Password
Status
Installed
Set Administrator
Password
[Entry Field]
Information only. Indicates
the status of the user
password.
Not Installed
Administrator password is used to
control change access in BIOS
Setup Utility.
Only alphanumeric characters can
be used. Maximum length is 7
characters. It is case sensitive.
Note: Administrator password must
be set in order to use the user
account.
Set User
Password
[Entry Filed]
User password is used to control
entry access to BIOS Setup Utility.
Only alphanumeric characters can
be used. Maximum length is 7
characters. It is case sensitive.
Note: Removing the administrator
password also automatically
removes the user password.
Power ON
Password
Enabled
Disabled
Comments
Information only. Indicates
the status of the
administrator password.
Enable Power On Password support.
If enabled, password entry is
required in order to boot the system
This option is only to
control access to the setup.
Administrator has full
access to all the setup
items. Clearing the
Administrator password
also clears the user
password.
Available only if the
administrator password is
installed. This option only
protects the setup.
User password only has
limited access to the setup
items.
When Power On Password
security is enabled, the
system will halt soon after
power on and the BIOS will
ask for a password before
continuing POST and
booting. Either the
Administrator or User
password may be used.
If an Administrator
password has not been set,
this option will be grayed
out and unavailable. If this
option is enabled and the
Administrator password is
removed, that will also
disable this option.
Front Panel
Lockout
Revision 2.0
Enabled
Disabled
If enabled, locks the power button
and reset button on the system's
front panel. If [Enabled] is selected,
power and reset must be controlled
through a system management
interface.
Intel order number G52803-002
103
BIOS Setup Interface
5.4.2.15
Intel®Server Boards S2400LP TPS
Server Management Screen (Tab)
The Server Management screen allows the user to configure several server management
features. This screen also provides an access point to the screens for configuring console
redirection, displaying system information, and controlling the BMC LAN configuration.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Server Management
screen is selected.
Main
Advance
d
Security
Server Management
Boot Options
Boot Manager
Assert NMI on SERR
Enabled / Disabled
Assert NMI on PERR
Enabled / Disabled
Reset on CATERR
Enabled / Disabled
Reset on ERR2
Enabled / Disabled
Resume on AC Power Loss
Stay Off / Last state / Power On
Power Restore Delay
Disabled/Auto/Fixed
Power Restore Delay Value
25
Clear System Event Log
Enabled / Disabled
FRB-2 Enable
Enabled / Disabled
OS Boot Watchdog Timer
Enabled / Disabled
OS Boot Watchdog Timer Policy
Power off / Reset
OS Boot Watchdog Timer Timeout
5 minutes / 10 minutes / 15 minutes / 20 minutes
Plug and Play BMC Detection
Shutdown Policy
Enabled / Disabled
Enabled / Disabled
► Console Redirection
► System Information
► BMC LAN Configuration
Figure 33. Server Management Screen
Table 42. Setup Utility – Server Management Configuration Screen Fields
Setup Item
Assert NMI on
SERR
104
Options
Enabled
Help Text
On SERR, generate an NMI and log an error.
Disabled
Note: [Enabled] must be selected for the Assert
NMI on PERR setup option to be visible.
Intel order number G52803-002
Comments
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Setup Item
Assert NMI on
PERR
Options
Enabled
Help Text
On PERR, generate an NMI and log an error.
Disabled
Note: This option is only active if the Assert NMI
on SERR option is [Enabled] selected.
Reset on CATERR
Enabled
When enabled system gets reset upon
encountering Catastrophic Error (CATERR); when
disabled system does not get reset on CATERR.
This option controls
whether the system will
be reset when the
CATERR signal is held
asserted, rather than
just pulsed to generate
an SMI.
Disabled
When enabled system gets reset upon
encountering ERR2 (Fatal error); when disabled
system does not get reset on ERR2
This option controls
whether the system will
be reset if the BMC’s
ERR2 Monitor times
out, that is, the ERR2
signal has been
continuously asserted
long enough to indicate
that the SMI Handler is
not able to service the
condition.
Stay Off
System action to take on AC power loss recovery.
Last state
[Stay Off] - System stays off.
Reset
[Last State] - System returns to the same state
before the AC power loss.
Disabled
Reset on ERR2
Resume on AC
Power Loss
Enabled
Comments
[Reset] - System powers on.
Clear System Event
Log
Enabled
Disabled
If enabled, clears the System Event Log. All
current entries will be lost.
Note: This option is reset to [Disabled] after a
reboot.
FRB-2 Enable
O/S Boot Watchdog
Timer
Enabled
Fault Resilient Boot (FRB).
Disabled
If enabled, the BIOS programs the BMC watchdog
timer for approximately 6 minutes. If the BIOS
does not complete POST before the timer expires,
the BMC resets the system.
Enabled
If enabled, the BIOS programs the watchdog timer
with the timeout value selected. If the OS does not
complete booting before the timer expires, the
BMC resets the system and an error is logged.
Disabled
Requires OS support or Intel Management
Software.
O/S Boot Watchdog
Timer Policy
Power Off
Reset
If the OS boot watchdog timer is enabled, this is
the system action taken if the watchdog timer
expires.
Grayed out when the
O/S Boot Watchdog
Timer is disabled.
[Reset] - System performs a reset.
[Power Off] - System powers off.
O/S Boot Watchdog
Timer Timeout
5 minutes
10 minutes
15 minutes
If the OS watchdog timer is enabled, this is the
timeout value used by the BIOS to configure the
watchdog timer.
Grayed out when the
O/S Boot Watchdog
Timer is disabled.
20 minutes
Revision 2.0
Intel order number G52803-002
105
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Setup Item
Plug and Play BMC
Detection
Options
Enabled
Shutdown Policy
Enabled
Disabled
Help Text
If enabled, the BMC is detectable by OSs that
support plug and play loading of an IPMI driver.
Do not enable if your OS does not support this
driver.
Enable/Disable Shutdown Policy
Disabled
Comments
This option is designed
for multiple-node
system and to control
the policy that BMC
should shutdown one
node if it detected
over-current or overtemperature condition.
The BIOS and the
BMC will synchronize
the policy during the
BIOS POST and
current value of the
BMC will be displayed
in BIOS Setup.
This option only shows
on Node 3 and Node 4
Console
Redirection
View/Configure console redirection information
and settings.
Takes the user to the
Console Redirection
screen.
System Information
View system information
Takes the user to the
System Information
screen.
BMC LAN
Configuration
View/Configure BMC LAN channel and user
settings
Takes the user to the
BMC configuration
screen.
5.4.2.16
Console Redirection
The Console Redirection screen allows the user to enable or disable Console Redirection for
Remote Management, and to configure the connection options for this feature.
To access this screen from the Main screen, select Server Management > Console
Redirection. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
106
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
BIOS Setup Interface
Server Management
Console Redirection
Console Redirection
Disabled / Serial Port A / Serial Port B
Flow Control
None / RTS/CTS
Baud Rate
9.6k / 19.2k / 38.4k / 57.6k / 115.2k
Terminal Type
PC-ANSI / VT100 / VT100+ / VT-UTF8
Legacy OS Redirection
Disabled / Enabled
Terminal Resolution
80x24 / 100x31
Figure 34. Console Redirection Screen
Table 43. Setup Utility – Console Redirection Configuration Fields
Setup Item
Console Redirection
Options
Disabled
Serial Port A
Serial Port B
None
Flow Control
RTS/CTS
Help Text
Console redirection allows a serial port to be used for server
management tasks.
[Disabled] - No console redirection.
[Serial Port A] - Configure serial port A for console redirection.
[Serial Port B] - Configure serial port B for console redirection.
Enabling this option disables the display of the Quiet Boot logo
screen during POST.
Flow control is the handshake protocol.
Setting must match the remote terminal application.
[None] - Configure for no flow control.
[RTS/CTS] - Configure for hardware flow control.
Baud Rate
9600
19.2K
38.4K
57.6K
115.2K
Serial port transmission speed. Setting must match the remote
terminal application.
Terminal Type
PC-ANSI
VT100
Character formatting used for console redirection. Setting must
match the remote terminal application.
VT100+
VT-UTF8
Legacy OS
Redirection
Disabled
Enabled
This option enables legacy OS redirection (that is, DOS) on serial
port. If it is enabled, the associated serial port is hidden from the
legacy OS.
Terminal Resolution
80x24
Terminal screen resolution for console redirection.
100x31
5.4.2.17
System Information
The System Information screen allows the user to view part numbers, serial numbers, and
firmware revisions. This is an Information Only screen
Revision 2.0
Intel order number G52803-002
107
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
To access this screen from the Main screen, select Server Management > System
Information. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
Server Management
System Information
Board Part Number
<Part Number display>
Board Serial Number
<Serial Number display>
System Part Number
<Part Number display>
System Serial Number
<Serial Number display>
Chassis Part Number
<Part Number display>
Chassis Serial Number
<Serial Number display>
Asset Tag
<Asset Tag-display>
BMC Firmware Revision
<BMC FW Rev display>
HSC Firmware Revision
<HSC FW Rev display>
ME Firmware Revision
<ME FW Rev display>
SDR Revision
<SDR Rev display>
UUID
<UUID display>
Figure 35. System Information Screen
Table 44. Setup Utility – Server Management System Information Fields
Setup Item
Board Part Number
Help Text
Information only.
Board Serial Number
Information only.
System Part Number
System Serial Number
Comments
Information only.
Press <Enter> to edit system Serial Number and
then use Backspace to delete existing value.
Information only.
Maximum length is 20 characters
Chassis Part Number
Information only.
Chassis Serial Number
Information only.
Asset Tag
Press <Enter> to edit system Serial Number and
then use Backspace to delete existing value.
Information only.
Maximum length is 20 characters
108
BMC Firmware Revision
Information only
HSC Firmware Revision
Information only. If there
is no HSC installed, the
Firmware Revision Number
appears as “0,00”.
ME Firmware Revision
Information only.
SDR Revision
Information only.
UUID
Information only.
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
5.4.2.18
BIOS Setup Interface
BMC LAN Configuration
The BMC configuration screen allows the Setup user to configure the BMC Baseboard LAN
channel and the RMM4 LAN channel, and to manage BMC User settings for up to five BMC
Users.
To access this screen from the Main screen, select Server Management > System
Information. To move to another screen, press the <Esc> key to return to the Server
Management screen, then select the desired screen.
Revision 2.0
Intel order number G52803-002
109
BIOS Setup Interface
Intel®Server Boards S2400LP TPS
Server Management
BMC LAN Configuration
Baseboard LAN configuration
IP Source
IP Address
Subnet Mask
Gateway IP
Baseboard LAN IPV6 configuration
IPV6
IPV6 source
IPV6 address
Gateway IPV6
IPV6 Prefix Length
Static/Dynamic
[0.0.0.0 IP display/edit]
[0.0.0.0 IP display/edit]
[0.0.0.0 IP display/edit]
Disable/Enable
Static/Dynamic/Auto
0000:0000:0000:0000
0000:0000:0000:0000
64
®
Intel RMM4 IPV4 LAN configuration
®
Intel RMM4
IP Source
IP Address
Subnet Mask
Gateway IP
<Present/Not Present>
Static/Dynamic
[0.0.0.0 IP display/edit]
[0.0.0.0 IP display/edit]
[0.0.0.0 IP display/edit]
®
Intel RMM4 IPV6 LAN configuration
®
Intel RMM4
IPV6 Source
IPV6 Address
Gateway IPV6
IPV6 Prefix Length
<Present/Not Present>
Static/Dynamic
0000:0000:0000:0000
0000:0000:0000:0000
64
BMC DHCP Host Name
[DHCP Host Name display/edit]
User Configuration
User ID
Privilege
User status
User Name
User Password.
anonymous/root/User3/User4/User5
Callback/ User/Operator/Administrator
Disable/Enable
[User Name display/edit]
Figure 36. BMC LAN Configuration Screen
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Table 45. Setup Utility — BMC configuration Screen Fields
Setup Item
IP source
Options
Static
Dynamic
Help Text
Select BMC IP source. When Static option is
selected, IP address, subnet mask and gateway
are editable. When Dynamic option selected,
these fields are read-only and IP is address
acquired automatically (DHCP).
IP address
View/Edit IP address. Press <Enter> to edit.
Subnet Mask
View/Edit subnet address. Press <Enter> to edit.
Gateway IP
View Edit Gateway IP address. Press <Enter> to
edit.
®
Intel RMM4
Present
Comments
Information Only
Not Present
IP source
Static
Dynamic
Select BMC IP source. When Static option is
selected, IP address, subnet mask and gateway
are editable. When Dynamic option selected,
these fields are read-only and IP is address
acquired automatically (DHCP).
IP address
View/Edit IP address. Press <Enter> to edit.
Subnet Mask
View/Edit subnet address. Press <Enter> to edit.
Gateway IP
View Edit Gateway IP address. Press <Enter> to
edit.
BMC DHCP Host
Name
View/Edit BMC DHCP host name. Press <Enter>
to edit.
User ID
anonymous
Available only when IP
source for any one
channel is dynamic
option.
Select the user id to configure.
root
User3
User4
User5
Privilege
Callback
View/Select user privilege
User
Operator
Administrator
User Status
Enable
Disable
Enable/Disable LAN access for selected user.
Also enables/disables SOL, KVM media
redirection.
User Name
Press <Enter> to edit user name. User name is
string of 4 to 15 alphanumeric characters. User
name must begin with an alphabetic character.
User Password
Press <Enter> Key to enter password. Only
alphanumeric characters can be used. Maximum
length is 15 characters and case sensitive.
This filed will not
indicate whether there is
password set already.
Note: Password entered will override any
previously set password.
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BIOS Setup Interface
5.4.2.19
Intel®Server Boards S2400LP TPS
Boot Options Screen (Tab)
The Boot Options screen displays all bootable media encountered during POST, and allows the
user to configure the desired order in which boot devices are to be tried.
The first boot device in the specified Boot Order which is present and is bootable during POST
will be used to boot the system, and will continue to be used to reboot the system until the boot
device configuration has changed (that is, which boot devices are present), or until the system
has been powered down and booted in a “cold” power-on boot.
If all types of bootable devices are installed in the system, then the default boot order is
as follows:






CD/DVD-ROM
Floppy Disk Drive
Hard Disk Drive
PXE Network Device
BEV (Boot Entry Vector) Device
EFI Shell and EFI Boot paths
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Options screen
is selected.
Main
Advanced
Security
Server Management
Boot Options
System Boot Timeout
<0 – 65535, 0 is default>
Boot Option #1
<Available Boot devices>
Boot Option #2
<Available Boot devices>
Boot Option #n
<Available Boot devices>
Boot Manager
► Network Device Order
► Hard Disk Order
► Delete EFI Boot Option
EFI Optimized Boot
Enabled/Disabled
Boot Option Retry
Enabled/Disabled
USB Boot Priority
Enabled/Disabled
Static Boot Ordering
Enabled/Disabled
Reset Static Boot Order
Yes/No Action
Figure 37. Boot Options Screen
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BIOS Setup Interface
Table 46. Setup Utility – Boot Options Screen Fields
Setup Item
Boot Timeout
Options
0 - 65535
Help Text
The number of seconds the BIOS should
pause at the end of POST to allow the user
to press the [F2] key for entering the BIOS
Setup utility.
Valid values are 0-65535. Zero is the
default. A value of 65535 causes the
system to go to the Boot Manager menu
and wait for user input for every system
boot.
Boot Option #x
Available boot
devices.
Comments
After entering the
necessary timeout, press
the Enter key to register
that timeout value to the
system. These settings
are in seconds.
Set system boot order by selecting the boot
option for this position.
Hard Disk Order
Set the order of the legacy devices in this
group.
Displays when one or
more hard disk drives are
in the system.
Network Device
Order
Set the order of the legacy devices in this
group.
Displays when one or
more of these devices are
available in the system.
Delete Boot Option
Remove an EFI boot option from the boot
order.
If the EFI shell is deleted,
it is restored on the next
system reboot. It cannot
be permanently deleted.
If enabled, the BIOS only loads modules
required for booting EFI-aware Operating
Systems.
Grayed out when [SW
RAID] SATA Mode is
Enabled. SW RAID can
only be used in Legacy
Boot mode.
EFI Optimized Boot
Enabled
Disabled
Boot Option Retry
Enabled
Disabled
USB Boot Priority
Enabled
Disabled
Static Boot Ordering
Enabled
Disabled
If enabled, this continually retries non-EFIbased boot options without waiting for user
input.
If enabled newly discovered USB devices
will be put to the top of their boot device
category.
If disabled newly discovered USB devices
will be put at the bottom of the respective
list
[Disabled] - Devices removed from the
system are deleted from Boot Order Tables.
[Enabled] - Devices removed have positions
in Boot Order Tables retained for later
reinsertion.
When the option changes
to “Enabled” from
“Disabled”, it will enable
Static Boot Ordering
(SBO) from the next boot
onward, and also the
current Boot Order will be
stored as the SBO
template.
When the option changes
to “Disabled” from
“Enabled”, it will disable
SBO and the SBO
template will be cleared.
Otherwise it will retain the
current Enabled/Disabled
state.
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BIOS Setup Interface
Setup Item
Reset Static Boot
Order
Intel®Server Boards S2400LP TPS
Options
Yes
No Action
Help Text
[Yes] Take snapshot of current boot order
to save as Static Boot Order Template.
Comments
This option will allow you
to take the current Boot
Options and save it as
the Static Boot Option
template without disabling
and re-enabling the Static
Boot Ordering option.
Select “Yes” to snapshot
the current Boot Options
into the Static Boot
Options. After saving
SBO, on next boot this
option will change back to
“No Action” automatically.
5.4.2.20
Hard Disk Order
The Hard Disk Order screen allows the user to control the order in which BIOS attempts to boot
from the hard disk drives installed in the system. This screen is only available when there is at
least one hard disk device available in the system configuration. Note that a USB attached Hard
Disk drive or a USB Key device formatted as a hard disk will appear in this section.
To access this screen from the Main screen, select Boot Options > Hard Disk Order. To move
to another screen, press the <Esc> key to return to the Boot Options screen, then select the
desired screen.
Boot Options
Hard Disk Order
Hard Disk #1
<Available Hard Disk devices>
Hard Disk #2
<Available Hard Disk devices>
Figure 38. Hard Disk Order Screen
Table 47. Setup Utility — Hard Disk Order Fields
5.4.2.21
Setup Item
Hard Disk #1
Options
Available Legacy devices for
this Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
Hard Disk #2
Available Legacy devices for
this Device group.
Set system boot order by selecting the boot
option for this position.
Network Device Order
The Network Device Order screen allows the user to control the order in which BIOS attempts to
boot from the network bootable devices installed in the system. This screen is only available
when there is at least one network bootable device available in the system configuration.
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BIOS Setup Interface
To access this screen from the Main screen, select Boot Options > Network Device Order. To
move to another screen, press the <Esc> key to return to the Boot Options screen, then select
the desired screen.
Boot Options
Network Device Order
Network Device #1
<Available bootable Network devices>
Network Device #2
<Available bootable Network devices>
Figure 39. Network Device Order Screen
Table 48. Setup Utility — Network Device Order Fields
Setup Item
Network
Device #1
Options
Available Legacy devices for
this Device group.
Help Text
Set system boot order by selecting the boot
option for this position.
Network
Device #2
Available Legacy devices for
this Device group.
Set system boot order by selecting the boot
option for this position.
5.4.2.22
Delete EFI Boot Option
The Delete EFI Boot Option screen allows the user to remove an EFI boot option from the boot
order. The “Internal EFI Shell” Boot Option will not be listed, since it is permanent and cannot be
added or deleted.
To access this screen from the Main screen, select Boot Options > Delete EFI Boot Option.
To move to another screen, press the <Esc> key to return to the Boot Options screen, then
select the desired screen.
Boot Options
Delete EFI Boot Option
Delete Boot Option
<Select one to Delete>
Figure 40. Delete EFI Boot Option Screen
Table 49. Setup Utility – Delete Boot Option Fields
Setup Item
Delete Boot Option
Revision 2.0
Options
Select one to Delete
Internal EFI Shell
Help Text
Remove an EFI boot option from the
boot order.
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BIOS Setup Interface
5.4.2.23
Intel®Server Boards S2400LP TPS
Boot Manager Screen (Tab)
The Boot Manager screen allows the user to view a list of devices available for booting, and to
select a boot device for immediately booting the system. Note that this list is not in order
according to the system Boot Option order. The “Internal EFI Shell” will always be available,
regardless of whether any other bootable devices are available.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Boot Manager
screen is selected.
Main
Advanced
Security
Server Management
Boot Options
Boot Manager
Launch EFI Shell
<Boot device #1>
<Boot Option #2>
<Boot Option #n>
Figure 41. Boot Manager Screen
Table 50. Setup Utility – Boot Manager Screen Fields
5.4.2.24
Setup Item
Internal EFI Shell
Help Text
Select this option to boot now.
Note: This list is not the system boot option order. Use the
Boot Options menu to view and configure the system boot
option order.
Boot Device #n
Select this option to boot now.
Note: This list is not the system boot option order. Use the
Boot Options menu to view and configure the system boot
option order.
Error Manager Screen (Tab)
The Error Manager screen displays any POST Error Codes encountered during BIOS POST,
along with an explanation of the meaning of the Error Code in the form of a Help Text. This is an
Information Only screen.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Error Manager
screen is selected.
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Error Manager
BIOS Setup Interface
Exit
► View Event Log
ERROR CODE
SEVERITY
INSTANCE
<Post Code>
<Major/Minor>
<Instance #>>
<Description>
5224
Major
N/A
This is an example.
Figure 42. Error Manager Screen
Table 51. Setup Utility — Error Manager Screen Fields
Setup Item
Displays System Errors
5.4.2.25
Options
Help Text
Comments
Information only. Displays errors that occurred
during POST.
Save and Exit Screen (Tab)
The Exit screen allows the user to choose whether to save or discard the configuration changes
made on other Setup screens. It also allows the user to restore the BIOS settings to the factory
defaults or to save or restore them to a set of user-defined default values. If Load Default
Values is selected, the factory default settings (noted in bold in the Setup screen images) are
applied. If Load User Default Values is selected, the system is restored to previously saved
user-defined default values.
To access this screen from the Main screen or other top-level “Tab” screen, press the right or
left arrow keys to traverse the tabs at the top of the Setup screen until the Exit screen is
selected.
Error Manager
Save & Exit
Save Changes and Exit
Discard Changes and Exit
Save Changes
Discard Changes
Load Default Values
Save as User Default Values
Load User Default Values
Figure 43. Exit Screen
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Table 52. Setup Utility — Exit Screen Fields
Setup Item
Save Changes and Exit
Help Text
Exit the BIOS Setup utility after saving changes.
The system reboots if required.
Comments
User prompted for confirmation only if
any of the setup fields were modified.
The [F10] key can also be used.
Discard Changes and
Exit
Exit the BIOS Setup utility without saving
changes.
User prompted for confirmation only if
any of the setup fields were modified.
The [Esc] key can also be used.
Save Changes
Save changes without exiting the BIOS Setup
Utility.
User prompted for confirmation only if
any of the setup fields were modified.
Note: Saved changes may require a system
reboot before taking effect.
Discard Changes
Discard changes made since the last Save
Changes operation was performed.
User prompted for confirmation only if
any of the setup fields were modified.
Load Default Values
Load factory default values for all BIOS Setup
utility options.
User prompted for confirmation.
The [F9] key can also be used.
Save as User Default
Values
Save current BIOS Setup utility values as
custom user default values. If needed, the user
default values can be restored through the Load
User Default Values option below.
User prompted for confirmation.
Note: Clearing the CMOS or NVRAM does not
cause the User Default values to be reset to the
factory default values.
Load User Default
Values
Load user default values.
User prompted for confirmation.
5.5 Loading BIOS Defaults
Different mechanisms exist for resetting the system configuration to the default values. When a
request to reset the system configuration is detected, the BIOS loads the default system
configuration values during the next POST. You can send the request to reset the system to the
defaults in the following ways:

Pressing <F9> from within the BIOS Setup utility.

Moving the clear system configuration jumper.

IPMI command (set System Boot options command)


Int15 AX=DA209
Choosing Load User Defaults from the Exit page of the BIOS Setup loads user set
defaults instead of the BIOS factory defaults.
The recommended steps to load the BIOS defaults are:
1. Power down the system (Do not remove AC power).
2. Move the BIOS DFLT jumper from pins 1-2 to pins 2-3.
3. Move the BIOS DFLT jumper from pins 2-3 to pins 1-2.
4. Power up the system.
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6.
Configuration Jumpers
Configuration Jumpers
The following table provides a summary and description of configuration, test, and debug
jumpers on the Intel® Server Board S2400LP. The server board has several 3-pin jumper blocks
that can be used.
Pin 1 on each jumper block can be identified by the following symbol on the silkscreen:
Figure 44. Jumper Blocks (J9C2, J9F2, J6E1, J6E1, J6E1, J6E1)
Table 53. Server Board Jumpers (J9C2, J9F2, J6E1, J6E1, J6E1, J6E1)
Jumper Name
J9C2: BMC Force
Update jumper
Jumper Position
1-2
Mode of Operation
Normal
Normal mode
2-3
Update
BMC in force update mode
J9F2: BIOS Recovery
Mode
1-2
Normal
Normal mode, password in protection
2-3
Recovery
BIOS in recovery mode
J6E1: Password Clear
2-4
Normal
Normal mode
4-6
Update
ME in force update mode
10-12
Normal
Normal mode
8-10
Recovery
BIOS in recovery mode
1-3
Normal
Normal mode
3-5
Clear BIOS Settings
BIOS settings are reset to factory default
J6E1: ME Force Update
J6E1: BIOS Default
Revision 2.0
Note
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Configuration Jumpers
6.1
Intel®Server Boards S2400LP TPS
Force BMC Update (J9C2)
When performing a standard BMC firmware update procedure, the update utility places the
BMC into an update mode, allowing the firmware to load safely onto the flash device. In the
unlikely event the BMC firmware update process fails due to the BMC not being in the proper
update state, the server board provides a BMC Force Update jumper (J9C2) which will force the
BMC into the proper update state. The following procedure should be followed in the event the
standard BMC firmware update process fails.
Table 54. Force BMC Update Jumper
Jumper Position
1-2
2-3
Mode of
Operation
Normal
Normal operation
Update
BMC in force update mode
Note
Steps to perform Force BMC Update:
1. Power down and remove the AC power cord.
2. Open the server chassis. See your server chassis documentation for instructions.
3. Move jumper from the default operating position, covering pins1 and 2, to the enabled
position, covering pins 2 and 3.
4. Close the server chassis.
5. Reconnect the AC cord and power up the server.
6. Perform the BMC firmware update procedure as documented in the ReleaseNote.TXT
file included in the given BMC firmware update package. After successful completion of
the firmware update process, the firmware update utility may generate an error stating
the BMC is still in update mode.
7. Power down and remove the AC power cord.
8. Open the server chassis.
9. Move the jumper from the enabled position, covering pins 2 and 3 to the disabled
position, covering pins 1 and 2.
10. Close the server chassis.
11. Reconnect the AC cord and power up the server.
Note: Normal BMC functionality is disabled with the Force BMC Update jumper is set to the
enabled position. You should never run the server with the BMC Force Update jumper set in this
position. You should only use this jumper setting when the standard firmware update process
fails. This jumper should remain in the default/disabled position when the server is running
normally.
The server board has several 3-pin jumper blocks that can be used to configure, protect, or
recover specific features of the server board.
6.2
BIOS Recovery Mode (J9F2)
The Intel® Server Board S2400LP uses BIOS recovery to repair the system BIOS from flash
corruption in the main BIOS and Boot Block. This 3-pin jumper is used to reload the BIOS when
the image is suspected to be corrupted. For directions on how to recover the BIOS, refer to the
specific BIOS release notes.
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Configuration Jumpers
Table 55. BIOS Recovery Mode Jumper
Jumper
Position
1-2
2-3
Mode of
Operation
Normal
Normal mode
Recovery
BIOS in recovery mode
Note
You can accomplish a BIOS recovery from the SATA CD and USB Mass Storage device.
Please note that this platform does not support recovery from a USB floppy.
The recovery media must contain the following files under the root directory:
1.
2.
3.
4.
RML.ROM
UEFI iFlash32 11.0 Build 2 (including iFlash32.efi and ipmi.efi)
*Rec.CAP
Startup.nsh (update accordingly to use proper *Rec.CAP file)
The BIOS starts the recovery process by first loading and booting to the recovery image file
(RML.ROM) on the root directory of the recovery media (USB disk). This process takes place
before any video or console is available. Once the system boots to this recovery image file
(FVMAIN.FV), it boots automatically into the EFI Shell to invoke the Startup.nsh script and start
the flash update application (IFlash32.efi). IFlash32.efi requires the supporting BIOS Capsule
image file (*Rec.CAP).
After the update is complete, a message displays, stating the “BIOS has been updated
successfully”. This indicates the recovery process is finished.
The user should then switch the recovery jumper back to normal operation and restart the
system by performing a power cycle.
The following steps demonstrate this recovery process:
1. Power OFF the system.
2. Insert recovery media.
3. Switch the recovery jumper. Details regarding the jumper ID and location can be obtained
from the Board EPS for that Platform.
4. Power ON the system.
5. The BIOS POST screen will appear displaying the progress, and the system automatically
boots to the EFI SHELL.
6. The Startup.nsh file executes, and initiates the flash update (IFlash32.efi) with a new
capsule file (*Rec.CAP). The regular iFlash message displays at the end of the process—
once the flash update succeeds.
7. Power OFF the system, and revert the recovery jumper position to "normal operation".
8. Power ON the system.
9. Do NOT interrupt the BIOS POST during the first boot.
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6.3
Intel®Server Boards S2400LP TPS
Password Clear (J6E1)
The user sets this 3-pin jumper to clear the password.
Table 56. Password Clear Jumper
Jumper Position
2-4
4-6
Mode of Operation
Normal
Note
Normal mode, password in protection
Clear Password
BIOS password is cleared
Steps to perform the password clear:
1. Power down server. Do not unplug the power cord.
2. Open the chassis. For instructions, see your server chassis documentation.
3. Move jumper (J6E1) from the default operating position, covering pins 2 and 4, to the
password clear position, covering pins 4 and 6.
4. Close the server chassis.
5. Power up the server, wait 10 seconds or POST completes.
6. Power down the server.
7. Open the chassis and move the jumper back to default position, covering pins 2 and 4.
8. Close the server chassis.
9. Power up the server. The password is now cleared and you can reset it by going into the
BIOS setup. The BIOS password is now cleared.
6.4
Force ME Update (J6E1)
When this 3-pin jumper is set, it manually puts the ME firmware in update mode, which enables
the user to update ME firmware code when necessary.
Table 57. Force ME Update Jumper
Jumper Position
10-12
8-10
Mode of
Operation
Normal
Normal operation
Update
ME in force update mode
Note
Note: Normal ME functionality is disabled with the Force ME Update jumper is set to the
enabled position. You should never run the server with the ME Force Update jumper set in this
position. You should only use this jumper setting when the standard firmware update process
fails. This jumper should remain in the default/disabled position when the server is
running normally.
Steps to perform the Force ME Update:
122
1.
Power down and remove the AC power cord.
2.
Open the server chassis. For instructions, see your server chassis documentation.
3.
Move jumper from the default operating position (covering pins 10 and 12) to the
enabled position (covering pins 8 and 10).
4.
Close the server chassis.
5.
Reconnect the AC cord and power up the server.
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Configuration Jumpers
6.
Perform the ME firmware update procedure as documented in the README.TXT file
that is included in the given ME firmware update package (same package as BIOS).
7.
Power down and remove the AC power cord.
8.
Open the server chassis.
9.
Move jumper from the enabled position (covering pins 8 and 10) to the disabled position
(covering pins 10 and 12).
10. Close the server chassis.
The password is now cleared and you can reset it by going into the BIOS setup.
6.5
Reset BIOS Settings (J6E1)
This jumper used to be the CMOS Clear jumper. The BIOS has moved CMOS data to the
NVRAM region of the BIOS flash since the previous generation. The BIOS checks during boot
to determine if the data in the NVRAM must be set to default.
Table 58. Reset BIOS Jumper
Jumper Position
1-3
3-5
Mode of Operation
Normal
Note
These pins should have a jumper in place for normal
system operation. (Default)
Reset BIOS Configuration
If these pins 3-5 are connected with AC power plugged,
the CMOS settings are cleared within five seconds.
These pins should not be connected for normal
operation.
Steps to clear BIOS settings:
1. Power down server. Do not unplug the power cord.
2. Open the server chassis. For instructions, see your server chassis documentation.
3. Move jumper (J1D5) from the default operating position, covering pins 1 and 3, to the
reset/clear position, covering pins 3 and 5.
4. Wait five seconds.
5. Remove AC power.
6. Move the jumper back to default position, covering pins 1 and 3.
7. Close the server chassis.
8. Power up the server.
The BIOS settings are now cleared and you can reset it by going into the BIOS setup.
Note: Removing AC Power before performing the BIOS settings Clear operation causes the
system to automatically power up and immediately power down, after the procedure is followed
and AC power is re-applied. If this happens, remove the AC power cord again, wait 30 seconds,
and re-install the AC power cord. Power-up the system and proceed to the <F2> BIOS Setup
Utility to reset the desired settings.
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Connector/Header Locations and Pin-out
Intel®Server Boards S2400LP TPS
7.
Connector/Header Locations and Pin-out
7.1
Power Connectors
To facilitate customers who want to cable to this board from a power supply, the power
connector is implemented through two 6pin pin Minifit Jr connectors, that can be used to deliver
12amps per pin or 60+Amps total. Note that no over-voltage protective circuits will exist on
the board.
Table 59. Main Power Supply Connector 6-pin 2x3 Connector (J1D1 and J1A2)
Pin
1
2
3
7.2
Signal Name
+12V
+12V
+12V
Pin
4
5
6
Signal Name
GND
GND
GND
System Management Headers
7.2.1 Intel®Remote Management Module 4 (Intel®RMM4 Lite) Connector
A 7-pin Intel® RMM4 Lite connector (J7F2) is included on the server board to support the
optional Intel® Remote Management Module 4. There is no support for third-party management
cards on this server board.
Note: This connector is not compatible with the Intel® Remote Management Module 3
(Intel® RMM3).
®
Table 60. Intel RMM4 Lite Connector Pin-out (J7F2)
Pin
1
3
5
7
7.3
Signal Description
DI
CLK
GND
GND
Pin
2
4
6
8
Signal Description
VCC
KEY
DO
CS_N
Bridge Board Connector
The bridge board delivers SATA/SAS signals, Disk back plane management signals, BMC
SMBUS*’s as well as SSI-Compliant front panel and miscellaneous node specific signals. The
fifth SAS connection was added to support a Raid 5 + hot spare configuration. This drives the
addition of a second set of SGPIO pins.
Table 61. Bridge Board Connector (J6A1)
Pin #
124
Signal
Pin #
Signal
1
5V Aux
2
5V Aux
3
Reserved
4
Reserved
5
Reserved
6
GND
7
GND
8
Reserved
9
NODE_Present_N
(Connect to GND on Base
10
Reserved
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Intel®Server Boards S2400LP TPS
Pin #
Connector/Header Locations and Pin-out
Signal
Pin #
Signal
baord)
11
ALL_NODE_OFF
12
GND
13
spare
14
USB2_P0P
15
GND
16
USB2_P0N
17
IPMB-Data
18
GND
19
IPMB-Clk
20
FP HDD_ACT_LED_N
21
GND
22
FP Activity LED_N
23
SMBUS_R1 DATA
24
FP Health LEDA_N
25
SMBUS_R1 CLK
26
FP Health LEDG_N
27
GND
28
FP PWR LED_N
29
SMBUS_R5 DATA
30
FP ID LED_N
31
SMBUS_R5 CLK
32
FP ID BTN_N
33
GND
34
FP RST BTN_N
35
SMBUS_R7 DATA
36
FP PWR BTN_N
37
SMBUS_R7 CLK
38
FP NMI BTN_N
39
GND
40
SPA_SOUT_N
41
PMBUS Alert_N
42
SPA_SIN_N
43
NODEx_ON_N
44
ID3
45
SGPIO DATA IN
46
ID2
47
SGPIO Data Out
48
ID1
49
SGPIO LD
50
ID0
51
SPKR
52
SGPIO CLK
53
GND
54
GND
55
SAS3_RXP
56
SAS3_TXN
57
SAS3_RXN
58
SAS3_TXP
59
GND
60
GND
61
SAS2_TXP
62
SAS2_RXN
63
SAS2_TXN
64
SAS2_RXP
65
GND
66
GND
67
SAS1_RXP
68
SAS1_TXN
69
SAS1_RXN
70
SAS1_TXP
71
GND
72
GND
73
SAS0_TXP
74
SAS0_RXN
75
SAS0_TXN
76
SAS0_RXP
77
GND
78
GND
79
GND
80
SATA_SAS_N
Combined system BIOS and the BMC support provide the functionality of the various supported
control panel buttons and LEDs. The following sections describe the supported functionality of
each control panel feature.
7.3.1 Power Button
The BIOS supports a front control panel power button. Pressing the power button initiates a
request that the BMC forwards to the ACPI power state machines in the chipset. It is monitored
by the BMC and does not directly control power on the power supply.
Revision 2.0
Intel order number G52803-002
125
Connector/Header Locations and Pin-out



Intel®Server Boards S2400LP TPS
Power Button — Off to On
The BMC monitors the power button and the wake-up event signals from the chipset. A
transition from either source results in the BMC starting the power-up sequence. Since
the processors are not executing, the BIOS does not participate in this sequence. The
hardware receives the power good and reset signals from the BMC and then transitions
to an ON state.
Power Button — On to Off (operating system absent)
The System Control Interrupt (SCI) is masked. The BIOS sets up the power button event
to generate an SMI and checks the power button status bit in the ACPI hardware
registers when an SMI occurs. If the status bit is set, the BIOS sets the ACPI power state
of the machine in the chipset to the OFF state. The BMC monitors power state signals
from the chipset and de-asserts PS_PWR_ON to the power supply. As a safety
mechanism, if the BIOS fails to service the request, the BMC automatically powers off
the system in four to five seconds.
Power Button — On to Off (operating system present)
If an ACPI operating system is running, pressing the power button switch generates a
request through SCI to the operating system to shut down the system. The operating
system retains control of the system and the operating system policy determines the
sleep state into which the system transitions, if any. Otherwise, the BIOS turns off the
system.
7.3.2 Reset Button
The platform supports a front control panel reset button. Pressing the reset button initiates a
request forwarded by the BMC to the chipset. The BIOS does not affect the behavior of the
reset button.
7.3.3 Chassis Identify Button
The front panel Chassis Identify button toggles the state of the chassis ID LED. If the LED is off,
pushing the ID button lights the LED. It remains lit until the button is pushed again or until a
Chassis Identify or a Chassis Identify LED command is received to change the state of the LED.
7.3.4 Power LED
The green power LED is active when the system DC power is on. The power LED is controlled
by the BIOS. The power LED reflects a combination of the state of system (DC) power and the
system ACPI state. The following table identifies the different states that the power LED
can assume.
Table 62. Power LED Indicator States
State
Power off
Power on
S5
S1 Sleep
S0
ACPI
No
No
Yes
Yes
Yes
Power LED
Off
Solid on
Off
~1 Hz blink
Solid on
7.3.5 System Status LED
Note: The system status LED state shows the state for the current, most severe fault. For
example, if there was a critical fault due to one source and a non-critical fault due to another
source, the system status LED state would be solid on (the critical fault state).
126
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Connector/Header Locations and Pin-out
The system status LED is a bicolor LED. Green (status) shows a normal operation state or a
degraded operation. Amber (fault) shows the system hardware state and overrides the
green status.
The BMC-detected state and the state from the other controllers, such as the SCSI/SATA hotswap controller state, are included in the LED state. For fault states monitored by the BMC
sensors, the contribution to the LED state follows the associated sensor state, with the priority
going to the most critical state currently asserted.
When the server is powered down (transitions to the DC-off state or S5), the BMC is still on
standby power and retains the sensor and front panel status LED state established prior to the
power-down event.
The following table maps the system state to the LED state.
Figure 45. System Status LED (A) and ID LED (B)
Revision 2.0
Intel order number G52803-002
127
Connector/Header Locations and Pin-out
Intel®Server Boards S2400LP TPS
Table 63. System Status LED
Color
State
System Status
Green
Green
Solid on
~1 Hz blink
Degraded
Amber
~1 Hz blink
Non-Fatal
Amber
Solid on
Fatal
Off
N/A
Not ready
Description
Ok System ready
BIOS detected
 Unable to use all of the installed memory (more than one DIMM
installed).1
 In a mirrored configuration, when memory mirroring takes place
and system loses memory redundancy. This is not covered by
(2). 1
 PCI Express* correctable link errors.
BMC detected
 Redundancy loss such as a power supply or fan. Applies only if
the associated platform subsystem has redundancy capabilities.
 CPU disabled – if there are two CPUs and one CPU is disabled.
 Fan alarm – Fan failure. Number of operational fans should be
more than minimum number needed to cool the system.
 Non-critical threshold crossed – Temperature, voltage, power
nozzle, power gauge, and PROCHOT2 (Therm Ctrl) sensors.
 Battery failure.
 Predictive failure when the system has redundant power
supplies.
Non-fatal alarm – system is likely to fail:
BIOS Detected
 In non-mirroring mode, if the threshold of ten correctable errors is
crossed within the window.1
 PCI Express* uncorrectable link errors.
BMC Detected
 Critical threshold crossed – Voltage, temperature, power nozzle,
power gauge, and PROCHOT (therm Ctrl) sensors.
 VRD Hot asserted.
 Minimum number of fans to cool the system is not present or
have failed.
Fatal alarm – system has failed or shut down:
BIOS Detected
 DIMM failure when there is one DIMM present and no good
memory is present.1
 Run-time memory uncorrectable error in non-redundant mode.1
 CPU configuration error (for instance, processor stepping
mismatch).
BMC Detected
 CPU CATERR signal asserted.
 CPU 1 is missing.
 CPU THERMTRIP.
 No power good – power fault.
 Power Unit Redundancy sensor – Insufficient resources offset
(indicates not enough power supplies are present).
Main power off
Notes:
1. The BIOS detects these conditions and sends a Set Fault Indication command to the BMC to provide the
contribution to the system status LED.
2. Support for an upper, non-critical threshold limit is not provided in default SDR configuration. However if a
user does enable this threshold in the SDR, then the system status LED should behave as described.
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Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Connector/Header Locations and Pin-out
7.3.6 Chassis ID LED
The chassis ID LED provides a visual indication of a system being serviced. The state of the
chassis ID LED is affected by the following:

Toggled by the chassis ID button

Controlled by the Chassis Identify command (IPMI)

Controlled by the Chassis Identify LED command (OEM)
Table 64. Chassis ID LED Indicator States
State
LED State
Identify active through button
Identify active through command
Off
Solid on
~1 Hz blink
Off
There is no precedence or lock-out mechanism for the control sources. When a new request
arrives, all previous requests are terminated. For example, if the chassis ID LED is blinking and
the chassis ID button is pressed, then the chassis ID LED changes to solid on. If the button is
pressed again with no intervening commands, the chassis ID LED turns off.
7.4
I/O Connectors
7.4.1 PCI Express* Connectors
The Intel® Server Board S2400LP uses two PCI Express* slots physically with different pint out
definition. Each riser slot has dedicated usage and cannot be used for normal PCIe based addin card.

Riser Slot 1: Riser to support PCIe x16 add-in card

Riser Slot 2: Riser to support PCIe x8 add-in card, or Intel® IOM card
The pin-outs for the slots are shown in the following tables.
Table 65. PCI Express* x16 Riser Slot 1 Connector (J8F1)
Pin
B1
B2
B3
B4
B5
PCIe
Riser
12V
20W 3.3V generated on riser
12V
12V
12V
66W for GPU
66W for GPU
66W for GPU
For wake on LAN
Pin
A1
PCIe
Riser
12V
20W 3.3V generated on riser
12V
12V
SMDATA
66W for GPU
66W for GPU
SMCLK
A2
A3
A4
A5
3.3VAUX
For wake on LAN
B6
3.3VAUX
A6
GPU_NODE_ON
can turn of 2U GPU power
B7
GND
A7
GPU_PWRGD
monitor if needed
B8
Tach9
A8
Tach11
B9
Tach8
A9
Tach10
Tach7
A10
Tach6
B10
B11
B12
KEY
KEY
KEY
KEY
Spare
A11
Spare
Spare
A12
PWM2
Revision 2.0
Intel order number G52803-002
GPU Fan speed control
129
Connector/Header Locations and Pin-out
Pin
PCIe
Riser
B13
Spare
B14
B17
GND
SMBUS_R4
CLK
SMBUS_R4
DAT
GND
B18
PETxP0
Tx Lane 0+
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
PETxN0
GND
GND
PETxP1
PETxN1
GND
GND
PETxP2
PETxN2
GND
GND
PETxP3
PETxN3
GND
GND
PETxP4
PETxN4
GND
GND
PETxP5
PETxN5
GND
GND
PETxP6
PETxN6
GND
Tx Lane 0-
B45
GND
B46
B47
B48
PETxP7
PETxN7
GND
B49
B15
B16
B50
B51
B52
B53
B54
B55
B56
B57
B58
130
Intel®Server Boards S2400LP TPS
Pin
A13
GND
A14
PERST#
A15
A16
PCIe
Riser
WAKE#
GND
A17
A18
REFCLK+
Clock pair 1
REFCLK-
Clock pair 1
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
GND
PERxP0
PERxN0
GND
GND
PERxP1
PERxN1
GND
GND
PERxP2
PERxN2
GND
GND
PERxP3
PERxN3
GND
GND
PERxP4
PERxN4
GND
GND
PERxP5
PERxN5
GND
GND
PERxP6
PERxN6
Rx Lane 6-
GND
GND
PERxP7
Rx Lane 7+
GND
A46
A47
A48
A49
PERxN7
Rx Lane 7-
PETxP8
PETxN8
GND
GND
PETxP9
PETxN9
GND
GND
PETxP10
A50
A51
A52
A53
A54
A55
A56
A57
A58
GND
GND
PERxP8
PERxN8
GND
GND
PERxP9
PERxN9
GND
Tx Lane 1+
Tx Lane 1-
Tx Lane 2+
Tx Lane 2-
Tx Lane 3+
Tx Lane 3-
Tx Lane 4+
Tx Lane 4-
Tx Lane 5+
Tx Lane 5-
Tx Lane 6+
Tx Lane 6-
Tx Lane 7+
Tx Lane 7-
Tx Lane 8+
Tx Lane 8-
Tx Lane 9+
Tx Lane 9-
Tx Lane 10+
Intel order number G52803-002
Rx Lane 0+
Rx Lane 0-
Rx Lane 1+
Rx Lane 1-
Rx Lane 2+
Rx Lane 2-
Rx Lane 3+
Rx Lane 3-
Rx Lane 4+
Rx Lane 4-
Rx Lane 5+
Rx Lane 5-
Rx Lane 6+
Rx Lane 8+
Rx Lane 8-
Rx Lane 9+
Rx Lane 9-
Revision 2.0
Intel®Server Boards S2400LP TPS
Pin
PCIe
Connector/Header Locations and Pin-out
Riser
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
PETxN10
GND
GND
PETxP11
PETxN11
GND
GND
PETxP12
PETxN12
GND
GND
PETxP13
PETxN13
GND
GND
PETxP14
PETxN14
GND
REFCLK+
REFCLKGND
PETxP15
Tx Lane 10-
B81
PETxN15
Tx Lane 15-
Pin
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
Tx Lane 11+
Tx Lane 11-
Tx Lane 12+
Tx Lane 12-
Tx Lane 13+
Tx Lane 13-
Tx Lane 14+
Tx Lane 14Clock pair 2
Clock pair 2
Tx Lane 15+
PCIe
GND
PERxP10
PERxN10
GND
GND
PERxP11
PERxN11
GND
GND
PERxP12
PERxN12
GND
GND
PERxP13
PERxN13
GND
GND
PERxP14
PERxN14
GND
PERxP15
PERxN15
Riser
Rx Lane 10+
Rx Lane 10-
Rx Lane 11+
Rx Lane 11-
Rx Lane 12+
Rx Lane 12-
Rx Lane 13+
Rx Lane 13-
Rx Lane 14+
Rx Lane 14Rx Lane 15+
Rx Lane 15-
GND
Table 66. PCI Express* x8 Riser Slot 2 Connector (J8A1)
Pin
B1
B2
B3
B4
B5
B6
PCIe
Riser
3.3V generated on
Pin
A1
for GPU
for GPU
for GPU
A2
A3
A4
A5
12V
12V
12V
20W
riser
66W
66W
66W
SMCLK
for rIOM temp sensor
3.3V Aux
For DNM and IOM wake on
LAN
12V
B7
B8
B9
B10
B11
GND
TXD_0
TXD_1
TXD_2
B12
B13
B14
B15
B16
B17
GND
TX_CLK
TX_CTL
MDIO
PERST#
WAKE#
TXD_3
Revision 2.0
RGMII txmit data
RGMII txmit data
RGMII txmit data
RGMII txmit data
KEY
KEY
RGMII txmit Clock
RGMII txmit Cntrl
A6
PCIe
Riser
12V
20W 3.3V generated on riser
12V
12V
SMDATA
66W for GPU
66W for GPU
for rIOM temp sensor
For DNM and IOM wake on
LAN
5VAUX
PRESENT#
DNM function present
A7
A8
A9
A10
A11
RIOM_ACT#
RXD_3
RXD_2
RXD_1
RGMII receive data
RGMII receive data
RGMII receive data
RXD_0
RGMII receive data
KEY
KEY
A12
A13
A14
A15
A16
A17
RX_CTL
GND
RX_CLK
MDC
GND
REFCLK+
RGMII receive Cntrl
Intel order number G52803-002
RGMII receive Clock
Clock pair 1
131
Connector/Header Locations and Pin-out
Pin
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
132
PCIe
PETxP0
PETxN0
GND
GND
PETxP1
PETxN1
GND
GND
PETxP2
PETxN2
GND
GND
PETxP3
PETxN3
GND
GND
PETxP4
PETxN4
GND
GND
PETxP5
PETxN5
GND
GND
PETxP6
PETxN6
GND
GND
PETxP7
PETxN7
GND
GND
PETxP8
PETxN8
GND
GND
PETxP9
PETxN9
GND
GND
PETxP10
PETxN10
GND
GND
PETxP11
PETxN11
GND
Intel®Server Boards S2400LP TPS
Riser
Tx Lane 0+
Tx Lane 0-
Tx Lane 1+
Tx Lane 1-
Tx Lane 2+
Tx Lane 2-
Tx Lane 3+
Tx Lane 3-
Tx Lane 4+
Tx Lane 4-
Tx Lane 5+
Tx Lane 5-
Tx Lane 6+
Tx Lane 6-
Tx Lane 7+
Tx Lane 7-
Tx Lane 8+
Tx Lane 8-
Pin
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
PCIe
REFCLKGND
PERxP0
PERxN0
GND
GND
PERxP1
PERxN1
GND
GND
PERxP2
PERxN2
GND
GND
PERxP3
PERxN3
GND
GND
PERxP4
PERxN4
GND
GND
PERxP5
PERxN5
GND
GND
PERxP6
PERxN6
GND
GND
PERxP7
PERxN7
GND
GND
PERxP8
PERxN8
GND
GND
PERxP9
PERxN9
GND
GND
PERxP10
PERxN10
GND
GND
PERxP11
Intel order number G52803-002
Riser
Clock pair 1
Rx Lane 0+
Rx Lane 0-
Rx Lane 1+
Rx Lane 1-
Rx Lane 2+
Rx Lane 2-
Rx Lane 3+
Rx Lane 3-
Rx Lane 4+
Rx Lane 4-
Rx Lane 5+
Rx Lane 5-
Rx Lane 6+
Rx Lane 6-
Rx Lane 7+
Rx Lane 7-
Revision 2.0
Intel®Server Boards S2400LP TPS
Pin
PCIe
Connector/Header Locations and Pin-out
Riser
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
GND
PETxP12
PETxN12
GND
GND
PETxP13
PETxN13
GND
GND
PETxP14
PETxN14
GND
REFCLK+
REFCLKGND
PETxP15
PETxN15
B82
GND
Pin
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
PCIe
Riser
PERxN11
GND
GND
PERxP12
PERxN12
GND
GND
PERxP13
PERxN13
GND
GND
PERxP14
PERxN14
GND
PERxP15
PERxN15
GND
Riser ID
Table 67. PCI Express* Riser ID Assignment
CPU1
Description
Riser 1 1x16
Riser 1 2x8
Riser 2 1x16
Riser 2 2x8
Riser ID(1)
1
0
Riser ID(2)
1
0
7.4.2 VGA Connector
The following table details the pin-out definition of the external VGA connector (J9D1).
Table 68. VGA External Video Connector (J9D1)
Pin
Revision 2.0
1
Signal Name
V_IO_R_CONN
Description
Red (analog color signal R)
2
V_IO_G_CONN
Green (analog color signal G)
3
V_IO_B_CONN
Blue (analog color signal B)
4
TP_VID_CONN_B4
No connection
5
GND
Ground
6
GND
Ground
7
GND
Ground
8
GND
Ground
9
TP_VID_CONN_B9
No connection
10
GND
Ground
11
TP_VID_CONN_B11
No connection
12
V_IO_DDCDAT
DDCDAT
13
V_IO_HSYNC_CONN
HSYNC (horizontal sync)
Intel order number G52803-002
133
Connector/Header Locations and Pin-out
Intel®Server Boards S2400LP TPS
Pin
14
Signal Name
V_IO_VSYNC_CONN
Description
VSYNC (vertical sync)
15
V_IO_DDCCLK
DDCCLK
7.4.3 NIC Connectors
The server board provides two independent RJ-45 connectors on the back edge of the board
(JA9F1, JA9E1). The pin-out for NIC connectors are identical and are defined in the
following table.
Table 69. RJ-45 10/100/1000 NIC Connector Pin-out (JA9F1, JA9E1)
7.4.4 SATA DOM Connectors
The server board provides one SATA DOM port (J7F1) connector on board. Additional four SAS
ports are provided through bridge board.
The pin configuration for each connector is identical and defined in the following table.
Table 70. SATA DOM Connector
Pin
1
2
3
4
5
6
7
Signal Name
GND
SATA_TX_P
SATA_TX_N
GND
SATA_RX_N
SATA_RX_P
P5V_SATA/GND
Description
Ground
Positive side of transmit differential pair
Negative side of transmit differential pair
Ground
Negative side of receive differential pair
Positive side of receive differential pair
+5V for DOM or Ground for SATA signals
7.4.5 Storage Upgrade Key Connector
The server board provides one SATA/SAS storage upgrade key connector (J9F1) on board. The
Storage Upgrade Key is a small PCB board that has up to two security EEPROMs that are read
134
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Connector/Header Locations and Pin-out
by the system ME to enable different versions of LSI RAID 5 software stack and/or upgrade
from SATA to SAS storage functionality.
The pin configuration of connector is identical and defined in the following table.
Table 71. Storage Upgrade Key Connector (J9F1)
Pin
Signal Description
GND
PBG_DYN_RAID_KEY
GND
SAS/SATA RAID KEY
1
2
3
4
7.4.6 Serial Port Connectors
The server board provides one internal 9-pin serial ‘A’ header (J8F5). The following tables
define the pin-outs.
Table 72. Internal 9-pin Serial A (COM1) (J8F5)
Pin
1
3
5
7
9
Signal Name
SPB_DCD
SPB_SIN_N
SPB_SOUT_N
SPB_DTR
GND
Pin
2
4
6
8
Signal Name
SPB_DSR
SPB_RTS
SPB_CTS
SPB_RI
7.4.7 USB Connectors
The following table details the pin-out of the external stack USB port 0/1 connectors (J9C1)
found on the back edge of the server board.
Table 73. External USB port Connector (J9C1)
Pin
1
2
3
4
Signal Name
+5V
USB_N
USB_P
GND
Description
USB Power
Differential data line paired with DATAH0
Differential date line paired with DATAL0
Ground
7.4.8 QSFP for InfiniBand*
The following table details the pin-out of the QSFP connector (J9B2) found on the back edge of
the server board. This port is only available on board SKU S2400LPQ
Table 74. QSFP Pin Definition
Side A
1
2
3
4
5
6
Revision 2.0
Signal
GND
IB_RX0_DN0
IB_RX0_DP0
GND
IB_RX0_DN2
IB_RX0_DP2
Side B
1
2
3
4
5
6
Signal
GND
IB_RX0_DN1
IB_RX0_DP1
GND
IB_RX0_DN3
IB_RX0_DP3
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Connector/Header Locations and Pin-out
Side A
7
8
9
10
11
12
13
14
15
16
17
18
19
7.5
Intel®Server Boards S2400LP TPS
Signal
GND
SMB_IB_QSFP0_DATA
SMB_IB_QSFP0_CLK
P3V3_RX_PORT0
RST_QSFP0_N
FM_QSFP0_MODSEIL_N
GND
IB_TX0_DP3
IB_TX0_DN3
GND
IB_TX0_DP1
IB_TX0_DN1
GND
Side B
7
8
9
10
11
12
13
14
15
16
17
18
19
Signal
GND
QSFP0_MODPRSL_N
IRQ_QSFP0_N
P3V3_TX_PORT0
P3V3_PORT0
QSFP0_LPMODE
GND
IB_TX0_DP2
IB_TX0_DN2
GND
IB_TX0_DP0
IB_TX0_DN0
GND
Fan Headers
To facilitate the connection of 3 x40mm double rotor fans, a 14 pin header is provided, all fans
will share a PWM. Both rotor tachs can be monitored.
Table 75. Baseboard Fan Connector (J1A1)
Pin
Signal Name
Pin
Signal Name
1
PWM1
2
Reserved
3
Tach0
4
Tach1
5
7
Tach2
Tach4
6
8
Tach3
Tach5
9
NODE_ON
10
GND
11
SMBUS_R4 CLK
12
SMBUS_R4 DAT
13
NODE_ADR0
14
NODE_PWRGD
The SMBUS* is used to connect to the hot swap controller that provides inrush current
protection and can measure the power being used by the node. The NODE_ON signal is used
to turn on the hot swap controller. Note that the polarity is correct as the ADI1275 controller uses
a high true enable signal. When the node is turned off, the fans will continue to rotate at a preset
rate; this rate is selected by Intel and preset by the Fan manufacturer. This is done to stop air
recirculation between nodes. When docking the board to a live 12V rail, the fans could spin up
immediately; it may be required to phase their connection to power to minimize the inrush
current. Bench testing of the fans should determine if this is necessary.
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8.
Intel®Light-Guided Diagnostics
Intel®Light-Guided Diagnostics
Intel® Server Board S2400LP has several onboard diagnostic LEDs to assist in troubleshooting
board-level issues. This section provides a description the location and function of each LED on
the server board.
8.1
Front Panel Support
The Intel® Server Board S2400LP supports Mini-FP on Intel® Server Chassis H2000LP. The
front panel control signals are provided through bridge board.
Each Mini-FP provides the below switch and LED features
 Power switch with integrated power LED (green), includes clear button lens but
painted black with laser etched power icon for light to shine through

Chassis ID switch with integrated ID LED (blue), includes clear button lens but
painted black with laser etched ID icon for light to shine through

Recessed reset switch with black actuator

Bi-color Status/Fault LED (green/amber). Includes a status/fault icon printed on
cosmetic front panel label. Icon should be translucent (only shows when LED is on).

Single network activity/link LED, hardware baseboard ORs Ethernet and Infiniband*
activity signals together into just one global signal. Includes a network activity/link
icon printed on cosmetic front panel label. Icon should be translucent (only shows
when LED is on).
8.1.1 System ID LED
The server board supports a blue system ID LED on the front panel, which is used to visually identify a
specific server installed among many other similar servers. There are two options available for
illuminating the System ID LED.
1. The front panel ID LED Button is pushed, which causes the LED to illuminate to a solid on state
until the button is pushed again.
2. An IPMI “Chassis Identify” command is remotely entered, which causes the LED to blink
The System ID LED on the server board is tied directly to the System ID LED on system front panel if
present.
8.1.2 System Status LED
The server board supports status LED on the front panel, which acts as same as the status LED
on the server board.
8.1.3 Network Link/Activity LED
The server board provides LED on the front panel for Network Link/Activity. On S2400LP base
SKU, this LED shows the status of Ethernet port. On S2400LPQ, S2400LPF and S2400LPT,
this shows the combination of both Ethernet port and InfiniBand* QSFP link and activities.
Below table shows the LED detail.
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Table 76. Network link/activity LED
LED
Color
LAN – Link/Activity
Green
Green
Condition
On
Blink
Off
What It Means
LAN link/no access
LAN access
Idle/no access
8.1.4 Dedicated InfiniBand* Link/Activity LED
The server board provides dedicated LEDs for InfiniBand* Link/Activity. They are located on the
baseboard rear, near diagnostic LED set. This set of LEDs only works on S2400LPQ and
S2400LPF baseboard. The following table shows the LED detail.
Table 77. InfiniBand* link/activity LED
LED Color
Amber (Right)
Green (Left)
8.2
LED State
NIC State
Off
No Logical Link
Blinking
Logincal Link established
Off
No Physical Link
On
Physical Link established
POST Code Diagnostic LEDs
Eight amber POST code diagnostic LEDs are located on the back left edge of the server board
in the rear I/O area of the server board by the QSFP connector.
During the system boot process, the BIOS executes a number of platform configuration
processes, each of which is assigned a specific hex POST code number. As each configuration
routine is started, the BIOS displays the given POST code to the POST code diagnostic LEDs
on the back edge of the server board. To assist in troubleshooting a system hang during the
POST process, you can use the Diagnostic LEDs to identify the last POST process executed.
For a complete description of how these LEDs are read and a list of all supported POST codes,
refer to Appendix A.
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Intel®Light-Guided Diagnostics
Figure 46. Rear Panel Diagnostic LEDs (Block A)
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Environmental Limits Specification
9.
Intel®Server Boards S2400LP TPS
Environmental Limits Specification
Operation of the server board at conditions beyond those shown in the following table may
cause permanent damage to the system. Exposure to absolute maximum rating conditions for
extended periods may affect long term system reliability.
Note: The Energy Star compliance is at systems level, but not board level. Use of Intel® boards
alone does not guarantee Energy Star compliance.
Table 78. Server Board Design Specifications
1
Operating Temperature
0ºC to 55ºC (32ºF to 131ºF) at product
airflow specification
Non-Operating Temperature
-40ºC to 70ºC (-40ºF to 158ºF)
DC Voltage
± 5% of all nominal voltages
Shock (Unpackaged)
Trapezoidal, 50 G, 170 inches/sec
Shock (Packaged)
<20 pounds
>= 20 to <40 pounds
>= 40 to <80 pounds
>= 80 to <100 pounds
>= 100 to <120 pounds
>= 120 pounds
36 inches
30 inches
24 inches
18 inches
12 inches
9 inches
Vibration (Unpackaged)
5 Hz to 500 Hz 3.13 g RMS random
Note:
®
®
Chassis design must provide proper airflow to avoid exceeding the Intel Xeon processor maximum case
temperature.
9.1
Processor Thermal Design Power (TDP) Support
To allow optimal operation and long-term reliability of Intel processor-based systems, the
processor must remain within the defined minimum and maximum case temperature (TCASE)
specifications. Thermal solutions not designed to provide sufficient thermal capability may affect
the long-term reliability of the processor and system. The server board is designed to support
the Intel® Xeon® Processor E5-2400 product family TDP guidelines up to and including 95W.
Disclaimer Note: Intel Corporation server boards contain a number of high-density VLSI and
power delivery components that need adequate airflow to cool. Intel ensures through its own
chassis development and testing that when Intel server building blocks are used together, the
fully integrated system will meet the intended thermal requirements of these components. It is
the responsibility of the system integrator who chooses not to use Intel developed server
building blocks to consult vendor datasheets and operating parameters to determine the amount
of airflow required for their specific application and environmental conditions. Intel Corporation
cannot be held responsible, if components fail or the server board does not operate correctly
when used outside any of their published operating or non-operating limits.
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Power Supply Specification Guidelines
10. Power Supply Specification Guidelines
This section provides power supply specification guidelines recommended for providing the
specified server platform with stable operating power requirements.
Note: The power supply data provided in this section is for reference purposes only. It reflects
Intel’s own DC power out requirements for a 1200W and 1600W power supply as used in an
Intel designed 2U server platform. The intent of this section is to provide customers with a guide
to assist in defining and/or selecting a power supply for custom server platform designs that
utilize the server boards detailed in this document.
10.1 Power Supply DC Output Connector
The server board includes two main power Minifit Jr connectors allowing for power supplies to
attach directly to the server board. The connectors are two sets of 2x3 pin and can be used to
deliver 12amps per pin or 60+Amps total. Note that no over-voltage protective circuits will exist
on the board.
Table 79. Power Supply DC Power Input Connector Pinout
Pin
1
2
3
Signal Name
+12V
+12V
+12V
Pin
4
5
6
Signal Name
GND
GND
GND
10.2 Power Supply DC Output Specification
10.2.1 Output Power/Currents
The following tables define the minimum power and current ratings. The power supply must
meet both static and dynamic voltage regulation requirements for all conditions.
Table 80. Minimum Load Ratings
Parameter
12V main
5Vstby
Min
0.0
0.0
Max.
60.0
2.0
Peak 1, 2
72.0
2.4
Unit
A
A
Notes:
1. Peak combined power for all outputs shall not exceed 800W.
2. Length of time peak power can be supported is based on thermal sensor and assertion of the SMBAlert# signal.
Minimum peak power duration shall be 20 seconds without asserting the SMBAlert# signal at maximum
operating temperature.
10.2.2 Standby Output
The 5VSB output shall be present when an AC input greater than the power supply turn on
voltage is applied. There should be load sharing in the standby rail.
10.2.3 Voltage Regulation
The power supply output voltages must stay within the following voltage limits when operating at
steady state and dynamic loading conditions. These limits include the peak-peak ripple/noise.
These shall be measured at the output connectors.
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Intel®Server Boards S2400LP TPS
Table 81. Voltage Regulation Limits
Parameter
+12V
+5V stby
Tolerance
- 5%/+5%
- 5%/+5%
Min
+11.40
+4.75
Nom
+12.00
+5.00
Max
+12.60
+5.25
Units
Vrms
Vrms
10.2.4 Dynamic Loading
The output voltages shall remain within limits specified for the step loading and capacitive
loading specified in the table below. The load transient repetition rate shall be tested between
50Hz and 5kHz at duty cycles ranging from 10%-90%. The load transient repetition rate is only a
test specification. The  step load may occur anywhere within the MIN load to the MAX
load conditions.
Table 82. Transient Load Requirements
Output
+5VSB
+12V
 Step Load Size
1.0A
60% of max load
Load Slew Rate
0.25 A/sec
0.25 A/sec
Test capacitive Load
20 F
2000 F
Note: For dynamic condition +12V min loading is 1A.
10.2.5 Capacitive Loading
The power supply shall be stable and meet all requirements with the following capacitive
loading ranges.
Table 83. Capacitive Loading Conditions
Output
+5VSB
+12V
Min
20
500
Max
3100
25000
Units
F
F
10.2.6 Grounding
The output ground of the pins of the power supply provides the output power return path. The
output connector ground pins shall be connected to the safety ground (power supply enclosure).
This grounding should be well designed to ensure passing the max allowed Common Mode
Noise levels.
The power supply shall be provided with a reliable protective earth ground. All secondary
circuits shall be connected to protective earth ground. Resistance of the ground returns to
chassis shall not exceed 1.0 m. This path may be used to carry DC current.
10.2.7 Closed loop stability
The power supply shall be unconditionally stable under all line/load/transient load conditions
including specified capacitive load ranges. A minimum of 45 degrees phase margin and 10dBgain margin is required. Closed-loop stability must be ensured at the maximum and minimum
loads as applicable.
10.2.8 Residual Voltage Immunity in Standby mode
The power supply should be immune to any residual voltage placed on its outputs (Typically a
leakage voltage through the system from standby output) up to 500mV. There shall be no
additional heat generated, nor stressing of any internal components with this voltage applied to
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Power Supply Specification Guidelines
any individual or all outputs simultaneously. It also should not trip the protection circuits during
turn on.
The residual voltage at the power supply outputs for no load condition shall not exceed 100mV
when AC voltage is applied and the PSON# signal is de-asserted.
10.2.9
Common Mode Noise
The Common Mode noise on any output shall not exceed 350mV pk-pk over the frequency
band of 10Hz to 20MHz.
10.2.10
Soft Starting
The Power Supply shall contain control circuit which provides monotonic soft start for its outputs
without overstress of the AC line or any power supply components at any specified AC line or
load conditions.
10.2.11
Zero Load Stability Requirements
When the power subsystem operates in a no load condition, it does not need to meet the output
regulation specification, but it must operate without any tripping of over-voltage or other fault
circuitry. When the power subsystem is subsequently loaded, it must begin to regulate and
source current without fault.
10.2.12
Hot Swap Requirements
Hot swapping a power supply is the process of inserting and extracting a power supply from an
operating power system. During this process the output voltages shall remain within the limits
with the capacitive load specified. The hot swap test must be conducted when the system is
operating under static, dynamic, and zero loading conditions.
10.2.13
Forced Load Sharing
The +12V output will have active load sharing. The output will share within 10% at full load. The
failure of a power supply should not affect the load sharing or output voltages of the other
supplies still operating. The supplies must be able to load share in parallel and operate in a hotswap/redundant 1+1 configurations. The 12VSBoutput is not required to actively share current
between power supplies (passive sharing). The 12VSBoutput of the power supplies are
connected together in the system so that a failure or hot swap of a redundant power supply
does not cause these outputs to go out of regulation in the system.
10.2.14
Ripple/Noise
The maximum allowed ripple/noise output of the power supply is defined in the following table.
This is measured over a bandwidth of 10Hz to 20MHz at the power supply output connectors. A
10F tantalum capacitor in parallel with a 0.1F ceramic capacitor is placed at the point
of measurement.
Table 84. Ripples and Noise
+12V main
120mVp-p
10.2.15
+5VSB
50mVp-p
Timing Reuqirement
These are the timing requirements for the power supply operation. The output voltages must rise
from 10% to within regulation limits (Tvout_rise) within 5 to 70ms. For 5VSB, it is allowed to rise
from 1.0 to 25ms. All outputs must rise monotonically. The following table shows the timing
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Intel®Server Boards S2400LP TPS
requirements for the power supply being turned on and off through the AC input, with PSON
held low and the PSON signal, with the AC input applied.
Table 85. Timing Requirements
Item
Tvout_rise
Tsb_on_delay
Tac_on_delay
Tvout_holdup
Tpwok_holdup
Tpson_on_delay
Tpson_pwok
Tpwok_on
Tpwok_off
Tpwok_low
Tsb_vout
T5VSB_holdup
Description
Output voltage rise time
Delay from AC being applied to 5VSB being within
regulation.
Delay from AC being applied to all output voltages
being within regulation.
Time 12Vl output voltage stay within regulation
after loss of AC.
Delay from loss of AC to de-assertion of PWOK
Delay from PSON# active to output voltages
within regulation limits.
Delay from PSON# deactivate to PWOK being deasserted.
Delay from output voltages within regulation limits
to PWOK asserted at turn on.
Delay from PWOK de-asserted to output voltages
dropping out of regulation limits.
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
Delay from 5VSB being in regulation to O/Ps
being in regulation at AC turn on.
Time the 5VSB output voltage stays within
regulation after loss of AC.
Min
5.0 *
Max
70 *
1500
Units
ms
ms
3000
ms
13
12
5
100
ms
400
ms
ms
5
ms
500
ms
1
ms
100
ms
50
70
1000
ms
ms
* The 5VSB output voltage rise time shall be from 1.0ms to 25ms.
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AC Input
Tvout_holdup
Vout
Tpwok_low
TAC_on_delay
Tsb_on_delay
PWOK
12Vsb
Tpwok_off
Tpwok_on
Tsb_on_delay
Tpwok_on
Tpwok_holdup
Tsb_vout
Tpwok_off
Tpson_pwok
T5Vsb_holdup
Tpson_on_delay
PSON
AC turn on/off cycle
PSON turn on/off cycle
Figure 47. Turn On/Off Timing (Power Supply Signals)
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Appendix A: Integration and Usage Tips
Intel®Server Boards S2400LP TPS
Appendix A: Integration and Usage Tips

When adding or removing components or peripherals from the server board, AC power
must be removed. With AC power plugged into the server board, 5-V standby is still
present even though the server board is powered off.

This server board supports the Intel® Xeon® Processor E5-2400 product family or Intel®
Xeon® Processor E5-2400 v2 product family with a Thermal Design Power (TDP) of up
to and including 95 Watts. Previous generations of the Intel® Xeon® processors are not
supported.

Processors must be installed in order. CPU 1 must be populated for the server board
to operate.

The server board includes a pre-installed CPU power cable harness. The cable harness
must be installed and fully seated in each connector for the server board to operate.

On the back edge of the server board are eight diagnostic LEDs that display a sequence
of amber POST codes during the boot process. If the server board hangs during POST,
the LEDs display the last POST event run before the hang.

This server board only supports registered DDR3 DIMMs (RDIMMs) and unbuffered
DDR3 DIMMs (UDIMMs). Mixing of RDIMMs and UDIMMs is not supported.

For the best performance, the number of DDR3 DIMMs installed should be balanced
across both processor sockets and memory channels. For example, a two-DIMM
configuration performs better than a one-DIMM configuration. In a two-DIMM
configuration, DIMMs should be installed in DIMM sockets A1 and D1. A six-DIMM
configuration (DIMM sockets A1, B1, C1, D1, E1, and F1) performs better than a threeDIMM configuration (DIMM sockets A1, B1, and C1).

The Intel® Remote Management Module 4 (Intel® RMM4) connector is not compatible
with any previous versions of the Intel® Remote Management Module (Product Order
Code – AXXRMM, AXXRMM2, AXXRMM3).
Clear the CMOS with AC power cord plugged. Removing the AC power before
performing the CMOS clear operation causes the system to automatically power up and
immediately power down after the CMOS clear procedure is followed and AC power is
re-applied. If this happens, remove the AC power cord, wait 30 seconds, and then reconnect the AC power cord. Power up the system and proceed to the <F2> BIOS Setup
utility to reset the desired settings.



146
Normal BMC functionality is disabled with the BMC Force Update jumper set to the
“enabled” position (pins 2-3). The server should never be run with the BMC Force
Update jumper set in this position and should only be used when the standard firmware
update process fails. This jumper should remain in the default (disabled) position (pins 12) when the server is running normally.
When performing a normal BIOS update procedure, the BIOS recovery jumper must be
set to its default position (pins 1-2).
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix B: Integrated BMC Sensor Tables
Appendix B: Integrated BMC Sensor Tables
This appendix lists the sensor identification numbers and information about the sensor type,
name, supported thresholds, assertion and de-assertion information, and a brief description of
the sensor purpose. See the Intelligent Platform Management Interface Specification, Version
2.0, for sensor and event/reading-type table information.

Sensor Type
The Sensor Type values are the values enumerated in the Sensor Type Codes table in
the IPMI specification. The Sensor Type provides the context in which to interpret the
sensor, such as the physical entity or characteristic that is represented by this sensor.

Event/Reading Type

The Event/Reading Type values are from the Event/Reading Type Code Ranges and
Generic Event/Reading Type Codes tables in the IPMI specification. Digital sensors are
a specific type of discrete sensor, which have only two states.
Event Offset/Triggers
Event Thresholds are event-generating thresholds for threshold types of sensors.
- [u,l][nr,c,nc]: upper non-recoverable, upper critical, upper non-critical, lower nonrecoverable, lower critical, lower non-critical
- uc, lc: upper critical, lower critical
Event Triggers are supported event-generating offsets for discrete type sensors. The
offsets can be found in the Generic Event/Reading Type Codes or Sensor Type Codes
tables in the IPMI specification, depending on whether the sensor event/reading type is
generic or a sensor-specific response.

Assertion/De-assertion Enables
Assertion and de-assertion indicators reveal the type of events the sensor generates:

- As: Assertions
- De: De-assertion
Readable Value/Offsets
Readable Value indicates the type of value returned for threshold and other nondiscrete type sensors.
- Readable Offsets indicate the offsets for discrete sensors that are readable with the
Get Sensor Reading command. Unless otherwise indicated, all event triggers are
readable; Readable Offsets consist of the reading type offsets that do not
generate events.
Event Data
-

Event data is the data that is included in an event message generated by the sensor. For
threshold-based sensors, the following abbreviations are used:
-
Revision 2.0
R: Reading value
T: Threshold value
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Appendix B: Integrated BMC Sensor Tables

Intel®Server Boards S2400LP TPS
Rearm Sensors
The rearm is a request for the event status for a sensor to be rechecked and updated
upon a transition between good and bad states. Rearming the sensors can be done
manually or automatically. This column indicates the type supported by the sensor. The
following abbreviations are used to describe a sensor:

- A: Auto-rearm
- M: Manual rearm
Default Hysteresis

The hysteresis setting applies to all thresholds of the sensor. This column provides the
count of hysteresis for the sensor, which can be 1 or 2 (positive or negative hysteresis).
Criticality

Criticality is a classification of the severity and nature of the condition. It also controls the
behavior of the Control Panel Status LED.
Standby
Some sensors operate on standby power. These sensors may be accessed and/or
generate events when the main (system) power is off, but AC power is present.
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Appendix B: Integrated BMC Sensor Tables
Table 86. BMC Sensor Table
Full Sensor Name
(Sensor name in SDR)
Power Unit Status
(Pwr Unit Status)
Power Unit
RedundancyNote1 (Pwr
Unit Redund)
IPMI Watchdog
(IPMI Watchdog)
Revision 2.0
Sensor #
01h
02h
03h
Platform
Applicability
All
Chassisspecific
All
Sensor Type
Power Unit
09h
Power Unit
09h
Watchdog 2
23h
Event/
Reading Type
Sensor
Specific
6Fh
Generic
0Bh
Sensor
Specific
6Fh
Event Offset Triggers
Contrib. To
System Status
00 - Power down
OK
02 - 240 VA power
down
04 - A/C lost
05 - Soft power
control failure
Fatal
OK
OK
01 - Redundancy lost
Degraded
02 - Redundancy
degraded
Degraded
03 - Non-redundant:
sufficient resources.
Transition from full
redundant state.
04 – Non-redundant:
sufficient resources.
Transition from
insufficient state.
05 - Non-redundant:
insufficient resources
Degraded
06 – Redundant:
degraded from fully
redundant state.
07 – Redundant:
Transition from nonredundant state.
Degraded
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Readable
Value/Off
sets
Event
Data
Rearm
Standby
As
and
De
–
Trig Offset
A
X
As
and
De
–
Trig Offset
M
X
As
–
Trig Offset
A
X
Fatal
06 - Power unit failure
00 - Fully Redundant
00 - Timer expired,
status only
01 - Hard reset
Assert/
Deassert
Degraded
Fatal
Degraded
OK
149
Appendix B: Integrated BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
Intel®Server Boards S2400LP TPS
Sensor Type
Event/
Reading Type
Event Offset Triggers
Contrib. To
System Status
Assert/
Deassert
Readable
Value/Off
sets
Event
Data
Rearm
Standby
OK
As
and
De
–
Trig Offset
A
X
OK
As
–
Trig Offset
A
–
Fatal
As
and
De
–
Trig Offset
A
–
OK
As
–
Trig Offset
A
X
Fatal
OK
As
and
De
As
-
Trig Offset
A
X
02 - Power down
03 - Power cycle
08 - Timer interrupt
00 - Chassis intrusion
04h
Chassis
Intrusion is
chassisspecific
Physical
Security
05h
Sensor
Specific
6Fh
FP Interrupt
(FP NMI Diag Int)
05h
Chassis specific
Critical
Interrupt
13h
SMI Timeout
(SMI Timeout)
All
SMI Timeout
F3h
00 - Front panel
NMI/diagnostic
interrupt
01 – State asserted
06h
System Event Log
(System Event Log)
07h
All
Event Logging
Disabled
10h
Sensor
Specific
6Fh
Digital
Discrete
03h
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Digital
Discrete
03h
Digital
Discrete
03h
00 – Power Button
02 – Reset Button
OK
AS
_
Trig Offset
A
X
01 – State Asserted
Degraded
As
–
Trig Offset
A
-
01 – State Asserted
Fatal
As
and
De
–
Trig Offset
M
X
00 - Fully redundant
01 - Redundancy lost
02 - Redundancy
degraded
03 - Non-redundant:
Sufficient resources.
Transition from
redundant
OK
Degraded
As
and
De
–
Trig Offset
A
–
Physical Security
(Physical Scrty)
System Event
12h
System Event
(System Event)
08h
All
Button Sensor
(Button)
09h
All
Button/Switch
14h
BMC Watchdog
0Ah
All
Mgmt System
Health
28h
Voltage Regulator
Watchdog
(VR Watchdog)
0Bh
All
Voltage
02h
Fan RedundancyNote1
(Fan Redundancy)
150
0Ch
Chassisspecific
Fan
04h
Generic
0Bh
04 - LAN leash lost
02 - Log area
reset/cleared
02 - Undetermined
system H/W failure
04 – PEF action
Intel order number G52803-002
Degraded
Degraded
Revision 2.0
Intel®Server Boards S2400LP TPS
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
Appendix B: Integrated BMC Sensor Tables
Sensor Type
Event/
Reading Type
Event Offset Triggers
04 - Non-redundant:
Sufficient resources.
Transition from
insufficient.
05 - Non-redundant:
insufficient resources.
06 – Non-Redundant:
degraded from fully
redundant.
07 - Redundant
degraded from nonredundant
Digital
Discrete
03h
Digital
Discrete
08h
Digital
Discrete
08h
Sensor
Specific
6Fh
Threshold
01h
OEM
defined(0x7
0)
SSB Thermal Trip
(SSB Therm Trip)
0Dh
All
Temperature
01h
IO Module Presence
(IO Mod Presence)
0Eh
Platformspecific
Module/Board
15h
SAS Module Presence
(SAS Mod Presence)
0Fh
Platformspecific
Module/Board
15h
BMC Firmware Health
(BMC FW Health)
10h
All
Mgmt Health
28h
11h
All
0x12
All
Baseboard Temperature 1
(Platform Specific)
20h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Front Panel Temperature
(Front Panel Temp)
21h
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
System Airflow
(System Airflow)
FW Update Status
Revision 2.0
Other Units
0Bh
Version
Change(0x2B)
Contrib. To
System Status
Assert/
Deassert
Readable
Value/Off
sets
Event
Data
Rearm
Standby
–
Trig Offset
M
X
–
Trig Offset
M
X
–
Trig Offset
M
X
As
-
Trig Offset
A
X
Degraded
Non-Fatal
Degraded
Degraded
As
and
De
As
and
De
As
and
De
01 – State Asserted
Fatal
01 – Inserted/Present
OK
01 – Inserted/Present
OK
04 – Sensor Failure
Degraded
–
–
–
Analog
–
–
–
0x00hUpdate
started
0x01hUpdate
completed
successfully.
0x02Update failure
OK
As
_
Trig Offset
A
_
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
As
and
De
As
and
De
Analog
R, T
A
X
Analog
R, T
A
X
Intel order number G52803-002
151
Appendix B: Integrated BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Sensor #
Platform
Applicability
SSB Temperature
(SSB Temp)
22h
Baseboard Temperature 2
(Platform Specific)
Intel®Server Boards S2400LP TPS
Sensor Type
Event/
Reading Type
All
Temperature
01h
Threshold
01h
[u,l] [c,nc]
23h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Baseboard Temperature 3
(Platform Specific)
24h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Baseboard Temperature 4
(Platform Specific)
25h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
IO Module Temperature
(I/O Mod Temp)
26h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
PCI Riser 1 Temperature
(PCI Riser 1 Temp)
27h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
IO Riser Temperature
(IO Riser Temp)
28h
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
29h
Chassisspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
2Ah
Chassisspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
2Bh
Chassisspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
PCI Riser 2 Temperature
(PCI Riser 2 Temp)
2Ch
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
SAS Module Temperature
(SAS Mod Temp)
2Dh
Platformspecific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
2Eh
Chassis
and
Platform
Specific
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Hot-swap Backplane 1
Temperature
(HSBP 1 Temp)
Hot-swap Backplane 2
Temperature
(HSBP 2 Temp)
Hot-swap Backplane 3
Temperature
(HSBP 3 Temp)
Exit Air Temperature
(Exit Air Temp)
152
Event Offset Triggers
Intel order number G52803-002
Contrib. To
System Status
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
Assert/
Deassert
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
nc =
Degraded
c = Non-fatal
As
and
De
Readable
Value/Off
sets
Event
Data
Rearm
Standby
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Analog
R, T
A
X
Revision 2.0
Intel®Server Boards S2400LP TPS
Full Sensor Name
(Sensor name in SDR)
Network Interface
Controller Temperature
(LAN NIC Temp)
Sensor #
Platform
Applicability
2Fh
All
Fan Tachometer Sensors
(Chassis specific
sensor names)
30h–3Fh
Fan Present Sensors
(Fan x Present)
40h–4Fh
Power Supply 1 Status
(PS1 Status)
Power Supply 2 Status
(PS2 Status)
Power Supply 1
AC Power Input
(PS1 Power In)
Power Supply 2
AC Power Input
(PS2 Power In)
Power Supply 1 +12V %
of Maximum Current
Output
(PS1 Curr Out %)
Power Supply 2 +12V %
of Maximum Current
Output
(PS2 Curr Out %)
Power Supply 1
Temperature
(PS1 Temperature)
Revision 2.0
50h
51h
Chassis
and
Platform
Specific
Chassis
and
Platform
Specific
Chassisspecific
Chassisspecific
Appendix B: Integrated BMC Sensor Tables
Sensor Type
Event/
Reading Type
Temperature
01h
Threshold
01h
[u,l] [c,nc]
Fan
04h
Threshold
01h
[l] [c,nc]
Fan
04h
Generic
08h
01 - Device inserted
OK
00 - Presence
01 - Failure
02 – Predictive Failure
03 - A/C lost
06 – Configuration
error
00 - Presence
01 - Failure
02 – Predictive Failure
03 - A/C lost
06 – Configuration
error
OK
Degraded
Degraded
Degraded
Power Supply
08h
Power Supply
08h
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Event Offset Triggers
Contrib. To
System Status
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = NonfatalNote2
Assert/
Deassert
As
and
De
Readable
Value/Off
sets
Event
Data
Rearm
Standby
Analog
R, T
A
X
As
and
De
Analog
R, T
M
-
As
and
De
-
Triggered
Offset
Auto
-
As
and
De
–
Trig Offset
A
X
As
and
De
–
Trig Offset
A
X
Analog
R, T
A
X
Analog
R, T
A
X
OK
OK
Degraded
Degraded
Degraded
OK
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
As
and
De
As
and
De
[u] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
X
Threshold
01h
[u] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
X
Threshold
01h
[u] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
X
54h
Chassisspecific
Other Units
0Bh
Threshold
01h
[u] [c,nc]
55h
Chassisspecific
Other Units
0Bh
Threshold
01h
[u] [c,nc]
58h
Chassisspecific
Current
03h
Threshold
01h
59h
Chassisspecific
Current
03h
5Ch
Chassisspecific
Temperature
01h
Intel order number G52803-002
153
Appendix B: Integrated BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Power Supply 2
Temperature
(PS2 Temperature)
Hard Disk Drive 16 - 24
Status
(HDD 16 - 24 Status)
Sensor #
5Dh
60h
–
68h
Platform
Applicability
Chassisspecific
Chassisspecific
Intel®Server Boards S2400LP TPS
Sensor Type
Temperature
Drive Slot
0Dh
HSC Status
69h
6Bh
Chassisspecific
Microcontrolle
r 16h
Processor 1 Status
(P1 Status)
70h
All
Processor
07h
Processor 2 Status
(P2 Status)
71h
All
Processor
07h
74h
All
Temperature
01h
75h
All
78h
Processor 1 Thermal
Margin
(P1 Therm Margin)
Processor 2 Thermal
Margin
(P2 Therm Margin)
Processor 1 Thermal
Control %
(P1 Therm Ctrl %)
Processor 2 Thermal
Control %
(P2 Therm Ctrl %)
Processor 1 ERR2
Timeout
(P1 ERR2)
Processor 2 ERR2
Timeout
(P2 ERR2)
154
Event/
Reading Type
Threshold
01h
Sensor
Specific
6Fh
Discrete
0Ah
Event Offset Triggers
Contrib. To
System Status
[u] [c,nc]
nc =
Degraded
c = Non-fatal
00 - Drive Presence
OK
01- Drive Fault
Degraded
07 - Rebuild/Remap in
progress
Assert/
Deassert
As
and
De
As
and
De
Readable
Value/Off
sets
Event
Data
Rearm
Standby
Analog
R, T
A
X
–
Trig Offset
A
X
–
Trig Offset
A
X
–
Trig Offset
M
X
–
Trig Offset
M
X
Degraded
As
and
De
As
and
De
As
and
De
04- transition to Off
Line
Degraded
01 - Thermal trip
Fatal
07 - Presence
01 - Thermal trip
OK
Fatal
07 - Presence
OK
Threshold
01h
-
-
-
Analog
R, T
A
–
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
All
Temperature
01h
Threshold
01h
[u] [c,nc]
Trig Offset
A
–
All
Temperature
01h
Threshold
01h
[u] [c,nc]
Analog
Trig Offset
A
–
7Ch
All
Processor
07h
–
Trig Offset
A
–
7Dh
All
Processor
07h
As
and
De
As
and
De
As
and
De
As
and
De
Analog
79h
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
–
Trig Offset
A
–
Sensor
Specific
6Fh
Sensor
Specific
6Fh
Digital
Discrete
03h
Digital
Discrete
03h
01 – State Asserted
fatal
01 – State Asserted
fatal
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Full Sensor Name
(Sensor name in SDR)
Catastrophic Error
(CATERR)
Processor1 MSID
Mismatch
(P1 MSID Mismatch)
Processor Population
Fault
(CPU Missing)
Processor 1 DTS Thermal
Margin
(P1 DTS Therm Mgn)
Processor 2 DTS Thermal
Margin
(P2 DTS Therm Mgn)
Processor2 MSID
Mismatch
(P2 MSID Mismatch)
Processor 1 VRD
Temperature
(P1 VRD Hot)
Processor 2 VRD
Temperature
(P2 VRD Hot)
Processor 1 Memory VRD
Hot 0-1
(P1 Mem01 VRD Hot)
Processor 1 Memory VRD
Hot 2-3
(P1 Mem23 VRD Hot)
Processor 2 Memory VRD
Hot 0-1
(P2 Mem01 VRD Hot)
Processor 2 Memory VRD
Hot 2-3
(P2 Mem23 VRD Hot)
Power Supply 1 Fan
Tachometer 1
(PS1 Fan Tach 1)
Revision 2.0
Appendix B: Integrated BMC Sensor Tables
Sensor #
Platform
Applicability
Sensor Type
80h
All
Processor
07h
81h
All
Processor
07h
82h
All
Processor
07h
83h
All
Temperature
01h
83h
All
Temperature
01h
87h
All
Processor
07h
90h
All
Temperature
01h
91h
All
Temperature
01h
94h
All
Temperature
01h
95h
All
Temperature
01h
96h
All
Temperature
01h
97h
All
Temperature
01h
A0h
Chassisspecific
Fan
04h
Event/
Reading Type
Event Offset Triggers
Contrib. To
System Status
01 – State Asserted
fatal
01 – State Asserted
fatal
01 – State Asserted
Fatal
Threshold
01h
-
Threshold
01h
Digital
Discrete
03h
Digital
Discrete
03h
Digital
Discrete
03h
Digital
Discrete
03h
Digital
Discrete
05h
Digital
Discrete
05h
Digital
Discrete
05h
Digital
Discrete
05h
Digital
Discrete
05h
Digital
Discrete
05h
Generic –
digital
discrete
Assert/
Deassert
As
and
De
As
and
De
As
and
De
Readable
Value/Off
sets
Event
Data
Rearm
Standby
–
Trig Offset
M
–
–
Trig Offset
M
–
–
Trig Offset
M
–
-
-
Analog
R, T
A
–
-
-
-
Analog
R, T
A
–
01 – State Asserted
fatal
–
Trig Offset
M
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
M
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
M
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
A
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
A
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
A
–
01 - Limit exceeded
Non-fatal
–
Trig Offset
A
–
01 – State Asserted
Non-fatal
-
Trig Offset
M
-
Intel order number G52803-002
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
155
Appendix B: Integrated BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Power Supply 1 Fan
Tachometer 2
(PS1 Fan Tach 2)
Power Supply 2 Fan
Tachometer 1
(PS2 Fan Tach 1)
Power Supply 2 Fan
Tachometer 2
(PS2 Fan Tach 2)
Processor 1 DIMM
Aggregate Thermal Margin
1
(P1 DIMM Thrm Mrgn1)
Processor 1 DIMM
Aggregate Thermal Margin
2
(P1 DIMM Thrm Mrgn2)
Processor 2 DIMM
Aggregate Thermal Margin
1
(P2 DIMM Thrm Mrgn1)
Processor 2 DIMM
Aggregate Thermal Margin
2
(P2 DIMM Thrm Mrgn2)
Processor 1 DIMM
Thermal Trip
(P1 Mem Thrm Trip)
Processor 2 DIMM
Thermal Trip
(P2 Mem Thrm Trip)
Global Aggregate
Temperature Margin 1
(Agg Therm Mrgn 1)
Global Aggregate
Temperature Margin 2
(Agg Therm Mrgn 2)
Global Aggregate
Temperature Margin 3
(Agg Therm Mrgn 3)
156
Sensor #
Intel®Server Boards S2400LP TPS
Platform
Applicability
Sensor Type
A1h
Chassisspecific
Fan
04h
A4h
Chassisspecific
Fan
04h
A5h
Chassisspecific
Fan
04h
All
Temperature
01h
Threshold
01h
All
Temperature
01h
Threshold
01h
All
Temperature
01h
Threshold
01h
B3h
All
Temperature
01h
Threshold
01h
C0h
All
Temperature
01h
C1h
All
Temperature
01h
C8h
Platform
Specific
Temperature
01h
C9h
Platform
Specific
CAh
Platform
Specific
B0h
B1h
B2h
Event/
Reading Type
Generic –
digital
discrete
Generic –
digital
discrete
Generic –
digital
discrete
Digital
Discrete
03h
Digital
Discrete
03h
Event Offset Triggers
Contrib. To
System Status
01 – State Asserted
Non-fatal
01 – State Asserted
Non-fatal
01 – State Asserted
Non-fatal
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
Assert/
Deassert
As
and
De
As
and
De
As
and
De
Readable
Value/Off
sets
Event
Data
Rearm
Standby
-
Trig Offset
M
-
-
Trig Offset
M
-
-
Trig Offset
M
-
As
and
De
Analog
R, T
A
–
As
and
De
Analog
R, T
A
–
As
and
De
Analog
R, T
A
–
As
and
De
Analog
R, T
A
–
–
Trig Offset
M
-
–
Trig Offset
M
-
As
and
De
As
and
De
01 – State Asserted
Fatal
01 – State Asserted
Fatal
Threshold
01h
-
-
-
Analog
R, T
A
–
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Full Sensor Name
(Sensor name in SDR)
Event Offset Triggers
Contrib. To
System Status
Assert/
Deassert
Readable
Value/Off
sets
Event
Data
Rearm
Standby
Threshold
01h
-
-
-
Analog
R, T
A
–
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
Platform
Specific
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
CEh
Platform
Specific
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
CFh
Platform
Specific
Temperature
01h
Threshold
01h
-
-
-
Analog
R, T
A
–
Baseboard +12V
(BB +12.0V)
D0h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
Baseboard +5V
(BB +5.0V)
D1h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
Baseboard +3.3V
(BB +3.3V)
D2h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
R, T
A
–
D3h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Analog
R, T
A
X
Baseboard +3.3V Auxiliary
(BB +3.3V AUX)
D4h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Analog
R, T
A
X
D6h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Analog
R, T
A
–
D7h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Analog
R, T
A
–
D8h
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
Analog
Baseboard +5V Stand-by
(BB +5.0V STBY)
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
Analog
R, T
A
–
Global Aggregate
Temperature Margin 4
(Agg Therm Mrgn 4)
Global Aggregate
Temperature Margin 5
(Agg Therm Mrgn 5)
Global Aggregate
Temperature Margin 6
(Agg Therm Mrgn 6)
Global Aggregate
Temperature Margin 7
(Agg Therm Mrgn 7)
Global Aggregate
Temperature Margin 8
(Agg Therm Mrgn 8)
Baseboard +1.05V
Processor 1 Vccp
(BB +1.05Vccp P1)
Baseboard +1.05V
Processor 1 Vccp
(BB +1.05Vccp P2)
Baseboard +1.5V P1
Memory AB VDDQ
(BB +1.5 P1MEM AB)
Revision 2.0
Sensor #
Appendix B: Integrated BMC Sensor Tables
Platform
Applicability
Sensor Type
Event/
Reading Type
CBh
Platform
Specific
Temperature
01h
CCh
Platform
Specific
CDh
Intel order number G52803-002
157
Appendix B: Integrated BMC Sensor Tables
Full Sensor Name
(Sensor name in SDR)
Sensor Type
Event/
Reading Type
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
DAh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
DBh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Baseboard +1.8V Aux
(BB +1.8V AUX)
DCh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Baseboard +1.1V Standby
(BB +1.1V STBY)
DDh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
Baseboard CMOS Battery
(BB +3.3V Vbat)
DEh
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
E4h
All
Voltage
02h
Threshold
01h
E5h
All
Voltage
02h
E6h
All
E7h
Baseboard +1.5V P1
Memory CD VDDQ
(BB +1.5 P1MEM CD)
Baseboard +1.5V P2
Memory AB VDDQ
(BB +1.5 P2MEM AB)
Baseboard +1.5V P2
Memory CD VDDQ
(BB +1.5 P2MEM CD)
Baseboard +1.35V P1
Low Voltage Memory AB
VDDQ
(BB +1.35 P1LV AB)
Baseboard +1.35V P1
Low Voltage Memory CD
VDDQ
(BB +1.35 P1LV CD)
Baseboard +1.35V P2
Low Voltage Memory AB
VDDQ
(BB +1.35 P2LV AB)
Baseboard +1.35V P2
Low Voltage Memory CD
VDDQ
(BB +1.35 P2LV CD)
Baseboard +3.3V Riser 1
Power Good
(BB +3.3 RSR1 PGD)
Baseboard +3.3V Riser 2
Power Good
(BB +3.3 RSR2 PGD)
158
Sensor #
Platform
Applicability
D9h
Intel®Server Boards S2400LP TPS
Event Offset Triggers
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
Assert/
Deassert
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
As
and
De
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
All
Voltage
02h
Threshold
01h
[u,l] [c,nc]
nc =
Degraded
c = Non-fatal
As
and
De
Analog
R, T
A
–
EAh
Platform
Specific
Voltage
02h
Threshold
01h
[u,l] [c,nc]
R, T
A
–
Platform
Specific
Voltage
02h
Threshold
01h
[u,l] [c,nc]
As
and
De
As
and
De
Analog
EBh
nc =
Degraded
c = Non-fatal
nc =
Degraded
c = Non-fatal
Analog
R, T
A
–
Intel order number G52803-002
Contrib. To
System Status
Readable
Value/Off
sets
Event
Data
Rearm
Standby
Analog
R, T
A
–
Analog
R, T
A
–
Analog
R, T
A
–
Analog
R, T
A
–
Analog
R, T
A
–
Analog
R, T
A
–
Revision 2.0
Intel®Server Boards S2400LP TPS
Full Sensor Name
(Sensor name in SDR)
Hard Disk Drive 1 -15
Status
(HDD 1 - 15 Status)
Sensor #
F0h
FEh
Platform
Applicability
Chassisspecific
Appendix B: Integrated BMC Sensor Tables
Sensor Type
Drive Slot
0Dh
Event/
Reading Type
Sensor
Specific
6Fh
Event Offset Triggers
Contrib. To
System Status
00 - Drive Presence
01- Drive Fault
07 - Rebuild/Remap in
progress
OK
Degraded
Degraded
Assert/
Deassert
Readable
Value/Off
sets
Event
Data
Rearm
Standby
As
and
De
–
Trig Offset
A
X
Notes:
1. Redundancy sensors will be only present on systems with appropriate hardware to support redundancy (for instance, fan or power supply).
2. This is only applicable when the system doesn't support redundant fans. When fan redundancy is supported, then the contribution to system state is
driven by the fan redundancy sensor.
Revision 2.0
Intel order number G52803-002
159
Appendix C: BIOS Sensors and SEL Data
Intel®Server Boards S2400LP TPS
Appendix C: BIOS Sensors and SEL Data
BIOS owns a set of IPMI-compliant Sensors. These are actually divided in ownership between
BIOS POST (GID = 01) and BIOS SMI Handler (GID = 33). The SMI Handler Sensors are
typically for logging runtime error events, but they are active during POST and may log errors
such as Correctable Memory ECC Errors if they occur.
It is important to remember that a Sensor is uniquely identified by the combination of Sensor
Owner plus Sensor Number. There are cases where the same Sensor Number is used with
different Sensor Owners – this is not a conflict. For example, in the BIOS Sensors list there is a
Sensor Number 83h for Sensor Owner 01h (BIOS POST) as well as for Sensor Owner 33h (SMI
Handler), but these are two distinct sensors reporting the same type of event from different
sources (Generator IDs 01h and 33h).
On the other hand, each distinct Sensor (GID + Sensor Number) is defined by one specific
Sensor Type describing the kind of data being reported, and one specific Event Type describing
the type of event and the format of the data being reported.
Table 87. BIOS Sensor and SEL Data
Sensor Name
Mirroring
Redundancy State
Sensor
Number
01h
Sensor Owner
(GID)
33h (SMI
Handler)
Sensor Type
0Ch (Memory)
Event/Reading Type
Offset Values
0Bh (Discrete,
Redundancy State)
0h = Fully Redundant
2h = Redundancy
Degraded
Event Data 2
Event Data 3
ED2 =
[7:4] = Mirroring
Domain
0-1 = Channel
Pair for Socket
[3:2] = Reserved
[1:0] = Rank on
DIMM
0-3 = Rank
Number
ED3 =
[7:5]= Socket ID
0-3 = CPU1-4
[4:3] = Channel
0-3 = Channel
A-D for Socket
[2:0] = DIMM
0-2 = DIMM 1-3
on Channel
160
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Sensor Name
Memory RAS
Configuration
Status
Sensor
Number
02h
Appendix C: BIOS Sensors and SEL Data
Sensor Owner
(GID)
01h (BIOS
POST)
Sensor Type
0Ch (Memory)
Event/Reading Type
Offset Values
09h (Digital Discrete)
0h = RAS
Configuration Disabled
1h = RAS
Configuration Enabled
Event Data 2
Event Data 3
ED2 =
[7:4] = Reserved
[3:0] Config Err
0 = None
3 = Invalid
DIMM Config for
RAS Mode
ED3 =
[7:4] = Reserved
[3:0] = RAS
Mode
0 = None
1 = Mirroring
2 = Lockstep
4 = Rank
Sparing
Memory ECC
Error
02h
33h (SMI
Handler)
0Ch (Memory)
6Fh (Sensor Specific
Offset)
0h = Correctable Error
1h = Uncorrectable
Error
ED2 =
[7:2] = Reserved
[1:0] = Rank on
DIMM
0-3 = Rank
Number
ED3 =
[7:5]= Socket ID
0-3 = CPU1-4
[4:3] = Channel
0-3 = Channel
A-D for Socket
[2:0] = DIMM
0-2 = DIMM 1-3
on Channel
Legacy PCI Error
03h
33h (SMI
Handler)
13h (Critical
Interrupt)
6Fh (Sensor Specific
Offset)
4h = PCI PERR
5h = PCI SERR
Revision 2.0
Intel order number G52803-002
ED2 =
[7:0] = Bus
Number
ED3 =
[7:3] = Device
Number
[2:0] = Function
Number
161
Appendix C: BIOS Sensors and SEL Data
Sensor Name
PCIe Fatal Error
(Standard AER
Errors)
(see Sensor 14h
for continuation)
Sensor
Number
04h
PCIe Correctable
Error
(Standard AER
Errors)
05h
BIOS POST Error
06h
QPI Correctable
Errors
(reserved for
Validation)
06h
OPI Fatal Error
07h
162
Intel®Server Boards S2400LP TPS
Sensor Owner
(GID)
33h (SMI
Handler)
33h (SMI
Handler)
01h (BIOS
POST)
Sensor Type
13h (Critical
Interrupt)
13h (Critical
Interrupt)
0Fh (System
Firmware
Progress)
Event/Reading Type
Offset Values
70h (OEM Discrete)
0h = Data Link Layer
Protocol Error
1h = Surprise Link
Down Error
2h = Completer Abort
3h = Unsupported
Request
4h = Poisoned TLP
5h = Flow Control
Protocol
6h = Completion
Timeout
7h = Receiver Buffer
Overflow
8h = ACS Violation
9h = Malformed TLP
Ah = ECRC Error
Bh = Received Fatal
Message From
Downstream
Ch = Unexpected
Completion
Dh = Received
ERR_NONFATAL
Message
Eh = Uncorrectable
Internal
Fh = MC Blocked TLP
71h (OEM Discrete)
0h = Receiver Error
1h = Bad DLLP
2h = Bad TLP
3h = Replay Num
Rollover
4h = Replay Timer
timeout
5h = Advisory Non-fatal
6h = Link BW Changed
7h = Correctable
Internal
8h = Header Log
Overflow
6Fh (Sensor Specific
Offset)
0h = System Firmware
Error (POST Error
Code)
Event Data 2
Event Data 3
ED2 =
[7:0] = Bus
Number
ED3 =
[7:3] = Device
Number
[2:0] = Function
Number
ED2 =
[7:0] = Bus
Number
ED3 =
[7:3] = Device
Number
[2:0] = Function
Number
ED2 =
[7:0] = LSB of
POST Error
Code
ED3 =
[7:0] MSB of
POST Error
Code
33h (SMI
Handler)
13h (Critical
Interrupt)
72h (OEM Discrete)
ED2 = Reserved
Offset Reserved
ED3 = Reserved
33h (SMI
13h (Critical
73h (OEM Discrete)
ED2 =
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Sensor Name
Sensor
Number
(see Sensor 17h
for continuation)
Chipset
Proprietary
(reserved for
Validation)
08h
QPI Link Width
Reduced
09h
Memory Error
Extension
(reserved for
Validation)
Revision 2.0
10h
Appendix C: BIOS Sensors and SEL Data
Sensor Owner
(GID)
Handler)
Sensor Type
Interrupt)
33h (SMI
Handler)
19h (Chipset)
01h (BIOS
POST)
13h (Critical
Interrupt)
33h (SMI
Handler)
0Ch (Memory)
Event/Reading Type
Offset Values
0h = Link Layer
Uncorrectable ECC
Error
1h = Protocol Layer
Poisoned Packet
Reception Error
2h = Link/PHY Init
Failure with resultant
degradation in link
width
3h = CSI PHY Layer
detected drift buffer
alarm
4h = CSI PHY detected
latency buffer rollover
5h = CSI PHY Init
Failure
6h = CSI Link Layer
generic control error
(buffer
overflow/underflow,
credit underflow and
so on.)
7h = Parity error in link
or PHY layer
8h = Protocol layer
timeout detected
9h = Protocol layer
failed response
Ah = Protocol layer
illegal packet field,
target Node ID and so
on.
Bh = Protocol Layer
Queue/table
overflow/underflow
Ch = Viral Error
Dh = Protocol Layer
parity error
Eh = Routing Table
Error
Fh = (unused)
Event Data 2
Event Data 3
[7:0] = Node ID
0-3 = CPU1-4
75h (OEM Discrete)
ED2 = Reserved
Offset Reserved
ED3 = Reserved
77h (OEM Discrete)
ED2 =
[7:0] = Node ID
0-3 = CPU1-4
1h = Reduced to ½
width
2h = Reduced to ¼
width
ED3 = No Data
ED3 = No Data
7Fh (OEM Discrete)
ED2 = Reserved
Offset Reserved
ED3 = Reserved
Intel order number G52803-002
163
Appendix C: BIOS Sensors and SEL Data
Sensor Name
Sparing
Redundancy State
Sensor
Number
11h
Intel®Server Boards S2400LP TPS
Sensor Owner
(GID)
33h (SMI
Handler)
Sensor Type
0Ch (Memory)
Event/Reading Type
Offset Values
0Bh (Discrete,
Redundancy State)
0h = Fully Redundant
2h = Redundancy
Degraded
Event Data 2
Event Data 3
ED2 =
[7:4] = Sparing
Domain
0-3 = Channel
A-D for Socket
[3:2] = Reserved
[1:0] = Rank on
DIMM
0-3 = Rank
Number
ED3 =
[7:5]= Socket ID
0-3 = CPU1-4
[4:3] = Channel
0-3 = Channel
A-D for Socket
[2:0] = DIMM
0-2 = DIMM 1-3
on Channel
Memory RAS
Mode Select
12h
01h (BIOS
POST)
0Ch (Memory)
09h (Digital Discrete)
0h = RAS
Configuration Disabled
1h = RAS
Configuration Enabled
ED2 = Prior
Mode
[7:4] = Reserved
[3:0] = RAS
Mode
0 = None
1 = Mirroring
2 = Lockstep
4 = Rank
Sparing
ED3 = Selected
Mode
[7:4] = Reserved
[3:0] = RAS
Mode
0 = None
1 = Mirroring
2 = Lockstep
4 = Rank
Sparing
164
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Sensor Name
Memory Parity
Error
Sensor
Number
13h
Appendix C: BIOS Sensors and SEL Data
Sensor Owner
(GID)
33h (SMI
Handler)
Sensor Type
0Ch (Memory)
Event/Reading Type
Offset Values
6Fh (Sensor Specific
Offset)
2h = Address Parity
Error
Event Data 2
Event Data 3
ED2 = Validity
[7:5] = Reserved
[4] = Channel
Validity Check
0 = ED3 Chan #
Not Valid
1 = ED3 Chan #
Is Valid
[3] = DIMM
Validity Check
0 = ED3 DIMM
# Not Valid
1 = ED3 DIMM
# Is Valid
[2:0] = Error
Type
0 = Not Known
2 = Address
Parity Error
ED3 = Location
[7:5]= Socket ID
0-3 = CPU1-4
[4:2] = Channel
0-3 = Channel
A-D for Socket
[1:0] = DIMM
0-2 = DIMM 1-3
on Channel
PCIe Fatal Error#2
(Standard AER
Errors)
(continuation of
Sensor 04h)
14h
OPI Fatal Error
(continuation of
Sensor 07h)
17h
Revision 2.0
33h (SMI
Handler)
33h (SMI
Handler)
13h (Critical
Interrupt)
13h (Critical
Interrupt)
76h (OEM Discrete)
0h = Atomic Egress
Blocked
1h = TLP Prefix
Blocked
Fh = Unspecified NonAER Fatal Error
74h (OEM Discrete)
0h = Illegal inbound
request
1h = PCH Write Cache
Uncorrectable Data
ECC Error
2h = PCH Write Cache
Uncorrectable Data
ECC Error
3h = PCH Write Cache
Uncorrectable Data
ECC Error
4h = PCH Received
XPF physical/logical
redirect interrupt
inbound
5h = PCH Illegal SAD
or Illegal or nonexistent address or
memory
6h = PCH Write Cache
Coherency Violation
Intel order number G52803-002
ED2 =
[7:0] = Bus
Number
ED3 =
[7:3] = Device
Number
[2:0] = Function
Number
ED2 =
[7:0] = Node ID
0-3 = CPU1-4
ED3 = No Data
165
Appendix C: BIOS Sensors and SEL Data
Sensor Name
System Event
Sensor
Number
83h
Intel®Server Boards S2400LP TPS
Sensor Owner
(GID)
01h (BIOS
POST)
Sensor Type
12h (System
Event))
Event/Reading Type
Offset Values
6Fh (Sensor Specific
Offset)
1h = System Boot
Event
5h = Time Synch
(PCSD)
System Event
83h
33h (SMI
Handler)
12h (System
Event))
6Fh (Sensor Specific
Offset)
5h = Time Synch
(PCSD)
Event Data 2
Event Data 3
ED2 = (only for
Time Synch)
[7:0] Synch #
st
00h = 1 in pair
nd
80h = 2 in pair
ED3 = No Data
ED2 = (only for
Time Synch)
[7:0] Synch #
st
00h = 1 in pair
nd
80h = 2 in pair
ED3 = No Data
166
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix D: POST Code LED Decoder
Appendix D: POST Code LED Decoder
During the system boot process, the BIOS executes several platform configuration processes,
each of which is assigned a specific hex POST code number. As each configuration routine is
started, the BIOS displays the POST code on the POST code diagnostic LEDs found on the
back edge of the server board. To assist in troubleshooting a system hang during the POST
process, the diagnostic LEDs can be used to identify the last POST process to be executed.
Each POST code is represented by the eight amber diagnostic LEDs. The POST codes are
divided into two nibbles, an upper nibble and a lower nibble. The upper nibble bits are
represented by diagnostic LEDs #4, #5, #6, and #7. The lower nibble bits are represented by
diagnostics LEDs #0, #1, #2, and #3. If the bit is set in the upper and lower nibbles, then the
corresponding LED is lit. If the bit is clear, then the corresponding LED is off.
The diagnostic LED #7 is labeled as “MSB” (Most Significant Bit), and the diagnostic LED #0 is
labeled as “LSB” (Least Significant Bit).
Figure 48. Diagnostic LED Placement Diagram
Revision 2.0
Intel order number G52803-002
167
Appendix D: POST Code LED Decoder
Intel®Server Boards S2400LP TPS
In the following example, the BIOS sends a value of ACh to the diagnostic LED decoder. The
LEDs are decoded as follows:
Table 88. POST Progress Code LED Example
Upper Nibble LEDs
LEDs
Status
Results
MSB
LED #7
8h
ON
1
Ah
LED #6
4h
OFF
0
LED #5
2h
ON
1
Lower Nibble LEDs
LED #4
1h
OFF
0
LED #3
8h
ON
1
Ch
LED #2
4h
ON
1
LED #1
2h
OFF
0
LSB
LED #0
1h
OFF
0
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two are concatenated as
ACh.
168
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix D: POST Code LED Decoder
Table 89. Diagnostic LED POST Code Decoder
Diagnostic LED Decoder
1 = On, 0=Off
Upper Nibble
Lower Nibble
Checkpoint
MSB
8h
4h 2h
L
#6 E #5
D
#7
1h
8h
4h
2h
LSB
1h
#4
#3
#2
#1
#0
0x10h
0x11h
0x12h
0x13h
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0x14h
0
0
0
1
0
1
0
0
0x15h
0
0
0
1
0
1
0
1
0x21h
0
0
1
0
0
0
0
1
0x22h
0x23h
0x24h
0x25h
0x26h
0x27h
0x28h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0xE4h
1
1
1
0
0
1
0
0
0xE6h
0xE8h
0xE9h
0xEAh
0xEBh
0xECh
0xEDh
0xEBh
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
Revision 2.0
Description
Host Processor
Power-on initialization of the host processor (bootstrap processor)
Host processor cache initialization (including AP)
Starting application processor initialization
SMM initialization
Selection of Processor with least features to be used as Boot Strap
Processor
Switch an AP processor to become the new Boot Strap Processor
Chipset
Initializing a chipset component
Memory
Reading configuration data from memory (SPD on FBDIMM)
Detecting presence of memory
Programming timing parameters in the memory controller
Configuring memory parameters in the memory controller
Optimizing memory controller settings
Initializing memory, such as ECC in it
Testing memory
BIOS cannot communicate with DIMM (serial channel hardware
failure)
DIMM(s) failed Memory iBIST or Memory Link Training failure
No memory available (system halted)
Unsupported or invalid DIMM configuration (system halted)
DIMM training sequence failed (system halted)
Memory test failed (system halted)
Unsupported or invalid DIMM configuration (system halted)
Unsupported or invalid DIMM configuration (system halted)
DIMM with corrupted SPD data detected (system halted)
Intel order number G52803-002
169
Appendix D: POST Code LED Decoder
0xA0h
0xA1h
0xA2h
0xA3h
0xA4h
0xA5h
0xA6h
0xA7h
0xA8h
0xA9h
0xAAh
0xABh
0xACh
0xADh
0xAEh
0xAFh
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0xB0h
0xB1h
0xB2h
0xB3h
0xB4h
0xB5h
0xB6h
0xB7h
0xB8h
0xB9h
0xBAh
0xBBh
0xBCh
0xBDh
0xBEh
0xBFh
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0x50h
0x51h
0x52h
0x53h
0x54h
0x55h
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
170
Intel®Server Boards S2400LP TPS
QuickPath Interconnect (QPI)
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
0
QPI Initialization
1
QPI Initialization
Integrated Memory Controller (IMC)
0
0
Memory Initialization of Integrated Memory Controller
0
1
Memory Initialization of Integrated Memory Controller
1
0
Memory Initialization of Integrated Memory Controller
1
1
Memory Initialization of Integrated Memory Controller
0
0
Memory Initialization of Integrated Memory Controller
0
1
Memory Initialization of Integrated Memory Controller
1
0
Memory Initialization of Integrated Memory Controller
1
1
Memory Initialization of Integrated Memory Controller
0
0
Memory Initialization of Integrated Memory Controller
0
1
Memory Initialization of Integrated Memory Controller
1
0
Memory Initialization of Integrated Memory Controller
1
1
Memory Initialization of Integrated Memory Controller
0
0
Memory Initialization of Integrated Memory Controller
0
1
Memory Initialization of Integrated Memory Controller
1
0
Memory Initialization of Integrated Memory Controller
1
1
Memory Initialization of Integrated Memory Controller
PCI Bus
0
0
Enumerating PCI buses
0
1
Allocating resources to PCI buses
1
0
Hot Plug PCI controller initialization
1
1
Reserved for PCI bus
0
0
Reserved for PCI bus
0
1
Reserved for PCI bus
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix D: POST Code LED Decoder
0x56h
0x57h
0x58h
0x59h
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0x5Ah
0x5Bh
0x5Ch
0x5Dh
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0x5Eh
0x5Fh
0
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0x61h
0
1
1
0
0
0
0
1
0x63h
0
1
1
0
0
0
1
1
0x70h
0x71h
0x72h
0x73h
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
0x78h
0x79h
0x7Ah
0x7Bh
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
0x90h
0x91h
0x92h
0x93h
0x94h
0x96h
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
0
0x98h
0x99h
0x9Ah
0x9Bh
0x9Ch
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
0
1
1
1
1
1
0
1
0
1
0
0xA8h
0xA9h
0xAAh
0xABh
0xACh
0xADh
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Revision 2.0
USB
Initializing USB host controllers
Detecting USB devices
Resetting USB bus
Reserved for USB devices
ATA/ATAPI/SATA
Resetting SATA bus and all devices
Detecting the presence of ATA device
Enable SMART if supported by ATA device
Reserved for ATA
SMBUS*
Resetting SMBUS*
Reserved for SMBUS*
I/O Controller Hub
Initializing I/O Controller Hub
Super I/O
Initializing Super I/O
Local Console
Resetting the video controller (VGA)
Disabling the video controller (VGA)
Enabling the video controller (VGA)
Reserved for video controller (VGA)
Remote Console
Resetting the console controller
Disabling the console controller
Enabling the console controller
Reserved for console controller
Keyboard (only USB)
Resetting the keyboard
Disabling the keyboard
Detecting the presence of the keyboard
Enabling the keyboard
Clearing keyboard input buffer
Reserved for keyboard
Mouse (only USB)
Resetting the mouse
Detecting the mouse
Detecting the presence of mouse
Enabling the mouse
Reserved for mouse
Serial Port
Resetting the serial port
Disabling the serial port
Detecting the presence of the serial port
Clearing serial port buffer
Enabling serial port
Reserved for serial port
Intel order number G52803-002
171
Appendix D: POST Code LED Decoder
0xB0h
0xB1h
1
1
0
0
1
1
1
1
0
0
0
0
0xB2h
1
0
1
1
0
0
0xB3h
0xB4h
1
1
0
0
1
1
1
1
0
0
0
1
0xB8h
0xB9h
1
1
0
0
1
1
1
1
1
1
0
0
0xBAh
1
0
1
1
1
0
0xBCh
0xBDh
1
1
0
0
1
1
1
1
1
1
1
1
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xDF
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0xE0h
0xE1h
0xE2h
0xE3h
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0xF0h
0xF1h
0xF2h
0xF3h
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0xE4h
0xE5h
0xE6h
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
0xE7h
0xE8h
0xE9h
0xEAh
0xEBh
0xECh
0xEDh
0xEEh
0xEFh
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
0
0
1
1
172
Intel®Server Boards S2400LP TPS
Fixed Media
Resetting fixed media device
Disabling fixed media device
Detecting presence of a fixed media device (SATA hard drive
1
0
detection, and so forth)
1
1
Enabling/configuring a fixed media device
0
0
Reserved for fixed media
Removable Media
0
0
Resetting removable media device
0
1
Disabling removable media device
Detecting presence of a removable media device (SATA CDROM
1
0
detection, and so forth)
0
0
Enabling/configuring a removable media device
0
1
Reserved for removable media device
Boot Device Selection (BDS)
0
0
Entered the Boot Device Selection phase (BDS)
0
1
Return to last good boot device
1
0
Setup boot device selection policy
1
1
Connect boot device controller
0
0
Attempt flash update boot mode
0
1
Transfer control to EFI boot
1
0
Trying to boot device selection
1
1
Reserved for boot device selection
Pre-EFI Initialization (PEI) Core
0
0
Entered Pre-EFI Initialization phase (PEI)
0
1
Started dispatching early initialization modules (PEIM)
1
0
Initial memory found, configured, and installed correctly
1
1
Transfer control to the DXE Core
PEI Modules
0
0
Install PEIM for Platform Status Codes
0
1
Detecting Platform Type
1
0
Early Platform Initialization
1
1
PEI Modules initialized
Driver eXecution Environment (DXE) Core
0
0
Entered EFI driver execution phase (DXE)
0
1
Started dispatching drivers
1
0
Started connecting drivers
DXE Drivers
0
1
Waiting for user input
0
0
Checking password
0
1
Entering BIOS setup
0
0
Flash Update
0
1
Legacy Option ROM initialization
0
0
DXE Drivers initialized
0
1
Transfer control to Boot Device Selection (BDS)
0
0
Calling Int 19. One beep unless silent boot is enabled.
0
1
Unrecoverable boot failure
0
0
0
1
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
0x30h
0x31h
0x34h
0x35h
0x36h
0x3Eh
0x3Fh
0
0
0
0
0
0
0
Revision 2.0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
Appendix D: POST Code LED Decoder
0
0
1
1
1
1
1
Pre-EFI Initialization Module (PEIM)/Recovery
0
0
Crisis recovery initiated because of a user request
0
1
Crisis recovery initiated by software (corrupt flash)
0
0
Loading crisis recovery capsule
0
1
Handing off control to the crisis recovery capsule
1
0
Begin crisis recovery
1
0
No crisis recovery capsule detected
1
1
Crisis recovery capsule failed integrity check of capsule descriptors
Intel order number G52803-002
173
Appendix E: Video Post Code Errors
Intel®Server Boards S2400LP TPS
Appendix E: Video POST Code Errors
Whenever possible, the BIOS outputs the current boot progress codes on the video screen.
Progress codes are 32-bit quantities plus optional data. The 32-bit numbers include class,
subclass, and operation information. The class and subclass fields point to the type of hardware
being initialized. The operation field represents the specific initialization activity. Based on the
data bit availability to display progress codes, a progress code can be customized to fit the data
width. The higher the data bit, the higher the granularity of information that can be sent on the
progress port. The progress codes may be reported by the system BIOS or option ROMs.
The Response section in the following table is divided into three types:



No Pause: The message is displayed on the local Video screen during POST or in the
Error Manager. The system continues booting with a degraded state. The user may want
to replace the erroneous unit. The setup POST error Pause setting does not have any
effect with this error.
Pause: The message is displayed on the Error Manager screen, and an error is logged
to the SEL. The setup POST error Pause setting determines whether the system pauses
to the Error Manager for this type of error, where the user can take immediate corrective
action or choose to continue booting.
Halt: The message is displayed on the Error Manager screen, an error is logged to the
SEL, and the system cannot boot unless the error is resolved. The user needs to replace
the faulty part and restart the system. The setup POST error Pause setting does not
have any effect with this error.
Table 90. POST Error Messages and Handling
Error Code
0012
CMOS date/time not set
Response
Major
0048
Password check failed
Major
0108
Keyboard component encountered a locked error.
Minor
0109
Keyboard component encountered a stuck key error.
Minor
0113
Fixed Media The SAS RAID firmware cannot run properly. The user should
attempt to reflash the firmware.
Major
0140
PCI component encountered a PERR error.
Major
0141
PCI resource conflict
Major
0146
PCI out of resources error
Major
0192
Processor 0x cache size mismatch detected.
Fatal
0193
Processor 0x stepping mismatch.
Minor
0194
Processor 0x family mismatch detected.
Fatal
0195
Processor 0x Intel(R) QPI speed mismatch.
Major
0196
Processor 0x model mismatch.
Fatal
0197
Processor 0x speeds mismatched.
Fatal
0198
Processor 0x family is not supported.
Fatal
019F
Processor and chipset stepping configuration is unsupported.
Major
5220
CMOS/NVRAM Configuration Cleared
Major
5221
Passwords cleared by jumper
Major
5224
Password clear Jumper is Set.
Major
174
Error Message
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix E: Video Post Code Errors
Error Code
8160
Error Message
Processor 01 unable to apply microcode update
Response
Major
8161
Processor 02 unable to apply microcode update
Major
8180
Processor 0x microcode update not found.
Minor
8190
Watchdog timer failed on last boot
Major
8198
OS boot watchdog timer failure.
Major
8300
Baseboard management controller failed self-test
Major
84F2
Baseboard management controller failed to respond
Major
84F3
Baseboard management controller in update mode
Major
84F4
Sensor data record empty
Major
84FF
System event log full
Minor
8500
Memory component could not be configured in the selected RAS mode.
Major
8501
DIMM Population Error.
Major
8502
CLTT Configuration Failure Error.
Major
8520
DIMM_A1 failed Self Test (BIST).
Major
8521
DIMM_A2 failed Self Test (BIST).
Major
8522
DIMM_B1 failed Self Test (BIST).
Major
8523
DIMM_B2 failed Self Test (BIST).
Major
8524
DIMM_C1 failed Self Test (BIST).
Major
8525
DIMM_C2 failed Self Test (BIST).
Major
8526
DIMM_D1 failed Self Test (BIST).
Major
8527
DIMM_D2 failed Self Test (BIST).
Major
8528
DIMM_E1 failed Self Test (BIST).
Major
8529
DIMM_E2 failed Self Test (BIST).
Major
852A
DIMM_F1 failed Self Test (BIST).
Major
852B
DIMM_F2 failed Self Test (BIST).
Major
8540
DIMM_A1 Disabled.
Major
8541
DIMM_A2 Disabled.
Major
8542
DIMM_B1 Disabled.
Major
8543
DIMM_B2 Disabled.
Major
8544
DIMM_C1 Disabled.
Major
8545
DIMM_C2 Disabled.
Major
8546
DIMM_D1 Disabled.
Major
8547
DIMM_D2 Disabled.
Major
8548
DIMM_E1 Disabled.
Major
8549
DIMM_E2 Disabled.
Major
854A
DIMM_F1 Disabled.
Major
854B
DIMM_F2 Disabled.
Major
8560
DIMM_A1 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8561
DIMM_A2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8562
DIMM_B1 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8563
DIMM_B2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8564
DIMM_C1 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8565
DIMM_C2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8566
DIMM_D1 Component encountered a Serial Presence Detection (SPD) fail error.
Major
8567
DIMM_D2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
Revision 2.0
Intel order number G52803-002
175
Appendix E: Video Post Code Errors
Intel®Server Boards S2400LP TPS
Error Code
8568
Error Message
DIMM_E1 Component encountered a Serial Presence Detection (SPD) fail error.
Response
Major
8569
DIMM_E2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
856A
DIMM_F1 Component encountered a Serial Presence Detection (SPD) fail error.
Major
856B
DIMM_F2 Component encountered a Serial Presence Detection (SPD) fail error.
Major
85A0
DIMM_A1 Uncorrectable ECC error encountered.
Major
85A1
DIMM_A2 Uncorrectable ECC error encountered.
Major
85A2
DIMM_B1 Uncorrectable ECC error encountered.
Major
85A3
DIMM_B2 Uncorrectable ECC error encountered.
Major
85A4
DIMM_C1 Uncorrectable ECC error encountered.
Major
85A5
DIMM_C2 Uncorrectable ECC error encountered.
Major
85A6
DIMM_D1 Uncorrectable ECC error encountered.
Major
85A7
DIMM_D2 Uncorrectable ECC error encountered.
Major
85A8
DIMM_E1 Uncorrectable ECC error encountered.
Major
85A9
DIMM_E2 Uncorrectable ECC error encountered.
Major
85AA
DIMM_F1 Uncorrectable ECC error encountered.
Major
85AB
DIMM_F2 Uncorrectable ECC error encountered.
Major
8604
Chipset Reclaim of non critical variables complete.
Minor
9000
Unspecified processor component has encountered a non specific error.
Major
9223
Keyboard component was not detected.
Minor
9226
Keyboard component encountered a controller error.
Minor
9243
Mouse component was not detected.
Minor
9246
Mouse component encountered a controller error.
Minor
9266
Local Console component encountered a controller error.
Minor
9268
Local Console component encountered an output error.
Minor
9269
Local Console component encountered a resource conflict error.
Minor
9286
Remote Console component encountered a controller error.
Minor
9287
Remote Console component encountered an input error.
Minor
9288
Remote Console component encountered an output error.
Minor
92A3
Serial port component was not detected
Major
92A9
Serial port component encountered a resource conflict error
Major
92C6
Serial Port controller error
Minor
92C7
Serial Port component encountered an input error.
Minor
92C8
Serial Port component encountered an output error.
Minor
94C6
LPC component encountered a controller error.
Minor
94C9
LPC component encountered a resource conflict error.
Major
9506
ATA/ATPI component encountered a controller error.
Minor
95A6
PCI component encountered a controller error.
Minor
95A7
PCI component encountered a read error.
Minor
95A8
PCI component encountered a write error.
Minor
9609
Unspecified software component encountered a start error.
Minor
9641
PEI Core component encountered a load error.
Minor
9667
PEI module component encountered a illegal software state error.
Fatal
9687
DXE core component encountered a illegal software state error.
Fatal
96A7
DXE boot services driver component encountered a illegal software state error.
Fatal
96AB
DXE boot services driver component encountered invalid configuration.
Minor
176
Intel order number G52803-002
Revision 2.0
Intel®Server Boards S2400LP TPS
Appendix E: Video Post Code Errors
Error Code
96E7
Error Message
SMM driver component encountered a illegal software state error.
Fatal
0xA000
TPM device not detected.
Minor
0xA001
TPM device missing or not responding.
Minor
0xA002
TPM device failure.
Minor
0xA003
TPM device failed self test.
Minor
0xA022
Processor component encountered a mismatch error.
Major
0xA027
Processor component encountered a low voltage error.
Minor
0xA028
Processor component encountered a high voltage error.
Minor
0xA421
PCI component encountered a SERR error.
Fatal
0xA500
ATA/ATPI ATA bus SMART not supported.
Minor
0xA501
ATA/ATPI ATA SMART is disabled.
Minor
0xA5A0
PCI Express* component encountered a PERR error.
Minor
0xA5A1
PCI Express* component encountered a SERR error.
Fatal
0xA5A4
PCI Express* IBIST error.
Major
0xA6A0
DXE boot services driver Not enough memory available to shadow a legacy
option ROM.
Minor
0xB6A3
DXE boot services driver Unrecognized.
Major
Revision 2.0
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Glossary
Intel®Server Boards S2400LP TPS
Glossary
This appendix contains important terms used in the preceding chapters. For ease of use,
numeric entries are listed first (for example, “82460GX”) with alpha entries following (for
example, “AGP 4x”). Acronyms are then entered in their respective place, with non-acronyms
following.
Table 91. Glossary
Term
ACPI
Advanced Configuration and Power Interface
AP
Application Processor
APIC
Advanced Programmable Interrupt Control
ARP
Address Resolution Protocal
ASIC
Application Specific Integrated Circuit
BIOS
Basic Input/Output System
BIST
Built-In Self Test
BMC
Baseboard Management Controller
Bridge
Circuitry connecting one computer bus to another, allowing an agent on one to access the other
BSP
Bootstrap Processor
Byte
8-bit quantity.
CATERR
On a catastrophic hardware event the core signals CATERR to the uncore. The core enters a halted
state that can only be exited by a reset.
CBC
Chassis Bridge Controller (A microcontroller connected to one or more other CBCs, together they
bridge the IPMB buses of multiple chassis.)
CEK
Common Enabling Kit
CHAP
Challenge Handshake Authentication Protocol
CMOS
In terms of this specification, this describes the PC-AT compatible region of battery-backed 128 bytes
of memory, which normally resides on the server board.
DCMI
Data Center Management Interface
DHCP
Dynamic Host Configuration Protocal
DPC
Direct Platform Control
EEPROM
Electrically Erasable Programmable Read-Only Memory
EHCI
Enhanced Host Controller Interface
EMP
Emergency Management Port
EPS
External Product Specification
FBD
Fully Buffered DIMM
F MB
Flexible Mother Board
FRB
Fault Resilient Booting
FRU
Field Replaceable Unit
FSB
Front Side Bus
GB
1024 MB
GPIO
General Purpose I/O
GTL
Gunning Transceiver Logic
GPA
Guest Physical Address
HSC
Hot-Swap Controller
HPA
Host Physical Address
Hz
Hertz (1 cycle/second)
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Definition
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Glossary
Term
Definition
I2C
Inter-Integrated Circuit Bus
IA
Intel Architecture
IBF
Input Buffer
ICH
I/O Controller Hub
IC MB
Intelligent Chassis Management Bus
IFB
I/O and Firmware Bridge
ILM
Independent Loading Mechanism
IMC
Integrated Memory Controller
INTR
Interrupt
IP
Internet Protocol
IPMB
Intelligent Platform Management Bus
IPMI
Intelligent Platform Management Interface
IR
Infrared
ITP
In-Target Probe
KB
1024 bytes
KCS
Keyboard Controller Style
LAN
Local Area Network
LCD
Liquid Crystal Display
LED
Light Emitting Diode
LPC
Low Pin Count
LUN
Logical Unit Number
MAC
Media Access Control
MB
1024KB
ME
Management Engine
MD2
Message Digest 2 – Hashing Algorithm
MD5
Message Digest 5 – Hashing Algorithm – Higher Security
ms
Milliseconds
MTTR
Memory Type Range Register
Mux
Multiplexor
NIC
Network Interface Controller
NMI
Nonmaskable Interrupt
OBF
Output Buffer
OEM
Original Equipment Manufacturer
Ohm
Unit of electrical resistance
PECI
Platform Environment Control Interface
PEF
Platform Event Filtering
PEP
Platform Event Paging
PIA
Platform Information Area (This feature configures the firmware for the platform hardware)
PLD
Programmable Logic Device
PMI
Platform Management Interrupt
POST
Power-On Self Test
PSMI
Power Supply Management Interface
PWM
Pulse-Width Modulation
QPI
QuickPath Interconnect
RAM
Random Access Memory
RASUM
Reliability, Availability, Serviceability, Usability, and Manageability
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Term
RISC
Reduced Instruction Set Computing
ROM
Read Only Memory
RTC
Real-Time Clock (Component of ICH peripheral chip on the server board)
RMM3
Remote Management Module 3
SDR
Sensor Data Record
SECC
Single Edge Connector Cartridge
SEEPROM
Serial Electrically Erasable Programmable Read-Only Memory
SEL
System Event Log
SIO
Server Input/Output
SMBUS*
System Management BUS
SMI
Server Management Interrupt (SMI is the highest priority nonmaskable interrupt)
SMM
Server Management Mode
SMS
Server Management Software
SNMP
Simple Network Management Protocol
TBD
To Be Determined
TDP
Thermal Design Power
TIM
Thermal Interface Material
UART
Universal Asynchronous Receiver/Transmitter
UDP
User Datagram Protocol
UHCI
Universal Host Controller Interface
URS
Unified Retention System
UTC
Universal time coordinare
UUID
Universally Unique Identifier
VID
Voltage Identification
VRD
Voltage Regulator Down
VT
Virtualization Technology
Word
16-bit quantity
ZIF
Zero Insertion Force
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Reference Documents
Reference Documents

ACPI 3.0: http://www.acpi.info/spec.htm

IPMI 2.0

Data Center Management Interface Specification v1.0, May 1, 2008:
www.intel.com/go/dcmi

PCI Bus Power Management Interface Specification 1.1: http://www.pcisig.com/

PCI Express* Base Specification Rev 2.0 Dec 06: http://www.pcisig.com/

PCI Express* Card Electromechanical Specification Rev 2.0: http://www.pcisig.com/

PMBus*: http://pmbus.org

SATA 2.6: http://www.sata-io.org/

SMBIOS 2.4

SSI-EEB 3.0: http://www.ssiforum.org

USB 1.1: http://www.usb.org

USB 2.0: http://www.usb.org

Windows Logo/SDG 3.0

Intel® Dynamic PowerTechnology Node Manager 1.5 External Interface Specification
using IPMI, 2007. Intel Corporation.

Node Power and Thermal Management Architecture Specification v1.5, rev.0.79. 2007,
Intel Corporation.

Intel® Server System Integrated Baseboard Management Controller Core External
Product Specification, 2007 Intel Corporation.

Intel® Thurley Server Platform Services IPMI Commands Specification, 2007. Intel
Corporation.

Intel® Server Safety and Regulatory, 2011. Intel Corporation. Order number: G23122001.

Intelligent Platform Management Bus Communications Protocol Specification, Version
1.0, 1998. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell
Computer Corporation.

Platform Environmental Control Interface (PECI) Specification, Version 2.0. Intel
Corporation.

Platform Management FRU Information Storage Definition, Version 1.0, Revision 1.2,
2002. Intel Corporation, Hewlett-Packard Company, NEC Corporation, Dell Computer
Corporation. http://developer.intel.com/design/servers/ipmi/spec.htm.
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