i.MX6 SODIMM SOM Hardware User Guide

i.MX6 SODIMM SOM Hardware User Guide
iW-RainboW-G15M-SM
i.MX6 SODIMM System On Module
Hardware User Guide
iWave Systems Technologies Pvt. Ltd.
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i.MX6 SODIMM SOM Hardware User Guide
Document Revision History
Document Number
Revision
Date
iW-PREPZ-UM-01-R3.0-REL1.2-Hardware
Description
1.0
29th Dec 2014 Initial Release Version
1.1
18th Jul 2016 Updated version - Substantive changes done throughout the document
03rd Mar 2017 Updated version
 Pins 179, 189, 194, 196 & 200 details are updated in Table 5
 Section 2.6.22 is newly added
 Section 3.3.1 is updated.
 Table 11 Orderable Product Part Numbers are updated
 Non-Substantive changes done throughout the document
PROPRIETARY NOTICE: This document contains proprietary material for the sole use of the intended recipient(s). Do
not read this document if you are not the intended recipient. Any review, use, distribution or disclosure by others is
strictly prohibited. If you are not the intended recipient (or authorized to receive for the recipient), you are hereby
notified that any disclosure, copying distribution or use of any of the information contained within this document is
STRICTLY PROHIBITED. Thank you. “iWave Systems Tech. Pvt. Ltd.”
1.2
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i.MX6 SODIMM SOM Hardware User Guide
Disclaimer
iWave Systems reserves the right to change details in this publication including but not limited to any Product
specification without notice.
No warranty of accuracy is given concerning the contents of the information contained in this publication. To the
extent permitted by law no liability (including liability to any person by reason of negligence) will be accepted by
iWave Systems, its subsidiaries or employees for any direct or indirect loss or damage caused by omissions from or
inaccuracies in this document.
CPU and other major components used in this product may have several silicon errata associated with it. Under no
circumstances, iWave Systems shall be liable for the silicon errata and associated issues.
Trademarks
All registered trademarks, product names mentioned in this publication are the property of their respective owners
and used for identification purposes only.
Certification
iWave Systems Technologies Pvt. Ltd. is an ISO 9001:2015 Certified Company.
Warranty & RMA
Warranty support for Hardware: 1 Year from iWave or iWave's EMS partner.
For warranty terms, go through the below web link,
http://www.iwavesystems.com/support/warranty.html
For Return Merchandise Authorization (RMA), go through the below web link,
http://www.iwavesystems.com/support/rma.html
Technical Support
iWave Systems technical support team is committed to provide the best possible support for our customers so that
our Hardware and Software can be easily migrated and used.
For assistance, contact our Technical Support team at,
Email
: support.ip@iwavesystems.com
Website
: www.iwavesystems.com
Address
: iWave Systems Technologies Pvt. Ltd.
# 7/B, 29th Main, BTM Layout 2nd Stage,
Bangalore, Karnataka,
India – 560076
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i.MX6 SODIMM SOM Hardware User Guide
Table of Contents
1.
INTRODUCTION ............................................................................................................................................ 7
1.1
1.2
1.3
1.4
1.5
1.6
2.
Purpose ............................................................................................................................................................. 7
SODIMM SOM Overview ................................................................................................................................... 7
List of Acronyms ................................................................................................................................................ 7
Terminlogy Description ..................................................................................................................................... 9
References ........................................................................................................................................................ 9
Important Note ............................................................................................................................................... 10
ARCHITECTURE AND DESIGN ....................................................................................................................... 11
2.1
i.MX6 SODIMM SOM Block Diagram............................................................................................................... 11
2.2
i.MX6 SODIMM SOM Features ........................................................................................................................ 12
2.3
i.MX6 CPU ....................................................................................................................................................... 14
2.4
PMIC ................................................................................................................................................................ 15
2.5
Memory........................................................................................................................................................... 15
2.5.1 DDR3 SDRAM .............................................................................................................................................. 15
2.5.2 SPI NOR Flash .............................................................................................................................................. 15
2.5.3 eMMC Flash ................................................................................................................................................ 15
2.6
i.MX6 SODIMM PCB Edge Connector.............................................................................................................. 16
2.6.1 Boot Setting ................................................................................................................................................. 17
2.6.2 Gigabit Ethernet .......................................................................................................................................... 18
2.6.3 PCIe Interface .............................................................................................................................................. 18
2.6.4 SATA Interface ............................................................................................................................................. 19
2.6.5 USB2.0 OTG Interface.................................................................................................................................. 19
2.6.6 USB2.0 Host Interface ................................................................................................................................. 19
2.6.7 SD Interface ................................................................................................................................................. 19
2.6.8 Parallel Camera Interface............................................................................................................................ 20
2.6.9 Parallel RGB Display Interface ..................................................................................................................... 20
2.6.10 LVDS Interface ............................................................................................................................................. 20
2.6.11 HDMI Interface ............................................................................................................................................ 21
2.6.12 I2S Audio Interface ...................................................................................................................................... 21
2.6.13 UART Interface ............................................................................................................................................ 22
2.6.14 SPI Interface ................................................................................................................................................ 22
2.6.15 CAN Interface .............................................................................................................................................. 22
2.6.16 I2C Interface ................................................................................................................................................ 23
2.6.17 PWM Interface ............................................................................................................................................ 23
2.6.18 GPIO Interface ............................................................................................................................................. 23
2.6.19 JTAG Interface ............................................................................................................................................. 23
2.6.20 Power Input ................................................................................................................................................. 24
2.6.21 Reset Button Input ...................................................................................................................................... 24
2.6.22 Power Button Input ..................................................................................................................................... 24
2.7
i.MX6 Pin Multiplexing on SODIMM Edge ...................................................................................................... 36
3.
TECHNICAL SPECIFICATION.......................................................................................................................... 47
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3.1
Electrical Characteristics ................................................................................................................................. 47
3.1.1 Power Input Requirement ........................................................................................................................... 47
3.1.2 Power Input Sequencing.............................................................................................................................. 48
3.1.3 Power Consumption .................................................................................................................................... 49
3.2
Environmental Characteristics ........................................................................................................................ 50
3.2.1 Environmental Specification........................................................................................................................ 50
3.2.2 RoHS Compliance ........................................................................................................................................ 50
3.2.3 Electrostatic Discharge................................................................................................................................ 50
3.3
Mechanical Characteristics ............................................................................................................................. 51
3.3.1 i.MX6 SODIMM SOM Mechanical Dimensions ............................................................................................ 51
4.
ORDERING INFORMATION .......................................................................................................................... 52
5.
APPENDIX I ................................................................................................................................................. 54
5.1
5.2
6.
Guidelines to insert the SODIMM SOM into Carrier board ............................................................................ 54
Guidelines to remove the SODIMM SOM from Carrier board ........................................................................ 54
APPENDIX II ................................................................................................................................................ 55
6.1
i.MX6 SODIMM SOM Development Platform ................................................................................................. 55
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List of Figures
Figure 1: i.MX6 SODIMM SOM Block Diagram................................................................................................................ 11
Figure 2: i.MX6 Simplified Block Diagram ....................................................................................................................... 14
Figure 3: i.MX6 SODIMM PCB Edge Connector............................................................................................................... 16
Figure 4: i.MX6 SODIMM SOM Power Sequence ............................................................................................................ 48
Figure 5: Mechanical dimension of i.MX6 SODIMM SOM - Top View ............................................................................ 51
Figure 6: Mechanical dimension of i.MX6 SODIMM SOM - Side View ........................................................................... 51
Figure 7: Module Insertion Procedure ............................................................................................................................ 54
Figure 8: Module Removal Procedure ............................................................................................................................ 54
Figure 9: i.MX6 SODIMM SOM Development Platform .................................................................................................. 55
List of Tables
Table 1: Acronyms & Abbreviations.................................................................................................................................. 7
Table 2: Terminology ........................................................................................................................................................ 9
Table 3: Boot Mode Pin Settings Truth Table ................................................................................................................. 17
Table 4: Compatible Magnetics ...................................................................................................................................... 18
Table 5: 200-Pin PCB Edge Connector Pin Assignment ................................................................................................... 25
Table 6: IOMUX Configuration of i.MX6 SODIMM SOM Edge Connector interfaces ..................................................... 36
Table 7: Power Input Requirement ................................................................................................................................. 47
Table 8: Power Sequence Timing .................................................................................................................................... 48
Table 9: Power Consumption .......................................................................................................................................... 49
Table 10: Environmental Specification ........................................................................................................................... 50
Table 11: Orderable Product Part Numbers ................................................................................................................... 52
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i.MX6 SODIMM SOM Hardware User Guide
1. INTRODUCTION
1.1
Purpose
This document is the Hardware User Guide for the i.MX6 SODIMM System On Module based on the NXP’s i.MX6
Applications Processor with PMIC. This board is fully supported by iWave Systems Technologies Pvt. Ltd. This Guide
provides detailed information on the overall design and usage of the i.MX6 SODIMM System On Module from a
Hardware Systems perspective.
1.2
SODIMM SOM Overview
The i.MX6 SODIMM SOM is extension of i.MX6 CPU. Also with the SOM approach one can reduce the cost and time
required for the development of customised solution on i.MX6 SODIMM platform. SODIMM module has a form
factor of 67.6mm x 37mm and provides the functional requirements for an embedded application. A single
ruggedized SODIMM connector provides the carrier board interface to carry all the I/O signals to and from the
SODIMM module.
1.3
List of Acronyms
The following acronyms will be used throughout this document.
Table 1: Acronyms & Abbreviations
Acronyms
ARM
BPP
BSP
CAN
CMOS
CPU
CSI
DDR3
eCSPI
eMMC
FLEXCAN
GB
Gbps
GPIO
HDMI
I2C
IC
JTAG
Kbps
Abbreviations
Advanced RISC Machine
Bits Per Pixel
Board Support Package
Controller Area Network
Complementary Metal-Oxide Semiconductor
Central Processing Unit
Camera Serial Interface
Double Data Rate 3
Enhanced Configurable Serial Peripheral Interface
Enhanced Multi Media Card
Flexible Controller Area Network
Giga Byte
Gigabits per sec
General Purpose Input Output
High Definition Multimedia Interface
Inter-Integrated Circuit
Integrated Circuit
Joint Test Action Group
Kilobits per second
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Acronyms
LCD
LVDS
MAC
MB
Mbps
MHz
NC
PCB
PCIe
PMIC
PWM
RTC
SAI
SD
SDRAM
SOM
SODIMM
UART
USB
USB OTG
Abbreviations
Liquid Crystal Display
Low Voltage Differential Signal
Media Access Controller
Mega Byte
Megabits per sec
Mega Hertz
No Connect
Printed Circuit Board
Peripheral Component Interface Express
Power Management Integrated Circuit
Pulse Width Modulation
Real Time Clock
Synchronous Audio Interface
Secure Digital
Synchronous Dynamic Random Access Memory
System On Module
Small Outline Dual in-line Memory Module
Universal Asynchronous Receiver/Transmitter
Universal Serial Bus
USB On The Go
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1.4
Terminlogy Description
In this document, wherever Signal Type is mentioned, below terminology is used.
Table 2: Terminology
Terminology
I
O
IO
CMOS
DIFF
OD
OC
Power
PU
PD
NA
NC
Description
Input Signal
Output Signal
Bidirectional Input/output Signal
Complementary Metal Oxide Semiconductor Signal
Differential Signal
Open Drain Signal
Open Collector Signal
Power Pin
Pull Up
Pull Down
Not Applicable
Not Connected
Note: Signal Type does not include internal pull-ups or pull-downs implemented by the chip vendors and only includes
the pull-ups or pull-downs implemented On-SOM.
1.5
References

i.MX6 Applications Processors Datasheet

i.MX6 Applications Processors Reference Manual
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1.6
Important Note
i.MX6 SODIMM Edge connector pin name mentioned in Table 5 is followed as per below format for easy
understanding.

If CPU pin functionality name and CPU pad name is same, Signal name is mentioned as
“CPU Pad Name”
Example: SD1_DATA1
In this signal, functionality which we are using and CPU Pad name is SD1_DATA1.

If CPU pin functionality name and pad name is different, Signal name is mentioned as
“Functionality name (CPU Pad name)”
Example: CAN1_RXD (UART3_RTS_B)
In this signal, CAN1_RXD is the functionality which we are using and UART3_RTS_B is the CPU Pad name.

If CPU pin functionality is GPIO, Signal name is mentioned as
“FunctionalityDescription (CPU Pad name)”
Example: PWM4_OUT (GPIO1_IO05)
In this signal, PWM4_OUT is the functionality which we are using and GPIO1_IO05 is the CPU pad name.
Note: The above naming is not applicable for other signals which are not connected to CPU.
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i.MX6 SODIMM SOM Hardware User Guide
2. ARCHITECTURE AND DESIGN
This section provides detailed information about the i.MX6 SODIMM SOM Features and Hardware architecture with
high level block diagram. Also this section provides detailed information about SODIMM edge connector pin
assignment and usage.
2.1
i.MX6 SODIMM SOM Block Diagram
iW-RainboW-G15M-SM -i.MX6 SODIMM SOM Block Diagram
DDR3 RAM
(1GB)
DDR31 (64bit)
10/100/1000
ENET
MMDC
RGMII x 1
Gigabit
Ethernet PHY
10/100/1000
Ethernet
PCIe x 1
SPI Flash
(2MB)
PCIe
SPI
eCSPI1
SATA2 x 1
SATA
eMMC
(4GB)
MMC (8bit)
USB Host x 1
USB HOST1
HS PHY
uSDHC4
USBOTG x 1
USB OTG
HS PHY
SD (4bit)
uSDHC3
Camera(8bit)3
CSI0
RGB LCD (24bpp)
DISP0
LVDS
LVDS0
SODIMM
PCB Edge
Connector
(200Pin)
HDMI
CPU
i.MX6x
HDMI 1.4
I2S x 1
AUDMUX4
Debug
UART2
UART1
UART4
UART5
UART3 x 3
SPI x 1
eCSPI2
CAN x 2
CAN1,CAN2
I2C x 2
I2C1,I2C3
PWM x 4
1
Solo CPU supports only 32bit DDR3 interface.
2 SATA interface is not supported in i.MX6
Duallite and Solo CPU.
3 If Parallel camera interface is used, then two
data UART interfaces (UART4 & UART5)
cannot be used with hardware flow control
signals on SODIMM edge.
PWM 1-4
GPIOs
GPIOs
JTAG
SJC
Power to
Peripherals
PMIC
3.3V
Figure 1: i.MX6 SODIMM SOM Block Diagram
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2.2
i.MX6 SODIMM SOM Features
The i.MX6 SODIMM SOM supports the following features.
CPU

NXP’s i.MX6 Quad/Dual/Duallite/Solo ARM™ Cortex-A9 based CPU @ up to 1.2GHz/Core

NXP’s MMPF0100 PMIC

1GB DDR3 RAM (Expandable)

2MB SPI NOR Flash (Expandable)

4GB eMMC Flash (Expandable)
PMIC
Memory
SODIMM PCB Edge Interfaces

Boot Mode Control Signals

Gigabit Ethernet through On-SOM Ethernet PHY Transceiver x 1 Port

PCIe x 1 Port

SATA II (3.0 Gbps) x 1 Port 1

USB2.0 OTG x 1 Port

USB2.0 Host x 1 Port

SD (4bit) x 1 Port

Parallel Camera Port (8bit) x 1 Port 2,3

Parallel RGB Display (24bpp) x 1 Port 4

LVDS x 1 Port 4

HDMI 1.4 x 1 Port 4

I2S Audio Interface x 1 Port

Debug UART

Data UART x 3 Ports 2

SPI x 1 Port 3

CAN x 2 Ports

I2C x 2 Ports

PWM x 4 Ports

General Purpose IOs

JTAG x 1 Port
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i.MX6 SODIMM SOM Hardware User Guide
General Specification

Power Supply : 3.3V

Form Factor
: 67.6mm x 37mm
1
SATA interface is not supported in i.MX6 Duallite and Solo CPU.
2
If Parallel camera interface is used, then two data UART interfaces (UART4 & UART5) cannot be used with hardware
flow control signals on SODIMM edge.
3
If Parallel camera is used with 12bit interface, then SPI interface (eCSPI2) cannot be used on SODIMM edge.
4
i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces (including
LVDS, HDMI & Parallel RGB) can be supported.
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2.3
i.MX6 CPU
i.MX6 SODIMM SOM is based on i.MX 6 series of applications processors is a feature and performance scalable
multicore platform that includes single-, dual- and quad-core families based on the ARM® Cortex® architecture,
including Cortex-A9 based solutions up to 1.2 GHz. i.MX6 CPU is NXP’s latest achievement in integrated multimedia
application processors which is part of growing multimedia-focused products that offers high performance
processing and are optimized for lowest power consumption. The Block Diagram of i.MX6 CPU from the NXP’s i.MX6
(Quad/Dual) datasheet is shown below for reference.
Figure 2: i.MX6 Simplified Block Diagram
Note: Please refer the latest i.MX6 Datasheet & Reference Manual from NXP website for Electrical characteristics of
i.MX6 Application CPU which may be revised from time to time.
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2.4
PMIC
i.MX6 SODIMM SOM supports NXP’s PF0100 PMIC for On-SOM power management. The PF0100 is a Power
Management Integrated Circuit (PMIC) designed specifically for always ON application with the NXP i.MX6
application processors.
This PMIC supports up to six buck converters, six linear regulators, RTC supply and coin-cell charger with
programmable output voltage, sequence and timing. i.MX6 CPU’s I2C1 interface is used for PMIC programmable. I2C
address for PMIC is 0x08.
2.5
Memory
2.5.1 DDR3 SDRAM
i.MX6 SODIMM SOM by default supports 1GB DDR3 RAM memory in 64bit mode. To support this, it uses four 256MB
DDR3 SDRAM ICs. These devices operate at 1.5V voltage level. Each pair of DDR3 ICs is physically located on either
side of the iMX6 SODIMM SOM. The RAM size can be expandable up to maximum of 4GB.
Note: By default, 512MB DDR3 with 32bit mode only supported in i.MX6 Solo CPU based SODIMM SOM.
2.5.2 SPI NOR Flash
The i.MX6 SODIMM SOM supports 2MB SPI NOR Flash as default boot device. This is connected to eCSPI1 controller
of the i.MX6 CPU and operates at 3.3 Voltage level. The SPI flash memory is physically located on top side of the
SODIMM SOM. The memory size of the SPI Flash can be expandable.
2.5.3 eMMC Flash
i.MX6 SODIMM SOM supports 4GB eMMC (expandable) memory as mass. eMMC is directly connected to the
uSDHC4 of the i.MX6 CPU and operating at 3.3V Voltage level. The eMMC flash memory is physically located on
bottom side of the SODIMM SOM. The memory size of the eMMC Flash can be expandable.
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2.6
i.MX6 SODIMM PCB Edge Connector
i.MX6 SODIMM SOM Supports JEDEC Physical Standard 200pin SODIMM PCB edge connector for interfaces
expansion. The interfaces which are available at SODIMM Edge connector are explained in the following sections.
Figure 3: i.MX6 SODIMM PCB Edge Connector
Number of Pins
- 200
Connector Part
- Not Applicable (On Board PCB Edge connector)
Mating Connector
- 1473005-1 from TE Connectivity
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2.6.1 Boot Setting
i.MX6 CPU boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to
begin execution starting from the on-chip boot ROM. i.MX6 CPU Boot ROM code uses the state of the internal
register BOOT_MODE [1:0] as well as the state of various eFUSEs and/or GPIO settings to determine the boot flow
behaviour of the device. i.MX6 SODIMM SOM boot media is fixed as SPI flash by On-SOM GPIO setting in hardware.
Note: Contact iWave if different boot media support is required other than SPI flash.
i.MX6 SODIMM SOM supports two boot mode signals on SODIMM Edge Connector. BOOT_MODE is initialized by
sampling the BOOT_MODE0 and BOOT_MODE1 inputs on the rising edge of POR_B. These Boot mode selection
signals are connected to SODIMM Edge connector and desired boot mode must be set from the carrier board as
explained in the below table.
For more details, refer SODIMM Edge connector pins 182 & 184 on Table 5.
Table 3: Boot Mode Pin Settings Truth Table
BOOT_MODE [1]
(SODIMM Edge Pin 184)
BOOT_MODE [0]
(SODIMM Edge Pin 182)
1
0
0
0
0
1
Boot Type
Description
In this mode, i.MX6 boots from the
boot media selected by Boot media
Internal Boot Mode GPIO pin’s settings. By default, SPI is
selected as boot media in i.MX6
SODIMM SOM hardware.
In this mode, i.MX6 boots from the
boot media selected by i.MX6 eFUSE
settings.
Boot From eFuses
Note: i.MX6 eFuse setting is not
modified by iWave from silicon
shipped value.
In this mode, i.MX6 boot media can
be Programmed through its USB OTG
Serial Downloader
interface using manufacturing tool
Mode
supported by NXP/Freescale (MFG
Tool).
Important Note: To make i.MX6 SODIMM SOM boots as expected, make sure to set the desired boot mode from the
carrier board.
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i.MX6 SODIMM SOM Hardware User Guide
2.6.2 Gigabit Ethernet
i.MX6 SODIMM SOM supports one 10/100/1000Mbps Ethernet interface on SODIMM Edge connector through
RGMII interface. The MAC is integrated in the i.MX6 CPU and connected to the external Ethernet PHY on SOM. Since
MAC and PHY are supported on SOM itself, only Magnetics are required on the carrier board. i.MX6 SODIMM SOM
also supports Link and Speed indication LED control signals to SODIMM Edge.
i.MX6 SODIMM SOM supports one “KSZ9031RNXCA” Ethernet PHY from Micrel. These PHY’s are interfaced with
i.MX6 CPU using RGMII interface and works at 1.8V IO voltage level. Since this PHY doesn’t require center tap supply
to the magnetics, CTREF voltage to SODIMM Edge is not supported on SOM. It is recommended that center tap pins
of magnetics should be separated from one another and connected through separate 0.1uF common mode
capacitors to ground. The below table provides the compatible magnetics recommended by PHY Manufacturer.
Table 4: Compatible Magnetics
Part Description
Gigabit Ethernet Discrete Transformer
Gigabit Ethernet Discrete Transformer
RJ45 Magjack with two Green LED
RJ45 Magjack with two Green LED
Gigabit Ethernet Discrete Transformer
Part Number
Manufacturer
Temperature
TG1G-E001NZRL
HX5008NL
JK0654219NL
0826-1G1T-23F
000-7093-37R-LF1
HALO
Pulse
Pulse
Bel Fuse
Wurth
-40°C to 85°C
-40°C to 85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
For more details, refer SODIMM Edge connector pins 2, 4, 6, 8, 14, 16, 15 & 17 on Table 5.
Note: As per i.MX6 CPU Errata ERR004512, Gigabit Ethernet MAC has throughout limitation. The theoretical
maximum performance of 1Gbps ENET is limited to 470 Mbps (total for Tx and Rx). The actual measured performance
in an optimized environment is up to 400 Mbps.
2.6.3 PCIe Interface
i.MX6 SODIMM SOM supports one PCI Express Gen2.0 lane on SODIMM Edge connector. i.MX6 CPU’s PCIe Express
core with integrated PHY is used for PCIe Interface which can support PCIe Gen2.0 at 5Gbps data rate and are
backward compatible to Gen1.1 at 2.5Gbps data rate. PCIe wake input and PCIe reset output are supported on
SODIMM Edge connector from i.MX6 CPU GPIOs GPIO_2 & GPIO_16 correspondingly.
For more details, refer SODIMM Edge connector pins 127, 128, 129, 130, 132, 134, 135 & 137 on Table 5.
Note: Termination is required on the PCIe differential clock lines and should be placed as close as possible to the
receiver device input or PCIe connector. Connect two 49.9 Ω resistors between REFCLK- and GND & REFCLK+ and
GND. Alternately, Connect a 100 Ω resistor between REFCLK- and REFCLK+. PCIe differential transmitter lines are ac
coupled on SOM itself.
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2.6.4 SATA Interface
i.MX6 SODIMM SOM supports one SATA II lane on SODIMM Edge connector. i.MX6 CPU’s SATA controller core with
integrated PHY is used for SATA Interface which can support SATA II with transfer rate of 3Gbps and backward
compatible to SATA I with transfer rate of 1.5Gbps.
For more details, refer SODIMM Edge connector pins 82, 84, 85 & 87 on Table 5.
Note: SATA interface is not supported in i.MX6 Duallite and i.MX6 Solo CPU.
2.6.5 USB2.0 OTG Interface
i.MX6 SODIMM SOM supports one High Speed USB2.0 OTG interfaces on SODIMM Edge connector. i.MX6 CPU’s
USB2.0 OTG controller core with integrated PHY is used for USB2.0 OTG interface which can operate in High Speed
operation (480 Mbps), Full Speed operation (12Mbps) and Low Speed operation (1.5 Mbps). i.MX6 CPU’s OTG
controller core can operate in Host mode and Device (Peripheral) mode. Also USB ID input from SODIMM Edge
connector is connected to i.MX6 CPU’s USB_OTG_ID for auto USB host or device detection.
For more details, refer SODIMM Edge connector pins 74, 77, 81 & 83 on Table 5.
2.6.6 USB2.0 Host Interface
i.MX6 SODIMM SOM supports one USB2.0 Host interface on SODIMM Edge connector. i.MX6 CPU’s USB2.0 Host
controller core with integrated PHY is used for USB2.0 Host interface which can operate in High Speed operation
(480 Mbps), Full Speed operation (12Mbps) and Low Speed operation (1.5 Mbps).
For more details, refer SODIMM Edge connector pins 39, 140, 188 & 190 on Table 5.
2.6.7 SD Interface
I.MX6 SODIMM SOM supports one SDIO interface port on SODIMM Edge connector. i.MX6 CPU’s uSDHC3 controller
is used for SD interface which is fully compliant with SD Memory Card Specifications v3.0 including high-capacity
SDHC cards up to 32 GB & SDXC cards up to 2TB and SDIO Card Specification Part E1, v1.10. It supports 1-bit or 4-bit
transfer mode for SD and SDIO cards up to UHS-I SDR104 mode (104 MB/s max). i.MX6 SODIMM SOM can also
support SDIO card detect input from SODIMM Edge connector through i.MX6 CPU pin EIM_D25 .
For more details, refer SODIMM Edge connector pins 105, 107, 108, 109, 111, 112 & 114 on Table 5.
Note: If EIM_D25 is not used for SDIO card detect, the same pins can be used for SS3 chip select
(eCSPI2_SS3(EIM_D25) of eCSPI2 interface.
Note: If more SDIO interfaces are required on SODIMM edge, it can be supported by modifying the CPU IOMUX
setting on SODIMM edge pins. Contact iWave for more details.
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i.MX6 SODIMM SOM Hardware User Guide
2.6.8 Parallel Camera Interface
i.MX6 SODIMM SOM supports one 8bit/12bit camera interface on SODIMM Edge Connector. i.MX6 CPU’s CSI parallel
port is used for camera interface which provides direct connectivity to most relevant CMOS sensors and CCIR656
video interface. The sensor is the master of the pixel clock (PIXCLK) & synchronization signals where synchronization
signals can be received using dedicated control signals method (HSYNC & VSYNC) or controls embedded in data
stream method (CCIR.656 protocol).
For more details, refer SODIMM Edge connector pins 38, 75, 93, 96, 100, 101, 104, 119,120, 121, 123 & 126 for 8bit
camera interface on Table 5. For 12bit camera, please refer pins 63, 66, 70 & 110 for extra 4bits on Table 5
Note: If Parallel camera interface is used on SODIMM edge, then UART4 & UART5 cannot be used with hardware flow
control for request to send and clear to send signals.
Note: If Parallel camera is used with 12bit interface on SODIMM edge, then eCSPI2 interface cannot be used.
2.6.9 Parallel RGB Display Interface
i.MX6 SODIMM SOM supports one 24bpp Parallel RGB display interface on SODIMM Edge connector. i.MX6 CPU’s
IPU is used for parallel LCD display interface which supports upto 24bit data bus (8bits/colour). i.MX6 CPU’s LCD can
support data rate up to up to 225 Mpixels/sec (for example, WUXGA at 60 Hz or dual HD1080 and WXGA at 60 Hz).
For more details, refer SODIMM Edge Connector pins 143, 144, 145, 146, 148, 149, 150, 152, 153, 154, 155, 156, 157,
158, 159, 161, 162, 163, 164, 165, 166, 167, 168, 170, 171, 172, 173, 174 on Table 5.
Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces
(including LVDS, HDMI & Parallel RGB) can be supported.
2.6.10 LVDS Interface
i.MX6 SODIMM SOM supports one LVDS display port on SODIMM Edge connector. i.MX6 CPU’s IPU with LDB is used
for LVDS interface. The purpose of the LDB is to support flow of synchronous RGB data from the IPU to external
display devices through the LVDS interface. It consists of one clock pair & four data pairs and can support data rate
up to 170Mhz (WUXGA 1920x1200). i.MX6 CPU LVDS interface supports 18bit RGB and 24bit RGB colour mapping.
i.MX6 CPU LVDS0 is directly connected to SODIMM Edge connector. LVDS backlight enable and LVDS backlight
brightness control (PWM) are supported on SODIMM Edge connector from i.MX6 CPU pins NANDF_ALE and GPIO_9.
For more details, refer SODIMM Edge connector pins 47, 48, 50, 52, 53, 54, 55, 56, 57, 58, 59 & 138 on Table 5.
Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces
(including LVDS, HDMI & Parallel RGB) can be supported.
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2.6.11 HDMI Interface
i.MX6 SODIMM SOM supports one HDMI display port (Ver. 1.4) on SODIMM Edge connector. HDMI is a compact
audio/video interface for transmitting uncompressed digital video data and uncompressed/compressed digital audio
data. HDMI is electrically compatible with the signals used by DVI and so no signal conversion is necessary, nor is
there a loss of video quality when a DVI-to-HDMI adapter is used.
i.MX6 CPU’s HDMI TX controller with integrated PHY is used for HDMI interface which can support video formats up
to 1080p at 60Hz and 720p/1080i at 120Hz. It can also support CEC interface & HDCP. i.MX6 CPU’s HDMI TX PHY
output is directly connected to SODIMM Edge connector HDMI port. Also i.MX6 CPU supports HDMI Hot plug detect
& HDMI CEC and connected to SODIMM Edge pins 25 & 10 correspondingly.
i.MX6 CPU’s I2C1 interface on SODIMM edge can be used as HDMI DDC interface. When HDCP is enabled, a
dedicated I2C controlled by the HDMI PHY should be used to exchange the HDCP encryption key & must sync several
times per second (not like a common I2C) and so i.MX6 I2C1 interface pins should be configured as HDMI_DDC.
Make sure to use suitable level shifter and driver to interface the I2C with the HDMI monitor since i.MX6 CPU’s I2C
cannot operate at the 5 V required by HDMI EDID. In addition, ESD protection must be used on all HDMI singleended and differential signals mounted near the HDMI connector. CM2020 from ON semiconductor or similar part
could be considered for ESD protection and I2C level conversion.
For more details, refer SODIMM Edge connector pins 18, 19, 21, 22, 23, 24, 25, 26, 28, 29, & 31 on Table 5.
Note: Customers who develop products using HDMI need to work with DCP (http://www.digital-cp.com/licensing) to
get the HDCP license and related device keys.
Note: i.MX6 Duallite and i.MX6 Solo CPU supports only one IPU and so at any time only two display interfaces
(including LVDS, HDMI & Parallel RGB) can be supported.
2.6.12 I2S Audio Interface
i.MX6 SODIMM SOM supports one I2S/SSI audio interface port on SODIMM Edge connector. i.MX6 CPU’s AUDMUX4
port is used for audio interface which provides a programmable interconnect device for voice, audio and
synchronous data routing between i.MX6 CPU’s SSI Controller and external audio/voice codec’s (also known as
coder-decoders). i.MX6 CPU’s SSI controller can be configured as AC’97 mode or I2S mode. I2S mode supports
sampling rate from 8KHz to 196KHz.
For more details, refer SODIMM Edge connector pins 61, 64, 67, 89 & 90 on Table 5.
Note: If AUDMUX4 interface is not required on SODIMM edge, the same pins can be configured as uSDHC2 interface.
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i.MX6 SODIMM SOM Hardware User Guide
2.6.13 UART Interface
i.MX6 SODIMM SOM supports four UART interface on SODIMM Edge connector in which one for Debug UART
interface and other three for Data UART interface. i.MX6 CPU’s UART2 controller is used for Debug UART interface
and UART1, UART4 & UART5 controller is used for Data UART interface on SODIMM Edge connector. Also i.MX6
SODIMM SOM supports hardware flow control for request to send and clear to send signals on UART1, UART4 &
UART5 interface.
i.MX6 CPU UART controller supports Serial RS-232NRZ mode, 9-bit RS-485 mode and IrDA mode. It is compatible
with High-speed TIA/EIA-232-F (up to 5.0 Mbit/s) with auto baud rate detection (up to 115.2 Kbit/s). It supports 7 or
8 data bits for RS-232 characters (9-bit RS-485 format), 1 or 2 stop bits and programmable parity (even, odd, and no
parity).
For more details, refer SODIMM Edge connector pins 117 & 118 for Debug UART, pins 7, 9, 97 & 94 for UART1
interface, pins 98, 99, 100 & 101 for UART4 interface, and pins 38, 75, 102 & 103 for UART5 interface on Table 5.
Note: If Parallel camera interface is used on SODIMM edge, then UART4 & UART5 cannot be used with hardware flow
control for request to send and clear to send signals.
2.6.14 SPI Interface
i.MX6 SODIMM SOM supports one SPI interface with three chip selects on SODIMM Edge connector. i.MX6 CPU’s
eCSPI2 is used for SPI interface which supports full-duplex synchronous four-wire serial interface with DMA. It
supports 32bit x 64 entry FIFO for both transmit and receive data. It can be configured as Master or Slave. Also
polarity and phase of the Chip Select and SPI Clock are configurable.
For more details, refer SODIMM Edge connector pins 62, 63, 66, 70, 71 & 110 on Table 5.
Note: If Parallel camera is used with 12bit interface on SODIMM edge, then eCSPI2 interface cannot be used.
Note: If SDIO card detect is not used on SODIMM Edge connector pin 105, the same pin can be used as fourth chip
select of eCSPI2 interface (eCSPI2_SS3(EIM_D25)).
2.6.15 CAN Interface
i.MX6 SODIMM SOM supports two CAN interface on SODIMM Edge connector. i.MX6 CPU’s FLEXCAN1 & FLEXCAN2
module is used for CAN interface which supports CAN protocol according to the CAN 2.0B protocol specification. It
supports programmable bit rate up to 1 Mb/sec with both standard and extended message frames. Also it supports
64 Message Buffers. To connect external CAN module to this bus, it is necessary to add transceiver in between.
For more details, refer SODIMM Edge connector pins 175, 176, 177 & 178 on Table 5.
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i.MX6 SODIMM SOM Hardware User Guide
2.6.16 I2C Interface
i.MX6 SODIMM SOM supports two I2C interface on SODIMM Edge connector. i.MX6 CPU’s I2C1 and I2C3.channels
are used for general purpose I2C interface which is compatible with the standard NXP I2C bus protocol. It supports
standard mode with data transfer rates up to 100kbps and Fast mode with data transfer rates up to 400kbps.
Since flexible I2C standard allows multiple devices to be connected to the single bus, i.MX6 CPU’s I2C1 and I2C3 can
be connected to more than one device on the carrier board. I2C1 interface is also connected to On-SOM PMIC with
I2C address 0x08 in the i.MX6 SODIMM SOM.
For more details, refer SODIMM Edge connector pins 18 & 19 for I2C1, pins 115 & 116 for I2C3 on Table 5.
2.6.17 PWM Interface
i.MX6 SODIMM SOM supports four PWM interface on SODIMM Edge connector. i.MX6 CPU’s PWM1 PWM2, PWM3
and PWM4 module are used for PWM interface which has a 16-bit counter and optimized to generate sound from
stored sample audio images and it can also generate tones. It uses 16-bit resolution and a 4 x 16 data FIFO.
For more details, refer SODIMM Edge connector pins 125, 138, 141, & 147 on Table 5.
2.6.18 GPIO Interface
Most of the i.MX6 CPU Pins which are connected to SODIMM Edge connector can be configured as GPIO with
interrupt capable (if not used as other interface). i.MX6 CPU GPIO controller provides dedicated general-purpose
pins that can be configured as either inputs or outputs. When configured as an output, it is possible to write to an
internal register to control the state driven on the output pin. When configured as an input, it is possible to detect
the state of the input by reading the state of an internal register. In addition, the GPIO peripheral can produce Core
interrupts.
2.6.19 JTAG Interface
i.MX6 SODIMM SOM supports one JTAG interface on SODIMM Edge Connector. i.MX6 CPU implements JTAG
Security modes internal to System JTAG Controller. The System JTAG Controller provides debug and test control with
the maximum security. The test access port is designed to support features compatible with the IEEE Standard
1149.1 v2001 (JTAG). The SJC module of the processor provides the bridge between external development and test
instrumentation and the internal JTAG-accessible debug and test resources.
For more details, refer SODIMM Edge connector pins 191, 193, 195, 197 & 199 on Table 5.
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i.MX6 SODIMM SOM Hardware User Guide
2.6.20 Power Input
i.MX6 SODIMM SOM works with single 3.3V power input (VIN_3V3) from SODIMM Edge connector and generates all
other required powers internally On-SOM itself. i.MX6 SODIMM SOM uses VRTC_3V0 coin cell power input from
SODIMM Edge connector to i.MX6 CPU’s RTC controller for real time clock (when VIN_3V3 is off).
For more details, refer SODIMM Edge connector pins 20, 32, 46, 60, 72, 88, 106, 124, 142, 160, 180 & 192 for 3.3V
power input (VIN_3V3) and pin 183 for VRTC_3V0 on Table 5.
2.6.21 Reset Button Input
i.MX6 SODIMM SOM supports reset button input on SODIMM Edge connector. Reset button input from SODIMM
Edge connector is the active low signal which is connected to i.MX6 CPU’s POR pin in i.MX6 SODIMM SOM. This pin
can be used to reset the i.MX6 CPU by connecting push button in the carrier board.
For more details, refer SODIMM Edge connector pin 187 on Table 5.
2.6.22 Power Button Input
i.MX6 SODIMM SOM supports PWRBTN# input from Edge connector which is the active low signal and connected to
i.MX6 CPU’s ONOFF pin. This pin can be used to On/Off the i.MX6 CPU by connecting push button in the carrier
board. When the board power is On, a button press between 750ms to 5s will send an interrupt to core to request
software to bring down the i.MX6 safely (if software supports). Otherwise, button press greater than 5s results in a
direct hardware power down which is applicable when software is unable to power Off the device. When the i.MX6
CPU power supply is Off, a button press greater in duration than 750ms asserts an output signal to request power
from a power IC to power up the i.MX6 CPU.
For more details, refer SODIMM Edge connector pin 196 on Table 5.
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i.MX6 SODIMM SOM Hardware User Guide
Table 5: 200-Pin PCB Edge Connector Pin Assignment
Pin
No.
1
2
SODIMM Edge Connector
Pin Name
GND
GPHY_ATXRXM
i.MX6 Ball Name/
Pin Number
NA
NA
Signal Type/
Termination
Power
IO, DIFF
3
4
5
6
7
VDVDH_GPHY
GPHY_ATXRXP
GND
GPHY_BTXRXM
UART1_RXD(SD3_DAT6)
IO, DIFF
Power
IO, DIFF
I, 3.3V CMOS
8
9
GPHY_BTXRXP
UART1_TXD(SD3_DAT7)
IO, DIFF
O, 3.3V CMOS
Ethernet receive differential pair 1 positive.
UART1 serial data transmitter.
10
GPIO1_IO21(SD1_DAT3)
IO, 3.3V CMOS
General Purpose Input/Output.
11
12
13
14
15
16
17
18
GPHY_LINK_LED2
GPHY_ACTIVITY_LED1
GND
GPHY_CTXRXM
GPHY_DTXRXM
GPHY_CTXRXP
GPHY_DTXRXP
I2C1_SCL(EIM_D21)
NA
NA
NA
NA
SD3_DAT6/
E13
NA
SD3_DAT7/
F13
SD1_DAT3/
F18
NA
NA
NA
NA
NA
NA
NA
EIM_D21/
H20
Ground.
Ethernet transmit differential pair 0
negative.
NC.
Ethernet transmit differential pair 0 positive.
Ground.
Ethernet receive differential pair 1 negative.
UART1 serial data receiver.
O, 3.3V CMOS
O, 3.3V CMOS
Power
IO, DIFF
IO, DIFF
IO, DIFF
IO, DIFF
O, 3.3V OD/
4.7K PU
19
I2C1_SDA(EIM_D28)
EIM_D28/
G23
IO, 3.3V OD/
4.7K PU
20
21
VIN_3V3
HDMI_D0P
I, 3.3V Power
O, TMDS
22
HDMI_D1P
O, TMDS
HDMI differential data lane 1 positive.
23
HDMI_D0M
O, TMDS
HDMI differential data lane 0 negative.
24
HDMI_D1M
O, TMDS
HDMI differential data lane 1 negative.
25
HDMI_HPD
I, 3.3V CMOS
HDMI Hot plug detect.
26
HDMI_D2P
NA
HDMI_D0P/
K6
HDMI_D1P/
J4
HDMI_D0M/
K5
HDMI_D1M/
J3
HDMI_HPD/
K1
HDMI_D2P/
K4
Ethernet link status LED.
Ethernet speed status LED.
Ground.
Ethernet receive differential pair 2 negative.
Ethernet receive differential pair 3 negative.
Ethernet receive differential pair 2 positive.
Ethernet receive differential pair 3 positive.
I2C1 Clock signal.
Note: I2C1_SCL(EIM_D21) is also connected
to On-SOM PMIC.
I2C1 Data signal.
Note: I2C1_SDA(EIM_D28) is also connected
to On-SOM PMIC.
Supply Voltage.
HDMI differential data lane 0 positive.
O, TMDS
HDMI differential data lane 2 positive.
iWave Systems Technologies Pvt. Ltd.
Description
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i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
27
28
SODIMM Edge Connector
Pin Name
GND
HDMI_D2M
i.MX6 Ball Name/
Pin Number
NA
HDMI_D2M/
K3
HDMI_CLKP/
J6
NANDF_D3/
D17
HDMI_CLKM/
J5
NA
NANDF_WP_B/
E15
NANDF_D6/
E17
EIM_A25/
H19
NANDF_CS0/
F15
NANDF_D2/
F16
CSI0_DAT18/
M6
EIM_D30/
J20
NA
NA
Signal Type/
Termination
Power
O, TMDS
Ground.
HDMI differential data lane 2 negative.
29
HDMI_CLKP
O, TMDS
HDMI differential clock positive.
30
GPIO2_IO03(NANDF_D3)
IO, 3.3V CMOS
General Purpose Input/Output.
31
HDMI_CLKM
O, TMDS
HDMI differential clock negative.
32
33
VIN_3V3
GPIO6_IO09(NANDF_WP_B)
I, 3.3V Power
IO, 3.3V CMOS
Supply Voltage.
General Purpose Input/Output.
34
GPIO2_IO06(NANDF_D6)
IO, 3.3V CMOS
General Purpose Input/Output.
35
GPIO5_IO02(EIM_A25)
IO, 3.3V CMOS
General Purpose Input/Output.
36
GPIO6_IO11(NANDF_CS0)
IO, 3.3V CMOS
General Purpose Input/Output.
37
GPIO2_IO02(NANDF_D2)
IO, 3.3V CMOS
General Purpose Input/Output.
38
UART5_RTS_B(CSI0_DAT18)
I, 3.3V CMOS
Parallel camera data 6.
39
USB_H1_OC(EIM_D30)
I, 3.3V CMOS
Over current sense for USB Host Port 1.
40
41
GND
GND
Power
Power
Ground.
Ground.
42
GPIO1_IO20(SD1_CLK)
SD1_CLK/
D20
NANDF_D4/
A19
NANDF_CLE/
C15
SD1_DAT0/
A21
NA
IO, 3.3V CMOS
General Purpose Input/Output.
43
GPIO2_IO04(NANDF_D4)
IO, 3.3V CMOS
General Purpose Input/Output.
44
GPIO6_IO07(NANDF_CLE)
IO, 3.3V CMOS
General Purpose Input/Output.
45
GPIO1_IO16(SD1_DAT0)
IO, 3.3V CMOS
General Purpose Input/Output.
46
VIN_3V3
I, 3.3V Power
Supply Voltage.
47
GPIO6_IO08(NANDF_ALE)
NANDF_ALE/
A16
IO, 3.3V CMOS
LVDS0_TX0_N
LVDS0_TX0_N/
U2
O, 2.5V LVDS
General Purpose Input/Output.
Note: Same signal is optionally connected to
Reset input of On-SOM eMMC through
resistor and default not populated.
LVDS primary channel differential pair 0
negative.
48
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Description
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i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
49
SODIMM Edge Connector
Pin Name
GPIO2_IO01(NANDF_D1)
50
LVDS0_TX0_P
51
52
GND
LVDS0_TX1_N
53
LVDS0_TX2_N
54
LVDS0_TX1_P
55
LVDS0_TX2_P
56
LVDS0_TX3_N
57
LVDS0_CLK_N
58
LVDS0_TX3_P
59
LVDS0_CLK_P
60
61
VIN_3V3
AUD4_RXD(SD2_DAT0)
62
eCSPI2_SS1(EIM_LBA)
63
eCSPI2_MISO(CSI0_DAT10)
64
CCM_CLKO1(GPIO_19)
65
66
GND
eCSPI2_SCLK(CSI0_DAT8)
67
AUD4_TXD(SD2_DAT2)
68
GPIO6_IO10(NANDF_RB0)
i.MX6 Ball Name/
Pin Number
NANDF_D1/
C17
NALVDS0_TX0_P/
U1
NA
LVDS0_TX1_N/
U4
LVDS0_TX2_N/
V2
LVDS0_TX1_P/
U3
LVDS0_TX2_P/
V1
LVDS0_TX3_N/
W2
LVDS0_CLK_N/
V4
LVDS0_TX3_P/
W1
LVDS0_CLK_P/
V3
NA
SD2_DAT0/
A22
EIM_LBA/
K22
Signal Type/
Termination
IO, 3.3V CMOS
CSI0_DAT10/
M1
GPIO_19/
P5
NA
CSI0_DAT8/
N6
SD2_DAT2/
A23
NANDF_RB0/
B16
I, 3.3V CMOS
SPI2 chip select 1.
Important Note: This signal is also used for
i.MX6 CPU bootstrap setting on SOM and so
no external loads or pull-up/pull-down
resistors to be connected to this pin which
will change the boot configuration.
SPI2 Master Input Slave Output.
O, 3.3V CMOS
Observability clock 1 output.
Power
O, 3.3V CMOS
Ground.
SPI2 clock signal.
O, 3.3V CMOS
Audio Transmit data.
IO, 3.3V CMOS
General Purpose Input/Output.
iWave Systems Technologies Pvt. Ltd.
O, 2.5V LVDS
Power
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
O, 2.5V LVDS
I, 3.3V Power
I, 3.3V CMOS
O, 3.3V CMOS/
10K PD
Description
General Purpose Input/Output.
LVDS primary channel
positive.
Ground.
LVDS primary channel
negative.
LVDS primary channel
negative.
LVDS primary channel
positive.
LVDS primary channel
positive.
LVDS primary channel
negative.
LVDS primary channel
negative.
LVDS primary channel
positive.
LVDS primary channel
positive.
Supply Voltage.
Audio receive data.
differential pair 0
differential pair 1
differential pair 2
differential pair 1
differential pair2
differential pair 3
differential clock
differential pair 3
differential clock
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i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
69
SODIMM Edge Connector
Pin Name
GPIO6_IO14(NANDF_CS1)
i.MX6 Ball Name/
Pin Number
NANDF_CS1/
C16
CSI0_DAT9/
N5
EIM_D24/
F22
NA
NANDF_D0/
A18
USB_OTG_CHD_B
B8
CSI0_DAT19/
L6
NANDF_D5/
B18
GPIO_1/
T4
NANDF_D7/
C18
NA
DI0_PIN4/
P25
USB_OTG_DP/
A6
SATA_TXP/
A12
70
eCSPI2_MOSI(CSI0_DAT9)
71
eCSPI2_SS2(EIM_D24)
72
73
VIN_3V3
GPIO2_IO00(NANDF_D0)
74
USB_OTG_CHD_B
75
UART5_CTS_B(CSI0_DAT19)
76
GPIO2_IO05(NANDF_D5)
77
USBOTG_ID(GPIO_1)
78
GPIO2_IO07(NANDF_D7)
79
80
GND
GPIO4_IO20(DI0_PIN4)
81
USB_OTG_DP
82
SATA_TXP
83
USB_OTG_DN
84
SATA_TXM
85
SATA_RXP
SATA_RXP/
B14
86
GPIO6_IO31(EIM_BCLK)
87
SATA_RXM
EIM_BCLK/
N22
SATA_RXM/
A14
88
VIN_3V3
USB_OTG_DN/
B6
SATA_TXM/
B12
NA
iWave Systems Technologies Pvt. Ltd.
Signal Type/
Termination
IO, 3.3V CMOS
General Purpose Input/Output.
O, 3.3V CMOS
SPI2 Master Output Slave Input.
O, 3.3V CMOS
SPI2 Chip select signal.
I, 3.3V Power
IO, 3.3V CMOS
Supply Voltage.
General Purpose Input/Output.
O, 3.3V CMOS
USB Charge Detect.
I, 3.3V CMOS
Parallel camera0 data 7.
IO, 3.3V CMOS
General Purpose Input/Output.
I, 3.3V CMOS
USB OTG ID to identify Host & Device.
IO, 3.3V CMOS
General Purpose Input/Output.
Power
IO, 3.3V
CMOS
IO, DIFF
Ground.
General Purpose Input/Output.
O, DIFF/
0.01uF AC
coupled
IO, DIFF
SATA0 transmit output differential positive.
O, DIFF/
0.01uF AC
coupled
I, DIFF/
0.01uF AC
coupled
IO, 3.3V
CMOS
I, DIFF/
0.01uF AC
coupled
I, 3.3V Power
SATA0 transmit output differential negative.
Description
USB OTG data positive.
USB OTG data negative.
SATA0 receive input differential positive.
General Purpose Input/Output.
SATA0 receive input differential negative.
Supply Voltage.
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i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
89
SODIMM Edge Connector
Pin Name
AUD4_TXFS(SD2_DAT1)
90
AUD4_TXC(SD2_DAT3)
91
AUD4_RXC(SD2_CMD)
92
AUD4_RXFS(SD2_CLK)
93
GPIO6_IO01(CSI0_DAT15)
94
UART1_RTS_B(EIM_D20)
95
96
GND
GPIO6_IO00(CSI0_DAT14)
97
UART1_CTS_B(EIM_D19)
98
UART4_TXD(KEY_COL0)
99
UART4_RXD(KEY_ROW0)
100
UART4_CTS_B(CSI0_DAT17)
101
UART4_RTS_B(CSI0_DAT16)
102
UART5_TXD(KEY_COL1)
103
UART5_RXD(KEY_ROW1)
104
GPIO5_IO31(CSI0_DAT13)
105
eCSPI2_SS3(EIM_D25)
106
VIN_3V3
107
SD3_DAT0
108
SD3_CMD
109
SD3_CLK
110
eCSPI2_SS0(CSI0_DAT11)
i.MX6 Ball Name/
Pin Number
SD2_DAT1/
E20
SD2_DAT3/
B22
SD2_CMD/
F19
SD2_CLK/
C21
CSI0_DAT15/
M5
EIM_D20/
G20
NA
CSI0_DAT14/
M4
EIM_D19/
G21
KEY_COL0/
W5
KEY_ROW0/
V6
CSI0_DAT17/
L3
CSI0_DAT16/
L4
KEY_COL1/
U7
KEY_ROW1/
U6
CSI0_DAT13/
L1
EIM_D25/
G22
NA
Signal Type/
Termination
O, 3.3V CMO
Audio transmit frame synchronization.
O, 3.3V CMOS
Audio transmit clock.
I, 3.3V CMOS
Audio receive clock.
I, 3.3V CMOS
Audio receive frame synchronization.
I, 3.3V CMOS
Parallel camera0 data 3.
I, 3.3V CMOS
UART1 ready to send data.
Power
I, 3.3V CMOS
Ground.
Parallel camera0 data 2.
O, 3.3V CMOS
UART1 clear to send data.
O, 3.3V CMOS
UART4 serial data transmitter.
I, 3.3V CMOS
UART4 serial data receiver.
I, 3.3V CMOS
Parallel camera0 data 5.
I, 3.3V CMOS
Parallel camera0 data 4.
O, 3.3V CMOS
UART5 serial data transmitter.
I, 3.3V CMOS
UART5 serial data receiver.
I, 3.3V CMOS
Parallel camera0 data 1.
O, 3.3V CMOS
I, 3.3V Power
General Purpose Input/Output.
Assigned for SD3 Card detect.
Supply Voltage.
SD3_DAT0/
E14
SD3_CMD/
B13
IO, 3.3V CMOS
SD3 Data0.
IO, 3.3V CMOS
SD3 command.
SD3_CLK/
D14
CSI0_DAT11/
M3
O, 3.3V CMOS
SD3 clock.
O, 3.3V CMOS
SPI2 Chip select 2.
iWave Systems Technologies Pvt. Ltd.
Description
REL 1.2
Page 29 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
111
SODIMM Edge Connector
Pin Name
SD3_DAT1
i.MX6 Ball Name/
Pin Number
SD3_DAT1/
F14
SD3_DAT2/
A15
NA
SD3_DAT3/
B15
GPIO_6/
T3
GPIO_3/
R7
EIM_D27/
E25
EIM_D26/
E24
CSI0_PIXCLK/
P1
CSI0_DAT12/
M2
CSI0_VSYNC/
N2
GPIO_18/
P6
CSI0_MCLK/
P4
Signal Type/
Termination
IO, 3.3V CMOS
SD3 Data1.
112
SD3_DAT2
IO, 3.3V CMOS
SD3 Data2.
113
114
GND
SD3_DAT3
Power
IO, 3.3V CMOS
Ground.
SD3 Data3.
115
I2C3_SDA(GPIO_6)
IO, 3.3V OD/
4.7K PU
O, 3.3V OD/
4.7K PU
I, 3.3V CMOS
I2C3 data.
116
I2C3_SCL(GPIO_3)
117
UART2_RXD(EIM_D27)
118
UART2_TXD(EIM_D26)
O, 3.3V CMOS
UART2 serial data transmitter.
119
GPIO5_IO18(CSI0_PIXCLK)
I, 3.3V CMOS
Parallel camera0 PIXCLK.
120
GPIO5_IO30(CSI0_DAT12)
I, 3.3V CMOS
Parallel camera0 data 0.
121
GPIO5_IO21(CSI0_VSYNC)
I, 3.3V CMOS
Parallel camera0 VSYNC.
122
GPIO7_IO13(GPIO_18)
IO, 3.3V CMOS
General Purpose Input/Output.
123
GPIO5_IO19(CSI0_MCLK)
I, 3.3V CMOS
Parallel Camera0 HSYNC.
124
VIN_3V3
NA
I, 3.3V Power
Supply Voltage.
125
PWM2_OUT(SD1_DAT2)
O, 3.3V CMOS
Pulse Width Modulation 2 Output.
126
GPIO5_IO20(CSI0_DATA_EN)
I, 3.3V CMOS
Parallel Camera0 Data Enable.
127
PCIE_TXP
SD1_DAT2/
E19
CSI0_DATA_EN/
P3
PCIE_TXP/
B3
PCIe differential transmit line positive.
128
PCIE_RXP
O, DIFF/
0.1uf AC
coupled
O, DIFF
129
PCIE_TXM
PCIe differential transmit line negative.
130
PCIE_RXM
O, DIFF/
0.1uf AC
coupled
O, DIFF
131
GND
Power
Ground.
PCIE_RXP/
B2
PCIE_TXM/
A3
PCIE_RXM/
B1
NA
iWave Systems Technologies Pvt. Ltd.
Description
I2C3 clock.
UART2 serial data receiver.
PCIe differential receive line positive
PCIe differential receive line negative.
REL 1.2
Page 30 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
132
SODIMM Edge Connector
Pin Name
GPIO7_IO11(GPIO_16)
133
GPIO7_IO12(GPIO_17)
134
GPIO1_IO02(GPIO_2)
135
PCIE_REFCLK_DP(CLK1_P)
136
GPIO4_IO13(KEY_ROW3)
137
PCIE_REFCLK_DM(CLK1_N)
138
PWM1_OUT(GPIO_9)
139
GPIO4_IO12(KEY_COL3)
140
USB_H1_PWR(GPIO_0)
141
PWM4_OUT(SD1_CMD)
142
143
VIN_3V3
DI0_PIN3
144
DI0_PIN2
145
DI0_DISP_CLK
146
DI0_PIN15
147
PWM3_OUT(SD1_DAT1)
148
DISP0_DAT16
149
DISP0_DAT17
150
DISP0_DAT18
151
152
GND
DISP0_DAT19
i.MX6 Ball Name/
Pin Number
GPIO_16/
R2
GPIO_17/
R1
GPIO_2/
T1
CLK1_P/
D7
KEY_ROW3/
T7
CLK1_N/
C7
GPIO_9/
T2
KEY_COL3/
U5
GPIO_0/
T5
Signal Type/
Termination
O, 3.3V CMOS
SD1_CMD/
B21
NA
DI0_PIN3/
N20
DI0_PIN2/
N25
DI0_DISP_CLK/
N19
DI0_PIN15/
N21
SD1_DAT1/
C20
DISP0_DAT16/
T21
DISP0_DAT17/
U24
DISP0_DAT18/
V25
NA
DISP0_DAT19/
U23
iWave Systems Technologies Pvt. Ltd.
IO, 3.3V CMOS
I, 3.3V CMOS
Description
General Purpose Input/Output.
Assigned for PCIe RESET.
General Purpose Input/Output.
O, DIFF
General Purpose Input/Output.
Assigned for PCIe WAKE.
PCIe differential reference clock positive.
IO, 3.3V CMOS
General Purpose Input/Output.
O, DIFF
PCIe differential reference clock negative.
O, 3.3V CMOS
Pulse Width Modulation 1 Output.
IO, 3.3V CMOS
General Purpose Input/Output.
O, 3.3V CMOS
O, 3.3V CMOS
General Purpose Input/Output.
Assigned for USB Host1 Power enable signal
to control USB Host1 VBUS voltage.
Pulse Width Modulation 4 Output.
I, 3.3V Power
O, 3.3V CMOS
Supply Voltage.
Parallel LCD VSYNC.
O, 3.3V CMOS
Parallel LCD HSYNC.
O, 3.3V CMOS
Parallel LCD Clock.
O, 3.3V CMOS
Parallel LCD Enable.
O, 3.3V CMOS
Pulse Width Modulation 3 Output.
O, 3.3V CMOS
Parallel LCD data 16 (Red data0).
O, 3.3V CMOS
Parallel LCD data 17 (Red data1).
O, 3.3V CMOS
Parallel LCD data 18 (Red data2).
Power
O, 3.3V CMOS
Ground.
Parallel LCD data 19 (Red data3).
REL 1.2
Page 31 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
153
SODIMM Edge Connector
Pin Name
DISP0_DAT20
154
DISP0_DAT21
155
DISP0_DAT22
156
DISP0_DAT23
157
DISP0_DAT8
158
DISP0_DAT9
159
DISP0_DAT10
160
161
VIN_3V3
DISP0_DAT11
162
DISP0_DAT12
163
DISP0_DAT13
164
DISP0_DAT14
165
DISP0_DAT15
166
DISP0_DAT0
167
DISP0_DAT1
168
DISP0_DAT2
169
170
GND
DISP0_DAT3
171
DISP0_DAT4
172
DISP0_DAT5
173
DISP0_DAT6
174
DISP0_DAT7
i.MX6 Ball Name/
Pin Number
DISP0_DAT20/
U22
DISP0_DAT21/
T20
DISP0_DAT22/
V24
DISP0_DAT23/
W24
DISP0_DAT8/
R22
DISP0_DAT9/
T25
DISP0_DAT10/
R21
NA
DISP0_DAT11/
T23
DISP0_DAT12/
T24
DISP0_DAT13/
R20
DISP0_DAT14/
U25
DISP0_DAT15/
T22
DISP0_DAT0/
P24
DISP0_DAT1/
P22
DISP0_DAT2/
P23
NA
DISP0_DAT3/
P21
DISP0_DAT4/
P20
DISP0_DAT5/
R25
DISP0_DAT6/
R23
DISP0_DAT7/
R24
iWave Systems Technologies Pvt. Ltd.
Signal Type/
Termination
O, 3.3V CMOS
Parallel LCD data 20 (Red data4).
O, 3.3V CMOS
Parallel LCD data 21 (Red data5).
O, 3.3V CMOS
Parallel LCD data 22 (Red data6).
O, 3.3V CMOS
Parallel LCD data 23 (Red data7).
O, 3.3V CMOS
Parallel LCD data 8 (Green data0).
O, 3.3V CMOS
Parallel LCD data 9 (Green data1).
O, 3.3V CMOS
Parallel LCD data 10 (Green data2).
I, 3.3V Power
O, 3.3V CMOS
Supply Voltage.
Parallel LCD data 11 (Green data3).
O, 3.3V CMOS
Parallel LCD data 12 (Green data4).
O, 3.3V CMOS
Parallel LCD data 13 (Green data5).
O, 3.3V CMOS
Parallel LCD data 14 (Green data6).
O, 3.3V CMOS
Parallel LCD data 15 (Green data7).
O, 3.3V CMOS/
Parallel LCD data 0 (Blue data0).
O, 3.3V CMOS
Parallel LCD data 1 (Blue data1).
O, 3.3V CMOS
Parallel LCD data 2 (Blue data2).
Power
O, 3.3V CMOS
Ground.
Parallel LCD data 3 (Blue data3).
O, 3.3V CMOS
Parallel LCD data 4 (Blue data4).
O, 3.3V CMOS/
Parallel LCD data 5 (Blue data5).
O, 3.3V CMOS
Parallel LCD data 6 (Blue data6).
O, 3.3V CMOS
Parallel LCD data 7 (Blue data7).
Description
REL 1.2
Page 32 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
175
SODIMM Edge Connector
Pin Name
CAN2_RX(KEY_ROW4)
i.MX6 Ball Name/
Pin Number
KEY_ROW4/
V5
GPIO_8/
R5
KEY_COL4/
T6
GPIO_7/
R3
KEY_COL2/
W6
Signal Type/
Termination
I, 3.3V CMOS
Receive input for CAN2 bus.
176
CAN1_RX(GPIO_8)
I, 3.3V CMOS
Receive input for CAN1 bus.
177
CAN2_TX(KEY_COL4)
O, 3.3V CMOS
Transmit output for CAN2 bus.
178
CAN1_TX(GPIO_7)
O, 3.3V CMOS
Transmit output for CAN1 bus.
179
GPIO4_IO10(KEY_COL2)
IO, 3V CMOS
NA
KEY_ROW2/
W4
BOOT_MODE0/
C12
I, 3.3V Power
IO, 3V CMOS
General Purpose Input/Output.
Note: KEY_COL2 is connected to this pin
through resistor and default populated.
KEY_COL2 is also connected to Edge
connector pin196 through resistor and
default not populated.
Note: CPU_ON_OFF is connected to this pin
through resistor and default not populated.
CPU_ON_OFF is also connected to Edge
connector pin196 through resistor and
default populated.
Supply Voltage.
General Purpose Input/Output.
180
181
VIN_3V3
GPIO4_IO11(KEY_ROW2)
182
BOOT_MODE0
183
184
VRTC_3V0
BOOT_MODE1
NA
BOOT_MODE1/
F12
I, 3V Power
I, 3.3V CMOS/
4.7K PU
185
186
GND
GND
NA
NA
Power
Power
iWave Systems Technologies Pvt. Ltd.
I, 3.3V CMOS/
4.7K PU
Description
Boot Mode Select bit0.
Important Note: This pin is directly
connected to i.MX6 CPU’s BOOT_MODE0 pin
with On-SOM pullup and so don’t add any
external pullup in carrier board on this pin.
Make sure to use this pin in carrier board to
select desired boot mode by driving only low
if required.
3V backup coin cell input for RTC.
Boot Mode Select bit1.
Important Note: This pin is directly
connected to i.MX6 CPU’s BOOT_MODE1 pin
with On-SOM pullup and so don’t add any
external pullup in carrier board on this pin.
Make sure to use this pin in carrier board to
select desired boot mode by driving only low
if required.
Ground.
Ground.
REL 1.2
Page 33 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
187
SODIMM Edge Connector
Pin Name
n_RST_OUT
i.MX6 Ball Name/
Pin Number
POR_B/
C11
Signal Type/
Termination
I, 3V CMOS/
10K PU
188
USB_H1_DP
IO, DIFF
189
GPIO1_IO04_BRD_CFG2(GPI
O_4)
USB_H1_DP/
E10
GPIO_4/
R6
190
USB_H1_DN
IO, DIFF
191
JTAG_TDO
O, 3.3V CMOS
JTAG Test Data Output.
192
193
VIN_3V3
JTAG_TRSTB
I, 3.3V Power
I, 3.3V CMOS
Supply Voltage.
JTAG Test Reset.
194
GPIO1_IO05_BRD_CFG3(GPI
O_5)
USB_H1_DN/
F10
JTAG_TDO/
G6
NA
JTAG_TRSTB/
C2
GPIO_5/
R4
General Purpose Input/Output.
Note: GPIO_4 is connected to this pin
through resistor and default populated.
USB Host Port 1 data negative.
IO, 3.3V CMOS
195
JTAG_TDI
I, 3.3V CMOS
196
CPU_ON_OFF
JTAG_TDI/
G5
ONOFF/
D12
General Purpose Input/Output.
Note: GPIO_5 is connected to this pin
through resistor and default populated.
JTAG Test Data Input.
197
JTAG_TCK
I, 3.3V CMOS
198
GND
JTAG_TCK/
H5
NA
CPU_ON_OFF signal.
Note: CPU_ON_OFF is connected to this pin
through resistor and default populated.
CPU_ON_OFF is also connected to Edge
connector pin179 through resistor and
default not populated.
Note: ENET_RX_ER is connected to this pin
through resistor and default not populated.
Note: KEY_COL2 is connected to this pin
through resistor and default not populated.
KEY_COL2 is also connected to Edge
connector pin179 through resistor and
default populated.
JTAG Test Clock.
Power
Ground.
iWave Systems Technologies Pvt. Ltd.
IO, 3.3V CMOS
I, 3.3V CMOS
Description
Active low reset button input.
Important Note: This reset input is connected
to i.MX6 CPU’s POR input with On-SOM
pullup and so don’t add any external pullup
in carrier board on this pin.
Note: NANDF_CS3 is optionally connected to
this pin through resistor and default not
populated.
USB Host Port 1 data positive.
REL 1.2
Page 34 of 56
i.MX6 SODIMM SOM Hardware User Guide
Pin
No.
199
SODIMM Edge Connector
Pin Name
JTAG_TMS
200
VBUS_5V
i.MX6 Ball Name/
Pin Number
JTAG_TMS/
C3
USB_OTG_VBUS/
E9 &
USB_H1_VBUS/
D10
iWave Systems Technologies Pvt. Ltd.
Signal Type/
Termination
I, 3.3V CMOS
I, Power 5V
Description
JTAG Test Mode Select.
USB VBUS Power.
Important Note: Recommended to connect
always available 5V power on this pin in
carrier board.
REL 1.2
Page 35 of 56
i.MX6 SODIMM SOM Hardware User Guide
2.7
i.MX6 Pin Multiplexing on SODIMM Edge
The i.MX6 CPU’s IO pins have many alternate functions and can be configured to any one of the alternate functions based on the requirement. Also most of the i.MX6
CPU’s IO pins can be configured as GPIO if required. The below table provides the details of i.MX6 CPU pin connections to the SOM edge connector with selected pin
function and available alternate functions. This table has been prepared by referring NXP’s i.MX6 Applications Processor Reference Manual.
Important Note: It is strongly recommended to use the pin function same as selected in the i.MX6 SOIDMM SOM Edge connector for iWave’s BSP reusability and to have
compatible SODIMM modules in future for upgradability.
Table 6: IOMUX Configuration of i.MX6 SODIMM SOM Edge Connector interfaces
Interface/
Function
SODIMM
Edge Pin No
182
Control
Signals
184
187
107
111
112
SD
114
108
109
105
i.MX6 CPU
Pad Name
BOOT_MOD
E0
BOOT_MOD
E1
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
POR_B
SRC_POR_B
SD3_DAT0
SD3_DATA0
SD3_DAT1
SD3_DATA1
SD3_DAT2
SD3_DAT3
SD3_CMD
SD3_CLK
EIM_D25
Default/
Reset State
SRC_BOOT_
MODE0
SRC_BOOT_
MODE1
UART1_CTS_
B
UART1_RTS_
B
FLEXCAN2_T
X
FLEXCAN2_R
X
SD3_DATA2
SD3_DATA3
SD3_CMD
SD3_CLK
EIM_DATA2
5
iWave Systems Technologies Pvt. Ltd.
UART3_CTS_
B
UART2_CTS_
B
UART2_RTS_
B
ECSPI4_SS3
FLEXCAN1_T
X
FLEXCAN1_R
X
UART3_RX_
DATA
ECSPI1_SS3
ECSPI2_SS3
GPIO7_IO04
GPIO7_IO04
GPIO7_IO05
GPIO7_IO05
GPIO7_IO06
GPIO7_IO06
GPIO7_IO07
GPIO7_IO07
GPIO7_IO02
GPIO7_IO02
GPIO7_IO03
GPIO7_IO03
GPIO3_IO25
AUD5_RXC
UART1_DSR
_B
EPDC_SDCE8
REL 1.2
Page 36 of 56
GPIO3_IO25
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
128
PCIE_RXP
PCIE_RX_P
130
PCIE_RXM
PCIE_RX_N
127
PCIE_TXP
PCIE_TX_P
129
PCIE_TXM
PCIE_TX_N
135
CLK1_P
137
CLK1_N
134
GPIO_2
133
GPIO_17
82
SATA_TXP
84
SATA_TXM
85
SATA_RXP
87
SATA_RXM
74
USB_OTG_C
HD_B
77
GPIO_1
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
PCIe
XTALOSC_CL
K1_P
XTALOSC_CL
K1_N
ESAI_TX_FS
ESAI_TX0
KEY_ROW6
ENET_1588_
EVENT3_IN
CCM_PMIC_
READY
GPIO1_IO02
SDMA_EXT_
EVENT0
SPDIF_OUT
SD2_WP
MLB_DATA
GPIO1_IO02
GPIO7_IO12
GPIO7_IO12
SATA_PHY_T
X_P
SATA_PHY_T
X_N
SATA_PHY_R
X_P
ATA_PHY_RX
_N
USB_OTG_C
HD_B
SATA
USB
OTG2.0
81
83
Default/
Reset State
ESAI_RX_CLK
WDOG2_B
KEY_ROW5
USB_OTG_ID
PWM2_OUT
GPIO1_IO01
SD1_CD_B
GPIO1_IO01
USB_OTG_D
P
USB_OTG_D
N
iWave Systems Technologies Pvt. Ltd.
USB_OTG_D
P
USB_OTG_D
N
REL 1.2
Page 37 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
USB2.0
Host
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
39
EIM_D30
EIM_DATA3
0
IPU1_DISP1_
DATA21
IPU1_DI0_PI
N11
UART3_CTS_
B
GPIO3_IO30
USB_H1_OC
140
GPIO_0
CCM_CLKO1
IPU1_CSI0_D
ATA03
ASRC_EXT_C
LK
EPIT1_OUT
GPIO1_IO00
USB_H1_PW
R
188
USB_H1_DP
USB_H1_DP
190
USB_H1_DN
USB_H1_DN
120
CSI0_DAT12
104
CSI0_DAT13
96
CSI0_DAT14
93
CSI0_DAT15
101
CSI0_DAT16
100
CSI0_DAT17
38
CSI0_DAT18
75
CSI0_DAT19
119
CSI0_PIXCLK
123
CSI0_MCLK
121
CSI0_VSYNC
126
CSI0_DATA_
EN
Camera
IPU1_CSI0_D
ATA12
IPU1_CSI0_D
ATA13
IPU1_CSI0_D
ATA14
IPU1_CSI0_D
ATA15
IPU1_CSI0_D
ATA16
IPU1_CSI0_D
ATA17
IPU1_CSI0_D
ATA18
IPU1_CSI0_D
ATA19
IPU1_CSI0_P
IXCLK
IPU1_CSI0_H
SYNC
IPU1_CSI0_V
SYNC
IPU1_CSI0_D
ATA_EN
iWave Systems Technologies Pvt. Ltd.
KEY_COL5
EIM_DATA0
8
EIM_DATA0
9
EIM_DATA1
0
EIM_DATA1
1
EIM_DATA1
2
EIM_DATA1
3
EIM_DATA1
4
EIM_DATA1
5
UART4_TX_
DATA
UART4_RX_
DATA
UART5_TX_
DATA
UART5_RX_
DATA
UART4_RTS_
B
UART4_CTS_
B
UART5_RTS_
B
UART5_CTS_
B
GPIO5_IO30
GPIO5_IO31
GPIO6_IO00
GPIO6_IO01
GPIO6_IO02
GPIO6_IO03
GPIO6_IO04
EIM_DATA0
1
EIM_DATA0
0
ALT8
ALT9
EPDC_SDOEZ
SNVS_VIO_5
GPIO5_IO19
GPIO5_IO21
GPIO5_IO20
Default/
Reset State
GPIO3_IO30
GPIO1_IO00
ARM_TRACE
09
ARM_TRACE
10
ARM_TRACE
11
ARM_TRACE
12
ARM_TRACE
13
ARM_TRACE
14
ARM_TRACE
15
GPIO5_IO30
GPIO5_IO31
GPIO6_IO00
GPIO6_IO01
GPIO6_IO02
GPIO6_IO03
GPIO6_IO04
GPIO6_IO05
GPIO5_IO18
CCM_CLKO1
ALT7
GPIO6_IO05
ARM_EVENT
O
ARM_TRACE
_CTL
ARM_TRACE
00
ARM_TRACE
_CLK
GPIO5_IO18
GPIO5_IO19
GPIO5_IO21
GPIO5_IO20
REL 1.2
Page 38 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
61
i.MX6 CPU
Pad Name
SD2_DAT0
89
SD2_DAT1
67
Audio
90
91
92
50
48
54
52
55
LVDS
53
58
56
57
59
ALT0
ALT1
SD2_DATA0
ECSPI5_MIS
O
SD2_DATA1
ECSPI5_SS0
SD2_DAT2
SD2_DATA2
SD2_DAT3
ALT2
ALT7
ALT8
ALT9
Default/
Reset State
ALT3
ALT4
ALT5
ALT6
AUD4_RXD
KEY_ROW7
GPIO1_IO15
DCIC2_OUT
EIM_CS2_B
AUD4_TXFS
KEY_COL7
GPIO1_IO14
GPIO1_IO14
ECSPI5_SS1
EIM_CS3_B
AUD4_TXD
KEY_ROW6
GPIO1_IO13
GPIO1_IO13
SD2_DATA3
ECSPI5_SS3
KEY_COL6
AUD4_TXC
GPIO1_IO12
GPIO1_IO12
SD2_CMD
SD2_CMD
ECSPI5_MOS
I
KEY_ROW5
AUD4_RXC
GPIO1_IO11
GPIO1_IO11
SD2_CLK
SD2_CLK
ECSPI5_SCLK
KEY_COL5
AUD4_RXFS
GPIO1_IO10
GPIO1_IO10
GPIO1_IO15
LVDS0_TX0_
P
LVDS0_TX0_
N
LVDS0_TX1_
P
LVDS0_TX1_
N
LVDS0_TX2_
P
LVDS0_TX2_
N
LVDS0_TX3_
P
LVDS0_TX3_
N
LVDS0_CLK_
N
LVDS0_CLK_
P
iWave Systems Technologies Pvt. Ltd.
LVDS0_DATA
0_P
LVDS0_DATA
0_N
LVDS0_DATA
1_P
LVDS0_DATA
1_N
LVDS0_DATA
2_P
LVDS0_DATA
2_N
LVDS0_DATA
3_P
LVDS0_DATA
3_N
LVDS0_CLK_
N
LVDS0_CLK_
P
REL 1.2
Page 39 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
DISP0_RGB
LCD
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
166
DISP0_DAT0
167
DISP0_DAT1
168
DISP0_DAT2
170
DISP0_DAT3
171
DISP0_DAT4
172
DISP0_DAT5
173
DISP0_DAT6
174
DISP0_DAT7
157
DISP0_DAT8
158
DISP0_DAT9
159
161
162
163
164
165
148
DISP0_DAT1
0
DISP0_DAT1
1
DISP0_DAT1
2
DISP0_DAT1
3
DISP0_DAT1
4
DISP0_DAT1
5
DISP0_DAT1
6
ALT0
ALT1
IPU1_DISP0_
DATA00
IPU1_DISP0_
DATA01
IPU1_DISP0_
DATA02
IPU1_DISP0_
DATA03
IPU1_DISP0_
DATA04
IPU1_DISP0_
DATA05
IPU1_DISP0_
DATA06
IPU1_DISP0_
DATA07
IPU1_DISP0_
DATA08
IPU1_DISP0_
DATA09
IPU1_DISP0_
DATA10
IPU1_DISP0_
DATA11
IPU1_DISP0_
DATA12
IPU1_DISP0_
DATA13
IPU1_DISP0_
DATA14
IPU1_DISP0_
DATA15
IPU1_DISP0_
DATA16
IPU2_DISP0_
DATA00
IPU2_DISP0_
DATA01
IPU2_DISP0_
DATA02
IPU2_DISP0_
DATA03
IPU2_DISP0_
DATA04
IPU2_DISP0_
DATA05
IPU2_DISP0_
DATA06
IPU2_DISP0_
DATA07
IPU2_DISP0_
DATA08
IPU2_DISP0_
DATA09
IPU2_DISP0_
DATA10
IPU2_DISP0_
DATA11
IPU2_DISP0_
DATA12
IPU2_DISP0_
DATA13
IPU2_DISP0_
DATA14
IPU2_DISP0_
DATA15
IPU2_DISP0_
DATA16
iWave Systems Technologies Pvt. Ltd.
ALT2
ALT3
ALT4
ECSPI3_SCLK
ALT5
ALT6
ALT7
ALT8
ALT9
Default/
Reset State
GPIO4_IO21
GPIO4_IO21
GPIO4_IO22
GPIO4_IO22
GPIO4_IO23
GPIO4_IO23
ECSPI3_SS0
GPIO4_IO24
GPIO4_IO24
ECSPI3_SS1
GPIO4_IO25
GPIO4_IO25
ECSPI3_MOS
I
ECSPI3_MIS
O
ECSPI3_SS2
AUD6_RXFS
GPIO4_IO26
GPIO4_IO26
ECSPI3_SS3
AUD6_RXC
GPIO4_IO27
GPIO4_IO27
GPIO4_IO28
GPIO4_IO28
ECSPI3_RDY
PWM1_OUT
WDOG1_B
GPIO4_IO29
GPIO4_IO29
PWM2_OUT
WDOG2_B
GPIO4_IO30
GPIO4_IO30
GPIO4_IO31
GPIO4_IO31
GPIO5_IO05
GPIO5_IO05
GPIO5_IO06
GPIO5_IO06
AUD5_RXFS
GPIO5_IO07
GPIO5_IO07
AUD5_RXC
GPIO5_IO08
GPIO5_IO08
ECSPI1_SS1
ECSPI2_SS1
GPIO5_IO09
GPIO5_IO09
ECSPI2_MOS
I
AUD5_TXC
GPIO5_IO10
GPIO5_IO10
SDMA_EXT_
EVENT0
REL 1.2
Page 40 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
149
150
152
153
154
DISP0_RGB
LCD
155
156
145
i.MX6 CPU
Pad Name
DISP0_DAT1
7
DISP0_DAT1
8
DISP0_DAT1
9
DISP0_DAT2
0
DISP0_DAT2
1
DISP0_DAT2
2
DISP0_DAT2
3
DI0_DISP_CL
K
144
DI0_PIN2
143
DI0_PIN3
146
DI0_PIN15
ALT1
ALT2
ALT3
ALT4
ALT5
IPU1_DISP0_
DATA17
IPU1_DISP0_
DATA18
IPU1_DISP0_
DATA19
IPU1_DISP0_
DATA20
IPU1_DISP0_
DATA21
IPU1_DISP0_
DATA22
IPU1_DISP0_
DATA23
IPU1_DI0_DI
SP_CLK
IPU1_DI0_PI
N02
IPU1_DI0_PI
N03
IPU1_DI0_PI
N15
IPU2_DISP0_
DATA17
IPU2_DISP0_
DATA18
IPU2_DISP0_
DATA19
IPU2_DISP0_
DATA20
IPU2_DISP0_
DATA21
IPU2_DISP0_
DATA22
IPU2_DISP0_
DATA23
IPU2_DI0_DI
SP_CLK
IPU2_DI0_PI
N02
IPU2_DI0_PI
N03
IPU2_DI0_PI
N15
ECSPI2_MIS
O
AUD5_TXD
SDMA_EXT_
EVENT1
GPIO5_IO11
ECSPI2_SS0
AUD5_TXFS
AUD4_RXFS
GPIO5_IO12
EIM_CS2_B
GPIO5_IO12
ECSPI2_SCLK
AUD5_RXD
AUD4_RXC
GPIO5_IO13
EIM_CS3_B
GPIO5_IO13
ECSPI1_SCLK
AUD4_TXC
GPIO5_IO14
GPIO5_IO14
AUD4_TXD
GPIO5_IO15
GPIO5_IO15
AUD4_TXFS
GPIO5_IO16
GPIO5_IO16
AUD4_RXD
GPIO5_IO17
GPIO5_IO17
GPIO4_IO16
GPIO4_IO16
AUD6_TXD
GPIO4_IO18
GPIO4_IO18
AUD6_TXFS
GPIO4_IO19
GPIO4_IO19
AUD6_TXC
GPIO4_IO17
GPIO4_IO17
iWave Systems Technologies Pvt. Ltd.
ECSPI1_MOS
I
ECSPI1_MIS
O
ECSPI1_SS0
ALT6
ALT7
ALT8
ALT9
Default/
Reset State
ALT0
GPIO5_IO11
REL 1.2
Page 41 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
HDMI
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
21
HDMI_D0P
23
HDMI_D0M
22
HDMI_D1P
24
HDMI_D1M
26
HDMI_D2P
28
HDMI_D2M
29
HDMI_CLKP
31
HDMI_CLKM
25
HDMI_HPD
66
CSI0_DAT8
70
CSI0_DAT9
63
CSI0_DAT10
110
CSI0_DAT11
62
EIM_LBA
71
EIM_D24
SPI
ALT0
ALT1
IPU1_CSI0_D
ATA08
IPU1_CSI0_D
ATA09
IPU1_CSI0_D
ATA10
IPU1_CSI0_D
ATA11
EIM_DATA0
6
EIM_DATA0
7
AUD3_RXC
ALT2
ALT3
ALT4
ALT5
ECSPI2_SCLK
KEY_COL7
I2C1_SDA
GPIO5_IO26
KEY_ROW7
I2C1_SCL
GPIO5_IO27
ECSPI2_MOS
I
ECSPI2_MIS
O
AUD3_RXFS
ECSPI2_SS0
EIM_LBA
IPU1_DI1_PI
N17
ECSPI2_SS1
EIM_DATA2
4
ECSPI4_SS2
UART3_TX_
DATA
iWave Systems Technologies Pvt. Ltd.
UART1_TX_
DATA
UART1_RX_
DATA
ALT6
GPIO5_IO28
GPIO5_IO29
GPIO2_IO27
ECSPI1_SS2
ECSPI2_SS2
GPIO3_IO24
AUD5_RXFS
ALT7
ARM_TRACE
05
ARM_TRACE
06
ARM_TRACE
07
ARM_TRACE
08
SRC_BOOT_
CFG26
UART1_DTR
_B
ALT8
ALT9
Default/
Reset State
HDMI_TX_D
ATA0_P
HDMI_TX_D
ATA0_N
HDMI_TX_D
ATA1_P
HDMI_TX_D
ATA1_N
HDMI_TX_D
ATA2_P
HDMI_TX_D
ATA2_N
HDMI_TX_CL
K_P
HDMI_TX_CL
K_N
HDMI_TX_H
PD
GPIO5_IO26
GPIO5_IO27
GPIO5_IO28
GPIO5_IO29
EPDC_DATA
04
EIM_LBA
EPDC_SDCE7
GPIO3_IO24
REL 1.2
Page 42 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
ALT0
7
SD3_DAT6
SD3_DATA6
9
SD3_DAT7
SD3_DATA7
97
EIM_D19
94
EIM_D20
117
EIM_D27
118
EIM_D26
98
KEY_COL0
99
KEY_ROW0
102
KEY_COL1
103
KEY_ROW1
19
EIM_D28
18
EIM_D21
116
GPIO_3
UART1
UART2
UART4
UART5
I2C1
I2C2
115
EIM_DATA1
9
EIM_DATA2
0
EIM_DATA2
7
EIM_DATA2
6
ECSPI1_SCLK
ECSPI1_MOS
I
ECSPI1_MIS
O
ECSPI1_SS0
EIM_DATA2
8
EIM_DATA2
1
ESAI_RX_HF
_CLK
ALT1
ALT2
ALT3
ALT4
UART1_RX_
DATA
UART1_TX_
DATA
IPU1_DI0_PI
N08
IPU1_DI0_PI
N16
IPU1_CSI0_D
ATA00
IPU1_CSI0_D
ATA01
IPU2_CSI1_D
ATA16
IPU2_CSI1_D
ATA15
IPU2_CSI1_D
ATA13
IPU2_CSI1_D
ATA14
AUD5_TXC
KEY_COL0
AUD5_TXD
KEY_ROW0
ENET_MDIO
AUD5_TXFS
KEY_COL1
ENET_COL
AUD5_RXD
KEY_ROW1
ECSPI4_MOS
I
IPU1_DI0_PI
N17
IPU2_CSI1_D
ATA12
IPU2_CSI1_D
ATA11
XTALOSC_RE
F_CLK_24M
ECSPI1_SS1
ECSPI4_SS0
IPU1_DI1_PI
N13
IPU1_DI1_PI
N11
ENET_RX_D
ATA3
ENET_TX_DA
TA3
I2C1_SDA
ECSPI4_SCLK
I2C3_SCL
UART1_CTS_
B
UART1_RTS_
B
UART2_RX_
DATA
UART2_TX_
DATA
UART4_TX_
DATA
UART4_RX_
DATA
UART5_TX_
DATA
UART5_RX_
DATA
UART2_CTS_
B
USB_OTG_O
C
CCM_CLKO2
ALT6
ALT8
ALT9
Default/
Reset State
GPIO6_IO18
GPIO6_IO17
GPIO6_IO17
EPDC_DATA
12
GPIO3_IO19
EPIT1_OUT
GPIO3_IO20
EPIT2_OUT
GPIO3_IO27
IPU1_SISG3
GPIO3_IO26
IPU1_SISG2
GPIO4_IO06
DCIC1_OUT
GPIO4_IO06
GPIO4_IO07
DCIC2_OUT
GPIO4_IO07
GPIO3_IO19
GPIO3_IO20
IPU1_DISP1_
DATA23
IPU1_DISP1_
DATA22
GPIO3_IO27
GPIO3_IO26
SD1_VSELEC
T
SD2_VSELEC
T
IPU1_EXT_T
RIG
IPU1_DI0_PI
N13
GPIO3_IO21
I2C1_SCL
SPDIF_IN
GPIO3_IO21
GPIO1_IO03
USB_H1_OC
MLB_CLK
GPIO1_IO03
GPIO1_IO06
SD2_LCTL
MLB_SIG
GPIO1_IO06
GPIO4_IO08
GPIO4_IO09
GPIO3_IO28
ESAI_TX_CLK
176
GPIO_8
ESAI_TX5_RX
0
XTALOSC_RE
F_CLK_32K
EPIT2_OUT
FLEXCAN1_R
X
UART2_RX_
DATA
GPIO1_IO08
SPDIF_SR_CL
K
178
GPIO_7
ESAI_TX4_RX
1
ECSPI5_RDY
EPIT1_OUT
FLEXCAN1_T
X
UART2_TX_
DATA
GPIO1_IO07
SPDIF_LOCK
iWave Systems Technologies Pvt. Ltd.
ALT7
GPIO6_IO18
GPIO_6
CAN1
I2C3_SDA
ALT5
GPIO4_IO08
GPIO4_IO09
USB_OTG_P
WR_CTL_WA
KE
USB_OTG_H
OST_MODE
EPDC_PWR_
CTRL3
GPIO3_IO28
I2C4_SDA
GPIO1_IO08
I2C4_SCL
GPIO1_IO07
REL 1.2
Page 43 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
175
KEY_ROW4
177
KEY_COL4
138
GPIO_9
ESAI_RX_FS
WDOG1_B
KEY_COL6
CCM_REF_E
N_B
PWM1_OUT
GPIO1_IO09
SD1_WP
GPIO1_IO09
125
SD1_DAT2
SD1_DATA2
ECSPI5_SS1
GPT_COMPA
RE2
PWM2_OUT
WDOG1_B
GPIO1_IO19
WDOG1_RES
ET_B_DEB
GPIO1_IO19
147
SD1_DAT1
SD1_DATA1
ECSPI5_SS0
PWM3_OUT
141
SD1_CMD
SD1_CMD
ECSPI5_MOS
I
PWM4_OUT
195
JTAG_TDI
JTAG_TDI
191
JTAG_TDO
JTAG_TDO
199
JTAG_TMS
JTAG_TMS
193
JTAG_TRSTB
JTAG_TRSTB
197
JTAG_TCK
JTAG_TCK
CAN2
ALT0
FLEXCAN2_R
X
FLEXCAN2_T
X
ALT1
IPU1_SISG5
IPU1_SISG4
PWM
JTAG
iWave Systems Technologies Pvt. Ltd.
ALT2
USB_OTG_P
WR
USB_OTG_O
C
ALT3
KEY_ROW4
KEY_COL4
GPT_CAPTU
RE2
GPT_COMPA
RE1
ALT4
UART5_CTS_
B
UART5_RTS_
B
ALT5
ALT6
ALT7
ALT8
ALT9
Default/
Reset State
GPIO4_IO15
GPIO4_IO15
GPIO4_IO14
GPIO4_IO14
GPIO1_IO17
GPIO1_IO17
GPIO1_IO18
GPIO1_IO18
REL 1.2
Page 44 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
SODIMM
Edge Pin No
33
i.MX6 CPU
Pad Name
NANDF_WP_
B
ALT0
NAND_WP_
B
EIM_ADDR2
5
NAND_DATA
02
NAND_DATA
04
ALT1
EIM_A25
37
NANDF_D2
43
NANDF_D4
45
SD1_DAT0
SD1_DATA0
ECSPI5_MIS
O
47
NANDF_ALE
NAND_ALE
49
NANDF_D1
ECSPI4_SS1
69
NANDF_CS1
73
NANDF_D0
122
ALT5
ALT6
ALT7
ALT8
GPIO6_IO09
ECSPI2_RDY
IPU1_DI1_PI
N12
IPU1_DI0_D
1_CS
GPIO5_IO02
HDMI_TX_C
EC_LINE
EPDC_DATA
15
ALT9
Default/
Reset State
I2C4_SCL
GPIO6_IO09
EIM_ACLK_F
REERUN
GPIO5_IO02
GPIO2_IO02
GPIO2_IO02
SD2_DATA4
GPIO2_IO04
GPIO2_IO04
GPIO1_IO16
GPIO1_IO16
SD4_RESET
GPIO6_IO08
GPIO6_IO08
SD1_DATA5
GPIO2_IO01
GPIO2_IO01
GPIO6_IO14
GPIO6_IO14
GPIO2_IO00
GPIO2_IO00
SD4_VSELEC
T
GPIO_18
ESAI_TX1
ENET_RX_CL
K
10
SD1_DAT3
SD1_DATA3
ECSPI5_SS2
30
NANDF_D3
34
NANDF_D6
36
NANDF_CS0
42
SD1_CLK
SD1_CLK
44
NANDF_CLE
NAND_CLE
IPU2_SISG4
64
GPIO_19
KEY_COL5
ENET_1588_
EVENT0_OU
T
iWave Systems Technologies Pvt. Ltd.
ALT4
SD1_DATA6
NAND_DATA
01
NAND_CE1_
B
NAND_DATA
00
NAND_DATA
03
NAND_DATA
06
NAND_CE0_
B
ALT3
IPU2_SISG5
35
GPIOs
ALT2
GPT_CAPTU
RE1
SD3_VSELEC
T
SD1_DATA4
SD3_VSELEC
T
GPT_COMPA
RE3
SDMA_EXT_
EVENT1
ASRC_EXT_C
LK
GPIO7_IO13
PWM1_OUT
WDOG2_B
GPIO1_IO21
SNVS_VIO_5
_CTL
WDOG2_RES
ET_B_DEB
GPIO7_IO13
GPIO1_IO21
SD1_DATA7
GPIO2_IO03
GPIO2_IO03
SD2_DATA6
GPIO2_IO06
GPIO2_IO06
GPIO6_IO11
GPIO6_IO11
GPIO1_IO20
GPIO1_IO20
GPIO6_IO07
GPIO6_IO07
ECSPI5_SCLK
XTALOSC_OS
C32K_32K_O
UT
SPDIF_OUT
GPT_CLKIN
CCM_CLKO1
ECSPI1_RDY
GPIO4_IO05
ENET_TX_ER
GPIO4_IO05
REL 1.2
Page 45 of 56
i.MX6 SODIMM SOM Hardware User Guide
Interface/
Function
GPIOs
SODIMM
Edge Pin No
i.MX6 CPU
Pad Name
68
NANDF_RB0
76
NANDF_D5
78
NANDF_D7
80
DI0_PIN4
86
EIM_BCLK
132
GPIO_16
136
KEY_ROW3
139
KEY_COL3
179
181
ALT1
NAND_READ
Y_B
NAND_DATA
05
NAND_DATA
07
IPU1_DI0_PI
N04
IPU2_DI0_PI
N01
GPIO6_IO10
GPIO6_IO10
SD2_DATA5
GPIO2_IO05
GPIO2_IO05
SD2_DATA7
GPIO2_IO07
GPIO2_IO07
GPIO4_IO20
GPIO4_IO20
DI0_PIN04
ALT2
AUD6_RXD
ALT3
ALT4
SD1_WP
ALT5
ALT6
ALT7
ALT8
ALT9
Default/
Reset State
ALT0
IPU1_DI1_PI
N16
ENET_1588_
EVENT2_IN
ENET_REF_C
LK
SD1_LCTL
SPDIF_IN
GPIO7_IO11
I2C3_SDA
ASRC_EXT_C
LK
HDMI_TX_D
DC_SDA
KEY_ROW3
I2C2_SDA
GPIO4_IO13
SD1_VSELEC
T
GPIO4_IO13
ECSPI1_SS3
ENET_CRS
HDMI_TX_D
DC_SCL
KEY_COL3
I2C2_SCL
GPIO4_IO12
SPDIF_IN
GPIO4_IO12
KEY_COL2
ECSPI1_SS1
ENET_RX_D
ATA2
FLEXCAN1_T
X
KEY_COL2
ENET_MDC
GPIO4_IO10
KEY_ROW2
ECSPI1_SS2
ENET_TX_DA
TA2
FLEXCAN1_R
X
KEY_ROW2
SD2_VSELEC
T
GPIO4_IO11
EIM_BCLK
ESAI_TX3_RX
2
XTALOSC_OS
C32K_32K_
OUT
GPIO6_IO31
EPDC_SDCE9
JTAG_DE_B
GPIO7_IO11
USB_H1_PW
R_CTL_WAK
E
HDMI_TX_C
EC_LINE
GPIO4_IO10
GPIO4_IO11
Note:
*Purple Coloured ALT functions are not supported in i.MX6 Quad and Dual core CPUs.
* Green Coloured ALT functions are not supported in i.MX6 Solo and Duallite CPUs.
iWave Systems Technologies Pvt. Ltd.
GPIO6_IO31
REL 1.2
Page 46 of 56
i.MX6 SODIMM SOM Hardware User Guide
3. TECHNICAL SPECIFICATION
This section provides detailed information about the i.MX6 SODIMM SOM technical specification with Electrical,
Environmental and Mechanical characteristics.
3.1
Electrical Characteristics
3.1.1 Power Input Requirement
The below table provides the Power Input Requirement of i.MX6 SODIMM SOM.
Table 7: Power Input Requirement
Sl. No.
1
2
3
Power Rail
VIN_3V3¹
VRTC_3V02
VBUS_5V³
Min (V)
3.15
2.8
4.4
Typical (V)
3.3
3
5
Max(V)
3.45
3.3
5.25
Max Input Ripple
±50mV
±20 mV
±50mV
¹ i.MX6 SODIMM SOM is designed to work with VIN_3V3 input power rail from SODIMM Edge connector.
² i.MX6 SODIMM SOM uses this voltage as backup power source to RTC when VIN_3V3 is off. This is an optional
power and required only if RTC functionality is used.
³ This power is used as supply voltage to both USB OTG and USB HOST1 block of i.MX6 CPU. It is recommended to
connect always available 5V power to this pin from carrier board.
iWave Systems Technologies Pvt. Ltd.
REL 1.2
Page 47 of 56
i.MX6 SODIMM SOM Hardware User Guide
3.1.2 Power Input Sequencing
i.MX6 SODIMM SOM’s Power Input sequence requirement is explained below.
Power up Sequence:

VRTC_3V0 must come up at the same time or before VIN_3V3 comes up.
Power down Sequence:

VIN_3V3 must go down at the same time or before VRTC_3V0 goes down.
Figure 4: i.MX6 SODIMM SOM Power Sequence
Note: VBUS_5V is not part of the power supply sequence and can be powered at any time.
Table 8: Power Sequence Timing
Item
T1
T2
Description
VRTC_3V0 rise time to VIN_3V3 rise time
VIN_3V3 fall time to VRTC_3V0 fall time
Value
≥ 0 ms
≥ 0 ms
Important Note: All the carrier board power supplies should be powered ON only after the SOM is powered ON
completely. Otherwise it can cause internal latch-up and malfunctions/bootup issues due to reverse current flows.
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3.1.3 Power Consumption
Table 9: Power Consumption
Task/Status
Power Rail
Run Mode Power Consumption¹
Play Video
Play Graphics 3D Demo
Play Audio
File Transfer
Dhrystone
Maximum Power Test:
 HDMI - Run the 1080p video
(creature.mp4)
 LVDS - Run the video (akiyo.mp4) on
LVDS
 Ethernet - Run the ping test
 FileTransfer - Transfer the 1MB file
between USB and Micro SD with 1000
count
 Audio - Run the mp3 file using Gplay
 Powermeasurement1.sh - Run the
dry2 application on back ground
 Powermeasurement2.sh - Run the
Graphics (OpenGL) application (tiger)
on LVDS
All above with below mentioned one change,
HDMI - Run the VGA video (akiyo.mp4) on
HDMI using VPU Decoder library
Low Power Mode Power Consumption²
System Idle Mode.
Deep Sleep Mode.
User Idle Mode - Enable the Bus frequency
RTC power when no VIN_3V3 supply is
provided
Current Drawn (A)/
Power Consumption (W)
VIN_3V3
VIN_3V3
VIN_3V3
VIN_3V3
VIN_3V3
VIN_3V3
0.49/1.617
0.33/1.089
0.46/1.518
0.27/0.891
0.39/1.287
1.02/3.366
VIN_3V3
1.18/3.894
VIN_3V3
1.09/3.597
VIN_3V3
VIN_3V3
VIN_3V3
VRTC_3V0
0.2/0.66
0.05/0.165
0.3/0.99
500uA³
¹ Power consumption measurements have been done in iWave’s i.MX6 Quad CPU based SODIMM SOM with iWave’s
Generic SODIMM Carrier board running iWave’s Linux3.14.38 BSP (iW-PREPZ-DF-01-R2.0-REL1.0-Linux3.14.38).
² Only i.MX6 CPU related power management is implemented in the BSP for low power modes.
³ i.MX6 RTC controller draws more power from VCC_RTC coin cell power input and so could drain the coin cell faster.
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i.MX6 SODIMM SOM Hardware User Guide
3.2
Environmental Characteristics
3.2.1 Environmental Specification
The below table provides the Environment specification of i.MX6 SODIMM SOM.
Table 10: Environmental Specification
Parameters
Operating temperature range (Industrial)¹
Operating temperature range (Commercial)¹
Humidity - Operating
Humidity - Storage
Min
Max
-40°C
0°C
10%RH
5%RH
85°C
70°C
90%RH
95%RH
¹ iWave guarantees the component selection for the given operating temperature. The operating temperature at the
system level will be affected by the various system components like carrier board and its components, system
enclosure, air circulation in the system, system power supply etc. Based on the system design, specific heat
dissipating approach might be required from system to system. It is recommended to do the necessary system level
thermal simulation and find necessary thermal solution in the system before using this board in the end application.
3.2.2 RoHS Compliance
iWave’s i.MX6 SODIMM SOM is designed by using RoHS compliant components and manufactured on lead free
production process.
3.2.3 Electrostatic Discharge
iWave’s i.MX6 SODIMM SOM is sensitive to electro static discharge and so high voltages caused by static electricity
could damage some of the devices on board. It is packed with necessary protection while shipping. Do not open or
use the SOM except at an electrostatic free workstation.
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3.3
Mechanical Characteristics
3.3.1 i.MX6 SODIMM SOM Mechanical Dimensions
i.MX6 SODIMM SOM PCB size is 67.6mm x 37mm x 1mm. SODIMM SOM mechanical dimension is shown below.
Please refer the JEDEC Physical standard DDR SODIMM specification for SODIMM Edge connector mechanical details.
Figure 5: Mechanical dimension of i.MX6 SODIMM SOM - Top View
i.MX6 SODIMM SOM PCB thickness is 1±0.1mm, top side maximum height component is SPI flash (2.16mm) followed
by iMX6 CPU (2.10mm) and bottom side maximum height component is Capacitor (1.25mm) followed by DDR3
SDRAM (1.0mm). Please refer the below figure which gives height details of the i.MX6 SODIMM SOM.
Figure 6: Mechanical dimension of i.MX6 SODIMM SOM - Side View
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4. ORDERING INFORMATION
i.MX6 SODIMM SOM is available in different variations. The below table provides the standard orderable part
numbers for different i.MX6 SODIMM SOM variations. Please contact iWave for orderable part number of higher
RAM memory size or Flash memory size configurations. Also if the desired part number is not listed in below table or
if any custom configuration part number is required, please contact iWave.
Table 11: Orderable Product Part Numbers
Product Part Number
Description
Temperature
i.MX6 Quad CPU based SODIMM SOMs
iW-G15M-SM04-3D001G-E004G-LCC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Linux
Commercial
iW-G15M-SM04-3D001G-E004G-ACC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Android
Commercial
iW-G15M-SM04-3D001G-E004G-BCC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Boot code
Commercial
iW-G15M-SM04-3D001G-E004G-LIC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Linux
Industrial
iW-G15M-SM04-3D001G-E004G-AIC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Android
Industrial
iW-G15M-SM04-3D001G-E004G-BIC
i.MX6 Quad Core CPU, 1GB RAM, 4GB eMMC with Boot code
Industrial
i.MX6 Dual CPU based SODIMM SOMs
iW-G15M-SM02-3D001G-E004G-LCC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Linux
Commercial
iW-G15M-SM02-3D001G-E004G-ACC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Android
Commercial
iW-G15M-SM02-3D001G-E004G-BCC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Boot code
Commercial
iW-G15M-SM02-3D001G-E004G-LIC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Linux
Industrial
iW-G15M-SM02-3D001G-E004G-AIC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Android
Industrial
iW-G15M-SM02-3D001G-E004G-BIC
i.MX6 Dual Core CPU, 1GB RAM, 4GB eMMC with Boot code
Industrial
i.MX6 Duallite CPU based SODIMM SOMs
iW-G15M-SM2L-3D001G-E004G-LCC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Linux
Commercial
iW-G15M-SM2L-3D001G-E004G-ACC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Android
Commercial
iW-G15M-SM2L-3D001G-E004G-BCC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Boot
code
Commercial
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i.MX6 SODIMM SOM Hardware User Guide
Product Part Number
Description
Temperature
iW-G15M-SM2L-3D001G-E004G-LIC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Linux
Industrial
iW-G15M-SM2L-3D001G-E004G-AIC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Android
Industrial
iW-G15M-SM2L-3D001G-E004G-BIC
i.MX6 Duallite Core CPU, 1GB RAM, 4GB eMMC with Boot
code
Industrial
i.MX6 Solo CPU based SODIMM SOMs
iW-G15M-SM01-3D512M-E004G-LCC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Linux
Commercial
iW-G15M-SM01-3D512M-E004G-ACC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Android
Commercial
iW-G15M-SM01-3D512M-E004G-BCC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Boot
code
Commercial
iW-G15M-SM01-3D512M-E004G-LIC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Linux
Industrial
iW-G15M-SM01-3D512M-E004G-AIC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Android
Industrial
iW-G15M-SM01-3D512M-E004G-BIC
i.MX6 Solo Core CPU, 512MB RAM, 4GB eMMC with Boot
code
Industrial
Important Note: Some of the above mentioned Part Number is subject to MOQ purchase. Please contact iWave for
further details.
Note: For SOM identification purpose, Product Part Number and SOM Unique Serial Number are pasted as Label with
Barcode readable format on SOM.
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i.MX6 SODIMM SOM Hardware User Guide
5. APPENDIX I
5.1
Guidelines to insert the SODIMM SOM into Carrier board

Make sure that power is not provided to the Carrier board.

Insert the module into the socket at a slight angle (approximately 30 degrees). Note that the socket and
module are both keyed, which means the module can be installed one way only.

To seat the module into the socket, apply firm, even pressure to each end of the module until you feel it slip
down into the socket.

With the module properly seated in the socket, rotate the module downward, as indicated in the illustration.
Continue pressing downward until the clips at each end of the socket lock into position.

Once the module has been installed, Carrier board can be Powered ON with 5V power supply.
Figure 7: Module Insertion Procedure
5.2
Guidelines to remove the SODIMM SOM from Carrier board

Make sure that power is not provided to the Carrier board.

When you remove the module, pull away the retention clips (A) on each side of the memory module.

The module pops up. Grasp the edge of the module (B) and gently pull the module out of the connector.
Figure 8: Module Removal Procedure
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6. APPENDIX II
6.1
i.MX6 SODIMM SOM Development Platform
iWave Systems supports iW-RainboW-G15D-SM – i.MX6 SODIMM Development Platform which is targeted for quick
validation of i.MX6 CPU with i.MX6 SODIMM SOM. iWave's i.MX6 SODIMM Development Board incorporates i.MX6
SODIMM SOM and SODIMM Carrier board for complete validation of i.MX6 SODIMM SOM functionality with
complete BSP support.
Being a Pico-ITX form factor with 100mmx72mm size, the i.MX6 SODIMM Development Platform carrier board is
highly packed with all the necessary on-board connectors to validate the i.MX6 CPU features with optional 4.3"
resistive display kit. For more details on i.MX6 SODIMM SOM Development platform, visit the below web link.
http://www.iwavesystems.com/product/development-platform/imx6-sodimm-development-kit-17/imx6-sodimmdevelopment-kit.html
Figure 9: i.MX6 SODIMM SOM Development Platform
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