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STK14D88
32Kx8 AutoStore™ nvSRAM
Features
■ 25, 35, 45 ns Read Access and R/W Cycle Time
■ Unlimited Read/Write Endurance
■ Automatic Nonvolatile STORE on Power Loss
■ Nonvolatile STORE Under Hardware or Software Control
■ Automatic RECALL to SRAM on Power Up
■ Unlimited RECALL Cycles
■ 200K STORE Cycles
■ 20-Year Nonvolatile Data Retention
■ Single 3.0V +20%, -10% Power Supply
■ Commercial, Industrial Temperatures
■ Small Footprint SOIC and SSOP Packages (RoHS-Compliant)
Description
The Cypress STK14D88 is a 256Kb fast static RAM with a nonvolatile Quantum Trap™ storage element included with each memory cell.
The SRAM provides fast access and cycle times, ease of use, and unlimited read and write endurance of a normal SRAM.
Data transfers automatically to the nonvolatile storage cells when power loss is detected (the STORE operation). On power up, data is automatically restored to the SRAM (the RECALL operation). Both STORE and RECALL operations are also available under software control.
The Cypress nvSRAM is the first monolithic nonvolatile memory to offer unlimited writes and reads. It is the highest performance, most reliable nonvolatile memory available.
Logic Block Diagram
V
CCX
V
CAP
DQ
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
A
5
A
6
A
7
A
8
A
9
A
11
A
12
A
13
A
14
STATIC RAM
ARRAY
512 x 512
Quantum Trap
512 x 512
STORE
RECALL
COLUMN I/O
COLUMN DEC
A
0
A
1
A
2
A
3
A
4
A
10
POWER
CONTROL
STORE/
RECALL
CONTROL
SOFTWARE
DETECT
HSB
A
0
- A
13
G
E
W
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-52037 Rev. **
• San Jose
,
CA 95134-1709 • 408-943-2600
Revised March 02, 2009
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STK14D88
Pin Configurations
Figure 1. Pin Diagram 48-Pin SSOP/32-SOIC
V
CAP
NC
NC
DQ
0
A
3
A
2
A
1
A
0
DQ
1
DQ
2
NC
A
14
A
12
A
7
A
6
A
5
NC
A
4
NC
NC
NC
V
SS
NC
NC
1
2
7
8
9
10
5
6
3
4
11
12
13
14
19
20
21
22
23
24
15
16
17
18
48-Pin SSOP
TOP
V
CC
NC
A
10
E
DQ
7
DQ
5
DQ
4
DQ
3
V
CC
NC
NC
V
SS
NC
NC
DQ
6
G
HSB
W
A
13
A
8
A
9
NC
A
11
NC
40
39
38
37
44
43
42
41
48
47
46
45
36
35
34
29
28
27
26
25
33
32
31
30
V
CAP
A
14
A
12
A
7
A
6
A
5
DQ
0
DQ
1
DQ
2
V
SS
A
4
A
3
NC
A
2
A
1
A
0
10
11
12
7
8
9
13
14
15
16
3
4
5
6
1
2
32-SOIC
TOP
Relative PCB Area Usage
[1]
V
CC
G
NC
A
10
E
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
HSB
W
A
13
A
8
A
9
A
11
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
Pin Descriptions
Pin Name
A
14
-A
0
DQ
7
-DQ
0
E
W
G
V
CC
HSB
V
CAP
V
SS
NC
I/O
Input
I/O
Input
Input
Address
Data
Description
: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable : The active low E input selects the device
Input
Write Enable : The active low W enables data on the DQ pins to be written to the address location latched by the falling edge of E
Output Enable : The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power Supply Power : 3.0V, +20%, -10%
I/O Hardware Store Busy : When low this output indicates a Store is in progress. When pulled low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor keeps this pin high if not connected. (Connection Optional).
Power Supply AutoStore™ Capacitor : Supplies power to nvSRAM during power loss to store data from SRAM to nonvolatile storage elements.
Power Supply Ground
No Connect Unlabeled pins have no internal connections.
Note
1. See “Package Diagrams” on page 15 for detailed package size specifications.
Document Number: 001-52037 Rev. ** Page 2 of 17
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STK14D88
Absolute Maximum Ratings
Voltage on Input Relative to Ground.................–0.5V to 4.1V
Voltage on Input Relative to V
SS
...........–0.6V to (V
CC
+ 0.5V)
Voltage on DQ
0-7 or HSB ......................–0.5V to (V
CC
+ 0.5V)
Temperature under Bias ............................... –55
°
C to 125
°
C
Storage Temperature .................................... –65
°
C to 140
°
C
Power Dissipation ............................................................. 1W
DC Output Current (1 output at a time, 1s duration)..... 15mA
Note: Stresses greater than those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NF (SOP-32) PACKAGE THERMAL CHARACTERISTICS
θ jc
5.4 C/W;
θ ja
44.3 [0fpm], 37.9 [200fpm], 35.1 C/W [500fpm].
RF (SSOP-48) PACKAGE THERMAL CHARACTERISTICS
θ jc
6.2 C/W;
θ ja
51.1 [0fpm], 44.7 [200fpm], 41.8 C/W [500fpm].
DC Characteristics
(V
CC
= 2.7V-3.6V)
I
I
I
I
I
I
I
Symbol
CC1
CC2
CC3
CC4
SB
ILK
OLK
V
V
V
IH
IL
OH
Average V
Average V
STORE
200ns
3V, 25°C, Typical
Average V
V
CC
Standby Current
(Standby, Stable CMOS Input
Levels)
Parameter
CC
CC
Average V
CC
Current
[2]
Current during
CAP
Current at t
AVAV
Current during
AutoStore Cycle
Input Leakage Current
Input Logic “1” Voltage
Input Logic “0” Voltage
Output Logic “1” Voltage
=
Off-State Output Leakage Current
Commercial
Min
2.0
V
SS
– .5
2.4
Max
65
55
50
3
10
±
±
3
3
1
1
V
CC
+ .5
0.8
Industrial
Min Max
70
60
55
3
10
Unit Notes mA mA mA t t
AVAV t
AVAV
AVAV
= 25ns
= 35ns
= 45ns
Dependent on output loading and cycle rate. Values obtained without output loads.
mA All Inputs Don’t Care, V
CC
= max
Average current for duration of
STORE cycle (t
STORE
) mA W
≥
(V
CC
– 0.2V)
All Others Cycling, CMOS Levels
Dependent on output loading and cycle rate. Values obtained without output loads.
±
±
3
3
1
1 mA All Inputs Don’t Care
Average current for duration of
STORE cycle (t
STORE
) mA E
≥
(V
CC
– 0.2V)
All Others V
IN
0.2V)
≤
0.2V or
≥
(V
CC
–
Standby current level after nonvolatile cycle complete
μ
A V
CC
= max
V
IN
= V
SS
to V
CC
μ
A V
CC
= max
V
IN
= V
SS
to V
CC
, E or G
≥
V
IH
V
2.0
V
CC
+ .5
V All Inputs
SS
– .5
0.8
V All Inputs
2.4
V I
OUT
= – 2mA
Note:
2. The HSB pin has I
OUT
=-10uA for V
OH
of 2.4V, this parameter is characterized but not tested
Document Number: 001-52037 Rev. ** Page 3 of 17
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STK14D88
DC Characteristics
(continued)
(V
CC
= 2.7V-3.6V)
Symbol
V
OL
T
A
V
CC
V
CAP
Parameter
[2]
Output Logic “0” Voltage
Operating Temperature
Operating Voltage
Storage Capacitance
Commercial
Min Max
0
2.7
17
0.4
70
3.6
120
Industrial
Min Max
- 40
2.7
17
0.4
85
3.6
120
Unit Notes
V I
OUT
= 4mA
°
C
V 3.3V +20%, -10%
μ
F Between V
CAP
pin and V
SS
, 5V
Rated
K
Years @ 55
°
C
DATA
R
NV
C
Data Retention
Nonvolatile STORE Operations
20
200
AC Test Conditions
Input Pulse Levels .................................................... 0V to 3V
Input Rise and Fall Times ............................................ <5 ns
Input and Output Timing Reference Levels .................... 1.5V
Output Load.................................. See Figure 2 and Figure 3
20
200
Figure 2. AC Output Loading
3.0V
577 Ω
OUTPUT
789
Ω
30 pF
INCLUDING
SCOPE AND
FIXTURE
Figure 3. AC Output Loading for Tri-state Specs (t
HZ
, t
LZ
, t
WLQZ
, t
WHQZ
, t
GLQX
, t
GHQZ
3.0V
577
Ω
OUTPUT
789
Ω
5 pF
INCLUDING
SCOPE AND
FIXTURE
Capacitance
Parameter
[3]
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Note
3. These parameters are guaranteed but not tested.
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
Document Number: 001-52037 Rev. **
Max
7
7
Unit pF pF
Conditions
Δ
V = 0 to 3V
Δ
V = 0 to 3V
Page 4 of 17
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STK14D88
SRAM READ Cycles #1 and #2
NO.
#1
1
2 t
AVAV
[4]
3 t
AVQV
[5]
4
5 t
AXQX
[5]
6 t
Symbols
#2 t
ELQV t
ELEH
[4] t
AVQV
[5] t
GLQV t
AXQX
[5]
ELQX
Alt.
t
ACS t
RC t
AA t
OE t
OH t
LZ
7
8
9
10
11 t
EHQZ
[6] t
HZ t
GLQX t
GHQZ
[6] t
ELICCH
[3] t
EHICCL
[3] t
OLZ t
OHZ t
PA t
PS
Parameter
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
STK14D88-25 STK14D88-35 STK14D88-45
Min Max Min Max Min Max
25 35 45
25 35 45
25
12
35
15
45
20
3
3
10
3
3
13
3
3
15
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
0
0
10
25
0
0
13
35
0
0
15
45
Unit ns ns ns ns ns ns ns ns ns ns ns
ADDRESS
DQ (DATA OUT)
Figure 4. SRAM READ Cycle 1: Address Controlled
[ 4 , 5, 6]
5 t
AXQX
2 t
AVAV
3 t
AVQV
DATA VALID
Figure 5. SRAM READ Cycle 2: E Controlled
[4, 7]
1
2
29
6
7
11
3
10
8
4
9
Notes
4. W must be high during SRAM READ cycles.
5. Device is continuously selected with E and G both low.
6. Measured ± 200mV from steady state output voltage.
7. HSB must remain high during READ and WRITE cycles.
Document Number: 001-52037 Rev. ** Page 5 of 17
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STK14D88
SRAM WRITE Cycle #1 and #2
Symbols
NO.
#1
12
13
14
15
16
17
18 t
AVAV t
WLWH t
ELWH t
DVWH t
WHDX t
AVWH t
AVWL
19
20 t t
WHAX
[6, 8]
WLQZ
21 t
WHQX
#2 t
AVAV t
WLEH t
ELEH t
DVEH t
EHDX t
AVEH t
AVEL t
EHAX
Alt.
t
WC t
WP t
CW t
DW t
DH t
AW t
AS t
WR t
WZ t
OW
Parameter
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
STK14D88-25 STK14D88-35 STK14D88-45
Unit
Min Max Min Max Min Max
25 35 45 ns
20
20
10
0
25
25
12
0
30
30
15
0 ns ns ns ns
20
0
0
3
10
25
0
0
3
13
30
0
0
3
15 ns ns ns ns ns
ADDRESS
E
W
DATA IN
DATA OUT
18 t
AVWL
Figure 6. SRAM WRITE Cycle 1: W Controlled
[8, 9]
12 t
AVAV
14 t
ELWH
19 t
WHAX
17 t
AVWH
13 t
WLWH
PREVIOUS DATA
20 t
WLQZ
15 t
DVWH
DATA VALID
HIGH IMPEDANCE
13 t
WHDX
21 t
WHQX
ADDRESS
18 t
AVEL
Figure 7. SRAM WRITE Cycle 2: E Controlled
[8, 9]
12 t
AVAV
14 t
ELEH
19 t
EHAX
E
17 t
AVEH
13 t
WLEH
W
15 t
DVEH
DATA IN
DATA OUT
Notes
8. If W is low when E goes low, the outputs remain in the high-impedance state.
9. E or W must be ≥ V
IH
during address transitions.
HIGH IMPEDANCE
DATA VALID
16 t
EHDX
Document Number: 001-52037 Rev. ** Page 6 of 17
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STK14D88
AutoStore/POWER UP RECALL
Alt.
No.
Symbols
22 t
RECALL
23 t
STORE
24 V
SWITCH
25 V
CCRISE t
HLHZ
Parameter
Power up RECALL Duration
STORE Cycle Duration
Low Voltage Trigger Level
Vcc Rise Time
Min
STK14D88
Max
20
12.5
2.65
150
Figure 8. AutoStore /POWER UP RECALL
Unit ms ms
V
μ s
Notes
10
11, 12
22
22
23
22
23
Note: Read and Write cycles are ignored during STORE, RECALL, and while V
CC
is below V
SWITCH
Notes
10. t
HRECALL
starts from the time V
CC
rises above V
SWITCH
.
11. If an SRAM WRITE has not taken place since the last nonvolatile cycle, no STORE will take place.
12. Industrial Grade Devices require 15 ms Max.
Document Number: 001-52037 Rev. ** Page 7 of 17
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STK14D88
Software-Controlled STORE/RECALL Cycle
[13, 14]
No.
Symbols
E Cont
Alternate
Parameter
STK14D88-25 STK14D88-35 STK14D88-45
Unit Notes
Min Max Min Max Min Max
26 t
AVAV
27 t
AVEL
28 t
ELEH
29 t
EHAX
30 t
RECALL t
RC t
AS t
CW
STORE/RECALL Initiation Cycle Time
Address Setup Time
Clock Pulse Width
Address Hold Time
RECALL Duration
25
0
20
1
50
35
0
25
1
50
45
0
30
1
50 ns ns ns ns
μ s
14
ADDRESS
Figure 9. E and G Controlled Software STORE/RECALL Cycle
[14]
26 t
AVAV
ADDRESS #1
26 t
AVAV
ADDRESS #6
27 t
AVEL
28 t
ELEH
E
29 t
ELAX
23 t
STORE
/
t
30
RECALL
HIGH IMPEDANCE
DQ (DATA DATA VALID
Notes
13. The software sequence is clocked on the falling edge of E controlled READs.
14. The six consecutive addresses must be read in the order listed in the software STORE/RECALL Mode Selection Table. W must be high during all six consecutive cycles.
Document Number: 001-52037 Rev. ** Page 8 of 17
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STK14D88
Hardware STORE Cycle
NO.
31
32
Symbols
Standard Alternate t
DELAY t
HLHX t
HLQZ
Parameter
Hardware STORE to SRAM Disabled
Hardware STORE Pulse Width
Figure 10. Hardware STORE Cycle
32
Min
STK14D88
Max
1
15
70
Unit
µs ns
Notes
15
23
31
Soft Sequence Commands
NO.
Symbols
Standard
33 t
SS
Parameter
Soft Sequence Processing Time
Min
STK14D88
Max
70
Figure 11. Software Sequence Commands
33 33
Unit
µs
Notes
16, 17
Notes
15. Read and Write cycles in progress before HSB is asserted are given this minimum amount of time to complete.
16. This is the amount of time that it takes to take action on a soft sequence command. Vcc power must remain high to effectively register command.
17. Commands like Store and Recall lock out I/O until operation is complete which further increases this time. See specific command.
Document Number: 001-52037 Rev. ** Page 9 of 17
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STK14D88
Mode Selection
L
L
E
H
L
W
X
H
L
H
L
X
G
X
L
L
L
L
H
H
H
L
L
L
A
14
–A
0
X
X
X
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x03F8
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x07F0
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0FC0
0x0E38
0x31C7
0x03E0
0x3C1F
0x303F
0x0C63
Mode
Not Selected
Read SRAM
Write SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Disable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Store
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile Recall
IO
Output High Z
Output Data
Input Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Power
Standby
Active
Active
Active
Active
Active
I
CC2
Active
Notes
18, 19, 20
18, 19, 20
18, 19, 20
18, 19, 20
Notes
18. The six consecutive addresses must be in the order listed. W must be high during all six consecutive cycles to enable a nonvolatile cycle.
19. While there are 15 addresses on the STK14D88, only the lower 14 are used to control software modes
20. I/O state depends on the state of G. The I/O table shown assumes G low.
Document Number: 001-52037 Rev. ** Page 10 of 17
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STK14D88
nvSRAM Operation nvSRAM
The STK14D88 nvSRAM is made up of two functional components paired in the same physical cell. These are the SRAM memory cell and a nonvolatile QuantumTrap™ cell. The SRAM memory cell operates like a standard fast static RAM. Data in the
SRAM can be transferred to the nonvolatile cell (the STORE operation), or from the nonvolatile cell to SRAM (the RECALL operation). This unique architecture allows all cells to be stored and recalled in parallel. During the STORE and RECALL operations SRAM READ and WRITE operations are inhibited. The
STK14D88 supports unlimited read and writes like a typical
SRAM. In addition, it provides unlimited RECALL operations from the nonvolatile cells and up to 200K STORE operations.
SRAM READ
The STK14D88 performs a READ cycle whenever E and G are low while W and HSB are high. The address specified on pins
A
0-16
determine which of the 32,768 data bytes will be accessed.
When the READ is initiated by an address transition, the outputs will be valid after a delay of t
AVQV
(READ cycle #1). If the READ is initiated by E and G, the outputs will be valid at t
ELQV
or at
, whichever is later (READ cycle #2). The data outputs will t
GLQV repeatedly respond to address changes within the t
AVQV
access time without the need for transitions on any control input pins, and will remain valid until another address change or until either
E or G is brought high, or W or HSB is brought low.
SRAM WRITE
A WRITE cycle is performed whenever E and W are low and HSB is high. The address inputs must be stable prior to entering the
WRITE cycle and must remain stable until either E or W goes high at the end of the cycle. The data on the common I/O pins
DQ
0-7
will be written into memory if it is valid t
DVWH end of a W controlled WRITE or t
DVEH controlled WRITE.
before the
before the end of an E
It is recommended that G be kept high during the entire WRITE cycle to avoid data bus contention on common I/O lines. If G is left low, internal circuitry will turn off the output buffers t
WLQZ
W
goes low.
after
AutoStore Operation
The STK14D88 stores data to nvSRAM using one of three storage operations. These three operations are Hardware Store
(activated by HSB), Software Store (activated by an address sequence), and AutoStore (on power down).
AutoStore operation is a unique feature of Cypress Quantum
Trap technology is enabled by default on the STK14D88.
During normal operation, the device will draw current from V to charge a capacitor connected to the V
CAP
CC
pin. This stored charge will be used by the chip to perform a single STORE operation. If the voltage on the V
CC
pin drops below VSWITCH, the part will automatically disconnect the V
CAP
pin from V
CC
. A
STORE operation will be initiated with power provided by the
V
CAP
capacitor.
Figure 12 shows the proper connection of the storage capacitor
(V
CAP
) for automatic store operation. Refer to the DC CHARAC-
TERISTICS table for the size of the capacitor. The voltage on the
V
CAP
pin is driven to 5V by a charge pump internal to the chip. A pull up should be placed on W to hold it inactive during power up.
To reduce unneeded nonvolatile stores, AutoStore and
Hardware Store operations will be ignored unless at least one
WRITE operation has taken place since the most recent STORE or RECALL cycle. Software initiated STORE cycles are performed regardless of whether a WRITE operation has taken place. The HSB signal can be monitored by the system to detect an AutoStore cycle is in progress.
Figure 12. AutoStore Mode
V
CC
V
CAP
V
CC
W
Hardware STORE (HSB) Operation
The STK14D88 provides the HSB pin for controlling and acknowledging the STORE operations. The HSB pin can be used to request a hardware STORE cycle. When the HSB pin is driven low, the STK14D88 will conditionally initiate a STORE operation after t
DELAY
. An actual STORE cycle will only begin if a WRITE to the SRAM took place since the last STORE or
RECALL cycle. The HSB pin has a very resistive pull up and is internally driven low to indicate a busy condition while the
STORE (initiated by any means) is in progress. This pin should be externally pulled up if it is used to drive other inputs.
SRAM READ and WRITE operations that are in progress when
HSB is driven low by any means are given time to complete before the STORE operation is initiated. After HSB goes low, the
STK14D88 will continue SRAM operations for t
DELAY t
DELAY
. During
, multiple SRAM READ operations may take place. If a
WRITE is in progress when HSB is pulled low, it will be allowed a time, t
DELAY
, to complete. However, any SRAM WRITE cycles requested after HSB goes low will be inhibited until HSB returns high.
If HSB is not used, it should be left unconnected.
Software STORE
Data can be transferred from the SRAM to the nonvolatile memory by a software address sequence. The STK14D88 software STORE cycle is initiated by executing sequential E controlled READ cycles from six specific address locations in exact order. During the STORE cycle, previous data is erased and then the new data is programmed into the nonvolatile elements. Once a STORE cycle is initiated, further memory inputs and outputs are disabled until the cycle is completed.
Document Number: 001-52037 Rev. ** Page 11 of 17
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STK14D88
To initiate the software STORE cycle, the following READ sequence must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0FC0, Initiate STORE Cycle
Once the sixth address in the sequence has been entered, the
STORE cycle will commence and the chip will be disabled. It is important that READ cycles and not WRITE cycles be used in the sequence. After the t
STORE cycle time has been fulfilled, the
SRAM will again be activated for READ and WRITE operation.
Software RECALL
Data can be transferred from the nonvolatile memory to the
SRAM by a software address sequence. A software RECALL cycle is initiated with a sequence of READ operations in a manner similar to the software STORE initiation. To initiate the
RECALL cycle, the following sequence of E controlled READ operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x0C63, Initiate RECALL Cycle
Internally, RECALL is a two-step procedure. First, the SRAM data is cleared, and second, the nonvolatile information is transferred into the SRAM cells. After the t
RECALL
cycle time, the
SRAM will once again be ready for READ or WRITE operations.
The RECALL operation in no way alters the data in the nonvolatile storage elements.
Data Protection
The STK14D88 protects data from corruption during low-voltage conditions by inhibiting all externally initiated STORE and
WRITE operations. The low-voltage condition is detected when
V
CC
<V
SWITCH
.
If the STK14D88 is in a WRITE mode (both E and W low) at power-up, after a RECALL, or after a STORE, the WRITE will be inhibited until a negative transition on E or W is detected. This protects against inadvertent writes during power up or brown out conditions.
Best Practices
nvSRAM products have been used effectively for over 15 years.
While ease-of-use is one of the product’s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices:
■ The nonvolatile cells in an nvSRAM are programmed on the test floor during final test and quality assurance. Incoming inspection routines at customer or contract manufacturer’s sites will sometimes reprogram these values. Final NV patterns are typically repeating patterns of AA, 55, 00, FF, A5, or 5A.
End product’s firmware should not assume an NV array is in a set programmed state. Routines that check memory content values to determine first time system configuration, cold or warm boot status, etc. should always program a unique NV pattern (e.g., complex 4-byte pattern of 46 E6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently.
■ Power up boot firmware routines should rewrite the nvSRAM into the desired state (autostore enabled, etc.). While the nvSRAM is shipped in a preset state, best practice is to again rewrite the nvSRAM into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, etc.).
■ If AutoStore has been firmware disabled, it will not reset to
“autostore enabled” on every power down event captured by the nvSRAM. The application firmware should re-enable or re-disable autostore on each reset sequence based on the behavior desired.
■ The V
CAP
value specified in this data sheet includes a minimum and a maximum value size. Best practice is to meet this requirement and not exceed the max V
CAP
value because the nvSRAM internal algorithm calculates V
CAP
charge time based
value. Customers that want to use a larger on this max V
CAP
V
CAP
value to make sure there is extra store charge and store time should discuss their V
CAP
size selection with Cypress to understand any impact on the V
CAP a t
RECALL
period.
voltage level at the end of
Low Average Active Power
CMOS technology provides the STK14D88 with the benefit of power supply current that scales with cycle time. Less current will be drawn as the memory cycle time becomes longer than 50 ns.
Figure 13 shows the relationship between I
CC
and
READ/WRITE cycle time. Worst-case current consumption is shown for commercial temperature range, V
CC
= 3.6V, and chip enable at maximum frequency. Only standby current is drawn when the chip is disabled. The overall average current drawn by the STK14D88 depends on the following items:
■ The duty cycle of chip enable
■ The overall cycle rate for operations
■ The ratio of READs to WRITEs
■ The operating temperature
■ The V
CC
level
■ I/O loading
Document Number: 001-52037 Rev. ** Page 12 of 17
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STK14D88
Figure 13. Current versus Cycle Time
50
40
30
20
10
0
Writes
Reads
50 100 150 200 300
Cycle Time (ns)
Noise Considerations
The STK14D88 is a high-speed memory and so must have a high-frequency bypass capacitor of 0.1 µF connected between both V
V
SS
CC
pins and V
SS
ground plane with no plane break to chip
. Use leads and traces that are as short as possible. As with all high-speed CMOS ICs, careful routing of power, ground, and signals will reduce circuit noise.
Preventing AutoStore
The AutoStore function can be disabled by initiating an
AutoStore Disable sequence. A sequence of READ operations is performed in a manner similar to the software STORE initiation. To initiate the AutoStore Disable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x03F8, AutoStore Disable
The AutoStore can be re-enabled by initiating an AutoStore
Enable sequence. A sequence of READ operations is performed in a manner similar to the software RECALL initiation. To initiate the AutoStore Enable sequence, the following sequence of E controlled or G controlled READ operations must be performed:
1. Read Address 0x0E38, Valid READ
2. Read Address 0x31C7, Valid READ
3. Read Address 0x03E0, Valid READ
4. Read Address 0x3C1F, Valid READ
5. Read Address 0x303F, Valid READ
6. Read Address 0x07F0, AutoStore Enable
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (Hardware or Software) needs to be issued to save the AutoStore state through subsequent power down cycles. The part comes from the factory with AutoStore enabled.
In all cases, make sure the READ sequence is uninterrupted. For example, an interrupt that occurs in the sequence that reads the nvSRAM would abort this sequence, resulting in an error.
Document Number: 001-52037 Rev. ** Page 13 of 17
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STK14D88
Part Numbering Nomenclature
STK14D88 - R F 45 I TR
Packaging Option:
TR = Tape and Reel
Blank = Tube
Lead Finish
Temperature Range:
Blank - Commercial (0 to 70°C)
I - Industrial (-40 to 85°C)
Speed:
25 - 25 ns
35 - 35 ns
45 - 45 ns
F = 100% Sn (Matte Tin) ROHS Compliant
Package:
N = Plastic 32-pin 300 mil SOIC (50 mil pitch)
R = Plastic 48-pin 300 mil SSOP(25 mil pitch)
Ordering Codes
Part Number
STK14D88-NF25
STK14D88-NF35
STK14D88-NF45
STK14D88-NF25TR
STK14D88-NF35TR
STK14D88-NF45TR
STK14D88-RF25
STK14D88-RF35
STK14D88-RF45
STK14D88-RF25TR
STK14D88-RF35TR
STK14D88-RF45TR
STK14D88-NF25I
STK14D88-NF35I
STK14D88-NF45I
STK14D88-NF25ITR
STK14D88-NF35ITR
STK14D88-NF45ITR
STK14D88-RF25I
STK14D88-RF35I
STK14D88-RF45I
STK14D88-RF25ITR
STK14D88-RF35ITR
STK14D88-RF45ITR
Description
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SOP32-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
3V 32Kx8 AutoStore nvSRAM SSOP48-300
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
35 ns
45 ns
25 ns
35 ns
45 ns
25 ns
35 ns
45 ns
Access Times Temperature
25 ns Commercial
35 ns
45 ns
Commercial
Commercial
25 ns
35 ns
45 ns
25 ns
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Commercial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Industrial
Document Number: 001-52037 Rev. ** Page 14 of 17
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STK14D88
Package Diagrams
0.050[1.270]
TYP.
16
17
0.810[20.574]
0.822[20.878]
Figure 14. 32-Pin (300 Mil) SOIC (51-85127)
PIN 1 ID
1
0.292[7.416]
0.299[7.594]
0.405[10.287]
0.419[10.642]
DIMENSIONS IN INCHES[MM]
REFERENCE JEDEC MO-119
32
PART #
S32.3 STANDARD PKG.
SZ32.3 LEAD FREE PKG.
MIN.
MAX.
SEATING PLANE
0.090[2.286]
0.100[2.540]
0.026[0.660]
0.032[0.812]
0.004[0.101]
0.0100[0.254]
0.004[0.101]
0.014[0.355]
0.020[0.508]
0.021[0.533]
0.041[1.041]
51-85127 *A
0.006[0.152]
0.012[0.304]
Document Number: 001-52037 Rev. ** Page 15 of 17
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Package Diagrams
(continued)
Figure 15. 48-Pin (300 Mil) SSOP (51-85061)
STK14D88
51-85061-*C
Document Number: 001-52037 Rev. ** Page 16 of 17
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STK14D88
Document History Page
Document Title: STK14D88 32Kx8 AutoStore™ nvSRAM
Document Number: 001-52037
Revision
**
ECN
Orig. of
Change
Submission
Date
2668632 GVCH 03/04/2009 New data sheet
Description of Change
Sales, Solutions, and Legal Information
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Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.
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© Cypress Semiconductor Corporation, 2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-52037 Rev. ** Revised March 02, 2009 Page 17 of 17
AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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