COMPUTERS, INCORPORATED

LITTLE BOARD/PLUS

TECHNICAL MANUAL

Part Number: A74010

Revision: B

67 East Evelyn Ave .• Mountain View, CA 94041 • (415) 962-0230

PREFACE

This manual is for integrators of systems based on Little Board/PLUS. It contains information on hardware requirements and interconnection, and details of how to use the system. There are five chapters, organized as follows:

ChapterlGENERAL DESCRIPTION: General information pertaining to the

Little Board/PLUS, its major features, and a brief functional description of the board.

Chapter 2 - INTEGRATING A SYSTEM: Descriptions of the external components necessary to construct a CP/M-based system with floppy and hard disk drives. Included are tables listing the pinouts of each of the six board connectors, as well as features and special considerations concerning the board's peripheral interfaces.

Chapter 3 - USING THE SYSTEM: System power-up procedures, and operation with AMPRO's enhanced CP/M operating system and utilities.

Chapter 4 - THEORY OF OPERATION: Detailed technical information on Little

Board/PLUS hardware.

Chapter 5 - PROGRAMMER'S REFERENCE: I/O port addresses and programming information regarding custom programming of Little Board/PLUS.

Only brief descriptions and instructions regarding the Little Board/PLUS system software are provided in this manual. For full details on the AMPROsupplied system software, please refer to the Z80 System Software User's

Manual (AMPRO part number A 74006).

PLEASE NOTE

Specifications are subject to change without notice. The contents of this document are believed to be accurate. If errors are found, please notify

AMPRO COMPUTERS INC., at the address shown on the title page of this document.

The following is a list of trademarks used within this document:

Z80: Zilog, Inc.

CP/M: Digital Research, Inc. mM: International Business Machines

ZCPR3: Richard L. Conn

LITTLE BOARD, LITTLE Board/PLUS, SCSI/PLUS: AMPRO Computers, Inc.

No part of this document may be reproduced in any form, for commercial purposes without the express written consent of AM PRO Computers, Inc.

Copyright (C) 1985, A.PRO COMPUTERS INCORPORATED

T ABLE OF CONTENTS

CHAPTER 1 - GENERAL DESCRIPTION

1.1 Introduction

1.2 Features

1.3 Functional Description

1.3.1 CPU, Memory, and Timing

1.3.2 Serial I/O Ports

1.3.3 Parallel I/O Port

1.3.4 Floppy Disk Controller

1.3.5 SCSI/PLUS Multi-Master Bus

1.4 Specifications

CHAPTER 2 - INTEGRATING A SYSTEM

2.1 Introduction

2.2 What Is Needed

2.2.1 DC Power

2.2.2 Reset, Power LED

2.2.3 Parallel Printer

2.2.4 Serial Ports

2.2.5 Floppy Disk Interface

2.2.6 SCSI/PLUS Interface

2.2.7 ID Input Port

2.3 Board Jumper Configurations

2.4 Booting the System

2.5 Troubleshooting

CHAPTER 3 - USING THE SYSTEM

3.1 Introduction

3.1.1 Software References

3.1.2 Conventions

3.2 First Time Use

3.2.1 Making Backup Disks

3.2.2 Customizing Your System Disk

3.3 Operating System Features

3.3.1 CP/M 2.2 BDOS

3.3.2 AMPRO Custom BIOS

3.3.3 ZCPR3 Command Processor

3.4 AMPRO-Supplied Utilities

3.4.1 CP/M Utilitiy Programs

3.4.2 AMPRO Utilities

3.4.3 ZCPR3 Utilities

3.4.4 Public Domain Programs

3.5 Generating Different Systems

CHAPTER 4 - THEORY OF OPERATION

4.1 Introduction

4.2 CPU, Memory, and Timing

4.3 Board Control Register

4.4 Serial Ports

4.5 Parallel Printer Port

4.6 Floppy Disk Interface

4.7 SCSI/PLUS lnterface

4-1

4-1

4-2

4-2

4-3

4-4

4-4

2-1

2-1

2-1

2-3

2-3

2-3

2-3

2-4

2-4

2-5

2-7

2-8

1-1

1-1

1-2

1-2

1-2

1-2

1-3

1-3

1-4

3-1

3-1

3-1

3-2

3-2

3-3

3-4

3-4

3-4

3-5

3-8

3-8

3-9

3-10

3-11

3-11

CHAPTER 5 PROGRAMMERS' REFERENCE

5.1 Introduction

5.2 ZSOA CPU

5.3 Memory

5.4 Board Control Register

5.5 Counter/Timer Circuit

5.6 Serial Ports

5.7 Baud Rate Generation

5.S Floppy Disk Interface

5.9 Parallel Printer Port

5.10 ID Input Port

5.11 SCSI/PLUS Interface

5.11.1 SCSI (SASI) Programming

5.11.2 Simple Bidirectional I/O

APPENDIX A - BOARD DIAGRAM, PARTS LIST, AND SCHEMATIC

5-1

5-1

5-1

5-2

5-3

5-3

5-4

5-5

5-5

5-5

5-6

5-6

5-7

APPENDIX B - TYPICAL INTERFACE CABLES

APPENDIX C - USER GROUPS

ApPENDIX D - COMPONENT DATA SHEETS

CHAPTER 1

GENERAL DESCRIPTION

1.1 INTRODUCTION

This chapter provides an overview and functional description of the AMPRO

Little Board/PLUS single board computer. It is intended to provide a basic understanding of the Little Board/PLUS, and how it forms the basis of a compact, powerful computer system.

1.2 FEATURES

Little Board/PLUS is a complete 8-bit, Z80-based single board microcomputer.

It includes all the circuitry, software, and firmware necessary to construct a functional CP/M-based computer system. Some of the main features are:

.4MHz Z80A 8-bit microprocessor

• 64K bytes dynamic RAM, 4K -32K EPROM

• Two spare counter/timer channels

• Floppy controller capable of controlling from one to four single- or doubl~-sided, single- or double-density, 40- or 80-track mini or micro floppy drives

• Two RS232C serial ports

• One Centronics printer port

• SCSI/PLUS multi-master I/O expansion bus:

• SASI Disk/Tape controller compatible

• ANSC X3T9.2 (SCSI) compatible

• Multiple Little Board networking

• Simple bi-directional I/O (17 lines)

• Mounts directly to a 5-1/4" disk drive

• Minimum external components

• Power connector and voltages compatible with 5-1/4 inch disk drives

1.3 FUNCTIONAL DESCRIPTION

The following paragraphs briefly describe the Little Board/PLUS single board computer. More detailed information can be found ,in Chapter 4, Theory of

Operation.

1-1

1.3.1 CPU, Memory, and Timing

The heart of the Little Board/PLUS is a Z80A 8-bit microprocessor operating at

4 MHz. All system functions are based on a single 16 MHz master clock.

System RESET is provided in two ways: upon power-up and via an external RESET switch.

Two types of memory are present: EPROM and RAM. A single 28-pin EPROM socket provides from 4K to 32K bytes of firmware space. Jumpers are used to program the socket for a 2732, 2764, 27128, or 27256 type EPROM. The EPROM can be enabled and disabled by software.

System RAM consists of eight 64k x 1 bit dynamic RAM devices. Control circuitry for the RAM memory is entirely digital (no one-shots or R-C components) and provides a high degree of reliability.

A ZSO Counter Timer Circuit (CTC) provides four programmable counter or timer channels. Two of the CTC channels provide the baud rate clocks used by the two serial I/O ports. The other two CTC channels are available for use as programmable timers in applications programs, for real-time clock functions, etc.

1.3.2 Serial Ports

A Z-SO Dual Asynchronous Receiver/Transmitter (DART) provides two fully programmable serial I/O ports. Each channel has four of the standard RS232C signals: TxD, RxD, RTS, and CTS. These signals are sufficient for interfacing most serial printers, modems, and terminals. In those cases where other interface signals are required for one of the serial ports, handshaking

·signals can be borrowed from the second port (if not needed by that port).

Polarity and use of the handshaking signals is defined by the software.

Programmable baud rate clocks are supplied by the CTC for baud rates up to

9600 baud. Additional circuitry provides baud rates of 19.2K and 3S.4K baud, for Port A only. Since the two serial ports are otherwise identical, either can be programmed as a terminal, modem, serial printer, or other RS232C interface.

1.3.3 Parallel Printer Port

The parallel printer port provides the 10 essential signals of a Centronicstype printer interface: Data Bits I-S, Data Strobe, and Busy. Both the Data

Strobe (output) and Busy (input) handshake protocols are defined by software.

1.3.4 Floppy Disk Controller

A Western Digital 1772 floppy disk controller device provides all of the functions required to interface with standard 5-1/4 inch "mini" -- and most 3 to 4 inch "micro" -- floppy disk drives. The 1772 includes the following capabilities within a single LSI device:

1-2

• Digital phase locked loop

• Digital write precompensation

• Motor on start/stop delay

• Software controlled step rates

Timing for the floppy disk interface is derived directly from the 8 MHz system

. clock, without delay lines, R-C time constants, or one-shots. This again results in a very high degree of system reliability.

1.3.5 SCSI/PLUS Multi-Master Bus

A 50-pin "ribbon cable bus" interface which meets the specifications for the popular Small Computer System Interfaces (SCSI) -- formerly called "SASI" -provides a general purpose multi-master I/O expansion bus. All SCSI Initiator and Target functions are fully supported, including bus arbitration and dis-

. connect/reselect.

In addition, Little Board/PLUS supports the Initiator function of AMPRO's innovative SCSI/PLUS extension to SCSI. This allows connection of up to 64

SCSI/PLUS Target devices, rather than the usual eight device limit of SCSI.

Applications include both direct and shared use of a wide variety of controllers and devices, as well as tightly coupled Little Board networks. For example, one or more Little Boards, an SCSI Winchester controller, and modules providing calendar/clock, serial port expansion, RAM disk, etc., might all coexist on the same SCSI/PLUS bus.

The 17 bidirectional I/O signals of the SCSI/PLUS interface may also be used as general purpose software-controlled digital I/O lines, without SCSI compatibility. In this case the board's 8-bit SCSI bus ID input register can serve as an additional 8-bit input port.

1-3

1.4 LITTLE BOARD/PLUS SPECIFICATIONS

CPU:

MEMORY:

TIMER:

SERIAL I/O:

4MHz Z80A, 8-bit microprocessor

64 kilobytes of dynamic RAM

4-32 kilobytes of EPROM

Z80A CTC (4 channels)

2 channels not used by AMPRO software

Z80A Dual Asynchronous Receiver/Transmitter (DART)

Two - RS232C compatible ports: DB-25 female conns.

Software-controlled baud rates:

Channel A - 75 to 38,400 baud

Channel B - 75 to 9600 baud

Four standard RS232C signals per port:

Data Out

Data In

Handshake Out

Handshake In

Two Ground pins

PARALLEL I/O: Centronics-compatible printer port

10 signals supported:

Data Bits 1-8 - output

Data Strobe - output

Printer Busy - input

12 Ground pins

DISK I/O: No. drives supported:

Disk Controller:

Data rate:

1 - 4

WD1772

250k bps (MFM), 125K bps (FM)

Sector size:

Phase locked loop:

128, 256, 512, or 1024 bytes digital (8 mHz)

Write precompensation: software enabled

Drive capacity (formatted):

Type 1 (40 track, 1-sided) - 200K bytes

Type 2 (40 track, 2-sided) - 400K bytes

Type 3 (80 track, 1-sided) - 400K bytes

Type 4 (80 track, 2-sided) - 800K bytes

SCSI/PLUS BUS INTERFACE:

POWER:

SASI Compatible

ANSI X3T9.2 (SCSI) compatible

SCSI/PLUS Initiator compatible

Uses NCR 5380 SCSI bus controller

Same power connector and voltabes as mini and micro floppy disk drives.

Power Requirements: +5VDC at O.95A

+9 to 12VDC at 0.05A

ENVIRONMENT: Temperature: 0 to 32 degrees C, operating

Humidity: 5 to 9596, non-condensing

Altitude: 0-10,000 feet

1-4

SIZE: ' 7.75 x 5.75 x 0.75 inches

SOFTWARE: Boot program in 2732 EPROM

CP/M Version 2.2 and BIOS on diskette

Little Board/Plus system utilities

Option: FRIENDLY Integrated Operating Environment

Option: BIOS and Utilities source code

DOCUMENTATION: Little Board/Plus Technical Manual

Little Board/Plus Software Manual

Option: SCSI/PLUS Technical Specification

1-5

CHAPTER 2

INTEGRA TING A SYSTEM

2.1 INTRODUCTION

This chapter describes what is required to build a floppy or hard disk based computer system using Little Board/PLUS as the heart of the machine. Details are provided concerning external device requirements, the boards connector pinouts, how to prepare the board for use, and connection of peripherals such as terminals, printers, and modems. Refer to Appendix B for tables.

2.2 WHAT IS NEEDED

A very minimum number of external parts will turn the Little Board/PLUS circuit board into a very powerful computer system. The items listed in Table

2-1 are easily available components.

Item

Floppy drive(s)

SCSI (SASI) hard disk controller

(option)

Hard disk drive(s)

(option)

Power supply

Reset switch

Cables

Cabinet

Table 2-1. System Components

Description

1 to 4 mini or micro floppy drives, 40 or 80 track, single- or double-sided

Adaptec ACB-4000 or Xebec 1410(A), or equivalent

SCSI (SASI) hard disk controller

5 to 20 Megabyte drive(s); must be compatible with your specific SCSI (SASI) controller

+12VDC @ 2.0A, +5 VDC @ 2.5A (2 floppies); additional power, as required for hard disk options

SPST, normally open, w/LED indicator

Serial (2), parallel, floppy, SCSI, and power cables for Little Board/PLUS and drives

Housing for completed system

Figure 2-1 shows the Little Board/PLUS interface connectors. All components can be housed in a very small box. The size is determined primarily by the disk drives, and perhaps the power supply. A space of approximately 7 x 8 x

11 inches is adequate for a dual floppy system. Tables 2-2 through 2-7 list the cable connector pinouts for the board's interface connectors. Table 2-2 provides suggested mating connectors and manufacturers' part numbers.

2-1

Board

Table 2-2. External Connector Part Numbers

Function Part Number

Connector

J1 Power Connector Housing: AMP 1-480424-0

Contacts: AMP 60619-1

(4 req.)

J2 Parallel Printer,

Board end

3M: 3399-6000

T&B: 609-2601M

Molex: 15-29-8262

J3,4

Parallel Printer,

Printer end

Serial Ports A,B

AMP:

3M:

T&B:

57F-30360

3366-1001

609-36M

Housing: Molex 22-01-2067

Contacts: Molex 08-50-0114

(6 req.)

J5

J6

J8

RESET, Power LED Housing: Molex 22-01-2047

Contacts: Molex 08-50-0114

(4 req.)

Floppy Disk Interface 3M: 3463-0001

(Card edge connectors) T&B: 609-3415M

Molex: 15-29-0341

SCSI/PLUS Interface T&B: 609-5000M

Molex: 15-29-8502

Berg: 66902-150

NOTE

All Little Board/PLUS s,oftware is distributed on doublesided 48 tpi AMPRO format mini floppy diskettes. This may be directly read from, or booted, in either a 48 or 96 tpi mini floppy drive. The only special requirement for first

time booting of the system is that you have a double-sided

48 or 96 tpi mini floppy drive capable of stepping at a 6 mS step rate, and a terminal capable of 9600 baud operation. Once you have initially booted the system, you may then generate a system disk with alternative defaults, e.g., single-sided, micro floppy, 12 mS step rate, 19.2K baud terminal data' rate, etc.

2-2

PARALLEL PRINTER

J

.0

---POWER

• o

~~--SERIAL

A

SERIAL B

~-+---RESET. POWER LED

...

'----- m

INPUT

Figure 2-1. Little Board/PLUS Connector Locations.

2-3

2.2.1 DC Power

The power connector (Jl) pinout is identical with that of the power connectors on nearly all 5 -1/4 inch floppy disk drives. Note that pin 1 on Jl is reversed from the other connectors on the same end of the board. Refer to

Table 2-3 for power connections.

CAUTION

BE SURE THE POWER PLUG IS CORRECTLY WIRED BEFORE

ATTEMPTING TO APPLY POWER TO THE BOARD.

Table 2-3. Power Connections (.11)

Pin Signal Name

1

2

3

4

+12VDC

Ground

Ground

+5VDC

Function

+6 to + 15VDC

Ground return

Ground return

+5VDC +/- 5%

2.2.2 RESET, Power LED

This connector is for connection to an external SPST switch, to provide the master RESET signal. In addition, a 15 rnA current source provides power to an

LED power-on indicator. Refer to Table 2-4 for the pinout of connector J5.

Pin

1

2

3

4

Table 2-4. RESET, Power LED Connector (.15)

Signal Name Function

Ground

LED

Ground

RESET

To LED Cathode

To LED Anode

To one side of RESET switch

To other side of RESET switch

2.2.3 Serial Ports

Table 2-5 lists the connector pinout and signal definitions for each of the two RS232C serial I/O ports. Serial Port A is board connector J3, and Serial

Port B is board connector J4. Appendix B gives typical cable wiring for connection to terminals, serial printers, and modems.

2-4

1

2

3

4

5

6

Pin

Table 2-5. Serial Connectors (.13/.14)

Signal Name Function

Ground

Ground

TxD

HSO

RxD

IISI

Protective Ground

Signal Ground

Data Output

Hand Shake Out (RTS)

Data Input

Hand Shake In (CTS) in/out DB-25 Pin

(DCE)

--

1

--

7 out 3 out 5 in in

2

20

2.2.4 Parallel Printer

The Little Board/PLUS parallel printer connector has a pinout that allows the use of flat ribbon cable between the J2 header and the first 26 lines of a 36 pin male Centronics-type connector at the printer end.

Refer to Table 2-6 for the printer connector's pinout and signal definitions.

Note that the pin numbering convention for the board's header connector (J2) differs from that of Centronics connectors, even though the required interconnection cable is straight through. To clarify this, each signal's corresponding Centronics connector pin number has been included in Table 2-6.

J2

Pin

9

11

13

15

1

3

5

7

.17

19

21

23

25

2-22

24,26

Table 2-6. Parallel Printer Connector (.12)

Signal Name Function in/out

-DS

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Data Strobe

LSB of printer data

·

·

·

·

Data 8 MSB of printer data

---

(Not used)

BUSY Printer BUSY

---

(Not used)

---

(Not used)

(even)

---

Signal grounds

(Not used) out out

·

·

·

·

· out in

Printer

Pin

6

7

8

9

1

2

3

4

5

11

19-29

30,31

Appendix 8 provides a wlrmg table for a cable which will work with most

Centronics compatible printers. The cable required is identical to that used with the Tandy (Radio Shack) TRS-80 Model 100 portable computer. The Tandy cable part number is 26-1409.

2-5

2.2.5 Floppy Disk Interface

Table 2-7 lists the Goppy disk drive interface connector (J6) pinout and signals. A single 34-conductor PC edgecard connector goes at the Little Board end, while there can be from 1 to 4 PC card edge connectors for connecting mini floppy disk drives. Micro Goppy drives generally use 34-conductor header connectors, instead.

Pin

Table 2-7. Floppy Disk Interface Connector ("'6)

Signal Name Function in/out

2

4

6

8

10

12

14

16

18

20

22

24

26

28

30

32

34

1-33

-LOW SPEED

---

-DRIVE DEL 4

-INDEX

-DRIVE SEL 1

-DRIVE SEL 2

-DRIVE SEL 3

-MOTOR ON

-DIR SEL

-STEP

-WRITE DATA

-WRITE GATE

-TRACK 00

-WRITE PRT

-READ DATA

-SIDE ONE

-READY

(all odd pins)

Speed select (option)

(Not used)

Drive Select 4

Index pulse

Drive Select 1

Drive Select 2

Drive Select 3

Motor on control

Direction select

Step

Write data

Write gate control

Track 00

Write protect

Read data

Side select

Drive ready (option)

Signal grounds out

-out in out out out out out out out out in in in out in

--

Nearly any type of soft-sectored, single- or double-sided, 40- or 80-track, mini (5 1/4") or micro (3" to 4") floppy disk drive is usable with the Little

Board. Naturally, the higher the quality of the drives you use, the better your system's reliability. Here are some things that may be helpful for you to know:

• As indicated earlier in this chapter,the default system parameters programmed on the standard Little Board/PLUS system disk, as shipped, require that drive A be a double-sided 48 or 96 tpi mini floppy drive, with 6 mS (or faster) stepping rate. Once you have booted that disk, you can create a new system disk with alternative defaults, allowing you to subsequently boot from any other system-compatible drive.

• The drives used must be compatible with the AMPRO floppy disk interface (see Table 2-7). This interface is generally referred to as SA-

450 compatible.

• Use of high quality floppy disk drives is recommended; preferably having DC servo-controlled direct drive motors.

• The drives must be capable of 12 mS (or faster) stepping.

2-6

• More than one type of floppy disk drive, up to four, can be present in the system, and in any mix.

• Each disk drive must be jumpered for a specific Drive Select value, 1 through 4. Drive A is 1, B is 2, etc.

• Resistive terminations should be installed only on the drive connected to the last interface cable connector (farthest from the computer).

• When using drives with a Head Load option, jumper the drives for "head load with motor on" rather than "head load with drive select" jumpering.

2.2.6 SCSI/PLUS Interface

The SCSI/PLUS interface (J8) uses a 50-pin male header connector to interface with SCSI-compatible peripherals. Table 2-8 shows the signal names and pin numbers for the SCSI/PLUS bus interface connector. Refer to your disk controller documentation, or the ANSI SCSI (X3T9.2) specification, for information on the signal functions.

Table 2-8. SCSI Interface Connector (.18)

Pin Signal Function

1 - 49

2

4

6

8

10

12

14

16

18

(All odd pins)

-DBO

-OBI

-DB2

-DB3

-DB4

-DB5

-DB6

-DB7

-DBP

20,22,24 Ground

25

---

26 TERMPWR

28,30 Ground

32 -ATN

34

36

Ground

-BSY

38

40

-ACK

-RST

42

44

46

48

50

-MSG

-SEL

-C/D

REQ

-I/O

Signal grounds

Data Bit 0 (LSB)

" " 1

" " 2

" " 3

" " 4

" " 5

" " 6

" " 7 (MSB)

Data Parity

Signal Ground

(Not used)

Termination +5 VDC

Signal Ground

Attention

Signal Ground

Busy

Transfer Acknowledge

Reset

Message

Select

Control/Data

Transfer Request

Data direction

2-7

This interface can serve a variety -of purposes, including connection of hard disk controllers, tape controllers, printer and communication servers, etc.

In addition, the interface signals may be used as direct input/output lines, allowing the connection of TTL-level interfacing devices and sensors, etc.

The output signals are open collector, 48mA drivers, and may be enabled and disabled under software control. On-board removable resistor networks provide bus termination.

2.2.1 ID Input Port

Eight pairs of jumper pins (J 7) provides an ID Input Port, which can be used by SCSI-related software to determine the board's SCSI bus ID for bus arbitration (or other) purposes. If not required for this purpose the ID Input Port can be used as a general purpose 8-bit input port connector, with a flat ribbon cable connector plugged onto J7. Table 2-9 shows the signal names and pin numbers for J7.

Table 2-9. ID Input Port ( ... 1)

Pin Signal Function

1

3

5

7

9

11

13

15

2-16

-ID7

-ID6

-ID5

-ID4

-ID3

";ID2

-IDI

-IDO

Ground

ID Bit 7 (MSB)

" " 6

" " 5

" " 4

" " 3

" " 2

" " 1

" " o

(LSB)

Signal Ground

2.3 BOARD JUMPER CONFIGURATIONS

Little Board/PLUS contains nine sets of jumpers, which may be used to customize the board's operation. The jumper sets consist of either two or three pins, with pin 1 a square pad; each jumper set is outlined with white boxes on the component side of the "board. The options available through these jumpers are described in the following paragraphs.

NOTE

Do not solder wires to the jumper pins, as this may void your board's warranty. Use wire wrap, or snorting plugs instead.

2-8

For normal operation, no jumper setup is required. All of the jumper settings are factory-set, by means of shorting plugs on the pins, or traces on the bottom side of the board. Use of J7 (SCSI bus ID) varies, according to software requirements. AMPRO's standard hard disk software does not require the use of J7.

"IIPI - Clock

This jumper, when shorted, connects the system 16 mHz master clock bus to the

16 mHz hybrid oscillator (U2). It is intended for test purposes only.

FACTORY SETTING: shorted

"IIP2 - CTC CLK/TRG3

This jumper connects the CTC's CLK/TRG3 input (JMP2-2) to either the 1772

FDC's interrupt request output signal (JMP2-3) or to the CTC's ZC/TC2 output signal (JMP2-1).

FACTORY SETTING: both options open

JIIP3 - CTC CLK/TRG2

This jumper, when shorted, connects the 5380 SCSI controller's interrupt request output signal (JMP3-2) to the CTC'S CLK/TRG2 input (JMP3-1).

FACTORY SETTING: open

JMP4 - U6 Option

This jumper is shorted for 8 mHz -only operation of the 1772 FDC device. NOTE:

If this jumper is shorted, the clock multiplexor IC, U6 must not be present; if U6 is present, this jumper must be open.

FACTORY SETTING: open (U6 present)

JMP5,6 - EPROM Type

These jumpers are used to program the board for various types of EPROM devices. These two jumpers are set as shown in Table 2-10.

2-9

Table 2-10. EPROM Jumper Configurations

EPROM Type JMP5: 1-2 JMP5: 2-3 JMP6

2732

2764

27128 open

* short short

* open

* open open short open short 27256

Factory setting: open short open

Notes

(1) Items indicated by

* can be open or shorted; however do not short both

JMP5 options simultaneously.

(2) When a 2732 24-pin EPROM is used, it must be plugged into the lower 24 pins of the 28-pin EPROM socket, so that the 2732's pin 1 plugs into pin 3 of the socket. dMP7 - DART RIA

This jumper, when shorted, connects the 1772 FDC's DRQ output singal (JMP7-2) to the DART's RIA input (JMP7-1).

FACTORY SETTING: open dllP8 - DART DCDA

This jumper, when shorted, connects the 5380 SCSI controller's DRQ output singal (JMP8-1) to the DART's RIA input (JMP8-2).

FACTORY SETTING: open dllP9 - SCSI Termination Power

This jumper, when shorted, connects the board's +5V DC power to the SCSI bus signal line provided for optional external termination.

FACTORY SETTING: open

2-10

JMP10,11 - 1772 Reset

These jumpers provide a choice of hardware or software control of the 1772

FDC's master reset input. Shorting JMPI0 connects the board's hardware -RESET signal (JMPI0-l) to the 1772's reset input (JMPI0-2). Shorting JMPll connects the DART's DTRB output (JMPll-2) to the 1772's reset input (JMPll-l).

FACTORY SETTING: JMPI0 shorted, JMPll open (hardware RESET)

U17,22 SCSI Bus Termination

These two 14-pin sockets contain resistive termination networks for SCSI bus termination. Every SCSI bus should have one set of termination at each end of the bus. These net works should be removed from the board if the bus is terminated by two other devices. If the SCSI interface will not be required, power may be saved by removing these termination networks, along with the 5380

SCSI controller, from the board. For non-SCSI use, the 220/330 termination networks may also be replaced with alternate values.

NOTE

The on-board resistive termination networks (UI7, U22) should be present on two, and only two, SCSI bus devices.

Be sure that the board's SCSI bus is terminated in at least one place (generally on the board); a non-terminated

SCSI bus may "hang" the system up due to indeterminate signal levels.

2.4 BOOTING THE SYSTEM

With the system completed, only connection to a terminal and a source of power for the computer are required. Typical cable wirings for connection to terminals, serial printers, and modems appear in Appendix B.

To boot from the standard distribution diskette, set your terminal as follows:

Baud Rate: 9600

Data Bits: 8

Parity: off

Stop Bits: 1

If your terminal provides the choice, set it so that the data bit 8 is transmitted as a 0 ("low" or "space"). Some terminals do not provide such an option, automatically sending a zero for data bit #8 when parity is off. The

AMPRO BIOS ordinarily masks the MSB when 8 bit transmission is selected, but you may choose to do otherwise. (Requires BIOS source code, available from

AM PRO).

2-11

Connect the terminal to Serial Port A. If a modem is being connected, use

Serial Port B. First time booting of the system requires that you connect a serial terminal capable of meeting the above specifications. As will be explained in Chapter 3, system boot parameters can be customized, but initially the system comes up with Serial Port A set for 9600 baud.

With a terminal connected and turned on, the system is ready to boot. When power is applied, a program in the EPROM will attempt to read the operating system from disk. If no disk is in the drive, the system will wait until a disk is in place, and drive latch closed. The system will then read the CP/M operating system from the disk in drive A.

IMPORTANT

See note in Table 2-1 concerning floppy drive requirements for booting the distribution system diskette.

If the drive's LED lights but nothing else happens, try inserting the flipside of the disk and pressing RESET. If this doesn't help, refer to the next section for troubleshooting information.

2.5 TROUBLESHOOTING

It is possible that the completed system does not work the first time. If you have to troubleshoot it, here are some suggestions:

• Recheck all wiring, soldered connections.

• Check that power is available from the power supply.

. B e certain that the drives are working, and are jumpered correctly.

NOTE: ffiM PC drives are not jumpered in a "standard" manner; the drive cable has swapped drive select wires. For use with Little

Board/PLUS, be sure drive A is jumpered as Drive Select 0, B as 1, etc.

• If both drive indicators light during power-up, with drive handles closed (across slot), the drive signal cable is probably reversed on the board's floppy interface connector (J6). Switch the computer OFF and reverse the drive cable connector at the Little Board/PLUS.

• Check the drive termination resistor pack(s) for proper location.

Normally, this will be located at the drive connected at the end of the drive cable.

• If you have the debugging Monitor EPROM option, you can verify some of the system functions using the debugger and other tools in the

Monitor.

In the event that your system still does not boot after following all of these instructions, contact AMPRO customer service for assistance.

2-12

CHAPTER 3

USING THE SYSTEM

3.1 INTRODUCTION

Assuming you have successfully booted CP/M as described in Chapter 2, you will probably want to take advantage of the flexibility designed into the Little

Board/PLUS CP/M BIOS and utilities to customize your system diskette.

This chapter explains how to install your operating system software for various system configurations, making use of standard CP/M and ZCPR3 utilities and the Little Board/PLUS utilities software supplied on the system software diskette.

3.1.1 Software References

Only brief references are made in this manual to the use and operation of the required software utilities. Whenever a software utility is mentioned, it will either be called an AMPRO utility, a CP/M utility, or a ZCPR3 utility.

This way you will know where to obtain further information on the program's use.

Full descriptions and operating instructions for the AMPRO software utilities are found in the AMPRO Z80 System Software User's Manual, AMPRO part number

A74006.

Some recommended CP/M and ZCPR3 references are:

CP/M Primer, by Stephen M. Murtha and Mitchell Waite (Howard W. Sams)

CP /M Handbook, by Rodnay Zaks (Sybex Inc.)

CP/M Revealed, by Jack D. Dennon (Haydon Publishing)

ZCPR3: The Manual, by R. L. Conn (Echelon Inc. - Phone: 415/948-3820)

3.1.2 Conventions

In the descriptions of the use of software utilities, terminal keyboard inputs which you will make to the system are shown underlined. This has been done to make it easy for you to distinguish between the computer's prompts and the operator's keystrokes. For example:

AO>DIR <RETURN>

Also, certain keys on your terminal's keyboard have special uses. The control key, generally labeled CTRL, is meant to be pressed at the same time as one other key. The required control key combination will be represented as follows: <CTRL-C> = control key pressed along with C key.

3-1

Two other special keys are the "escape" key, indicated by <ESC> and the

"return" key (also called the "carriage return" or "enter" key), indicated by

<RETURN>. In general, all commands you enter from the CP/M (or ZCPR3) command prompt require you to press <RETURN> key to begin the operation, as in the example above.

3.2 FIRST TIME USE

Chapter 2 discussed connecting the completed system to terminal, a modem, and initial power-up. Assuming the computer works, there are two things it is recommended that you do immediately:

1. Make a backup copy of the disks included with the Little Board/PLUS.

2. Customize your system diskette.

3.2.1 Making Backup Disks

It is always a good idea to have at least one backup copy of all floppy disks.

This is especially true of your master system disks. The exact procedure you use to make backup disks depends on your system configuration. Here are three methods:

Method 1: Two identical format types.

When making a backup in which the source and destination disks will be the same floppy format (i.e., 48 to 48 tpi, or 96 to 96 tpi), the backup can easily be made with the Copy function of the AMPRO AMPRODSK utility. The only catch is that AMPRODSK requires the source and destination to be the same floppy format and drive type. One exception is that double-sided drives can be used to copy from or to single-sided floppy formats. The AMPRODSK Copy funtion even formats the destination disk for you. Simply follow the instructions given by the program when you run it.

NOTE

AMPRODSK can not read 48 tpi disks in 96 tpi drives. • Use

Method 2.

Method 2: Two different drive types.

You can backup a source disk onto a different floppy format (e.g. 96 tpi backup of 48 tpi disk or visa versa), as follows:

1. Use the AMPRODSK utility's Format function to format a fresh disk having the desired destination format, in the destination drive.

2. Use a file copy utility (CP/M PIP, ZCPR3 DISK7, ZCPR3 MCOPY,AMPRO

FRIENDL Y, etc.) to copy all files from the source to the destination disk.

3-2

3. If the source disk is a system disk, use the AMPRO SYSGEN utility to copy the source system tracks to the destination system tracks.

Method 3: Single-drive S~stems.

If you have a system with only one disk drive, you can do nearly anything that can be done with two or more drives. For example, a backup of your system software diskette can be made as follows:

1. Use the AMPRO AMPRODSK utility's Format function to format a blank disk. The program will indicate what you need to do.

2. Use the AMPRO SWAPCOPY utility to copy all files from the source disk system disk to the backup disk. The required command is:

AO>SWAPCOPY

*.*

<RETURN>

3. Use the AMPRO SYSGEN utility to copy the system tracks from the source disk to the backup disk. The program will indicate what to do.

3.2.2 Customizing Your S~stem Disk

When using your system for the first time, some of the system initial default values are probably not perfect for your system configuration. The AM PRO

CONFIG utility allows you to easily modify the serial port setups (baud rates, handshaking, etc.), printer port assignment (serial or parallel), floppy drive step rates, and automatic powerup/reset command.

NOTE

Any modifications to the system parameters should only be performed using your backup disks. Do not use the disks shipped with your Little Board/PLUS.

One important parameter to be sure to set correctly is the floppy disk drive step rate. Initially, the system disk is set up for, and boots with, a step rate of 6 mS. Check your drive's step rate specification, and set the default step rate to the one that is closest to the drive's specification. The CONFIG utility will guide you through its use.

You will also want to customize the terminal characteristics definition file,

MYTERM.Z3T, so that it matches your terminal. This is done with the ZCPR3

TCSELECT or TCMAKE utilities. The menu which displays when you boot your system will look better, and write to the screen faster, once you have created a MYTERM.Z3T file for your terminal.

3-3

3.3 OPERATING SYSTEM FEATURES

The operating system included with the Little Board/PLUS is an enhanced version of standard CP/M version 2.2. One major difference is that the user command line interface (Console Command Processor, CCP) is replaced by an enhanced Z80 Command Processor Replacement called ZCPR3. The Little

Board/PLUS operating system consists of three portions:

CP/M 2.2 BDOS: Standard CP/M file and device management facility

AMPRO Custom BIOS: Enhanced Basic I/O System

ZCPR3 CCP: Z80 Command Processor Replacement version 3

3.3.1 CP/M 2.2 BDOS

The heart of the Little Board/PLUS operating system is the Basic Disk

Operating System (BDOS), which is the normal CP/M 2.2 BDOS. This is the part of the operating system that interacts with programs. Because this is completely standard CP/M 2.2, all software programs designed to work with CP/M

2.2 will run without modification, provided they do not contain hardwaredependant routines.

3.3.2 AMPRO Custom BIOS

The CP/M Basic I/O System (BIOS) takes care of all hardware-dependant operating system functions. Many features of the Little Board/PLUS CP/M operating system are the result of a highly flexible, sophisticated BIOS implementation.

Here are a few:

Automatic Format Sensing - Single- and double-sided, 40- and 80- track disks and drives may be intermixed freely. The BIOS senses what format is present, and adjusts accordingly. 40-track (48 tpi) diskettes may even be read (but not written) in 80-track (96 tpi) drives. NOTE: CP/M requires that you use a

<CTRL-C> keystroke when you change diskettes.

Alien Format Support - One disk drive can be assigned as an "emulating" drive, so that you can read from or write to your choice of non-AMPRO format.

Hard Disk Support (Optional) - You can add one or more hard disk controllers and drives to your system. The BIOS contains generic SCSI (SASI) support, making it compatible with a wide variety of devices, and has been structured to maximize the flexibility of this function.

Power-up Port Defaults - You can easily alter the system power-up I/O port defaults (console baud rate, printer port assignment and setup, etc.) using the AMPRO configuration utility.

Power-up Auto-Command - A single command can be specified to run automatically on system power-up or reset. This is one of the options available through the

AMPRO configuration utility.

3-4

IOBYTE Implementation - The IOBYTE can be changed by the CP/M STAT utility, to reassign logical I/O devices to physical I/O devices. Table 3-1 lists the standard CP/M logical-to-physical device assignments and choices, as supported in the Little Board/PLUS BIOS.

Table 3-1. Logical-to-Physical I/O Assignments

Logical Device Physical Device Choices Default

CON:

RDR:

PUN:

LST:

Where:

CRT: or TTY:

TTY: (input)

TTY: (output)

CRT: or TTY: or LPT:

CRT:

TTY:

LPT:

=

Serial Port A

=

Serial Port B

=

Parallel Printer Port

CRT:

TTY:

TTY:

LPT:

As implemented, the IOBYTE allows two choices for console port (Serial Port A or Serial Port B), and two choices for printer port (Serial Port A, Serial

Port B, or Parallel Printer Port).

In addition, the AMPRO CONFIG utility program allows you to set the IOBYTE either temporarily, or in the cold-boot defaults on the system tracks of a disk.

3.3.3 ZCPR3 Command Processor

The normal CP/M console command processor (CCP) has been replaced with the more powerful Z80 Command Processor Replacement, version 3 (ZCPR3). As indicated in Table 3-2, the ZCPR3 implementation differs slightly from standard

CP/M, but can be used in the much same way you would use standard CP/M. If you wish to eliminate the ZCPR3 enhancement, you can do so through the use of the AM PRO MOVCPM utility. (Refer to the AMPRO Z80 System Software User's

Manual for information on how to do this.)

Your system software includes only part of the full power of the ZCPR3 System; the full ZCPR3 System occupies several megabytes of disk! The following paragraphs cover the ZCPR3 features that are present in the standard Little

Board/PLUS operating system software. Additional ZCPR3 options can be easily added, as discussed in the AMPRO Z80 System Software User's Manual. Contact

Echelon Inc. (Phone: 415/948-3820) for additional ZCPR3 information and support. ZCPR3 utilities and information are also available at no charge through many CP/M and ZCPR3 user groups and bulletin board systems (see

Appendix C).

3-5

Table 3-2. ZCPR3/CCP Command Comparison

Function ZCPR3 Command CCPCommand

Display all files

Display files in specific DU

Erase specified file

Erase with verify

DIR

DIR DU:

ERA DU:afn

ERA DU:afn V

DIR

No equivalent

ERA D:afn

No equivalent

Rename file REN DU:ufn=ufn2 REN D:ufn=ufn2

Rename file over existing file REN DU:ufn=ufn2 No equivalent

Print file on console

Without paging

Print file on console

With paging

TYPE DU:ufn P

TYPE DU:ufn

TYPE D:ufn

No equivalent

Save memory into file

Save memory into file and specify siz e in hex

Save memory into file and specify number of blocks

Change disk

Change user

Change disk and user at same time

SAVE n DU:ufn

SAVE nB DU:ufn

SAVE n DU:ufn S No equivalent or

SAVE nB DU:ufn S

D:

U:

DU:

SAVE n D:ufn

No equivalent

D:

USER n

No equivalent

DU: - Drive number,User number (e.g., AO:, B15:, C:, 13:) ufn - Unambiguous file name (e.g., MYFILE. TXT, DIR.COM) afn - Ambiguous file name (e.g., *.COM, MYFILE.*, M??ILE.T?T)

Sub-Directories

Each floppy disk has a directory of files; each directory can contain up to 16 sub-directories (also called user areas), numbered 0 through 15. Normal CP/M uses the USER command to change between the 16 possible sub-directories, with the default being O. ZCPR3 uses a directory label formed from the combination of the drive letter (A, B, etc.) and user area (0,1, etc.). This is called a drive-user, or "DU" expression. For example, AO represents drive A user area

0, while B15 corresponds to drive B user area 15.

Using ZCPR3, the current drive and user area are displayed in the command prompt. Instead of using CP/M's USER command to change user areas, you do it in the same way that you change drives. In addition, whenever you use the DU expression, you may omit either the letter or number portion, if that part of the expression is the same as the current one. For example:

3-6

AO>B15:<RETURN>

B15 >O:<RETURN>

BO:A:<RETURN>

AO>

In addition, functions such as directory (DIR), erase (ERA), rename (REN), etc., allow the DU form as destination and source directory designations.

Another powerful feature of ZCPR3 is the option of "named" sub-directories.

When the named directory option is present, a directory name can be substituted for the DU expression in all command line inputs. This feature is not present in the AMPRO system software as shipped, but can be easily added.

Please refer to the above-mentioned software references for further information.

Directory Utility

In AMPRO's ZCPR3 implementation, the DIR utility is not an "intrinsic"

(internal) function, but requires the presence of the ZCPR3 DIR.COM utility on disk. As you will notice as soon as you use this command, the DIR utility has quite a few nice features, such as alphabetical file sorting and direct access to any directory. For example

AO>DIR B5:<RETURN> displays the directory of drive B, user area 5 (sorted alphabetically!).

Also, since the directory utility is disk-based rather than internal, you can select from a large assortment of public domain directory utilities -- simply rename your favorite one "DIR.COM".

Multiple Commands per Line

With ZCPR3, multiple commands may be given on a single command line, with semi-colons (;) used as separators. For example, the sequence

AO>DIR;ERA *.BAK;DIR<RETURN> runs the directory program, erases all files with the .BAK type, and then runs the directory program a second time.

Command Search Path

ZCPR3 also uses an automatic command search path. This means that programs referenced on the command line may be located anywhere along a pre-defined command search path. You can be logged onto drive B, and execute a program on drive A, without typing the drive prefix for the program drive. The default search path is:

3-7

current drive, current user current drive, user 0 drive A, current user drive A, user 0 drive A, user 15 current drive, user 15

Since the search path covers both different drive letters and different user area numbers, you can "hide" programs and utilities in different user areas.

This results in cleaner looking directories. A common practice is to "hide"

COM files (programs) in user 15. Such files will not be visible from user 0, but will execute from user O.

NOTE

Some application programs must be run from the same drive letter and user area as the files they will be used with, or require additional programs, overlays, or files to be present in the same directory (drive and user area) as the program itself.

The ZCPR3 DISK7 and MCOPY, and the AMPRO FRIENDLY utilities can be used to copy files directly between user areas. The ZCPR3 PATH utility allows you to easily change the search path as needed.

Intrinsic Commands

With the exception of the DIR and USER commands noted above, all standard CP/M version 2.2 intrinsic commands are implemented, as well as some additions.

Table 3-2 lists the ZCPR3 commands versus those of the standard CP/M CCP.

Aliases

One of the most powerful features of ZCPR3 is the use of aliases. This feature is made possible by the multiple command line capability. An "alias" is a disk-resident multiple command line. The alias has. a command file name, such as FUNCTION.COM, but represents a pre-programmed set of commands. Whenever you run the alias,you get the set of commands. It is like a fast, memory-based submit, or batch, facility. By using an alias (usually

STARTUP.COM) as the CONFIG auto-command, you can have a complex sequence of functions automatically initialize your system on power-up or reset.

Shells

ZCPR3 also provides shell support. A. "shell" is a substitute operating environment. Examples of ZCPR3-compatible shells are ZCPR3 MENU, VMENU, and

VFILER, and AMPRO FRIENDLY. A shell is a program that always reloads following the execution of any program, rather than returning you to the command prompt. Once a shell is loaded, you might never see the AO> prompt again! ZCPRa shells provide varying levels of isolation of the user from the

3-8

operating system, and can even completely replace the CCP interface. The powerful MENU shell program is included on your system diskette.

Termcap Facility

ZCPR3 adds another powerful feature to CP/M which is lacking in most microcomputer operating systems: a termcap facility. The AMPRO CP/M implementation contains a special buffer area in memory which is used by ZCPR3 to standardize terminal display control codes. This allows application programs to be terminal-independent, providing the software is written to take advantage of the

ZCPR3 termcap. The ZCPR3 utilities TCSELECT and TCMAKE are used to create a termcap file, usually called MYTERM.Z3T. The ZCPR3 utility LDR is used to load the appropriate term cap file into memory, for use by compatible programs.

3.4 AMPRO-SUPPLIED UTILITIES

A powerful set of software programs is sipplied with the Little Board/PLUS.

This section contains brief descriptions of each. They include:

• the standard CP/M 2.2 software set

• the AMPRO Little Board/PLUS utilities

• several key ZCPR3 utilities

• several public domain programs

The programs described below are those included on the Little Board/PLUS system software diskette at the time of this writing (hard disk software is optional). Actual contents may vary. Complete descriptions and operating instructions are provided in the publications listed in the introduction to this chapter. Program and program description updates are available from

AM PRO on an on-going basis, at nominal charge. Contact AMPRO for information.

3.4.1 CP/M Utility Programs

Included with the Little Board/PLUS are all the standard CP/M utility programs:

ASM.COM Standard assembler for 8080 instructions. May be used to assemble

Little Board/PLUS source code.

DDT.COM Dynamic Debugging Tool: standard CP/M debugger.

DUMP.COM Permits display of a file in hexadecimal values.

ED.COM Standard CP/M line editor. May be used to edit Little Board/PLUS source code.

3-9

LOAD.COII Converts .HEX file output of the ASM program to an executable .COM file.

PIP.COII Permits single or multiple disk-to-disk file transfers. Also portto-port and port-to/from-disk transfers.

ST AT .COII Status of disk and other I/O devices. Also may be used to set file attributes.

SUBIiIT .COII Permits execution of multiple commands and parameters stored in a disk file.

XSUB.COII For use with SUBMIT .COM, to allow passing of parameters direct to programs.

3.4.2 AIIPRO Utilities

The following programs are specific to Little Board/PLUS, and used for system customization, disk formatting, disk format translation, etc. Source code is available from AMPRO at nominal cost. The hard disk utilities are available in the optional Z80 Hard Disk Software package.

AIIPRODSK.COII Used to copy, format, and verify AMPRO-format disks.

CONPIG.COM Used to modify or set your system's current or powerup default peripheral port characteristics according to your particular requirements.

Lets you set serial port A and B baud rates, data characteristics, and handshaking, floppy drive step rates, printer port choice (serial or parallel), and command for power-up or reset automatic execution.

DOS.COII Used to read and write files on MS-DOS format disks. Also used to read the directory and erase files.

DOSPMT.COII Used to format MS-DOS disks in all standard formats.

ESET .COII Permits reading and writing of data to and from disk formats other than those available with the MULTIDSK.COM utility. (See MULTIDSK.COM)

BPORMA T .COII (optional) - Hard disk formatting program.

HINIT .COII (optional) - Hard disk controller and system initialization utility.

HPARK.COII (optional) - Hard disk drive head parking utility. Moves the head to an unused area of the disk drive's surface· prior to system shut down, to prevent data loss from head crash.

MOVCPII.COM Configures the operating system for a user-definable memory size.

Same as ZMOVCPM.COM, except contains the standard CP/M CCP. Used as part of the procedure for generating a hard disk system, if ZCPR3 is not desired.

IIULTIDSK.COM Provides compatibility with other computers' disk formats.

After MULTIDSK is run, you can read from or write to the selected alien format by using the drive letter "E" instead of the drive's normal designation (A, B, etc.).

3-10

IIULTIFIIT.COII Permits formating (and verifying) disks using non-AMPRO formats.

SET .COII Allows setting of current serial port characteristics (baud rate, data characteristics, hand shaking) and assignment of printer port (serial or parallel). Similar to CONFIG.COM, but all parameters are given from the command line, thus allowing use with ALIASes, MENU lines, etc.

SWAP.COII Re-assigns CP/M disk drive letters, swapping them in pairs.

SYSGEN.COM Used to write the AMPRO CP/M operating system tracks onto a disk.

Allows source of the system tracks to be either another disk's system tracks, a disk file, or a memory image (generally placed in memory by MOVCPM or

ZMOVCPM).

ZIIOVCPII.COII Configures the operating system for a user-definable memory size. Same as MOVCPM.COM, except contains the standard ZCPR3 CCP replacement.

Used as part of the procedure for generating a hard disk system.

3.4.3 ZCPR3 Utilities

The following ZCPR3 utilities are included on the Little Board/PLUS system disk. Source code is available from ECHELON Inc. (415/948-3820) at nominal cost.

ALIAS.COII Used to create or modify multiple command line files (aliases).

DIR.COII Displays contents of disk directories. Allows direct drive/user area (D U) access.

DIFF.COII File compare utility. Checks two files for differences.

DISK7.COII Easy to use disk file management utility. Includes a menu of single-keystroke commands for Copy, Rename, Delete, Length, and drive Status.

LDR.COII Used to load terminal definition files (e.g. MYTERM.Z3T), system environments, and other system-resident ZCPR3 files.

IICOPY.COII General purpose file copying program. Allows direct file movement between directories (e.g. AO to B15).

IIENU.COM Powerful system menu shell program.

PATH.COII Modifies command search path.

TCMAK.E.COM Used to create non-standard terminal definition files (e.g.

MYTERM.Z3T).

TCSELECT.COM Used to select a standard terminal definition file from a menu of standard terminals.

UNERA.COM command.

Recovers deleted disk files. Inverse of the ERA (erase)

3-11

WHEEL.COM Sets user privileges. (Required to use PATH.COM to change command search paths.)

Z3INS.COM ZCPR3 installation utility. Installs other ZePR3 utilities for your operating system configuration. AMPRO-suplied ZCPR3 utilities do not require installation prior to use with the standard AMPRO-supplied operating system.

ZEX.COM Memory-resident submit facility,similar to CP/M's SUBMIT utility, but more powerful.

3.4.4 Public Domain Programs

Several valuable public domain programs have also been included. Source code for these programs is available through CP/M user groups and bulletin board systems (see Appendix C).

FINDBAD.COII Bad sector lockout program for use in mapping out hard disk drive surface defects. Creates a file [UNUSED).BAD containing all bad sectors.

IIDII740.COII General purpose, powerful communication program. Modified for use with the Little Board/PLUS serial port B. (AMPRO-specific overlay is contained in the file, M&-LB.ASM.) Allows direct computer-to-computer file transfer over Rs232, or may be used with a modem. Fearures include ASCII transfer or XMODEM protocol, auto dialing, stored phone library, and more.

SD.COII Directory display utility alternative to DIR.COM. Options you may specify in the command line allow printing the directory, creating a file containing the directory, and inclusion of multiple user areas.

SWAPCOPY.COII Single drive disk-to-disk copy utility. Modified for use with

AMPRO foreign formats (allows copying from A to A, A to E, and E to A).

3.5 GENERATING DIFFERENT SYSTEMS

There are several reasons why you may wish to generate an alternate operating system:

1. Use of hard disk drives

2. Alternate ZCPR3 system configurations

3. Memory requirements of a modified BIOS or custom software

4. Substitution of standard CP/M CCP for ZCPR3 CCP

5. Generation of a larger TPA system, using the Version 1 BIOS

3-12

In the first three cases, additional buffer areas are required in high memory, above the operating system. This requires moving the operating system

down in

memory, and leaving room for the required functions. In the fourth case, the use of CP/M results in less memory required for the operating system, allowing the operating system bo be moved up in memory. In the fifth case, sligntly more program area is made available by using a BIOS with a few less features.

The AM PRO utilities MOVCPM.COM or ZMOVCPM.COM are used to relocate or regenerate the operating system. Refer to the AMPRO Z80 System Software

User's Manual for additional information on the generation of alternate CP/M configurations.

3-13

CHAPTER 4

THEORY OF OPERATION

4.1 INTRODUCTION

This chapter provides detailed information on the functional operation of

Little Board/PLUS. No information on the internal operation of the LSI components is included. Please refer to the manufacturers' data sheets (Appendix

D) for specific details. Figure 4-1 is a block diagram of Little Board/PLUS.

Chapter 5 contains programming information, and indicates the assignment of programmable device pins to specific hardware signals and functions.

Z80A

CPU

COUNTER/ 4K-32K

TIMER EPROM

64K

RAM

\ t t

~

INTERNAL BUS t

FLOPPY DUAL

CONTROLLER UART

PARALLEL SCSI/PLUS

TII

PRINTER BUS

PORT INTERFACE

,v34

6,

I, ~6 ,~26 ,~50

RESET

-=

+5V

-'-

-

330n

,:!:;-

+5VDC

+12VDC

GROUND

RESET

SWITCH

$

POWER

LED

1-4

FLOPPY

DISK

DRIVES

PORTA PORTB

TERMINALS, CENTRONICS-

MODEMS, COMPATIBLE

PRINTERS,

ETC.

PRINTER

)1/0

EXPANSION BUS

HARD DISK, TAPE, NETWORKS, •••

Figure 4-1. Little Board/PLUS Block Diagram

4.2 CPU, MEMORY, AND TIMING

The main system time base is provided by a 16 MHz oscillator module. A binary counter provides three system clocks: 8 MHz, 4 MHz, and 2 MHz. The 4 MHz signal is used by the Z80A, Counter Timer Circuit (CTC), and Dual Asynchronous

Receiver/Transmitter (DART) devices. The 8 MHz signal provides the normal clock input to the 1772 Floppy Disk Controller (FDC).

4-1

The Z80A interrupt "daisy chain" is implemented in accordance with the standard Zilog protocol, using the peripheral devices' Interrupt Enable Input and Interrupt Enable Output signals. Several of the CTC and DART input lines have jumper options which allow those devices to optionally function as interrupt controllers for a number of floppy and SCSI interface signals. (See the jumpering information in Chapter 2.)

All control signals for the 64K dynamic RAM are derived from the system's 4 and 8 MHz clocks and the Z80A refresh output signal. RAM devices with access times up to 200 nS can be used. The Z80A generates the required 7-bit refresh addresses and timing required by the 64K by 1 bit dynamic RAM devices.

When a memory read or write occurs with address line A15 set to zero, and bit

6 of the Board Control Register is set to zero, memory address decoding logic selects the EPROM rather than RAM. In addition, a wait state generator becomes active whenever the EPROM is selected, permitting the use of EPROM device access times up to 450 nS.

A programmable array logic (PAL) device and a pair of two-to-four decoders generate the device select addresses for all of the Little Board's I/O devices. Table 4-1 shows the device select addresses in binary. Where XIS are indicated in the table entries, the corresponding address bit may be a 1 or a O. I/O address groups indicated as "unused" are available for I/O expansion via the Z80A CPU socket. There are 40 unused I/O addresses. A summary of the I/O ports, addresses and functions, are shown in Table 4-2.

Table 4-1. I/O Device Addresses

Device Select

Board Control Register

Parallel Port Data Latch

Parallel Port Strobe Set

Parallel Port Strobe Clear

(Unused)

(Unused)

5380 Chep Select

5380 DMA Acknowledge

ID Input Port

(Unused)

CTC

DART

FDC

I/O Address (Binary)

0000 OXOO

0000 OX01

0000 OXIO

0000 OXU

0000 1XXX

0001 XXXX

0010 OXXX

0010 1XXO

0010 1XX1

0011 XXXX

01XX XXXX

10XX XXXX llXX XXXX

4-2

Address

Table 4-2. Summary of I/O Ports

Input/Output Function

OOh

01h

02h

03h

20-27h

28h

29h

40h

50h

60h

70h

80h

84h

88h

8Ch

COh

Clh

C2h

C3h

C4h

C5h

C6h

C7h

Output

Output

Output

Output

I/O

I/O

Input

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Output

Output

Output

Output

Input

Input

Input

Input

Board Control Register

Parallel Printer Data Register

Parallel Printer Data Strobe Set

Parallel Printer Data Strobe Clear

SCSIControllerlnternal Registers

SCSI Controller "DMA" Read/Write

ID Input Port

CTC Channel 0

CTC Channell

CTC Channel 2

CTC Channel 3

DART Channel A Data

DAR T Channel A Control

DART Channel B Data

DART Channel B Control

FDC Command Register

FDC Track Register

FDC Sector Register

FDC Data Register

FDC Status Register

FDC Track Register

FDC Sector Register

FDC Data Register

NOTE

The I/O device addresses for these ports are not unabiguously decoded. Refer to Table 4-1.

4.3 BOARD CONTROL REGISTER

The Board Control Register (BCR) is a simple octal output latch which controls several board functions. Seven of the eight bits of the BCR control are associated with the floppy disk interface: drive selects (4), side select, density select, and 1772 clock select. These are discussed in the section about the floppy disk interface (below). One bit in the BCR also serves to enable or disable the EPROM device. All outputs of the BCR are cleared (to 0) by the board's RESET signal, selecting the EPROM at power-up or when the RESET signal is active.

4.4 SERIAL PORTS

A Z80A dual asynchronous receiver/transmitter (DART) forms the basis of two

RS232C serial I/O ports. Baud rates for these ports are generated by the Z80A

CTC. Channel A of the DART has an alternate baud rate clock source

(614.385kHz), which is obtained by dividing the 16 MHz system clock by 104.

This provides serial channel A with two additional baud rates: 19,200 and

38,400 baud, as well as 9600 baud.

4-3

Baud rate selection is accomplished by programming the CTC time constants, selecting the CTC channel mode (counter or timer), programming the DART prescale factor (16, 32, or 64), and, for serial I/O channel A, selecting either the high or low speed baud rate mode. The high/low baud rate mode of channel A is controlled using the DTRA output of the DART.

DAR T R TSA and R TSB output signals generate each channel's output handshake signal, while CTSA and CTSB provide the two channels' handshake inputs.

RS232C signal levels are converted to and from TTL levels by a 75188/1488 line driver and 75189/1489 line receiver. An on board -12 volt DC-to-DC converter provides the -12VDC power for the line driver.

Several of the DART's input and output signals are used for purposes not associated with serial communications:

• DCDA and RIA are available as optional interrupt sources

• DCDB is available for reading the optional floppy disk ready signal

• RIB is used to sence the parallel printer Busy signal

4.5 PARALLEL PRINTER PORT

An octal D-latch with a 24 rnA output current sinking capacity is used to drive the eight parallel printer port data lines. In addition, there are two handshaking signals: Data Strobe (output) and Busy (input).

The Data Strobe output is generated by a flip-flop which is set and reset by software. This permits software controlled timing of data relative to strobe, and strobe polarity. The printer Busy input is sensed by the RIB input of the

DART.

4.6 FLOPPY DISK INTERFACE

Nearly all of the logic required for the floppy disk interface is provided by the Western Digital 1772 Floppy Disk Controller (FDC) device. Only the drive and side-selection and interface input signal buffering require additional devices.

The Board Control Register (BCR) controls the state of the four drive select lines, the side select line, the 1772 density select input, and the 1772 master clock input rate. In principle, by switching the 1772 master clock rate to 16 mHz, single-density eight inch disk drive data rates (250 kbits/sec) are possible. However, the current version of the 1772 is not guaranteed to function properly with a 16 mHz input clock, so the use of this option is not recommended at this time.

The floppy disk interface Ready signal connects to the DART DCDB input signal.

This can be optionally used with floppy disk drives which provide this signal.

The AMPRO Little Board/PLUS BIOS does not use this option.

4-4

4.1 SCSI/PLUS INTERFACE

The SCSI/PLUS multi-master bus interface consists of an SCSI bus controller IC

(NCR 5380) and an 8-bit jumperable bus ID input port. All of the signals of the SCSI/PLUS expansion bus interface connect directly to pins of the 5380 bus controller IC.

A 74LS244 is used as an ID input port, allowing the state of eight jumpers to be read under software control. Alternatively, this port may be used for general purpose input sensing.

The 5380 integrates approximately 20 components in a single 40-pin package.

It allows full programmable control of 17 bi-directional bus signals, and provides both buffered (low leakage) bus inputs and high current (48 mAl bus output drive capacity. A pair of socketed 220/330 ohm termination networks provide optional on-board SCSI bus termination.

The 5380 is fully compatible with the ANSC X3T9.2 (SCSI) standard, including all roles and all phases. In addition, the 5380 can support the Initiator role of the proposed SCSI/PLUS enhancement to SCSI, but not the SCSI/PLUS

Target role.

You can obtain a copy of the NCR 5380 SCSI Interface Chip Design Manual from:

NCR Microelectronics - (303) 596-5612 or (800) 525-2252

You may also wish to obtain a copy of the ANSI SCSI specification. Copies of this standard may be obtained by sending $20, and a self-addressed mailing label (for each copy desired) to:

The X3 Secretariat

Computer and Business Equipment Manufacturers Association

311 First Street, N.W. - Suite 500

Washington, DC 20001

In addition, the SCSI/PLUS Preliminary Technical Specification, which details

AMPRO's proposed enhancement to SCSI to allow 64 (rather than 8) bus devices, is available from AMPRO.

4-5

CHAPTER 5

PROGRAMMER'S REFERENCE

5.1 INTRODUCTION

This chapter discusses programming techniques and peripheral device register addresses and requirements. Programming most Little Board/PLUS devices is straight forward. However, the floppy disk controller is relatively complex to program; we recommend that you modify the BIOS and utilities source code

(available from AMPRO) rather than create custom floppy disk drivers. For more complete information on device functions not covered here, refer to the data sheets in Appendix D of this manual.

5.2 Z80A CPU

The Z80A 8-bit CPU operates at a 4.00 MHz clock rate. No wait states occur during RAM access; one wait state occurs for each EPROM access.

The Z80A's non-maskable interrupt (NMI) input is not connected; only maskable interrupts can occur. All maskable interrupt modes are supported. The Z80 interrupt priority daisy chain is fully implemented, with the following prioritization:

• The CTC device has the highest interrupt priority, with each channel sub-prioritized: channel 0 is highest, channel 3 lowest.

• DART Channel A (middle priority)

• DART Channel B (lowest priority)

A number of jumper options on the board allow interrupts to be registered from the floppy and SCSI interface controller devices. These jumpers allow the

CTC's channel 2 and 3 clock inputs, and the DART's external status inputs (RIA and DCDA) to be used as optional interrupt sources. This allows a variety of interrupt sources, each with its own prioritization and vectoring. Refer to the jumpering information in Chapter 2, and to the board schematic, for more details.

5.3 MEMORY

When the EPROM enable bit in the Board Control Register is low, the EPROM is enabled in the lower 32K bytes of RAM. When the EPROM is enabled, the EPROM contents are repeated reduntantly throughout the lower 32K bytes of memory.

When the EPROM enable bit in the BCR is high, the EPROM disappears, leaving

64K bytes of RAM.

5-1

5.4 BOARD CONTROL REGISTER

An eight bit register Board Control Register (BCR) controls seven FDC related functions, and provides the EPROM enable/disable control. A write to I/O address OOh immediately changes the state of the BCR's eight output signals, which are defined in Table 5-1.

Table 5-1. Board Control Register Programming.

Bit 7 6 5 4 3 2 1 0

Signal FDCHI EPROM DDEN SIDEI DS4 DS3 DS2 DSI

Bit Signal Function

7 FDCHI

6

5

4

3

2

1

0

-EPROM

-DDEN

SIDEI

DS4

DS3

DS2

DSI

FDC Controller master clock select: o =

8 mHz; 1

=

16 mHz

EPROM Enable

o

= enabled; 1

= disabled

Double density enable: 0

= enabled

Floppy drive side select o = side 0; 1

=

Drive Select 4, 1 side 1

= select drive 4

Drive Select 3, 1

Drive Select 2, 1

Drive Select 1, 1

= select drive 3

= select drive 2

= select drive 1

FDCHI (data bit 7) allows the master clock input to the 1772 to be switched between 8 MHz (FDCHI = 0) and 16 MHz (FDCHI = 1). This theoretically allows the 1772 to function at eight-inch floppy drives, when its clock is set to 16

MHz. However, the 1772 is currently not guaranteed to work reliably with a 16

MHz clock. It is therefore not recommended that you use this capability at this time. If you do attempt to switch the 1772's clock input, we suggest the following algorithm:

1. Read and store 1772 internal register contents. Note whether the motor on bit is active.

2. Deselect all drives.

3. Re-write BCR with new speed

4. Re-write BCR with desired drive select.

5. Restore 1772 register contents. Be sure to restore. the condition of the motor activity (i.e., turn it on with a null seek, etc., if it was on previously.

The reading and restoring of the 1772 registers, and restoration of motor on status, protect against corruption during clock switches. The deselection of drives is done to p~otect media from accidental write pulses during clock switches.

The signals controlled by the BCR are utilized as follows:

5-2

-EPROM (data bit 6) enables the EPROM and disables the lower 32K bytes of

RAM, when a 0 is written to data bit 6 of the BCR, and visa versa, when a 1 is written to that bit.

-DDEN (data bit 5) places the 1772 in double density operation when a 0 is written to data bit 5 of the BCR, and single density when a 1 is written to that bit.

SIDE1 (data bit 4) - selects side one of the floppy media when it is set to 1, and. selects side 0 of the floppy media when it is set to O.

DS4-DSI (data bits 3-0) - select one of four drive units when the corresponding bit is set to 1. Do not set more than one drive select to 1 at anyone time.

On power-up or RESET, all bits in the board control register are automatically cleared (set to O's).

5.5 COUNTER/TIMER CIRCUIT (CTC)

The CTC device contains four independent counter/timers addressed at I/O addresses 40h, 50h, 60h, and 70h, as shown in Table 5-2.

Table 5-2. CTC Register Addresses

Address

40H

50H

60H

70H

CTC Channel

0

1

2

3

All Channels are read/write

The CTC master clock is the 4.00 MHz system clock. The Clock input for

Channels 0 and 1 is 2.00 MHz. Each of the four addresses is both a read and' a write register representing one of the CTC channels. It is through these locations that the CTC is programmed. The CTC has the following assigned channel functions and options:

CTC Channels 0 and 1 - Baud rate generators for DART Channels A and B, respectively. The CLK/TRG inputs for these channels are connected to 2.00

MHz. Each of these channels can be used in either the Counter or Timer mode to generate a full range of baud rates (discussed below).

CTC Channels 2 and 3 Not normally used by Little Board/PLUS software. These channels are available for use in timing functions, and may be cascaded. In addition, they may be used as interrupt controllers for floppy or SCSI functions, etc. These options can be configured using the board's jumpers.

5-3

You may use CTC channels 2 or 3 as interrupt controllers by programing the channel in Counter mode, with a count of 1, triggerable on a rising' orfaUing edge, as appropriate. Use the jumper options described in Chapter 2.

You may cascade channels 2 and 3, for accurate real time clock functions, by jumpering channel 2's ZC/TC2 output to channell's CLK/TRGI input (see jumpering information, Chapter 2).

5.6 SERIAL PORTS

A Z80 DART device forms the basis of board's two RS232C serial ports. In addition, three of the DART I/O signals support other on-board functions, and several more are available for use as general purpose interrupt sources.

The DART internal registers are accessed through four, non-consecutive I/O addresses, as shown in Table 5-3. Each register is both read and write.

NOTE

In order to read the current state of the DART external status signals (CTS, RI, DCD, etc), a Reset External

Status command must first be sent to the associated DART channel.

Table 5 -3. DART Register I/O Addresses.

Address Function

80H

84H

88H

Channel A, Data

Channel A, Control

Channel B, Data

8CH Channel B, Control

All are read/write.

5.6.1 DART Channel A Signals

DART Channel A input/output signals are utilized as shown in Table 5-4. Note that the high/low baud rate select for Channel A uses the DTRA signal, and that DCDA and RIA are available as optional interrupt sources.

5-4

Table 5 -4. DART Channel A Pin Assignment.

Signal Name DART Pin Function

Serial Port Functions:

Transmit Data

Receive Data

Handshake Out

Handshake In

Data Clock

TXDA

RXDA

RTSA

CTSA output to RS232C input from RS232C output to RS232C input from RS232C

RXCA, TXCA input from CTC ZC/TCO pin

Additional Functions:

Low Baud Select

(options)

DTRA Serial Port A baud rate mode

DCDA, RIA Optional interrupt sources

5.6.2 DART Channel B Signals

DART Channel B input/output signals are assigned as shown in Table 5-5. Note the additional functions. The floppy drive ready signal is not used by the

Little Board/PLUS BIOS.

Table 5-5. DART Channel B Pin Assignment.

Signal Name DART Pin Function

Serial Port Functions:

Transmit Data

Receive Data

Handshake Out

Handshake Input

Data Clock

Additional Functions:

Printer BUSY*

(option)

TXDB

RXDB

RTSB output to RS232C input from RS232C output to RS232C

CTSB input from RS232C

RXCB, TXCB input from CTC ZC/TCl pin

RIB

DC DB input from printer interface input from FDC interface

5.7 BAUD RATE GENERATION

Both serial ports use clocks provided by the CTC for baud rates up to 9600.

You set the channel's baud rate input clock by setting the associated CTC channel mode and time constant, and programming the DART channel prescale factor (16, 32, or 64). In addition, Serial Port A can be placed in a high speed mode, in which a 615.385 kHz signal is used as the baud rate clock input to DART channel A. This allows Serial Port A baud rates of 9600, 19.2k, and

38.4k.

5-5

NOTE

The Little Board/PLUS CP/M BIOS contains tables of DART and CTC initialization parameters, along with a BIOS call which initializes the DART and CTC devices. It is recommended that you utilize the BIOS tables and initialization call, or at least update the contents of the tables after modifying a device's operational characteristics.

5.7.1 Below 9600 Baud

Serial Port A baud rates are determined by CTC channel 0 (in that port's low speed mode), and Serial Port B baud rates are determined by CTC channell.

For Serial Port A low speed mode (baud rates of 9600 baud or less), program

DART output DTRA as a 1 (active). Program each CTC and DART channel as shown in Tables 5-6 and 5-7. For information on programming of the CTC and DART devices, refer to the device data sheets (Appendix D). Table 5 -7 lists the available baud rates through the CTC clock sources.

Table 5-6. Baud Rate Programming, up to 9600 Baud.

Device Function Setting

CTC Interrupt

CTC Mode

Disable per Table 5-7

CTC Prescaler *16

CTC CLK/TRIG edge Either

CTC Timer Trigger *Set to automatic

CTC Time Constant per Table 5-7

DART Scale Factor per Table 5-7

*

= don't cares in Counter mode

NOTE

These settings assume Channel A's low baud rate mode, obtained by setting DART output DTRA to 1.

Table 5-7. CTC and DART Scale Factors

Desired CTC Time CTC Channel DART Scale

Baud Rate Constant Mode Factor

9600

4800

2400

1200

600

300

110

13

26

52

104

208

208

142

Counter

Counter

Counter

Counter

Counter

Counter

Timer

16

16

16

16

16

32

16

Actual

Baud Rate

9615

4808

2404

1202

601

300

110

5-6

NOTE

Other combinations may be used to obtain higher, nonstandard, baud rates -- up to 125K baud.

5."1.2 Above 9600 Baud

Serial Port A can also be programmed to standard baud rates of 9600, 19.2K, and 38.4K, using the high baud rate mode. Higher, "non-standard" baud rates are also possible, by using different CTC and DART scale factors than those indicated in Table 5-7. For example, using a CTC time constant of 1 (in counter mode), and a DART scale factor of 16, results in 124.8K baud.

To select Serial Port A's the high baud rate mode, CTC Channel 0 must be turned off with a software reset, and the DART DTRA output must be cleared

(set to 0). The values shown in Table 5-8 represent the required DART Scale

Factor to be written to the DART. To program Serial Port A for the higher baud rates:

• Issue a software reset to CTC Channel O. (Write a 03H byte as a control word to CTC Channel 0.)

• Clear DART channel A's DTRA (set to 0).

• Set DART channel A's scale factor as indicated in Table 5-8.

Table 5-8. DART Channel A Settings, 8igh Baud Rate Mode

Desired DART Scale Actual

Baud Rate Factor Baud Rate

38400

19200

9600

16

32

64

38462

19230

9615

5.8 FLOPPY DISK INTERFACE

A Western Digital 1772 Floppy Disk Formatter/Controller (FDC) occupies I/O addresses COH thru C7H. Since the A2 address line is connected to the -R/W input of the 1772, read and write registers in the FDC occupy unequal addresses, as shown in Table 5-9. (This differs from the 1772 data sheet description.) The floppy interface signals associated with devices other than the 1772 are shown in Table 5-10.

5-7

Table 5-9. 1772 Register Addresses

Address Function Read/Write

COH

C1H

C2H

C3H

C4H

C5H

C6H

C7H

Command register

Track register

Sector register

Data register

Status register

Track register

Sector register

Data register

Write

Write

Write

Write

Read

Read

Read

Read

Table 5-10. Non-1772 Floppy Signals

Interface Signal

Drive select 4

Drive select 3

Drive select 2

Drive select 1

Drive Ready

Source/Destination

BCR, bit 3, output

BCR, bit 2, output

BCR, bit 1, output

BCR, bit 0, output

DART DCDB input

Due to the complexity of programming of the floppy disk interface, we recommend that you modify the standard Little Board/PLUS FDC drivers (source is available from AMPRO),rather than creating new custom routines.

5.9 PARALLEL PRINTER PORT

The parallel printer interface supports eight data output bits (D1 - D8), a

Data Strobe (output), and a printer Busy signal (input). With the exception of Busy, these signals are controlled flip-flop is cleared (Data Strobe as shown in Table 5-11. The Data Strobe

=

0) upon power-up or RESET.

Table 5-11. Parallel Printer Port Addresses

Address Function

01H 8-bit data register written to by CPU. CPU data bit 0 printer D1; bit 1

= printer D2; ••• ; bit 7

= printer D8.

=

02H A write to this address sets the data strobe flip-flop.

03H A write to this address clears the data strobe flip-flop.

The data strobe flip-flop is cleared on power-up or RESET.

5-8

The printer Busy signal is connected to the DART Rm input; the DART Channel B status register must be read for Rm status. NOTE: In order to read the current state of the printer Busy signal, DART Channel B must first be sent a

Reset External Status command. Note also that the sense of this signal is inverted: when printer Busy

=

1, Rm reads 0 (inactive); when printer Busy

=

0, Rm reads 1 (active).

5.10 ID INPUT PORT

This port can either be used for SCSI bus 10, for general purpose jumper settings, or as an 8-bit general purpose data input port.

The ID input port is read by an input from I/O address 29h. The jumpering of the eight pairs of pins at location J7 on the board determines the data byte obtained. The input buffer is non-inverting: the data read directly reflects the level on the input pin. When a jumper is inserted, the corresponding data is low (0); when out, the data bit is high (1).

Jumper assignment is as follows: J7 pins 1 and 2 corresponds to data bit 7; pins 3 and 4 are data bit 6; ••• ; pins 15 and 16 are data bit O.

5.11 SCSI/PLUS INTERFACE

The SCSI/PLUS interface is controlled by means of an NCR 5380 SCSI Protocol

Controller device. The 5380 contains 8 readable and 8 writable registers.

These are addressed as shown in Table 5-12.

Table 5-12. 5380 Internal Registers

Read Registers

Current SCSI Data

Initiator Command Register

Mode Register

Target Command Register

Current SCSI Bus Status

Bus &: Status Register

Input Data Register

Reset Parity/Interrupt

Write Registers

Output Data Register 20h

Initiator Command Register

Mode Register

Target Command Register

21h

22h

23h

Select Enable Register

Start DMA Send

24h

25h

Start DMA Target Receive 26h

Start DMA Initiator Receive 27h

Address

20h

21h

22h

23h

24h

25h

26h

27h

Address

5-9

The SCSI/PLUS interface has a wide variety of applications, including:

• use with SCSI (SASI) disk controllers and devices

• use with up to 64 SCSI/PLUS Target devices

• use as a bidirectional I/O port

• use as a multi-master network bus

If you plan to use SCSI (SASI) devices not supported by the standard Little

Board/PLUS BIOS, you can either use the SCSI BIOS call provided for that purpose, or modify the BIOS source code as required.

If you plan to use program the 5380 yourself, you will probably require a copy of the NCR 5380 SCSI Interface Chip Design Manual. Contact:

NCR Microelectronics - (303) 596-5612 or (800) 525-2252

You may also wish to obtain a copy of the ANSI SCSI specification. Copies of this standard may be obtained by sending $20 and a self-addressed mailing label (for each copy desired) to:

The X3 Secretariat

Computer and Business Equipment Manufacturers Association

311 First Street, N.W. - Suite 500

Washington, DC 20001

In addition, the SCSI/PLUS Preliminary Technical Specification, which details

AMPRO's proposed enhancement to SCSI to allow 64 (rather than 8) bus devices, is available from AMPRO.

5.11.1 SCSI (SASI) Programming

When using the SCSI/PLUS interface with SCSI (SASI) disk controllers, special programming is not generally required; the AMPRO BIOS hard disk driver and

AMPRO hard disk utilities accomodate many types of disk controllers and disk drives. Installation of the hard disk software is all that is generally required, providing you are using controller and drive types supported by the

BIOS. (Refer to AMPRO Z80 System Software User's Manual.)

When using the 5380 in SCSI (SASI) applications, care must be taken to meet the specified timing constraints. For detailed timing information, consult your peripheral controller's technical manual, or the SCSI specification referenced above. The Little Board/PLUS BIOS source code (available from

AM PRO) represents an excellent example of how to use the 5380 in SCSI applications.

5.11.2 Simple Bidirectional I/O

If you plan to prQgram the 5380 yourself,you will need a copy of the NCR 5380 design manual mentioned above. The 5380 has 17 bidirectional I/O lines, which may be used as inputs or outputs under software control.

5-10

The 5380 has two operating modes: Initiator and Target modes. In Initiator mode, several conditions are required before data output to the I/O bus can be active. If the device is used in the Target mode, however, these special conditions are not applicable. This results in more straight forward programming of simple 8-bit I/O applications, and is recommended for simple bidirectional I/O.

The 5380 is placed in Target mode by writing 40h to the Mode Register. Once in Target mode, all 17 I/O signals except ACK and A TN may be used as both inputs and outputs. In Target mode, ACK and ATN are inputs only. The data lines (DBO-7,P) are outputs when bit 0 (n Assert Data Bus") of the Initiator

Command Register is a 1, and inputs when bit 0 of that register is a O.

Eight additional inputs are available via the ID Input Port, discussed above.

Also, the parallel printer port can also provide an additional set of eight outputs and two handshake signals, if it not required as a printer interface.

5-11

APPENDIX A

BOARD DIAGRAM, PARTS LIST, AND SCHEMTAIC

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J~·:·nJ~:~·~n·:~;~·:~n'::~u:,:,u~:,. Ig~'O::<[]:~: e~u~.:: .~:":~~·:'[j'.~:·i

: :"'1::::':

.~~~u~

:

:11: :::,:',.,

~ ;!~il;':

:.0'.: :,:: :':' ::: :,:,:,: ::: :',' C" "CI': " '"

~~:: ri~" ~~~[Ju"~·~~:'~Du:~O~:~~uu~c~f~~u:.~cO~·~~·?~~·r~~' fO~~:1T

~J:

• • • • • 3 •

• s: :: :::.: .. : ::: :.'.:' : :: : : :: ••

.c::::::l ••

•

• . • • • • • • •

..

34

;';' '

I

2

2

-A

D c

•

AMPRO COMPUTERS INCORPORATED - PARTS LIST

ASSEMBLY: A60060 - Little Board Plus

DESrG.

R1, 5, 6, 7

R2

R3,R8

R4

RP1,4,5,7

RP2,:3

RP6

Ul

U2

U3

U4

U5

U6,U35

1J7

U8

U'3

U10

Ull

U12

U13

U14

U15

QTY.

A13004 1

Cl-19,21-23, 24

26,28

C20,24, 25, 27 4

CRl

J1

J2

J3,4

J5

J8

J9

1

JfY1Pl, 3, 6, 7, 8, 8

9,10,11

1

1

2

1

1

1

JMP5,2

JMP1,5,10

2

:3

1

4

2

1

4

1

2

SPARE

1

1

1

1

2

1

1

1

1

1

1

1

1

NOT USED

DESCRI PTION

PCB, AMPRO SERIES IB

CAP CER AXIAL .1UF

+80~ -20~ 50V

MRA RPA20-Z5U-104Z50

CRN CAC02Z5U104Z050A

UNI CGC104ZDZ

CAP 10UF ELC RADIAL .l00-0C UCK LL25VB10-M

20~ 25V ALB LBRIE100S-M

DIODE IN4148

CONN HDR 4POS SIL RT/AG POWER

CONN HDR 26POS .l00-0C STR

CONN HDR 6POS SIL RT/AG

CONN HDR 4POS SIL RT/AG

CONN HDR 50POS • l00-0C STR

CONN HDR 16POS .100-0C STR

MLX 8'381-4R-l

SAE THD6'326WIS

MLX 22-05-3061

MLX 22-05-3041

SAE THD6'350WIS

SAE THD6'316WIS

CONN HDR 2POS SIL • 100-0C MLX 22-10-2021

AMP 641122-2

CONN HDR 3POS SIL . 100-0C

CONN SHUNT 2POS • 100-0C

<.40 MAX HEIGHT>

RES CF 4700 5~ 1/4W

RES CF 1K 5~ 1/4W

RES CF 3'3 5~ 1/4W

RES CF 10K 5~ 1/4W

RES PK 8SIP 7-4700 5~

RES PK 8SIP 7-1K 5~

RES PK 8SIP 7-330 5~

MLX 15-38-1024

OSCILLATOR, 16.000MHZ

IC, 74F163 OR 74F161

IC, Z80A CPU

IC! l0L8/PROGRAMMED

IC, 74F00

IC, 74LS16'3

IC, 7518'3A/1489A

IC, 7518811488

HYBRID, -12VDC/DC CONVERTER

IC, Z80A CTC

IC, 2732 450nS (PROGRAMMED)

IC, WD1770 DISK CONTROLLER

IC, Z80A SIO/0 or Z80A DART

REV: A

VENDOR PIN

SRX NCT070C16MHZ

NDK TD1114A-16.00

**

NO TI

ELPAC/TDK CB3811

WESTERN DIGITAL I

DATE: 06/19/85

AMPRO PIN

TI

A13004

90514-001

'30514-001

'30514-001

90522-001

'30522-001

'30300-001

90'307-001

90907-002

90907-003

90907-004

'30907-009

90907-007

'30905-001

'30905-001

90905-003

90905-002

90905-002

'30015-003

90015-002

90015-001

90015-007

90014-003

90014-002

90014-001

90824-001

90824-001

90620-025

90670-002

A75507

90620-019

90620-012

90660-002·

90660-001

90702-001

90670-003

A75508

90670-001

90670-008

A-3

AMPRO COMPUTERS INCORPORATED - PARTS LIST

ASSEMBLY: A60060 - Little Board Plus

DESIG. QTY. DESCR I PTI ON

REV: A

VENDOR PIN

U16 1

U17,18 2

U19-21,30-34 8

U22,23

U24

U25

U26,37

U27

U2B

U29

U35

U3B

U39,41

U40

2

1

1

1

1

2

1

1

2

1

1

U4, 15, 16

U13,14

U17, lB

3

.::;

.....

2

IC, NCR 5380 BUS CONTROLLER

RES NIW DIP 12 - 220/330

IC, 4164 200YIS 64K DYN RAM

IC, 74LS157

IC, 74F32

IC, 7406

IC, 74F74

IC, 74LS139

IC, 7438

IC, 74LS374

IC, 74LS74

IC, 74F02

IC, 74LS244

IC, 74LS273

IC SOCKET 40 POS DUAL WIPE

IC SOCKET 28 POS DUAL WIPE

IC SOCKET 14 POS DUAL WIPE

**

NO TI

JNE J23-5040

AMP 2-640379-3

JNE J23-5028

JNE J23-5014

DATE: 06/19/85

AMPRO PIN

90670-005

90014-004

90680-002

90620-010

90620-016

90620-003

90620-021

90620-009

90620-018

90620-015

90620-007

90620-026

90620-013

90620-014

90800-002

90800-002

90800-004

90800-003

A-4

4

D c

AI5

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'-~Il

..

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"tS

Ai~

AI3

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AI.

A'

AU'

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A8

A7

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GND

A

A3

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A8 z

A1

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NCRDfKK*(3)

NCRC5"(~)

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IORO .. C~)

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AI

INITIAL AELEA

S£E ET FOP. REV

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J'MPS: I-Z OPt:N Nle SHORT SHORT

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I. NUMeEAS IN PAAENTtESttS INDICATE

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NOTES;

UNLESS OTHERWISE SPECIFIED

I. COMPONENT LAYOUT SHOWN IS CPU lA.

2. MOUNTING DIMENSIONS ARE THE SAME FOR ALL M)OELS.

3. Jl,3,4,5, 6 LOC/I liON IS THE SAME.

3 rSLOT .144 WIDE 4PL

5.75

5.29 r

2

SIZE C / DRAWING NUMBER

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OESCfllPTlDN

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B

ITEM

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SPECIFICATION t

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DATE

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DECIMALS

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XXt.02 xxxt-I-APP'O

REL

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2·8-B4 TITLE:

A

DIMENSIONS IN PARENTHESIS 1-'-'::.::...'-----'----1

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FINISH: DO

C PU

MOUNTING

::;E~C:LEo~RA:INlrJ-SC-IZ-E;--IDR-A-W-t-7-0-U-O--B--2-:-A----t

2

I I

APPENDIX B

TYPICAL INTERFACE CABLES

This Appendix contains wiring information for connection of the two Little

Board/PLUS serial ports to typical terminals, modems, and serial printers. In the tables, signal directions are relative to Little Board/PLUS.

TERMINAL CABLE

Table B-1 lists the pin connections generally used to connect to a terminal.

NOTE: to reduce EMI radiation, the cable should be shielded, with shield connected to the connector shell. Suggested part numbers for the board connector are given in Table 2-2. The terminal connector can be either male or female, depending upon the specific terminal.

Board

Connector

(J3)

Table B-1. Typical Terminal Cable Wiring

Signal Name Function Terminal

Connector

(DB-25)

1

5

3

4

2

6

Ground

RxD

TxD

HSO

Ground

HSI

Protective Ground

Data Input

Data Output

Handshake Signal Out

Signal Ground

Handshake Signal In

5

7

20

1

2

3

SERIAL PRINTER CABLE

Table B-2 lists the pin connections generally used to connect Serial Port B to a serial printer. NOTE: to reduce EM! radiation, the cable must be shielded, and the shield must be connected to the connector shell. Suggested part numbers for the board connector are given in Table 2-2. The printer connector can be either male or female, depending upon the specific printer.

Table B-2. Typical Serial Printer Cable Wiring

Board

Connector

(J3)

Signal Name Function Printer

Connector

(DB-25)

1

5

3

4

2

6

Ground

RxD

TxD

HSO

Ground

HSI

Protective Ground

Data Input

Data Output

Hand Shake Out

Signal Ground

Hand Shake In

1

2

3

5

7

(11)*

B-1

*

NOTE:

"Handshake Signal In" must connect to the printer's "Busy" output, i.e., the signal which tells the computer to start/stop sending data to the printer. The specific printer connector pin required for "Handshake Signal In" may vary between printers, so be sure to consult your printer's instruction manual.

MODEM CABLE

Table B-3 lists the pin connections generally used to connect to a modem.

NOTE: to reduce EMI radiation, the cable must be shielded, and the shield connected to the connector shell. The connector for the computer end must be a male OB-25, while the modem connector can be either male or female (usually male), depending upon the specific modem.

Table B-3. Typical Modem Cable Wiring

Signal Name Function Board

Connector

(J3)

Modem

Connector

(OB-25)

1

5

3

4

2

6

Ground

RxO

TxO

HSO

Ground

HSI

Protective Ground

Data Input

Data Output

Hand Shake Out

Signal Ground

Hand Shake In

1

3

2

20

7

5

B-2

APPENDIX C

CP/II USER GROUPS

AMPROl: AMPRO USER'S BULLETIN BOARD

(408) 258-8128

24 hrs/day, 7 days/week, 300/1200 baud

AMPR02: AIIPRO USER'S BULLETIN BOARD

(415) 962-9023

24 hrs/day, 7 days/week, 300/1200 baud

Both boards provide a focal point for dissemination of public domain software, and a place to exchange AMPROrelated hardware and software applications. The AMPROl bulletin board is not owned by AMPRO Computers, but is provided and maintained by AM PRO users for the benefit of

AMPRO users. The AMPR02 bulletin board is owned and operated by AMPRO Computers. Additional boards may become operational at any time. We suggest that you call into either of the above boards to check on the status of new boards in your area.

ZCPR3 BULLETIN BOARD: liZ-NODE CENTRAL"

(415) 489-9005

24 hrs/day, 7 days/week, 300/1200 baud

Filled with the latest ZCPR3 news, as well as the up-todate versions of ZCPR3 utilities.

CPIIUG The CP/M User Group

1651 Third Avenue

New York, NY 10028

SIG/II Special Interest Group for Microcomputers

P.O. Box 97

Iselin, NJ 08830

PICONET (a CP/M user group)

P.O. Box 391566

Mountain View, CA 94039-1566

New York Amateur Computer Club

P.O. Box 106

Church Street Station

New York, NY 10008

C-l

APPENDIX D

COMPONENT DATA SHEETS

D-l

Zilog

18400

zarc:pu

c:a.lral

Proc ......

Vall

Product

.p.dBcalloD

Features • The instruction set contains 158 instructions.

The 78 instructions of the 8080A are included as a subset; 8080A software compatibility

IS maintained.

• Eight MHz, ,6 MHz, 4 MHz and 2.5 MHz clocks for the zaOH. zaOB. zaOA, and Z8Q

CPU result in rapid instruction execution with consequent high data throughput.

• The extensive instruction set includes string. bit, byte, and word operations. Block searches and'block transfers together with indexed and relative addressing result in the most powerful data handling capabilities in the microcomputer industry.

• The 280 microprocessors and associated family of peripheral controllers are linked by a vectored interrupt system. This system

September 1983 may be daisy-chained to allow implementationof a priority interrupt scheme. Little, if any, additional logic is required for daisychaining.

• Duplicate sets of both general-purpose and flag registers are provided. easing the design and operation of system software through single-context SWitching. background-foreground programming. and single-level interrupt processing. In addition, two I6-bit index registers facilitate program processing of tables and arrays.

• There are three modes of high-speed interrupt processing: 8080 similar, non-Z8Q peripheral device. and zao Family peripheral with or without daisy chain.

• On-chip dynamic memory refresh counter. iii

.ft_1 iORO

IiAiQ

CONTROL liD

\Vii

RFSH

CONTROL

-I Hm

WAIT iNT

Hili zeoCPU

REsET iUSREQ iiiSACK lUI

CONTROL

CLK

•• v

A,

AI

AI

AI

A,

"-

ADDRDI aul aul

IN"

A"

A,.

A,.

A,.

All

CLK

D. lit

Do

0.

.IV lit

0,

Do

D, iiiT

NMI

HiLT iimi i'5Jiij

AI

AI

AI

AI

AI

A,

A"

AI

AI

A,

AI

GND mH

III iIBif iiiiiiiii

WAif

IiJiiCii

Wii iifI

Figure 2. Pln Anlgnmenla Figure 1. Pin Funcliou

2001-0210, 0211 5

"Reproduced by permiSSion 01983 Zilog, lne,

This material shall not be reproduced without tha written consent of Zilog. Inc,"

General

Description

The 280, 280A, 280B, and 280H CPUs are third-generation single-chip microprocessors with exceptional computational power. They offer higher system throughput and more efficient memory utilization than comparable second-and third-generation microprocessors.

The internal registers contain 208 bits of read/write memory that are accessible to the programmer. These registers include two sets of six general-purpose registers which may be used indiVidually as either 8-bit registers or as

IS-bit register pairs. In addition, there are two sets of accumulator and flag registers. A group of "Exchange" instructions makes either set of main or alternate registers accessible to the programmer. The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response.

The 280 also contains a Stack POinter, Program Counter, two index registers, a

Refr~sh register (counter), and an Interrupt register.

The CPU is easy to incorporate into a system since it requires only d single + 5 V power source. All output signals are fully decoded and timed to control standard memory or peripheral circuits, and it is supported ,by an extensive family of peripheral controllers. The internal block diagram (Figure 3) shows the primary functions of the 280 processors.

Subsequent text provides more detail on the

280 I/O controller family, registers, instruction set, interrupts and daisy chaining, and CPU timing.

+5V ___

GNU ....

CLOCK ...... '

• SYSTEMS 5 CPU

AND CPU CONTROL

CONTROL INPUTS

OUTPUTS

Figure 3.

zao

CPU Block Diagram

6

"Reproduced by permission C>1983 Zilog. Inc.

This material shall not be reproduced without the written consent of Zilog. Inc."

2001-0212

Z80 Microprocessor

Family

zao

CPU

Registers

The Zilog

zao

microprocessor is the central element of a·comprehensive microprocessor product family. This family works together in most applications with minimum requirements for additional logic, facilitating the design of efficient and cost-effective microcomputerbased systems.

Zilog has designed five components to provide extensive support for the

zao

microprocessor. These are:

• The PIO (Parallel InpuVOutput) operates in both data-byte I/O transfer mode (with handshaking) and in bit mode (without handshaking). The PIO may be configured to interface with standard parallel peripheral devices such as printers, tape punches, and keyboards.

• The CTC (CounterlTimer Circuit) features four programmable B-bit counter/timers,

Figure 4 shows three groups of registers within the ZBO CPU. The first group consists of duplicate sets of B-bit registers: a principal set and an alternate set (deSignated by , [prime). e.g., A '). Both sets consist of the Accumulator Register, the Flag Register, and six general-purpose registers. Transfer of data between these duplicate sets of registers is accomplished by use of "Exchange" instructions. The result is faster response to interrupts and easy, efficient implementation of such versatile programming techniques as backgroundeach of which has an B-bit prescaler. Each of the four channels may be configured to operate in either counter or timer mode.

• The DMA (Direct Memory Access) controller provides dual port data transfer operations and the ability to terminate data transfer as a result of a pattern match.

• The SIO (Serial InpuVOutput) controller offers two channels. It is capable of operating in a variety of programmable modes for both synchronous and asynchronous communication, including

Bi-Sync and SDLC.

• The DART (Dual Asynchronous Receiver/

Transmitter) device provides low cost asynchronous serial communication. It has two channels and a full modem control interface. foreground data processing. The second set of registers consists of six registers with assigned functions. These are 'the I (Interrupt Register), the R (Refresh Register), the IX and IY (Index

Registers), the SP (Stack Pointer), and the PC

(Program Counter). The third group consists of two interrupt status flip-flops, plus an additional pair of flip-flops which assists in identifying the interrupt mode at any particular time. Table 1 provides further information on these registers.

I

9

MAIN REGISTER NT

A ACCUMULATOR F FLAG REGISTER

•

GENERAL PURPOSE C GENERAL PURPOSE

D GENERAL PURPOSE E GENERAL PURPOSE

A' ACCUMULATOR

8' GENERAL PURPOSE

D' GENERAL PURPOSE

H GENERAL PURPOSE

~B8ITS

L GENERAL PURPOSE .

.......... - - - - - ' - - I . I I T $ - - - - - - - _

H' GENERAL PURPOSE

IX INDEX REGISTER

IV INDEX REGISTER

SP STACK POINTER

PC PROGRAM COUNTER

I INTERRUPT VECTOR

_ - - S B I T S - - *

I

R MEMORY REFRESH

Figure 4. CPU Registers

F' FLAG REGISTER

C' GENERAL PURPOSE

E' GENERAL PURPOSE

L' • GENERAL PURPOSE

INTERRUPT FUP·FLOPS STATUS o ".

INTERRUPTS DISABLED

1 '" INTERRUPTS ENABLED

INTERRUPT MODE FlIp·FLOPS

IMF. IMFl! o o t t

INTERRUPT MODE 0

NOTU$ED

INTERRUPT MODE 1

INT£RRUPT MODI 2

2001·0213 7

"Reproduced by permission "1983 Zilog, Inc.

This material shall nol be reproduced without the written consent of Zilog. Inc."

Z80 CPU

Reglstel'1l

(Continued)

Interrupts:

General

Operation

A,A'

F, F'

B, B'

C,C'

D, D'

E, E'

H, H'

L, L'

R

IX

IY

SP

Reglater

Accumulator

Flags

General Purpose

General Purpose

General Purpose

General Purpose

General Purpose

General Purpose

Interrupt Register

Relresh Register

Index Register

Index Register

Stack Pointer

PC Program Counter

IFFrIFF2 Interrupt Enable

IMFa-IMFb Interrupt Mode

SI.e (Bits) . Remarks

8

8

8

8

8

8

8

8

8

8

16

16

16

16

Flip-Flops

Flip-Flops

Stores an operand or the results 01 an operation_

See Instruction Set.

Can be used separately or as a 16-bit register with C_

See B, above_

Can be used separately or as a 16-bit register with E.

See D, above.

Can be used separately or as a 16-bit register with L.

See H, above.

Note: The (B,C), (D,E), and (H,L) SlIts are combined as follows:

B High byte C Low byte

D High byte E Low byte

H High byte L Low byte

Stores upper eight bils 01 memory address lor vectored interrupt processing.

Provides user-transparent dynamic memory relresh. Lower seven bits are automatically incremented and all eight are placed on the address bus during each instruction letch cycle relresh time.

Used lor indexed addreSSing.

Same as IX, above.

Holds address 01 the top 01 the stack. See Push or Pop in instruction set.

Holds address 01 next instruction.

Set or reset to indicate interrupt status

(~ee

Figure 4).

Rellect Interrupt mode (see Figure 4).

Table I. Z80 CPU Regi8ters

The CPU accepts two interrupt input signals: • Mode 1 Peripheral Interrupt service, for

NMI and INT. The NMI is a non-maskable use with non-8080/ZS0 systems. interrupt and has the highest priority. INT is a lower priority interrupt and it requires that

• Mode 2 "- a vectored interrupt scheme, usually daisy-chained, for use with Z80 interrupts be enabled in software in order to operate. INT can be connected to multiple

Family and compatible peripheral devices. peripheral devices in a wired-OR configuration.

The Z80 has a single response mode for interrupt service for the non-maskable inter-

NMI and INT signals at the rising edge 6f the last clock of an instruction. Further interrupt service proceSSing depends upon the type of interrupt that was detected. Details on interrupt. The maskable interrupt, INT, has three programmable response modes available.

These are: rupt responses are shown in the CPU Timing

Section.

• Mode 0 similar to the 8080 microprocessor.

8

"Reproduced by parmiaslon 01983 Zllog, Inc.

This material shall not ba reproduced without the written consent of Zllog, Inc."

Interrupts:

General

Operation

(Continued)

Non-Maskable Interrupt (NMI)_ The nonmaskable interrupt cannot be disabled by program control and therefore will be accepted at all times by the CPU. NMI is usually reserved for servicing only the highest priority type interrupts, such as that for orderly shutdown after power failure has been detected.

After recognifion of the NMI signal (providing

BUSREQ is not active), the CPU jumps to restart location 0066H. Normally, software starting at this address contains the interrupt service routing.

Maskable Interrupt (INT). Regardless of the mterrupt mode set by the user, the 280 response to a maskable interrupt input follows a common timing cycle. After the interrupt has been detected by the CPU (provided that interrupts are enabled and BUSREQ is not active) a special interrupt processing cycle begins. This is a special felch (MI) cycle in which IORQ becomes active rather than

MREQ, as in normal

"Ml cycle. In addition, this special MI cycle is automatically extended by two

WATf states, to allow for the time required to acknowledge the interrupt request.

Mode 0 Interrupt Operation. This mode is similar to the 8080 microprocessor interrupt service procedures. The interrupting device places an instruction on the data bus. This is normally a Restart instruction, which will initiate a call to the selected one of eight restart locations in page zero of memory. Unlike the

8080, the 280 CPU responds to the Call instruction with only one interrupt acknowledge cycle followed by two memory read cycles.

Mode I Interrupt Operation. Mode I operation is very similar to that for the NMI. The principal difference is that the Mode 1 interrupt has a restart location of 0038H only.

Mode 2 Interrupt Operation. This interrupt mode has been designed to utilize most effectively the capabilities of the 280 microprocessor and its associated peripheral family. The interrupting peripheral device selects the startmg address of the interrupt service routine. It does this by p~cing.an 8-bit vector on the data bus during the interrupt acknowledge cycle. The CPU forms a pointer using this byte as the lower 8-bits and the contents of the I register as the upper 8-bits. This points to an entry in a table of addresses for interrupt

• ~rvice routines. The CPU then jumps to the routine at that address. This flexibility in selecting the interrupt service routine address allows the peripheral device to use several different types of service routines. These routines may be located at any available location in memory. Since the interrupting device supplies the low-order byte of the 2-byte vector, bit 0 (Ao) must be a zero.

Interrupt Priority (Daisy Chaining and

Nested Interrupts). The interrupt priority of each peripheral device is determined by its phYSical location within a daisy-chain configuration. Each device in the chain has an interrupt enable input line (lEI) and an interrupt enable output line (lEO), which is fed to the next lower priority deVice. The first device in the daisy chain has its lEI input hardwired to a

High level. The first device has highest priority, while each succeeding device has a corresponding lower priority. This arrangement Permits the CPU to select the highest priority interrupt from several simultaneously interrupting peripherals.

The interrupting device disables its lEO line to the next lower priority peripheral until it has been serviced. After servicing, its lEO line is raised, allowing lower priority peripherals to demand interrupt servicing.

The 280 CPU will nest (queue) any pending interrupts or interrupts received while a selected peripheral is being serviced.

Interrupt Enable/Disable Operation •. Two flip-flops, IFF) and IFF2, referred to in the register description are used to signal the CPU interrupt status. Operation of the two flip-flops is described in Table 2. For more details, refer to the Z80 CPU Technical Manuol and Z80

Assembly Language Manual.

AcU_ IFF, lFFa CommeDta

CPU Reset 0 0

D1lnstructlon execution

EI Instruction execution

LD A,I instruction execution

LD A,R Instruction execution

AcceptNMi

0

•

0

0

IFFI

Maskable Interrupt mT disabled

Maskable Interrupt

INT disabled

Masleable interrupt

INT enabled

IFF2 - Parity flag

IFF2 - Parity flag

REm Instruction execution

IFF2

IFFI - IFF2

(Maskable interrupt 1m dIsabled)

IFF2 - )FFI at

~lelionofan

N I service routine.

Table I. State 01 FUp-Flo):'a

I

I

9

"Reproduced by perrnlHlon

.'983

Zilog. Inc.

This material shall not be reproduced without the written consent 01 Zllog. Inc."

Instruction

Set a-Bit

Load

Group

The 280 microprocessor has one of the most powerful and versatile instruction sets available in any a-bit microprocessor. It includes such unique operations as a block move for fast, efficient data transfers within memory or between memory and I/O. It also allows operations on any bit in any location in memory.

The folloWing is a summary of the Z80 instruction set and shows the assembly language mnemonic, the operation, the flag status, and gives comments on each instruction. The Z80 CPU Technical Manual

(03-0029-01) and Assembly Language

Programming Manual (03-0002-01) contain significantly more details for programming use.

The instructions are diVided into the follOWing categories: o a-bit loads

Ol6-bit loads o Exchanges.-block transfers, and searches o a-bit arithmetic and logic operations o General-purpose arithmetic and CPU control o 16-bit arithmetic operations o Rotates and· shifts o

Bit set, reset, and test operations o Jumps. o Calls,' returns, and restarts o

Input and output operations

A variety of addressing modes are

Implemented to permit efficient and fast data transfer between various registers, memory locations, and input/output devices. These addreSSing modes include: o Immediate o Immediate extended o Modified page zero o Relative o

Extended o

Indexed o

Register o Register indirect o

Implied o

Bit

LO r, r'

LD r, n r - r'

Symbolic

OJNll'a'ioa

LD r, (HL) r - (HL)

LD r, (lX+d) r - (lX+d)

LD r, (lY +d) r-(IY+d)

LO (HL), r (HL) - r

LD(lX+d). r (lX+d) - r

LD(lY+d). r (IY+d) - r

LD (HL), n (HL) - n

LO (lX+d), n (IX+d) - n

LD (IY +d). n (lY+d) - n

LD A, (BC)

LOA, (DE)

LO A, (nn)

LD(Be), A

LO(DE), A

LD (nn), A

LOA, I

LDA, R

LDI,A

LOR, A

A - (BC)

A - (DE)

A - (nn)

(Be) A

(DE) - A

(nn) - A

A - I

A - R

1- A

R-A

S Z

·

·

X x x

X

X

Flap

H

·

·

X x

X

X

PlY "

·

·

·

X

·

· X x

·

X x

·

· · x

· x

·

·

X

X

·

·

X

X

·

C

Opcode

71 543 210 H ••

01 r r

00 r 110

- n -

01 r 110

11 011 101 DO

01 r 101

- d -

11 III 101 FO

01 r 110

- d -

01 110 r

II 011 101 DO

01 110 r

- d -

II 111 101 FD

01 110 r

- d -

00 110 110 36

- n -

11 011 101 DO

00 110 110 36

- d -

· · x

· x

· . ·

· ·

· · x x x x

X x

·

· x x x x

X x

·

·

·

X 0 X IFF 0

X 0 X

· · x x

· x x

IFF 0

·

11 III 101 FD

00 110 110 36

- d -

- n -

00 001 010 OA

00 011 010 IA

00 III 010

- n -

- n -

3A

00 000 010 02

00 010 010 12

00 110010 32

- n -

- n -

II 101 101 ED

01 010 III 57

11 101 101 ED

01 011 III SF

II 101 101 ED

01 000 111 47

11 101 101 ED

01 001 111 4F

NOTES, r> r' means aflY vi the registers A, D, C, D. E, H. L

IfF the contenl oj the inlt:rrupt enable Ihp-llop. (IFF) is

COPied into Iht! PlV Hag.

For dn explanClllon of flag nolalion and symbols lor mnemonic tables, see Symbolic Notation $eChon iollowmq tables.

I

I

3

I

2

I

I

3

2

No.oI No.oI M No.of T

B,.. ..

Cycleo

S._

5

2

5

S

5

2

2

4

2

2

4

7

19

19

7

19

19

10

19

19

7

7

13

7

7

13

9

9

9

9

CoaaaaeDta

~

000 B

001

010·

C

0

011 E

100 H

101

III

L

A

2001-001 10

"Reproduced by permiaaion 01983 ZlIog, Inc,

This material shall not be reproduced without the written consent of Zilog. Inc,"

Il-BU Load

Group

POPqq

POP IX

POPIY

PUSH IX

--

IymboUc

0p0raII0D

•

I

.......

•

PlY • C 71 MIll .....

80."

""""

.

.........

,

CyaIM

....... c--to

LD del. nn del nn X X 00 delO 001

- n -

- n -

3 10 .!lsL-h!!:

Oll Be

01 DE

LD IX. nn IX-nn X X 4 14 10 HL II 011 101 DO

00 100 001 21 II SP

- n -

- n -

II III 101 FD LD IY. nn IY - nn X X 14

00 100 001 21

- n -

LD HL. (nn)

LD del. (nn)

LD IX. (nn)

LD IY. (nn)

LD (nn). HL

LD (nn). dd

LD (nn).1X

LD (nn). IY

LD SP. HL

LD SP.IX

LD SP. IY

PUSHqq

H_(nn .. 1)

L - (nn) delH - (nn + I) delL - (nn)

IXH - (nn .. l)

IXL - (nn)

IYH - (nn .. l)

IYL - (nn)

(nn .. l) - H

(nn) - L

(nn+ I) - ddH

(nn) - ddL

(nn+ I) - IXH

(nn) - IXL

(nn+ I) - IYH

(nn) - IYL

SP - HL

SP - IX

SP- IY

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

X

- n -

00 101010 2A

- n -

- n -

II 101 101 ED

01 dell 011

- n -

- n -

II 011 101 DO

00 101 010 2A

- n -

- n -

II III 101 FD

00 101 010 2A

- n -

- n -

00 100 010 22

- n -

- n -

II 101 101 ED

01 ddO 011

- n -

- n -

11 011 101 DO

00 100 OlD 22

- n -

- n -

11 111 101 FD

00 100 010 22

- n -

- n -

11 111 001 f9

II 011 101 DO

11 111 001 f9

11 111 101 FD

11 111 001 f9

11 qqO 101

II 011 101 DO

11 100 101 E5

3

4

4

3

4

I

2

2

2

8

18

20 a

20

6

5

6

6

6

I

2

2

3

4

20

16

20

20

20

6

10

10

11

15

~

01 DE

10

11

HL

U

PUSHIY

(SP-2) - qqL

(SP-I) - QQH

SP - SP-2

(SP-2) - IXL

(SP-I) - IXH

SP - SP-2

(SP-2) - IYL

(SP-I) - IYH

SP- SP-2

QQH - (SP+ I) qqL - (SP)

SP - SP +2

IXH - (SP .. II

IXL (SP)

SP - SP .. 2

IYH - (SP+ II

IYL - (SP)

SP- SP +2

X

X

X

X

X

X

X

X

11 111 101 FD

11 100 101 E5

11 qqO 001

II 011 101 DO

11 lOll 001 EI

2

2

4

3

4

15

10

14

14 II 111 101 FD

11 lOll 001 81

Exchange.

Block

TraDBfer.

Block Search

GrOUpll

NOTES, del il eny of the reqiat..- plirs BC, DE, HL. SP. qq is any oj Ihe register peir. AV, Be, DE. HL.

': order and low order eight bit.ot the reQllter pair respectively.

EX DE. HL DE -HL

EXU,AT AF U'

£XX Be-BC'

DE - DE'

HL - HL'

EX (SP). HL H-(SP+I)

EX

EX

(SP). IX

(SP), IY

L (sp)

IXH - (SP+ 1)

IXL - (SP)

IYH - (SP+I)

IYL - (SP)

X

X

X

X

X

X

X

X

X

X

X

X

LDI X 0 X

<D

(DE) - (HL)

DE - DE+l

HL-HL+I

Be - Be-I

LDIR (DE) - (HL)

DE - DE+I

HL-HL+I

Be - Be-I

Repeot until

Be = 0

NOTE,

CD

P/V Ilag is 0 illhe r~ult

01

Be 1 - 0, olherwll8 PIV .. l.

<D

X 0 X 0

.

11 101 011 ED

00 001 000 08

11 011 001 D9

0

0

11 lOll 011 E3

11 011 101 DO

11 lOll 011 E3

11 111 101 FD

11 lOll 011 E3

11 101 101 ED

10 100 000 AD

II 101 101 ED

10 110000 BO

2

2

2

2

2

6

6

4

4

4

4

19

23

23

16

21

16

II8QloIe< bank and auxiliary I'OQlIIer bank ucbanoe

Load (HL) Into

(DE), JncremanI the poIn_ and decrementthebJte countar (BC)

JIBe .. 0

JlBC .0

2001·001

"Reproduced by permission 01983 Zilog. Inc.

This material shall not be reproduced without the written consent 01 Zllog,lnc."

11

I

I

Exchange,

Block

Transfer,

Block Search

Groups

(Continued)

~

.,-..

Opeoadoo

LDD

LDDR

(DE) - (HL)

DE - DE-I

HL - HL-I

BC- BC-I

(DE) - (HL)

DE-DE-I

HL - HL-I

BC- BC-I

R_luntll

BC

Q

0 naio

Opcode •

Z R p" • C "MlI1D'"

. .

. x

X '0

CD

0 X I 0

X

@

0 0

CPI

CPIR

A - (HL)

HL-HL+I

BC - BC-I

A - (HL)

~ CD

I X I X

I

Ol CD

I X I X I

CPO

HL - HL+I

BC-BC-I

Repeelunlil

A. (HL)

01'

BC·O

A - (HL)

HL-HL-I

BC - BC-I

A - (HL)

() CD

I X I X 1

CPDR

()

I X I X

CD

HL ":HL-I

BC - BC-I

Repelt until

A = (HL)

0'

BC·O

NOTES:

(j)

PlY 1149

I'

0 at the ruul'

~

Be-I. O. otMrw'le P/V • 1. a>

P/V IlaQ IS 0 at completIon'" INlrt.aChon on.,. a>

Z IIl1q

II') If A • (HW. otherwlle Z • o.

·

·

II 101 101 ED

10101 000 AS

11 101 101 ED

10 III 000 Be

11 ·101 101 ED

10100 001 AI

11 101 101 ED

10 110001 BI

11 101 101 ED

10 101 001 A9

11 101 101 ED

10 III 001 B9

.,...

II IIo.ot T c,cJo.

....... c.-to

2

2

2

2

2

5

4

5

16

21

16

16

21

16

16

21

16

UBC" 0

UBC

&

0

IIBC"Oancl

A" (HL)

IIBC-Oor

A. (HL)

IIBC"Oond

A" (HL)

IIBC-Oor

A

=

(HL)

I·BIt

Arithmetic ancl Logical

Group

ADDA. ,

ADDA. n

A -A +,

A-A+n

ADDA.(HL) A-A+(HL)

ADD A. UX+d) A - A + (1X+d)

ADDA.UY+d) A -A + (IY+d)

ADCA ••

SUB.

SBCA ••

AND.

OR.

XOR.

CP.

INC,

INC(HL)

INC (1X+d)

INC (1Y+d)

DEem

A - A-.

A - A-.-CY

A-A . . .

A-AV.

A - A e.

A-. r - r + 1

(HL) -(HL) + 1

(1X+d) ..

(1X+d)+ I

(lY +d) -

(lY +d)+ I m -m-l

X I X V 0 101!!g ,

I

I X I X V 0

I X I X V 0

I X I X V 0 I

I X I X V 0

I X

X

X

X

X V 0

X v

X V I I

X P 0 0

1l1iiii)1I0 n

-

101il!im 110

11 011 101 DO

10

IiiiiD

110 d

-

11 111 101 FD

10 1ijg110

d

mmJ mIl mID

11m

(j]jJ

I X 0 X P 0 0

X 0 X P 0 0

X

X

X

X

X V I

X V 0

X V 0

X V 0

I X I X V 0

I X I X V I

£ml)

·

00 lIm r mm ·

00 110

Iiiii

11 011 101 DO

·

00 110m d

-

11 111 101

00 110m d

ImD

'0

2·

I

3

3 i

2

2

5

5

I

3

6

6

4

7

7

19

~

000 B

001 C

010 0

011 I

100 H

101 L

III A

19

4

11

23

23

I I I any of r, n.

(HL). (1X+d).

(IY+d) eollhawn for ADD inllruL1ion.

The Indlcobld blta rep100a the IiiiiIln the ADD ... Above. mil ony 0/ '. (HL).

(lX+d). (IY +d) eo "'-n /or INC.

DEC_formal ond_uINC.

RepIaee liM! with

ImD in opcode.

12 2OO1"()()1

"Reproduced by pennl.lon 01863 Z1log. Inc.

This materlai shall not be reproduced without

01 Z1log. Inc."

General-

Purpose

CPU Control

·Group.

~

Arithmetic DAA and

CPL

IymboIIc

0p0raIIa0a

Convert. ace. content

Into packed BCD fol1owlno add or

.ubtract with pecked

BCI2 oparanda.

A-A

Flap Opoode 110.01 110.01. 110.01 T •

Z B 'IV II C 111141110 . . . BrtCyclooo 1Itat .. eo.-...

X X P 00 100 III 71 4 Decimal odjul! accumulator.

NEG

CCF

SCF

NOP

HALT

DI *

E1*

1i00i0

1i00i1

1M2

A-O-A

CY-C'i

CY - I

No operation

CPU halted

IFF - 0

IFF I

Set Inlerrupt mode 0

Set mterrupt mode I

Sel

Interrupt mooe 2

X

X

X

X

X

X V

X X X

X 0 X

X

X

X

X

X

X

X

X

X

X

X

X

0

0

00 101 III 2F

II 101 101 ED

01 000 100 44

00 III III 3F

00 110 III 37

00 000 000 00

01 110 110 76

II 110 011 F3

II III 011 FB

II 101 101 ED

01 000 110 46

II 101 101 ED

01 010 110 56

II 101 101 ED

01 011 110 5E

2 2

2

8

8 ij

Complement accumulator (Olltt'. complement) .

Neqate ace. (two', complement).

CompieJMnt carry

1109.

Set carry lIa\l.

NOTES' In' Indlcat .. ,he Interrupt _noble iIIp-f1tlP.

CY Indlcal .. the carry flip· flop .

• lndlcalea mterrupt. are not sampled 411 the end of El or DI.

IS-Bit

Arithmetic

Group

ADDHL, ..

ADCHL, ..

HL - HL+ ..

HL ~L+lS+CY

SBC HL, ..

ADD IX, pp

HL - HL-u-CY

IX-IX+pp

ADDIY,rr IY-IY+rr

X X X

X X X V 0

X X X V

X X X 0

X X X 0

00 .. I 001

II lOt 101 ED

01 .01 010

11 101 101 ED

01 .sO 010

11011 101 DD

01 ppl 001

11 111 101 FD

00 rrl 001

II

15

15

15

15

~

00 BC

01 DE

10 HL

11 SP

~.

01 DE

10 IX

II SP

~

01 DE

10 IY

II SP

INC ..

INC IX lNCIY

DEC ..

DEC IX

DECIY

1 1 - ••

+1.

IX - IX • I

IY - lY + I

.. - 51-I

IX - IX-I

IY - IY-I

X

X

X

X

X

X

X

X

X

X

X

X

00 ..0 011

II 011 101 DD

00 100 011 23

II III 101 FD

00 100 011 23

00 .. I 011

II 011 101 DD

00 101 011 2B

II III 101 FD

00 101 011 2B

2

I

2

2

6

10

10

6

10

10

NOTES, IS II any 01 the reqlsler pair.!'C, DE, Hl.. sr,

PP" an~ oilntregilter poll,. BC, PE. IX. SP. rf II any of the regl.ter pair. BC. DE. 1Y, SP.

Rotate and

Shift Group RLCA

RlA

RRCA

RRA

RLC r

RLC (Hl)

Ree (IX+d)

@!]~ r,(Hl),(IX + d),(IY + d)

RlC(lY+d)

RL m

AAem

@!]~

A

X 0 X 0 00 000 III 07

Cfill--1

7 0

A p'

X 0 X 0 00 010 III 17

L~@!]

A

X 0 X 0 00 001 III OF t::EtF@J

A

X X 0 00 011 III IF

X 0 X P 0

L.[~_~ m.r,(HLUIX+dj,(IY +d)

~@J m.r,(HL),(IX +dUIY +d)

X 0 X P 0

X 0 X P 0

X X P 0

X 0 X P 0

X 0 X P 0

II 001 011 CB

OO~r

II 001 011 CB

00~1I0

II Oll 101 DD

II 001 011 CB d

-

OO~IIO

11 III 101 FD

II 001 011 CB

d

-

00 00lI110 m:m

ImD

6

Rotate left ctrculer accumulator.

Rotate lelt accumulator .

Rotate riQht circulor accumulator.

Rotate rl9ht accumulator.

8

15

23·

Rolate lett circular reqister r.

L-..Jl5.

000 B

001 C

010 D

011 E

100 ·H

101

III

L

A

23

Instruction format and stales arc 45 shown for RLe's.

To form new apcocie replace ilQQ) or RLC's

WIth shown code.

2001·001

"Reproduced by permission 01983 Zilog, Inc.

This material shall not be reproduced without the written consent of Zilog, Inc."

13

I

9

Rotate and

Shift Group

(Continued)

~

IrmJooUc

0pe0atI0a

RR m

SLAm

SRAm

SRLm

RLO

RRO

I I

~@}J m _ r.(HL).(IX + d).(IY + d) ffi]~o m_r.(HL).UX +d).(lY+d) c:Q.=D--@!J m.r.(HL).(IX + d).(IY +d)

.~@!J m.r.(HL).(lX+d).(lY +d)

Il-.I'~.

A tHll li:lli:!J

[lS~

I

• tHL)

H

......

PlY II C

X 0 X P 0

X 0 X P 0

X 0 X P 0

Opcode

" MIlia

..... H .... II H .... T

Roo IyIoo 0JaI00 ....... mIl

!WI

IIIDl c..-..

X 0 X P 0

X 0 X P 0

X 0 X P 0

IIiII

·

11 101 101 ED

01 101 III 6F

2 5 18 Role .. dlqlt leIt and rlqht b8twoan

·

11 101 101

01 100 III

ED

61

2 5' 18 the accumulator and IocaUOn (HL).

The content 01 tho up_hoUol the accumulator .. unaffected,

Bit Set. R ...

BIT b. r and Test

Group

BIT b. (HL)

Z - 'II

Z - (iiL)b

BIT b. (IX + d)b Z - (1X+d)b

BIT b. (lY +d)b Z - (lY +d)b

SET b. r

SET b. (HL)

SET b. (lX+d) (1X'+d)b - 1

SETb. UY+d) (lY+d)b- 1

RES b. m

'b I

(HL)b- 1

!lib 0 m. r. (HL).

(IX + d).

(lY+d)

X

X

X

X

X

X

X

X

X X 0

X X 0

X X 0

X X 0

·

11 001 011 CB

01 b r

11 001 011 CB.

2

2

2

3

8

12

~

001 C

· 01 b 110

11 011 101 DO

11 001 011 CB

d

01 b 110

5 20

010

011

100 H

101

0

E

L

III A b 81IT_

5 20 000 0 11 III 101 FO

11 001 011 CB d

01 b 110

001 I

010 2

011 3

100 4

101 5

110 6

·

X

X

·

·

X

·

X

·

X

X

·

11 001 011 CB

Il]b

2 2

·

11 001 011 CB 2 4 15

Il]b 110 · .

11 011 101 DO

11 001 011 CB

d

I!lb 110 '

4 6 23

8

X

·

X

·

11 111 101 FO

11 001 011 CB

6 23 d

III 7

· x

· x

·

1m

[lJ b 110

Tolorm new opoodo repIaco

[!J

01 SET b •• with

I!!J.

FiaQI and lime a t

SET -.ucllon.

NOTES: The nqallon mb indlCaln bit b (0 10 7) or tac.uon ...

Jump

Group

!Pnn

JPw, na

JR.

IRC ••

JRIIC ••

!PZ ••

IRIIZ ••

IP(HI.)

'IP(IX)

PC-lID

D condttlOD cc II

_PC-nn. oIhorwlIe continuo

PC - PC+.

DC - O. continue

DC -I.

PC - PC+.

DC -I. continuo

DC - O.

PC - PC+.

DZ - 0 oonllnue

DZ - I.

PC - PC+. liZ - 1. continue lIZ c O.

PC - PC+.

PC- HL

PC -IX

0

0

0

0

·

·

X

X

·

·

X

X

·

·

11 000 011 C3 -

n

..

11 cc 010

-

II n

3

3

3

3

10

10 oc

000

001 Z

I0I'O

010

CondHlon

HZ non-zero'

He non-oorry

011 C ....,.

·

X

X

·

X

X

·

00 011 000 18 3 12

100 PO portly odd

101 PE portly_

110

III

P

IiqD poaItI . .

· - 0-2-

00 111 000 38

- 0-2-

2 7

D condition not _ .

D condition II _ .

2 3 12

·

X

·

X 0 0 00 110 000 30 2 2 7

D condition not _ .

. - 2 -

2 3 12

D condition II _ .

D condition not _ .

X 0 X 0

00 101 000 28

. - 2 -

2 2 7

D condIUOn I. _ .

3 12

II condtUOn not _ .

X

0 X 0 00 100 000 20

. - 2 -

2 2 7

3

II cond"1on II _ .

2 12

4 X 0

X 0

X 0

X 0

11 101 001 E8

11 011 101 DO

11 101 001 19

2 2 8

14 2001-001

"Reproctucacl by parmlMion .1883 Z11og. Inc.

This matorlal "'all not be reproduced without the written COIIIOI'It of Z11og. Inc."

Jump Group

(Continued)

~ a,-.u.

IP(lY) PC -IY

I I

X

X

Plago Opaode 110.01 110.01 II Ko.oI T •

PlV II C "141110 ..... IyIM CyeIoe a eo.-..

X 11 111 101 FD 8

11 101 001 E9

00 010 000 10 X

2 •

8 If 8 - O.

- .-2 -

DINZ •• 8 - 8-1

II 8 . O. conUnue

If 8'1' O.

PC - PC+.

NOTES, • repr ...

• I ••• the: reno-

• - 2 In the opcode provide. an .flectlve .dd ..... of pc by 2 prIOr 10 the addition 01 ••

< -116. 129

+. Ii.

>.

PC I, IncrelMnte4

2 3 13 If 8 .. O.

Call and

Return Group

CALL nn (SP-I) - PCH

(SP-2) - PCL

PC nn

CALL ce. nn If conditlon cc is talee continue,

CALL nn

RET

RETcc

PCl - (SP)

PCH - (SP+ I)

11 condition cc is falae continue, otherwil8 sama as.

RET

RETI

RETNI

RSTp

Return from interrupt

Return from non· maskahle interrupt

(SP-I) - PCH

(SP-2) - PCL

PCH - 0

PCL-P

X

X

X

X

X

X

X

X

X

X

X

X

X

X

11 001 101 CD n

n

-

11 celOO n n

-

3

11 001 001 C9

11 cc 000

11 101 101 ED

01 001 101 40

11 101 101 ED

01 000 101 45

11 I III

3

4

17

)0

17

If co 1l1aIoe.

If co II \rue.

10

NOTE, 'flETN loodo Iff'. - IFF I

Input and

Output Group

IN A. (n)

IN r. (C)

INI

INlR

A - (n) r - (C)

If r =

11090

110 only will be the ollectacl

(Hl) - (C)

8 - 8-1

HL-HL+I

(HL) - (C)

8 - B-1

HL-HL+I

Reptt4t until

8 . 0

X

X

X

X P 0

(j)

X X X X X

X

~

X X X X

IND

INDR

(Hl) - (C)

8 - B-1

HL - HL-I

(HL) - (C)

B - 8-1

HL - HL-I

Repeal unlll

B = 0

(n) - A

(j)

X

X

X X X X

~

X X X X

OUT (n). A

OUT(C), r

OUTI

OTIR

(C) - r

(C) -(HL)

B - 8-1

HL-HL.I

(C) - (HL)

8 - 8-1

HL-HL+I

Repeat until

B.O

X X

X X

X

(j)

X ,X X X

X

~

X X X X

OUTD (C) - (HL)

B - B-1'

Hl - HL-I

X

(j)

X X X X

Non, <D

Ii the result 01 B-1 is zero the Z UaQ II set. otherwiH It i. reaet.

@Z lIag IS set opon Instruction complttticn only. --,.

2001·00,

X

X

X

X

X

X

11 011 011 DB

n

-

11 101 101 ED

01 r 000

X 11 101 101 ED

10 100 010 A2

II 101 101 ED

10 110010 52

II 101 101 ED

10 101 010 AA

11 101 101 ED

10 III 010 BA

11 010 011 03

n

-

II 101 101 ED

01 r 001

II 101 101 ED

10 100 011 A3

11 101 101 ED

10 110 011 B3

11 101 101 ED

10 101 Oil AB

2

3

4

5

(II B'I'O)

4

(lIB-O)

21 f6

4

II

12

16

16

2

2

5

(lIB'I'O)

4

(IIB-O)

21

16

II

12

16

2

5

(IIB'I'O)

4

(IIB-O)

21

16

16

11

14

14

·11

If ce I. 1aIoe.

II cc II \rue. cc

CiOO

Condltlon

NZ non·..."

001 Z zero

010 NC non·cany

011 C cany

100 PO portty odd

101 PE portty even

110 P oIcjn~tI.,.

111M oIcjn neqeUve

~

001 08H

010 10H

011 ISH

100 20H

101 28H

110 30H

III 38H nlo Ao - A7

Ace. to As - AIS

CtoAo- A7

B to As - AI5

CtoAo - A7

BtoAs - AIS

C toAo - A7

B to As - AI5

CtoAo - A7

BtoAs - AI5

CtoAo - A7

B 10 As - A15 ntoAo - A7

Ace. to As - AI5

CtoAo - A7

B to As - A15

CtoAo - A7

BloAs - AIS

CtoAo - A7

BtoAs - AI5

CtoAo - A7

8 to As - AI5

"ReproduGed by permission 01983 Zilog. InG.

This material shall not be reproduced without the written Goneent of Zilog. InG."

15

I

I

IDput and

Output Group

(Continued)

.............. SraaboIlc

I Z

FkllII

H PlY If C aTDR

NOTE

CDz

II"Q

(e) (HL)

8 - 8-1

<D

X 1 X X X X

HL - HL-l

RepE"at unhl B

II

0

II lei uJlOn IMlru, hon C'OfIlplcllon o,)n~y.

X

Summary of

Flag

OperatioD

.......... IOD

ADD A. s;

ADC A. , sua s; sac A .• ; CP s;

NEG

AND,

OR •• XOR.

INC,

DEC,

ADDDO ...

ADC HL ... sac HL ...

RLA.RLCA.RRA;RRCA

RL m; RLC m; RR m;

RRC m; SLA m;

SRA m: SRL on

RLO; RRO

DAA

CPL

SCF

CCF

INr(C)

INI. IND. OUl'l; OUTO

INIR; INOR; OTIR; OTOR

LOI; LOD

LOIR; LOOR

CPI; CPIR; CPO; CPOR

LOA. I. LDA. R

BIT b.,

()pcoM 1I0.oI lfo.oI

711141110 . . . lIyteo CyMo

....... eo.-

0,

8 Z H

Do

PlY N C

X I X V 0

X I X V 1 I

X I X P 0

g}

X 0

X I

X I

X P 0

X V 0

X V I

X X X 0

X X X V 0

X X X V I

X 0 X 0

X 0 X P 0 c:o...-to

8·bit add or odd with carry.

8 bit subtract, subtract with carry. con:spare and neQate accumulator.

L\)Qica.J operatIon ••

S·bil Increment.

8-bil decrement.

16·blt odd.

16·blt add w~th carry.

16·blt subtract with carry,

Rotate accumulator.

Rot4te and .hdt iocah(\n8.

X 0 X P

X I X P

X I X I

I I

X

X

X

0 X

X X

0 X p

0

0

0

X I X X X X I

X I X X X X I

X X X 0 X I 0

X X X 0 X 0 0

X I X X X I

I

X

X 0

X I

X In 0

X X 0

11 101 101

10 III 011

ED 2 5

(II B .. O)

(II

4 a-o)

21

16

CtoAo - A7

BtoAa - AI5

Rotate di9i1 left and rl9ht.

Decimal edjult accumulator.

ComplE"ment accumulal0r.

Set carry.

Complement carry.

Input reqlstgr indirect.

:}

Block input and output. Z = 0 if B _ 0 otherwtae Z == o.

:}

Block transfer instructions. P/V = 1 if BC • 0, otherwise P/V • O.

Block aeerch instruchons. Z "" 1 If A

" ac ..

O. O.herwlse P/V = o.

= (HL), otherwise Z = O. PIV s 1

The content 01 the mterrupt enable flip·flop (IFF) ,. COPied Into the PIV floq.

The state 01 bit b of location

8 is copied into the Z nag.

Symbolic

Notation

Symbol

S

Z

P/V

H

N

H&N

C

Sign flag. S

Zero flag. Z

Operation

=

I if the MSB of the result is I.

=

I if the result of the operation is O.

Parity or overflow flag. Panty (P) and overflow

(V) share the Same flag. Logical operations affect this flag with the parity 01 the result while arithmetic operations affect this flag with the overflow of the result. Ii P/V holds parity, P/V

I if the result of the opel'ation is even. P/V = 0 if result is odd. II PIV holds overflow, PIV

=

I if the result of the operation produced an overflow.

Half·carry flag. H .. I if the add or subtract operation produced a carry into or borrow from bit 4 of the accumulator.

Add/Subtract flag. N

=

1 if the previous operation was a subtract.

Hand N flags are used in conjunction with the decimal adlust instruction (DAA) to pl'operly correct the result into packed BCD format following addition or subtraction using operands with packed BCD lormat. .

CarrylLink flag. C

=

I if the operation produced a cllrry from the MSB 01 the operand or result.

•

0

I

X

V

Symbol

I

P ss ii

R n nn

Operation

The flag 18 affected according to the result of the operation.

The flag is unchanged by the operation .

The flag is reset by the operation.

The flag is set by the operation.

The flag is a "don't care."

PIV flag affected according to the overflow result of the operatio.n.

PlY flag affected according to the parity result of the operation.

Anyone 01 the CPU registers A, B, C, D. E, H, L.

Any 8·bit location for all the addressing modes allowed for the particular instruction.

Any IS·bit location for all the addressing modes allowed for thatlnslruction.

Anyone of the two index registers IX or IY.

Refresh counter.

8·bit value In range

IS·bit value In rallge

< 0, 255 >.

< 0,65535 >.

16

"Reproduced by permissiOn .1983 Zilog. Inc.

This material shall not be reproduced wIthout the written coneent of Zilog. Inc."

2OO1'()()1

Pin

Descriptions

Ao-Aui' Address Bus (output, active High,

3-state). Ao-AI5 form a 16-bit address bus. The

Address Bus provides the address for memory data bus exchanges (up to 64K bytes) and for

I/O device exchanges.

-SUS-ACK.

Bus Acknowledge (output, active

Low). Bus Acknowledge indicates to the requesting device that the CPU address bus, data bus. and

~ontrol signals MREQ, 10RQ, ffb, and WR have entered their highimpedance states. The external circuitry can now control these lines.

BUSREQ. Bus Request (input, active Low).

Bus Request has a higher priority than NMl and is always recognized at the end of the current machine cycle. BUSREQ forces the CPU address bus, data bus, and control l:iignals

MREQ, lORd, RD, and WR to go to a highimpedance state so that other devices can control these lines. BUSREQ is normally wire-

ORed and requires an external pullup for these applicatIons. Extended BUSREQ periods due to extensive DMA operations can prevent the CPU from properly refreshing dynamic RAMs.

Do-D7. Dala Bus (input/output, active High,

3-state). Do-D7 constitute an 8-bit bidirectional data bus, used for data exchanges with memory and I/O.

HALr.

Hall State (output, active Low). HALT indicates that the CPU has executed a Halt instruction and is awaiting either a nonmaskable or a maskable interrupt (with the mask enabled) before operation can resume.

While halted, the CPU executes NOPs to maintain memory refresh.

INT.

Interrupt Request (input, active Low).

Interrupt Request is generated by I/O devices.

The CPU honors a request at the end of the current instruction if the internal softwarecontrolled interrupt enable flip-flop (IFF) is enabled. ffii'f is normally wire-ORed and requires an external pullup for these applications. fORQ.

Input/Output Request (output, active

Low, 3-state). IORQ indi'cates that the lower half of the address bus holds a valid I/O address for an I/O read or write operation.

10RQ is also generated concurrently with MI during an interrupt acknowledge cycle to indicate that an interrupt response vector can be placed on the data bus.

Ml. Machine Cycle One (output, active Low).

MI, together with MREQ, indicates that the current machine cycle is the opcode fetch cycle of an instruction execution. MI, together with 10RQ, indicates an interrupt acknowledge cycle.

MREQ. Memory Request (output, active

Low, 3-state). MREQ indicates that the address bus holds a valid address for a memory read or memory write operation.

NMI. Non-Maskable Interrupt (input, negative edge:.!!:!9gered). NMI has a higher priority than INT. NMI is always recognized at the end of the current instruction, independent of the status of the interrupt enable flip-flop, and automatically forces the CPU to restart at location 0066H.

RD. Read (output, active Low, 3-state). RD indicates that the CPU wants to read data from memory or an 110 device. The addressed 110 device or memory should use this signal to gate data onto the CPU data bus.

RESET. Reset (input, active Low). RESET initializes the CPU as follows: it resets the interrupt enable flip-flop, clears the PC and

Registers I and R, and sets the interrupt status to Mode O. During reset time, the address and data bus go to a high-impedance state, and all control output signals go to the inactive state.

Note that RESET must be active for a minimum of three full clock cycles before the reset operation is complete.

RFSH. Refresh (output, active Low). RFSH, together with MREQ, indicates that the lower seven bits of the system's address bus can be used as a refresh address to the system's dynamic memories.

WAIT. Wait (input, active Low). WAIT indicates to the CPU that the addressed memory or 1/0 devices are not ready for a data transfer. The CPU continues to enter a Wait' state as long as this signal is active. Extended

WAIT periods can prevent the CPU from refreshing dynamic memory properly.

WR. Write (output, active Low, 3-state). WR indicates that the CPU data bus holds valid data to be stored at the addressed memory or

110 location.

I

9

17

"Reproduced by permission .1983 Zllog, Inc.

This materiel shall not be reproduced without the written cOMen! of Zilog. Inc."

CPU Timing The ZBO CPU executes Instructions by proceeding through a specific sequence of operations:

• Memory read or write

• 1/0 device read or write

• Interrupt acknowledge

Instruction Opcode Fetch. The CPU places the contents of the Program Counter (PC) on the address bus at the start of the cycle (Figure

5). Approximately one-half clock ~ie

MREQ goes active. When active, RD indicates that the memory data can be enabled onto the

CPU data bus.

The basic clock period is referred to as a

T time or cycle, and three or more T cycles make up a machine cycle (MI, M2 or M3 for instance). Machine cycles can be extended either by the CPU automatically inserting one or more Wait states or by the insertion of one or more Wait states by the user.

The CPU samples the WAIT input with the falling edge of clock state T2. During clock states T3 and T4 of an MI cycle dynamic RAM refresh can occur while the CPU starts decoding and executing the instruction. When the Refresh Control signal becomes active, refreshing of dynamic memory can take place.

T, T,

TW' T.

CLOCK

~-At'

__ __ __

____ -H __ ________ ~ ~-'~

~-D, ~)-_u _~(

C<

=:j!~jC==::t==

NOTE: Tw-Walt cycle added when I18C8814ry for 810w anellliary devices.

Figure 5. JlllllractloD Opcode Fetch

18

"Reproduced by pennission 01983 Zliog. Inc.

This materiallhall not be reproduced without the written coneant 01 Zliog. Inc.".

2005·882

CPU

Timing

(Continued)

Memory Read or Write Cycles. Figure 6 shows the timing of memory read or write cycles other than an opcode fetch (Ml) cycle.

The MREQ and RD signals function exactly as in the fetch cycle. In a memory write cycle.

MREQ also becomes active when the address bus Is stable. The WR line Is active when the data bus is stable, so that it can be used directly as an R/W pulse to most semiconductor memories.

;

•

•

»

»

31

Wfi

J o"":::J:

{

~_D. ______________ (:::::::::::~D~A~n~oo~T:::::::::::::)

Figure 8. Memory R_d or Write Cycl ..

I

9

2005·883

"Reproduced by permission "1983 Zliog. Inc.

This material shall not be reproduced without the written consent of Zilog. Inc,'·

19

CPU

Timing

(Continued)

Input or Output Cyel... Figure 7 shows the timing for an 110 read or 110 write operation.

During 110 operations. the CPU automatically inserts a single Wait state (T w).

This extra Wait state allows sufficient time for an 110 port to· decode the address from the port address linea.

CLOCK

M:{

OPERATION

I iii

WRl~

~T~

Do-Dy _________

-(::::::::::::::::~::::::~~~:::::j

NOTE: Tw' = O~e Wail cycle automatically inserted by CPU.

Figure 7. Input or Output Cyel . .

Interrupt Request/Acknowledge Cycle. Tho:'!

CPU samples the interrupt signal with the rising edge of the last clock cycle at the end of any instruction (Figure 8). When an interrupt is accepted. a special MI cycle is generated.

CLOCK

T, T,

During this MI cycle. 10RQ becomes active

(instead of MREQ) to indicate that the interrupting device can place an 8-bit vector on the data bus. The CPU automatically adds two

Wait states to this cycle.

Tw' TW'

Ao-At. ___________

+--"I .... __________

...;,;PC;;....+ ______ #~J_----_H_--#-,...--

20

... r-

NOTE. 1) TL= Last state 0/ previous instruction.

.. ~~K:

2) Two Wait cycles automatically Inserted by CPU!').

Figure 8. lut.nupt Requestl Ac:kaowlaclge Cyc:l.

"Reproduced by permission .1983 Zilog, Inc.

This material shall not be reproduced without the written consent of Zllog,lnc:."

CPU

Tlming

(Continued)

Non-Nauable Interrupt Request Cycl ••

NMI is sampled at the same time as the maskable interrupt input INT but has higher priority and cannot be disabled under software control.

The subsequent timing is similar to that of a normal instruction fetch except that data put on the bus by the memory is ignored. The

CPU instead executes a restart (RST) operation and jumps to the NMI service routine located at address 0066H (Figure 9).

·I+---------------------IM~,----------------_.I

CLOCK

HI

------~

®\r---

-------H----

Ao·& ..

----------+"1'-+------t-'1"-----+--+----+''-

l1li

• Although m;n i. an asynchronous input. to

~antee its being recognized on the following machine cycle. NMl's falling edge must occur no later than the rising edge of the clock cycle preceding T LAST.

FlgW'e'. Non.Mculcablelnterrupt RequHt Operation

Bu.

Reque.V Acknowledge Cycle. The CPU samples BUSREQ with the rising edge of the last clock period of any machine cycle (Figure

10). If BUSREQ is active, the CPU sets its address, data, and MREQ, IORQ, RD, and WR lines to a high· impedance state with the rising edge of the next clock pulse. At that time, any external device can take control of these lines, usually to transfer data between memory and

va

devices.

T, Tit

CLOCK

I

!

Ao'A ..

=========~=)--fJ---~~----+~

~'D'::=::::::::::::::~=)--fJ_--~~___ --+~

2005·0218. 886 iIitt UNCMANOED

-----------------------+------.-------------------------------

NOTE: TL = Last state of any M cycle. TX = An arbitrary clock cycle used by requ ... Ung deVice.

Figure 10. Z-BUS Requnt/Acknowledge Cycle

"Reproduced by permission ~1983

This material shall not be reproduced without the written consent of Zilog. Inc."

21

CPU

TlmlDg

(Continued)

BaIt Acknowledge Cycle, When the CPU receives a Halt instruction, it executes NOP states until either an INT or NMI input is received. When in the Halt state, the HALT output is active and remains so until an interrupt is received (Figure 11).

111 111 111

_14 _14

:~

tr-'----------

U1 -

NOTE: INT will

4110 force .. Halt exit. 'See note, FlQure 9.

Figure II. Halt Ac:Imowledge Cycle

Reset Cycle, RESET must be active for at least three clock cycles for the CPU to properly accept it. As long as RESET remains active, the address and data buses float, and the control outputs are inactive. Once RESET.goes inactive., three internal T cycles are consumed before the CPU resumes normal processing operation. RESET clears the PC register, so the first opcode fetch will be to location 0000

(Figure 12).

1 - - - 1 1 1 - - - - - -

T •

22

~--------I~Z~ZI~Z~Z-7----·~?--------------\-----------_-_

Figure 12 . . . . Cycle

''Reproduced by permission .1983 Zllog. Inc.

This material sha" nol ba reproduced wilhout lhe wriltencon18nl of Zllog. Inc."

2005-887. 888

AC Characteristics

Number Symbol Parameter

Z80CPU

Min Max

TcC

2 TwCh

3 Twel

4 TIC

Clock Cycle Time

Clock Pulse Width (High)

Clock Pulse Width (Low)

Clock Fall Time

Clock Rise Time 5-TrC

G

7

TdCr(A) Clock I to Address Valid Delay

TdA(MREQf) Address Valid to MREQ

I Delay

H TdCf(MREQI) Clock I to MREQ I Delay

9 TdCr(MREQr) Clock I to MREQ I Delay

10 TwMREOh - -

MREQ

Pulse Width (High) - - 170-

II TwMREQI MREQ Pulse Width (Low) 360-

12 TdCl(MREQr) Clock I to MREQ I Delay

13 TdCl(RDf) Clock I to RD 1 Delay

14 TdCr(RDr) Clock t to RD I Delay

15 TsD(Cr) - - - Data Setup Time to Clock I - - 50

16 ThD(RDr)

17 TsWAIT(Cf)

Data Hold Time to RD I

WATt

Setup Time to Clock 1 70

18 ThWAIT(Cf) WAIT Hold Time after Clock 1

19 TdCr(MlI) Clock I to MI I Delay

20 TdCr(Mlr) - - Clock I to MI I Delay

21 T dCr(RFSHf) Clock I to RFSH I Delay

22 TdCr(RFSHr) Clock I to RFSH I Delay

23 TdCf(RDr) Clock 1 to RD I Delay

24 TdCr(RDf) Clock I to RD I Delay

25 TsD(Cf) - - - Data Setup to Clock I during - 60

M 2• M 3•

~

26 TdA(IORQf) Address Stable prior to IORQ I 320-

27 TdCr(IORQI) Clock I to IORQ I Delay

28 TdCf(IORQr) Clock I to IORQ I Delay

29 TdD(WRf) Data Stable prior to WR I

30 TdCf(WRf) - - Clock I to WR I, Delay

190-

WR Pulse Width 360" 31 TwWR

32 TdCf(WRr)

33 TdD(WRf)

Clock 1 to WR I Delay

Data Stable prior to WR 1 20"

34 TdCr(WRf) Clock I to WR 1 Delay

35 TdWRr(D) - - Data Stable from WR I

36 TdCf(HALT) Clock I to HALT I or I

37 TwNMI NMI Pulse Width

38 TsBUSREQ(Cr) BUSREQ Setup Time to Clock I

120-

SO

SO

400"

180*

180 2000

30

30

145

125-

100

100

100

130

100

0

0

130

130

180

150

110

100

90

110

90

100

80

300

• For clock periods other than the minimums shown in the table, calculate paramntcrs using the expr(.'ssions in the table on the followlfl'l page. t Units

In n.:moseconds (ns). All timings are preliminary and subject ~u change. zaOA CPU

Min Max

250*

110"

110 2000

30

30

110

65"

85

85

110"

220-

85

95

85

35

0

70

0

100

100

130

120

85

85

50

ISO"

75

85

SO-

SO

220"

80

-10"

68

60-

300

80

50

Z80B CPU

M11l Max

Z80HCPUt

Mill Max

165*

65"

65 2000

20

20-·-

125*

55"

55 2000

10

- l O -

90 80

3520-

65-

135*

30

60

70

70

70

80

70

0

0

80

SO-

110

100.

70

70

60

60

45--

100"

60

.

70

60

30-

0

50

0

70

- 7 0 -

95

85

60

60

3040

110*

25-

135-

-55-

30-

7.0

50

65

70

7 0 -

70

60

75*

55

60

5-

- 6 0 -

100"

60

55*

55

15*-

260 225

50"

40

I

I

23

"Reproduced by permission 01983 Zilog, Inc,

This mllterlal shall not be reproduced without the written consent of Zilog, Inc,"

AC Characteristics (Continued)

Number Symbol Parameter

ZIOCPU

Min Max

ZIOACPU

Min Max

39 ThBUSREQ(Cr) BUSREQ Hold Time after Clock 1 0

40 -TdCr(BUSACKI)-Clock 1 to BUSACK I Delay - - - - 120

0

41 TdCf(BUSACKr) Clock I to BUSACK 1 Delay

42 TdCr(Dz) Clock I to Data Float Delay

43 TdCr(CTz) Clock 1 to Control O~puts Float

OelallMREQ. lOR • im. and WR)

110

90

110

44 TdCr(Az) Clock I to Address Float Delay 110

45-TdCTr(A)--MREQ I. IORQ I. RD I. a n d - - l S O * - - - -

WR I to Address Hold Time

SO*

46 TsRESET(Cr) RESET to Clock I Setup Time 90 60

47 ThRESET(Cr) RESET to Clock I Hold Time o

48 TsINTf(Cr) INT to Clock 1 Setup Time 80 SO

49 ThINTr(Cr) INT to Clock I Hold Time o

50 TdMlf(lORQI) -Mi I to iORQ I Delay - - - - 9 2 0 * - - - - 565*

51 TdCf(IORQf)

52 TdCf(IORQr)

53 TdCf(D)

Clock 1 to IORQ I Delay

Clock I to IORQ 1 Delay

Clock I to Data Valid Delay

110

100

230

100

100

90

SO

90

0

0

85

85

ISO

ZIOBCPU

MID Max

0

ZIOHCPUt

Min Max

0

9 0 - - - - S O

90

SO

70

SO

70

60

35*

SO

70

365~

SO

0

0

70

70

130

20*-

"For clock periods other than the minimums shown in the table. cdlculal<' parameters using the following expressions. Calculated values above assumed rrC = rfC

=

20 ns. t Units

In nanoseconds (ns). All timings are preliminary and subject to change.

Foot DOt . . to AC Characteristics

ZIG

2

TcC

TwCh

TwCh + TwCI + TrC + TIC TwCh + TwCI + TrC + TIC TwCh + TwCl + TrC + TIC

Although static by design. Although .tatlc by detllgn. Although static by design.

TwCh 01 greater than 200 1'. TwCh of greater than 200 1'. TwCh of greater than 200 1'.

Is not guaranteed Is not guaranteed Is not guaranteed

7 -TdA(MREQf)-TwCh + TIC - 75----TWCh + TIC - 65----TWCh + TIC - 5 0 ' - - - -

10 TwMREQh TwCh + TIC 30 TwCh + TIC 20 TwCh + TIC 20

11 TwMREQI TcC - 40 TcC - 30

26 TdA(lORQf) TcC - 80 TcC - 70

29 TdD(WRf) TcC - 210 TcC - 170

31-TwWR - - T c C - 40 -:-. - - - - - - T C C - 30

TcC - 30

TcC - 55

TcC - 140

TcC 3 0 - - - - - -

33 TdD(WRf)

35 TdWRr(D)

TwCl + TrC - 180

TwCl + TrC - 80

TwCl + TrC - 140

TwCl + TrC - 70

TwCl + TrC - 140

TwCI + TrC 55.

45 TdCTr(A) TwCl + TrC - 40 Twel + TrC - 50 TwCl + TrC - 50

50 TdMlf(lORQf) 2TcC + TwCh + TIC - 80 2TcC + TwCh + TIC - 65 2TcC + TwCh + TIC - 50

70

45

0

55

0

270*-

SO

60

115

AC Test Conditions:

VIH" :l.OV

VIL" 0.8 V

VIHC = VCC -0.6 V

VILC = 0.45 V

VOH" 2.0V

VOL" 0.8 V

FLOAT .. ;to.S V

24

"Reproduced by pennl .. ZlIog. Inc.

This matsrlellllaJl not be reproduced without the wrltt8n coneant of Zliog. Inc."

Absolute

Maxlmum

Ratlngs

Standard

T.st

Condltlons

-65°C to + 150°C

Temperature under Bias ........ Specified operating range

Voltages on all inputs and outputs with respect to ground. -0.3 V to + 7 V

Power Dissipation . . . . . . . . . . . . . . . . . . . . 1.5 W

Stresses greeter than ihose IIB1ed under Absolute MaxI· mum Rating. may c:auae permanent damage to the device.

This 18 a stress rating only; operation of the device al any condition above those Indlc:aled In the operallonal sections

01 these speclllc:allons Is nol Implied. Expoaure to absolute maximum rallng conditions lor extended periods may affect device reliability.

The characteristics below apply for the following standard test conditions, unless otherwise noted. All voltages are referenced to

GND (0 V). Positive current flows into the referenced pin.' Available operating temperature ranges are:

• S* = O°C to + 70°C,

+4.75 V S Vee S

+5.25 V

• E* = -40°C to +85°C,

+4.75 V s

Vee S +5.25 V

• M* = -55°C to + 125°C,

+4.5 V s Vee S +5.5 V

'SeE' Ordering InforlTl4lion section lor package temperature rat\ge and product number.

All ac parameters assume a load capacitance of 100 pF. Add 10 ns delay for each 50 pF increase in load up to a maximum of 200 pF for the data bus and 100 pF for address and control lines.

.IV u.

':"

I

I

DC

Characterlstics

Symbol Parameter Min Max Unit Test CoDCUUOD

VILe

VIHC

VIL

VIH

VOL

VOH

Ice

III

ILO

Clock Input Low Voltage

Clock Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Power Supply Current

ZSO

ZSOA

ZSOB

Input Leakage Current

3·State Output Leakage Current in Float

I. For military grade parts, ICC ts 200 rnA.

2. Typic.1 rate lor ZSOA is 90 rnA.

-0.3

Vee-·6 VCC+·3 V

-0.3 0.8 V

2.0

0.45 V

Vee

0.4

V

V

2.4 V

IOL= 1.8 rnA

IoH = -250 pA

-10 lSO

I

20()2

200

10 rnA rnA rnA pA

10

3 pA

VIN = OtoVcc

VOUT = 0.4 to Vee

3. AIS-Ao, 07-00, MREQ, IORO. JiI). and WR.

Capacitance Symbol Parameter

Ccl.OCK

C

IN

COUT

Clock Capacitance

Input Capacitance

Output Capacitance

TA = 2soe. I

= I MHz.

MiD Max

35

5

10

Unit Note pF pF pF

Unmeasured pins returned to ground

25 8085·029

"Reproduced by permission .1983 Zliog. Inc.

This material shall not be reproducacl without the written canaant of Zllog, Inc."

Ordering

Information

28400

28400

Z8400

Z8400

28400

28400

Z8400

Z8400

Z8400A

Z8400A

Product

Humber

Package/

Temp Speed Desc:ripllon

CE 2.5 MHz· Z80 CPU (40-pin)

CM 2.5 MHz Same as above

CMB 2.5 MHz Same as above

CS 2.5 MHz Same as above

Z8400A

28400A

28400A

28400A

DE 2.5 MHz Same as above

DS 2.5 MHz Same as above

PE 2.5 MHz Same as above

PS 2.5 MHz

CE 4.0 MHz

Same as above

Z8400A

28400A

28400B

Z8400B

ZSOA CPU (40-pin) 28400B

CM 4.0 MHz Same as above

Product Package/

Humber Temp Speed Description

CMB 4.0 MHz· ZSOA CPU (40-pin)

CS 4.0 MHz Same as above

DE 4.0 MHz Same as above

DS 4.0 MHz Same as above

PE

PS

4.0 MHz Same as above

4.0 MHz Same as above

CS 6.0 MHz ZSOB CPU (40·pin)

DS 6.0 MHz Same as above

PS 6.0 MHz Same as above

'NOTES: C = Ceramic, D = Cerdip. P = Pldstic; E

~

-40·C to +85°C.

MIL·STD·883 Class B pr",," •• mg. S = O·C to + 70·C.

M.= -55·C to + 12SoC, MB = -55·C to + 12S·C with

26

"Reproduced by pennl.ion 01983 Z1log. Inc.

This material shall not bareproduced without tha written consent of Z1log, Inc."

18430

zaer

CTC CoDDlerl

Tbaer Clrcall

Prodael

Speclllc.doD

Zilog

Features • Four independently programmable counter/timer channels, each with a readable downcounter and a selectable

16 or 256 prescaler. Downcounters are reloaded automatically at zero count.

• Three channels have Zero Count/Timeout outputs capable of driving Darlington transistors.

September 1983

• Selectable positive or negative trigger initi'ates timer operation.

• Standard Z-80 Family daisy-chain interrupt structure provides fully vectored, prioritized interrupts without external logic. The eTC may also be used as an interrupt controller .

• Interfaces directly to the Z-BO CPU or-for baud rate generation-to the Z-80 SIO.

I a

General

Description

The Z-80 eTC four-channel counter/timer can be programmed by system software for a broad range of counting and timing applications. The four independently programmable channels of the Z-BO eTC satisfy common microcomputer system requirements for event counting, interrupt and interval timing, and general clock rate generation.

System design is Simplified because the eTC connects directly to both the Z-80 CPU and the

Z-80 SIO with no additional logic. In larger systems, address decoders and buffers may be required.

Programming the eTC is straightforward: each channel is programmed with two bytes; a third is necessary when interrupts are enabled.

Once started, the eTC counts down, reloads its time constant automatically, and resumes counting. Software timing loops are completely eliminated. Interrupt processing is Simplified because only one vector need be specified; the eTC internally generates a unique vector for each channel.

The Z-BO eTC requires a single + 5 V power supply and the standard Z-80 single-phase system clock. It is fabricated with n-channel silicon-gate depletion-load technology, and packaged in a 28-pin plastic or ceramic DIP.

2U41(J1~>4, 0155

CMAMIIa&.

IIGIlALa f f t eLK +sv GND

Figure 1. Pin Functions

"ReprodUCEd by permission 01983 Zilog. Inc.

This material shall not be reproduCED without the written consent of Zilog. Inc."

D.

D.

D.

0,

OND

RD

ZClTOo zcno, zcnOr iOiiCi lEO iii lEi iii lis lis

D,

Do

+IV

ClKITRCIo

ClKITRO,

ClKITRO.

ClKlTRO. cs.

Clo iiiii'i

CI

ClK

59

Functional

Deaeriptlon

The Z-BO CTC has four independent counter/ timer channels. Each channel is individually programmed with two words: a control word and a time-constant word. The control word selects the operating mode (counter or timer), enables or disables the channel interrupt, and selects certain other operating parameters. If the timing mode is selected, the control word also sets a prescaler, which diVides the system clock by either 16 or 256. The time-constant word is a value from 1 to 256.

During operation, the individual counter channel counts down from the preset time constant value. In counter mode operation the counter decrements on each of the CLKlTRG input pulses until zero count is reached. Each decrement is synchronized by the system clock. For counts greater than 256, more than one counter can be cascaded. At zero count, the down-counter is automatically reset with the time constant value.

The timer mode determines time intervals as small as 4 p.s {Z-80A) or 6.4 p.s (Z-80) Without additional logic or software timing loops. Time intervals are generated by dividing the system clock with a prescaler that decrements

.a preset down-counter.

Thus, the time interval is an integral multiple of the clock period, the prescaler value

(16 or 256) and the time constant that is preset in the down-counter. A timer is triggered automatically when Its time constant value is programmed, or by an external CLKlTRG input.

Three channels have two outputs that occur at zero count. The first output is a zerocount/timeout pulse at the ZCITO output. The fourth channel (Channel 3) does not have a

ZC/TO output; Interrupt request is the only output available from Channel 3.

The second output is Interrupt Request

(INT), which occurs if the channel has its interrupt enabled during programming. When the Z-80 CPU acknowledges Interrupt Request, the Z-80 CTC places an interrupt vector on the data bus.

The four channels of the Z-80 CTC are fully prioritized and fit into four contiguous slots in a standard Z-80 daisy-chain interrupt structure. Channel 0 is the highest priority and

Channel 3 the lowest. Interrupts can be indiVidually enabled (or disabled) for each of the four channels.

Architecture The CTC has four major elements, as shown in Figure 3.

• CPU bus I/O

• Channel control logic

• Interrupt logic

• Counter/timer circuits

CPU Bua I/O. The CPU bus I/O circuit decodes the address inputs, and interfaces the

CPU data and control signals to the eTC for distribution on the internal bus.

Internal Control Logic. The CTC internal control logic controls overall chip operating

Junctions such as the chip enable, reset, and read/write logic.

Interrupt Logic. The interrupt control logic ensures that the CTC interrupts interface properly with the Z-80 CPU interrupt system. The logic controls the interrupt priority of the CTC as a function of the lEI signal. If lEI is High, the CTC has priority. During interrupt

DATA

I'IIOM

Z80 CPU

{

CONTROL

Figure 3. FUDCIlODGl Block DIagram

60

2041·0157

"Reproduced by permission 01983 Zllog. Inc.

This material shall not be reproduced without the written consent oi ZilOg. Inc."

.Architecture

(Continued) processing, the interrupt logic holds lEO Low, which lilhlbits the Interrupt operation on lower priority devices. If the lEI input goes Low, priority is relinquished and the Interrupt logic drives lEO Low.

If a channel Is programmed to request an interrupt, the Interrupt logic drives lEO Low at the zero count, and generates an INT signal to the Z-BO CPU. When the Z-BO CPU responds with Interrupt acknowledge (MI and 10RQ), then the interrupt logic arbitrates the CTC internal priorities, and the interrupt control logic places a unique interrupt vector on the data bus.

If an interrupt is pending, the interrupt logic holds lEO Low. When the Z-BO CPU issues a

Return From Interrupt (RETI) instruction, each peripheral device decodes the first byte

(EDI6)' If the device has a pending interrupt, it raises lEO (High) for one Ml cycle. This ensures that all lower priority devices can decode the entire RET! instruction and reset properly. ' npre t. Couater/TI_ Block DIagram

CounterlTlmer Clrcults. The CTC has four independent counter/timer circuits, each containing the logic shown in Figure 4.

ChaDDel Control Logic. The channel control logic receives the S-bit channel control word when the counter/timer channel is programmed. The channel control logic decodes the control word and sets the following operating conditions:

• Interrupt enable (or disable)

• Operatln9 mode (timer or counter)

• Timer mode prescaler factor (16 or 256)

• Active slope for CLKlTRG input

• Timer mode trigger (automatic or CLK/TRG input)

• Time constant data word to follow

• Software reset

TIlDe Constant Register. When the counter/ timer channel is programmed, the time constant reQister receives and stores an S-bit time constant value, which can be anywhere from I to 256 (0 = 256). This constant is automatically loaded into the down-counter when the counter/timer channel is initialized, and subsequently after each zero count.

Presc:aler. The prescaler, which is used only in timer mode, divides the system clock frequency by a factor of either 16 or 256. The prescaler output clocks the down-counter during timer operation. The effect of the prescaler on the down-counter is a multiplication of the system clock period by 16 or 256. The prescaler factor is programmed by bit 5 of the channel control word.

Down-Counter. Prior to each count cycle, the down-counter is loaded with the time constant register contents. The counter is then decremented one of two ways, depending on operating mode:

• By the prescaler output (timer mode)

• By the trigger pulses into the CLKlTRG input (counter mode)

Without disturbing the down-count, the Z-BO

CPU can read the count remaining at any time by performing an I/O read operation at the port address assigned to the CTC channel.

When the down-counter reaches the zero count, the ZCITO output generates a p:>sitivegoing pulse. When the interrupt is enabled, zero count also triggers an interrupt request signal (INT) from the interrupt logic.

I a

2041·015&

"Reproduced by permission 01983 Zilog. Inc,

This material shall not be reproduced without the written consent of ZUog. Inc,"

61

62

Programming Each Z-80 eTe channel must be programmed prior to operation. Programming consists of writing two words to the 1/0 port that corresponds to the desired channel. The first word is a control word that selects the operating mode and other parameters; the second word is a time constant, which is a binary data word with a value from 1 to 256. A time constant word must be preceded by a channel control word.

After initialization, channels may be reprogrammed at any lime. If updated control and time constant words are written to a channel during the count operation, the count continues to zero before the new time constant is loaded into the counter.

If the interrupt on any Z-80 eTC channel is enabled, the programming procedure should also include an interrupt vector. Only one vector is required for all four channels, because the interrupt logic automatically modifies the vector for the channel requesting service.

A control word is identified by a I in bit O.

A I in bit 2 indicates a time constant word is to follow. Interrupt veclors are always addressed to Channel 0, and identified by a 0 in bit O.

Addressing. During programming, channels are addressed with the channel select pins CSI and CS2. A 2-bit binary code selecls the appropriate channel as shown in the following table.

Channel CSI

CSo o

1

0

0

0

'1

2 1 0

3 1 1

Res.t. The CTC has both hardware and software resets. The hardware reset terminates all down-counts and disables all CTC interrupts by resetting the interrupt bits. in the control registers. In addition, the ZC/TO and Interrupt outputs go inactive, lEO reflecls lEI, and o

_. o

SelECTS TIMER MODE

, SELECTS COUNTeR MODE

.

Jj

PIIIICAL." VALUI·

I = VALUE OF 258 o = VALUE OF " o

SELECTS FALUNG EDGE

, SELECTS RISING EDGE t

L

CONTIIOL OR ¥aCTOR o •

VECTOR

I • CONTROL WORD

RnaT o "'

CONTINUED OPERATION

1 = SOFTWARE RESET

TI • • CONITANT o

= NO TIME CONSTANT FOLLOWS

1 = TIME CONSTANT FOLLOWS

~--

"MaRTA,Gal"o = AUTOMATIC TRIGGER WHEN

1 =

TIME CONSTANT IS LOADED

CLKITRG PULS£ STARTS TIMER

"TIMER MODE ONLY

Do-DJ go to the high-impedance state. All channels must be completely reprogrammed afler a hardware reset.

The software reset is controlled by bit 1 in the channel control word. When a channel receives a software reset, it stops counting.

When a software reset is used, the other bits in the control word also change the contents of the channel control register. After a software reset a new time constant word must be written to the same channel.

If the channel control word has both bits 01 and 02 set to I, the addressed channel stops operating, pending a new time constant word.

The channel is ready to resume after the new constant is programmed. In timer mode, if

03

= O. operation is triggered automatically when the time constant word is loaded.

Channel Control Word Programming. The channel control word is shown in Figure 5. It sets the modes and parameters described below.

Interrupt Enable.

DJ enables the interrupt, so that an interrupt output (INT) is generated at zero count. Interrupts may be programmed in either mode and may be enabled or disabled at qny lime.

Operating Mode. 06 selects either timer or counter mode.

Prescaler FaCtor. (Timer Mode Only). 05 seleclsfaclor-either 16 or 256;

Trigger Slope. 04 selects the active edge or slope of the CLK/TRG input pulses. Note that reprogramming the CLKlTRG slope during operation is equivalent to issuing an active edge. If the trigger slope is changed by a control word update while a channel is pending operation in timer mode, the result is the same as a CLK/TRG pulse and the timer starts.

Similarly, if the channel is in counter mode, the counter decrements.

Figure 5. ChollDel Control Word

2041-0159

"Reproduced by permission "1983 Zilog.lnc.

This material shen not be reproduced without the written consent 01 Znog. Inc."

Programming

(Continued)

Trigger Mode (Timer Mode Only). D3 selects the trigger mode for timer operation. When D3 is reset to 0, the timer is triggered automatically. The time constant word is programmed during an 110 write operation, which takes one machine cycle. At the end of the write operation there is a setup delay of one clock period.

The timer starts automatically (decrements) on the rising edge of the second clock pulse (T2) of the machine cycle folloWing the write operation. Once started, the timer runs continuously. At zero count the timp.r reloads automatically and continues counting without interruption or delay, until stopped by a reset.

When D3 is set to I, the timer is triggered externally through the CLK/TRG input. The time constant word is programmed during an

110 write operation, which takes one machine cycle. The timer is ready for operation on the rising edge of the second clock pulse (T2) of the follOWing machine cycle. Note that the first timer decrement follows the active edge of the

CLK/TRG pulse by a delay time of one clock cycle if a minimum setup time to the riSing edge of clock is met. If this minimum is not met, the delay is extended by another clock period. Consequently, for immediate triggering, the CLK/TRG input must precede T2 by one clock cycle plus its minimum setup time. If the minimum time is not met, the timer will start on the third clock cycle (T3).

Once started the timer operates continuously, Without" interruptiori or delay, until stopped by a reset.

Time Constant to Follow. A I in D2 indicates that the next word addressed to the selected channel is a time constant data word for the time constant register. The time constant word may be written at any time.

A 0 in D2 indicates no time constant word is to follow. This is ordinarily used when the channel is already in operation and the new channel control word is an update. A channel will not operate without a time constant value.

The only way to write a time constant value is to write a control word with D2 set.

Software Reset. Setting Dl to I causes a software reset, which is described in the Reset section.

Control Word. Setting Do to 1 identifies the word as a control word.

Time Constant Programming. Before a channel can start counting it must receive a time constant word from the CPU. During programming or reprogramming, a channel control word in which bit 2 is set must precede the time constant word to indicate that the next word is a time constant. The time constant word can be any value from 1 to 256 (Figure

6). Note that 0016 is interpreted as 256.

In timer mode, the time interval is controlled by three factors:

• The system clock period (I/»

• The'prescaler factor (P), which multiplies the interval by either 16 or 256

• The time constant (T), which is programmed into the time constant register

Consequently, the time interval is the product of I/> x P x T. The minimum timer resolution is 16 x I/> (4 /lS with a 4 MHz clock). The maximum timer interval is 256 x I/> x 256 (16.4 ms with a 4 MHz clock). For longer intervals timers may be cascaded.

Interrupt Vector Programming. If the Z-80

CTC has one or more interrupts enabled, it can supply interrupt vectors to the Z-BO CPU.

To do so, the Z-80 CTC must be pre-programmed with the most-significant five bits of the interrupt vector. Programming consists of writing a vector word to the 110 port corresponding to the Z-80 CTC Channel O. Note that Do of the vector word is always zero, to distinguish the vector from a channel control word. Dl and D2 are not used in programming the vector word. These bits are supplied by the interrupt logic to identify the channel requesting interrupt service with a unique interrupt vector (Figure 7). Channel 0 has the highest priority.

I~I~I~I~I~I~I~I~I

:~: gJJ~ ~~:~

L = T C 2

TC. Te3

VlwY:a

SUPPLIED

BY USER

=-oM]

L

0 - INTERRUPT VECTOR WORD

1 CONTROL WORD

CHANNEL IDENTIFIER lAUTOMATICALLY INSERTED

BY CTC) o o.

CHANNEL 0 o

1 . CHANNEL 1

1 o.

CHANNEL 2

1 1 . CHANNEL 3

Figure 7. Interrupt Vector Word Figure 6. Time Constant Word

204!-016(J, V!6! 63

"Reproduced by permission 41>1983 Zilog. Inc,

This material shall not be reproduced without the written consent of Zilog. Inc_"

Pin o..Cl'lptlOD

CEo Chip Enable (input, active Low). When enabled the CTC accepts control words, interrupt vectors, or time constant data words from the data bus during an 1/0 write cycle; or transmits the contents of the down-counter to the CPU during an. I/O read cycle. In most applications this signal is decoded from the eight least significant bits of the address bus for any of the four 1/0 port addresses that are mapped to the four counter-timer channels.

CLK. System Clock (input). Standard singlephase Z-80 system clock.

CLK/TRGo-CLK/TRGa. External Clock/Timer

Trigger (input, user-selectable active High or

Low). Four pins corresponding to the four Z-80

CTC channels. In counter mode, every active edge on this pin decrements the down-counter.

In timer mode, an acti.ve edge starts the timer.

CSo-CS1' Channel Select (inputs active High).

Two-bit binary address code selects one of the four CTC channels for an 1/0 write or read

(usually connected to AQ and AI).

Do-D.,.

System Data Bus (bidirectional,

3-state). Transfers all data and commands between the Z-80 CPU and the Z-80 CTC.

CPU

T

oo.-L

.,ITEM

IU".

Vt--I\ i'f -y

1-

~

'f

-

iNi

PlO lEI iNT lEO leI

.t..

-y

RDV

OM"

Figure 8. A Typlccrl z,,80 EnYlrcmmenl lEI. Interrupt Enable In (input, active High).

A High indicates that no other interrupting devices of higher priority in the daisy chain are being serviced by the Z-80 CPU. lEO. Interrupt Enable Out (output, active

High). High only if lEI is High and the Z-80

CPU is not servicing an interrupt from any

Z-80 CTC channel. lEO blocks lower priority devices from interrupting while a higher priority interrupting device is being serViced.

INT. Interrupt Request (output, open drain, active Low). Low when any Z-80 CTC channel that has been programmed to enable interrupts has a zero-count condition in its down-counter.

IORQ. Input/Output R~est (i~t from CPU, active Low). Used with CE and RD to transfer data and channel control words between the

Z-80 CpU and the Z-80 CTC. During a write cycle, IORQ and CE are active and RD inactive. The Z-80 CTC does not receive a speCific write Signal; rather, it internally generates its own from the inverse of an active

RD signal. In a read cycle, IORQ, CE and RD are active; the contents of the down-counter are read by the Z-80 CPU. If IORQ and MI are both true, the CPU is acknowledging an interrupt request, and the highest priority interrupting channel places its interrupt vector on the Z-80 data bus.

MI. Machine Cycle One (input from CPU, active Low). When Ml and IORQ are active, the Z-80 CPU is acknowledging an interrupt.

The Z-80 CTC then places an interrupt vector on the data bus if it has highest priorit~nd if a channel has requested an interrupt (INT).

RD. Read Cycle Status (input, active Low).

Used in conjunction with IORQ and CE to transfer data and channel control words between the Z-80 CPU and the Z-80 CTC.

RESET. Reset (input active Low). Terminates all down-counts and disables all interrupts by resetting the interrupt bits in all control registers; the ZCITO and the Interrupt outputs go inactive; lEO reflects lEI; Do-D7 go to the high-impedance state.

ZC/TOo-ZC/TOz. Zero Count/Timeout (output, active High). Three ZC/TO pins corresponding to Z-80 CTC channels 2 through 0 (Channel 3 has no ZCITO pin). In both counter and timer modes the output is an active High pulse when the down-counter decrements to zero.

2041-0156 64

"Reproduced by permission .1983 Zilog. Inc.

This material shall not be reproduced without the written consent 01 Zilog. Inc."

Timing Read Cycle Timing. Figure 9 shows read cycle timing. This cycle reads the contents of a down-counter without disturbing the count.

During clock cycle T2. the Z-80 CPU initiates a read cycle by driving the following inputs

Low:RD. fORO. and CEo A 2-bit binary code at inputs CSI and CSo selects the channel to be read. MI must be High to distinguish this cycle from an interrupt acknowledge. No additional wait states are allowed.

T, T, TWA T, T,

CLK latched into the appropriate register with the rising edge of clock cycle T3.

CLIUTRG

Figure 11. nmer Mod. Timing cae. cs ... " iORO

RD

X

CHANNEL ADDRESS

\

\

X

I

I

---~--------------------------

. J

DATA - - - - - - - - -

Figure 9. Read Cycle Timing

Timer Operation. In the timer mode. a

CLK/TRG pulse input starts the timer (Figure

11) on the second succeeding rising edge of

CLK. The trigger pulse is asynchronous. and it must have a minimum Width. A minimum lead time (210 ns) is required between the active edge of the CLK/TRG and the next rising edge of CLK to enable the prescaler on the following clock edge. If the CLK/TRG edge occurs closer than this, the initiation of the timer function is delayed one clock cycle. This corresponds to the startup timing discussed in the programming section. The timer can also be started automatically if so programmed by the channel control word.

Write Cycle Timing. Figure 10 shows write cycle liming lor loading control. time constant or vedor words.

The CTC does not have a write signal input. so it generc~tes one internally when the read

(Fio) illput is High during TI. During T2

IORO and

CE inputs are Low.

'~fi must be

High to distinguish a write cycle from an interrupt acknowledge. A 2-bit binary code at inputs CSI and CSo selects the channel to be addressed. and the word being written is placed on the Z-80 data bus. The ddta word is

CLKITRG

IIITIIRIIAL

COUIITIIR

- - - . . J f

Figure 12. Counter Mode TlmIllg

Clo. CI ..

--IX

CHANNEL ADDRESS

X", __ _ iDRD

._ --'7"----------------------

RD I

. J

.... .,.

.1

• .1

I

------------------------

IN

X'-____ _

Figure 10. Write Cycle Timing

Counter Operation. In the counter mode. the

CLK/TRG pulse input decrements the downcounter. The trigger is asynchronous. but the count is synchronized with CLK. For the decrement to occur on the next rising edqa of eLK. the trigger edge must precede eLK by a minimum lead time as shown in Figure 12. If the lead time is less than speCified, the count is delayed by one clock cycle. The trigger pulse must have a minimum width, and the trigger period must be at least twice the clock period.

The ZC/TO output occurs immediately after zero count, and follows the rising CLK edge.

I a

20410162,0163, OIM, 0165

"Reproduced by permission 01983 Zliog. Inc.

This material shall not be reproduced without the written consent of Zilog. Inc,"

65

Interrupt

OperatloD

The Z-BO CTC follows the Z-BO system Interrupt protocol for nested priority Interrupts and return fron: interrupt, wherein the Interrupt priority of a peripheral Is determined by its location In a daisy chain. Two lines-lEI and lEO-in the CTC connect It to the system daisy chain. The device closest to the + 5 V supply has the highes.t priority (Figure 13). For additionallnformation on the Z-BO interrupt structure, refer to the Z-80 CPU Product Specifica- tion and the Z-80 CPU Technical Manual.

T PIIIORITT

DaVICE

!.Owan

PRIORITY

DaVICE

Figure 13. Daisy-Chain Interrupt Priorities

Within the Z-BO CTC, interrupt priority Is predetermined by channel number: Channel 0 has the highest priority, and Channel 3 the lowest. If a device or channel Is being serviced with an Interrupt routine, it cannot be interrupted by a device or channel with lower priority until service Is complete. Higher priority devices or channels may interrupt the servicing of lower priority deVices or channels.

A Z-BO CTC channel may be programmed to request an interrupt every time Its downcounter reaches zero. Note that the CPU must be programmed for interrupt mode 2. Some time after the interrupt request, the CPU sends an Interrupt acknowledge. The CTC Interrupt control logiC determines the highest priority channel that is requesting an interrupt. Then,

If the CTC lEI Input Is High (indicating that It has priority within the system daisy chain) it places an 8-bit Interrupt vector on the system data bus. The high-order five bits of this vector were written to the CTC during the programming Processi the next two bits are provided by the CTC interrupt control logiC as a binary code that Identifies the highest priority channel requesting an Interrupti the low-order bit is always zero.

Interrupt Acbowledp TImlDg. Figure 14 shows interrupt acknowledge timing. After an interrupt request, the Z-80 CPU sends an interrupt acknowledge (MI and IORQ). All channels are inhibited from changing their interrupt request status when Mils active-about two clock cycles earlier than IORQ. RD is

High to distinguish this cycle from an instruction fetch.

The erc

Interrupt logic determines the highest priority channel requesting an interrupt. If the erc

Interrupt enable input (lEI) is

High, the highest priority interrupting channel within the CTC places Its Interrupt vector on the data bus when lORa goes Low. Two walt states (TWA) a.e automatically inserted at this time to allow the daisy chain to stabilize. Additional wait states may be added.

RetW'D from IDterrupt Tlmlag. At the end of an Interrupt service routine the RETI (Return

From Interrupt) Instruction Initializes the daisy chain enable lines for proper control of nested priority Interrupt handling. The CTC decodes the 2-byte RETI code internally and determines whether It Is Intended for a channel being serviced. Figure 15 shows RETI timing.

If several Z-BO peripherals are In the daisy

. chain, lEI settles active (High) on the chip currently being serviced when the opcode

EDI6 Is decoded. If the follOWing opcode Is

4DI6, the peripheral being serviced Is released and Its lEO becomes active. Additional wait states are allowed.

CLK

T,

TWA TWA

\~_..JI

T.

T,

CLK iIi'1\ iii)

T, T. T. T, T,

I \ I

T. T.

Do-D, ED

-

-

-

-

- - -

-,----

.....

-

- - --

DATA------------------~~~------

IEO _ _ _ _ _ _ _ _ _ _ _ _ _

Jr

Figure 14. IlIterrupt Acknowledge TimID; Figure 15. Retlll'D From IDtemapt Tlm1Dg

2041·0166.0167.0168 66

"Reproduced by permillion 01983 Zilog. Inc.

This material shall not be reproduced without the written connnt of Zilog. Inc."

Absolute

Maximum

Ratings

CondltloDS

DC

Characteristics

Voltages on all Inputs and outputs with respect to GND .......... -0.3 V to + 7.0 V

Operating Ambient As Specified in

Temperature ........... Ordering Information

Storage Temperature ........ -65°e to + 150

0 e

Stresses greater than those listed under Absolute Maxi· mum Ratings may cause permanent damage to the device.

This is a stress rating only; operation 01 the device at any condition above those indicated in the operational sections

01 these specilications is not implied. Exposure to absolute maximum rating conditions lor extended periods may alfect device reliability.

V

Il.C

V

IHe

V

1L

V

IH

VOL

V

OH

Icc

III

ILO loHD

The characteristics below apply for the follOWing test conditions, unless otherwise noted. All voltages are referenced to GND

(0 V). Positive current flows into the referenced pin. Available operating temperature ranges are:

• S* = ooe to + 70°C,

+4.75 V:s Vee:s +5.25 V

• E* = -40 oe to +85°e,

+4.75 V:s Vee:S +5.25 V

• M* = -55°e to + 125°C,

+4.5 V:s Vee:s +5.5 V

Symbol Parameter

Clock Input Low Voltage

Clock Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Power Supply Current

Input Leakage Current

3·Slale Outpul Leakage Current in Float

Darlington Drive Current

'See Ordering Inlormation section lor package temper.ture range and product number.

Min Max UDtt

-0.3 +0.45

Vee-.6 Vee +.3

-0.3 +0.8

+2.0 Vee

+0.4

+2.4

+20

±IO

±IO

-1.5

V

V rnA p.A p.A rnA

V

V

V

V

+IV

.... t Condition loL=2mA loH

= 250 p.A

.VIN

=

0 to Vee

Vour

VO H

R EXT

=

0.4 to Vee

=

1.5 V

= 390ll

I a

Symbol Parameter

CLK

C

1N

Cour

Clock Capacitance

Input CapaCitance

Output Capacitance

TA

=

25°C. f

=

1 MHz

Max

20

5

10

UDtt pF pF pF

CoDditioD

Unmeasured pins returned to ground

8085·0239

"Reproduced by permission 0'983 Zliog. Inc.

This malarial shall not be reproduced without the written canasnt of Zliog. Inc."

67

68

MAD

WRITII

CLOCK

..J

- - - 0 r----,

~

-<D-

.(D.~

n nu~

Cio. CI,

Ci iiRQ

IX X

1----0-~I

~

I-<!>-

~

I~

L

@-I--I

L r<!H

AD

I~

L

FA

-#-

DATA

I..=-@~

CIo.CI, . ci iiRQ

DATA

\.

I~

~

~

X X

1-0-~

L

~I

L

~

X X

I--®-~I

M1

\.

I~ I-<H

IIITIiRRUPT

ACKNOWLIIDQII lORQ

'\

~

DATA

-#-

~-

""

~

\.

'II'

)

111O iiiT

CLltlTRQo_1

(COUNTER

MODE)

CLKITRQo-I

(TIMER

MODE)

ZC1T00-2

" n

®-I j

~

®-Ir~

r---®-

-!-

-@-

~

~

_I

W

) k~

.~ \.

~

"Reproduced by permission "'1983 Zilog. Inc.

This malerial shall not be reproduced without the written consent of Zilog. Inc."

Number Symbol Para ......

Z-80CTC

MID

Z-IOACTC Z-8OB eTC

Max MID Max MID Max

CDI) CDI) CDI) C-) C-) CDI) Notes-

TcC

2 TwCH

3 TwCl

4 TfC

5-TrC

6 Th

7 TBCS(C)

Clock Cycle Time

Clock Width (High)

Clock Width (Low)

Clock Fall Time

Clock Rise Time

All Hold Times

CS to Clock I Setup Time

400

.170

170

0

250

8 TsCE(C)

9 TsIO(C)

CE to Clock I Setup Time 200

IORQ I to Clock I Setup Time 2SO

10 TsRD(C) - - RD I to Clock I Setup Time - - 240

(1)

2000

2000

30

30

250 [1)

105 lOS

0

160

ISO

115

115

2000

2000

30

30

II TdC(DO) Clock I to Data Out Delay

12 TdC(DOz) Clock I to Data Out Float Delay

13 TsDl(C)

14 TsMI(C)

Data In to Clock I Setup Time 60 m to Clock I Setup Time 210

15 TdMI(IEO)- Ml I to lEO I Delay (Int~pt

Immedl~tely preceding Ml)

16 TdIO(DOI) IORQ I to Data Out Delay

(lNT A Cycle)

240

230

300

340

SO

90

200

110

190

160

0

100

100

70

70

165 (1)

65

65

2000

2000

20

20

130

90

40

70

130

110

(2)

(3)

(2)

17 TdIEI(lEOf) lEI I to lEO I Delay

18 TdIEI(IEOr) lEI t to lEO I Delay

(After ED Decode)

19 TdC(lNT) Clock I to INT I Delay

190

220

(TcC+2OO)

130 100

160 110

(TcC+ 140) TcC+ 120

(3)

(3)

(4)

20 TdCLK(lNT) CLKITRG I to INT I

IsCTR(C) satisfied tsCTR(C) not satisfied

21 TcCTR

22 TrCTR

CLK/TRG Cycle Time

CLKlTRG Rise Time

23 TfCTR

24 TwCTRI

CLKITRG Fall Time

CLKITRG Width (Low)

25 TwCTRh - - CLKITRG Width (High)

26 TsCTR(Cs) CLKlTRG I to Clock , Setup

Time for Immediate Count

27 TsCTR(Ct) CLKITRG I to Clock I Setup

Time for enabling of Prescaler on following clock'

28 TdC(ZCITOr) Clock , to ZCITO , Delay

29 TdC(ZClTOf) Clock I to ZCITO I Delay

(19) + (26)

(1) +(19) + (26)

(2TcC)

(19) +(26) (19) + (26) IS)

(1)+(19)+(26) (1)+(19)+(26) IS)

(2TcC) 2TcC IS)

SO

SO

SO

SO

40

40

200

200

200

200

120

120

300

210

260

190

210

210

190

!90

ISO

ISO

I

140

140

IS)

(4)

(AI 2.5 TcC

+ TTL

> (n·2) TdIEI(lEOI) buller delay. II any.

+ TdMI(IEO) + TIIEI(lO)

(S) RESET must be active lor a minimum 01 3 clock cycles.

NOTES:

III TcC = TwCh + TwCl + TrC + TIC.

(21 Increase delay by 10 ns lor each 50 pF inc ..... se In loading.

200 pF maximum lor data lines, and 100 pF lor control Unes.

131 Increa . . delay by 2

III lor .... ch 10 pF Inc ....... In loedlll9.

100 pF maximum.

14) Timer mode.

151 Counter mode.

(6) RESET must be aclive lor a minimum 0/ 3 clock cycles.

• All timings are preliminary and subject to change.

I a

69

"Reproduced by permission 01983 ZlIog. Inc.

This malerial shall not be reproduced wilhout lhe written coneenl of Z1Iog, Inc."

Z8430

28430

28430

28430

28430

28430

28430

28430

28430A

28430A

Product

Number

Paclcagel

T.mp Speed DetcrlptloD

CE 2.5 MHz

CM 2.5 MHz

CMB 2.5 MHz

CS 2.5 MHz

ZSO CTC (28-pin)

Same as above

Same as above

Same as above

DE 2.5 MHz Same as above

DS 2.5 MHz Same as above

PE

PS

2.5 MHz

2.5 MHz

Same as above

Same as above

Z8430A

Z8530A

Z8430A

Z8430A

Z8430A

Z8430A

Z8430B

Z8430B

CE 4.0 MHz ZSOA CTC (28-pin) 28430B

CM 4.0 MHz Same as above

Product Paclcagel

Number Temp Speed DetcrlptlOD

CMB 4.0 MHz ZSOA CTC (28-pin)

CS 4.0 MHz Same as above

DE 4.0 MHz Same as above

DS 4.0 MHz

PE 4.0 MHz

Same as above

Same as above

PS 4.0 MHz Same as above

CS 6.0 MHz Same as above

DS 6.0 MHz Same as above

PS 6.0 MHz Same as above

'NOTES; C ' Cerdrmc. D = Ccrdip, P = Pldstie; E = -40·C to

MII.·STD·683 Class B processing. S = O·C to + 70·C.

+ 8S"C, M = -SS·C to + 12S"C, MB = -5SoC to + 125°C with

70

"Reproduced by permlasion 0t983 Zllog, Inc.

This malerial shall not be reproduced without the written consent of Zllog, Inc."

Zilog

Z8470 Z80@ DABT

Dual~JDcbroDoas

Becelver/Transmltter

Prodact

IpecUlcadoD

Features

Description

• Two independent full-duplex channels with separate modem controls. Modem status can be monitored.

• In xl clock mode, data rates are 0 to 500K bits/second' with a 2.5 MHz clock, or 0 to

800K bits/second with a 4.0 MHz clock.

• Receiver data registers are quadruply buffered; the transmitter is doubly buffered.

• Programmable options include I, I Y2 or 2 stop bits; even, odd or no parity; and xl, x16, x32 and x64 clock modes.

The Z-BO DART (Dual-Channel Asynchronous Receiver/Transmitter) is a dual-channel multi-function peripheral component that satisfies a wide variety of asynchronous serial data communications requirements in microcomputer systems. The Z-80 DART is used as a serial-to-parallel, parallel-to-serial converter/ controller in asynchronous applications. In addition, the device also provides modem controls for both channels. In applications where

September 1983

• Break generation and detection as well as parity-, overrun- and framing-error detection are available.

• Interrupt features include a programmable interrupt vector, a "status affects vector" mode for fast interrupt processing, and the standard Z-BO peripheral daisy-chain interrupt structure that provides automatic interrupt vectoring with no external logic.

• On-chip logic for ring indication and carrier-detect status. modem controls are not nee4ed, these lines can be used for general-purpose 1/0.

Zilog also offers the Z-BO

sio,

a more versatile device that provides synchronous

(Bisync, HDLC and SDLC) as well as asynchronous operation ..

The Z-80 DART is fabricated with n-channel silicon-gate depletion-load technology, and is packaged in a 40-pin plastic or ceramic DIP.

Cpu{

DATA

BU.

{ m:

CONTROL iORa

"=

IiIJ iii

CI6

8Ii

+5V GND elK

Figure 1. Z80 DART PID FUJlc:lloDB

RaDA

Ir.i!l

TaDA r.a

WiIIIi\'l

I8l

!!TIl

C'IIl

I7rQ

III!IIl

CN·A

RaDII liiiTiil!I

TaDII

WiRDVI

-}~

DTAB iiC6iI ell-B

D,

D,

Do

Dr

IRT lEI lEO iii

Yao

WIIf9'il

I8l

RaDA

RiCA

~

TaDA

Il'i'Iil iifiA

CTil

6C6A eLK

0"

0,

D. lilt

ClI!

IiIJ

GND

WlIIOva

101

RaDI iiir.CI

TaDI iifiii iif8i

Cilili iiC6iI iifift

2044·002, 007 87

"Reproduced by permission 01983 ZlIog, Inc.

This material shall not be reproduced without the written consent of Zllog, Inc."

Pin

Description

I/A. Channel A Or.B Select (input. High selects Channel B). This input defines which channel is accessed during a data transfer between the CPU and the l-BO DART.

C/D. Control Or Dota Select (input, High selects Control). Thisinpu! specifies the type of information (control or data) transferred on the data bus between the CPU and the l-80

DART.

CEo Chip Enable (input, active Low). A Low at this input enables the l-80 DART to accept command or data input from the CPU during a write cycle. or to transmit data to the CPU during a read cycle.

CLK. System Clock (input). Th~ l-80 DART uses the standard l-80 single-phase system clock to synchronize internal signals.

CTSA. CTSI. Clear To Send (inputs. active

Low). When programmed as Auto Enables, a

Low on these inputs enables the respective transmitter. If· not programmed as Auto

Enables, these inputs may be programmed as general-purpose inputs. Both inputs are

Schmitt-trigger buffered to accommodate slowrisetime signals.

Do·D,. System Data Bus (bidirectional.

:3-state) transfers data and commands between the CPU and the l-80 DART.

DCDA. DCDB. Data Carrier Detect (inputs. active Low). These pins function as receiver enables if the l-80 DART is programmed for

Auto Enables; otherWise they may be used as general-purpose input pins. Both pins are

Schmi tt -trigger buffered.

DTRA. DTRB. Data Terminal Ready (outputs, active Low), These outputs follow the state programmed into the DTR bit. They can also be programmed as general-purpose outputs. lEI. Interrupt Enable In (input. active High) is used with lEO to form a priority daisy chain when there is more than one interrupt-driven device. A High on this line indicates that no other device of higher priority is being serviced by a CPU interrupt service routine. lEO. Interrupt Enable Out (output. active

High). lEO is High only if lEI is High and the

CPU is not servicing an interrupt from Ihis •

Z-80 DART. Thus. this signal blocks lower priority devices from interrupting while a higher priority device is being serviced by its '

CPU interrupt service routine.

INT. Interrupt Request (output, open drain. active Low). When the 2-80 DART is requesting an interrupt, it pulls iNT Low.

MI. Machine Cycle One (input from l-BO

CPU. active Low), When Mi" and RD are both active, the l-BO CPU is fetching an instruction from memory; when Ml is active while IORQ is active. the l-80 DART accepts

M1 and iORQ as an interrupt acknowledge if the l-BO DART is the highest priority device that has iriterrupted the l-BO CPU.

10RQ. Input/Output Request (input from CPU, active Low). 10RQ is used in conjunction with

BIA, C/O, CE and RD to transfer commands and data between the CPU and the l-80

DART. When.CE, RD and IORQ are all active, the channel selected by BlAtransfers data to the CPU (a read o~ation).

When

CE and IORQ are active, but RD is inactive, the channel selected by BIA is written to by the

CPU with either data or control information as s~cified by C/O.

RxCA. RxCB. Receiver Clocks (inputs).

Receive data is sampled on the rising edge of

RxC. The Receive Clocks may be I,

I6~

32 or

64 times the data rate.

RD. Read Cycle Status. (input from CPU, active Low). If RD is active, a memory or 110 read operation is in progress.

RxDA. RxDB. Receive Data (inputs, active

High),

RESET. Reset (input, active Low). Disables both receivers and transmitters, forces TxDA and TxDB marking, forces the modem controls

High and disables all interrupts.

RIA. RIB. Ring Indicator (inputs, At:tive

Low). These inputs are ,similar to CTS and

DCD. The l-80 DART detects both logic level transitions and interrupts the CPU. When not used in switched-line applications, these inputs can be used as general-purpose inputs.

RTSA. RTSB. Request to Send (outputs, active Low). When the RTS bit is set, the RTS output goes Low. When the RTS bit is reset, the output goes High after the transmitter empties.

TxCA. TxCB. TransmJiter Clocks (inputs). TxD changes on the falUng edge of TxC. The

Transmitter Clocks may be I, 16, 32 or 64 times the data rate; however, the clock multiplier for the transmitter and the receiver must be the same. The Transmit Clock inputs are Schmitt-trigger buffered. Both the Receiver and Transmitter Clocks may be driven by the

l-80 CTC Counter Time Circuit for program· mabIe baud .rate generatIOn. .

TxDA. TxDB. Transmit Dota (outputs, active

High).

WfRDYA. W!RDYB. Wait/Ready (outputs, open drain when programmed for Wait function, driven High and Low when programmed . for Ready function). These dual-purpose outputs may be programmed as Ready lines for a

DMA 'controller or as Wait lines that synchronize the CPU to the l-BO DART data rate.

The reset state is open drain.

88

"Rliproducad by permission .1983 Zilog. Inc,

This material shall not be reproduced without the written conSent of Zilog. Inc,"

FunctloDal The functional capabilities of the Z-80 DART can, be described from two different points of view: as a data communications device, it transmits and receives serial data, and meets the reqUirements of asynchronous data communications protocols; as a

z-oo

family peripheral, it interacts with the Z-80 CPU and other Z-OO peripheral circuits, and shares the data, address and control buses, as well as being a part of the Z-80 interrupt structure. As a peripheral to other microprocessors, the Z-OO

DART offers valuable features such as nonvectored interrupts, polling and Simple handshake capability.

CommunlcatloDII Capabllitl ... The Z-OO

DART provides two independent full-duplex channels for use as an asynchronous receiver/transmitter. ThA follOWing is a short description of receiver/transmitter capabilities.

For more details, refer to the Asynchronous

Mode section of the Z-80 S10 Technical

Manual. The Z-80 DART offers transmission and reception of five to eight bits per character, plus optional even or odd parity.

The transmitter can supply one, one and a half or two stop bits per character and can provide a break output at any time. The receiver break detection logic interrupts the CPU both at the start and end of a received break. Reception is protected from spikes by a transient spike rejection mechanism that checks the signal onehalf a bit time after a Low level is detected on the Receive Data input. If the Low does not persist-as in the case of a transient-the character assembly process is not started.

I/O Interface Capab~lltl... The Z-80 DART offers the choice of Polling, Interrupt (vectored or non-vectored) and Block Transfer modes to transfer data, status and control information to

The first part of the following functional description introduces Z-OO DART data communications capabilities; the second part describes the Interaction between the CPU and the Z-80 DART.

The Z-OO DART offers RS-232 serial communications'support by providing device signals for external modem control. In addition to dual-channel Request To Send, Clear To

Send, and Data Carrier Detect ports, the Z-OO

DART also features a dual channel Ring Indicator (RIA, RIB) input to facilitate

10caVremote or station-to-statlon communication capability.

Framing errori and overrun 'errors are detected and buffered together with the character on which they occurred. Vectored interrupts allow fast servicing of interrupting conditions using dedicated routines. Furthermore, a built-in checking process avoids interpreting a framing error as a new start bit: a framing error results in the addition of one-half a bit time to the point at which the search for the next start bit is begun.

The Z-OO DART does not require symmetric

Transmit and Receive Clock signals-a feature that allows it to be used with a Z-OO CTC or any other clock source. The transmitter and receiver can handle data at a rate of 1, 1/16,

1/32 or 1/64 of the clock rate supplied to the

Receive and Transmit Clock inputs. When using Channel B. the bit rates for transmit and receive operations must be the same because

RxC and TxC are bonded together (RxTXCB). and from the CPU. The Block Transfer mode can be implemented under CPU or DMA control.

I

I

.EIUAL .... TA

INTERNAL

CONTROL

LOGIC

_OR

OTNIIII CONTIICIU

INTERNAL IUS

INTIRRUPT

UN., t t t

+SVONDCLK

INTERRUPT

CONTROL

LOGIC

CltANNELI

READlWRITE

REGISTERI

Figure 3. Block Diagram iii

_ .... TA

CHANNIL ct.OCIC

WIIflIIUII'P

2044-001 89

"Reproduced by permlaslon .1983 Ziiog. Inc,

This material shall not ba reproduced without ths writtan con.,.t 01 Zilog. Inc,"

Functional

Description

(Continued)

POllING. There are no interrupts in the

Polled mode. Status registers RHO and RRI are updated at appropriate times for each function being performed. All the interrupt modes of the Z-80 DART must be disabled to operate the device in a polled environment.

While in its Polling sequence, the CPU examines the status contained in RRO for each channel; the RRO status bits serve as an acknowledge to the Poll inquiry. The two RRO status bits DO and D2 indicate that a data transfer is needed. The status also indicates

Error or other special status conditions (see

"Z-80 DART Programming"). The Special

Receive Condition status contained in RRI does not have to be read in a Polling sequence because the status bits in RRI are accompanied by a Receive Character Available status in RHO.

INTERRUPTS. The Z-80 DART offers an elaborate interrupt scheme that provides fast interrupt response in real-time applications. As a member of the Z-80 family, the Z-80 DART can be daisy-chained along with other Z-80 peripherals for peripheral interrupt-priority resolution. In addition, the internal interrupts of the Z-80 DART are nested to prioritize the various interrupts generated by Channels A and B. Channel B registers WR2 and RR2 contain the interr.upt vector that points to an interrupt service routine in the memory. To eliminate the necessity of writing a status analysiS routine, the'Z-80 DART can modify the interrupt vector in RR2 so it points directly to one of eight interrupt service routines. This is done under program control by setting a program bit (WR I, D

2) in Channel B called

"Status Affects Vector." When this bit is set, the interrupt vector in RR2 is modified according to the assigned priority of the various interrupting conditions.

Transmit interrupts, Receive Interrupts and

External/Status interrupts are the main sources of interrupts. Each interrupt source is enabled under program control with Channel A having a higher priority than Channel B, and with

Receiver, Transmit and External/Status interrupts prioritized in that order within each channel. When the Transmit interrupt is enabled, the CPU is interrupted by the transmit buffer becoming empty. (This implies that the transmitter must have had a data character written into it so it can become empty.) When enabled, the receiver can interrupt the CPU in one of three ways:

• Interrupt on the first received character

• Interrupt on all received characters

• Interrupt on a Special Receive condition

Interrupt On First Character is typically used with the Block Transfer mode. Interrupt

On All Receive Characters can optionally modify the interrupt vector in the event of a parity error. The Special Receive Condition interrupt can occur on a character basis. The

Special Receive condition can cause an interrupt only if th~ Interrupt On First Receive

Character or Interrupt On All Receive Characters mode is selected. In Interrupt On First

Receive Character, an interrupt can occur from Special Receive conditions (except Parity

Error) after the first receive character interrupt

(example: Receive Overrun interrupt).

The main function ofthe External/Status interrupt is to monitor the signal transitions of the CTS, DCD and RI pins; however, an

External/Status interrupt is also causFld by the detection of a Break sequence in the data stream. The interrupt caused by the Break sequence has a special feature that allows the

Z-80 DART to interrupt when the Break sequence is detected or terminated. This feature facilitates the proper termination of the current message, correct initialization of the next message, and 'the accurate timing of the

Break condition.

CPUlDMA BLOCK TRANSFER. The Z-80

DART provides a Block Transfer mode to accommodate CPU block transfer functions and DMA block transfers (Z-80 DMA or other designs). The Block Transfer mode uses the

W

WaiVReady bits of Write Register 1. The

WIRDY output can be defined under software control as a Wait line in the CPU Block

Transfer mode or as a Ready line in the DMA

Block Transfer mode.

To a DMA controller, the Z-80 DART Ready output indicates that the Z-80 DART is ready to

, transfer data to or from memory. To the CPU, the Wait output indicates that the Z-80 DART is not ready to transfer data, thereby requesting the CPU to extend tne 110 cycle.

90

"Reproduc:ed by permission 01983 Zllog.lnc.

This material shaH not be reproduced without the written consent of Zllog, Inc."

Internal

Architecture

The device internal structure includes a Z-80

CPU interface, internal control and interrupt logic, and two full-duplex channels. Each channel contains read and write registers, and discrete control and status logic that provides the interface to modems or other external devices.

The read and write register group includes five 8-bit control registers and two -status registers. The interrupt vector is written into an additional8-bit register (Write Register 2) in Channel B that may be read through Read

Register 2 in Channel B. The registers for both channels are designated as follows:

WRO-WRS Write Registers 0 through S

RRO-RR2 Read Registers 0 through 2

The bit assignment and functional grouping of each register is configured to Simplify and organize the programming process.

The logic for both channels provides formats, bit synchronization and validation for data transferred to and from the channel interface. The modem control inputs Clear to Send

(CTS), Data Carrier Detect (DCD) and Ring

Indicator (RI ) are monitored by the control logic under program control. All the modem control signals are general purpose in nature and can be used for functions other than. modem control.

For automatic interrupt vectoring, the interrupt control logic determines which channel and which device within the channel has the highest priority. Priority is fixed with Channel

A assigned a higher priority thim Channel B;

Receive, Transmit and External/Status interrupts are prioritized in that order within each channel.

Data Path. The transmit and receive data path illustrated for Channel A in Figure 4 is identical for both channels. The receiver has three

8-bit buffer registers in a FIFO arrangement in addition to the 8-bit receive shift register. This scheme creates additional time for the CPU to service a Receive Character Available interrupt in a high-speed data transfer.

The transmitter has an 8-bit transmit data register that is loaded from the internal data bus, and a 9-bit transmit shift register that is loaded from the transmit data register.

I

•

&

TxDA .

RICIlY.

ERROR

LCI8IC

Figure". Data Path

"Reproduced by permlulon .1983 Zilog, Inc.

This materiel shall not be reprodUced without the written CO/lHflt of Zilog. Inc."

$1

Read.

Write cmd

Interrupt

Timing

Read Cycle. The timing signals generated by a Z-80 CPU input instruction to read a Data or

Status byte frpm the Z-BO DART are illustrated

In Figure Sa.

Write Cycle. Figure 5b illustrates the timing and data signals generated by a Z-BO CPU output instrucUon to write a Data or Control byte into the Z-BO DART.

Interrupt Ac:lmowled.ge Cycle. After receiving an Interrupt Request signal (INf pulled

Low). the Z-BO CPU sends an Interrupt

Acknowledge signal (Ml and IORQ both Low).

The daisy-chained interrupt Circuits determine the highest priority interrupt requestor. The lEI of the highest priority peripheral is terminated

High. For any peripheral that has no interrupt pending or under service, lEO

= lEI. Any peripheral that does have an interrupt pending or under service forces its lEO Low.

To insure stable conditions In the daisy chain, all interrupt status signals are prevented from changing while

MI is ·Low. When iOHO is

Low. the highest priority interrupt requestor

(the one with lEI High) places its interrupt vector on the data bus and sets its internal interrupt-under-service latch.

Refer to the Z-BO SIO Technical Manual for additional details on the interrupt daisy chain and interrupt nesting.

Return From Interrupt Cycle. Normally, the

Z-BO CPU Issues an RETI (Return From Interrupt) instruction at the end of an interrupt service routine. RET! is a 2-byte opcode (ED-4D) that resets the interrupt-under-service latch to terminate the interrupt that has just been processed.

When used with other CPUs, the Z-80 DART allows the user to return from the interrupt cycle with a special command called "Return

From Interrupt" in Write Register 0 of Channel

A. This command is interpreted by the Z-BO

DART in exactly the same way it would interpret an RETI command on the data bus.

T, Tt

CLOCK

Ci

____

-',~---------J

T t

T t

T, Tw T,

CLOCK f t

____ -',+-__________

r'-__ __

~------------------------------

DATA

-------------------cE)t---

FIgure Sa. Read Cycle

u------------------------

~------------------------------

DATA __________

X"' ____ _

F~

Write Cre1tt

92

CLOCK ill

\~

__JI

',-_-,I

B-----------------

1 \ ____ _

DATA------------------i~~---

DO-D,

••• - - - - - - I

------.1

10 ______________________

....,1

Figure Sc. IDlerrupt Aclmowledge Cye1tt

2044-008, 009, 010, 011

"Reproduced by permiulon 01983 Z1log. Inc.

This material shall nQl be reproduced without the written consent of Z11og. Inc."

Z-80 DART

Programming

To program the 2-80 DART, the system program first issues a series of commands that initialize the basic mode and then other commands that qualify conditions within the selected mode. For example, the character length, clock rate, number of stop bits, even or odd parity are first set, then the Interrupt mode and, finally, receiver or transmitter enable.

Both channels contain command registers that must be programmed via the system program prior to operation. The Channel Select input (B/A) and the Control/Data input (C/D) are the command structure addressing controls, and are normally controlled by the CPU address bus.

Write Registers. The 2-80 DART contains six registers (WRO- WR5) in each channel that are programmed separately by the system program to configure the functional personality of the channels (Figure 4). With the exception of

WRO, programming the write registers requires two bytes. The first byte contains three bits

(0

0

-0

2) that point to the selected register; the second byte is the actual control word that is written into the register to configure the 2-80

DART.

WRO is a special case in that all the basic commands (CMD o -CMD

2) can be accessed with a single byte. Reset (internal or external) initializes the pointer bits 0

0

-0 2 to point to

WRO. This means that a register cannot be pOinted to in the same operation as a channel reset.

Write Register FuDCtloDS

WRO Register pointers, initialization commands for the various modes, etc.

WRI TransmiVReceive interrupt and data transfer mode definition.

WR2 Interrupt vector (Channel B only)

WR3 Receive parameters and control

WR4 T ransmiVReceive' miscellaneous parameters and modes

WRS Transmit parameters and controls

I

I

Read Registers. The 2-80 DART contains three registers (RRO-RR2) that can be read to obtain the status information for each channel

(except for RR2, which applies to Channel B only). The status information includes error conditions, interrupt vector and standard communications-interface signals.

To read the contents of a selected read register other than RRO, the system program must first write the pointer byte to WRO in exactly the same way as a write register operation. Then, by executing an input instruction, the contents of the addressed read register can be read by the CPU.

The status bits of RRO and RRI are carefully grouped to simplify status monitoring. For example, when the interrupt vector indicates that a Special Receive Condition interrupt has occurred, all the appropriate error bits can be read from a single register (RRl).

Read Register FuDCtloDS

RRO TransmiVReceive buffer status, interrupt status and external status

RRI Special Receive Condition status

RR2 Modified interrupt vector (Channel B only)

'"Reproduced by permiSSion 1>1983 Zilog. Inc.

This material shall not be reproduced without the written consent of Zilog, Inc.

oo

93

READ REGISTER 0

Z·80 DART

Read aDd Writ.

Registers

94

READ REGISTER I'

LALLIENT

PARITY ERROR

Rx OVERRUN ERROR

FRAMING ERROR

NOT USED

·Used WII~ SpecIal ~ecel\le Condition Modtt

.

WRITE REGISTER 0

I~I~I~I~I~I~I~I~I T-C

1 o o

•

• o o o

I

• o

•

REGISTER 0

REGISTER.

REGl8TER2

REGISTER 3

REGISTER.

REGISTER 5 o

0 0 NULL CODE o

0 • NOT USED o

1 0 RESET EXT/STATUS INTERRUPTS o • •

CHANNEL RESET

•

•

•

•

0 0

0

•

•

•

0

•

ENABLE INT ON NEXT Ax CHARACTER

RESET TxlNT PENDING

ERROR RESET

RETURN FROIlINT ICH .... ONLy)

WRITE REGISTER 2 ICHAIfMEL B om

YI

I~I~I~I~I~I~!~I~I

~~

INTERRUPT

VECTOR

WRITE REGISTER 4

I~I~I~I~I~I~I~I~I

ITT

I L

PARITY ENABLE

. L

PARITY EVENIOliII o

0

•

NOT USED

•

STOP BITICHARACTER

•

•

0

1

• 'h STOP 81TSICHARACTER

2 BTOP BITSICHARACTER

NOTUIED o

0 X' CLOCK MODE o

1 XII CLOCK MODE

1 0 X32 CLOCK MODE

• 1 XN CLOCK MODE

READ REGISTER 2

INTERRUPT

VECTOR

• ·Varlable II "Slalus Affects

Veclor Is Programmed

WRITE REGISTER 1

I~I~I~I~I~I~I~I~I T

.

L

TxlNT ENABLE

BTATUS AFFECTS VECTOR

ICH.IONLy) o •

RxlNT DISABLE

Ax INT ON FIRST CHA...,cTER

}

OR ON

• OINT ON ALL Rx CHARACTERBIPARITY SPECIAL

AFFECTS VECTOR) RECEIYE

INT ON ALL Rx CHARACTER8IPARITY CONDITION

DOES NOT AFFECT VECTOR)

' - - - - - WAIT/READY ON R/T

1-.. _ _ _ _ _ WAIT/READY FUNCTION

' - - - - - - - - WAIT/READY ENAILE

WRITE REGISTER 3

I~I~I~I~I~I~I~I~I

T

I

I

L Ax ENABLE

L -

NOT USED IIIUST BE "-RAIIIIED.,

'-. - - - - - - AUTO ENABLES

Ra 5811'11CHARACTER

Ax 7 IITSICHARACTER

Rx' IITSICHARACTER

Ax' 81T11CftAMCTER

WRITE REGISTER &

I~I~I~I~I~I~I~I~J

TxENABLE

BENDIREAK o

0

•

Tx

Tx

5 BITI

7 fOR LESSIICHARACTER

BITSICHARACTER

1

1

0

•

Tx • BITSICHARACTER

Tx • eIT8ICHARACTER

' - - - - - - O T R

2044-004. 005

"Reproducad by parmisalon 81983 Zliog. Inc.

This materiel shall not be reproduced without the written consent of Z1tog. Inc."

Absolute

Maxlmum

Ratings

Test

Conditions

DC

Characteristics

Voltages on all inputs and outputs with respect to GND .......... -0.3 V to + 7.0 V

Operating Ambient As Specified in

Temperature ........... Ordering Information

Storage Temperature ........ -65°C to + lSOoC

The characteristics below apply for the following test conditions, unless otherwise noted. All voltages are referenced to GND

(0 V). Positive current flows into the referenced pin. Available operating temperature ranges are:

• S* = O°C to + 70°C,

+4.75 V S Vee S +5.25 V

• E* = -40°C to +85°C,

+4.75 V:s Vee

S

+5.25 V

• M* = -55°C to + 125°C,

+4.5 V S Vee s. +5.5 V

Symbol Parameter

VILe

V lHe

V IL

V

IH

VOL

V

OH

IL

IL(RIl

Icc

Clock Input Low Voltage

Clock Input High Voltage

Inp\lt Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input/3-State Output Leakage Current

HI Pin Leakage Current

Power Supply Current

TA

=

O°C to 70°C, Vee

=

+5V, ±S%

Stresses qreater than those listed under Absolute Maxi· mum Rallnqs may cause permanent damaqe to the device.

This Is a stress rallnq only; operation of the device at any condition above those Indicated In the operational sections of these specifications Is not Implied. Exposure to absolute maximum ratinq conditions for extended periods may affect device reliability.

'See Orderlnq Information section for package temperature range and product number.

Mba Max Uldt

-0.3 +0.45

Vee-0.6 +5.5

-0.3 +0.8

+2.0 +5.5

+0.4

+2.4

-10 + 10

-40 +10

100

V

V

V

V

V

V

,J.

,J. rnA

.IV

UK

Test CoDClltlOD

IoL =

2.0 rnA

IoH

= -25O,J.

0.4<V<2.4V

0.4<V<2.4V

I i

8085·0006

"Reproduced by permission 01983 Zilog, tnc.

This material shall not be reproduced without the written consent of Zilog. Inc."

95

AC

Electrical

Characteristics

CUI

C..eli,lIIi

._.ii iii» iit

-

-

..

DooD, iii

--®-

Number Symbol Parameter

%-80 DART Z-8OADART %-BOB DART*t

Min Max Min Max MID Max

1 TcC

2 TwCh

Clock Cycle Time

Clock Width (High)

400 4000

170 2000

250 4000

105 2000

165 4000

70 2000

3 TIC

8 TdC(OO)

Clock Fall Time

Clock t to Data Out Delay

30

4 TrC Clock Rise Time

240

30

115

30

60

15

5-TwCI---Clock Width ( L o w ) - - - - - - - - - - - - -170-2000--105-2000--70-2000-

6 TsAD(C)

CE. ciiS.

B/A to Clock t Setup Time 160 145 60

7 TsCS(C) IORO. RD to Clock t Setup Time

240

30

220

15

ISO

SO 30 9 TsDI(C) Data In to Clock t Setup Time (Write or Ml Cycle)

10-TdRD(OOz)-RD t to Data Out Float D e l a y - - - - - - - - - - - 230

11 TdIO(OOl)

12 TsMl(C)

IORO I to Data Out Delay (INTACK Cycle)

Mlto Clock t Setup Time

SO

210

340

13 TsIEI(IO) lEI to IORO I Setup Time (INTACK Cycle)

14 TdMl(IEO) MIl to lEO I Delay (interrupt belore Ml)

200

300

15-TdIEI(IEOr)-IEI t to lEO t Delay (after ED d e c o d e ) ' - - - - - - - - ISO

16 TdIEI(IEOf) lEI I to lEO I Delay ISO

17 TdC(INT) Clock t to INT I Delay

18 TdIO(W/RWf) IOROI or CE I to W/RDY I Delay (Wait Mode)

200

19

20

TdC(W/RR) Clock t to

TdC(W/RWz) Clock I to

W/RDY

W/RDY

I Delay (Ready Mode)

Float Delay (Wait Mode)

300

120

ISO

90

140

110

160

190

100

100

200

210

120

130

75

120

90-

100

160

70-

70

ISO

.l75

100

110

• All timings are prelimir..ary and subject to chi:mge. tUnlls 10 ns.

96

"Reproduced by permission 01983 Zilog. Inc.

This material shall not ba reproduced ,,\,ithout the written consent of Z1log. Inc."

AC

Electrical

Characteristics

(Continued) eft, iiCIi, ~

TiC

T.D

W/IIDT fliT iiC

II.D

W/IIDY fliT

'"

<D

~

JI'" ,

M

"

Number Symbol Parameter

I TwPh Pulse Width (High)

2 TwPI

3 TcTxC

4 TwTxCI

Pulse Width (Low)

TxC Cycle Time

TxC Width (Low)

5-TwTxCh--TxC Width (High)

6 TdTxC(TxD) TxC I to TxD Delay

7 TdTxC(W/RRf) TxC I to W/RDY I DeidY (Ready Mode)

8 TdTxC(INT) TxC I to INT I Delay

9 TcRxC RxC Cycle Time

IO-TwRxCI---RxC Width (Low}

11 TwRxCh RxC Width (High)

12 TsRxD(RxC) RxD to RxC 1 Setup Time (xl Mode)

13 ThRxD(RxC) RxD Hold Time (xl Mode)

14 TdRxC(W/RRf) RxC r

Mode) to W/RDY I Delay (Ready

15 TdRxC(lNT) RxC r to INT I Delay

NOTES:

1 In i'tH modt"s, the System Clock. ratt! must be dt IE'dst five times thp mitXtmum ddta rate. RESET musl be dchvf:' d m.mmum 01 one comp!vI~~ clock cycle.

Z-SODART Z-BOA DART Z-SOB DARTI

Min Max Min Max Min Max Not.at

200

200

400 00

180 00

200

200

400 00

180 00

200

200

330 00

100 00

2

2

2

2

180-00--180-00--100 - 0 0 - - - 2 -

5

400

9 5

300

9 5

220

9

2

3

5

400 00

9 5 tOO 00

9

180-00--180-00

180 00 180 00

0

140

10 13

0

140

10 13

5

330 00

9

0

100

3

2 lQQ 0 0 - - - 2 -

100 00 2

2

2

10 13 3

10 13 10 13 10 13 3

1. Timings are preliminary and subject to change.

2. Units

In nanoseconds (ns).

3. Umts <,qual 10 System Clock Periods.

&

2044·013 97

"Reproduced by permIssion "1983 Zilog, Inc.

This material shall not be reproduced without the written consent of Zilog, Inc."

Z8470

Z8470

Z8470

Z8470

28470

Z8470

Z8470

Z8410

Z8470A

Product Package/

Number Temp

Z8470A

Z8470A

Speed Deac:rlptloD

Product Package/

Number Temp Speed

CE 2.5 MHz ZSO DART (40-pin) 28470A

CM 2.5 MHz Same as above

CMB 2.5 MHz Same as above

28470A

28470A

CS 2.5 MHz Same as above

DE. 2.5 MHz Same as above

OS

PE

2.5 MHz Same as above

2.5 MHz Same as above

Z8470A

28410A

28410B

PS

CE

2.5 MHz Same as above

4.0 MHz ZSOA DART

(40-pin)

Z8410B

Z8410B

Z8470B

CM 4.0 MHz Same as above

CMB 4.0 MHz Same as above

Deac:rlptloa

CS 4.0 MHz ZSOA DART

(4O-pin)

DE

DS

PE

4.0 MHz

4.0 MHz Same as above

4.0 MHz

Same as above

Same as above

PS 4.0 MHz Same as above

CE 6.0 MHz ZSOB DART

(40-pin)

CS 6.0 MHz Same as above

OS 6.0 MHz Same as above

PS 6.0 MHz Same as above

'NOTES: C

=

C"'-'''nI,', D

=

Cerdil', P = Plasli,': E = -40·C 10 + 85·C. M = ~55°C 10 + 125·C. MB = _55°C to + 125°C with

MIL·~ll)!J!lJ Clds. B pWL'e •• 1llY. S = O·C toO + 70"C.

98

"Reproduced by permission 01983 Z1Jog, Inc.

This matorial aha)) not be reproduced without the writton consent of Z1log. Inc."

WESTERN DIGITAL

c o

R P 0 R A T I o N

WD177011772

5~"

Floppy Disk ControlieriFonnatter

FEATURES

• 28 PIN DIP

• SINGLE 5V SUPPLY

• BUILT·IN DATA SEPARATOR

• BUILT·IN WRITE PRECOMPENSATION

• 51/4- SINGLE AND DOUBLE DENSITY

• MOTOR CONTROL

• 128, 256, 512 OR 1024 SECTOR LENGTHS

• TIL COMPATIBLE

• 8 BIT BIDIRECTIONAL DATA BUS

• TWO VERSIONS AVAILABLE

WD1nO = STANDARD 179X STEP RATES

WD1n2

=

FASTER STEP RATES

CS

RNl

AO

A1

DALO

DAL1

DAL2

DAL3

DAl4

DALS

DALS

DAL7

MR

GND

PIN DESIGNATION

INTRa

DRa

DDEN

WPRT iP

TROO

WD

WG

MO iii

CLK

DiRe

STEP vee

DESCRIPTION

The WD1nO is a MOSILSI device which performs the functions of a 51/4" Floppy Disk Controller/Fonnatter.

It is similar to its predecessor, the WDl79X, but also contains a digital data separator and write precom· pensation circuitry. The drive side of the interface needs no additional logic except for buffers! receivers. Designed for 51/4· single or double density operation, the device contains a programmable

Motor On signal.

The WD1nO is implemented in NMOS silicon gate technology and is available in a 28 pin dual·in-line.

The WD1nO is a low cost version of the FDl79X

Floppy Disk Controller/Formatter. It is compatible with the 179X, but has a bullt·in digital data separator and write precompensation circuits. A single read line (RD, Pin 19) is the only input required to recover serial FM or MFM data from the disk drive. The device has been specifically designed for control of

51/4· floppy disk drives with data rates of 125

KBits/Sec (single density) and 250 KBits/Sec (double density). In addition, write precompensation of 125

Nsec from nominal can be enabled at any point through simple software commands. Another programmable feature, Motor On, has been incorporated to enable the spindle motor automatically prior to operating a selected drive.

Two versions of the WD1nO are available. The standard version is compatible with the 179X stepping rates, while the WD1n2 offers stepping rates of 2, 3,

5and6msec.

The processor interface consists of an B-bit bidirectional bus for transfer of status, data, and commands.

All host communication with the drive occurs through these data lines. They are capable of driving one standard TTL load or three "LS" loads.

June, 1983

Reproduced with permiSSion from

Weslern Digital Corporallon

PIN

NUMBER

1

PIN NAME

CHIP SELECT

2 READlWRITE

3,4

5-12

17

18

19

20

21

22

23

13

14

15

16

24

25

26

ADDRESS 0,1

DATA ACCESS LINES o

THROUGH 7

DALO-DAl7

MASTER RESET

GROUND

POWER SUPPLY

STEP

GND

VCC

STEP

DIRECTION

CLOCK

READ DATA

MOTOR ON

WRITE GATE

WRITE DATA

TRACK 00

INDEX PULSE

WRITE PROTECT

DOUBLE DENSITY

ENABLE

SYMBOL

AO,A1

DIRC

ClK

RD

MO

WG

WD

TROO

FUNcnON

A logic low on this input selects the chip and enable Host communication with the device.

A logic high on this l!!Q.ut controls the placement of data on the [)().C7 lines from a selected register, while a logic low causes a write operation to a selected register.

These two inputs select a register to ReadlWrite data:

CS o o o o

A1 o o

1

1

AO o

Status Reg

1 Track Reg o

Sector Reg

1 DataReg

RIW

=

0

Command Reg

Track Reg

Sector Reg

Data Reg

Eight bit bidirectional bus used for transfer of data, control, or status. This bus is enabled by

CS and RIW. Each line will drive one TTL load.

A logic low pulse on this line resets the device and initializes the status register (intemal pull·up).

Ground.

+ 5V ± 5% power supply input.

The Step output contains a pulse for each step of the drive's RIW head. The

WD1772 offer different step rates.

WD1nO and

The Direction output is high when stepping in towards the center of the diskette, and low when stepping out.

This input requires a free-running 50% duty cycle clock (for internal timing) at 8 MHZ ± 1 %.

This active low input is the raw data line containing both clock and data pulses from the drive.

Active high output used to enable the spindle motor prior to read, write or stepping operations.

This output is made valid prior to writing on the diskette.

FM or MFM clock and data pulses are placed on this line to be written on the diskette.

This active low input informs the WD1nO that the drive's

RiW heads are positioned over Track zero (internal pull-up).

This active low input informs the WD1nO when the physical index hole has been encountered on the diskette (intemal pull-up).

This input is sampled whenever a Write

Command is received. A logic low on this line will prevent any Write Command from executing (intemal pull-up).

This input pin selects either single (FM) or double (MFM) density. When DDEN

=

0, double density is selected (intemal pull-up).

2

RePfOducedwith permission from

Weatern Digital Corporation

PIN

NUMBER

27

28

PIN NAME

DATA REQUEST

SYMBOL

DRQ

INTERRUPT REQUEST INTRQ

FUNCTION

This active high output indicates that the Data

Register is full (on a Read) or empty (on a Write operation).

This active high output is set at the completion of any command or reset a read of the Status

Register.

H

0

S

T

R

F

A

C

E

I

N

T

E

ClK

IA rr

00·07

AO "

...

At

CS

RiW

Km

WD1770

WG

WO

RO

115" i'ROO

WP'R'f

MO

OIRC ORa

INTRa

+5

.I

GNOVCC --r

L+ 5V

. : ODEN

=

STEP

51/4 "

F l

0

P p y

0

R

I

V

E

WD1no SYSTEM BLOCK DIAGRAM

ARCHITECTURE

The Floppy Disk Formatter block diagram is illustrated on page 4. The primary sections include the parallel processor interface and the Floppy Disk interface.

Data ShiH Register This 8-bit regjger assembles serial data from the Read Data input (RD) during Read operations and transfers serial data to the Write Data output during Write operations.

Data Register This 8-bit register is used as a holding register during Disk Read and Write operations. In Disk Read operations, the assembled data byte is transferred in parallel to the Data Register from the Data Shift Register. In Disk Write operations, information is transferred in parallel from the Data

Register to the Data Shift Register.

When executing the Seek command, the Data Register holds the address of the desired Track position.

This register is loaded from the DAL and gated onto the DAL under processor control.

Track Register This 8-blt register holds the track number of the current ReadlWrite head position. It is

Incremented by one every time the head Is stepped In and decremented by one when the head is stepped out (towards track 00). The contents of the register are compared with the recorded track number in the

10 field during disk Read, Write, and Verity operations. The Track Register can be loaded from or transferred to the DAL This Register should not be loaded when the device is busy.

Sector Register (SR) This 8-bit register holds the address of the desired sector position. The contents of the register are compared with the recorded sector number in the 10 field during disk Read or Write operations. The Sector Register contents can be loaded from or transferred to the DAL This register should not be loaded when the device is busy.

Command Register (CR) This 8-bit register holds the command presently being executed. This register should not be loaded when the device is busy unless the new command is a force interrupt. The command register can be loaded from the DAL, but not read ontotheDAL

Status Register (STR) This 8-blt register holds device Status information. The meaning of the Status bits is a function of the type of command previously executed. This register can be read onto the DAL, but not loaded from the DAL

CRC Logic This logic is used to check or to generate the 1&bit CycliC Redundancy Check (CRC).

The polynomial is:

G(x) = x16 + x12 + x5 + 1.

The CRC includes all information starting with the address mark and up to the CRC characters. The

CRC register is preset to ones prior to data being

Shifted through the circuit.

Arithmetic/Logic Unit (ALU) The ALU is a serial comparator, incrementer, and decrementer and is used for register modification and comparisons with the disk recorded 10 field.

3

Reproduced witt> permission from

Western Digital Corporation

(DAl)

ORO

INTRa

1m

~

RIW

AO

A1

CLK(8MHZ)

~

COMPUTER

INTERFACE

CONTROL

CONTROL

~

PLA

CONTROL

(240 X 19)

..

CONTROL

..

DISK

INTERFACE

CONTROL

WG

WPRT

1\5"

TJ!IOO

STEP

DIRC

MOTOR ON

WD1770 BLOCK DIAGRAM

TIming and Control All computer and Floppy Disk interface controls are generated through this logic.

The intemal device. timing is generated from an external crystal clock. The FD1770 has two different

When ODEN

When DDEN

=

0, double density (MFM) is enabled.

=

1, single density is enabled.

AM Detector The address mark detector detects

10, data and index address marks during read and write operations.

Data Separator A digital data separator consisting of a ring shift register and data window detection logic provides read data and a recovery clock to the

AM detector.

PROCESSOR INTERFACE

The Interface to the processor is accomplished through the eight Data Access Lines (DAL) and associated control signals. The DAL are used to transfer Data, Status, and Control words out of, or Into the WD1770. The DAL are three state buffers that are enabled as output drivers when Chip Select (CS) and AIW

=

1 are active or act as Input recElivers when

CS and AIW

=

0 are active.

When transfer of data with the Floppy Disk Controller is required by the host processor, the device address is decoded and CS is made low. The address bits A 1 and AO, combined with the signal AIW during a Read operation or Write operation are interpreted as selecting the following registers: .

4

Reproduced wi1h permission from

Western Digi1al Corporation

A1 AD READ (RIW

=

0 0 Status Register

0 1

1 0

1 1

WRITE (RIW

=

Command Register

Track Register Track Register

Sector Register Sector Register

Data Register Data Register

During Direct Memory Access (DMA) types of data transfers between the Data Register of the WD1no and the processor, the Data Request (ORO) output is used in Data Transfer control. This signal also appears as status bit 1 during Read and Write operations.

On Disk Read operations the Data Request is activated (set high) when an assembled serial Input byte is transferred In parallel to the Data Register. This bit is cleared when the Data Register is read by the processor. If the Data Register Is read after one or more characters are lost, by having new data transferred into the register prior to processor readout, the lost

Data bit is set in the Status Register. The Read operations continues until the end of sector Is reached.

On Disk Write operations the Data Request is activated when the Data Register transfers Its contents to the Data Shift Register, and requires a new data byte. It is reset when the Data Register is loaded with new data by the processor. If new data is not loaded at the time the next serial byte is required by the

Floppy Disk, a byte of zeroes is written on the diskette and the lost Data is set in the Status

Register.

At the completion of every command an INTRa is generated. INTRa is reset by either reading the status register or by loading the command register with a new command. In addition,lNTRa is generated if a Force Interrupt command condition is met.

The WD1no has two modes of operation according to the state DDEN (Pin 26). When DDEN

=

1, Single density is selected. In either case, the ClK input (Pin

18) Is at 8 MHZ.

GENERAL DISK READ OPERA nONS

Sector lengths of 128, 256, 512 or 1024 are obtainable

In either FM or MFM formats. For FM, DDEN should be placed to logical "1:' For MFM formats,

Dt>EN should be placed to a logical "0:' Sector lengths are determined at format time by the fourth byte in the

"ID"field.

SECTOR LENGTH TABLE

SECTOR

L~::TH

FIELD(H

NUMBER OF BYTES

IN SECTOR (DECIMAL)

00

01

02

03

128

256

512

1024 number of tracks as far as the WD1770 Is concemed is from 0 to 255 tracks.

GENERAL DISK WRITE OPERA nON

When writing is to take place on the diskette the

Write Gate (WG) output is activated, allOWing current to flow into the ReadlWrite head. As a precaution to erroneous writing the first data byte must be loaded into the Data Register in response to a Data Request from the device before the Write Gate signal can be activated.

Writing is inhibited when the Write Protect Input Is a logic low, In which case any Write command is Immediately terminated, an Interrupt is generated and the Write Protect status bit is set.

For Write operations, the WD1no provides Write

Gate (Pin 21) to enable a Write condition, and Write

Data (Pin 22) which consists of a series of active high pulses. These pulses contain both Clock and Data information in FM and MFM. Write Data provides the unique missing clock pattems for recording Address

Marks.

The Precomp Enable bit in Write commands allow automatic Write precompensatlon to take place. The outgoing Write Data stream Is delayed or advanced from nominal by 125 nanoseconds according to the following table:

PATTERN

X 1 1 0

X 0 1 1

0 0 0 1

1 0 0 0

I

MFM

Eariy

Late

Early

Late

FM

N/A

N/A

NlA

N/A

I L

Next Bit to be sent

Current Bit sending n t

Precompensation Is typically enabled on the Innermost tracks where bit shifts usually occur and bit

. density is at its maximun.

COMMAND DESCRIPTION

The WD1770 will accept eleven commands. Command words should only be loaded In the Command

Register when the Busy status bit is off (Status bit 0).

The one exception is the Force Interrupt command.

Whenever a command is being executed, the Busy status bit is set. When a command is completed, an

Interrupt is generated and the Busy status bit is reset. The Status Register indicates whether the completed command encountered an error or was fault free. For ease of discussion, commands divided into four types. Commands and types are are summarized in Table 1.

The number of sectors per tract as far as the WD1770 is concerned can be from 1 to 255 sectors. The

5

Reproduced with permillSion from

Western Digital Corporation

COMMAND SUMMARY

TYPE COMMAND

I Restore

I Seek

I Step

I Step-in

I Step-out

II Read Sector

II Write Sector

III Read

Address

III Read Track

III Write Track

IV Force

Interrupt

BITS

7 6 5 4 3 2 1

0 0 0 0 h V r1

0 0 0 1

0 0 1 u

0 1 0 u

0 1 1 u

1 0 0 m

1 0 1 m h V r1 h V r1 h V r1 h V r1 h E 0 h E P

0 ro ro ro ro ro

0 ao

1 1 0 0

1 1 1 0

1 1 1 1 h E 0 h E 0 h E P

0

0

0

1 1 0 1 13 12 11 10

.FLAG SUMMARY

TYPE I COMMANDS h h h

=

Molor On Flag (Bil3)

=

0, Enable Spin-Up Sequence

= 1, Disable Spin-Up Sequence

V

=

Verify Flag (BII2)

v

= 0, No Verify

V

=

1, Verify on Destination Track r1, ro

= Stepping Rale (Blls 1, 0) r1,

0 0

0 1

1 0

1 1 ro WD1nO

6ms

12ms

20ms

30ms u u u

=

Update Flag (BI14)

=

0, No Update

=

1, Update Track Register

WD1n2

2ms

3ms

5ms

6ms

TYPE II & III COMMANDS m m m

=

Mulliple Seclor Flag (Bil4)

=

0, Single Sector

1, Multiple Sector eo ao ao

=

Data Address Mark (BII 0)

=

0, Write Normal Data Mark

=

1, Write Deleted Data Mark

E

E

E

=

30ms SeHling Delay (BII2)

=

0, No Delay

=

1, Add 30ms Delay

P

P

P

=

Write Precompensalion (BI11)

=

0, Enable Write Precomp

=

1, Disable Write Precomp

TYPE IV COMMAND$

13-10 Intenupt Condition (Bits 3.())

10

11

12

=

1, Don't Care

=

1, Don't Care

=

1,Interrupt on Index Pulse

13 = 1, Immediate Interrupt

13-10

=

0, Terminate without Interrupt

TYPE I COMMANDS

The Type I Commands include the Restore, Seek,

Step, Step-In, and Step-Out commands. Each of the

Type I Commands contains a rate field (ro,r1), which determines the stepping motor rate.

A 4,.Is (MFM) or 8 lAS (FM) pulse is provided as an output to the drive. For every step pulse issued, the drive moves one track location in a direction determined by the direction output. The chip will step the drive in the same direction it last stepped unless the cornmand changes the direction.

The Direction signal is active high when stepping in and low when stepping out. The Direction signal is valid 24,.1s before the first stepping pulse is generated.

After the last directional step an additional 30 milliseconds of head settling time takes place If the

Verify flag is set in Type I commands. There is also a

30 ms head settling time If the E flag is set in any

Type II or III command.

When a Seek, Step or Restore command is executed, an optional verification of ReadlWrite can be performed by setting bit 2 rI

= head position

1) in the cornmand word to a logic 1. The verification operation begins at the end of the 30 millisecond settling time after the head is loaded against the media The track number from the first encountered 10 Field is cornpared against the contents of the Track Register. If the track numbers compare and the 10 Field Cyclic

Redundancy Check (CRC) is correct, the verify operation is complete and an INTRQ is generated with no errors. If there Is a match but not a valid CRC, the

CRC error status bit is set (Status Bit 3), and the next encountered 10 field is read from the disk for the verification operation.

The WD1nO must find an 10 field with correct track number and correct CRC within 5 revolutions of the media, otherwise the seek error is set and an INTRa is generated. If V

=

0, no verification is performed.

All commands, except the Force Interrupt command, may be programmed via the h Flag to delay for spindle motor start up time. If the h Flag is set and the

Motor On line (Pin 20) is low when a command is received, the WD1nO will force Motor On to a logic 1 and wait 6 revolutions before executing the c0mmand. At 300 RPM, this guarantees a one second spindle start up time. If after finishing the command, the device remains idle for 10 revolutions, the Motor

6

Reproduced with permission from

Western Olgl181 Corporation

On line will go back to a logic O. If a command is issued while Motor On is high, the command will execute immediately, defeating the 6 revolution start up. This feature allows consecutive Read or Write commands without waiting for motor start up pach time; the WD1nO assumes the spindle motor is up to speed.

RESTORE (SEEK TRACK 0)

Upon receipt of this command, the Track 00 (fROO) input is sampled: If fFiOO is active low Indicating the

ReadlWrite head is positioned over track 0, the Track

Register ,s loaded with zeroes and an interrupt Is generated. If TROO is not active low, stepping pulses

(Pin 16) at a rate specified by the r1,ra field are issued until the TROO input is activated.

~----------------~

NO

TYPE I COMMAND FLOW

7

Reproduced with permission from

Western Digital Corporation

TYPE I COMMAND FLOW

SET DIRECTION

-1 TOTR

OTOTR

At this time, the Track Register is loaded with zeroes and an interrupt is generated. If the

'i'ROO input does not go active low after 255 stepping pulses, the

W01770· terminates operation, interrupts, and sets the Seek error status bit, providing the V flag is set. A verification operation also takes place if the V flag is set. The h bit allows the Motor On option at the start of command.

SEEK

This command assumes that the Track Register contains the track number of the current position of the

ReadlWrite head and the Data Register contains the desired track number. The W01770 will update the

Track Register and issue stepping pulses in the appropriate direction until the contents of the Track

Register are equal to the contents of the Data

Register (the desired track location). A verification

VERIFY

SEQUENCE

SET

CRC

ERROR

INTRQ

RESET BUSY operation takes place if the V flag is on.· The h bit allows the Motor On option at the start of the command. An interrupt is generated at the cOmpletion of the command. Note: When using multiple drives, the track register must be updated for the drive selected before seeks are issued.

STEP

Upon receipt of this command, the W01770 issues one stepping pulse to the disk drive. The stepping motor direction is the same as in the previous step command. After a delay determined by the r1 ,It) field, a verification takes place if the V flag is on. If the U flag is on, the Track Register is updated. The h bit allows the Motor On option at the start of the command. An interrupt is generated at the completion of the command.

STEP·IN

Upon receipt of this command, the W01770 issues one stepping pulse in the direction towards track 76.

If the U flag is on, the Track Register is incremented by one. After a delay determined by the r1,1t) fieid, a verification takes place if the V flag is on. The h bit allows the Motor On option at the start of the command. An interrupt is generated at the compietion of the command.

STEP·OUT

Upon receipt of this command, the WD1770 issues one stepping pulse in the direction towards track O. If the U flag is on, the Track Register is decremented by one. After deiay determined by the rvo field, a verification takes place if the V flag is on. The h bit allows the Motor On option at the start of the command. An interrupt is generated at the completion of the command.

TYPE II COMMANDS

The Type II Commands are the Read Sector and Write

Sector commands. Prior to loading the Type II Command into the Command Register, the computer must load the Sector Register with the desired sector number. Upon receipt of the Type II command, the busy status bit is set. If the E flag

=

1 the command will execute after a 30 msec deiay.

When an 10 field is located on the disk, the W01770 compares the Track Number on the 10 field with the

Track Register. If there is not a match, the next encountered 10 field is read and a comparison is again made. If there was a match, the Sector Number of the

10 field is compared with the Sector Register. If there is not a Sector match, the next encountered 10 field is read off the disk and comparisons again made. If the 10 field CRe is correct, the data field is then located and will be either written into, or read from depending upon the command. The W01770 must find an 10 field with a Track number, Sector number, and CRC within four revolutions of the disk, other·

TYPE I COMMAND FLOW

8

Reproduced with permission from

Western Digital Corporation

4

SETMO

WAIT

6 INDEX PULSES the Sector register Intemally updated so that an address verification can occur on the next record. The

WD1770 will continue to read or write multiple records and update the sector register In numerical ascending sequence until the sector register exceeds the number of sectors on the track or until the

Force Interrupt command Is loaded Into the C0mmand Register, which terminates the command and generates an interrupt.

For example: If the WD1770 is instructed to read sector 27 and there are only 26 on the track, the sector register exceeds the number available. The WD1770 will search for 5 disk revolutions, interrupt out, reset busy, and set the record not found status bit.

READ SECTOR

Upon receipt of the Read Sector command, the Busy status bit is set, and when a 10 field is encountered that has the correct track number; correct sector number, and correct CRC, the data field is presented to the computer. The Data Address Mark of the data field must be found within 30 bytes in single density and 43 bytes in double density of the last 10 field

CRe byte; if not, the 10 field is searched for and verified again followed by the Data Address Mark search. If after 5 revolutions the DAM cannot be found, the Record Not Found status bit is set and the operation is terminated. When the first character or byte of the data field has been shifted through the

DSR, it is transferred to the DR, and DRQ is generated. When the next byte is accumulated in the

DSR, it is transferred to the DR and another DRQ is generated. If the computer has not read the previous contents of the DR before a new character is transferred that character is lost and the Lost Data Status bit is set. This sequence continues until the cornplete data field has been inputted to the computer. If there is a CRC error at the end of the data field, the

CRC error status bit is set, and the command is terminated (even if it is a multiple record command).

At the end of the Read operation, the type of Data Address Mark encountered in the data field is recorded in the Status Register (Bit 5) as shown:

INTRa. RESET BUSY

SET WRITE PROTECT

STATUS BIT 5

1 o

Deleted Data Mark

Data Mark

TYPE II COMMAND wise, the Record not found status bit is set (Status

Bit 4) and the command is terminated with an interrupt (INTRQ).

Each of the Type II Commands contains an (m) flag which determines if multiple records (sectors) are to be read or written, depending upon the command. If m

=

0, a single sector is read or written and an interrupt Is generated at the completion of the command.

If m

=

1, multiple records are read or written with

WRITE SECTOR

Upon receipt of the Write Sector command, the Busy status bit is set. When an 10 field is encountered that has the correct track number, correct sector number, and correct CRC, a ORQ is generated. The WD1nO counts off 11 bytes in single density and 22 bytes in double density from the CRe field and the WrIte Gate

(WG) output is made active if the DRQ is serviced

(i.e., the DR has been loaded by the computer). If DRQ has not been serviced, the command is terminated

9

Reproduced with permission from

Western Digitel Corporation

NO

NO

NO

SETCRC

STATUS ERROR

BRING IN SECTOR LENGTH FIELD

STORE LENGTH IN INTERNAL

REGISTER

INTRQ. RESET BUSY

SET RECORO-NOT FOUND

TYPE II COMMAND and the Lost Data status bit is set. If the ORO has been serviced, the WG is made active and six bytes of zeroes in single density and 12 bytes In double density are then written on the disk. At this time, the

Data Address Mark Is. then written on the disk determined by the as

ao

field of the command as shown below: so

DATA ADDRESS MARK (BIT 0)

1 Deleted Data Mark o

Data Mark

The WD1770 then writes the data field and generates

ORa's to the computer. If the ORO Is not serviced in time for continuous writing the Lost Data Status Bit

10

Reproduced with permllSlon from

Western Digital Corporation

READ SECTOR

SEQUENCE

NO

SET DATA

LOST

NO

INTRQ. RESET BUSY

SET CRC ERROR

TYPE II COMMAND

11

Reproduced with permission from

Western DigItal Corporation

INTRQ RESET BUSY

SEQUENCE

NO

TYPE II COMMAND

12

Reproduced with penni_ion from

Western Olgltel Corporation

SET DATA LOST

WRITE BYTE

OF ZEROES

is set and a byte of zeroes is written on the disk. The command is not terminated. After the last data byte has been written on the disk, the tw(>byte CRC is computed internally and written on the disk followed by one byte of logic ones in FM or in MFM. The WG output is then deactivated. INTRa will set 24,Jsec

(MFM) after the last CAe byte is written. For partial sector writing, the proper method is to write data and fill the balance with zeroes.

TYPE III COMMANDS

Read Address

Upon receipt of the Read Address command, the

Busy Status Bit is set. The next encountered 10 field is then read in from the disk, and six data bytes of the

10 field are assembled and transferred to the DR, and a ORa is generated for each byte. The six bytes of the

10 field are shown below:

TRACK SIDE SECTOR SECTOR CRC CRC

ADDR NUMBER ADDRESS LENGTH 1 2

1 2 3 4 5 6

Although the CRC characters are transferred to the computer; the WD1770 checks for validity and the

CRC error status bit is set if there is a CRC error. The

Track Address of the 10 field is written into the sector register so that a comparison can be made by the user. At the end of the operation an interrupt is generated and the Busy Status is reset.

Read Track

Upon receipt of the READ track command, the head is loaded and the Busy Status bit is set. Reading starts with the leading edge of the first encountered index pulse and continues until the next index pulse.

All Gap, Header; and data bytes are assembled and transferred to the data register and ORO's are generated for each byte. The accumulation of bytes is synchronized to each address mark encountered.

An interrupt is generated at the completion of the command.

This command has several characteristics which make it suitable for diagnostic purposes. They are: no

CRC checking is performed; gap information is included in the data stream; and the address mark detector is on for the duration of the command.

Because the AM detector is always on, write splices or noise may cause the chip to look for an AM.

The 10 AM, 10 field, 10 CRC bytes, DAM, Data, and

Data CRC Bytes for each sector will be correct. The

Gap Bytes may be read incorrectly during write-splice time because of synchronization.

WRITE TRACK FORMAmNG THE DISK

(Refer to section on Type diagrams.)

III commands for flow

Formatting the disk is a relatively simple task when operating programmed I/O or when operating under

DMA with a large amount of memory. Data and gap information must be provided at the computer inter· face. Formatting the disk is accomplished by positioning the AIW head over the desired track number and issuing the Write Track command.

Upon reGeipt of the Write Track command, the Busy

Status bit is set. Writing starts with the leading edge of the first encountered index pulse and continues until the next index pulse, at which time the interrupt is activated. The Data Request is activated immediately upon receiving the command, but writing will not start until after the first byte h8$ been loaded into the Data Register. If the DR has not been loaded within 3 byte times, the opP.ration is terminated making the device Not Busy, the lost Data Status Bit is set, and the interrupt is activated. If a byte is not present in the DR when needed, a byte of zeroes is substituted.

This sequence continues from one index mark to the next index mark. Normally, whatever data pattem appears in the data register is written on the disk with a normal clock pattern. However; if the WD1

no

detects a data pattem of F5 through FE in the data register; this is interpreted as data address marks with missing clocks or CRC generation.

DATA PATTERN

IN DR (HEX)

OOthru F4

F5

F6

IN FM (DDEN = 1)

Write 00 thru F4 with ClK

=

FF

Not Allowed

Not Allowed

IN MFM (DDEN = 0)

Write 00 thru F4, in M FM

WriteA1" in MFM, PresentCRC

Write C2"" in MFM

F7

F8thru FB

Fe

FD

FE

FF

..

Generate 2 CRC bytes

Write F8 thru FB, ClK

Generate 2 CRC bytes

=

C7, Preset CAe Write F8 thru FB, in MFM

Write FC with ClK

=

07

Write FD with ClK

=

FF

Write FE, ClK

=

C7, Preset CRC

Write FF with ClK

=

"MISSing clock transition between bits 4 and 5.

FF

Write FC in MFM

Write FD in MFM

Write FE in MFM

Write FF in MFM

·"Missing clock transition between bits 3 and 4.

13

Reproduced with permission from

Western Digital Corporation

NO

SET MO

DELAY 6

INDEX PULSES

YES

SET INTRQ

LOST DATil

RESET BUSY

TYPE III COMMAND WRITE TRACK

14

Reproduced with pP.rmission from

Western Digital Corporation

WRITE 2 CRC

CHARS. ClK

=

FF

WRITE FC

ClK

=

07

WRITE FD, FE OR

F8-F9, ClK

=

C7

INITIALIZE CRC

TYPE III COMMAND WRITE TRACK

15

Reproduced will, permission from

Western Oigital Corporation

WRITE

BYTE OF ZEROES

SET DATA lOST

WRITE Al IN MFM

WITH MISSING

CLOCK INITIALIZE

CRC

WRITE C2 IN MFM

WITH MISSING

CLOCK

WRITE 2 CRC

CHARS.

The CRC generator is initialized when any data byte from F8 to FE is about to be transferred from the DR to the DSR in FM or by receipt of F5 in MFM. An F7 pattern will generate two CRC characters in FM or

MFM. As a consequence, the patterns F5 through FE must not appear in the gaps, data fields, or 10 fields.

Also, CRC's must be generated by an F7 pattern.

Disks may be formatted in IBM 3740 or System 34 formats with sector lengths of 128, 256, 512, or 1024 bytes.

TYPE IV COMMANDS

The Forced Interrupt command is generally used to terminate a multiple sector read or write command or to insure Type I status in the status register. This command can be loaded into the command register at any time. If there is a current command under execution (busy status bit set) the command will be terminated and the busy status bit reset.

The lower four bits of the command determine the conditional interrupt as follows:

10 = Don't Care

11 = Don't Care

12

13

= Every Index Pulse

= Immediate Interrupt

The conditional interrupt is enabled when the corresponding bit positions of the command (13-10) are set to a 1. Then, when the condition for interrupt is met, the INTRO line will go high signifying that the condition specified has occurred. If 13-10 are all set to zero (HEX DO), no interrupt will occur but any command presently under execution will be immediately terminated. When using the immediate interrupt condition (13 = 1) an interrupt will be immediately generated and the current command terminated.

Reading the status or writing to the command

.register will not automatically clear the interrupt. The

HEX DO is the only command that will enable the immediate interrupt (HEX 08) to clear on a subsequent load command register or read status register operation. Follow a HEX 08 with DO command.

Wait 16 micro sec (double density) or 32 micro sec

(single density) before issuing a new command after issuing a forced interrupt. Loading a new command sooner than this will nullify the forced interrupt.

Forced interrupt stops any command at the end of an internal micro-instruction and generates INTRO when the specified condition is met. Forced interrupt will wait until ALU operations in progress are complete (CRC calculations, compares, etc.).

Status Register

Upon receipt of any command, except the Force Interrupt command, the Busy Status bit is set and the rest of the status bits are updated or cleared for the new command. If the Force Interrupt Command is received when there is a current command under execution, the Busy status bit is reset. and the rest of the status bits are unchanged. If the Force Interrupt command is received when there is not a current command under execution, the Busy Status bit is reset and the rest of the status bits are updated or cleared. In this case, Status reflects the Type I commands.

The user has the option of reading the status register through program control or using the ORO line with

DMA or interrupt methods. When the Data register is read the ORO bit in the status register and the ORO line are automatically reset. A write to the Data register also causes both ORO's to reset.

The busy bit in the status may be monitored with a user program to determine when a command is complete, in lieu of using the INTRO line. When using the

INTRO, a busy status check is not recommended because a read of the status register to determine the condition of busy will reset the INTRO line.

The format of the Status Register is shown below:

(BITS)

87

I

86

I

S5

I

S4

I

S3

I

S2

I

S1

I

SO

RECOMMENDED 128 BYTES/SECTOR

Shown below is the recommended single-density format with 128 bytes/sector. In order to format a diskette, the user must issue the Write Track command, and load the data register with the following values.

For every byte to be written, there is one Data

Request.

NUMBER

OF BYTES HEX VALUE OF BYTE WRITTEN

6

1

1

1

1

1

1

11

00

FE (10 Address Mark)

Track Number

Side Number

F7

(Sector Length)

(2 CRC's written)

FF(orOO)

(00 orOi)

Sector Number(1 thru 1A)

00

6

1

00

FB (Data Address Mark)

128

1

Data (IBM uses E5)

F7 (2 CRC's written)

10 FF(orOO)

L..--:;3""'6*'9· • FF (or 00)

'Write bracketed field 16 times.

"Continue writing until WD1770 interrupts out.

Approx. 369 bytes.

256 BYTES/SECTOR

Shown below is the recommended dual-density format with 256 bytes/sector. In order to format a diskette the user must issue the Write Track command and load the data register with the following values. For every byte to be written, there is one data request.

16

Reproduced with permission from

Western Digital Corporation

n

REPEATED

'-_ _ _ _ _ _ _ _ _ _ ..

FOR EACH SECTOR l

40 BYTES 6 BYTES

'FF' '00'

10

'FE'

TRACK

#

SIDE SECTOR LENGTH CRC CRC 11 BYTES 6 BYTES • •

/I 1 2 'FF' '00'

' - - - - - - - - - - I D F I E L D - - - - - - - - - - - '

DATA

ADR

MARK

USER DATA

128 BYTES

CRC

1

CRC

2

' - - - - - - - D A T A F I E L D I - - - -.....

"I

10 BYTES

'FF'

V

WRITEGATE---..1

SINGLE DENSITY FORMAT

INDEX

PULSE _ _ _

REPEATED

' - - - - - - - - - - -

'4E' '00' 'AI' 'FE'

FOR EACH SECTOR

•

/I

•

/I 1 2 '4E' '00' 'AI' 'FB' 256 BYTES 1 2 '4E'

"'1 I"

I

60 BYTES 12 BYTES 3 BYTES 10 TRACK SIDE SECTOR LENGTH CRC CRC 22 BYTES 12 BYTES 3 BYTES ID USER DATA CRC CRC 24 BYTES

(

I

10 FIELD

I I

DATA FIELD

WRITE GATE----~

DOUBLE DENSITY FORMAT

NUMBER

OF BYTES HEX VALUE OF BYTE WRITTEN

60

12

3

1

1

22

12

3

1

256

1

1

1

1

4E

00

F5 (Writes A 1)

FE (10 Address Mark)

Track Number (0 thru 4C)

Side Number (0 or 1)

Sector Number (1 thru 1A)

01 (Sector Length)

F7 (2 CRC's written)

4E

00

F5 (Writes A 1)

FB (Data Address Mark)

DATA

1 F7 (2 CRC's written)

24 4E

668-4E

-Wnte bracketed field 16 times.

- -Continue writing until WD1770 interrupts out.

Approx. 668 bytes.

1. Non-Standard Formats

Variations in the recommended formats are possible to a limited extent if the following requirements are met:

1) Sector size must be 128, 256, 512 of 1024 bytes.

2) Gap 2 cannot be varied from the recOmmended format.

3) 3 bytes of A 1 must be used in MFM.

In addition, the Index Address Mark is not required for operation by the WD1770 Gap 1, 3, and 4· lengths can be as short as 2 bytes for WD1770 operation, however PLL lock up time, motor speed variation, write-s'plice area, etc. will add more bytes to each gap to achieve proper operation. It Is recommended that the recommended format be used for highest system reliability.

Gap I

Gap II

-

-

Gap 111--

FM

16 bytes FF

11 bytesFF

6 bytes 00

10 bytes FF •

4 bytes 00

MFM

32bytes4E

22bytes4E

12 bytes 00

3 bytesA1

24bytes4E

8 bytes 00

3 bytesA1

Gap IV 16 bytes FF 16bytes4E

- Byte counts must be exact.

- - Byte counts are minimum, except exactly 3 bytes of A 1 must be written.

STATUS REGISTER DESCRIPTION

BIT NAME

S7MOTORON

MEANING

This bit reflects the status of the Motor On output.

S6 WRITE PROTECT On Read Record: Not Used. On Read Track: Not Used. On any Write: It indicates a

Write Protect. This bit is reset when updated.

SSRECORD lYPEISPIN·UP

S4 RECORD NOT

FOUND (RNF)

When set, this bit indicates that the Motor Spin·Up sequence has completed (6 revolutions) on Type I commands. Type 2 & 3 commands, this bit indicates record

Type. 0

=

Data Mark. 1

=

Deleted Data Mark~

When set, it indicates that the desired track, sector, or Side were not found. This bit is reset when updated.

S3CRCERROR

S2 LOST DATAl

TRACK 00

S1 DATA REQUESTI

INDEX so

BUSY

If S4 is set, an error is found in one or more 10 fields; otherwise it indicates error in data field. This bit is reset when updated.

When set, it indicates the computer did not respond to DRQ in one byte time. This bit is reset to zero when update. On Type I commands, this bit reflects the status of the TRACK 00 Pin.

This bit is a copy of the ORO output. When set, it indicates the DR is full on a Read

Operation or the DR is empty on a Write operation. This bit is reset to zero when updated. On Type I commands, this bit indicates the status of the Index Pin.

When set, command is under execution. When reset, no command is under execution.

DC ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Storage Temperature ......... - 55°C to

+

125·C Maximum Voltage to Any Input

Operating Temperature ...... O·C to 70·C Ambient with Respectto Vss ............. (-15 to - 0.3V)

18

Reproduced with permiSSion from western Dlgltsl Corporation

DC OPERATING CHARACTERISTICS

TA

=

O·C to 70·C, Vss

=

OV, VCC

=

+ 5V ± .25V

SYMBOL

III

CHARACTERISTIC

Input leakage

MIN.

IOl Output Leakage

VIH Input High Voltage 2.0

Vil Input low Voltage

VOH Output High Voltage 2.4

Output low Voltage VOL

Po

Rpu

Power Dissipation

Intemal Pull·Up 100

ICC Supply Current 75 (Typ)

MAX.

10

10

0.8

0.40

.75

1700

1SO

UNITS

/AA

/AA

V

V

V

V

W

/AA rnA

CONDITIONS

VIN

VOUT

=

Vee

=

Vee

10

10

=

-1oo/AA

=

VIN

1.6mA

=

OV

AC TIMING CHARACTERISTICS

TA

=

O·C to 70·C, Vss

=

OV, VCC

=

+ 5V ± .25V

READ ENABLE TIMING - RE such that: RIW

=

1, CS

= o.

SYMBOL CHARACTERISTIC MIN. TYP.

TRE RE Pulse Width of CS

TDRR

TIRR

DRa Reset from RE

INTRa Reset from RE

TOV Data Valid from RE

TDOH Data Hold from RE

1SO

SO

25

100

MAX. UNITS

100

8000

200

1SO nsec nsec nsec nsec nsec

CONDITIONS

CL

=

SOpf

CL

CL

=

SOpf

=

SOpf

Note: DRa and INTRQ reset are from rising edge (lagging) of RE, whereas resets are from falling edge (leading) of WE.

WRITE ENABLE TIMING - WE such that: RIW

=

0, CS

= o.

SYMBOL CHARACTERISTIC MIN. TYP.

TAS

TSET

Setup ADDR to CS

Setup RIW to CS

Hold ADDR from CS TAH

THLD

TWE

Hold RIW from CS

WE Pulse Width

TORW DRQ Reset from WE

TlRW INTRa Reset from WE

TOS

TDH

Data Setup to WE

Data Hold from WE

SO

0

20

0

1SO

1SO

0

100

MAX.

200

8000

UNITS nsec nsec nsec nsec nsec nsec nsec nsec nsec

CONDITIONS

19

ReprOduced with permission from

Western Digital Corporation

~~L5

I

X

VALID .

X,---

R,iW

AO,Al

O~

I

,~ t'08]=::3

----------.1\

TRE, TWE

~

"fl

--------1

_----..''':1

X

=l r-

'"CO

xr---:-··.---

~ ~

xr----

I

I I

I r-

TORR - , \

I

REGISTER TIMINGS

20

Reproduced with penni_ion from

Westem DIgital Corporation .

/\

-h-

I

EARlYTWP

I

1\ 1\

I I

6·112 CLKS

NOMINAL TWP

LATETWP f I f

I

5-112 ClKS

4·112 ClKS

WRITE DATA nMING

WRITE DATA nMING:

SYMBOL

Twg

CHARACTERISTIC

Write Gate to Write Data

Tbc

Twf

Write Data Cycle Time

Write Gate off from WD

Twp Write Data Pulse Width

INPUT DATA nMING:

SYMBOL

TPW

TBC

CHARACTERI8nC

Raw Read Pulse Width

Raw Read Cycle Time

MIN.

200

3000

MISCELLANEOUS nMING:

SYMBOL

TCD1

TCD2

TSTP

CHARACTERlSnC

Clock Duty (low)

Clock Duty (high)

Step Pulse Output

TDIR

TMR

TIP

Dir Setup to Step

Master Reset Pulse Width

Index Pulse Width

MIN.

50

50

50

20

MIN.

TYp.

4

2

4,6,8

4

2

820

690

570

1380

TYP.

TYp.

"67

67

4

8

24

48

MAX. UNITS

"sec

"sec

"sec

"sec

"sec nsec nsec nsec nsec

MAX. UNITS nsec nsec

MAX. UNITS nsec nsec

"sec

"sec

"sec

"sec

CONDmoNS

FM

MFM

FM

MFM

EarlyMFM

NominalMFM

LateMFM

FM

CONDmONS

CONDmoNS

MFM

FM

MFM

FM

1\

I

} t-

.l\-

21

Reproduced with permlaslon from western Digital Corporation

w

~f-.---------------

, . . - - - - - - - - - - - - - t $ · V I H f.m

S~-----....,I

I-TMR-I

DIRC

VOL

STEP

I

STEP IN

_R,Ro°_

MISCELLANEOUS nMING

22

Reproduced with perm_Ion !rom .

Western DIgital Corporation

NCR 5380 SCSI INTERFACE

PRODUCT BRIEF

SCSI INTERFACE

• Asynchronous data transfer to 1.5 M BPS

• Supports both initiator and target roles

• Parity generation w/optlonal checking

• Supports arbitration

• Direct control of aU bus signals

• High current outputs drive SCSI bus directly

MPUINTERFACE

• Memory or 1/0 mapped Interface

• DMA or programmed I/O

• Normal or block mode DMA

• Optional MPU Interrupts

The NCR 5380 is designed to accommodate the Small Computer Systems Interface (SCSI) as defined by the ANSI X3T9.2 committee. The 5380 operates in both the Initiator and Target roles and can there· fore be used in host adapter and control unit designs. This device supports arbitration, including reselection, and is intended to be used in systems that require either open collector or differential pair transceivers. * It has special high current outputs for driving the SCSI bus directly in the open collector mode.

The NCR 5380 communicates with the system microprocessor as a peripheral device. The chip is controlled by reading and writing several internal registers which may be addressed as standard or memory mapped 110. Minimal processor intervention is required for DMA transfers because the 5380 controls the necessary handshake signals. The NCR 5380 interrupts the MPU when it detects a bus condition that requires attention. Normal and block mode DMA is provided to match many popular

DMA controllers.

* Differential pair operation is supported in the NCR 5381 (48 PIN).

OMA

["OP

READY

CONTROL ORQ

OACK

REGISTER

[~

ADDRESSING AO

A1

A2

DATA BUS 00 ... 07

RESET

IRQ

GNO

FUNCTIONAL PIN GROUPING

NCR

5380

SCSI OAT A BUS

I

[)SO" ...

I

7, DBP

BSY

SEL

RST

ATN SCSI

ACK CONTROLS

REQ

MSG c/o

110

VOO

DO

OB7

DB6

DB5

OB4

OB3

OB2

OB1

OBO

OBP

GNO

SEL

BSY

ACK

ATN

RST

110

C/O

MSG

REQ

PINOUT

NCR

5380

01

02

03

04

05

06

07

A2

A1

Voo

AO lOW mn

EOP

DACR

READY lOR

IRQ

ORQ cs

2 m8~

PIN DESCRIPTIONS

MICROPROCESSOR INTERFACE SIGNALS

Pin Name Pin Number Description

AO ... A2 30,32,33 INPUTS _ _

This address is used with CS, lOR or lOW to address ali internal registers.

21 INPUT

Chip Select enables a read or write of the internal register selected by AO ... A2. CS is a low active signal.

POWER SIGNALS

Pin Name Pin Number Description

VDD 31 +5 VOLTS

GND 11 GROUND

SCSI INTERFACE SIGNALS

Pin Name Pin Number Description

ACK 14 BI-DIRECTIONAl, OPEN COL.

INITIATOR ROLE: The chip asserts this 8igl')al in response to JiEtI for a byte transfer on the SCSI bus.

TARGET ROLE: ACK is received as a response to the REa signal.

26 INPUT

DMA Acknowledge resets ORa and selects the data register for input or output. DACK is a low active signal.

ATN. 15

ORa

00 ... 07 34 ... 40,1 BI-DIRECTIONAl, TRI·STATE

Microprocessor data bus Active high

EOP lOR lOW

IRa

READY

RESET

22

27

24

29

23

25

28

OUTPUT

DMA Request indicates that the data register is ready to be read or written. ORa occurs only if

DMA MODE is true in the command register. It is cleared by

DACK.

INPUT

The End of Process signal is true during the last byte of a DMA transfer. This stops additional transfers but aliows the current transfer to finish. EOP is a low active signal.

INPUT

110 Read is used to read an internal register selected by CS and

AO ... A2. It aiso selects the data

!.!!9!ster when used with DACK. iOR is a low active signal.

INPUT

110 Write is used to write an internal register selected by bs and

AO ... A2. It also selects the data register when used with DACK. lOW is a low active signal.

OUTPUT

Interrupt Request alerts the microprocessor of an error condition or an event completion.

OUTPUT

Ready can be used to control the speed of block mode DMA transfers.

INPUT

Reset clears ali registers. It does not force the SCSI signal RST to the active state. RESET is a low active signal.

C/O

116

MSG

REO

RST

SBO...

SB7,SBP

13

18

17

19

20

16

2 ... 10 sa

12

BI-DIRECTIONAl, OPEN COL.

INITIATOR ROLE: The chip asserts this signal when the microprocessor requests the attention condition.

TARGET ROLE: ATN is a received signal.

ATN is an active low signal.

BI-DIRECTIONAl, OPEN COL.

The SCSI BSY signal can be driven and received concurrently.

BSY is an active low signal.

BI-DIRECTIONAL, OPEN COL.

Command/Data is an input for an initiator, an 9utput for a target. It indicates a command when asserted.

C7D is an active low signal.

BI-DIRECTIONAl, OPEN COL.

Input/Output is an input for an initiator, an output for a target. It indicates an input to the initiator when asserted.

I/O is an active low signal.

BI-DIRECTIONAl, OPEN COL.

Message is an input for an initiator, an output for a target. It indicates a message when asserted.

JVlSG is an active low signal.

BI-DIRECTIONAL, OPEN COL.

The target asserts REO to request a byte transfer from t,he initiator.

The transfer may be in either direction.

REa is an active low signal.

BI-DIRECTIONAL, OPEN COL.

SCSI BUS reset signal

RST is an active low signal.

BI-DIRECTIONAL, OPEN COL.

SCSI DATA BUS and PARITY

These signals are low active

BI-DIRECTIONAL, OPEN COL.

Select is used for selection and reselect operations.

SEL is an active low signal.

NCR 5380 BLOCK DIAGRAM

r - - - - - - - - -- lOW" - - - - -,

IRQ

READY DRQ mrs

~

If

AO ..• A2 DO ... D7

I

I CPU

INTERFACE

I

_ ____

~

NCR 5380

HIGH CURRENT O.C.

OUTPUT DRIVERS

REGISTER SUMMARY

A2 A1 AD R/W REGISTER NAME

0

0

0 0 R Current SCSI Data

0 0 W Output Data Register

0 0 1 RIW Initiator Command Reg.

0 1 0 RIW Mode Register

0 1 1 RIW Target Command Reg.

1 0 0 R SCSI Bus Status

1 0 0 W Select Enable Register

1 0 1 R Bus & Status Register

1 0 1 W Start DMA Send

1 1 0 R Input Data Reg.

1 1 0 W Start Target Rec. DMA

1 1 1 R Reset Parityllnterrupts

1 1 1 W Start Init. Rec. DMA

3

4

REGISTER DESCRIPTION

READ

CURRENT SCSI DATA (00)

7 6 5 4 3 2 1 0

[J

I I I I I I I

DBO ... DB7

Assert

Assey Data Bus

Assert A N

Assertm

Ern?"

ACK - . I Assert

Lost Arbitration

Arbitration In Progress

Assert RST

Enable

Arbitration

DMA Mode

Monitor §SV

Ern'" Interrupt

Enable Parity Interrupt

Enable Parity Checking

Target Mode

Block Mode DMA

TARGET COMMAND REGISTER (03)

7 6 5· 4 3 2 1 0

COTIJ]]

0

I I I I J -'-

I I

I Assert

Assert

Assert MSG

Assert REO

C70

110

CURRENT SCSI BUS STATUS (04)

7 6 5 4 3 2 1 0

_SEL

DBP

_110

REO

~SY

RST

C/O

_MSG

...... 1

ATN

Busy Error

Phase Match

Interrupt Request

Parity Error

DMA Request

End of DMA

INPUT DATA REGISTER (06)

7 6 5 4 3 2 1 0

ccrrrrco

DBO ... DB7

RESET PARITYIINTERRUPT (07)

7 6 5 4 3 2 1 0

W£x:"X]

X ] X

Wi]

WRITE

OUTPUT DATA REGISTER (00)

7 6 5 4 3 2 1 0

I I I I I I I I

DBO: .. DB7

Assert Data Bus

AssmA'm .

Ass!H1.SEL

Assert

Test Mode

Assert RST

BSY

Assert~

Differential Enable (NCR 5381)

Monitor

Enable

Arbitration

DMAMode

EOJ5

BSY

Interrupt

I

Enable Parity Interrupt

Enable Parity Checking

Target Mode

Block Mode DMA

TARGET COMMAND REGISTER (03)

7 6 5 4 3 2 1 0

I

X

I

X

I

X

I xl I II I

I I

I Assert

Assert

Assert~

Assert A'EQ

C1D i/O

SELECT ENABLE REGISTER (04)

7 6 5 4 3 2 1 0

I I I I I I I I

DBO ... DB7

START DMA SEND (05)

7 6 5 4 3 2 1 0

/xlxlxlxlxlxlxlxl

START DMA TARGET RECEIVE (06)

7 6 5 4 3 2 1 0

Ixlxlxlxlxlxlxlxl

START DMA INITIATOR RECEIVE (07)

7 6 5 4 3 2 1 0

Ixlxlxlxlxlxlxlxl

NOTE: X

=

DON'T CARE

NCR 5380

ELECTRICAL CHARACTERISTICS

OPERATING CONDITIONS

PARAMETER

Supply Voltage

Supply Current

Ambient Temperature

SYMBOL MIN MAX UNITS

VOO

100

TA

4.75 5.25 Volts

145 rnA ..

0 70 °C

INPUT SIGNAL REQUIREMENTS

PARAMETER

High·level, Input VIH

Low·level, Input VIL

CONDITIONS MIN MAX UNITS

2.0 5.25 Volts

-0.3 0.8 Volts

SCSI BUS pins 2 ••• 20

High·levellnput Current, IIH VIH = 5.25 V

Low·level Input Current, IlL VIL= 0 Volts

All other pins

High·levellnput Current, IIH VIH= 5.25 V

Low·level Input Current, IlL VIL= 0 Volts

50

·50

10

·10

",a.

J4a.

).La.

).La.

OUTPUT SIGNAL REQUIREMENTS

CONDITIONS MIN MAX UNITS PARAMETER

SCSI BUS pins 2 ••• 20

Low·level Output VOL VOO = 4.75 V

IOL= 48.0 rnA. 0.5 Volts

All other pins

High·level Output VOH

Low·level Output VOL

VOO = 4.75 V

IOH = ·3.0mA.

VOO = 4,75 V

IOL = 7.0mA.

2.4 Volts

0.5 Volts

PRELIMINARY

Notice: This is not a final specification.

Some parametric limits are subject to change.

NCR 5380

5

TYPICAL CONFIGURATION NCR 5380

DMA

CONTROL LOGIC t - -.....

EOP

........

---f~~gK

NCR 5380

..... --tREADy

SCSI BUS

NCR MICROELECTRONICS DIVISION

1635 Aeroplaza Drive

Colorado Springs, Colorado 80916

Phone: 8001525·2252

Telex: 45 2457 NCR MICRO CSP

While the information herein presented has been checked for both accuracy and reliability, NCR assumes no responsibility for either Its use or for the Infringement of any patents or other rights of third parties, which would result from its use. The publication and dissemination of the enclosed information confers no license, by implication or otherwise, under any patent or patent rights owned by NCR.