PCI 9056RDK-LITE

Errata Documentation

1. PME# MOSFET Source/Drain Reversed

Errata Revision 1.2

Note. This erratum only pertains to PCI 9056RDK-Lite board revisions prior to board p/n 90-0020-200-A. It has been fixed in revision 90-0020-200-A and later.

Description: The MOSFET used in the PME# circuit has an internal protection diode, and consequently MOSFET source/drain orientation is not reversible within this circuit. The orientation shown in the original schematic and used in the RDK can provide a low impedance path to ground when power is off, in violation of the PCI Bus Power Management Interface Specification. Thus inserting the RDK into a PCI slot while the system is in a low-power state could cause the system to detect PME# assertion and consequently wake up.

Workaround:

1. The correct MOSFET orientation is shown on current RDK schematics

(revision 205, dated Oct. 21, 2004), and is detailed below:

CARD_VAUX

PCI PME#

D

240K

240K

G

0.1µF

S

N-Channel MOSFET

FDN335N

PLX PME#

2. On PCI 9056RDK-Lite schematics prior to revision 200, reverse U5 pins 2 and 3.

2. Install Current-limiting Resistors between PCI Connector

VIO Pins and PCI 9056 VIO Power Pins

Note. This erratum pertains to all PCI 9056RDK-Lite board revisions.

Description: PCI 9056 Data Book Section 13.1 states, with respect to power sequencing requirements, the following: there are five different power sources-

Vring, Card_Vaux, Vcore, 2.5Vaux, and VIO. To properly sequence power to

Document number: PCI 9056/LITE-RDK-ER-1.2

Revision: Released Rev. 1.2

-1-

these five sources, the only requirement is that Vcore, 2.5Vaux, and VIO must receive power no later than 10 ms after Vring and Card_Vaux receive power...

Caution: Violating the above power sequencing requirement will damage the

PCI 9056 device.

Each PCI pin/pad contains two clamping diodes, one to VIO and the other to ground. If the VIO voltage source is not powered and it presents a low impedance path to ground, the PCI 9056's VIO pins can source high current, which could damage the part immediately or cause undue long-term electrical stress to the part. The amount of current each PCI pin/pad will source is dependent upon the device that is driving the signal/pad, or upon the value of the pull-up resistor when the signal is not driven.

Workaround: For designs and add-in cards that have an independent voltage source for VIO for which proper power sequencing cannot be guaranteed, a resistor MUST be used between the VIO voltage source and PCI 9056 VIO pins to limit the current and protect the device from damage or long term undue stress. Use the following guidelines to determine the value of this required resistance.

A 40-200 ohm resistance between the VIO voltage source and PCI 9056 VIO pins is recommended if VIO will be a maximum of 3.6 Volts (3.3 Volt signaling environments only). For designs that can operate in either 3.3 or 5.0 Volt signaling environments, 40-70 ohm resistance is recommended. A single resistor can be used if the VIO pins are bused, or multiple parallel resistors can be used between the VIO voltage source and the VIO pins. The power dissipation rating of the resistor(s) depends upon the size of the resistance and the signaling environment. For example, if a single 50 ohm resistor is used in a 5V signaling environment, the worst case power dissipation would be 480mW calculated as

(V*V)/R (5.5V (maximum signal amplitude plus 10%) - 0.6V (1 diode drop)) squared divided by 50 ohms = 480mW. If four 200 ohm resistors are used in parallel, each would need to be able to dissipate 120mW.

Any resistance value within the recommended ranges will prevent the part from being damaged while providing enough clamping action to keep the Input

Voltage (VIN) below its maximum rating. A resistance value at the lower end of the range is recommended to provide better clamping action and therefore provide more Input Voltage (VIN) margin.

The PCI Specification requires that each PCI connector VIO pin that is unused must be decoupled to ground with at least 0.01 µF average capacitance per pin

(VIO pins can share capacitors), and VIO pins that are used should be decoupled to ground with average capacitance of at least 0.047 µF average capacitance per pin. Trace length from the PCI connector pad to the capacitor pad, assuming

0.02 inch trace width, must not exceed 0.25 inches.

On the PCI 9056RDK-860, PCI VIO pins that are connected to the PCI 9056 are not decoupled. The single unused VIO pin, A59, is decoupled by capacitor C9.

Document number: PCI 9056/LITE-RDK-ER-1.2

Revision: Released Rev. 1.2

-2-

If a board design includes decoupling capacitors on VIO traces connected to the

PCI 9056, each VIO current-limiting resistor needs to be installed between the

VIO decoupling capacitor and the PCI 9056, so that in the event the VIO power sequencing requirement is not met, current to charge the capacitors that is sourced through the PCI 9056 will be limited by the resistance.

Current-limiting resistors should be installed between:

PCI connector pin A10 and PCI 9056 ball B3

PCI connector pin A16 and PCI 9056 ball E2

PCI connector pin B19 and PCI 9056 ball M2

PCI connector pin B59 and PCI 9056 ball N4

_____________________________________________________________________________

Copyright

©

2005 by PLX Technology, Inc. All rights reserved. PLX is a trademark of PLX Technology, Inc. which may be registered in some jurisdictions. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by

PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology reserves the right, without notice, to make changes in product design or specification..

-3-

Document number: PCI 9056/LITE-RDK-ER-1.2

Revision: Released Rev. 1.2