NXP Semiconductors ColdFire MCF52233 Reference Manual

MCF52235 ColdFire

®

Integrated

Microcontroller Reference Manual

Devices Supported:

MCF52230

MCF52231

MCF52233

MCF52234

MCF52235

Document Number:

MCF52235RM

Rev. 0

04/2006

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© Freescale Semiconductor, Inc. 2006. All rights reserved.

Document Number: MCF52235RM

Rev. 0

04/2006

Table of Contents

Chapter 1

Overview

1.1

MCF52235 Family Configurations ...................................................................................................2

1.2

Block Diagram ..................................................................................................................................2

1.3

Part Numbers and Packaging ............................................................................................................4

1.4

Features .............................................................................................................................................4

Chapter 2

Signal Descriptions

2.1

Introduction .......................................................................................................................................1

2.2

Overview ...........................................................................................................................................1

2.3

Reset Signals .....................................................................................................................................8

2.4

PLL and Clock Signals ......................................................................................................................8

2.5

Mode Selection ..................................................................................................................................8

2.6

External Interrupt Signals ..................................................................................................................8

2.7

Queued Serial Peripheral Interface (QSPI) .......................................................................................9

2.8

Fast Ethernet Controller PHY Signals ............................................................................................10

2.9

I

2

C I/O Signals ................................................................................................................................10

2.10 UART Module Signals ....................................................................................................................11

2.11 DMA Timer Signals ........................................................................................................................11

2.12 ADC Signals ....................................................................................................................................11

2.13 General Purpose Timer Signals .......................................................................................................12

2.14 Pulse Width Modulator Signals .......................................................................................................12

2.15 Debug Support Signals ....................................................................................................................12

2.16 EzPort Signal Descriptions ..............................................................................................................13

2.17 Power and Ground Pins ...................................................................................................................14

Chapter 3

ColdFire Core

3.1

Processor Pipelines ............................................................................................................................1

3.2

Memory Map/Register Description ...................................................................................................2

3.3

Instruction Set Architecture (ISA_A+) .............................................................................................8

3.4

Exception Processing Overview ........................................................................................................8

3.5

Exception Stack Frame Definition ..................................................................................................10

3.6

Processor Exceptions .......................................................................................................................11

3.7

Instruction Execution Timing ..........................................................................................................18

3.8

Standard One Operand Instruction Execution Times ......................................................................20

MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 0


Preliminary iii

3.9

Standard Two Operand Instruction Execution Times ......................................................................21

3.10 Miscellaneous Instruction Execution Times ...................................................................................22

3.11 EMAC Instruction Execution Times ...............................................................................................23

3.12 Branch Instruction Execution Times ...............................................................................................24

Chapter 4

Enhanced Multiply-Accumulate Unit (EMAC)

4.1

Multiply-Accumulate Unit ................................................................................................................1

4.2

Introduction to the MAC ...................................................................................................................2

4.3

General Operation .............................................................................................................................2

4.4

Memory Map/Register Definition .....................................................................................................5

4.5

EMAC Instruction Set Summary ....................................................................................................11

Chapter 5

Cryptographic Acceleration Unit

5.1

CAU Registers ...................................................................................................................................1

5.2

CAU Operation .................................................................................................................................2

5.3

CAU Commands ...............................................................................................................................2

5.4

CAU Equate Values ...........................................................................................................................7

Chapter 6

Random Number Generator Accelerator (RNGA)

6.1

Overview ...........................................................................................................................................1

6.2

Features .............................................................................................................................................2

6.3

Modes of Operation ...........................................................................................................................2

6.4


6.5

Functional Description ....................................................................................................................11

6.6

Initialization/Application Information ............................................................................................12

Chapter 7

Clock Module

7.1

Introduction .......................................................................................................................................1

7.2

Features .............................................................................................................................................1

7.3

Modes of Operation ...........................................................................................................................1

7.4

Low-power Mode Operation .............................................................................................................2

7.5

Block Diagram ..................................................................................................................................2

7.6

Signal Descriptions ...........................................................................................................................4

7.7

Memory Map and Registers ..............................................................................................................5

7.8


Chapter 8

Real Time Clock

8.1

Introduction .......................................................................................................................................1

8.2


iv



Preliminary

8.3


8.4

Initialization/Application Information ............................................................................................13

Chapter 9

Power Management

9.1

Introduction .......................................................................................................................................1

9.2


9.3

IPS Bus Timeout Monitor ...............................................................................................................10

9.4


Chapter 10

Reset Controller Module

10.1 Introduction .......................................................................................................................................1

10.2 Features .............................................................................................................................................1

10.3 Block Diagram ..................................................................................................................................1

10.4 Signals ...............................................................................................................................................2

10.5 Memory Map and Registers ..............................................................................................................2

10.6 Functional Description ......................................................................................................................5

Chapter 11

Static RAM (SRAM)

11.1 Introduction .......................................................................................................................................1

11.2 Memory Map/Register Description ...................................................................................................1

11.3 Initialization/Application Information ..............................................................................................3

Chapter 12

Chip Configuration Module (CCM)

12.1 Introduction .......................................................................................................................................1

12.2 External Signal Descriptions .............................................................................................................2

12.3 Memory Map/Register Definition .....................................................................................................2


12.5 Reset ..................................................................................................................................................6

Chapter 13

System Control Module (SCM)

13.1 Introduction .......................................................................................................................................1

13.2 Overview ...........................................................................................................................................1

13.3 Features .............................................................................................................................................1

13.4 Memory Map and Register Definition ..............................................................................................2

13.5 Register Descriptions ........................................................................................................................3

13.6 Internal Bus Arbitration ..................................................................................................................11

13.7 System Access Control Unit (SACU) .............................................................................................14



Preliminary v

Chapter 14

General Purpose I/O Module

14.1 Introduction .......................................................................................................................................1

14.2 Overview ...........................................................................................................................................2

14.3 Features .............................................................................................................................................3

14.4 Signal Descriptions ...........................................................................................................................3



14.7 Ports Interrupts ................................................................................................................................15

Chapter 15

Interrupt Controller Module

15.1 68K/ColdFire Interrupt Architecture Overview ................................................................................1

15.2 Memory Map .....................................................................................................................................4


15.4 Low-Power Wakeup Operation .......................................................................................................18

Chapter 16

Edge Port Module (EPORT)

16.1 Introduction .......................................................................................................................................1

16.2 Low-Power Mode Operation .............................................................................................................2

16.3 Interrupt/GPIO Pin Descriptions .......................................................................................................2


Chapter 17

ColdFire Flash Module (CFM)

17.1 Introduction .......................................................................................................................................1

17.2 External Signal Description ..............................................................................................................3

17.3 Memory Map and Register Definition ..............................................................................................3

17.4 Functional Description ....................................................................................................................14

Chapter 18

Fast Ethernet Controller (FEC)

18.1 Overview ...........................................................................................................................................1

18.2 Modes of Operation ...........................................................................................................................1

18.3 FEC Top-Level Functional Diagram .................................................................................................3


18.5 Programming Model .......................................................................................................................17

18.6 Buffer Descriptors ...........................................................................................................................42

Chapter 19

Ethernet Physical Transceiver (EPHY) Block Description

19.1 Introduction .......................................................................................................................................1

19.2 External Signal Descriptions .............................................................................................................3

vi



Preliminary

19.3 Memory Map and Register Descriptions ..........................................................................................5


Chapter 20

DMA Controller Module

20.1 Introduction .......................................................................................................................................1

20.2 M-bus Priority Level (MPL) .............................................................................................................4

20.3 DMA Transfer Overview ..................................................................................................................4



Chapter 21

EzPort

21.1 Features .............................................................................................................................................1

21.2 Modes of Operation ...........................................................................................................................1


21.4 Command Definition .........................................................................................................................3



Chapter 22

Programmable Interrupt Timer Modules (PIT0–PIT1)

22.1 Introduction .......................................................................................................................................1



Chapter 23

General Purpose Timer Module (GPT)

23.1 Introduction .......................................................................................................................................1

23.2 Features .............................................................................................................................................1

23.3 Block Diagram ..................................................................................................................................2

23.4 Low-Power Mode Operation .............................................................................................................3

23.5 Signal Description .............................................................................................................................3

23.6 Memory Map and Registers ..............................................................................................................4


23.8 Reset ................................................................................................................................................21

23.9 Interrupts .........................................................................................................................................21

Chapter 24

DMA Timers (DTIM0–DTIM3)

24.1 Introduction .......................................................................................................................................1






Preliminary vii

Chapter 25

Queued Serial Peripheral Interface (QSPI)

25.1 Introduction .......................................................................................................................................1




25.5 Initialization/Application Information ............................................................................................16

Chapter 26

UART Modules

26.1 Introduction .......................................................................................................................................1




I

2

Chapter 27

C Interface

27.1 Introduction .......................................................................................................................................1

27.2 Overview ...........................................................................................................................................1

27.3 Features .............................................................................................................................................1

27.4 I

2

C System Configuration .................................................................................................................3


27.6 I

2

C Programming Examples ............................................................................................................12

Chapter 28

Analog-to-Digital Converter (ADC)

28.1 Introduction .......................................................................................................................................1

28.2 Features .............................................................................................................................................1

28.3 Block Diagram ..................................................................................................................................1


28.5 Register Definitions .........................................................................................................................18

Chapter 29

Pulse Width Modulation (PWM) Module

29.1 Introduction .......................................................................................................................................1



Chapter 30

FlexCAN

30.1 Introduction .......................................................................................................................................1



30.4 Functional Overview .......................................................................................................................20

30.5 FlexCAN Initialization Sequence ....................................................................................................28

viii



Preliminary

Chapter 31

Debug Module

31.1 Introduction .......................................................................................................................................1


31.3 Real-Time Trace Support ..................................................................................................................3


31.5 Background Debug Mode (BDM) ...................................................................................................17

31.6 Real-Time Debug Support ...............................................................................................................37

31.7 Processor Status, DDATA Definition ..............................................................................................40

31.8 Freescale-Recommended BDM Pinout ...........................................................................................44

Chapter 32

IEEE 1149.1 Test Access Port (JTAG)

32.1 Introduction .......................................................................................................................................1




32.5 Initialization/Application Information ............................................................................................10

Appendix A

Register Memory Map Quick Reference



Preliminary ix

x



Preliminary

Chapter 1

Overview

This chapter provides an overview of the major features and functional components of the MCF52235 family of microcontrollers. The MCF52235 family is a highly integrated implementation of the ColdFire

® family of reduced instruction set computing (RISC) microcontrollers that also includes the MC52230,

MCF52231, MC52233 and MC52234 . The differences between these parts are summarized in Table 1-1 .

This document is written from the perspective of the MC52235 .The MC52235 represents a family of highly-integrated 32-bit microcontrollers based on the V2 ColdFire microarchitecture. Featuring up to 32

Kbytes of internal SRAM and 256 Kbytes of Flash memory, four 32-bit timers with DMA request capability, a 4-channel DMA controller, fast Ethernet, a CAN module, an I

2

C™ module, 3 UARTs and a queued SPI, the MC52235 family has been designed for general-purpose industrial control applications. n enhanced multiply-accumulate unit (EMAC) and divider providing 56Drystone 2.1 MIPS at a frequency up to 60MHz from internal Flash. On-chip modules include the following:

• V2 ColdFire core with enhanced multiply-accumulate unit (EMAC)

• Cryptographic Acceleration Unit (CAU)

• 32 Kbytes of internal SRAM

• 256 Kbytes of on-chip Flash memory

• Fast Ethernet Controller (FEC) with on-chip transceiver (ePHY)

• Three universal asynchronous receiver/transmitters (UARTs)

• Controller area network 2.0B (FlexCAN) module

• Inter-integrated circuit (I 2 C) bus controller

• 12-bit analog-to-digital converter (ADC)

• Queued serial peripheral interface (QSPI) module

• Four-channel, 32-bit direct memory access (DMA) controller

• Four-channel, 32-bit input capture/output compare timers with optional DMA support

• Two 16-bit periodic interrupt timers (PITs)

• Programmable software watchdog timer

• Two interrupt controllers, each capable of handling up to 63 interrupt sources (126 total)

These devices are ideal for cost-sensitive applications requiring significant control processing for connectivity, data buffering, and user interface, as well as signal processing in a variety of key markets such as security, imaging, networking, gaming, and medical. This leading package of integration and high performance allows fast time to market through easy code reuse and extensive third party tool support.

To locate any published errata or updates for this document, refer to the ColdFire products website at http://www.freescale.com/coldfire .



Preliminary

1-1

Overview

1.1

MCF52235 Family Configurations

Table 1. MCF52235 Family Configurations

Module 52230 52231 52233 52234 52235

ColdFire Version 2 Core with EMAC (Enhanced

Multiply-Accumulate Unit)

System Clock

Performance (Dhrystone 2.1 MIPS)

Flash / Static RAM (SRAM)

Interrupt Controllers (INTC0/INTC1)

Fast Analog-to-Digital Converter (ADC)

Random Number Generator and Crypto

Acceleration Unit (CAU)

FlexCAN 2.0B Module

Fast Ethernet Controller (FEC) with on-chip interface (EPHY)

Four-channel Direct-Memory Access (DMA)

Software Watchdog Timer (WDT)

Programmable Interrupt Timer

Four-Channel General Purpose Timer

32-bit DMA Timers

QSPI

UART(s)

I

2

C

Eight/Four-channel 8/16-bit PWM Timer

General Purpose I/O Module (GPIO)

Chip Configuration and Reset Controller Module

Background Debug Mode (BDM)

JTAG - IEEE 1149.1 Test Access Port

1 x

128/32 Kbytes 128/32 Kbytes x x

x x

x x x x x x x

3 x

4 x x

2

x x x x x x x x x

3 x

4 x x

2 x x x

60 MHz

56 x x x x x x x

3 x

4 x x

2 x x

-

x x

256/32 Kbytes x x

x x x x x x x

3 x

4 x x

2 x x x x x x x x

1

Package 80, 112-pin

LQFP

80, 112-pin

LQFP

80, 112-pin

LQFP

121 MAPBGA

80, 112-pin

LQFP

121 MAPBGA

112-pin LQFP

121 MAPBGA

The full debug/trace interface is available only on the 112- and 121-pin packages. A reduced debug interface is bonded on the 80-pin package.

x x x x x x x

3 x

4 x x

2

1.2

Block Diagram

The superset device in the MCF52235 family comes in a 112-leaded quad flat package (LQFP) and a 121 pin MAPBGA. Figure 1-1 shows a top-level block diagram of the MCF52235 .

1-2



Preliminary

Overview

EPHY_TX

EPHY_RX

EzPD

EzPQ

EPHY

Fast

Ethernet

Controller

(FEC)

4 CH DMA

To/From PADI

JTAG_EN MUX

EzPort

Arbiter

EzPCK

EzPCS

Interrupt

Controller 1

Interrupt

Controller 2

UART

0

DTIM

0

UART

1

UART

2

DTIM

1

DTIM

2

I

2

C

DTIM

3

QSPI

RTC

V2 ColdFire CPU

IFP OEP CAU EMAC

AN[7:0]

JTAG

TAP

ADC

V

RH

V

RL

32 Kbytes

SRAM

(4Kx16)x4

256 Kbytes

Flash

(32Kx16)x4

PORTS

(GPIO)

PMM

CIM

Edge

Port 1

PLL

CLKGEN

Edge

Port 2

EXTAL XTAL CLKOUT

To/From Interrupt Controller

RNGA

FlexCAN

Figure 1-1. MCF52235 Block Diagram

PIT0

PIT1

GPT

PWM

ICOC n

QSPI_DIN,

QSPI_DOUT

QSPI_SCK,

QSPI_PCS n

I

2

C_SDA

I

2

C_SCL

U n TXD

U n RXD

U n RTS

U n CTS

DTIN n /DTOUT n

CANRX

CANTX

PWM n

RSTIN

RSTOUT



Preliminary

1-3

Overview

1.3

Part Numbers and Packaging

Table 1-2. Part Number Summary

Part Number

MCF52230

MCF52231

MCF52233

MDCF52234

MCF52235

Flash / SRAM Key Features

128 Kbytes / 32 Kbytes 3 UARTs, I

2

C, QSPI, A/D, FEC EPHY, DMA,

16-/32-bit/PWM Timers


2


16-/32-bit/PWM Timers, CAN


2


16-/32-bit/PWM Timers


2

C, QSPI, A/D, FEC, EPHY, DMA,

16-/32-bit/PWM Timers, CAN


2

C, QSPI, A/D, Crypto, FEC,

EPHY, DMA, 16-/32-bit/PWM Timers, CAN

Package

80-pin TQFP

112-pin LQFP

80-pin TQFP

112-pin LQFP

80-pin TQFP

112-pin LQFP

80-pin TQFP

112-pin LQFP

121 MAPBGA

112-pin LQFP

121 MAPBGA

Speed

60 MHz

60 MHz

60 MHz

60 MHz

60 MHz

Table 1-2

summarizes the features of the MCF52235 product family. Several speed/package options are available to match cost- or performance-sensitive applications.

1.4

Features

The MCF52235 family includes the following features:

• Version 2 ColdFire variable-length RISC processor core

— Static operation

— 32-bit address and data paths on-chip

— Up to 60 MHz processor core frequency

— Sixteen general-purpose, 32-bit data and address registers

— Implements ColdFire ISA_A with extensions to support the user stack pointer register and four new instructions for improved bit processing (ISA_A+)

— Enhanced Multiply-Accumulate (EMAC) unit with 32-bit accumulator to support

16 × 16 → 32 or 32 × 32 → 32 operations

— Cryptography Acceleration Unit (CAU)

– Tightly-coupled coprocessor to accelerate software-based encryption and message digest functions

– FIPS-140 compliant random number generator

— Support for DES, 3DES, AES, MD5, and SHA-1 algorithms

— Illegal instruction decode that allows for 68K emulation support

• System debug support

— Real time trace for determining dynamic execution path

— Background debug mode (BDM) for in-circuit debugging (DEBUG_B+)

— Real time debug support, with six hardware breakpoints (4 PC, 1 address and 1 data) that can be configured into a 1- or 2-level trigger

1-4



Preliminary

Overview

• On-chip memories

— 32-Kbyte dual-ported SRAM on CPU internal bus, supporting core and DMA access with standby power supply support

— 256 Kbytes of interleaved Flash memory supporting 2-1-1-1 accesses

• Power management

— Fully static operation with processor sleep and whole chip stop modes

— Very rapid response to interrupts from the low-power sleep mode (wake-up feature)

— Clock enable/disable for each peripheral when not used

• Fast Ethernet Controller (FEC)

— 10/100 BaseT/TX capability, half duplex or full duplex

— On-chip transmit and receive FIFOs

— Built-in dedicated DMA controller

— Memory-based flexible descriptor rings

• On-chip Ethernet Transceiver (EPHY)

— Digital adaptive equalization

— Supports auto-negotiation

— Baseline wander correction

— Full-/Half-duplex support in all modes

— Loopback modes

— Supports MDIO preamble suppression

— Jumbo packet

• FlexCAN 2.0B module

— Based on and includes all existing features of the Freescale TouCAN module

— Full implementation of the CAN protocol specification version 2.0B

– Standard Data and Remote Frames (up to 109 bits long)

– Extended Data and Remote Frames (up to 127 bits long)

– 0–8 bytes data length

– Programmable bit rate up to 1 Mbit/sec

— Flexible Message Buffers (MBs), totalling up to 16 message buffers of 0–8 byte data length each, configurable as Rx or Tx, all supporting standard and extended messages

— Unused Message Buffer space can be used as general purpose RAM space

— Listen only mode capability

— Content-related addressing

— No read/write semaphores required

— Three programmable mask registers: global for MBs 0-13, special for MB14, and special for

MB15

— Programmable transmit-first scheme: lowest ID or lowest buffer number



Preliminary

1-5

Overview

— “Time stamp” based on 16-bit free-running timer

— Global network time, synchronized by a specific message

— Maskable interrupts

• Three universal asynchronous/synchronous receiver transmitters (UARTs)

— 16-bit divider for clock generation

— Interrupt control logic with maskable interrupts

— DMA support

— Data formats can be 5, 6, 7 or 8 bits with even, odd or no parity

— Up to 2 stop bits in 1/16 increments

— Error-detection capabilities

— Modem support includes request-to-send (RTS) and clear-to-send (CTS) lines for two UARTs

— Transmit and receive FIFO buffers

• I 2 C module

— Interchip bus interface for EEPROMs, LCD controllers, A/D converters, and keypads

— Fully compatible with industry-standard I 2 C bus

— Master and slave modes support multiple masters

— Automatic interrupt generation with programmable level

• Queued serial peripheral interface (QSPI)

— Full-duplex, three-wire synchronous transfers

— Up to four chip selects available

— Master mode operation only

— Programmable bit rates up to half the CPU clock frequency

— Up to 16 pre-programmed transfers

• Fast analog-to-digital converter (ADC)

— Eight analog input channels

— 12-bit resolution

— Minimum 1.125 µ s conversion time

— Simultaneous sampling of two channels for motor control applications

— Single-scan or continuous operation

— Optional interrupts on conversion complete, zero crossing (sign change), or under/over low/high limit

— Unused analog channels can be used as digital I/O

• Four 32-bit DMA timers

— 16.7-ns resolution at 60 MHz

— Programmable sources for clock input, including an external clock option

— Programmable prescaler

— Input capture capability with programmable trigger edge on input pin

1-6



Preliminary

Overview

— Output compare with programmable mode for the output pin

— Free run and restart modes

— Maskable interrupts on input capture or output compare

— DMA trigger capability on input capture or output compare

• Four-channel general purpose timer

— 16-bit architecture

— Programmable prescaler

— Output pulse widths variable from microseconds to seconds

— Single 16-bit input pulse accumulator

— Toggle-on-overflow feature for pulse-width modulator (PWM) generation

— One dual-mode pulse accumulation channel

• Pulse-width modulation timer

— Operates as eight channels with 8-bit resolution or four channels with 16-bit resolution

— Programmable period and duty cycle

— Programmable enable/disable for each channel

— Software selectable polarity for each channel

— Period and duty cycle are double buffered. Change takes effect when the end of the current period is reached (PWM counter reaches zero) or when the channel is disabled.

— Programmable center or left aligned outputs on individual channels

— Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies

— Emergency shutdown

• Real-Time Clock (RTC)

— Maintains system time-of-day clock

— Provides stopwatch and alarm interrupt functions



Preliminary

1-7

Overview

• Two periodic interrupt timers (PITs)

— 16-bit counter

— Selectable as free running or count down

• Software watchdog timer

— 32-bit counter

— Low power mode support

• Clock Generation Features

— 25 MHz crystal input

— On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency

— Provides clock for integrated EPHY

• Dual Interrupt Controllers (INTC0/INTC1)

— Support for multiple interrupt sources organized as follows:

– Fully-programmable interrupt sources for each peripheral

– 7 fixed-level interrupt sources

– Seven external interrupt signals

— Unique vector number for each interrupt source

— Ability to mask any individual interrupt source or all interrupt sources (global mask-all)

— Support for hardware and software interrupt acknowledge (IACK) cycles

— Combinatorial path to provide wake-up from low power modes

• DMA controller

— Four fully programmable channels

— Dual-address transfer support with 8-, 16-, and 32-bit data capability, along with support for

16-byte (4 x 32-bit) burst transfers

— Source/destination address pointers that can increment or remain constant

— 24-bit byte transfer counter per channel

— Auto-alignment transfers supported for efficient block movement

— Bursting and cycle steal support

— Software-programmable DMA requesters for the UARTs (3) and 32-bit timers (4)

• Reset

— Separate reset in and reset out signals

— Seven sources of reset:

– Power-on reset (POR)

– External

– Software

– Watchdog

– Loss of clock

– Loss of lock

1-8



Preliminary

Overview

– Low-voltage detection (LVD)

— Status flag indication of source of last reset

• Chip integration module (CIM)

— System configuration during reset

— Selects one of three clock modes

— Configures output pad drive strength

— Unique part identification number and part revision number

• General purpose I/O interface

— Up to 56 bits of general purpose I/O

— Bit manipulation supported via set/clear functions

— Programmable drive strengths

— Unused peripheral pins may be used as extra GPIO

• JTAG support for system level board testing

1.4.1

V2 Core Overview

The version 2 ColdFire processor core is comprised of two separate pipelines that are decoupled by an instruction buffer. The two-stage instruction fetch pipeline (IFP) is responsible for instruction-address generation and instruction fetch. The instruction buffer is a first-in-first-out (FIFO) buffer that holds prefetched instructions awaiting execution in the operand execution pipeline (OEP). The OEP includes two pipeline stages. The first stage decodes instructions and selects operands (DSOC); the second stage

(AGEX) performs instruction execution and calculates operand effective addresses, if needed.

The V2 core implements the ColdFire instruction set architecture revision A+ with added support for a separate user stack pointer register and four new instructions to assist in bit processing. Additionally, the

MCF52235 core includes the enhanced multiply-accumulate (EMAC) unit for improved signal processing capabilities. The MAC implements a three-stage arithmetic pipeline, optimized for 16 x 16 bit operations, with support for one 32-bit accumulator. Supported operands include 16- and 32-bit signed and unsigned integers, signed fractional operands, and a complete set of instructions to process these data types. The EMAC provides support for execution of DSP operations within the context of a single processor at a minimal hardware cost.

1.4.2

Integrated Debug Module

The ColdFire processor core debug interface is provided to support system debugging in conjunction with low-cost debug and emulator development tools. Through a standard debug interface, users can access debug information and real-time tracing capability is provided on 112-and 121-lead packages. This allows the processor and system to be debugged at full speed without the need for costly in-circuit emulators.

The on-chip breakpoint resources include a total of nine programmable 32-bit registers: an address and an address mask register, a data and a data mask register, four PC registers, and one PC mask register. These registers can be accessed through the dedicated debug serial communication channel or from the processor’s supervisor mode programming model. The breakpoint registers can be configured to generate triggers by combining the address, data, and PC conditions in a variety of single- or dual-level definitions.



Preliminary

1-9

Overview

The trigger event can be programmed to generate a processor halt or initiate a debug interrupt exception.

The MCF52235 implements revision B+ of the coldfire Debug Architecture.

The MCF52235 ’s interrupt servicing options during emulator mode allow real-time critical interrupt service routines to be serviced while processing a debug interrupt event, thereby ensuring that the system continues to operate even during debugging.

To support program trace, the V2 debug module provides processor status (PST[3:0]) and debug data

(DDATA[3:0]) ports. These buses and the PSTCLK output provide execution status, captured operand data, and branch target addresses defining processor activity at the CPU’s clock rate. The MCF52235 includes a new debug signal, ALLPST. This signal is the logical ‘AND’ of the processor status (PST[3:0]) signals and is useful for detecting when the processor is in a halted state (PST[3:0] = 1111).

The full debug/trace interface is available only on the 112 and 121-pin packages. However, every product features the dedicated debug serial communication channel (DSI, DSO, DSCLK) and the ALLPST signal.

1.4.3

JTAG

The MCF52235 supports circuit board test strategies based on the Test Technology Committee of IEEE and the Joint Test Action Group (JTAG). The test logic includes a test access port (TAP) consisting of a

16-state controller, an instruction register, and three test registers (a 1-bit bypass register, a -bit boundary-scan register, and a 32-bit ID register). The boundary scan register links the device’s pins into one shift register. Test logic, implemented using static logic design, is independent of the device system logic.

The MCF52235 implementation can do the following:

• Perform boundary-scan operations to test circuit board electrical continuity

• Sample MCF52235 system pins during operation and transparently shift out the result in the boundary scan register

• Bypass the MCF52235 for a given circuit board test by effectively reducing the boundary-scan register to a single bit

• Disable the output drive to pins during circuit-board testing

• Drive output pins to stable levels

1.4.4

On-Chip Memories

1.4.4.1

SRAM

The dual-ported SRAM module provides a general-purpose 32-Kbyte memory block that the ColdFire core can access in a single cycle. The location of the memory block can be set to any 32-Kbyte boundary within the 4-Gbyte address space. This memory is ideal for storing critical code or data structures and for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can quickly service core-initiated accesses or memory-referencing commands from the debug module.

1-10



Preliminary

Overview

The SRAM module is also accessible by the DMA. The dual-ported nature of the SRAM makes it ideal for implementing applications with double-buffer schemes, where the processor and a DMA device operate in alternate regions of the SRAM to maximize system performance.

1.4.4.2

Flash

The ColdFire Flash module (CFM) is a non-volatile memory (NVM) module that connects to the processor’s high-speed local bus. The CFM is constructed with four banks of 32K x 16-bit Flash arrays to generate 256 Kbytes of 32-bit Flash memory. These arrays serve as electrically erasable and programmable, non-volatile program and data memory. The Flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring an external high voltage source. The CFM interfaces to the ColdFire core through an optimized read-only memory controller which supports interleaved accesses from the 2-cycle Flash arrays. A backdoor mapping of the

Flash memory is used for all program, erase, and verify operations, as well as providing a read datapath for the DMA. Flash memory may also be programmed via the EzPort, which is a serial Flash programming interface that allows the Flash to be read, erased and programmed by an external controller in a format compatible with most SPI bus Flash memory chips. This allows easy device programming via Automated

Test Equipment or bulk programming tools.

1.4.5

Cryptography Acceleration Unit

The MCF52235 device incorporates two hardware accelerators for cryptographic functions. First, the

CAU is a coprocessor tightly-coupled to the V2 ColdFire core that implements a set of specialized operations to increase the throughput of software-based encryption and message digest functions, specifically the DES, 3DES, AES, MD5 and SHA-1 algorithms. Second, a random number generator provides FIPS-140 compliant 32-bit values to security processing routines. Both modules supply critical acceleration to software-based cryptographic algorithms at a minimal hardware cost.

1.4.6


The MCF52235 incorporates several low power modes of operation which are entered under program control and exited by several external trigger events. An integrated power-on reset (POR) circuit monitors the input supply and forces an MCU reset as the supply voltage rises. The low voltage detector (LVD) monitors the supply voltage and is configurable to force a reset or interrupt condition if it falls below the

LVD trip point.

1.4.7

FlexCAN

The FlexCAN module is a communication controller implementing version 2.0 of the CAN protocol parts

A and B. The CAN protocol can be used as an industrial control serial data bus, meeting the specific requirements of reliable operation in a harsh EMI environment with high bandwidth. This instantiation of

FlexCAN has 16 message buffers.



Preliminary

1-11

Overview

1.4.8

UARTs

The MCF52235 has three full-duplex UARTs that function independently. The three UARTs can be clocked by the system bus clock, eliminating the need for an external clock source. On smaller packages, the third UART is multiplexed with other digital I/O functions.

1.4.9

I

2

C Bus

The I 2 C bus is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange and minimizes the interconnection between devices. This bus is suitable for applications requiring occasional communications over a short distance between many devices on a circuit board.

1.4.10

QSPI

The queued serial peripheral interface (QSPI) provides a synchronous serial peripheral interface with queued transfer capability. It allows up to 16 transfers to be queued at once, minimizing the need for CPU intervention between transfers.

1.4.11

Fast ADC

The Fast ADC consists of an eight-channel input select multiplexer and two independent sample and hold

(S/H) circuits feeding separate 12-bit ADCs. The two separate converters store their results in accessible buffers for further processing.

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform a programmed scan sequence repeatedly until manually stopped.

The ADC can be configured for either sequential or simultaneous conversion. When configured for sequential conversions, up to eight channels can be sampled and stored in any order specified by the channel list register. Both ADCs may be required during a scan, depending on the inputs to be sampled.

During a simultaneous conversion, both S/H circuits are used to capture two different channels at the same time. This configuration requires that a single channel may not be sampled by both S/H circuits simultaneously.

Optional interrupts can be generated at the end of the scan sequence if a channel is out of range (measures below the low threshold limit or above the high threshold limit set in the limit registers) or at several different zero crossing conditions.

1.4.12


There are four independent, DMA transfer capable 32-bit timers (DTIM0, DTIM1, DTIM2, and DTIM3) on the each device. Each module incorporates a 32-bit timer with a separate register set for configuration and control. The timers can be configured to operate from the system clock or from an external clock source using one of the DTINx signals. If the system clock is selected, it can be divided by 16 or 1. The input clock is further divided by a user-programmable 8-bit prescaler which clocks the actual timer counter register (TCRn). Each of these timers can be configured for input capture or reference (output) compare mode. Timer events may optionally cause interrupt requests or DMA transfers.

1-12



Preliminary

Overview

1.4.13

General Purpose Timer (GPT)

The general purpose timer (GPT) is a 4-channel timer module consisting of a 16-bit programmable counter driven by a 7-stage programmable prescaler. Each of the four channels can be configured for input capture or output compare. Additionally, one of the channels, channel 3, can be configured as a pulse accumulator.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. The input capture and output compare functions allow simultaneous input waveform measurements and output waveform generation. The input capture function can capture the time of a selected transition edge. The output compare function can generate output waveforms and timer software delays. The 16-bit pulse accumulator can operate as a simple event counter or a gated time accumulator.

1.4.14

Periodic Interrupt Timers (PIT0 and PIT1)

The two periodic interrupt timers (PIT0 and PIT1) are 16-bit timers that provide interrupts at regular intervals with minimal processor intervention. Each timer can either count down from the value written in its PIT modulus register, or it can be a free-running down-counter.

1.4.15

Pulse Width Modulation (PWM) Timers

The MCF52235 has an 8-channel, 8-bit PWM timer. Each channel has a programmable period and duty cycle as well as a dedicated counter. Each of the modulators can create independent continuous waveforms with software-selectable duty rates from 0% to 100%. The PWM outputs have programmable polarity, and can be programmed as left aligned outputs or center aligned outputs. For higher period and duty cycle resolution, each pair of adjacent channels ([7:6], [5:4], [3:2], and [1:0]) can be concatenated to form a single 16-bit channel. The module can thus be configured to support 8/0, 6/1, 4/2, 2/3, or 0/4 8-/16-bit channels.

1.4.16

Software Watchdog Timer

The watchdog timer is a 32-bit timer that facilitates recovery from runaway code. The watchdog counter is a free-running down-counter that generates a reset on underflow. To prevent a reset, software must periodically restart the countdown.

1.4.17

Phase Locked Loop (PLL)

The clock module contains a crystal oscillator, 8 MHz on-chip relaxation oscillator (OCO), phase-locked loop (PLL), reduced frequency divider (RFD), low-power divider status/control registers, and control logic. In order to improve noise immunity, the PLL, crystal oscillator, and relaxation oscillator have their own power supply inputs: VDDPLL and VSSPLL. All other circuits are powered by the normal supply pins, VDD and VSS.



Preliminary

1-13

Overview

1.4.18

Interrupt Controller (INTC0/INTC1)

There are two interrupt controllers on the MCF52235. These interrupt controllers are organized as seven levels with up to nine interrupt sources per level. Each interrupt source has a unique interrupt vector, and provide each peripheral with all necessary interrupts. Each internal interrupt has a programmable level

[1-7] and priority within the level. The seven external interrupts have fixed levels/priorities.

1.4.19

DMA Controller

The direct memory access (DMA) controller provides an efficient way to move blocks of data with minimal processor intervention. It has four channels that allow byte, word, longword, or 16-byte burst line transfers. These transfers are triggered by software explicitly setting a DCRn[START] bit or by the occurrence of certain UART or DMA timer events.

1.4.20

Reset

The reset controller determines the source of reset, asserts the appropriate reset signals to the system, and keeps track of what caused the last reset. There are seven sources of reset:

• External reset input

• Power-on reset (POR)

• Watchdog timer

• Phase locked-loop (PLL) loss of lock

• PLL loss of clock

• Software

• Low-voltage detector (LVD)

Control of the LVD and its associated reset and interrupt are handled by the reset controller. Other registers provide status flags indicating the last source of reset and a control bit for software assertion of the RSTO pin.

1.4.21

GPIO

Nearly all pins on the MCF52235 have general purpose I/O capability in addition to their primary functions, and are grouped into 8-bit ports. Some ports do not utilize all 8 bits. Each port has registers that configure, monitor, and control the port pins.

1-14



Preliminary


Chapter 2


2.1

Introduction

This chapter describes signals implemented on this device and includes an alphabetical listing of signals that characterizes each signal as an input or output, defines its state at reset, and identifies whether a pull-up resistor should be used.

NOTE

The terms ‘assertion’ and ‘negation’ are used to avoid confusion when dealing with a mixture of active-low and active-high signals. The term

‘asserted’ indicates that a signal is active, independent of the voltage level.

The term ‘negated’ indicates that a signal is inactive.

Active-low signals, such as SRAS and TA, are indicated with an overbar.

2.2

Overview

Figure 2-1

shows the block diagram of the device with the signal interface.



Preliminary

2-1


EPHY_TX

EPHY_RX

EzPD

EzPQ

EPHY

Fast

Ethernet

Controller

(FEC)

4 CH DMA

To/From PADI

JTAG_EN MUX

EzPort

Arbiter

EzPCK

EzPCS

Interrupt

Controller 1

Interrupt

Controller 2

UART

0

DTIM

0

UART

1

UART

2

DTIM

1

DTIM

2

I

2

C

DTIM

3

QSPI

RTC

V2 ColdFire CPU

IFP OEP CAU EMAC

AN[7:0]

JTAG

TAP

ADC

V

RH

V

RL

32 Kbytes

SRAM

(4Kx16)x4

256 Kbytes

Flash

(32Kx16)x4

PORTS

(GPIO)

PMM

CIM

ICOC n

QSPI_DIN,

QSPI_DOUT

QSPI_SCK,

QSPI_PCS n

I

2

C_SDA

I

2

C_SCL

U n TXD

U n RXD

U n RTS

U n CTS

DTIN n /DTOUT n

CANRX

CANTX

PWM n

RSTIN

RSTOUT

Edge

Port 1

PLL

CLKGEN

Edge

Port 2

EXTAL XTAL CLKOUT

To/From Interrupt Controller

RNGA

FlexCAN

PIT0

PIT1

GPT

PWM

Figure 2-1. Block Diagram with Signal Interfaces

Table 2-1

shows the pin functions by primary and alternate purpose, and illustrates which packages contain each pin.

2-2



Preliminary

Pin

Group

Primary

Function

ADC

Clock

Generation

Debug

Data

SYNCA

SYNCB

VDDA

VSSA

VRH

VRL

EXTAL

XTAL

AN3

AN2

AN1

AN0

AN7

AN6

AN5

AN4

VDDPLL

VSSPLL

ALLPST

DDATA[3:0]

PST[3:0]

—

—

—

—

—

—

—

—

CANTX

3

CANRX

3

—

—

—

—

—

—

—

—

—

—

Secondary

Function

—

Table 2-1. Pin Functions by Primary and Alternate Purpose

Tertiary

Function

FEC_MDIO

FEC_MDC

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

Quaternary

Function

Drive

Strength /

Control

1

Wired OR

Control

Pull-up /

Pull-down

2

Pin on121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

PDSR[39]

PDSR[39]

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

High

High

Low

Low

Low

Low

Low

Low

Low

Low

—

—

—

—

PAS[3]

PAS[2]

—

—

PAN[7]

PAN[6]

PAN[5]

PAN[4]

PAN[3]

PAN[2]

PAN[1]

PAN[0]

—

—

—

PDD[7:4]

—

—

—

—

—

—

—

—

—

—

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

PDD[3:0] High — — —

95

96

48

49

28

27

93

94

45

47

7

12,13,

16,17

80,79,

78,77

89

90

91

92

88

87

86

85

70

71

36

37

20

19

69

72

33

35

7

—

65

66

67

68

64

63

62

61

—

Notes

Pin

Group

Primary

Function

Ethernet

LEDs

Ethernet

PHY

I

2

C

ACTLED

COLLED

DUPLED

LNKLED

SPDLED

RXLED

TXLED

PHY_RBIAS

PHY_RXN

PHY_RXP

PHY_TXN

PHY_TXP

PHY_VDDA

PHY_VDDRX

PHY_VDDTX

PHY_VSSA

PHY_VSSRX

PHY_VSSTX

SCL

SDA

—

—

—

—

—

—

—

—

—

—

CANTX

3

CANRX

3

—

—

—

—

—

—

—

—

Secondary

Function

—

—

—

—

—

—

—

—

—

—

TXD2

RXD2

—

—

—

—

—

—

—

—

Tertiary

Function

Quaternary

Function

Drive

Strength /

Control

1

Wired OR

Control

Pull-up /

Pull-down

2

Pin on121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

—

—

—

—

—

—

—

—

PLD[0]

PLD[4]

PLD[3]

PLD[1]

PLD[2]

PLD[5]

PLD[6]

—

—

—

PAS[0]

PAS[1]

PDSR[32] PWOR[8]

PDSR[36] PWOR[12]

PDSR[35] PWOR[11]

PDSR[33] PWOR[9]

PDSR[34] PWOR[10]

PDSR[37] PWOR[13]

PDSR[38] PWOR[14]

— —

—

—

—

—

PDSR[0]

PDSR[0]

N/A

N/A

—

—

N/A

N/A

N/A

N/A

—

—

—

—

—

—

—

—

—

—

— pull-up pull-up

4

4

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

68

75

69

67

74

73

71

70

76

72

111

112

81

52

51

66

84

58

59

83

48

55

49

47

54

53

51

50

56

52

79

80

57

—

—

46

60

42

43

59

Notes

Pin

Group

Primary

Function

Interrupts

JTAG/BDM

Mode

Selection

IRQ7

IRQ6

IRQ5

IRQ4

IRQ3

IRQ2

IRQ1

JTAG_EN

TCLK/

PSTCLK

TDI/DSI

TDO/DSO

TMS

/BKPT

TRST

/DSCLK

RCON/

EZPCS

IRQ15

IRQ14

IRQ13

IRQ12

IRQ11

IRQ10

IRQ9

IRQ8

Secondary

Function

—

—

—

—

—

—

—

—

—

—

—

—

—

—

SYNCA

—

CLKOUT

Tertiary

Function

—

—

—

—

—

—

—

—

—

FEC_RXER

FEC_RXD[1]

—

FEC_RXD[2]

FEC_RXD[3]

PWM1

—

—

Quaternary

Function

Drive

Strength /

Control

1

Wired OR

Control

Pull-up /

Pull-down

2

Pin on121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

PGP[7]

PGP[6]

PGP[5]

PGP[4]

PGP[3]

PGP[2]

PGP[1]

PGP[0]

PNQ[7]

PNQ[6]

PNQ[5]

PNQ[4]

PNQ[3]

PNQ[2]

PNQ[1]

—

—

PSDR[47]

PSDR[46]

PSDR[45]

PSDR[44]

PSDR[43]

PSDR[42]

PSDR[41]

PSDR[40]

Low

Low

Low

Low

Low

Low

High

N/A

High

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

N/A

— pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-up

4 pull-down pull-up

5

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

106

105

98

97

57

29

11

10

56

19

20

41

53

54

55

18

1

—

—

—

—

—

—

—

—

40

—

—

29

—

—

39

12

1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

N/A

High

N/A

N/A

N/A

N/A

N/A

N/A

N/A

N/A pull-up

—

5 pull-up

5 pull-up pull-up

5

—

—

—

—

—

4

5

2

6

3

4

5

2

6

3

Notes

Pin

Group

Primary

Function

Secondary

Function

PWM

QSPI

Reset

7

Test

Timers,

16-bit

Timers,

32-bit

PWM7

PWM5

PWM3

PWM1

QSPI_DIN/

EZPD

QSPI_DOUT/

EZPQ

QSPI_SCK/

EZPCK

QSPI_CS3

QSPI_CS2

QSPI_CS1

QSPI_CS0

RSTI

RSTO

TEST

GPT3

—

—

—

—

CANRX

3

CANTX

SCL

3

SYNCA

—

—

SDA

—

—

—

FEC_TXD[3]

GPT2

GPT1

GPT0

TIN3

TIN2

TIN1

TIN0

FEC_TXD[2]

FEC_TXD[1]

FEC_TXER

TOUT3

TOUT2

TOUT1

TOUT0

Tertiary

Function

—

—

—

—

RXD1

Quaternary

Function

Drive

Strength /

Control

1

Wired OR

Control

Pull-up /

Pull-down

2

Pin on121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

PTD[3]

PTD[2]

PTD[1]

PTD[0]

PQS[1]

PDSR[31]

PDSR[30]

PDSR[29]

PDSR[28]

—

—

—

—

PDSR[2] PWOR[4]

—

—

—

—

—

—

—

—

—

—

104

103

100

99

34

—

—

—

—

25

TXD1

RTS1

SYNCB

—

—

CTS1

—

—

—

PWM7

PWM5

PWM3

PWM1

PWM6

PWM4

PWM2

PWM0

PQS[0]

PQS[2]

PQS[6]

PQS[5]

PQS[4]

PQS[3]

—

—

—

PTA[3]

PTA[2]

PTA[1]

PTA[0]

PTC[3]

PTC[2]

PTC[1]

PTC[0]

PDSR[1]

PDSR[3]

PDSR[7]

PDSR[6]

PWOR[5]

PWOR[6]

PDSR[5] —

PDSR[4] PWOR[7]

N/A high

N/A

PDSR[23]

PDSR[22]

PDSR[21]

PDSR[20]

PDSR[19]

PDSR[18]

PDSR[17]

PDSR[16]

—

—

N/A

—

N/A

—

—

—

—

—

—

—

—

— pull-up

—

—

6

— pull-up

6 pull-up

7

— pull-down pull-up

8 pull-up

8 pull-up

8 pull-up

8

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

35

36

40

39

38

37

44

46

50

107

108

109

110

22

21

9

8

26

27

13

9

8

76

77

78

14

32

34

38

75

—

—

—

58

Notes

Pin

Group

Primary

Function

Secondary

Function

Tertiary

Function

Quaternary

Function

Drive

Strength /

Control

1

Wired OR

Control

Pull-up /

Pull-down

2

Pin on121

MAPBGA

Pin on 112

LQFP

Pin on 80

LQFP

Notes

UART 0

UART 1

CTS0

RTS0

RXD0

TXD0

CTS1

RTS1

RXD1

TXD1

CANRX

CANTX

—

—

SYNCA

SYNCB

—

—

3

3

FEC_RXCLK

FEC_RXDV

FEC_RXD[0]

FEC_CRS

RXD2

TXD2

FEC_TXD[0]

FEC_COL

PUA[3]

PUA[2]

PUA[1]

PUA[0]

PUB[3]

PUB[2]

PUB[1]

PUB[0]

PDSR[11]

PDSR[10]

PDSR[9]

PDSR[8]

PDSR[15]

PDSR[14]

PDSR[13]

PDSR[12]

—

—

PWOR[0]

PWOR[1]

—

—

PWOR[2]

PWOR[3]

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

26

25

30

31

24

23

32

33

18

17

21

22

16

15

23

24

UART 2 CTS2

RTS2

—

—

—

—

PUC[3]

PUC[2]

PDSR[27]

PDSR[26]

—

—

—

—

—

—

61

60

—

—

FlexCAN

RXD2

TXD2

SYNCA

SYNCB

—

—

CANTX

9

CANRX

3

—

—

—

FEC_MDIO

FEC_MDC

PUC[1]

PUC[30]

PAS[3]

PAS[2]

PDSR[25]

PDSR[24]

PDSR[39]

PDSR[39]

—

—

—

—

—

—

—

—

—

—

—

—

62

63

—

—

—

—

—

—

See Note

See Note

3

3

VDD

10

VDD — — N/A N/A — 14,43,65,

82,102

10,31,45,

58,74

VSS VSS — — — N/A N/A — 15,42,

64,101

11,30,

44,73

2

3

4

5

6

7

8

9

1

10

The PDSR and PSSR registers are described in Chapter 14, “General Purpose I/O Module . All programmable signals default to 2mA drive in normal (single-chip)

mode.

All signals have a pull-up in GPIO mode.

The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.

For primary and GPIO functions only.

Only when JTAG mode is enabled.

For secondary and GPIO functions only.

RSTI has an internal pull-up resistor, however the use of an external resistor is very strongly recommended

For GPIO function. Primary Function has pull-up control within the GPT module

The multiplexed CANTX and CANRX signals do not have dedicated pins, but are available as muxed replacements for other signals.

This list for power and ground does not include those dedicated power/ground pins included elsewhere, e.g. in the ethernet PHY.


2.3

Reset Signals

Table 2-2

describes signals that are used to either reset the chip or as a reset indication.

Table 2-2. Reset Signals

Signal Name

Reset In

Reset Out

Abbreviation

RSTI

RSTO

Function

Primary reset input to the device. Asserting RSTI immediately resets the CPU and peripherals.

Driven low for 512 CPU clocks after the reset source has deasserted and PLL locked.

I/O

I

O

2.4

PLL and Clock Signals

Table 2-3

describes signals that are used to support the on-chip clock generation circuitry.

Table 2-3. PLL and Clock Signals

Signal Name

External Clock In

Crystal

Clock Out

Abbreviation Function

EXTAL

XTAL

Crystal oscillator or external clock input.

Crystal oscillator output.

CLKOUT This output signal reflects the internal system clock.

I/O

I

O

O

2.5

Mode Selection

Table 2-4

describes signals used in mode selection, Table 2-5 describes particular clocking modes.

Table 2-4. Mode Selection Signals

Signal Name

Reset Configuration

Test

Abbreviation

RCON

TEST

Function

The serial Flash programming mode is entered by asserting the

RCON pin (with the TEST pin negated) as the chip comes out of reset. During this mode, the EzPort has access to the Flash memory which can be programmed from an external device.

Reserved for factory testing only and in normal modes of operation should be connected to VSS to prevent unintentional activation of test functions.

I/O

I

2.6

External Interrupt Signals

Table 2-5

describes the external interrupt signals.

Table 2-5. External Interrupt Signals

Signal Name

External Interrupts

Abbreviation

IRQ[15:1] External interrupt sources.

Function I/O

I

2-8



Preliminary


2.7


Table 2-6

describes the QSPI signals.

Table 2-6. Queued Serial Peripheral Interface (QSPI) Signals

Signal Name Abbreviation Function

QSPI Synchronous

Serial Output

QSPI Synchronous

Serial Data Input

QSPI Serial Clock

QSPI_DOUT Provides the serial data from the QSPI and can be programmed to be driven on the rising or falling edge of QSPI_CLK.

QSPI_DIN Provides the serial data to the QSPI and can be programmed to be sampled on the rising or falling edge of QSPI_CLK.

QSPI_CLK Provides the serial clock from the QSPI. The polarity and phase of

QSPI_CLK are programmable.

Synchronous Peripheral

Chip Selects

QSPI_CS[3:0] QSPI peripheral chip selects that can be programmed to be active high or low.

I/O

O

I

O

O



Preliminary

2-9


2.8

Fast Ethernet Controller PHY Signals

Table 7

describes the Fast Ethernet Controller (FEC) Signals.

Table 7. Fast Ethernet Controller (FEC) Signals

Signal Name

Twisted Pair Input +

Twisted Pair Input -

Twisted Pair Output +

Twisted Pair Output -

Bias Control Resistor

Activity LED

Link LED

Speed LED

Duplex LED

Collision LED

Transmit LED

Receive LED


RXP

RXN

TXN

Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset.

Differential Ethernet twisted-pair input pin. This pin is high-impedance out of reset.

Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset.

TXP

RBIAS

Differential Ethernet twisted-pair output pin. This pin is high-impedance out of reset.

Connect a 12.4 k

Ω

(1.0%) external resistor, RBIAS, between the

PHY_RBIAS pin and analog ground.

Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF

(>50 pF will cause instability). No high-speed signals can be permitted in the region of RBIAS.

ACT_LED Indicates when the EPHY is transmitting or receiving

LINK_LED Indicates when the EPHY has a valid link

SPD_LED Indicates the speed of the EPHY connection

DUPLED Indicates the duplex (full or half) of the EPHY connection

COLLED Indicates if the EPHY detects a collision

TXLED Indicates if the EPHY is transmitting

RXLED Indicates if the EPHY is receiving

I/O

I

I

I

O

O

O

O

O

O

O

O

O

2.9

I

2

C I/O Signals

Table 2-8

describes the I

2

C serial interface module signals.

Table 2-8. I

2

C I/O Signals

Signal Name

Serial Clock

Serial Data

Abbreviation

SCL

SDA

Function

Open-drain clock signal for the for the I

2

C interface. Either it is driven by the I

2

C module when the bus is in master mode or it becomes the clock input when the I

2

C is in slave mode.

Open-drain signal that serves as the data input/output for the I

2

C interface.

I/O

I/O

I/O

2-10



Preliminary


2.10

UART Module Signals

Table 2-9

describes the UART module signals.

Table 2-9. UART Module Signals

Signal Name

Transmit Serial Data Output

Abbreviation

UTXD n

Receive Serial Data Input

Clear-to-Send

Request-to-Send

URXD

UCTS

URTS n n n

Function I/O

Transmitter serial data outputs for the UART modules. The output is held high (mark condition) when the transmitter is disabled, idle, or in the local loopback mode. Data is shifted out, LSB first, on this pin at the falling edge of the serial clock source.

Receiver serial data inputs for the UART modules. Data is received on this pin LSB first. When the UART clock is stopped for power-down mode, any transition on this pin restarts it.

O

I

Indicate to the UART modules that they can begin data transmission.

I

Automatic request-to-send outputs from the UART modules. This signal can also be configured to be asserted and negated as a function of the RxFIFO level.

O

2.11 DMA Timer Signals

Table 2-10

describes the signals of the four DMA timer modules.

Table 2-10. DMA Timer Signals

Signal Name

DMA Timer Input

DMA Timer Output

Abbreviation

DTIN

DTOUT

Function

Event input to the DMA timer modules.

Programmable output from the DMA timer modules.

2.12 ADC Signals

Table 2-11 describes the signals of the analog-to-digital converter.

Table 2-11. ADC Signals

Signal Name

Analog Inputs

Analog Reference

Analog Supply

Abbreviation

AN[7:0]

V

RH

V

RL

V

DDA

V

SSA

Function

Inputs to the A-to-D converter.

Reference voltage high and low inputs.

Isolate the ADC circuitry from power supply noise

I/O

I

I

I

—

—

I/O

I

O



Preliminary

2-11


2.13 General Purpose Timer Signals

Table 2-12

describes the general purpose timer signals.

Table 2-12. GPT Signals

Signal Name

General Purpose Timer

Input/Output

Abbreviation

GPT[3:0]

Function

Inputs to or outputs from the general purpose timer module

2.14 Pulse Width Modulator Signals

Table 2-13

describes the PWM signals.

Table 2-13. PWM Signals

Signal Name

PWM Output Channels

Abbreviation

PWM[7:0]

Function

Pulse width modulated output for PWM channels

I/O

I/O

I/O

O

2.15 Debug Support Signals

The signals in

Table 2-14

are used as the interface to the on-chip JTAG controller and also to interface to the BDM logic.

Table 2-14. Debug Support Signals

Signal Name

JTAG Enable

Test Reset

Test Clock

Test Mode Select

Test Data Input

Test Data Output

Development Serial

Clock

Breakpoint


JTAG_EN Select between debug module and JTAG signals at reset

TRST This active-low signal is used to initialize the JTAG logic asynchronously.

TCLK

TMS

TDI

Used to synchronize the JTAG logic.

Used to sequence the JTAG state machine. TMS is sampled on the rising edge of TCLK.

Serial input for test instructions and data. TDI is sampled on the rising edge of TCLK.

TDO

DSCLK

BKPT

Serial output for test instructions and data. TDO is three-stateable and is actively driven in the shift-IR and shift-DR controller states. TDO changes on the falling edge of TCLK.

Development Serial Clock. Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising bus clock edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is PSTCLK/5. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

Breakpoint. Input used to request a manual breakpoint. Assertion of

BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals () as the value 0xF.

I

I

I/O

I

I

I

I

I

O

2-12



Preliminary


Table 2-14. Debug Support Signals (continued)

Signal Name Abbreviation Function

Development Serial

Input

Development Serial

Output

Debug Data

Processor Status Clock

Processor Status

Outputs

All Processor Status

Outputs

DSI

DSO

Development Serial Input. Internally synchronized input that provides data input for the serial communication port to the debug module, once the DSCLK has been seen as high (logic 1).

Development Serial Output. Provides serial output communication for debug module responses. DSO is registered internally. The output is delayed from the validation of DSCLK high.

DDATA[3:0] Debug data. Displays captured processor data and breakpoint status.

The CLKOUT signal can be used by the development system to know when to sample DDATA[3:0].

PSTCLK Processor Status Clock. Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA output.

PSTCLK indicates when the development system should sample PST and DDATA values.

If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, and

PST and DDATA outputs from toggling without disabling triggers.

Non-quiescent operation can be reenabled by clearing CSR[PCD], although the external development systems must resynchronize with the PST and DDATA outputs.

PSTCLK starts clocking only when the first non-zero PST value (0xC,

0xD, or 0xF) occurs during system reset exception processing.

PST[3:0] Indicate core status. Debug mode timing is synchronous with the processor clock; status is unrelated to the current bus transfer. The

CLKOUT signal can be used by the development system to know when to sample PST[3:0].

ALLPST Logical “AND” of PST[3.0]

I/O

I

O

O

O

O

O

2.16 EzPort Signal Descriptions

Table 2-15

contains a list of EzPort external signals

Table 2-15. EzPort Signal Descriptions

Signal Name

EzPort Clock

EzPort Chip Select

EzPort Serial Data In

EzPort Serial Data Out

Abbreviation

EZPCK

EZPCS

EZPD

EZPQ

Function

Shift clock for EzPort transfers

Chip select for signaling the start and end of serial transfers

EZPD is sampled on the rising edge of EZPCK

EZPQ transitions on the falling edge of EZPCK

I/O

I

I

I

O



Preliminary

2-13


2.17 Power and Ground Pins

The pins described in Table 2-16 provide system power and ground to the chip. Multiple pins are provided

for adequate current capability. All power supply pins must have adequate decoupling (bypass capacitance) for high-frequency noise suppression.

Table 2-16. Power and Ground Pins

Signal Name

PLL Analog Supply

Positive Supply

Ground

Abbreviation

VDDPLL,

VSSPLL

VDD

VSS

Function

Dedicated power supply signals to isolate the sensitive PLL analog circuitry from the normal levels of noise present on the digital power supply.

These pins supply positive power to the core logic.

This pin is the negative supply (ground) to the chip.

I/O

I

I

Some of the V

DD

and V

SS

pins on the device are only to be used for noise bypass. Figure 2 shows a typical

connection diagram. Pay particular attention to those pins which show only capacitor connections. Do not connect power supply voltage directly to these pins unless the desire is to send the device into a slow but certain death spiral.

2-14



Preliminary


MCF52235

Pin numbering is shown for the 80-lead TQFP

45

44

74

73

10

31

30

71

72

58

11

33

35

69

70

V

DD

PLL

V

SS

PLL

V

DDA

V

RH

V

RL

V

SSA

V

DDR

V

SSX1

V

DDX1

V

DDX2

V

SSX2

V

DD2

V

SS2

V

DD1

V

SS1

0.22µF 1000pF

0.1µF

0.1µF

*

10µH

10µF

10V

Tantalum

0.1µF

0.1µF

0.1µF

0.22µF

3.3V

0.22µF

12.4K

Ω

1%

0.22µF 0.22µF 0.22µF

*

optional

Figure 2. Suggested connection scheme for Power and Ground



Preliminary

2-15


2-16



Preliminary

Chapter 3

ColdFire Core

This section describes the organization of the Version 2 (V2) ColdFire

®

processor core and an overview of the program-visible registers. For detailed information on instructions, see the ISA_A+ definition in the

ColdFire Family Programmer’s Reference Manual .

3.1

Processor Pipelines

Figure 3-1

is a block diagram showing the processor pipelines of a V2 ColdFire core.

Instruction

Fetch

Pipeline

IAG

IC

Instruction

Address

Generation

Instruction

Fetch Cycle

Address [31:0]

IB

FIFO

Instruction Buffer

Data[31:0]

Operand

Execution

Pipeline

DSOC

Decode & Select,

Operand Fetch

AGEX

Address

Generation,

Execute

Figure 3-1. V2 ColdFire Core Pipelines

As with all ColdFire cores, the V2 ColdFire core is comprised of two separate pipelines that are decoupled by an instruction buffer.

The instruction fetch pipeline (IFP) is a two-stage pipeline for prefetching instructions. The prefetched instruction stream is then gated into the two-stage operand execution pipeline (OEP), which decodes the



Preliminary

3-1

ColdFire Core instruction, fetches the required operands and then executes the required function. Since the IFP and OEP pipelines are decoupled by an instruction buffer which serves as a FIFO queue, the IFP is able to prefetch instructions in advance of their actual use by the OEP thereby minimizing time stalled waiting for instructions.

The V2 ColdFire core pipeline stages include the following:

• Two-stage instruction fetch pipeline (IFP) (plus instruction buffer stage)

— Instruction address generation (IAG)—Calculates the next prefetch address

— Instruction fetch cycle (IC)—Initiates prefetch on the processor’s local bus

— Instruction buffer (IB)—Buffer stage minimizes effects of fetch latency using FIFO queue

• Two-stage operand execution pipeline (OEP)

— Decode and select/operand fetch cycle (DSOC)—Decodes instructions and fetches the required components for effective address calculation, or the operand fetch cycle

— Address generation/execute cycle (AGEX)—Calculates operand address or executes the instruction

When the instruction buffer is empty, opcodes are loaded directly from the IC cycle into the operand execution pipeline. If the buffer is not empty, the IFP stores the contents of the fetch cycle in the IB until it is required by the OEP.

For register-to-register and register-to-memory store operations, the instruction passes through both OEP stages once. For memory-to-register and read-modify-write memory operations, an instruction is effectively staged through the OEP twice: the first time to calculate the effective address and initiate the operand fetch on the processor’s local bus, and the second time to complete the operand reference and perform the required function defined by the instruction.

The resulting pipeline and local bus structure allows the V2 ColdFire core to deliver sustained high performance across a variety of demanding embedded applications.

3.2

Memory Map/Register Description

The following sections describe the processor registers in the user and supervisor programming models.

The appropriate programming model is selected based on the privilege level (user mode or supervisor mode) of the processor as defined by the S bit of the status register (SR).

Table 3-1 lists the processor

registers.

The user programming model is the same as the M68000 family microprocessors, consisting of the following registers:

• 16 general-purpose 32-bit registers (D0–D7, A0–A7)

• 32-bit program counter (PC)

• 8-bit condition code register (CCR)

The supervisor programming model is intended to be used only by system control software to implement restricted operating system functions, I/O control, and memory management. All accesses that affect the control features of ColdFire processors are in the supervisor programming model, which consists of registers available in user mode as well as the following control registers:

3-2



Preliminary

ColdFire Core

• 16-bit status register (SR)

• 32-bit supervisor stack pointer (SSP)

• 32-bit vector base register (VBR)

• Two 32-bit memory base address registers (RAMBAR, FLASHBAR)

Table 3-1. ColdFire Core Programming Model

DRc[4–0]

1

Register

Width

(bits)

Access Reset Value

Written with

MOVEC

Section/Page

Supervisor/User Access Registers

32 R/W 0xCF20_6089 Load: 0x080

Store: 0x180

Load: 0x081

Store: 0x181

Data Register 0 (D0)

Data Register 1 (D1)

Load: 0x082–7

Store: 0x182–7

Data Register 2–7 (D2–D7)

Load: 0x088–8E

Store: 0x188–8E

Address Register 0–6 (A0–A6)

Load: 0x08F

Store: 0x18F

Supervisor/User A7 Stack Pointer (A7)

0x804

0x805

0x806, 0x809,

0x80A, 0x80B

0x807

MAC Status Register (MACSR)

MAC Address Mask Register (MASK)

MAC Accumulators 0–3 (ACC0–3)

0x808

0x80E

0x80F

MAC Accumulator 0,1 Extension Bytes

(ACCext01)

MAC Accumulator 2,3 Extension Bytes

(ACCext23)

Condition Code Register (CCR)

Program Counter (PC)

32

32

32

32

32

32

32

32

32

8

32

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x10A0_1070

Undefined

Undefined

Undefined

0x0000_0000

0xFFFF_FFFF

Undefined

Undefined

Undefined

Undefined

Undefined

No

No

No

No

No

No

No

No

No

No

No

Yes

3.2.1/3-4

3.2.1/3-4

3.2.1/3-4

3.2.2/3-4

3.2.3/3-4

3.2.4/3-5

3.2.4/3-5

3.2.4/3-5

3.2.4/3-5

3.2.4/3-5

3.2.5/3-5

3.2.6/3-6

Supervisor Access Only Registers

0x800

0x801

0x80E

0xC04

User/Supervisor A7 Stack Pointer (OTHER_A7)

Vector Base Register (VBR)

Status Register (SR)

Flash Base Address Register (FLASHBAR)

32

32

16

32

R/W

R/W

R/W

R/W

Undefined

0x0000_0000

0x27--

0x0000_0000

No

Yes

No

Yes

3.2.3/3-4

3.2.7/3-6

3.2.8/3-7

3.2.9/3-8

0xC05 RAM Base Address Register (RAMBAR) 32 R/W 0x0000_0000 Yes

3.2.9/3-8

1

The addresses listed in this column represent the value of the DRc field used when accessing the core registers via the BDM port.

For more information see Chapter 31, “Debug Module.”



Preliminary

3-3

ColdFire Core

3.2.1

Data Registers (D0–D7)

Registers D0–D7 are used as data registers for bit (1-bit), byte (8-bit), word (16-bit) and longword (32-bit) operations; they can also be used as index registers.

NOTE

Registers D0 and D1 contain hardware configuration details after reset. See

Section 3.6.14, “Reset Exception ,

” for more details.

DRc[4:0]: Load: 0x080 + n; n = 0-7 (D n )

Store: 0x180 + n; n = 0-7 (D n )

Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

Data

Reset

(D2-D7)

– – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Reset

(D0, D1)

See Section 3.6.14, “Reset Exception”

Figure 3-2. Data Registers (D0–D7)

3.2.2

Address Registers (A0–A6)

These registers can be used as software stack pointers, index registers, or base address registers; they can also be used for word and longword operations.

DRc[4:0]: Load: 0x088 + n; n = 0–6 (A n )

Store: 0x188 + n; n = 0–6 (A n )


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 3-3. Address Registers (A0–A6)

3.2.3

Supervisor/User Stack Pointers (A7 and OTHER_A7)

This ColdFire architecture supports two independent stack pointer (A7) registers—the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible 32-bit registers does not identify one as the SSP and the other as the USP. Instead, the hardware uses one 32-bit register as the active A7 and the other as OTHER_A7. Thus, the register contents are a function of the processor operation mode, as shown in the following: if SR[S] = 1 then else

A7 = Supervisor Stack Pointer

OTHER_A7 = User Stack Pointer

A7 = User Stack Pointer

OTHER_A7 = Supervisor Stack Pointer

3-4



Preliminary

ColdFire Core

The BDM programming model supports direct reads and writes to A7 and OTHER_A7. It is the responsibility of the external development system to determine, based on the setting of SR[S], the mapping of A7 and OTHER_A7 to the two program-visible definitions (SSP and USP).

To support dual stack pointers, the following two supervisor instructions are included in the ColdFire instruction set architecture to load/store the USP: move.l Ay, USP; move to USP move.l USP, Ax; move from USP

These instructions are described in the ColdFire Family Programmer’s Reference Manual .

NOTE

The USP must be initialized using the mov.l Ay,USP

instruction before any entry into user mode.

DRc[4:0]: Load: 0x08F (A7)

Store: 0x18F (A7)

0x800 (OTHER_A7)

Access: A7: User read/write

OTHER_A7: Supervisor read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

Address

W

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 3-4. Stack Pointer Registers (A7 and OTHER_A7)

3.2.4

EMAC Register Description

The registers in the EMAC portion of the user programming model, are described in Chapter 4, “Enhanced

Multiply-Accumulate Unit (EMAC),”

and include the following registers:

• Four 48-bit accumulator registers partitioned as follows:

— Four 32-bit accumulators (ACC0–ACC3)

— Eight 8-bit accumulator extension bytes (two per accumulator). These are grouped into two

32-bit values for load and store operations (ACCEXT01 and ACCEXT23).

Accumulators and extension bytes can be loaded, copied, and stored, and results from EMAC arithmetic operations generally affect the entire 48-bit destination.

• Eight 8-bit accumulator extensions (two per accumulator), packaged as two 32-bit values for load and store operations (ACCext01 and ACCext23)

• One 16-bit mask register (MASK)

• One 32-bit status register (MACSR) including four indicator bits signaling product or accumulation overflow (one for each accumulator: PAV0–PAV3)

3.2.5

Condition Code Register (CCR)

The CCR is the LSB of the processor status register (SR). Bits 4–0 act as indicator flags for results generated by processor operations. The extend bit (X) is also used as an input operand during multiprecision arithmetic computations.



Preliminary

3-5

ColdFire Core

DRc[4:0]: LSB of Status Register (SR)

7

0

6

0 R

W

Reset: 0 0

5

0

4

X

3

N

2

Z

0 — —

Figure 3-5. Condition Code Register (CCR)

—

Access: User read-only

1

V

0

C

— —

Field

2

Z

1

V

7–5

4

X

3

N

0

C

Table 3-2. CCR Field Descriptions

Description

Reserved, should be cleared.

Extend condition code bit. Set to the value of the C-bit for arithmetic operations; otherwise not affected or set to a specified result.

Negative condition code bit. Set if the most significant bit of the result is set; otherwise cleared.

Zero condition code bit. Set if the result equals zero; otherwise cleared.

Overflow condition code bit. Set if an arithmetic overflow occurs implying that the result cannot be represented in the operand size; otherwise cleared.

Carry condition code bit. Set if a carry out of the operand msb occurs for an addition, or if a borrow occurs in a subtraction; otherwise cleared

Set to the value of the C bit for arithmetic operations; otherwise not affected.

3.2.6

Program Counter (PC)

The PC contains the address of the currently executing instruction. During instruction execution and exception processing, the processor automatically increments the contents of the PC or places a new value in the PC, as appropriate. The PC is used as a base address for PC-relative operand addressing.

DRc[4:0]: 0x80F (PC) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 3-6. Program Counter Register (PC)

3.2.7

Vector Base Register (VBR)

The VBR contains the base address of the exception vector table in memory. To access the vector table, the displacement of an exception vector is added to the value in VBR. The lower 20 bits of the VBR are not implemented by ColdFire processors; they are assumed to be zero, forcing the table to be aligned on a

1 MByte boundary.

3-6



Preliminary

ColdFire Core

DRc[4:0]: 0x801 (VBR) Access: Supervisor read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

Base Address

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 3-7. Vector Base Register (VBR)

3.2.8

Status Register (SR)

The SR stores the processor status and includes the CCR, the interrupt priority mask, and other control bits. In supervisor mode, software can access the entire SR. In user mode, only the lower 8 bits are accessible (CCR). The control bits indicate the following states for the processor: trace mode (T bit), supervisor or user mode (S bit), and master or interrupt state (M bit). All defined bits in the SR have read/write access when in supervisor mode. The SR register must be explicitly loaded after reset and before any compare, Bcc, or Scc instructions are executed.

DRc[4:0]: 0x80E (SR)

15

R

W

T

Reset 0

14

0

0

13

S

1

System Byte

12 11

0

M

0

10 9

I

8 7

0

6

0

0 1 1 1 0 0

Figure 3-8. Status Register (SR)

Access: Supervisor read/write

Condition Code Register (CCR)

5

0

4

X

3

N

2

Z

1

V

0

C

0 — — — — —

Field

11

10–8

I

7–5

4–0

CCR

15

T

14

13

S

12

M

Table 3-3. SR Field Descriptions

Description

Trace enable. When set, the processor performs a trace exception after every instruction.


Supervisor/user state. Denotes whether the processor is in supervisor mode (S = 1) or user mode (S = 0).

Master/interrupt state. This bit is cleared by an interrupt exception, and can be set by software during execution of the RTE or move to SR instructions.


Interrupt level mask. Defines the current interrupt level. Interrupt requests are inhibited for all priority levels less than or equal to the current level, except the edge-sensitive level 7 request, which cannot be masked.


Refer to

Table 3-2 .



Preliminary

3-7

ColdFire Core

3.2.9

Memory Base Address Registers (RAMBAR, FLASHBAR)

The memory base address registers are used to specify the base address of the internal SRAM and Flash modules and indicate the types of references mapped to each. Each base address register includes a base address, write-protect bit, address space mask bits, and an enable bit. FLASHBAR determines the base address of the on-chip Flash, and RAMBAR determines the base address of the on-chip RAM. For more information, refer to

Section 11.2.1, “SRAM Base Address Register (RAMBAR).”

3.3

Instruction Set Architecture (ISA_A+)

The original ColdFire instruction set architecture (ISA) was derived from the M68000-family opcodes based on extensive analysis of embedded application code. After the initial ColdFire compilers were created, developers identified ISA additions that would enhance both code density and overall performance. Additionally, as users implemented ColdFire-based designs into a wide range of embedded systems, they identified frequently used instruction sequences that could be improved by the creation of new instructions. This observation was especially prevalent in development environments that made use of substantial amounts of assembly language code.

Table 3-4

summarizes the instructions added to revision ISA_A to form revision ISA_A+. For more details see the ColdFire Family Programmer’s Reference Manual .

Table 3-4. Instruction Enhancements over Revision ISA_A

Instruction Description

BITREV

BYTEREV

The contents of the destination data register are bit-reversed; that is, new Dn[31] = old Dn[0], new Dn[30] = old Dn[1], ..., new Dn[0] = old Dn[31].

The contents of the destination data register are byte-reversed; that is, new Dn[31:24] = old

Dn[7:0], ..., new Dn[7:0] = old Dn[31:24].

FF1 The data register, Dn, is scanned, beginning from the most-significant bit (Dn[31]) and ending with the least-significant bit (Dn[0]), searching for the first set bit. The data register is then loaded with the offset count from bit 31 where the first set bit appears.

MOVE FROM

USP

USP

→

Destination

MOVE TO USP Source

→

USP

STLDSR Pushes the contents of the status register onto the stack and then reloads the status register with the immediate data value.

3.4

Exception Processing Overview

Exception processing for ColdFire processors is streamlined for performance. The ColdFire processors differ from the M68000 family in that they include:

• A simplified exception vector table

• Reduced relocation capabilities using the vector base register

• A single exception stack frame format

• Use of a single self-aligning stack pointer (for ISA_A implementations only)

3-8



Preliminary

ColdFire Core

All ColdFire processors use an instruction restart exception model. However, Version 2 ColdFire

processors require more software support to recover from certain access errors. See Section 3.6.1, “Access

Error Exception

” for details.

Exception processing includes all actions from the detection of the fault condition to the initiation of fetch for the first handler instruction. Exception processing is comprised of four major steps.

First, the processor makes an internal copy of the SR and then enters supervisor mode by setting the S bit and disabling trace mode by clearing the T bit. The occurrence of an interrupt exception also forces the M bit to be cleared and the interrupt priority mask to be set to the level of the current interrupt request.

Second, the processor determines the exception vector number. For all faults except interrupts, the processor performs this calculation based on the exception type. For interrupts, the processor performs an interrupt-acknowledge (IACK) bus cycle to obtain the vector number from the interrupt controller. The

IACK cycle is mapped to a special acknowledge address space with the interrupt level encoded in the address.

Third, the processor saves the current context by creating an exception stack frame on the system stack.

Processors implementing ISA_A support a single stack pointer in the A7 address register; therefore, there is not notion of separate supervisor and user stack pointer. As a result, the exception stack frame is created at a 0-modulo-4 address on top of the current system stack. For processors implementing all other ISA revisions and supporting 2 stack pointers, the exception stack frame is created at a 0-modulo-4 address on top of the system stack defined by the supervisor stack pointer (SSP). Additionally, the processor uses a simplified fixed-length stack frame for all exceptions. The exception type determines whether the program counter placed in the exception stack frame defines the location of the faulting instruction (fault) or the address of the next instruction to be executed (next).

Fourth, the processor calculates the address of the first instruction of the exception handler. By definition, the exception vector table is aligned on a 1 Mbyte boundary. This instruction address is generated by fetching an exception vector from the table located at the address defined in the vector base register. The index into the exception table is calculated as (4 × vector number). Once the exception vector has been fetched, the contents of the vector determine the address of the first instruction of the desired handler. After the instruction fetch for the first opcode of the handler has been initiated, exception processing terminates and normal instruction processing continues in the handler.

All ColdFire processors support a 1024-byte vector table aligned on any 1 Mbyte address boundary (see

Table 3-5

). The table contains 256 exception vectors; the first 64 are defined by Freescale and the remaining 192 are user-defined interrupt vectors.

Table 3-5. Exception Vector Assignments

Vector

Number(s)

2

3

0

1

Vector

Offset (Hex)

0x000

0x004

0x008

0x00C

Stacked

Program

Counter

—

—

Fault

Fault

Assignment

Initial stack pointer

Initial program counter

Access error

Address error



Preliminary

3-9

ColdFire Core

Table 3-5. Exception Vector Assignments (continued)

Vector

Number(s)

Vector

Offset (Hex)

Stacked

Program

Counter

Assignment

9

10

11

12

4

5

6–7

8

0x010

0x014

0x018–0x01C

0x020

0x024

0x028

0x02C

0x030

Fault

Fault

—

Fault

Next

Fault

Fault

Next

Illegal instruction

Divide by zero

Reserved

Privilege violation

Trace

Unimplemented line-a opcode

Unimplemented line-f opcode

Debug interrupt

13

14

15–23

24

0x034

0x038

0x03C–0x05C

0x060

—

Fault

—

Next

Reserved

Format error

Reserved

Spurious interrupt

25–31

32–47

48–63

64–255

0x064–0x07C

0x080–0x0BC

0x0C0–0x0FC

0x100–0x3FC

—

Next

—

Next

Reserved

Trap # 0-15 instructions

Reserved

User-defined interrupts

“Fault” refers to the PC of the instruction that caused the exception; “Next” refers to the PC of the next instruction that follows the instruction that caused the fault.

All ColdFire processors inhibit interrupt sampling during the first instruction of all exception handlers.

This allows any handler to effectively disable interrupts, if necessary, by raising the interrupt mask level contained in the status register. In addition, the ISA_A+ architecture includes an instruction (STLDSR) that stores the current interrupt mask level and loads a value into the SR. This instruction is specifically intended for use as the first instruction of an interrupt service routine which services multiple interrupt requests with different interrupt levels. For more details see the ColdFire Family Programmer’s Reference

Manual .

3.5

Exception Stack Frame Definition

The exception stack frame is shown in Figure 3-9 . The first longword of the exception stack frame contains

the 16-bit format/vector word (F/V) and the 16-bit status register, and the second longword contains the

32-bit program counter address.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SSP

→

FORMAT FS[3:2] VECTOR FS[1:0] Status Register

+ 0x4 Program Counter

Figure 3-9. Exception Stack Frame Form

3-10



Preliminary

ColdFire Core

The 16-bit format/vector word contains 3 unique fields:

• A 4-bit format field at the top of the system stack is always written with a value of 4, 5, 6, or 7 by

the processor indicating a two-longword frame format. See Table 3-6

.

Table 3-6. Format Field Encodings

Original SSP @ Time of Exception, Bits 1:0

00

01

10

11

SSP @ 1st

Instruction of

Handler

Original SSP - 8

Original SSP - 9

Original SSP - 10

Original SSP - 11

Format Field

6

7

4

5

• There is a 4-bit fault status field, FS[3:0], at the top of the system stack. This field is defined for

access and address errors only and written as zeros for all other types of exceptions. See Table 3-7 .

Table 3-7. Fault Status Encodings

FS[3:0]

00 xx

0100

0101

011x

1000

1001

101x

1100

1101

111x

Definition

Reserved

Error on instruction fetch

Reserved

Reserved

Error on operand write

Attempted write to write-protected space

Reserved

Error on operand read

Reserved

Reserved

• The 8-bit vector number, vector[7:0], defines the exception type and is calculated by the processor for all internal faults and represents the value supplied by the interrupt controller in the case of an interrupt. Refer to

Table 3-5

.

3.6

Processor Exceptions

3.6.1

Access Error Exception

The exact processor response to an access error depends on the type of memory reference being performed.

For an instruction fetch, the processor postpones the error reporting until the faulted reference is needed by an instruction for execution. Therefore, faults that occur during instruction prefetches that are then followed by a change of instruction flow do not generate an exception. When the processor attempts to



Preliminary

3-11

ColdFire Core execute an instruction with a faulted opword and/or extension words, the access error is signaled and the instruction aborted. For this type of exception, the programming model has not been altered by the instruction generating the access error.

If the access error occurs on an operand read, the processor immediately aborts the current instruction’s execution and initiates exception processing. In this situation, any address register updates attributable to the auto-addressing modes, (for example, (An)+,-(An)), have already been performed, so the programming model contains the updated An value. In addition, if an access error occurs during the execution of a

MOVEM instruction loading from memory, any registers already updated before the fault occurs contain the operands from memory.

The V2 ColdFire processor uses an imprecise reporting mechanism for access errors on operand writes.

Because the actual write cycle may be decoupled from the processor’s issuing of the operation, the signaling of an access error appears to be decoupled from the instruction that generated the write.

Accordingly, the PC contained in the exception stack frame merely represents the location in the program when the access error was signaled. All programming model updates associated with the write instruction are completed. The NOP instruction can collect access errors for writes. This instruction delays its execution until all previous operations, including all pending write operations, are complete. If any previous write terminates with an access error, it is guaranteed to be reported on the NOP instruction.

3.6.2

Address Error Exception

Any attempted execution transferring control to an odd instruction address (that is, if bit 0 of the target address is set) results in an address error exception.

Any attempted use of a word-sized index register (Xn.w) or a scale factor of 8 on an indexed effective addressing mode generates an address error as does an attempted execution of a full-format indexed addressing mode.

3.6.3

Illegal Instruction Exception

Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and most line-F opcode generates their unique exception types, vector numbers 10 and 11, respectively.

ColdFire cores do not provide illegal instruction detection on the extension words on any instruction, including MOVEC.

3.6.4

Divide-By-Zero

Attempting to divide by zero causes an exception (vector 5, offset = 0x014).

3.6.5

Privilege Violation

The attempted execution of a supervisor mode instruction while in user mode generates a privilege violation exception. See the ColdFire Programmer’s Reference Manual for a list of supervisor-mode instructions.

3-12



Preliminary

ColdFire Core

3.6.6

Trace Exception

To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing capability. While in trace mode, indicated by setting of the T bit in the status register (SR[15] = 1), the completion of an instruction execution (for all but the STOP instruction) signals a trace exception. This functionality allows a debugger to monitor program execution.

The STOP instruction has the following effects:

1. The instruction before the STOP executes and then generates a trace exception. In the exception stack frame, the PC points to the STOP opcode.

2. When the trace handler is exited, the STOP instruction is executed, loading the SR with the immediate operand from the instruction.

3. The processor then generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP, and the SR reflects the value loaded in the previous step.

If the processor is not in trace mode and executes a STOP instruction where the immediate operand sets

SR[T], hardware loads the SR and generates a trace exception. The PC in the exception stack frame points to the instruction after the STOP, and the SR reflects the value loaded in step 2.

Because ColdFire processors do not support any hardware stacking of multiple exceptions, it is the responsibility of the operating system to check for trace mode after processing other exception types. As an example, consider the execution of a TRAP instruction while in trace mode. The processor will initiate the TRAP exception and then pass control to the corresponding handler. If the system requires that a trace exception be processed, it is the responsibility of the TRAP exception handler to check for this condition

(SR[T] in the exception stack frame asserted) and pass control to the trace handler before returning from the original exception.

3.6.7

Unimplemented Line-A Opcode

A line-A opcode is defined when bits 15-12 of the opword are 0b1010. This exception is generated by the attempted execution of an undefined line-A opcode.

3.6.8

Unimplemented Line-F Opcode

A line-F opcode is defined when bits 15-12 of the opword are 0b1111. This exception is generated by attempted execution of an undefined line-F opcode.

3.6.9

Debug Interrupt

This special type of program interrupt is discussed in detail in Chapter 31, “Debug Module.”

This exception is generated in response to a hardware breakpoint register trigger. The processor does not generate an IACK cycle but rather calculates the vector number internally (vector number 12).



Preliminary

3-13

ColdFire Core

3.6.10

RTE and Format Error Exception

When an RTE instruction is executed, the processor first examines the 4-bit format field to validate the frame type. For a ColdFire core, any attempted RTE execution where the format is not equal to {4,5,6,7} generates a format error. The exception stack frame for the format error is created without disturbing the original RTE frame and the stacked PC pointing to the RTE instruction.

The selection of the format value provides some limited debug support for porting code from M68000 applications. On M68000 family processors, the SR was located at the top of the stack. On those processors, bit 30 of the longword addressed by the system stack pointer is typically zero. Thus, if an RTE is attempted using this “old” format, it generates a format error on a ColdFire processor.

If the format field defines a valid type, the processor: (1) reloads the SR operand, (2) fetches the second longword operand, (3) adjusts the stack pointer by adding the format value to the auto-incremented address after the fetch of the first longword, and then (4) transfers control to the instruction address defined by the second longword operand within the stack frame.

3.6.11

TRAP Instruction Exception

The TRAP #n instruction always forces an exception as part of its execution and is useful for implementing system calls.

3.6.12

Interrupt Exception

Interrupt exception processing includes interrupt recognition and the fetch of the appropriate vector from the interrupt controller using an IACK cycle. See Chapter 12, “Interrupt Controller Module,” for details on the interrupt controller.

3.6.13

Fault-on-Fault Halt

If a ColdFire processor encounters any type of fault during the exception processing of another fault, the processor immediately halts execution with the catastrophic “fault-on-fault” condition. A reset is required to force the processor to exit this halted state.

3.6.14

Reset Exception

Asserting the reset input signal to the processor causes a reset exception. The reset exception has the highest priority of any exception; it provides for system initialization and recovery from catastrophic failure. Reset also aborts any processing in progress when the reset input is recognized. Processing cannot be recovered.

The reset exception places the processor in the supervisor mode by setting the S bit and disables tracing by clearing the T bit in the SR. This exception also clears the M bit and sets the processor’s interrupt priority mask in the SR to the highest level (level 7). Next, the VBR is initialized to zero (0x00000000).

The control registers specifying the operation of any memories (e.g., cache and/or RAM modules) connected directly to the processor are disabled.

3-14



Preliminary

ColdFire Core

NOTE

Other implementation-specific registers are also affected. Refer to each of the modules in this user’s manual for details on these registers.

Once the processor is granted the bus, it then performs two longword read bus cycles. The first longword at address 0 is loaded into the stack pointer and the second longword at address 4 is loaded into the program counter. After the initial instruction is fetched from memory, program execution begins at the address in the PC. If an access error or address error occurs before the first instruction is executed, the processor enters the fault-on-fault halted state.

ColdFire processors load hardware configuration information into the D0 and D1 general-purpose registers after system reset. The hardware configuration information is loaded immediately after the reset-in signal is negated. This allows an emulator to read out the contents of these registers via BDM to determine the hardware configuration.

Information loaded into D0 defines the processor hardware configuration as shown in

Figure 3-10 .

Access: User read-only DRc[4:0]: Load: 0x080 (D0)

Store: 0x180 (D0)

30 29 31

R

W

Reset 1 1 0

28

PF

27

0 1

26

1

25

1

24

1

23

0

22

VER

21

0 1

20

0

19

0

18

REV

17

0 0

16

0

15 14 13 12 11 10

R MAC DIV EMAC FPU MMU 0

W

Reset 0 1 1 0 0 0

9

0

0

8

0

0

7

1

6

0

ISA

5

0

Figure 3-10. D0 Hardware Configuration Info

4

0

3

1

2 1

DEBUG

0 0

0

1

Table 3-8. D0 Hardware Configuration Info Field Description

Field Description

31–24

PF

Processor family. This field is fixed to a hex value of 0xCF indicating a ColdFire core is present.

23–20

VER

ColdFire core version number. Defines the hardware microarchitecture version of the ColdFire core.

0010 V2 ColdFire core (This is the value used for this device.)

0011 V3 ColdFire core



Else Reserved for future use.

19–16

REV

Processor revision number. The default is 0b0000.

15

MAC

MAC present.This bit signals if the optional multiply-accumulate (MAC) execution engine is present in the processor core.

0 MAC execute engine not present in core. (This is the value used for this device.)

1 MAC execute engine is present in core.



Preliminary

3-15

ColdFire Core

Table 3-8. D0 Hardware Configuration Info Field Description (continued)


14

DIV

Divide present. This bit signals if the hardware divider (DIV) is present in the processor core.

0 Divide execute engine not present in core.

1 Divide execute engine is present in core. (This is the value used for this device.)

13

EMAC

EMAC present. This bit signals if the optional enhanced multiply-accumulate (EMAC) execution engine is present in the processor core.

0 EMAC execute engine not present in core.

1 EMAC execute engine is present in core.(This is the value used for this device.)

12

FPU

11

MMU

FPU present. This bit signals if the optional floating-point (FPU) execution engine is present in the processor core.

0 FPU execute engine not present in core. (This is the value used for this device.)

1 FPU execute engine is present in core.

MMU present. This bit signals if the optional virtual memory management unit (MMU) is present in the processor core.

0 MMU execute engine not present in core. (This is the value used for this device.)

1 MMU execute engine is present in core.

10–8 Reserved.

7–4

ISA

ISA revision. This 4-bit field defines the instruction set architecture (ISA) revision level implemented in the ColdFire processor core.

0000 ISA_A

0001 ISA_B

0010 ISA_C

1000 ISA_A+ (This is the value used for this device)

Else Reserved

3–0

DEBUG

Debug module revision number. This 4-bit field defines the revision level of the debug module implemented in the

ColdFire processor core.

0000 DEBUG_A

0001 DEBUG_B

0010 DEBUG_C

0011 DEBUG_D

0100 DEBUG_E

1001 DEBUG_B+ (This is the value used for this device)

Else Reserved

Information loaded into D1 defines the local memory hardware configuration as shown in the figure below.

3-16



Preliminary

ColdFire Core

DRc[4:0]: Load: 0x081 (D1)

Store: 0x181 (D1)

R

W

Reset

0

31

CLSZ

30

0

29

CCAS

28

0 1

27 26

CCSZ

25 24

0 0 0 0

23 22 21

FLASHSZ

20 19

0

1 0 1 0 0


18

0

0

17

0

0

16

0

0

R

W

Reset 0

15

MBSZ

14

0

13

UCAS

12 11

0

10

0

9

0

8

0

7 6 5

SRAMSZ

4 3

0

0 1 0 0 0 0 0 1 1

Figure 3-11. D1 Hardware Configuration Info

1 0

Table 3-9. D1 Hardware Configuration Information Field Description


31–30

CLSZ

29–28

CCAS

27–24

CCSZ

Cache line size. This field is fixed to a hex value of 0x0 indicating a 16-byte cache line size.

Configurable cache associativity.

00 Four-way

01 Direct mapped (This is the value used for this device)

Else Reserved for future use

Configurable cache size. Indicates the amount of instruction/data cache.

0000 No configurable cache (This is the value used for this device)

0001 512B configurable cache

0010 1KB configurable cache







Else Reserved

23–20

FLASHSZ

Flash bank size.

0000-0111 No flash

1000 64KB Flash

1001 128KB Flash

1010 256KB Flash (This is the value used for this device)

1011 512KB Flash

Else Reserved for future use.

19–16

15–14

MBSZ

Reserved

Bus size. Defines the width of the ColdFire master Bus datapath.

00 32-bit system bus datapath (This is the value used for this device)

01 64-bit system bus datapath

Else Reserved

2

0

0

1

0

0

0

0 0



Preliminary

3-17

ColdFire Core

Table 3-9. D1 Hardware Configuration Information Field Description (continued)


13–12

UCAS

11–8

7–4

SRAMSZ

3-0

Unified cache associativity. Defines the unified cache set-associativity.

00 Four-way

01 Direct mapped (This is the value used for this device)


Reserved.

SRAM bank size.

0000 No SRAM

0001 512 bytes

0010 1 Kbytes

0011 2 Kbytes

0100 4 Kbytes

0101 8 Kbytes

0110 16 Kbytes

0111 32 Kbytes (This is the value used for this device)

1000 64 Kbytes

1001 128 Kbytes


Reserved

3.7

Instruction Execution Timing

This section presents processor instruction execution times in terms of processor core clock cycles. The number of operand references for each instruction is enclosed in parentheses following the number of processor clock cycles. Each timing entry is presented as C(R/W) where:

• C is the number of processor clock cycles, including all applicable operand fetches and writes, and all internal core cycles required to complete the instruction execution.

• R/W is the number of operand reads (R) and writes (W) required by the instruction. An operation performing a read-modify-write function is denoted as (1/1).

This section includes the assumptions concerning the timing values and the execution time details.

3.7.1

Timing Assumptions

For the timing data presented in this section, the following assumptions apply:

1. The OEP is loaded with the opword and all required extension words at the beginning of each instruction execution. This implies that the OEP does not wait for the IFP to supply opwords and/or extension words.

2. The OEP does not experience any sequence-related pipeline stalls.The most common example of this type of stall involves consecutive store operations, excluding the MOVEM instruction. For all

STORE operations (except MOVEM), certain hardware resources within the processor are marked as “busy” for two clock cycles after the final decode and select/operand fetch cycle (DSOC) of the store instruction. If a subsequent STORE instruction is encountered within this 2-cycle window, it

3-18



Preliminary

ColdFire Core is stalled until the resource again becomes available. Thus, the maximum pipeline stall involving consecutive STORE operations is 2 cycles. The MOVEM instruction uses a different set of resources and this stall does not apply.

3. The OEP completes all memory accesses without any stall conditions caused by the memory itself.

Thus, the timing details provided in this section assume that an infinite zero-wait state memory is attached to the processor core.

4. All operand data accesses are aligned on the same byte boundary as the operand size, i.e., 16-bit operands aligned on 0-modulo-2 addresses, 32-bit operands aligned on 0-modulo-4 addresses.

The processor core decomposes misaligned operand references into a series of aligned accesses as shown

in Table 3-10 .

Table 3-10. Misaligned Operand References address[1:0]

01 or 11

01 or 11

10

Size

Word

Long

Long

Bus

Operations

Byte, Byte

Byte, Word,

Byte

Word, Word

Additional

C(R/W)

2(1/0) if read

1(0/1) if write

3(2/0) if read

2(0/2) if write

2(1/0) if read

1(0/1) if write

3.7.2

MOVE Instruction Execution Times

Table 3-11

lists execution times for MOVE.{B,W} instructions; Table 3-12 lists timings for MOVE.L. For

all tables in this section, the execution time of any instruction using the PC-relative effective addressing modes is the same for the comparable An-relative mode.The nomenclature “xxx.wl” refers to both forms of absolute addressing, xxx.w and xxx.l.

Table 3-11. MOVE Byte and Word Execution Times

Source

Dy

Ay

(Ay)

(Ay)+

-(Ay)

(d16,Ay)

(d8,Ay,Xi*SF) xxx.w

xxx.l

(d16,PC)

Rx

1(0/0)

1(0/0)

3(1/0)

3(1/0)

3(1/0)

3(1/0)

4(1/0)

3(1/0)

3(1/0)

3(1/0)

(Ax)

1(0/1)

1(0/1)

3(1/1)

3(1/1)

3(1/1)

3(1/1)

4(1/1)

3(1/1)

3(1/1)

3(1/1)

(Ax)+

1(0/1)

1(0/1)

3(1/1)

3(1/1)

3(1/1)

3(1/1)

4(1/1)

3(1/1)

3(1/1)

3(1/1)

Destination

-(Ax)

1(0/1)

1(0/1)

3(1/1)

3(1/1)

3(1/1)

3(1/1)

4(1/1))

3(1/1)

3(1/1)

31/1)

(d16,Ax) (d8,Ax,Xi*SF) xxx.wl

1(0/1)

1(0/1)

3(1/1)

3(1/1)

3(1/1)

3(1/1)

—

—

—

3(1/1)

2(0/1)

2(0/1)

4(1/1))

4(1/1))

4(1/1)

—

—

—

—

—

1(0/1)

1(0/1)

3(1/1)

3(1/1)

3(1/1)

—

—

—

—

—



Preliminary

3-19

ColdFire Core

Dy

Ay

(Ay)

(Ay)+

-(Ay)

(d16,Ay)

(d8,Ay,Xi*SF) xxx.w

xxx.l

(d16,PC)

(d8,PC,Xi*SF)

#xxx

Source

(d8,PC,Xi*SF)

#xxx

Source

Rx

1(0/0)

1(0/0)

2(1/0)

2(1/0)

2(1/0)

2(1/0)

3(1/0)

2(1/0)

2(1/0)

2(1/0)

3(1/0)

1(0/0)

Table 3-11. MOVE Byte and Word Execution Times (continued)

Destination

Rx

4(1/0)

1(0/0)

(Ax)

4(1/1)

3(0/1)

(Ax)+

4(1/1)

3(0/1)

-(Ax)

4(1/1))

3(0/1)


—

—

—

—

—

—

Table 3-12. MOVE Long Execution Times

Destination

(Ax)

1(0/1)

1(0/1)

2(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(0/1)

(Ax)+

1(0/1)

1(0/1)

2(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(0/1)

-(Ax)

1(0/1)

1(0/1)

2(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(1/1)

2(1/1)

2(1/1)

3(1/1)

2(0/1)


1(0/1)

1(0/1)

2(1/1)

2(1/1)

2(1/1)

2(1/1)

—

—

—

2(1/1)

—

—

2(0/1)

2(0/1)

3(1/1)

3(1/1)

3(1/1)

—

—

—

—

—

—

—

1(0/1)

1(0/1)

2(1/1)

2(1/1)

2(1/1)

—

—

—

—

—

—

—

3.8

Standard One Operand Instruction Execution Times

Table 3-13. One Operand Instruction Execution Times

Opcode <EA> bitrev byterev clr.b

clr.w

clr.l

ext.w

ext.l

extb.l

ff1

Dx

Dx

<ea>

<ea>

<ea>

Dx

Dx

Dx

Dx

Rn

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

(An)

—

—

1(0/1)

1(0/1)

1(0/1)

—

—

—

—

(An)+

—

—

1(0/1)

1(0/1)

1(0/1)

—

—

—

—

Effective Address

-(An)

—

—

1(0/1)

1(0/1)

1(0/1)

—

—

—

—

(d16,An) (d8,An,Xn*SF) xxx.wl

—

—

1(0/1)

1(0/1)

1(0/1)

—

—

—

—

—

—

2(0/1)

2(0/1)

2(0/1)

—

—

—

—

—

—

1(0/1)

1(0/1)

1(0/1)

—

—

—

—

#xxx

—

—

—

—

—

—

—

—

—

3-20



Preliminary

ColdFire Core

Opcode <EA> neg.l

negx.l

not.l

scc swap tst.b

tst.w

tst.l

Dx

<ea>

<ea>

<ea>

Dx

Dx

Dx

Dx

Table 3-13. One Operand Instruction Execution Times (continued)

Rn

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0)

(An)

—

3(1/0)

3(1/0)

2(1/0)

—

—

—

—

(An)+

—

3(1/0)

3(1/0)

2(1/0)

—

—

—

—


-(An)

—

3(1/0)

3(1/0)

2(1/0)

—

—

—

—


—

3(1/0)

3(1/0)

2(1/0)

—

—

—

—

—

—

—

—

—

4(1/0)

4(1/0)

3(1/0)

—

3(1/0)

3(1/0)

2(1/0)

—

—

—

—

3.9

Standard Two Operand Instruction Execution Times

Table 3-14. Two Operand Instruction Execution Times

Opcode asl.l

asr.l

bchg bchg bclr bclr bset bset add.l

add.l

addi.l

addq.l

addx.l

and.l

and.l

andi.l

btst btst cmp.l

cmpi.l

<EA>

Rn

<ea>,Rx

Dy,<ea>

1(0/0)

—

#imm,Dx 1(0/0)

#imm,<ea> 1(0/0)

Dy,Dx

<ea>,Rx

Dy,<ea>

#imm,Dx

1(0/0)

1(0/0)

—

1(0/0)

<ea>,Dx

<ea>,Dx

1(0/0)

1(0/0)

Dy,<ea> 2(0/0)

#imm,<ea> 2(0/0)

Dy,<ea> 2(0/0)

#imm,<ea> 2(0/0)

Dy,<ea> 2(0/0)

#imm,<ea> 2(0/0)

Dy,<ea> 2(0/0)

#imm,<ea> 1(0/0)

<ea>,Rx

#imm,Dx

1(0/0)

1(0/0)

(An)

—

—

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

3(1/0)

3(1/1)

—

3(1/1)

—

3(1/0)

3(1/1)

—

3(1/1)

3(1/1)

3(1/0)

—

(An)+


-(An)

—

—

4(1/1)

4(1/1)

4(1/1)

4(1/1)

41/1)

4(1/1)

3(1/0) 3(1/0)

3(1/1) 3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/0)

—

3(1/0)

3(1/1) 3(1/1)

— —

3(1/1)

3(1/1)

3(1/0)

—

3(1/1)

3(1/1)

3(1/0)

—

—

—

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

(d16,An)

(d16,PC)

(d8,An,Xn*SF)

(d8,PC,Xn*SF) xxx.wl

—

—

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

4(1/1)

3(1/0)

3(1/1)

—

3(1/1)

—

3(1/0)

3(1/1)

—

3(1/1)

3(1/1)

3(1/0)

—

—

—

5(1/1)

—

5(1/1)

—

5(1/1)

—

4(1/0)

4(1/1)

—

4(1/1)

—

4(1/0)

4(1/1)

—

4(1/1)

—

4(1/0)

—

—

—

4(1/1)

—

4(1/1)

—

4(1/1)

—

3(1/0)

3(1/1)

—

3(1/1)

—

3(1/0)

3(1/1)

—

3(1/1)

—

3(1/0)

—

#xxx

—

—

—

—

1(0/0)

1(0/0)

—

—

1(0/0)

—

—

—

—

1(0/0)

—

—

—

1(0/0)

1(0/0)

—

#xxx

—

1(0/0)

1(0/0)

1(0/0)

—

—

—

—



Preliminary

3-21

ColdFire Core

Table 3-14. Two Operand Instruction Execution Times (continued) lsr.l

moveq or.l

or.l

ori.l

rems.l

remu.l

sub.l

divs.w

divu.w

divs.l

divu.l

eor.l

eori.l

lea lsl.l

sub.l

subi.l

subq.l

subx.l

Opcode


<EA>

Rn (An) (An)+ -(An)

(d16,An)

(d16,PC)

(d8,An,Xn*SF)

(d8,PC,Xn*SF) xxx.wl

<ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0)

<ea>,Dx 20(0/0) 23(1/0) 23(1/0) 23(1/0) 23(1/0)

<ea>,Dx

≤

35(0/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

<ea>,Dx

≤

35(0/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

Dy,<ea> 1(0/0) 3(1/1) 3(1/1) 3(1/1) 3(1/1)

#imm,Dx

<ea>,Ax

<ea>,Dx

<ea>,Dx

1(0/0)

—

1(0/0)

1(0/0)

—

1(0/0)

—

—

—

—

—

—

—

—

—

—

—

1(0/0)

—

—

#imm,Dx

<ea>,Rx

—

1(0/0)

—

3(1/0)

—

3(1/0)

—

3(1/0)

—

3(1/0)

Dy,<ea> — 3(1/1) 3(1/1) 3(1/1) 3(1/1)

#imm,Dx 1(0/0) — — — —

<ea>,Dx

≤

35(0/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

<ea>,Dx

≤

35(0/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

≤

38(1/0)

<ea>,Rx 1(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0)

Dy,<ea>

#imm,Dx

—

1(0/0)

#imm,<ea> 1(0/0)

Dy,Dx 1(0/0)

3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/1)

—

3(1/1)

—

—

—

4(1/0)

4(1/1)

—

—

—

4(1/0)

24(1/0)

24(1/0)

—

—

4(1/1)

—

2(0/0)

—

4(1/1)

—

4(1/1)

—

#xxx

—

—

3(1/0)

3(1/1)

—

—

—

3(1/0)

23(1/0) 20(0/0)

23(1/0) 20(0/0)

—

—

—

—

3(1/1)

—

1(0/0)

—

—

—

—

1(0/0)

3(1/1)

—

3(1/1)

—

—

—

—

—

1(0/0)

1(0/0)

1(0/0)

—

—

—

—

1(0/0)

3.10

Miscellaneous Instruction Execution Times

Table 3-15. Miscellaneous Instruction Execution Times

Opcode <EA>

Rn link.w

move.l

Ay,#imm

Ay,USP move.l

USP,Ax move.w

CCR,Dx

2(0/1)

3(0/0)

3(0/0)

1(0/0) move.w

<ea>,CCR 1(0/0) move.w

SR,Dx 1(0/0) move.w

<ea>,SR movec Ry,Rc movem.l

<ea>,&list

7(0/0)

9(0/1)

—

(An)

—

—

—

—

—

—

—

—

1+n(n/0)

(An)+

—

—

—

—

—

—

—

—

—


-(An)

—

—

—

—

—

—

—

—

—


—

—

—

—

—

—

—

—

1+n(n/0)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

#xxx

—

—

—

—

1(0/0)

—

7(0/0)

2

—

—

3-22



Preliminary

ColdFire Core

Table 3-15. Miscellaneous Instruction Execution Times (continued)


Opcode <EA>

Rn (An) (An)+ -(An) (d16,An) (d8,An,Xn*SF) xxx.wl

#xxx movem.l

&list,<ea> nop pea pulse stldsr stop trap trapf trapf.w

trapf.l

unlk wddata

<ea>

#imm

#imm

#imm

Ax

<ea>

—

3(0/0)

—

1(0/0)

—

—

—

1(0/0)

1(0/0)

1(0/0)

2(1/0)

—

1+n(0/n)

—

2(0/1)

—

—

—

—

—

—

—

—

3(1/0)

—

—

—

—

—

—

—

—

—

—

—

3(1/0)

—

—

—

—

—

—

—

—

—

—

—

3(1/0)

1+n(0/n)

—

2(0/1)

—

—

—

—

—

—

—

—

3(1/0)

4

—

—

3(0/1)

—

—

—

—

—

—

—

—

4(1/0)

5

—

—

2(0/1)

—

—

—

—

—

—

—

—

3(1/0) wdebug <ea> — 5(2/0) — — 5(2/0) — —

1 n is the number of registers moved by the MOVEM opcode.

2

If a MOVE.W #imm,SR instruction is executed and imm[13] = 1, the execution time is 1(0/0).

3

The execution time for STOP is the time required until the processor begins sampling continuously for interrupts.

4

PEA execution times are the same for (d16,PC).

5

PEA execution times are the same for (d8,PC,Xn*SF).

—

—

—

—

5(0/1)

3(0/0)

3

15(1/2)

—

—

—

—

3(1/0)

—

3.11

EMAC Instruction Execution Times

Table 3-16. EMAC Instruction Execution Times


Opcode <EA>

Rn (An) (An)+ -(An) (d16,An)

(d8,An,

Xn*SF) xxx.wl

#xxx muls.w

mulu.w

muls.l

mulu.l

mac.w

mac.l

msac.w

msac.l

<ea>y, Dx

<ea>y, Dx

<ea>y, Dx

<ea>y, Dx

Ry, Rx, Raccx

Ry, Rx, Raccx

Ry, Rx, Raccx

Ry, Rx, Raccx

4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0)

4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0)

4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0)

4(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0)

1(0/0)

1(0/0)

1(0/0)

1(0/0) mac.w

Ry, Rx, <ea>, Rw, Raccx — mac.l

Ry, Rx, <ea>, Rw, Raccx —

—

—

—

—

—

—

—

—

—

—

—

—

— — — —

2(1/0) 2(1/0) 2(1/0) 2(1/0)

1

2(1/0) 2(1/0) 2(1/0) 2(1/0)

1

71/0) 6(1/0) 4(0/0)

71/0) 6(1/0) 4(0/0)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—



Preliminary

3-23

ColdFire Core

Table 3-16. EMAC Instruction Execution Times (continued)


Opcode <EA>

Rn msac.w

Ry, Rx, <ea>, Rw — msac.l

Ry, Rx, <ea>, Rw, Raccx — move.l

move.l

move.l

move.l

<ea>y, Raccx

Raccy,Raccx

<ea>y, MACSR

<ea>y, Rmask

1(0/0)

1(0/0)

5(0/0)

4(0/0)

(An) (An)+ -(An) (d16,An)

(d8,An,

Xn*SF) xxx.wl

#xxx

2(1/0) 2(1/0) 2(1/0) 2(1/0)

1

2(1/0) 2(1/0) 2(1/0) 2(1/0)

1

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

1(0/0)

—

5(0/0)

4(0/0) move.l

move.l

<ea>y,Raccext01

<ea>y,Raccext23

1(0/0)

1(0/0)

1(0/0)

2

—

—

—

—

—

—

—

—

—

—

—

—

1(0/0)

1(0/0) move.l

move.l

move.l

move.l

Raccx,<ea>x

MACSR,<ea>x

Rmask, <ea>x

Raccext01,<ea.x

1(0/0)

1(0/0)

1(0/0)

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

— move.l

Raccext23,<ea>x 1(0/0) — — — — — —

1

2

Effective address of (d16,PC) not supported

Storing an accumulator requires one additional processor clock cycle when saturation is enabled, or fractional rounding is performed (MACSR[7:4] = 1---, -11-, --11)

—

3.12

Branch Instruction Execution Times

Table 3-17. General Branch Instruction Execution Times

Opcode <EA> bsr jmp jsr rte rts

<ea>

<ea>

Rn

—

—

—

—

—

(An)

—

3(0/0)

3(0/1)

—

—

(An)+

—

—

—

10(2/0)

5(1/0)

—

—

—

—

—


-(An)

(d16,An)

(d16,PC)

(d8,An,Xi*SF)

(d8,PC,Xi*SF)

3(0/1)

3(0/0)

3(0/1)

—

—

—

4(0/0)

4(0/1)

—

— xxx.wl

—

3(0/0)

3(0/1)

—

—

#xxx

—

—

—

—

—

3-24



Preliminary

Opcode bra bcc

Table 3-18. BRA, Bcc Instruction Execution Times

Forward

Taken

2(0/0)

3(0/0)

Forward

Not Taken

—

1(0/0)

Backward

Taken

2(0/0)

2(0/0)

Backward

Not Taken

—

3(0/0)

ColdFire Core



Preliminary

3-25

ColdFire Core

3-26



Preliminary

Chapter 4


This chapter describes the functionality, microarchitecture, and performance of the enhanced multiply-accumulate (EMAC) unit in the ColdFire family of processors.

4.1

Multiply-Accumulate Unit

The MAC design provides a set of DSP operations that can be used to improve the performance of embedded code while supporting the integer multiply instructions of the baseline ColdFire architecture.

The MAC provides functionality in three related areas:

1. Signed and unsigned integer multiplies

2. Multiply-accumulate operations supporting signed and unsigned integer operands as well as signed, fixed-point, fractional operands

3. Miscellaneous register operations

The ColdFire family supports two MAC implementations with different performance levels and capabilities. The original MAC features a three-stage execution pipeline optimized for 16-bit operands, with a 16x16 multiply array and a single 32-bit accumulator. The EMAC features a four-stage pipeline optimized for 32-bit operands, with a fully pipelined 32 × 32 multiply array and four 48-bit accumulators.

The first ColdFire MAC supported signed and unsigned integer operands and was optimized for 16x16 operations, such as those found in a variety of applications including servo control and image compression.

As ColdFire-based systems proliferated, the desire for more precision on input operands increased. The result was an improved ColdFire MAC with user-programmable control to optionally enable use of fractional input operands.

EMAC improvements target three primary areas:

• Improved performance of 32 × 32 multiply operation.

• Addition of three more accumulators to minimize MAC pipeline stalls caused by exchanges between the accumulator and the pipeline’s general-purpose registers

• A 48-bit accumulation data path to allow the use of a 40-bit product, plus the addition of 8 extension bits to increase the dynamic number range when implementing signal processing algorithms

The three areas of functionality are addressed in detail in following sections. The logic required to support this functionality is contained in a MAC module, as shown in

Figure 4-1

.



Preliminary

4-1


Operand Y

X

Shift 0,1,-1

+/-

Accumulator(s)

Operand X

Figure 4-1. Multiply-Accumulate Functionality Diagram

4.2

Introduction to the MAC

The MAC is an extension of the basic multiplier found in most microprocessors. It is typically implemented in hardware within an architecture and supports rapid execution of signal processing algorithms in fewer cycles than comparable non-MAC architectures. For example, small digital filters can tolerate some variance in an algorithm’s execution time, but larger, more complicated algorithms such as orthogonal transforms may have more demanding speed requirements beyond the scope of any processor architecture and may require full DSP implementation.

To strike a balance between speed, size, and functionality, the ColdFire MAC is optimized for a small set of operations that involve multiplication and cumulative additions. Specifically, the multiplier array is optimized for single-cycle pipelined operations with a possible accumulation after product generation.

This functionality is common in many signal processing applications. The ColdFire core architecture also has been modified to allow an operand to be fetched in parallel with a multiply, increasing overall performance for certain DSP operations.

Consider a typical filtering operation where the filter is defined as in

Equation 4-1

.

=

∑ a k ( – ) +

∑ b k ( – )

Eqn. 4-1 k = 1 k = 0

Here, the output y(i) is determined by past output values and past input values. This is the general form of an infinite impulse response (IIR) filter. A finite impulse response (FIR) filter can be obtained by setting coefficients a(k) to zero. In either case, the operations involved in computing such a filter are multiplies and product summing. To show this point, reduce the above equation to a simple, four-tap FIR filter, shown

in Equation 4-2 , in which the accumulated sum is a sum of past data values and coefficients.

3

=

∑ b k ( – ) = k = 0

4.3

General Operation

b 0 x i + b 1 ( – ) + b 2 ( – ) + b 3 ( – )

Eqn. 4-2

The MAC speeds execution of ColdFire integer multiply instructions (MULS and MULU) and provides additional functionality for multiply-accumulate operations. By executing MULS and MULU in the MAC,

4-2



Preliminary

Enhanced Multiply-Accumulate Unit (EMAC) execution times are minimized and deterministic compared to the 2-bit/cycle algorithm with early termination that the OEP normally uses if no MAC hardware is present.

The added MAC instructions to the ColdFire ISA provide for the multiplication of two numbers, followed by the addition or subtraction of the product to or from the value in an accumulator. Optionally, the product may be shifted left or right by 1 bit before addition or subtraction. Hardware support for saturation arithmetic can be enabled to minimize software overhead when dealing with potential overflow conditions.

Multiply-accumulate operations support 16- or 32-bit input operands of the following formats:

• Signed integers

• Unsigned integers

• Signed, fixed-point, fractional numbers

The EMAC is optimized for single-cycle, pipelined 32 × 32 multiplications. For word- and longword-sized integer input operands, the low-order 40 bits of the product are formed and used with the destination accumulator. For fractional operands, the entire 64-bit product is calculated and either truncated or rounded to the most-significant 40-bit result using the round-to-nearest (even) method before it is combined with the destination accumulator.

For all operations, the resulting 40-bit product is extended to a 48-bit value (using sign-extension for signed integer and fractional operands, zero-fill for unsigned integer operands) before being combined with the 48-bit destination accumulator.

Figure 4-2

and Figure 4-3 show relative alignment of input operands, the full 64-bit product, the resulting

40-bit product used for accumulation, and 48-bit accumulator formats.

X

OperandY

OperandX

32

32

Product

40

23 “0”

Extended Product

+

Accumulator

8 40

8 40 8

Extension Byte Upper [7:0] Accumulator [31:0] Extension Byte Lower [7:0]

Figure 4-2. Fractional Alignment



Preliminary

4-3


X

OperandY

OperandX

32

32

Product

24 8 32

Extended Product

+

Accumulator

8 8 32

8 8 32

Extension Byte Upper [7:0] Accumulator [31:0]

Extension Byte Lower [7:0]

Figure 4-3. Signed and Unsigned Integer Alignment

Thus, the 48-bit accumulator definition is a function of the EMAC operating mode. Given that each 48-bit accumulator is the concatenation of 16-bit accumulator extension register (ACCext n ) contents and 32-bit

ACC n contents, the specific definitions are as follows: if MACSR[6:5] == 00 /* signed integer mode */

Complete Accumulator[47:0] = {ACCext n [15:0], ACC n [31:0]} if MACSR[6:5] == 01 or 11 /* signed fractional mode */

Complete Accumulator [47:0] = {ACCext n [15:8], ACC n [31:0], ACCext n [7:0]} if MACSR[6:5] == 10 /* unsigned integer mode */

Complete Accumulator[47:0] = {ACCext n [15:0], ACC n [31:0]}

The four accumulators are represented as an array, ACC n , where n selects the register.

Although the multiplier array is implemented in a four-stage pipeline, all arithmetic MAC instructions have an effective issue rate of 1 cycle, regardless of input operand size or type.

All arithmetic operations use register-based input operands, and summed values are stored internally in an accumulator. Thus, an additional move instruction is needed to store data in a general-purpose register.

One new feature found in EMAC instructions is the ability to choose the upper or lower word of a register as a 16-bit input operand. This is useful in filtering operations if one data register is loaded with the input data and another is loaded with the coefficient. Two 16-bit multiply accumulates can be performed without fetching additional operands between instructions by alternating the word choice during the calculations.

The EMAC has four accumulator registers versus the MAC’s single accumulator. The additional registers improve the performance of some algorithms by minimizing pipeline stalls needed to store an accumulator value back to general-purpose registers. Many algorithms require multiple calculations on a given data set.

By applying different accumulators to these calculations, it is often possible to store one accumulator without any stalls while performing operations involving a different destination accumulator.

4-4



Preliminary


The need to move large amounts of data presents an obstacle to obtaining high throughput rates in DSP engines. New and existing ColdFire instructions can accommodate these requirements. A MOVEM instruction can move large blocks of data efficiently by generating line-sized burst references. The ability to simultaneously load an operand from memory into a register and execute a MAC instruction makes some DSP operations such as filtering and convolution more manageable.

The programming model includes a mask register (MASK), which can optionally be used to generate an operand address during MAC + MOVE instructions. The application of this register with auto-increment addressing mode supports efficient implementation of circular data queues for memory operands.

4.4

Memory Map/Register Definition

The following table and sections explain the MAC registers:

Table 4-1. EMAC Memory Map

CPU Space

(Rc)

Register

0x804

0x805


MAC Address Mask Register (MASK)

0x806, 0x809,

0x80A, 0x80B

MAC Accumulators 0–3 (ACC0–3)

0x807

0x808

MAC Accumulator 0,1 Extension Bytes (ACCext01)

MAC Accumulator 2,3 Extension Bytes (ACCext23)

Width

(bits)

Access Reset Value Section/Page

32

32

32

R/W

R/W

R/W

0x0000_0000

0xFFFF_FFFF

Undefined

4.4.1/4-5

4.4.2/4-9

4.4.3/4-10

32

32

R/W

R/W

Undefined

Undefined

4.4.4/4-10

4.4.4/4-10

4.4.1

MAC Status Register (MACSR)

The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.

Operational mode bits control whether operands are signed or unsigned and whether they are treated as integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding is performed. Negative, zero, and multiple overflow condition flags are also provided.

Address: CPU @ 0x804 Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PAV n

7 6 5 4 3 2 1 0

N Z V EV

OMC S/U F/I R/T

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 4-4. MAC Status Register (MACSR)



Preliminary

4-5


Field

31–12

11–8

PAV n

7

OMC

6

S/U

5

F/I

4

R/T

3

N

2

Z

Table 4-2. MACSR Field Descriptions

Description


Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or

MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a

MAC or MSAC instruction is executed, the PAV n flag associated with the destination accumulator is used to form the general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a

MOV.L, MACSR instruction or the accumulator is loaded directly.

Overflow/saturation mode. Used to enable or disable saturation mode on overflow. If set, the accumulator is set to the appropriate constant on any operation which overflows the accumulator. Once saturated, the accumulator remains unaffected by any other MAC or MSAC instructions until either the overflow bit is cleared or the accumulator is directly loaded.

Signed/unsigned operations.

In integer mode:

S/U determines whether operations performed are signed or unsigned. It also determines the accumulator value during saturation, if enabled.

0 Signed numbers. On overflow, if OMC is enabled, an accumulator saturates to the most positive

(0x7FFF_FFFF) or the most negative (0x8000_0000) number, depending on both the instruction and the value of the product that overflowed.

1 Unsigned numbers. On overflow, if OMC is enabled, an accumulator saturates to the smallest value

(0x0000_0000) or the largest value (0xFFFF_FFFF), depending on the instruction.

In fractional mode:

S/U controls rounding while storing an accumulator to a general-purpose register.

0 Move accumulator without rounding to a 16-bit value. Accumulator is moved to a general-purpose register as a 32-bit value.

1 The accumulator is rounded to a 16-bit value using the round-to-nearest (even) method when it is moved

to a general-purpose register. See Section 4.4.1.1.1, “Rounding

.” The resulting 16-bit value is stored in the lower word of the destination register. The upper word is zero-filled. The accumulator value is not affected by this rounding procedure.

Fractional/integer mode Determines whether input operands are treated as fractions or integers.

0 Integers can be represented in either signed or unsigned notation, depending on the value of S/U.

1 Fractions are represented in signed, fixed-point, two’s complement notation. Values range from -1 to

1 - 2

-15

for 16-bit fractions and -1 to 1 - 2

-31

for 32-bit fractions. See Section 4.5.2, “Data

Representation

."

Round/truncate mode. Controls the rounding procedure for MOV.L ACCx,Rx, or MSAC.L instructions when operating in fractional mode.

0 Truncate. The product’s lsbs are dropped before it is combined with the accumulator. Additionally, when a store accumulator instruction is executed (MOV.L ACCx,Rx), the 8 lsbs of the 48-bit accumulator logic are simply truncated.

1 Round-to-nearest (even). The 64-bit product of two 32-bit, fractional operands is rounded to the nearest

40-bit value. If the low-order 24 bits equal 0x80_0000, the upper 40 bits are rounded to the nearest even

(lsb = 0) value. See Section 4.4.1.1.1, “Rounding .” Additionally, when a store accumulator instruction is

executed (MOV.L ACCx,Rx), the lsbs of the 48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] = 0 and MACSR[R/T] = 1, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] = 1, the low-order 24 bits are used to round the resulting 16-bit fraction.

Negative. Set if the msb of the result is set, otherwise cleared. N is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions.

Zero. Set if the result equals zero, otherwise cleared. This bit is affected only by MAC, MSAC, and load operations; it is not affected by MULS and MULU instructions.

4-6



Preliminary


Field

1

V

0

EV

Table 4-2. MACSR Field Descriptions (continued)

Description

Overflow. Set if an arithmetic overflow occurs on a MAC or MSAC instruction indicating that the result cannot be represented in the limited width of the EMAC. V is set only if a product overflow occurs or the accumulation overflows the 48-bit structure. V is evaluated on each MAC or MSAC operation and uses the appropriate PAV n flag in the next-state V evaluation.

Extension overflow. Signals that the last MAC or MSAC instruction overflowed the 32 lsbs in integer mode or the 40 lsbs in fractional mode of the destination accumulator. However, the result is still accurately represented in the combined 48-bit accumulator structure. Although an overflow has occurred, the correct result, sign, and magnitude are contained in the 48-bit accumulator. Subsequent MAC or MSAC operations may return the accumulator to a valid 32/40-bit result.

Table 4-3

summarizes the interaction of the MACSR[S/U,F/I,R/T] control bits.

Table 4-3. Summary of S/U, F/I, and R/T Control Bits

S/U F/I R/T

0

0

0

1

0

1

1

1

1

0

1

1

Operational Modes x Signed, integer

0 Signed, fractional

Truncate on MAC.L and MSAC.L

No round on accumulator stores


Round on MAC.L and MSAC.L

Round-to-32-bits on accumulator stores x Unsigned, integer


Truncate on MAC.L and MSAC.L

Round-to-16-bits on accumulator stores


Round on MAC.L and MSAC.L

Round-to-16-bits on accumulator stores

4.4.1.1

Fractional Operation Mode

This section describes behavior when the fractional mode is used (MACSR[F/I] is set).

4.4.1.1.1

Rounding

When the processor is in fractional mode, there are two operations during which rounding can occur:

1. Execution of a store accumulator instruction (MOV.L ACCx,Rx). The lsbs of the 48-bit accumulator logic are used to round the resulting 16- or 32-bit value. If MACSR[S/U] is cleared, the low-order 8 bits are used to round the resulting 32-bit fraction. If MACSR[S/U] is set, the low-order 24 bits are used to round the resulting 16-bit fraction.

2. Execution of a MAC (or MSAC) instruction with 32-bit operands. If MACSR[R/T] is zero, multiplying two 32-bit numbers creates a 64-bit product that is truncated to the upper 40 bits; otherwise, it is rounded using round-to-nearest (even) method.



Preliminary

4-7


To understand the round-to-nearest-even method, consider the following example involving the rounding of a 32-bit number, R0, to a 16-bit number. Using this method, the 32-bit number is rounded to the closest

16-bit number possible. Let the high-order 16 bits of R0 be named R0.U and the low-order 16 bits be R0.L.

• If R0.L is less than 0x8000, the result is truncated to the value of R0.U.

• If R0.L is greater than 0x8000, the upper word is incremented (rounded up).

• If R0.L is 0x8000, R0 is half-way between two 16-bit numbers. In this case, rounding is based on the lsb of R0.U, so the result is always even (lsb = 0).

— If the lsb of R0.U = 1 and R0.L = 0x8000, the number is rounded up.

— If the lsb of R0.U = 0 and R0.L =0x8000, the number is rounded down.

This method minimizes rounding bias and creates as statistically correct an answer as possible.

The rounding algorithm is summarized in the following pseudocode: if R0.L < 0x8000 then Result = R0.U

else if R0.L > 0x8000 then Result = R0.U + 1 else if lsb of R0.U = 0 then Result = R0.U

else Result = R0.U + 1

/* R0.L = 0x8000 */

The round-to-nearest-even technique is also known as convergent rounding.

4.4.1.1.2

Saving and Restoring the EMAC Programming Model

The presence of rounding logic in the output datapath of the EMAC requires that special care be taken during the EMAC’s save/restore process. In particular, any result rounding modes must be disabled during the save/restore process so the exact bit-wise contents of the EMAC registers are accessed. Consider the following memory structure containing the EMAC programming model: int acc0; int acc1; int acc2; int acc3; int accext01; int accext02; int mask; int macsr;

} macState;

The following assembly language routine shows the proper sequence for a correct EMAC state save. This code assumes all Dn and An registers are available for use and the memory location of the state save is defined by A7.

EMAC_state_save: move.l macsr,d7 clr.l d0 move.l d0,macsr move.l acc0,d0 move.l acc1,d1 move.l acc2,d2 move.l acc3,d3

; save the macsr

; zero the register to ...

; disable rounding in the macsr

; save the accumulators

4-8



Preliminary

Enhanced Multiply-Accumulate Unit (EMAC) move.l accext01,d4 move.l accext23,d5 move.l mask,d6 movem.l #0x00ff,(a7)

; save the accumulator extensions

; save the address mask

; move the state to memory

The following code performs the EMAC state restore:

EMAC_state_restore: movem.l (a7),#0x00ff move.l #0,macsr move.l d0,acc0 move.l d1,acc1 move.l d2,acc2 move.l d3,acc3 move.l d4,accext01 move.l d5,accext23 move.l d6,mask move.l d7,macsr

; restore the state from memory

; disable rounding in the macsr

; restore the accumulators

; restore the accumulator extensions

; restore the address mask

; restore the macsr

By executing this type of sequence, the exact state of the EMAC programming model can be correctly saved and restored.

4.4.1.1.3

MULS/MULU

MULS and MULU are unaffected by fractional mode operation; operands are still assumed to be integers.

4.4.1.1.4

Scale Factor in MAC or MSAC Instructions

The scale factor is ignored while the MAC is in fractional mode.

4.4.2

Mask Register (MASK)

The 32-bit MASK implements the low-order 16 bits to minimize the alignment complications involved with loading and storing only 16 bits. When the MASK is loaded, the low-order 16 bits of the source operand are actually loaded into the register. When it is stored, the upper 16 bits are all forced to ones.

This register performs a simple AND with the operand address for MAC instructions. That is, the processor calculates the normal operand address and, if enabled, that address is then ANDed with

{0xFFFF, MASK[15:0]} to form the final address. Therefore, with certain MASK bits cleared, the operand address can be constrained to a certain memory region. This is used primarily to implement circular queues in conjunction with the (An)+ addressing mode.

This feature minimizes the addressing support required for filtering, convolution, or any routine that implements a data array as a circular queue. For MAC + MOVE operations, the MASK contents can optionally be included in all memory effective address calculations. The syntax is as follows:

MAC.sz Ry,RxSF,<ea>y&,Rw

The & operator enables the use of MASK and causes bit 5 of the extension word to be set. The exact algorithm for the use of MASK is as follows:



Preliminary

4-9

Enhanced Multiply-Accumulate Unit (EMAC) if extension word, bit [5] = 1, the MASK bit, then if <ea> = (An) oa = An & {0xFFFF, MASK} if <ea> = (An)+ oa = An

An = (An + 4) & {0xFFFF, MASK} if <ea> =-(An) oa = (An - 4) & {0xFFFF, MASK}

An = (An - 4) & {0xFFFF, MASK} if <ea> = (d16,An) oa = (An + se_d16) & {0xFFFF0x, MASK}

Here, oa is the calculated operand address and se_d16 is a sign-extended 16-bit displacement. For auto-addressing modes of post-increment and pre-decrement, the calculation of the updated An value is also shown.

Use of the post-increment addressing mode, {(An)+} with the MASK is suggested for circular queue implementations.

Address: CPU @ 0x805 (MASK) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

Mask

W

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 4-5. Mask Register (MASK)

4.4.3

Accumulator Registers (ACC0–3)

The accumulator registers store 32-bits of the MAC operation result. The accumulator extension registers are used to form the entire 48-bit result.

Address: CPU @ 0x806 (ACC0)

CPU @ 0x809 (ACC1)

CPU @ 0x80A (ACC2)

CPU @ 0x80B (ACC3)


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

Accumulator

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 4-6. Accumulator Registers (ACC0–3)

4.4.4

Accumulator Extension Registers (ACCext01, ACCext23)

Each pair of 8-bit accumulator extension fields are concatenated with the corresponding 32-bit accumulator register to form the 48-bit accumulator. For more information on their use, see

Section 4.3,

“General Operation.”

4-10



Preliminary


Address: CPU @ 0x807 (ACCext01) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

Accumulator 0 Upper

Extension Byte

Accumulator 0 Lower

Extension Byte

Accumulator 1 Upper

Extension Byte

Accumulator 1 Lower

Extension Byte

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 4-7. Accumulator Extension Register (ACCext01)

Address: CPU @ 0x808 (ACCext23) Access: User read/write

R

W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Accumulator 2 Upper

Extension Byte

Accumulator 2 Lower

Extension Byte

Accumulator 3 Upper

Extension Byte

Accumulator 3 Lower

Extension Byte

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 4-8. Accumulator Extension Register (ACCext23)

4.5

EMAC Instruction Set Summary

Table 4-4

summarizes EMAC unit instructions.

Table 4-4. EMAC Instruction Summary

Command Mnemonic Description

Multiply Signed

Multiply Unsigned

Multiply Accumulate

MULS <ea>y,Dx

MULU <ea>y,Dx

MAC Ry,RxSF,ACCx

MSAC Ry,RxSF,ACCx

Multiplies two signed operands yielding a signed result

Multiplies two unsigned operands yielding an unsigned result

Multiplies two operands and adds/subtracts the product to/from an accumulator

MAC Ry,Rx,<ea>y,Rw,ACCx

MSAC Ry,Rx,<ea>y,Rw,ACCx

Multiplies two operands and combines the product to an accumulator while loading a register with the memory operand

Multiply Accumulate with Load

Load Accumulator

Store Accumulator

Copy Accumulator

Load MACSR

MOV.L {Ry,#imm},ACCx

MOV.L ACCx,Rx

MOV.L ACCy,ACCx

MOV.L {Ry,#imm},MACSR

Store MACSR MOV.L MACSR,Rx

Store MACSR to CCR MOV.L MACSR,CCR

Load MAC Mask Reg MOV.L {Ry,#imm},MASK

Store MAC Mask Reg MOV.L MASK,Rx

Loads an accumulator with a 32-bit operand

Writes the contents of an accumulator to a CPU register

Copies a 48-bit accumulator

Writes a value to MACSR

Write the contents of MACSR to a CPU register

Write the contents of MACSR to the CCR

Writes a value to the MASK register

Writes the contents of the MASK to a CPU register

Load AccExtensions01 MOV.L {Ry,#imm},ACCext01 Loads the accumulator 0,1 extension bytes with a 32-bit operand

Load AccExtensions23 MOV.L {Ry,#imm},ACCext23 Loads the accumulator 2,3 extension bytes with a 32-bit operand



Preliminary

4-11


Table 4-4. EMAC Instruction Summary (continued)

Command Mnemonic

Store AccExtensions01 MOV.L ACCext01,Rx

Store AccExtensions23 MOV.L ACCext23,Rx

Description

Writes the contents of accumulator 0,1 extension bytes into a

CPU register

Writes the contents of accumulator 2,3 extension bytes into a

CPU register

4.5.1

EMAC Instruction Execution Times

The instruction execution times for the EMAC can be found in Section 3.11, “EMAC Instruction

Execution Times.”

The EMAC execution pipeline overlaps the AGEX stage of the OEP; that is, the first stage of the EMAC pipeline is the last stage of the basic OEP. EMAC units are designed for sustained, fully-pipelined operation on accumulator load, copy, and multiply-accumulate instructions. However, instructions that store contents of the multiply-accumulate programming model can generate OEP stalls that expose the

EMAC execution pipeline depth, as in the following: mac.w

mov.l

Ry, Rx, Acc0

Acc0, Rz

The mov.l instruction that stores the accumulator to an integer register (Rz) stalls until the program-visible

copy of the accumulator is available. Figure 4-9 shows EMAC timing.

DSOC

AGEX mac mac

Three-cycle regBusy stall mov mov mov

EMAC EX1

EMAC EX2

EMAC EX3

EMAC EX4

Accumulator 0 mac mac mac mac mov old new

Figure 4-9. EMAC-Specific OEP Sequence Stall

In Figure 4-9 , the OEP stalls the store-accumulator instruction for 3 cycles: the depth of the EMAC

pipeline minus 1. The minus 1 factor is needed because the OEP and EMAC pipelines overlap by a cycle, the AGEX stage. As the store-accumulator instruction reaches the AGEX stage where the operation is performed, the just-updated accumulator 0 value is available.

4-12



Preliminary


As with change or use stalls between accumulators and general-purpose registers, introducing intervening instructions that do not reference the busy register can reduce or eliminate sequence-related store-MAC instruction stalls. In fact, a major benefit of the EMAC is the addition of three accumulators to minimize stalls caused by exchanges between the accumulator(s) and the general-purpose registers.

4.5.2

Data Representation

MACSR[S/U,F/I] selects one of the following three modes, where each mode defines a unique operand type:

1. Two’s complement signed integer: In this format, an N-bit operand value lies in the range -2

(N-1)

< operand < 2

(N-1)

- 1. The binary point is right of the lsb.

2. Unsigned integer: In this format, an N-bit operand value lies in the range 0 < operand < 2

N binary point is right of the lsb.

- 1. The

3. Two’s complement, signed fractional: In an N-bit number, the first bit is the sign bit. The remaining bits signify the first N-1 bits after the binary point. Given an N-bit number, its value is given by the equation in

Equation 4-3

.

a

N-1 a

N-2 a

N-3

... a

2 a

1 a

0

, value = – ( ) +

∑

2

( ) ⋅ ai i = 0

This format can represent numbers in the range -1 < operand < 1 - 2

(N-1)

.

Eqn. 4-3

For words and longwords, the largest negative number that can be represented is -1, whose internal representation is 0x8000 and 0x8000_0000, respectively. The largest positive word is 0x7FFF or (1 - 2

-15 the most positive longword is 0x7FFF_FFFF or (1 - 2

-31

).

);

4.5.3

MAC Opcodes

MAC opcodes are described in the ColdFire Programmer’s Reference Manual .

Note the following:

• Unless otherwise noted, the value of MACSR[N,Z] is based on the result of the final operation that involves the product and the accumulator.

• The overflow (V) flag is handled differently. It is set if the complete product cannot be represented as a 40-bit value (this applies to 32 × 32 integer operations only) or if the combination of the product with an accumulator cannot be represented in the given number of bits. The EMAC design includes an additional product/accumulation overflow bit for each accumulator that are treated as sticky indicators and are used to calculate the V bit on each MAC or MSAC instruction. See

Section 4.4.1, “MAC Status Register (MACSR) .”

• For the MAC design, the assembler syntax of the MAC (multiply and add to accumulator) and

MSAC (multiply and subtract from accumulator) instructions does not include a reference to the single accumulator. For the EMAC, it is expected that assemblers support this syntax and that no explicit reference to an accumulator is interpreted as a reference to ACC0. These assemblers would also support syntaxes where the destination accumulator is explicitly defined.



Preliminary

4-13


• The optional 1-bit shift of the product is specified using the notation {<< | >>} SF, where <<1 indicates a left shift and >>1 indicates a right shift. The shift is performed before the product is added to or subtracted from the accumulator. Without this operator, the product is not shifted. If the

EMAC is in fractional mode (MACSR[F/I] is set), SF is ignored and no shift is performed. Because a product can overflow, the following guidelines are implemented:

— For unsigned word and longword operations, a zero is shifted into the product on right shifts.

— For signed, word operations, the sign bit is shifted into the product on right shifts unless the product is zero. For signed, longword operations, the sign bit is shifted into the product unless an overflow occurs or the product is zero, in which case a zero is shifted in.

— For all left shifts, a zero is inserted into the lsb position.

The following pseudocode explains basic MAC or MSAC instruction functionality. This example is presented as a case statement covering the three basic operating modes with signed integers, unsigned integers, and signed fractionals. Throughout this example, a comma-separated list in curly brackets, {}, indicates a concatenation operation.

switch (MACSR[6:5])

{ case 0:

/* MACSR[S/U, F/I] */

/* signed integers */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then {

MACSR.PAVn = 0

/* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {sign-extended Ry[31], Ry[31:16]} else operandY[31:0] = {sign-extended Ry[15], Ry[15:0]} if (U/Lx == 1) then operandX[31:0] = {sign-extended Rx[31], Rx[31:16]} else operandX[31:0] = {sign-extended Rx[15], Rx[15:0]}

} else {operandY[31:0] = Ry[31:0] operandX[31:0] = Rx[31:0]

}

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */ if ((product[63:39] != 0x0000_00_0) && (product[63:39] != 0xffff_ff_1)) then { /* product overflow */

MACSR.PAVn = 1

MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then if (product[63] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ if (product[63] == 1) then result[47:0] = 0xffff_8000_0000 else result[47:0] = 0x0000_7fff_ffff

}

4-14



Preliminary


/* sign-extend to 48 bits before performing any scaling */ product[47:40] = {8{product[39]}} /* sign-extend */

/* scale product before combining with accumulator */ switch (SF)

{

/* 2-bit scale factor */ case 0: break;

/* no scaling specified */ case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: break; case 3:

/* reserved encoding */

/* SF = “>> 1” */ product[39:0] = {product[39], product[39:1]} break;

} if (MACSR.PAVn == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0]

}

/* check for accumulation overflow */ if (accumulationOverflow == 1) then {MACSR.PAVn = 1

MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x0000_7fff_ffff else result[47:0] = 0xffff_8000_0000

}

/* transfer the result to the accumulator */

ACCx[47:0] = result[47:0]

}

MACSR.V = MACSR.PAVn

MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:31] == 0x0000_0) || (ACCx[47:31] == 0xffff_1)) then MACSR.EV = 0 else MACSR.EV = 1 break; case 1,3: /* signed fractionals */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then {

MACSR.PAVn = 0 if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {Ry[31:16], 0x0000} else operandY[31:0] = {Ry[15:0], 0x0000} if (U/Lx == 1)



Preliminary

4-15

Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {Rx[31:16], 0x0000} else operandX[31:0] = {Rx[15:0], 0x0000}


}

/* perform the multiply */ product[63:0] = (operandY[31:0] * operandX[31:0]) << 1

/* check for product rounding */ if (MACSR.R/T == 1) then { /* perform convergent rounding */ if (product[23:0] > 0x80_0000) then product[63:24] = product[63:24] + 1 else if ((product[23:0] == 0x80_0000) && (product[24] == 1)) then product[63:24] = product[63:24] + 1

}

/* sign-extend to 48 bits and combine with accumulator */

/* check for the -1 * -1 overflow case */ if ((operandY[31:0] == 0x8000_0000) && (operandX[31:0] == 0x8000_0000)) then product[71:64] = 0x00 else product[71:64] = {8{product[63]}}

/* zero-fill */

/* sign-extend */ if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[71:24] else result[47:0] = ACCx[47:0] + product[71:24]


MACSR.V = 1 if (MACSR.OMC == 1) then /* accumulation overflow, saturationMode enabled */ if (result[47] == 1) then result[47:0] = 0x007f_ffff_ff00 else result[47:0] = 0xff80_0000_0000

}



}


MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) break; then MACSR.Z = 1 else MACSR.Z = 0 if ((ACCx[47:39] == 0x00_0) || (ACCx[47:39] == 0xff_1)) then MACSR.EV = 0 else MACSR.EV = 1 case 2: /* unsigned integers */ if (MACSR.OMC == 0 || MACSR.PAVn == 0) then {

MACSR.PAVn = 0

/* select the input operands */ if (sz == word) then {if (U/Ly == 1) then operandY[31:0] = {0x0000, Ry[31:16]} else operandY[31:0] = {0x0000, Ry[15:0]} if (U/Lx == 1)

4-16



Preliminary

Enhanced Multiply-Accumulate Unit (EMAC) then operandX[31:0] = {0x0000, Rx[31:16]} else operandX[31:0] = {0x0000, Rx[15:0]}


}

/* perform the multiply */ product[63:0] = operandY[31:0] * operandX[31:0]

/* check for product overflow */ if (product[63:40] != 0x0000_00) then { /* product overflow */

MACSR.PAVn = 1

MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */ result[47:0] = 0xffff_ffff_ffff

}

/* zero-fill to 48 bits before performing any scaling */ product[47:40] = 0 /* zero-fill upper byte */

/* scale product before combining with accumulator */ switch (SF)

{

/* 2-bit scale factor */ case 0: break;

/* no scaling specified */ case 1: /* SF = “<< 1” */ product[40:0] = {product[39:0], 0} break; case 2: break; case 3:

/* reserved encoding */

/* SF = “>> 1” */ product[39:0] = {0, product[39:1]} break;

}

/* combine with accumulator */ if (MACSR.PAVn == 0) then {if (inst == MSAC) then result[47:0] = ACCx[47:0] - product[47:0] else result[47:0] = ACCx[47:0] + product[47:0]

}


MACSR.V = 1 if (inst == MSAC && MACSR.OMC == 1) then result[47:0] = 0x0000_0000_0000 else if (MACSR.OMC == 1) then /* overflowed MAC, saturationMode enabled */



Preliminary

4-17

Enhanced Multiply-Accumulate Unit (EMAC) result[47:0] = 0xffff_ffff_ffff

}

}



}


MACSR.N = ACCx[47] if (ACCx[47:0] == 0x0000_0000_0000) then MACSR.Z = 1 else MACSR.Z = 0 break; if (ACCx[47:32] == 0x0000) then MACSR.EV = 0 else MACSR.EV = 1

4-18



Preliminary

Chapter 5 Cryptographic Acceleration Unit

This chapter describes the Cryptographic Acceleration Unit (CAU) programming model. The CAU is an instruction level coprocessor that is accessed with ColdFire coprocessor instructions (see section XX). The

CAU supports acceleration of the following cryptographic algorithms: DES, 3DES, AES, MD5 and

SHA-1.

NOTE

To enhance readability, this chapter shows the CAU as coprocessor 0.

Future implementations could have the CAU designated as coprocessor 1.

5.1

CAU Registers

The CAU register file consists of eight, 32-bit registers as shown in Table 5-1

. All registers can be read with the coprocessor store instruction (cp0st.l) and written with the coprocessor load instruction (cp0ld.l).

However, only bits 0-1 of the CASR are writable. Bits 2-27 of CASR loads should be 0 for compatibility with future versions of the CAU. The CAU only supports long word accesses and register codes 0x8-0xF are reserved.

Table 5-1. CAU Register File

Code

6

7

4

5

2

3

0

1

Name

CASR

CAA

CA0

CA1

CA2

CA3

CA4

CA5

Description status register accumulator general purpose 0 general purpose 1 general purpose 2 general purpose 3 general purpose 4 general purpose 5

DES AES SHA-1 MD5

--

--

L

R

--

--

C

D

--

--

W0

W1

W2

W3

--

--

--

T

A

B

C

D

E

W

--

-c d

-b

-a

5.1.1

CAU Status Register

The status register (CASR) contains all of the status and configuration for the CAU. It has three defined fields and 26 bits reserved as shown in

Figure 5-1 <f-helvetica><st-bold>Figure 5-1..



Preliminary

5-1


31

R

W

RESET: 0

30

VER

29

0 0

28

1

27

0

0

26

0

0

25

0

0

24

0

0

23

0

0

22

0

0

21

0

0

20

0

0

19

0

0

18

0

0

17

0

0

16

0

0

R

W

RESET:

15

0

0

14

0

0

13

0

0

12

0

0

11

0

0

10

0

0

9

0

0

8

0

0

7

0

0

6

0

0

= Read Only or Reserved

Figure 5-1. Status Register (CASR)

IC — Illegal Command

1 = Illegal coprocessor command issued

0 = No illegal commands issued

DPE — DES Parity Error

1 = DES key parity error detected

0 = No error detected

VER — CAU Version

Indicates CAU version; only version 1 is defined.

5

0

0

4

0

0

3

0

0

2

0

0

1 0

DPE IC

0 0

5.2

CAU Operation

The cp0ld.l instruction is used to write to CAU registers and specify CAU operations. Operand 1 of the instruction is the source operand (if any) and the CAU destination register is encoded in the CMD field.

All CAU load instruction commands have an execution time specifier of 0.

The cp0st.l instruction is used to read CAU registers. The CAU source register is encoded in the CMD.

The CAU only supports long word stores. The CAU store instruction command has an execution time specifier of 0.

5.3

CAU Commands

The CAU supports 22 commands as shown in

Table 5-2

and described in the following sections, (see

section Section 5.4, “CAU Equate Values

“ for assembly constant definitions). All other encodings are reserved. The IC bit in the CASR will be set if any command is issued that is not defined in the encodings described in this section. A specific illegal command (ILL) is defined to allow for software self checking.

Reserved commands should not be issued to ensure compatibility with future implementations.

NOTE

The value CAx is any CAU register (CASR, CAA, CA0-CA5).

5-2



Preliminary

Inst Type cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0st.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l

cp0ld.l


Table 5-2. CAU Commands

Command

Name

MVRA

MVAR

AESS

AESIS

AESC

AESIC

AESR

AESIR

DESR

DESK

CNOP

LDR

STR

ADR

RADR

ADRA

XOR

ROTL

HASH

SHS

MDS

ILL

Description

No Operation

Load Reg

Store Reg

Add

Reverse and Add

Add Reg to Acc

Exclusive Or

Rotate Left

Move Reg to Acc

Move Acc to Reg

AES Sub Bytes

AES Inv Sub Bytes

AES Column Op

AES Inv Column Op

AES Shift Rows

AES Inv Shift Rows

DES Round

DES Key Setup

Hash Function

Secure Hash Shift

Message Digest Shift

Illegal Command

CMD[8:4]

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x10

0x11

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

0x12

0x13

0x14

0x1F

CMD[3:0] Operation

CAx

CAx

CAx

CAx

CAx

CAx

0x0

0x0

0x0

CAx

CAx

CAx

CAx

CAx

CAx

CAx

---

Op1 -> CAx

CAx -> Destination

CAx + Op1 -> CAx

CAx + ByteRev(Op1) -> CAx

CAx + CAA -> CAA

CAx ^ Op1 -> CAx

CAx <<< Op1 -> CAx

CAx -> CAA

CAA -> CAx

SubBytes(CAx) -> CAx

InvSubBytes(CAx) -> CAx

MixColumns(CAx)^Op1 -> CAx

InvMixColumns(CAx^Op1) -> CAx

ShiftRows(CA0-CA3) -> CA0-CA3

InvShiftRows(CA0-CA3) -> CA0-CA3

IP FP KS[1:0] DES Round(CA0-CA3)->CA0-CA3

0 0 CP DC DES Key Op(CA0-CA1)->CA0-CA1

Key Parity Error & CP -> CASR[1]

0 HF[2:0]

0x0

Hash Func(CA1-CA3)+CAA->CAA

CAA <<< 5 -> CAA,

CAA->CA0, CA0->CA1,

CA1 <<< 30 -> CA2,

CA2->CA3, CA3->CA4

0x0

0x0

CA3-> CAA, CAA->CA1, CA1->CA2,

CA2->CA3,

0x1->CASR[0]

5.3.1

CNOP - coprocessor no operation

cp0ld.l #CNOP

The CNOP command is the coprocessor cp0nop instruction defined for synchronization.

5.3.2

LDR - load register

cp0ld.l <ea>,#LDR+CAx

The LDR command loads CAx with the source data specified by <ea>.

5.3.3

STR - store register

cp0st.l <ea>,#STR+CAx

The STR command stores the value from CAx to the destination specified by <ea>.



Preliminary

5-3


5.3.4

ADR - add to register

cp0ld.l <ea>,#ADR+CAx

The ADR command adds the source operand specified by <ea> to CAx and stores the result in CAx.

5.3.5

RADR - reverse and add to register

cp0ld.l <ea>,#RADR+CAx

The RADR command does a byte reverse on the source operand specified by <ea>, adds that value to CAx and stores the result in CAx. An example is shown in

Table 5-3 .

Table 5-3. RADR Command Example

Operand

01020304

CAx Before

A0B0C0D0

CAx After

A4B3C2D1

5.3.6

ADRA - add register to accumulator

cp0ld.l #ADRA+CAx

The ADRA command adds CAx to CAA and stores the result in CAA.

5.3.7

XOR - exclusive or

cp0ld.l <ea>,#XOR+CAx

The XOR command does an exclusive or of the source operand specified by <ea> with CAx and stores the result in CAx.

5.3.8

ROTL - rotate left

cp0ld.l <ea>,#ROTL+CAx

The ROTL rotates the bits of CAx to the left with the result stored back to CAx. The number of bits to rotate is the value specified by <ea> modulo 32.

5.3.9

MVRA - move register to accumulator

cp0ld.l #MVRA+CAx

The MVRA moves the value from the source register CAx to the destination register CAA.

5.3.10

MVAR - move accumulator to register

cp0ld.l #MVAR+CAx

The MVRA command moves the value from source register CAA to the destination register CAx.

5-4



Preliminary


5.3.11

AESS - AES substitution

cp0ld.l #AESS+CAx

The AESS command performs the AES byte substitution operation on CAx and stores the result back to

CAx.

5.3.12

AESIS - AES inverse substitution

cp0ld.l #AESIS+CAx

The AESIS command performs the AES inverse byte substitution operation on CAx and stores the result back to CAx.

5.3.13

AESC - AES column operation

cp0ld.l <ea>,#AESC+CAx

The AESC command performs the AES columns operation on the contents of CAx then performs an exclusive or of that result with the source operand specified by <ea> and stores the result in CAx.

5.3.14

AESIC - AES inverse column operation

cp0ld.l <ea>,#AESIC+CAx

The AESIC command performs an exclusive or operation of the source operand specified by <ea> on the contents of CAx followed by the AES inverse mix columns operation on that result and stores the result back in CAx.

5.3.15

AESR - AES shift rows

cp0ld.l #AESR

The AESR command performs the AES shift rows operation on registers CA0, CA1, CA2 and CA3. An example is shown in

Table 5-4

.

Table 5-4. AESR Command Example

Register

CA0

CA1

CA2

CA3

Before

01020304

05060708

090A0B0C

0D0E0F00

After

01060B00

050A0F04

090E0308

0D02070C

5.3.16

AESIR - AES inverse shift rows

cp0ld.l #AESIR

The AESR command performs the AES inverse shift rows operation on registers CA0, CA1, CA2 and

CA3. An example is shown in Table 5-5 .



Preliminary

5-5


Table 5-5. AESIR Command Example

Register

CA0

CA1

CA2

CA3

Before

01060B00

050A0F04

090E0308

0D02070C

After

01020304

05060708

090A0B0C

0D0E0F00

5.3.17

DESR - DES round

cp0ld.l #DESR+{IP}+{FP}+{KSx}

The DESR command performs a round of the DES algorithm and a key schedule update with the following source and destination designations: CA0=C, CA1=D, CA2=L, CA3=R. If the IP bit is set then the DES initial permutation is performed on CA2 and CA3 before the round operation. If the FP bit is set then the

DES final permutation (inverse initial permutation) is performed on CA2 and CA3 after the round operation. The round operation uses the source values from registers CA0 and CA1 for the key addition operation. The KSx field specifies the shift to use for the key schedule operation used to update the values

in CA0 and CA1. The specific shift function performed is based on the KSx field as defined in Table 5-6

.

Table 5-6. Key Shift Function Codes

KSx

Code

2

3

0

1

KSx

Define

KSL1

KSL2

KSR1

KSR2

Shift Function

Left 1

Left 2

Right 1

Right 2

5.3.18

DESK - DES key setup

cp0ld.l #DESK+{CP}+{DC}

The DESK command performs the initial key transformation (permuted choice 1) defined by the DES algorithm on CA0 and CA1 with CA0 containing bits 1-32 of the key and CA1 containing bits 33-64 of the key

1

. If the DC bit is set then no shift operation is performed and the values C

0

and D

0

are stored back to CA0 and CA1 respectively. The DC bit should be set for decrypt operations. If the DC bit is not set then a left shift by 1 is also performed and the values C

1

and D

1

are stored back to CA0 and CA1 respectively.

The DC bit should be 0 for encrypt operations. If the CP bit is set and a key parity error is detected then the DPE bit of the CASR is set, otherwise it is cleared.

5.3.19

HASH - hash function

cp0ld.l #HASH+HFx

The HASH command performs a hashing operation on CA1, CA2 and CA3 and adds that result to the value in CAA and stores the result in CAA. The specific hash function performed is based on the HFx field

as defined in Table 5-7 .

1.The DES algorithm numbers the most significant bit of a block as bit1 and the least significant as bit 64.

5-6



Preliminary

HFx

Code

2

3

0

1

4

5

HFx

Define

HFF

HFG

HFH

HFI

HFC

HFM


Table 5-7. Hash Function Codes

Hash Function

MD5 F()

MD5 G()

MD5 H(), SHA Parity()

MD5 I()

SHA Ch()

SHA Maj()

Hash Logic

CA1&CA2 | ~CA1&CA3

CA1&CA3 | CA2&~CA3

CA1^CA2^CA3

CA2^(CA1|~CA3)

CA1&CA2 ^ ~CA1&CA3

CA1&CA2 ^ CA1&CA3 ^ CA2&CA3

5.3.20

SHS - secure hash shift

cp0ld.l #SHS

The SHS command does a set of register to register move and shift operations in parallel that is useful for implementing SHA-1. The following source and destination assignments are made: CAA=CAA<<<5,

CA0=CAA, CA1=CA0, CA2=CA1<<<30, CA3=CA2, CA4=CA3.

5.3.21

MDS - message digest shift

cp0ld.l #MDS

The MDS command does a set of register to register move operations in parallel that is useful for implementing MD5. The following source and destination assignments are made: CAA=CA3,

CA1=CAA, CA2=CA1, CA3=CA2.

5.3.22

ILL - illegal command

cp0ld.l #ILL

The ILL command is a specific illegal command that sets the IC bit in the CASR. All undefined commands are reserved for use in future implementations.

5.4

CAU Equate Values

; CAU Registers (CAx)

.set CASR,0x0

.set CAA,0x1

.set CA0,0x2

.set CA1,0x3

.set CA2,0x4

.set CA3,0x5

.set CA4,0x6

.set CA5,0x7

; CAU Commands

.set CNOP,0x000

.set LDR,0x010

.set STR,0x020

.set ADR,0x030



Preliminary

5-7


.set RADR,0x040

.set ADRA,0x050

.set XOR,0x060

.set ROTL,0x070

.set MVRA,0x080

.set MVAR,0x090

.set AESS,0x0A0

.set AESIS,0x0B0

.set AESC,0x0C0

.set AESIC,0x0D0

.set AESR,0x0E0

.set AESIR,0x0F0

.set DESR,0x100

.set DESK,0x110

.set HASH,0x120

.set SHS,0x130

.set MDS,0x140

.set ILL,0x1F0

; DESR Fields

.set IP,0x08 ; initial permutation

.set FP,0x04 ; final permutation

.set KSL1,0x00 ; key schedule left 1 bit

.set KSL2,0x01 ; key schedule left 2 bits

.set KSR1,0x02 ; key schedule right 1 bit

.set KSR2,0x03 ; key schedule right 2 bits

; DESK Field

.set DC,0x01 ; decrypt key schedule

.set CP,0x02 ; check parity

; HASH Functions Codes

.set HFF,0x0 ; MD5 F() CA1&CA2 | ~CA1&CA3

.set HFG,0x1 ; MD5 G() CA1&CA3 | CA2&~CA3

.set HFH,0x2 ; MD5 H(), SHA Parity() CA1^CA2^CA3

.set HFI,0x3 ; MD5 I() CA2^(CA1|~CA3)

.set HFC,0x4 ; SHA Ch() CA1&CA2 ^ ~CA1&CA3

.set HFM,0x5 ; SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3

5-8



Preliminary

Chapter 6 Random Number Generator Accelerator (RNGA)

A top level block diagram of the RNGA is shown in Figure 6-1 . The module is connects to the IP Bus

defined in SRS version 3.1.1 IP Interface Specification.

Output Register

RNGA Core/Control

Logic

Internal

Bus

Figure 6-1. RNGA Block Diagram

6.1

Overview

The RNGA (Random Number Generator Accelerator) module is a digital integrated circuit capable of generating 32-bit random numbers. It is designed to comply with FIPS-140 standards for randomness and non-determinism. The random bits are generated by clocking shift registers with clocks derived from ring oscillators. The configuration of the shift registers ensures statistically good data (i.e. data that looks random). The oscillators with their unknown frequencies provide the required entropy needed to create random data.

It is important to note that there is no known cryptographic proof showing that this is a secure method of generating random data. In fact, there may be an attack against the random number generator described in this document if its output is used directly in a cryptographic application (the attack is based on the linearity of the internal shift registers). In light of this, it is highly recommended that the random data produced by this module be used as an input seed to a NIST approved (based on DES or SHA-1) or cryptographically secure (RSA Generator or BBS Generator) random number generation algorithm. It is also recommended that other sources of entropy be used along with the RNGA to generate the seed to the pseudorandom algorithm. The more random sources combined to create the seed the better. The following is a list of sources which could be easily combined with the output of this module.

• Current time using highest precision possible.

• Mouse and keyboard motions (or equivalent if being used on a cell phone or PDA).

• Other entropy supplied directly by the user.


Freescale Semiconductor Preliminary 6-1


6.2

Features

The RNGA includes these distinctive features:

• 32-bit interface

• 32-bit Output Register

• secure mode

• power saving mode

6.3

Modes of Operation

Although the RNGA has several modes, only one is intended for use during normal operation. The other modes were created to aid in verification and testability of the module. The Normal and Oscillator

Frequency Test Modes are entered by setting the appropriate bits in the RNGA Mode register. The Sleep

Mode is entered by setting the appropriate bit in the RNGA Control register. These registers are described in more detail in

Section 6.4.1, “.Register Descriptions

.

• Normal Mode

In this mode the RNGA generates random data. Since this is the default mode of operation, the user is not required to change the mode before requesting random data. This is also the only valid mode when in the secure state. While in this mode, the internal shift registers are driven by internally generated clocks with unknown frequency. Depending on the internal state of the RNGA, these clocks are derived from either the RNGA’s oscillators or a deterministic clock (based on the system clock). For simplicity sake, throughout the rest of this document these clocks will be referred to as the oscillator clocks.

• Secure Mode

In this mode the RNGA is forced into the Normal mode described above. Secure Mode is equivalent to the condition where the RNGA is in Normal mode and is unable to exit that mode. The low power

Sleep Mode can be entered while in the Secure Mode.

• Verification Mode

This mode is provided for verification and testing of the module. While in this mode, the random output is generated by a counter rather than the usual shift registers. The deterministic result allows for easy verification of the surrounding RNGA control logic.

• Oscillator Frequency Test Mode

This mode is provided for testing of the RNGA’s ring oscillators. While in this mode, the shift registers are clocked exclusively by the oscillator clocks (this may not be the case in the Normal

Mode) allowing the oscillator frequency counters (described in Section 6.4.1, “.Register

Descriptions ) to accurately count the pulses received from the oscillator clocks during a given

amount of time.

• Sleep Mode

6-2


Preliminary Freescale Semiconductor


In this mode the RNGA’s oscillator clocks are shut off. The mode is entered by writing to the Sleep bit in the Control Register. When in this mode, the Output Register will not be loaded.

• Scan Mode

In this mode the RNGA reconfigures much of its untestable logic so it is testable by scan. The mode is entered by driving the block input ipt_mode active. This mode should only be used when scan is used to test the module.

These are high level descriptions only, detailed descriptions of operating modes are contained in later sections.

6.4


The address map for the RNGA is shown in Table 6-1 . The following subsections describe each

addressable register in more detail.

Address

0x00

0x04

0x08

0x0c

0x10

0x14

0x18

0x1c

0x20

0x24

Table 6-1. Module Memory Map

1

Use

Control

Status

Entropy Register

Output Register

Mode

Verification Control

Oscillator Control Counter

Oscillator #1 Counter

Oscillator #2 Counter

Oscillator Counter Status

Access

R/W

R

W

R

R/W

R/W

R/W

R

R

R

= Registers which are inaccessible in secure mode

1

Shaded registers are intended for factory test purposes only. Access to these registers is blocked when the RNGA is in Secure Mode

6.4.1

.

Register Descriptions

This section consists of register descriptions in address order. All RNGA_32IP registers are 32-bit access only.

6.4.1.1

Control Register

Immediately after reset the RNGA begins generating entropy in its internal shift registers. Random data is not pushed to the Output Register until after the Go bit in the Control register is set to a one. After this, a random 32-bit word is pushed to the Output Register every 256 cycles. If the Output Register is full, then



Random Number Generator Accelerator (RNGA) no push will occur. In this way the Output Register will be kept as full as possible. The fields in the Control

Register are defined in

Figure 6-2

.

R

W

RESET:

REG

ADDR

31:5

0x0000000

0x0000000

4

Sleep

0

3

0

Clear Interrupt

0

2

Interrupt

Mask

0x001F_0000

0

1

High Assurance

0

= Unimplemented or Reserved

0

Go

0

Figure 6-2. Control Register

Go

The Go Bit must be set before the RNGA will begin loading data into the Output Register. This bit is sticky and can only be cleared by a hardware reset or by changing to Secure Mode. Setting the Go bit will not bring the RNGA out of Sleep Mode. Furthermore, the Go bit does not need to be reset after exiting Sleep Mode.

1 = Output Register will be loaded with random data.

0 = Output Register is not loaded with random data.

High Assurance

While this bit is high, the RNGA will notify the SCC if a security violation occurs (i.e. the Output

Register is read while empty). This bit enables Security Violation bit in the Status Register as well as the output rnga_scc_debug port. This bit is sticky and can only be cleared through a hardware reset.

1 = Enable notification of security violations.

0 = Disable notification of security violations.

Interrupt Mask

This bit masks the error interrupt, ipi_error_int.

1 = Interrupt ipi_error_int is masked.

0 = Interrupt ipi_error_int is enabled.

Clear Interrupt

Writing a one to this bit clears the error interrupt as well as the error status bit in the Status Register.

The bit is self clearing.

1 = Clear interrupt ipi_error_int.

0 = Do not clear interrupt ipi_error_int.

Sleep

The RNGA can be placed in low power mode by either asserting the module input ipg_doze, or by setting this Sleep bit. If either of these conditions are met, the oscillators are disabled. De-asserting ipg_doze and resetting the Sleep Bit will cause the RNGA to exit Sleep Mode. The Output Register will not be pushed while the RNGA is in Sleep Mode.

1 = RNGA is in Sleep Mode.

6-4




0 = RNGA is not in Sleep Mode.

6.4.1.2

Status Register

The Status Register shown in Figure 6-3 is a read only register which reflects the internal status of the

RNGA. Only 32-bit reads of this register is supported.

R

31

Osc.

Dead

30:24

0x00

23-16

Output

Register

Size

15:8

Output

Register

Level

7:5

0x0

4

Sleep

3

Error Interrupt

2

Output

Register

Underflow

1

Last Read

Status

0

Security

Violation

W

RESET:

REG

ADDR

0 0x00 0x01 0x00 0x0 0

0x001F_0004

0 0 0 0


Figure 6-3. Status Register

Security Violation

When enabled by the High Assurance bit in the Control Register, this bit signals that a security violation has occurred. Currently, Output Register underflow is the only condition which is considered a security violation. The bit is sticky and can only be cleared by a hardware reset. The output rnga_scc_debug is driven off this bit.

1 = A security violation has occurred.

0 = No security violations have occurred or the High Assurance bit in the Control Register is not set.

Last Read Status

This bit is always enabled and reflects the status of the most recent read of the Output Register.

1 = Last read was performed while the Output Register was empty (underflow condition).

0 = Last read was performed while the Output Register was not empty.

Output Register Underflow

This bit is always enabled and signals a Output Register underflow condition. The bit is reset by reading the Status Register.

1 = The Output Register has been read while empty since last read of the Status Register.

0 = The Output Register has not been read while empty since last read of the Status Register.

Error Interrupt

This bit is always enabled and signals a Output Register underflow condition. This bit is different from the previous two bits in that it is only reset by a write to the clear interrupt bit in the Control Register.

This bit is not masked by the Interrupt Mask bit of the Control Register.

1 = The Output Register has been read while empty.

0 = The Output Register has not been read while empty.

Sleep




This bit reflects whether the RNGA is in Sleep mode (i.e. either the Sleep bit in the Control Register is set or the ipg_doze input is asserted). When this bit is a one, the RNGA is in Sleep Mode and the oscillator clocks are inactive. While in this mode, the Output Register will not be loaded and the Output

Register Level will not increase.

1 = The RNGA is in Sleep Mode.

0 = The RNGA is not in Sleep Mode.

Output Register Level

Signals how many random words are currently resident in the Output Register. The bits should be interpreted as an integer (the value 0b00001001 = signals that 0x09 random words are in the Output

Register)

Output Register Size

Signals the actual size of the Output Register. In other words, this is the maximum possible Output

Register Level. The bits should be interpreted as an integer.

Osc. Dead

Indicates that at least one of the shift registers is stuck in its reset state. This information can be used to determine whether the oscillator clocks are operational (i.e. not dead or broken). Verification of the oscillator clocks is achieved through a sequence of commands written to the Verification Control

Register (see

Section 6.4.1.6, “Verification Control Register ). First, the oscillator clocks should be

turned off. Second, the shift registers should be reset. At this point, the oscillator dead bit will assert since the shift registers are in their reset state. Finally, the oscillators should be turned back on. If the oscillator dead bit does not de-assert within a few clock cycles, the oscillators are dead.

1 = At least one oscillator is broken

0 = Both oscillators are operational

Note : This bit is intended to be used for silicon (production) test purposes and the above sequence should be followed to determine if the RNGA oscillators are functional. For simulation purposes, this bit will not be deterministic and should be masked or “don’t cared”.

6.4.1.3

Entropy Register

The Entropy Register is a write-only register which allows the user to insert entropy into the RNGA. This register allows an external user to continually seed the RNGA with externally generated random data.

Although the use of this register is recommended, it is also optional. The Entropy Register can be written at any time during operation and cannot be written too quickly.

6-6




Each time the Entropy Register is written, the written value is used to update the internal state of the

RNGA. The update is performed in such a way that the entropy in the RNGA’s internal state is preserved.

Use of the Entropy Register can increase the entropy but never decrease it.

R

W

RESET:

REG

ADDR

31:0

0x00000000

External Entropy

0x00000000

0x001F_0008


Figure 6-4. Entropy Register

External Entropy

The bits in this field are used to update the internal state of the RNGA.

6.4.1.4

Output Register

The Output Register provides temporary storage for random data generated by the RNGA. The output of the Output Register is accessible through address 0x0c in the RNGA_32IP’s address map. As long as the

Output Register is not empty, a read of this address will return 32 bits of random data. If the Output

Register is read when it is empty, Error Interrupt, Output Register Underflow and Last Read bits in the

Status Register will be set. If the interrupt is enabled in the Control Register ipi_error_int will also be driven active. If the High Assurance bit in the Control Register is set, then rnga_scc_debug will also be

driven high. The Output Register Level field in the Status Register, described in Section 6.4.1.2, “Status

Register , can be polled to monitor how many 32-bit words are currently resident in the Output Register.

When in Normal Mode, a new random word is pushed into the Output Register every 256 clock cycles (as long as the Output Register is not full). It is very important that the host polls the Status Register to make sure random values are present before reading from the Output Register.

R

W

RESET:

REG

ADDR

31:0

Random Output

0x00000000

0x001F_000C


Figure 6-5. Output Register

Random Output

32 bits of random data.




6.4.1.5

Mode Register

This register cannot be accessed when the RNGA is in the Secure Mode. The Mode register is used to

configure the RNGA’s mode of operation. Figure 6-6 shows the valid fields in the Mode Register.

R

W

RESET:

REG

ADDR

31:2

0

0x00000000

1

Oscillator Frequency

Test

0

0x001F_0010

0

Verification

0


Figure 6-6. Mode Register

Verification

When this bit is active, the RNGA is in Verification Mode. While in this mode, the pseudorandom output of the shift registers is ignored and replaced with a counter value that increments every time the output is sampled. This allows the deterministic logic around the shift registers and oscillators to be verified easily.

1 = RNGA is in Verification Mode

0 = RNGA is not in Verification Mode

Oscillator Frequency Test

When this bit is active, the RNGA is in Oscillator Frequency Test Mode. While in this mode, the

RNGA drives the shift registers with the oscillator clocks 100% of the time (while in Normal Mode, the oscillator clocks are occasionally disabled). This allows the approximate frequencies of the oscillators to be calculated accurately.

1 = RNGA is in Oscillator Frequency Test Mode

0 = RNGA is not in Oscillator Frequency Test Mode

6.4.1.6

Verification Control Register

Through use of this register, the RNGA can placed in a deterministic mode allowing verification of the design. A diagram of the register is shown in

Figure 6-7

.

6-8

R

W

RESET:

REG

ADDR

31:3

0x0000000

0x00000

2

0

Reset Shift

Registers

0

0x14

1

Force System Clock

0


Figure 6-7. Verification Control Register‘

0

Shift Clock

Off

0




Shift Clock Off

The shift registers in the RNGA are clocked by two internally generated clocks. This bit turns these internal clocks on and off.

1 = The shift register clocks are off.

0 = The shift register clocks are on.

Force System Clock

While in Normal Mode, the shift register clocks are derived from free running oscillators with unknown frequency. The shift register clocks can be made deterministic by setting this bit.

1 = The shift registers are driven by a deterministic clock derived from the system clock.

0 = The shift registers are driven by the oscillator based clocks.

Reset Shift Registers

The shift registers in the RNGA are not connected to the asynchronous reset provided to the RNGA.

In order to reset the shift registers, this self clearing bit must be set.

1 = Reset the shift registers.

0 = Do not reset the shift registers.

6.4.1.7

Oscillator Counter Control Register

This register cannot be accessed when the RNGA is in the Secure Mode. The register is used to tell the oscillator test logic how long to count the oscillator clock pulses. The value written to the register is decremented every system clock cycle (ipg_clk) until it reaches zero. When it reaches zero, the Oscillator

Counter registers are frozen (refer to

Section 6.4.1.8, “Oscillator #1 Counter and

Section 6.4.1.9,

“Oscillator #2 Counter ) allowing an outside observer to count the number of oscillator clock pulses in a

given amount of time. In turn, the approximate frequency of each oscillator clock can be computed.

R

W

RESET:

REG

ADDR

31:18

0x0000

0x0000

17:0

Number of clock cycles remaining

Number of clock cycles during which to count the oscillator clock pulses

0x01000

0x08


Figure 6-8. Oscillator Counter Control Register

6.4.1.8

Oscillator #1 Counter

This register cannot be accessed when the RNGA is in the Secure Mode. The register is used to count the number of oscillator pulses received from Oscillator #1 starting from the time the Oscillator Counter

Control Register is written and ending at the time the Oscillator Counter Control Register reaches zero.

The Oscillator #1 Counter resets when the Oscillator Counter Control Register is written to and stops incrementing when the Oscillator Counter Control Register reaches zero. This register is clocked



Random Number Generator Accelerator (RNGA) asynchronously with respect to the ipg_clk clock domain. In order to avoid unknown values during simulation and meta stable states in silicon, this register should only be read when the Oscillator Counter

Control Register is zero (i.e. when the register is not counting).

31:20

R

W

RESET: 0x000

REG

ADDR

19:0

Number of clock pulses received from Oscillator #1

0x00000

0x0C


Figure 6-9. Oscillator Counter Control Register

6.4.1.9

Oscillator #2 Counter

This register cannot be accessed when the RNGA is in the Secure Mode. This register behaves like the

Oscillator #1 Counter Register except that it is connected to the second oscillator, and it is accessed at address 0x20. Please refer to

Section 6.4.1.8, “Oscillator #1 Counter .

6.4.1.10

Oscillator Counter Status

This register cannot be accessed unless the RNGA is in the Secure Mode. The bits in this register signal that each oscillator has generated a minimum of 0x400 clock pulses each. After hardware reset, the oscillator counters will count oscillator pulses for 0x1000 system clock cycles. So, immediately after reset, the bits in this register verify that the oscillators are running at least 1/4 the frequency of the system clock.

This information may be useful on the tester where deterministic behavior is required.

R

W

RESET:

REG

ADDR

31:2

0x00000000

0x00000000

0x24


Figure 6-10. Oscillator Counter Status Register

1

Osc

#2

0

0

Osc

#1

0

Osc #1 Status

Indicates that the clock derived from the first oscillator has toggled at least 0x400 times since the last write of the Oscillator Counter Control Register (the act of resetting the RNGA can be considered such a write since the Oscillator Counter Control Register resets to a non zero value).

1 = Oscillator #1 has toggled 0x400 times

0 = Oscillator #1 has not toggled 0x400 times.

6-10



Functional Description

Osc #2 Status

Indicates that the clock derived from the second oscillator has toggled at least 0x400 times since the last write of the Oscillator Counter Control Register (the act of resetting the RNGA can be considered such a write since the Oscillator Counter Control Register resets to a non zero value).

1 = Oscillator #2 has toggled 0x400 times

0 = Oscillator #2 has not toggled 0x400 times.

6.5


The RNGA has three functional areas. They are the Output Register, IF Unit and the RNGA Core/Control

Logic blocks. Each of these can be seen in

Figure 6-1

. The following sections describe the blocks in more detail.

6.5.1

Output Register

The Output Register provides temporary storage for random data generated by the RNGA Core/Control

Logic block. For simplicity, the output of the Output Register is accessed through the interface at the

address defined in Table 6-1 . The Status register, described in

Section 6.4.1.2, “Status Register

, allows the host to monitor the number of random words in the Output Register through the Output Register Level field. If the host reads from the Output Register when it is empty and the interrupt is enabled, the RNGA will indicate an error. It is very important that the host polls the Status Register to make sure random values are present before reading from the Output Register.

6.5.2

Interface Block

This block translates the interface block signals for slave control of the RNGA. The interface supports

32-bit word aligned accesses only.

6.5.3

RNGA Core/Control Logic Block

This block contains the RNGA’s control logic as well as its core engine used to generate random data. A diagram is shown in

Figure 6-11

.




Interface control

Core Engine

(Random Number Engine) random data

Control Block

Output Register

Interface

RNGA Core/Control Logic

Figure 6-11. RNGA Logic Block Diagram

6.5.3.1

Control

The Control Block contains the address decoder, all addressable registers, and control state machines for the RNGA. This block is responsible for communication with both the Slave interface and the Output

Register interface. The block also controls the Core Engine to generate random data. The general functionality of the block is as follows. After reset, entropy is generated and stored in the RNGA’s shift registers. After the Go bit is set in the Control register is written, the Output Register is loaded with a random word every 256 cycles. The process of loading the Output Register continues as long as the Output

Register is not full.

6.5.3.2

Core Engine

The Core Engine Block contains the logic used to generate random data. The logic within the Core Engine contains the internal shift registers as well as the logic used to generate the two oscillator based clocks.

This logic is brainless and must be controlled by the Control Block. The Control Block controls how the shift registers are configured as well as when the oscillator clocks are turned on.

6.6

Initialization/Application Information

The intended general operation of the RNGA is as follows:

1. Reset/initialize

2. Write to the Control register and set the Interrupt Mask, High Assurance, and Go bits.

3. Poll Status register for Output Register level

4. Read available random data from Output Register

5. Repeat steps 3 and 4 as needed

6-12







6-14



Chapter 7

Clock Module

7.1

Introduction

The clock module allows the MCF52235 to be configured for one of several clocking methods. Clocking modes include internal phase-locked loop (PLL) clocking with either an external clock reference or an external crystal reference supported by an internal crystal amplifier. The PLL can also be disabled and an external oscillator can be used to clock the device directly. The device always comes out of reset running in external crystal mode (although this mode also supports an external clock source) with the PLL disabled. Once out of reset, it is not possible to change the input clock source, although it is possible to enable the PLL and switch between the PLL clock and the oscillator clock as the source of the system clock.The clock module contains the following:

• Crystal amplifier and oscillator (OSC)

• Phase-locked loop (PLL)

• Reduced frequency divider (RFD)

• Status and control registers

• Control logic

7.2

Features

Features of the clock module include the following:

• 25MHz crystal input

• Provides clock for integrated EPHY

• On-chip PLL can generate core frequencies up to maximum 60MHz operating frequency

7.3


The clock module can be operated in normal PLL mode, 1:1 PLL mode or external clock mode (PLL disabled).

7.3.1

Normal PLL Mode

In normal PLL mode, the PLL is fully programmable. It can synthesize frequencies ranging from 4x to 18x the reference frequency and has a post divider capable of reducing this synthesized frequency without disturbing the PLL. The PLL reference can be either a crystal oscillator or an external clock.



Preliminary

7-1

Clock Module

7.3.2

1:1 PLL Mode

In 1:1 PLL mode, the PLL synthesizes a frequency equal to the external clock input reference frequency.

The post divider is not active.

7.3.3

External Clock Mode

In external clock mode, the PLL is bypassed, and the external clock is applied to EXTAL. The resulting operating frequency is equal to the external clock frequency.

7.4

Low-power Mode Operation

This subsection describes the operation of the clock module in low-power and halted modes of operation.

Low-power modes are described in Chapter 7, “Power Management.”

Table 7-1

shows the clock module operation in low-power modes.

Table 7-1. Clock Module Operation in Low-power Modes

Low-power Mode

Wait

Clock Operation

Clocks sent to peripheral modules only

Doze

Stop

Halted

Clocks sent to peripheral modules only

All system clocks disabled

Normal

Mode Exit

Exit not caused by clock module, but normal clocking resumes upon mode exit

Exit not caused by clock module, but normal clocking resumes upon mode exit

Exit not caused by clock module, but clock sources are re-enabled and normal clocking resumes upon mode exit

Exit not caused by clock module

In wait and doze modes, the system clocks to the peripherals are enabled and the clocks to the CPU and memory are stopped. Each module can disable its clock locally at the module level.

In stop mode, all system clocks are disabled. There are several options for enabling or disabling the PLL in stop mode, compromising between stop mode current and wakeup recovery time. The PLL can be disabled in stop mode, but requires a wakeup period before it can relock.

There is also a fast wakeup option for quickly enabling the system clocks during stop recovery. This eliminates the wakeup recovery time but at the risk of sending a potentially unstable clock to the system.

To prevent a non-locked PLL frequency overshoot when using the fast wakeup option, change the RFD divisor to the current RFD value plus one before entering stop mode.

In external clock mode, there are no wakeup periods for oscillator startup or PLL lock.

7.5

Block Diagram

Figure 7-1

shows a block diagram of the entire clock module. The PLL block in this diagram is expanded

in detail in Figure 7-2 .

7-2



Preliminary

EXTAL XTAL

EXTERNAL CLOCK

OSC

STOP MODE

STPMD[1:0]

Clock Module

PLLREF

REFERENCE

CLKGEN

CLOCK

LOCEN

PLLSEL

MFD

RSTOUT

PLLMODE

CLKOUT

PLL

LOLRE LOCRE

PLL CLOCK OUT

SCALED PLL CLOCK OUT

INTERNAL CLOCK

LOCKS

LOCK

LOCS

RFD[2:0]

TO RESET

MODULE

CLKOUT

DISCLK

INTERNAL

CLOCKS

STOP MODE

PLLMODE

LOCK

FWKUP

Figure 7-1. Clock Module Block Diagram



Preliminary

7-3

Clock Module

LOCEN

REFERENCE

CLOCK

PLLSEL

DISCLK

CLKOUT

RSTOUT STPMD

LOCK

DETECT

LOLRE

PLLMODE

LOCRE

LOSS OF

CLOCK

DETECT

PHASE AND

FREQUENCY

DETECT

CHARGE

PUMP

FILTER VCO

MDF[2:0]

÷ MFD

(4–18)

LOCKS

LOCK

TO RESET

MODULE

LOCS

RFD[2:0]

SCALED PLL

CLOCK OUT

PLL CLOCK

OUT

Figure 7-2. PLL Block Diagram

7.6


The clock module signals are summarized in Table 7-2 and a brief description follows. For more detailed

information, refer to Chapter 2, “Signal Descriptions.”

Table 7-2. Signal Properties

Name

EXTAL

XTAL

CLKOUT

RSTO

Function

Oscillator or clock input

Oscillator output

System clock output

Reset signal from reset controller

7.6.1

EXTAL

This input is driven by an external clock except when used as a connection to the external crystal when using the internal oscillator.

7-4



Preliminary

Clock Module

7.6.2

XTAL

This output is an internal oscillator connection to the external crystal. If CLKMOD0 is driven low during reset, XTAL is sampled to determine clocking mode.

7.6.3

CLKOUT

This output reflects the internal system clock.

7.6.4

RSTO

The RSTO pin is asserted by one of the following:

• Internal system reset signal

• FRCRSTOUT bit in the reset control status register (RCR); see Section 9.5.1, “Reset Control

Register (RCR).”

7.7

Memory Map and Registers

The clock module programming model shown in

Table 7-3 consists of registers that define clock operation

and status as well as additional peripheral power management registers.

Table 7-3. Clock Module Memory Map

IPSBAR

Offset

1

Register

Width

(bits)


Supervisor Mode Access Only

0x0012_0000 Synthesizer Control Register (SYNCR)

0x0012_0002 Synthesizer Status Register (SYNSR)

0x0012_0006 Low Power Divider Register (LPDR)

0x0012_0008 Clock Control High Register

16

8

8

8

R/W

R

R/W

R/W

0x1002

0x00

0x00

0x00

7.7.1.1/7-6

7.7.1.2/7-8

7.7.1.3/7-9

7.7.1.4/7-10

0x0012_000C Real Time Clock Divide Register

0x0000_000C Peripheral Power Management Register High (PPMRH)

2

32

32

R/W 0x00000000

R/W 0x00000000

0x0000_0008 Peripheral Power Management Register Low (PPMRL)

2

32 R/W 0x00000001

1

2

Addresses not assigned to a register and undefined register bits are reserved for expansion.

See Section 7.2.1, “Peripheral Power Management Registers (PPMRH, PPMRL).”

7.7.1.5/7-10

7.2.1/7-1

7.2.1/7-1

7.7.1


This subsection provides a description of the clock module registers.



Preliminary

7-5

Clock Module

7.7.1.1

Synthesizer Control Register (SYNCR)

IPSBAR

Offset:

0x0012_0000 (SYNCR)

14 15

R

W

Reset

LOLRE

0

MFD2

0

13

MFD1

0

12

MFD0

11

LOCRE


10

RFD2

9

RFD1

8

RFD0

1 0 0 0 0

7 6 5 4 3 2 1 0

R

W

Reset

LOCEN DISCLK FWKUP — — CLKSRC

1

PLLMODE PLLEN

1

0 0 0 0 0 0 1 0

Figure 7-3. Synthesizer Control Register (SYNCR)

1

The reset values of PLLEN and CLKSRC are zero, as the PLL will not be enabled when the device emerges from reset).

Field

15

LOLRE

Table 7-4. SYNCR Field Descriptions

Description

Loss-of-lock reset enable. Determines how the system handles a loss-of-lock indication. When operating in normal mode or 1:1 PLL mode, the PLL must be locked before setting the LOLRE bit. Otherwise, reset is immediately asserted. To prevent an immediate reset, the LOLRE bit must be cleared before writing the

MFD[2:0] bits or entering stop mode with the PLL disabled.

0 No reset on loss of lock

1 Reset on loss of lock

Note: In external clock mode, the LOLRE bit has no effect.

7-6



Preliminary

Field

14–12

MFD

11

LOCRE

10–8

RFD

7

LOCEN

6

DISCLK

Clock Module

Table 7-4. SYNCR Field Descriptions (continued)

Description

Multiplication Factor Divider. Contain the binary value of the divider in the PLL feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one.

Note: In external clock mode, the MFD[2:0] bits have no effect.

The following table shows the system frequency multiplier of the reference frequency

1

in normal PLL mode.

MFD[2:0]

000

2

(4x)

001

(6x)

010

(8x)

(3)

011

(10x)

100

(12x)

101

(14x)

110

(16x)

111

(18x)

000 (

÷

1)

001 (

÷

2)

3

010 (

÷

4)

011 (

÷

8)

100 (

÷

16)

101 (

÷

32)

4

2

1

1/2

1/4

1/8

6

3

3/2

3/4

3/8

3/16

8

4

2

1

1/2

1/4

10

5

5/2

5/4

5/8

5/16

12

6

3

3/2

3/4

3/8

14

7

7/2

7/4

7/8

7/16

16

8

4

2

1

1/2

18

9

9/2

9/4

9/8

9/16

110 (

÷

64) 1/16 3/32 1/8 5/32 3/16 7/32 1/4 9/32

111 (

÷

128) 1/32 3/64 1/16 5/64 3/32 7/64 1/8 9/64

1

2

3 f sys

= f ref

x 2(MFD + 2)/2 exp RFD; f ref x 2(MFD + 2)

≤

80 MHz, f sys

≤

MHz

MFD = 000 not valid for f ref

< 3 MHz

Default value out of reset

Loss-of-clock reset enable. Determines how the system handles a loss-of-clock condition. When the

LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared before entering stop mode with the PLL disabled.

0 No reset on loss-of-clock

1 Reset on loss-of-clock

Note: In external clock mode, the LOCRE bit has no effect.

Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL frequency divisor; see table in MFD bit description. Changing RFD[2:0] does not affect the PLL or cause a relock delay. Changes in clock frequency are synchronized to the next falling edge of the current system clock. To avoid surpassing the allowable system operating frequency, write to RFD[2:0] only when the LOCK bit is set.

Enables the loss-of-clock function. LOCEN does not affect the loss-of-lock function.

0 Loss-of-clock function disabled

1 Loss-of-clock function enabled

Note: In external clock mode, the LOCEN bit has no effect

.

Disable CLKOUT determines whether CLKOUT is driven. Setting the DISCLK bit holds CLKOUT low.

0 CLKOUT enabled

1 CLKOUT disabled



Preliminary

7-7

Clock Module

Field

5

FWKUP

4–3

—

2

CLKSRC

1

PLLMODE

0

PLLEN

Table 7-4. SYNCR Field Descriptions (continued)

Description

Fast wakeup. Determines when the system clocks are enabled during wakeup from stop mode.

0 System clocks enabled only when PLL is locked or operating normally

1 System clocks enabled on wakeup regardless of PLL lock status

Note: When FWKUP = 0, if the PLL or oscillator is enabled and unintentionally lost in stop mode, the PLL wakes up in self-clocked mode or reference clock mode depending on the clock that was lost. In external clock mode, the FWKUP bit has no effect on the wakeup sequence.


Clock Source. Determines whether the PLL output clock or the PLL reference clock is to drive the system clock. This bit is ignored when the PLL is disabled, in which case the PLL reference clock will drive the system clock. Having this separate bit allows the PLL to first be enabled, and then the system clock can be switched to the PLL output clock only after the PLL has locked. When disabling the PLL, the clock can be switched before disabling the PLL so that a smooth transfer is ensured.

0) PLLreference clock (input clock) drives the system clock.

1) PLL output clock drives the system clock (provided the PLL is enabled).

Determines the operating mode of the PLL. This bit should only be changed after reset with the PLL disabled.

0) PLL operates in 1:1 mode

1) PLL operates in normal mode

Enables and disables the PLL. If the PLL is enabled out of reset the chip will not leave the reset state until the PLL is locked and the system clock will be driven by the PLL output clock. Use the CLKSRC control bit to switch the system clock between the PLL output clock and PLL bypass clock once the PLL is enabled.

0) PLL is disabled

1) PLL is enabled

7.7.1.2

Synthesizer Status Register (SYNSR)

The SYNSR is a read-only register that can be read at any time. Writing to the SYNSR has no effect and terminates the cycle normally.

IPSBAR

Offset:

0x0012_0002 (SYNSR) Access: Supervisor read/write

W

Reset:

7

R EXTOSC

1

6

—

5

—

4

LOCKS

3

LOCK

2

LOCS

0 0 See note 1 See note 1 0

Note: 1. See the LOCKS and LOCK bit descriptions.

Figure 7-4. Synthesizer Status Register (SYNSR)

1

—

0

0

—

0

Field

7

EXTOSC

6–5

Table 7-5. SYNSR Field Descriptions

Description

Indicates if an external oscillator is providing the reference clock source

0) Reference clock is not external oscillator

1 Reference clock is external oscillator


7-8



Preliminary

Field

4

LOCKS

3

LOCK

2

LOCS

1–0

Clock Module

Table 7-5. SYNSR Field Descriptions (continued)

Description

Sticky indication of PLL lock status.

0 PLL loss of lock since last system reset or MFD change or currently not locked due to exit from STOP with FWKUP set

1 No unintentional PLL loss of lock since last system reset or MFD change

The lock detect function sets the LOCKS bit when the PLL achieves lock after:

• A system reset

• A write to SYNCR that changes the MFD[2:0] bits

When the PLL loses lock, LOCKS is cleared. When the PLL relocks, LOCKS remains cleared until one of the two listed events occurs.

In stop mode, if the PLL is intentionally disabled, then the LOCKS bit reflects the value prior to entering stop mode. However, if FWKUP is set, then LOCKS is cleared until the PLL regains lock. Once lock is regained, the LOCKS bit reflects the value prior to entering stop mode. Furthermore, reading the LOCKS bit at the same time that the PLL loses lock does not return the current loss of lock condition.

In external clock mode, LOCKS remains cleared after reset. In normal PLL mode and 1:1 PLL mode,

LOCKS is set after reset.

Set when the PLL is locked. PLL lock occurs when the synthesized frequency is within approximately 0.75% of the programmed frequency. The PLL loses lock when a frequency deviation of greater than approximately

1.5% occurs. Reading the LOCK flag at the same time that the PLL loses lock or acquires lock does not return the current condition of the PLL. The power-on reset circuit uses the LOCK bit as a condition for releasing reset.

If operating in external clock mode, LOCK remains cleared after reset.

0 PLL not locked

1 PLL locked

Sticky indication of whether a loss-of-clock condition has occurred at any time since exiting reset in normal

PLL and 1:1 PLL modes.

• LOCS = 0 when the system clocks are operating normally.

• LOCS = 1 when system clocks have failed due to a reference failure or PLL failure.

After entering stop mode with FWKUP set and the PLL and oscillator intentionally disabled

(STPMD[1:0] = 11), the PLL exits stop mode in the SCM while the oscillator starts up. During this time,

LOCS is temporarily set regardless of LOCEN. It is cleared once the oscillator comes up and the PLL is attempting to lock.

If a read of the LOCS flag and a loss-of-clock condition occur simultaneously, the flag does not reflect the current loss-of-clock condition.

A loss-of-clock condition can be detected only if LOCEN = 1 or the oscillator has not yet returned from exit from stop mode with FWKUP = 1.

0 Loss-of-clock not detected since exiting reset

1 Loss-of-clock detected since exiting reset or oscillator not yet recovered from exit from stop mode with

FWKUP = 1

Note: The LOCS flag is always 0 in external clock mode.


7.7.1.3

Low Power Divider Register (LPDR)

The low power divider is a 4-bit field that divides down the system clock (regardless if the reference clock or PLL clock is driving the system clock) by a factor of 2 n

(where n is a number from 0 to 15 represented by the 4 bit field). The clock change takes effect with the next rising edge of the system clock.



Preliminary

7-9

Clock Module

IPSBAR

Offset:

0x0012_0007 (LPDR)

7

— R

W

Reset: 0

6

—

5

—

4

—

3

LPD3

0 0 0 0

Figure 7-5. Low Power Divider Register

2


LPD2

0

1

LPD1

0

0

LPD0

0

7.7.1.4

Clock Control High Register (CCHR)

The Pre-Divider Factor divides down the PLL input clock by 1 (PFD[2:0] = 000) to 8 (PFD[2:0] =111).

This allows an external oscillator or crystal of more than 10 MHz to be used with the PLL. The division factor should be set to generate an input clock for the PLL above 1 MHz and below 10 MHz. When

PFD[2:0] are changed or the PLL is disabled in stop mode, the PLL loses lock. In 1:1 PLL mode, PFD[2:0] are ignored, and the pre-division factor is one.

IPSBAR

Offset:

0x0012_0008 (PFD)

7

— R

W

Reset: 0

6

—

0

5

—

4

—

3

—

0 0 0

Figure 7-6. Clock Control High Register

2

PFD2

0


1

PFD1

0

0

PFD0

0

7.7.1.5

Real Time Clock Divide Register (RTCDR)

The Real Time Clock Divide Factor is a 32 bit read/write register that divides down the oscillator clock to a 1 Hz clock for the Real Time Clock module. If this register is programmed with zero then the clock to the Real Time Clock module is disabled, otherwise the oscillator clock is divided by one more than the value written to the register field (between 2 and 4,294,967,296).

7-10



Preliminary

Clock Module

IPSBAR

Offset:

0x0011_000C (RTCDF)

31 30

R

W

Reset 0 0

23 22

R

W

Reset 0

15

0

14

R

W

Reset 0

7

0

6

R

W

Reset 0 0

29

0

13

0

21

0

5

28

RTCDF (31:24)

27

0

20

RTCDF (23:16)

0

19

0

12

RTCDF 15:8)

0

11

0

4

RTCDF (7:0)

0

3

0 0 0

Figure 7-7. Real Time Clock Divide Register

26

0

18

0

2

0

0

10


25

0

9

0

17

0

1

0

24

0

8

0

16

0

0

0

7.8


This section provides a functional description of the clock module.

7.8.1

Clock Operation During Reset

The PLL is always disabled as the part emerges from Reset, with a default configuration of external crystal mode (although this mode also supports an external clock source). Once out of reset, it is not possible to change the input clock source, although it is possible to enable the PLL and switch between the PLL clock and the oscillator clock as the source of the system clock.

7.8.2

System Clock Generation

In normal PLL clock mode, the default system frequency is two times the reference frequency after reset.

The RFD[2:0] and MFD[2:0] bits in the SYNCR select the frequency multiplier. The LPD[3:0] field in the

LPCR register provides additional settings for dividing down the system clock (including when the PLL is disabled) for low power operation.



Preliminary

7-11

Clock Module

When programming the PLL, do not exceed the maximum system clock frequency listed in the electrical specifications. Use this procedure to accommodate the frequency overshoot that occurs when the MFD bits are changed:

1. Determine the appropriate value for the MFD and RFD fields in the SYNCR. The amount of jitter in the system clocks can be minimized by selecting the maximum MFD factor that can be paired with an RFD factor to provide the required frequency.

2. Write a value of 1 + RFD (from step 1) to the RFD field of the SYNCR.

3. Write the MFD value from step 1 to the SYNCR.

4. Monitor the LOCK flag in SYNSR. When the PLL achieves lock, write the RFD value from step

1 to the RFD field of the SYNCR. This changes the system clocks frequency to the required frequency.

NOTE

Keep the maximum system clock frequency below the limit given in the electrical characteristics.

7.8.3

PLL Operation

In PLL mode, the PLL synthesizes the system clocks. The PLL can multiply the reference clock frequency by 4x to 18x, provided that the system clock frequency remains within the range listed in electrical specifications. For example, if the reference frequency is 2 MHz, the PLL can synthesize frequencies of

8 MHz to 36 MHz. In addition, the RFD can reduce the system frequency by dividing the output of the

PLL. The RFD is not in the feedback loop of the PLL, so changing the RFD divisor does not affect PLL operation.

Figure 7-8

shows the external support circuitry for the crystal oscillator with example component values.

Actual component values depend on crystal specifications.

The following subsections describe each major block of the PLL. Refer to Figure 7-8 to see how these

functional sub-blocks interact.

C1

C2

25-MHz CRYSTAL CONFIGURATION

C1 = 15 pF, C2 = 39pF

RF = 1 M

Ω

RS = 470

Ω

R1 = 10 M

Ω

R1

V

SSPLL

EXTAL XTAL V

SSPLL

ON-CHIP

RF

RS

7-12

Figure 7-8. Crystal Oscillator Example



Preliminary

Clock Module

7.8.3.1

Phase and Frequency Detector (PFD)

The PFD is a dual-latch phase-frequency detector. It compares both the phase and frequency of the reference and feedback clocks. The reference clock comes from either the crystal oscillator or an external clock source.

The feedback clock comes from one of the following:

• CLKOUT in 1:1 PLL mode

• VCO output divided by two if CLKOUT is disabled in 1:1 PLL mode

• VCO output divided by the MFD in normal PLL mode

When the frequency of the feedback clock equals the frequency of the reference clock, the PLL is frequency-locked. If the falling edge of the feedback clock lags the falling edge of the reference clock, the

PFD pulses the UP signal. If the falling edge of the feedback clock leads the falling edge of the reference clock, the PFD pulses the DOWN signal. The width of these pulses relative to the reference clock depends on how much the two clocks lead or lag each other. Once phase lock is achieved, the PFD continues to pulse the UP and DOWN signals for very short durations during each reference clock cycle. These short pulses continually update the PLL and prevent the frequency drift phenomenon known as dead-banding.

7.8.3.2

Charge Pump/Loop Filter

In 1:1 PLL mode, the charge pump uses a fixed current. In normal mode the current magnitude of the charge pump varies with the MFD as shown in

Table 7-6

.

Table 7-6. Charge Pump Current and MFD in Normal Mode Operation

Charge Pump Current

1x

2x

4x

MFD

0

≤

MFD < 2

2

≤

MFD < 6

6

≤

MFD

The UP and DOWN signals from the PFD control whether the charge pump applies or removes charge, respectively, from the loop filter. The filter is integrated on the chip.

7.8.3.3

Voltage Control Output (VCO)

The voltage across the loop filter controls the frequency of the VCO output. The frequency-to-voltage relationship (VCO gain) is positive, and the output frequency is four times the target system frequency.

7.8.3.4

Multiplication Factor Divider (MFD)

When the PLL is not in 1:1 PLL mode, the MFD divides the output of the VCO and feeds it back to the

PFD. The PFD controls the VCO frequency via the charge pump and loop filter such that the reference and feedback clocks have the same frequency and phase. Thus, the frequency of the input to the MFD, which is also the output of the VCO, is the reference frequency multiplied by the same amount that the MFD divides by. For example, if the MFD divides the VCO frequency by six, the PLL is frequency locked when the VCO frequency is six times the reference frequency. The presence of the MFD in the loop allows the

PLL to perform frequency multiplication, or synthesis.



Preliminary

7-13

Clock Module

In 1:1 PLL mode, the MFD is bypassed, and the effective multiplication factor is one.

7.8.3.5

PLL Lock Detection

The lock detect logic monitors the reference frequency and the PLL feedback frequency to determine when frequency lock is achieved. Phase lock is inferred by the frequency relationship, but is not guaranteed. The

LOCK flag in the SYNSR reflects the PLL lock status. A sticky lock flag, LOCKS, is also provided.

The lock detect function uses two counters: one is clocked by the reference, and the other is clocked by the PLL feedback. When the reference counter has counted N cycles, its count is compared to that of the feedback counter. If the feedback counter has also counted N cycles, the process is repeated for N + K counts. Then, if the two counters still match, the lock criteria is relaxed by 1/2 and the system is notified that the PLL has achieved frequency lock.

After lock is detected, the lock circuit continues to monitor the reference and feedback frequencies using the alternate count and compare process. If the counters do not match at any comparison time, then the

LOCK flag is cleared to indicate that the PLL has lost lock. At this point, the lock criteria is tightened and the lock detect process is repeated.

The alternate count sequences prevent false lock detects due to frequency aliasing while the PLL tries to lock. Alternating between tight and relaxed lock criteria prevents the lock detect function from randomly toggling between locked and non-locked status due to phase sensitivities.

Figure 7-9 shows the sequence

for detecting locked and non-locked conditions.

In external clock mode, the PLL is disabled and cannot lock.

Start with Tight Lock

Criteria

Reference Count

≠ Feedback Count

Loss of Lock Detected

Set Tight Lock Criteria and Notify System of Loss of Lock Condition

Reference Count

≠ Feedback Count

Count N

Reference Cycles and Compare

Number of Feedback

Cycles Elapsed

Reference Count =

Feedback Count = N

In Same Count/Compare Sequence

Count N + K

Reference Cycles and Compare Number of Feedback Cycles

Elapsed

Lock Detected.

Set Relaxed Lock

Condition and Notify

System of Lock

Condition

Figure 7-9. Lock Detect Sequence

Reference Count = Feedback Count = N + K

In Same Count/Compare Sequence

7-14



Preliminary

Clock Module

7.8.3.6

PLL Loss of Lock Conditions

Once the PLL acquires lock after reset, the LOCK and LOCKS flags are set. If the MFD is changed, or if an unexpected loss of lock condition occurs, the LOCK and LOCKS flags are negated.

While the PLL is in the non-locked condition, the system clocks continue to be sourced from the PLL as the PLL attempts to relock.

Consequently, during the relocking process, the system clocks frequency is not well defined and may exceed the maximum system frequency, violating the system clock timing specifications.

However, once the PLL has relocked, the LOCK flag is set. The LOCKS flag remains cleared if the loss of lock was unexpected. The LOCKS flag is set when the loss of lock is caused by changing MFD. If the

PLL is intentionally disabled during stop mode, then after exit from stop mode, the LOCKS flag reflects the value prior to entering stop mode once lock is regained.

7.8.3.7

PLL Loss of Lock Reset

If the LOLRE bit in the SYNCR is set, a loss of lock condition asserts reset. Reset reinitializes the LOCK and LOCKS flags. Therefore, software must read the LOL bit in the reset status register (RSR) to determine if a loss of lock caused the reset. See Section 9.5.2, “Reset Status Register (RSR).”

To exit reset in PLL mode, the reference must be present, and the PLL must achieve lock.

In external clock mode, the PLL cannot lock. Therefore, a loss of lock condition cannot occur, and the

LOLRE bit has no effect.

7.8.3.8

Loss of Clock Detection

The LOCEN bit in the SYNCR enables the loss of clock detection circuit to monitor the input clocks to the phase and frequency detector (PFD). When either the reference or feedback clock frequency falls below the minimum frequency, the loss of clock circuit sets the sticky LOCS flag in the SYNSR.

NOTE

In external clock mode, the loss of clock circuit is disabled.

7.8.3.9

Loss of Clock Reset

The clock module can assert a reset when a loss of clock or loss of lock occurs. When a loss-of-clock condition is recognized, reset is asserted if the LOCRE bit in SYNCR is set. The LOCS bit in SYNSR is cleared after reset. Therefore, the LOC bit must be read in RSR to determine that a loss of clock condition occurred. LOCRE has no effect in external clock mode.

To exit reset in PLL mode, the reference must be present, and the PLL must acquire lock.

Reset initializes the clock module registers to a known startup state as described in

Section 7.7, “Memory

Map and Registers .”

7.8.3.10

Alternate Clock Selection

Depending on which clock source fails, the loss-of-clock circuit switches the system clocks source to the remaining operational clock. The alternate clock source generates the system clocks until reset is asserted.



Preliminary

7-15

Clock Module

As Table 7-7 shows, if the reference fails, the PLL goes out of lock and into self-clocked mode (SCM).

The PLL remains in SCM until the next reset. When the PLL is operating in SCM, the system frequency depends on the value in the RFD field. The SCM system frequency stated in electrical specifications assumes that the RFD has been programmed to binary 000.

If the loss-of-clock condition is due to PLL failure, the PLL reference becomes the system clocks source until the next reset, even if the PLL regains and relocks.

Table 7-7. Loss of Clock Summary

Clock

Mode

PLL

System Clock Source

Before Failure

Reference Failure Alternate Clock

Selected by LOC Circuit

1

Until Reset

PLL Failure Alternate Clock

Selected by LOC Circuit Until Reset

PLL PLL self-clocked mode

None

1

The LOC circuit monitors the reference and feedback inputs to the PFD. See

Figure 7-8

.

PLL reference

NA

A special loss-of-clock condition occurs when both the reference and the PLL fail. The failures may be simultaneous, or the PLL may fail first. In either case, the reference clock failure takes priority and the

PLL attempts to operate in SCM. If successful, the PLL remains in SCM until the next reset. If the PLL cannot operate in SCM, the system remains static until the next reset. Both the reference and the PLL must be functioning properly to exit reset.

7.8.3.11

Loss of Clock in Stop Mode

Table 7-8

shows the resulting actions for a loss of clock in stop mode when the device is being clocked by the various clocking methods.

Table 7-8. Stop Mode Operation

MODE

In

Expected

PLL

Action at

Stop

PLL Action

During Stop

EXT X X X X X X —

NRM 0 0 0 Off Off 0 Lose lock, f.b. clock, reference clock

—

Lose reference clock

Regain

No regain

MODE

Out

EXT

Stuck

NRM

Stuck

0

—

‘LK

—

0

—

0

—

1

—

‘LC

—

Comments

7-16



Preliminary

Clock Module

Table 7-8. Stop Mode Operation (continued)

MODE

In

Expected

PLL

Action at

Stop

PLL Action

During Stop

MODE

Out

NRM X 0 0 Off Off 1 Lose lock, f.b. clock, reference clock

Regain clocks, but don’t regain lock

SCM–> unstable

NRM

No reference clock regain

SCM–>

Stuck

Comments

0–>‘LK 0–>1 1–>‘LC Block LOCS and

LOCKS until clock and lock respectively regain; enter

SCM regardless of LOCEN bit until reference regained

0–> 0–> 1–> Block LOCS and

LOCKS until clock and lock respectively regain; enter

SCM regardless of LOCEN bit

— — — No f.b. clock regain

NRM 0 0 0 Off On 0 Lose lock Regain NRM ‘LK 1 ‘LC Block LOCKS from being cleared

Lose reference clock or no lock regain

Lose reference clock, regain

NRM 0 0 0 Off On 1 Lose lock No lock regain

Stuck

NRM

Unstable

NRM

‘LK

—

1

—

‘LC

0–>‘LK 0–>1 ‘LC

—

Block LOCKS from being cleared

Block LOCKS until lock regained

Lose reference clock or no f.b. clock regain

Lose reference clock, regain

Stuck

Unstable

NRM

— —

0–>‘LK 0–>1 ‘LC

—

LOCS not set because

LOCEN = 0

NRM 0 0 0 On On 0 — — NRM

Lose lock or clock Stuck

Lose lock, regain NRM

Lose clock and lock, regain

NRM

0

0

‘LK

—

1

1

1

—

‘LC

—

‘LC

‘LC LOCS not set because

LOCEN = 0



Preliminary

7-17

Clock Module


MODE

In

Expected

PLL

Action at

Stop

PLL Action

During Stop

MODE

Out

NRM 0 0 0 On On 1 — —

Lose lock

NRM

Unstable

NRM


Lose clock Stuck

Lose clock, regain without lock

Unstable

NRM

Lose clock, regain with lock

NRM

RESET RESET NRM X X 1 Off X X Lose lock, f.b. clock, reference clock

NRM 0 0 1 On On X — — NRM

Lose lock or clock RESET

‘LK

0

0

0

0

—

—

‘LK

—

1 ‘LC

0–>1 ‘LC

1

—

‘LC

—

0–>1 ‘LC

1

—

‘LC

—

1

—

‘LC

—

NRM 1 0 0 Off Off 0 Lose lock, f.b. clock, reference clock

Regain

No regain

NRM 1 0 0 Off On 0 Lose lock, f.b. clock

Regain

NRM

Stuck

NRM

‘LK

‘LK

—

—

Comments

Reset immediately

1 ‘LC

1

—

‘LC

—

REF mode not entered during stop

— —

Reset immediately

REF not entered during stop;

SCM entered during stop only during oscillator startup

NRM 1 0 0 Off On 1 Lose lock, f.b. clock

No f.b. clock or lock regain


Stuck

SCM

Regain f.b. clock Unstable

NRM

0 0 1

0–>‘LK 0–>1 ‘LC

Wakeup without lock

REF mode not entered during stop

No f.b. clock regain


Stuck

SCM 0

—

0

—

1

—

Wakeup without lock

7-18



Preliminary

Clock Module

MODE

In

NRM 1 0 0 On On 0

NRM 1 0 0 On On 1


Expected

PLL

Action at

Stop

—

PLL Action

During Stop

—


Lose f.b. clock

MODE

Out

NRM

SCM

REF

‘LK

0

0

—

Lose lock Stuck

Lose lock, regain NRM clock

—

Lose reference

Lose f.b. clock

NRM

SCM

REF

1

0

X

‘LC

1

1

Comments

0

‘LK

0

—

0

1

1

0

— —

‘LC

‘LC

1

X 1

Wakeup without lock

Wakeup without lock

0 0–>1 ‘LC

Wakeup without lock

Wakeup without lock

NRM 1 0 1 On On X —

Lose lock Unstable

NRM

— NRM

Lose lock or clock RESET

RESET

‘LK

—

—

1

—

—

‘LC

—

—

Reset immediately

Reset immediately

NRM 1 1 X Off X X Lose lock, f.b. clock, reference clock

RESET

NRM 1 1 0 On On 0 — —

Lose clock

NRM

RESET

NRM 1 1 0 On On 1 —

Lose lock Stuck


—

Lose clock

NRM

RESET

‘LK

—

0

‘LK

—

—

0

1

—

‘LC

— Reset immediately

1

1

— —

‘LC

—

‘LC

0–>1 ‘LC


NRM 1 1 1 On On X —

Lose lock Unstable

NRM


— NRM

Lose clock or lock RESET

0

‘LK

—

1

1

—

‘LC

‘LC




Preliminary

7-19

Clock Module


MODE

In

Expected

PLL

Action at

Stop

PLL Action

During Stop

MODE

Out

Comments

REF 1 0 0 X X X — —


Regain SCM

REF

Stuck

0

—

X

—

1

—

SCM 1 0 0 Off X 0 PLL disabled

SCM 1 0 0 Off X 1 PLL disabled

SCM 1 0 0 On On 0 —

Regain SCM

SCM

SCM

0

0

0

0

1

1

Wakeup without lock

—


—

SCM

SCM

0 0 1 Wakeup without lock

SCM 1 0 0 On On 1 —


SCM

SCM

0 0 1

Note:

PLL = PLL enabled during STOP mode. PLL = On when STPMD[1:0] = 00 or 01

OSC = oscillator enabled during STOP mode. Oscillator is on when STPMD[1:0] = 00, 01, or 10

MODES

NRM = normal PLL crystal clock reference or normal PLL external reference or PLL 1:1 mode. During PLL 1:1 or normal external reference mode, the oscillator is never enabled. Therefore, during these modes, refer to the OSC = On case regardless of STPMD values.

EXT = external clock mode

REF = PLL reference mode due to losing PLL clock or lock from NRM mode

SCM = PLL self-clocked mode due to losing reference clock from NRM mode

RESET = immediate reset

LOCKS

‘LK -= expecting previous value of LOCKS before entering stop

0–>‘LK = current value is 0 until lock is regained which then will be the previous value before entering stop

0–> = current value is 0 until lock is regained but lock is never expected to regain

LOCS

‘LC = expecting previous value of LOCS before entering stop

1–>‘LC = current value is 1 until clock is regained which then will be the previous value before entering stop

1–> = current value is 1 until clock is regained but CLK is never expected to regain

7-20



Preliminary

Chapter 8

Real Time Clock

8.1

Introduction

This section discusses how to operate and program the real-time clock (RTC) module that maintains the system clock, provides stopwatch, alarm, and interrupt functions, and supports the following features.

8.1.1

Overview

Figure 8-1

is a block diagram of the functional organization of the Real Time Clock (RTC) block, it consists of the following blocks:

• Time-of-day (TOD) clock counter

• Alarm

• Minute stopwatch

• Associated control and bus interface hardware

I Hz Input CLock

RTC_INT

INTERRUPT

CONTROL

CLOCK

CONTROL

INTERRUPT

ENABLE

INTERRUPT

STATUS

ADDRESS

DATA

BUS CONTROL

IPBUS

DECODE

TOD CLOCK

SECOND

1 PPM

MINUTE

1 PPH

HOUR

1 PPD

DAY

ALARM COMPARATOR

SECOND

LATCH

MINUTE

LATCH

MINUTE STOPWATCH

HOUR

LATCH

Figure 8-1. Real Time Clock Block Diagram



Real Time Clock

8.1.2

Features

The RTC module includes the following features:

• Full clock—days, hours, minutes, seconds

• Minute countdown timer with interrupt

• Programmable daily alarm with interrupt

• Once-per-day, once-per-hour, once-per-minute, and once-per-second interrupts

8.1.3


The incoming 1 Hz signal is used to increment the seconds, minutes, hours, and days TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values.

The sampling timer generates fixed-frequency interrupts, and the minute stopwatch allows for efficient interrupts on minute boundaries.

• Counter

The counter portion of the RTC module consists of four groups of counters that are physically located in three registers:

– The 6-bit seconds counter is located in the SECONDS register

– The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register

– The 16-bit day counter is located in the DAYR register

• Alarm

There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the real-time clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time that the alarm should generate an interrupt. When the TOD clock value and the alarm value coincide, an interrupt occurs.

• Minute Stopwatch

The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt on a minute boundary.

8.2


The RTC module includes ten 32-bit registers.

Table 8-1

summarizes these registers and their addresses

Address

$BASE+0x00

$BASE+0x04

$BASE+0x08

$BASE+0x0C

Table 8-1. RTC Module Register Memory Map

Use

RTC Hours and Minutes Counter Register(HOURMIN)

RTC Seconds Counter Register(SECONDS)

RTC Hours and Minutes Alarm Register(ALRM_HM)

RTC Seconds Alarm Register(ALRM_SEC)

Access read/write read/write read/write read/write

8-2




$BASE+0x10

$BASE+0x14

$BASE+0x18

$BASE+0x1C

$BASE+0x20

$BASE+0x24

Table 8-1. RTC Module Register Memory Map (continued)

RTC Control Register(RCCTL)

RTC Interrupt Status Register(RTCISR)

RTC Interrupt Enable Register(RTCIENR)

Stopwatch Minutes Register(STPWCH)

RTC Days Counter Register(DAYS)

RTC Seconds Counter Register(ALARM_DAY) read/write read/write read/write read/write read/write read/write

8.2.1


This section consists of register descriptions in address order. Each description includes a standard register diagram with an associated figure number. Details of register bit and field function follow the register diagrams, in bit order.

8.2.1.1

RTC Hours and Minutes Counter Register(HOURMIN)

The real-time clock hours and minutes counter register (HOURMIN) is used to program the hours and minutes for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset.

$BASE_ADDRESS+0x0

31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

23

0

0x0000

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

0

14

0

0

13

0

0

12

?

11 10

HOURS

?

?

9

?

8

?

7

0

0

6

0

0

5

?

4

?

3 2

MINUTES

?

?

1

?


Figure 8-2. RTC Hours and Minutes Counter Register

HOURS — Hour setting which indicates the current hour, can be set to any value between 0 and 23.

Table 8-2. Meanings of HOURS (HOURMIN Register)

Values

00000

00001

......

10111

Meanings current hour is 0 current hour is 1

......

current hour is 23

0

?



Real Time Clock

MINUTES — Minutes setting which indicates the current minutes, can be set to any value between 0 and

59.

Table 8-3. Meanings of MINUTES(HOURMIN Register)

Values

000000

000001

......

111011

Meanings current minute is 0 current minute is 1

......

current minute is 59

8.2.1.2

RTC Seconds Counter Register(SECONDS)

The real-time clock seconds register (SECONDS) is used to program the seconds for the TOD clock. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset.


31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

0

14

0

0

13

0

0

12

0

0

11

0

0

10

0

0

9

0

0

8

0

0

7

0

0

6

0

0

5

?

4

?

3 2

SECONDS

?

?

1

?

0

?


Figure 8-3. RTC Seconds Counter Register

SECONDS—Seconds setting which indicates the current seconds, can be set to any value between 0 and

59.

Table 8-4. Meanings of SECONDS(SECONDS Register)

Values

000000

000001

......

111011

Meanings current second is 0 current second is 1

......

current second is 59

8.2.1.3

RTC Hours and Minutes Alarm Register(ALRM_HM)

The real-time clock hours and minutes alarm (ALRM_HM) register is used to configure the hours and minutes setting for the alarm. The alarm settings can be read or written at any time.

8-4





31

0

30

0

29

0 R

W

RESET:

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12 11 10

HOURS

9 8

0x0000

7

0

6

0

5 4 3 2

MINUTES


Figure 8-4. RTC Hours and Minutes Alarm Register

HOURS — Hour setting of the alarm hours, can be set to any value between 0 and 23.

Table 8-5. Meanings of HOURS(ALRM_HM Register)

Values

00000

00001

......

10111

Meanings current hour is 0 current hour is 1

......

current hour is 23

MINUTES — Minutes setting of the alarm minutes, can be set to any value between 0 and 59.

Table 8-6. Meanings of MINUTES(ALRM_HM Register)

Values

000000

000001

......

111011

Meanings current minute is 0 current minute is 1

......

current minute is 59

1 0

8.2.1.4

RTC Seconds Alarm Register(ALRM_SEC)

The real-time clock seconds alarm (ALRM_SEC) register is used to configure the seconds setting for the alarm. The alarm settings can be read or written at any time.



Real Time Clock

$BASE_ADDRESS+0x0C

31

0

30

0

29

0 R

W

RESET:

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

0x0000

7

0

6

0

5 4 3 2

SECONDS


Figure 8-5. RTC Seconds Alarm Register

SECONDS—Seconds setting of the alarm seconds, can be set to any value between 0 and 59.

Table 8-7. Meanings of SECONDS(ALRM_SEC Register)

Values

000000

000001

......

111011

Meanings current second is 0 current second is 1

......

current second is 59

1 0

8.2.1.5

RTC Control Register(RTCCTL)

The real-time clock control (RTCCTL) register is used to enable the real-time clock module and specify the reference frequency information for the prescaler.


31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

EN

0x0080

6

0


Figure 8-6. RTC Control Register

5

0

4

0

3

0

2

0

1

0

0

SWR

8-6




EN — Enables/Disables the real-time clock. The software reset bit (SWR) has no effect on this bit.

Bit description

1 = Enable the real-time clock

0 = Disable the real-time clock

XTL — Crystal Selection, selects the proper input crystal frequency. It is important to set these bits correctly or the real-time clock will be inaccurate.

Table 8-8. Meanings of XTL(RTCCTL Register)

Values

00

01

10

11

Meanings input crystal frequency is 32.768KHz

input crystal frequency is 32KHz input crystal frequency is 38.4KHz

input crystal frequency is 32.768KHz

SWR — Software reset, Resets the module to its default state. However, a software reset will have no effect on the RTC enable (EN) bit.

Bit description

1 = Reset the module to its default state.

0 = No effect.

8.2.1.6

RTC Interrupt Status Register(RTCISR)

The real-time clock interrupt status register (RTCISR) indicates the status of the various real-time clock interrupts. When an event of the types included in this register occurs, then the bit will be set in this register regardless of its corresponding interrupt enable bit.These bits are cleared by writing a value of 1, which also clears the interrupt. Interrupts may occur while the system clock is idle or in sleep mode.


31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

0x0000

7

0

6

0

5 4 3 2 1 0

HR 1HZ DAY ALM MIN SW


Figure 8-7. RTC Interrupt Status Register

HR — Hour Flag, indicates that the hour counter has incremented. If enabled, this bit is set on every increment of the hour counter in the time-of-day clock.



Real Time Clock

Bit description

1 = A 1-hour interrupt has occurred.

0 = No 1-hour interrupt occurred.

1HZ — 1 Hz Flag, indicates that the second counter has incremented. If enabled, this bit is set on every increment of the second counter of the time-of-day clock.

Bit description

1 = A 1 Hz interrupt has occurred.

0 = No 1 Hz interrupt occurred.

DAY — Day Flag, indicates that the day counter has incremented. If enabled, this bit is set on every increment of the day counter of the time-of-day clock.

Bit description

1 = A 24-hour rollover interrupt has occurred.

0 = No 24-hour rollover interrupt occurred.

ALM — Alarm Flag—Indicates that the real-time clock matches the value in the alarm registers. Note that the alarm will reoccur every 65536 days. For a single alarm, clear the interrupt enable for this bit in the interrupt service routine.

Bit description

1 = An alarm interrupt has occurred.

0 = No alarm interrupt occurred.

MIN — Minute Flag, indicates that the minute counter has incremented. If enabled, this bit is set on every increment of the minute counter in the time-of-day clock.

Bit description

1 = A 1-minute interrupt has occurred.

0 = No 1-minute interrupt occurred.

SW — Stopwatch Flag, indicates that the stopwatch countdown timed out.

Bit description

1 = The stopwatch timed out.

0 = The stopwatch did not time out.

8.2.1.7

RTC Interrupt Enable Register(RTCIENR)

The real-time clock interrupt enable register (RTCIENR) is used to enable/disable the various real-time clock interrupts. Masking an interrupt bit has no effect on its corresponding status bit.

8-8





31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

0x0000

7

0

6

0

5 4 3 2 1 0

HR 1HZ DAY ALM MIN SW


Figure 8-8. RTC Interrupt Enable Register

HR — Hour Interrupt Enable, Enables/Disables an interrupt whenever the hour counter of the real-time clock increments.

Bit description

1 = The 1-hour interrupt is enabled.

0 = The 1-hour interrupt id disabled.

1HZ — 1 Hz Interrupt Enable, Enables/Disables an interrupt whenever the second counter of the real-time clock increments.

Bit description

1 = The 1 Hz interrupt is enabled.

0 = The 1 Hz interrupt is disabled.

DAY — Day Interrupt Enable, Enables/Disables an interrupt whenever the hours counter rolls over from

23 to 0. (midnight rollover)

Bit description

1 = The 24-hour interrupt is enabled.

0 = The 24-hour interrupt is disabled.

ALM — Alarm Interrupt Enable, Enables/Disables the alarm interrupt.

Bit description

1 = The alarm interrupt is enabled.

0 = The alarm interrupt is disabled.

MIN — Minute Interrupt Enable, Enables/Disables an interrupt whenever the minute counter of the real-time clock increments.

Bit description

1 = The 1-minute interrupt is enabled.

0 = The 1-minute interrupt is disabled.



Real Time Clock

SW — Stopwatch Interrupt Enable, Enables/Disables the stopwatch interrupt. Please note that the stopwatch counts down and remains at decimal -1 until it is reprogrammed. If this bit is enabled with -1

(decimal) in the STPWCH register, an interrupt will be posted on the next minute tick.

Bit description

1 = Stopwatch interrupt is enabled.

0 = Stopwatch interrupt is disabled.

8.2.1.8

RTC Stopwatch Minutes Register(STPWCH)

The stopwatch minutes (STPWCH) register contains the current stopwatch countdown value. When the minute counter of the TOD clock increments, the value in this register decrements.

$BASE_ADDRESS+0x1C

31

0

30

0

29

0 R

W

RESET:

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15

0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

0x003F

7

0

6

0

5 4 3

CNT

2 1 0


Figure 8-9. RTC Stopwatch Minutes Register

CNT — Stopwatch Count, Contains the stopwatch countdown value. Please note that the stopwatch counter is decremented by the minute (MIN) tick output from the real-time clock, so the average tolerance of the count is 0.5 minutes. For better accuracy, enable the stopwatch by polling the MIN bit of the

RTCISR register or by polling the minute interrupt service routine.

Table 8-9. Meanings of CNT(STPWCH Register)

Values

000000

000001

......

111111

Meanings stopwatch countdown value is 0 stopwatch countdown value is 1

......

stopwatch countdown value is 63

8.2.1.9

RTC Days Counter Register(DAYR)

The real-time clock days counter register (DAYR) is used to program the day for the TOD clock. When the HOUR field of the HOURMIN register rolls over from 23 to 00, the day counter increments. It can be read or written at any time. After a write, the time changes to the new value. This register cannot be reset since the real-time clock is always enabled at reset. Only 16-bit accesses to this register are allowed.

8-10





31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15 14 13 12 11 10 9 8

DAYS

7

0x????

6 5 4 3 2 1


Figure 8-10. RTC Days Counter Register

DAYS — Day Setting, indicates the current day count, can be set to any values between 0 and 65535.

Table 8-10. Meanings of DAYS(DAYR Register)

Values

0x0000

0x0001

......

0xFFFF

Meanings current day count is 0 current day count is 1

......

current day count is 65535

0

8.2.1.10

RTC Day Alarm Register(DAYALARM)

The real-time clock day alarm (DAYALARM) register is used to configure the day for the alarm. The alarm settings can be read or written at any time.


31

0

30

0 R

W

RESET:

29

0

28

0

27

0

26

0

25

0

24

0

0x0000

23

0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

R

W

RESET:

15 14 13 12 11 10 9 8 7

DAYSAL

0x0000

6 5 4 3 2 1 0


Figure 8-11. RTC Day Alarm Register

DAYSAL — Day Setting of the Alarm, indicates the current day setting of the alarm. It can be set to any value between 0 and 65535.



Real Time Clock

Table 8-11. Meanings of DAYSAL(DAYALARM Register)

Values

0x0000

0x0001

......

0xFFFF

Meanings current day setting of alarm is 0 current day setting of alarm is 1

......

current day setting of alarm is 65535

8.3


A 1 Hz signal is supplied to the RTC, which used it to increment the seconds, minutes, hours, and days

TOD counters. The alarm functions, when enabled, generate RTC interrupts when the TOD settings reach programmed values. The minute stopwatch allows for efficient interrupts on minute boundaries.

8.3.1

Prescaler and Counter

A 1 Hz clock is supplied to the RTC. This 1 Hz clock drives the RTC’s counters. The counter portion of the RTC module consists of four groups of counters that are physically located in three registers:

• The 6-bit seconds counter is located in the SECONDS register

• The 6-bit minutes counter and the 5-bit hours counter are located in the HOURMIN register

• The 16-bit day counter is located in the DAYR register

These counters cover a 24-hour clock over 65536 days. All three registers can be read or written at any time.

Interrupts signal when each of the four counters increments, and can be used to indicate when a counter rolls over. For example, each tick of the seconds counter causes the 1HZ interrupt flag to be set. When the seconds counter rolls from 59 to 00, the minute counter increments and the MIN interrupt flag is set. The same is true for the minute counter with the HR signal, and the hour counter with the DAY signal.

8.3.2

Alarm

There are three alarm registers that mirror the three counter registers. An alarm is set by accessing the real-time clock alarm registers (ALRM_HM, ALRM_SEC, and DAYALARM) and loading the exact time that the alarm should generate an interrupt. When the TOD clock value and the alarm value coincide, if the ALM bit in the real-time clock interrupt enable register (RTCIENR) is set, an interrupt occurs. Please be noted that if the alarm is not disabled, it will reoccur every 65536 days. If a single alarm is desired, the alarm function must be disabled through the RTC Interrupt Enable Register (RTCIENR).

8.3.3

Minute Stopwatch

The minute stopwatch performs a countdown with a one minute resolution. It can be used to generate an interrupt on a minute boundary. For example, to turn off the LCD controller after five minutes of inactivity, program a value of 0x04 into the Stopwatch Count (CNT) field of the Stopwatch Minutes (STPWCH)

8-12



Initialization/Application Information register. At each minute, the value in the stopwatch is decremented. When the stopwatch value reaches -1, the interrupt occurs. The value of the register does not change until it is reprogrammed. Note that the actual delay includes the seconds from setting the stopwatch to the next minute tick.

8.4


8.4.1

Flow Chart of RTC Operation

Figure 8-12

shows the flow chart of a typical RTC operation.

configure RTC Control Register c onfig RTC Days Counter Register config RTC Seconds Counter Reg config RTC Hr/Min Counter Register config RTC Alarm Registers config RTC Interrupt Enable Reg

Check RTC Interrupt Status Register

Figure 8-12. Flow Chart of RTC Operation

8.4.2

Code Example to initialize the Real-Time Clock

Figure 8-13

is the code example of instructions for configuring RTC.

LDR r1,=RTC_BASE_ADDR



Real Time Clock

LDR r2,[r1,#0x10]

ORR r2,r2,#0x21

STR r2,[r1,#0x10] ; Software reset and 32k crystal

LDR r3,=0x0000

STR r3,[r1,#0x20] ;DAY

LDR r3,=0x00038

STR r3,[r1,#0x04] ;SECOND

LDR r3,=0x173B

STR r3,[r1] ;HR, MIN

LDR r3,=0x0001

STR r3,[r1,#0x24] ;Alarm Day

LDR r3,=0x0000

STR r3,[r1,#0x08] ;Alarm hour, minute

LDR r3,=0x01

STR r3,[r1,#0x0C] ;Alarm seconds

LDR r2,[r1,#0x18] ;set ALARM interrupt

ORR r2,r2,#0x4

STR r2,[r1,#0x18]

ALARM_STATUS_3

LDR r2,[r1,#0x18] ;check ALARM STATUS FLAG

TST r2,#0x04

BNE ALARM_STATUS_3

Figure 8-13. Code Example of ARM Instruction

8-14



Chapter 9


9.1

Introduction

This chapter explains the low-power operation of the MCF5235.

9.1.1

Features

The following features support low-power operation.

• Four modes of operation: run, wait, doze, and stop

• Ability to shut down most peripherals independently

• Ability to shut down the external CLKOUT pin

9.2


The power management programming model consists of registers from both the SCM and CCM memory

space, as shown in Table 9-1 .

Table 9-1. Power Management Memory Map

IPSBAR

Offset

1

Register

Width

(bits)


0x11_0004 Chip Configuration Register (CCR)

2

0x11_0007 Low-Power Control Register (LPCR)

16

8

R

R/W

0x0001

0x00

12.3.3.1/12-3

9.2.4.1/9-9


0x00_0010 Core Reset Status Register (CRSR)

3

0x00_0011 Core Watchdog Control Register (CWCR)

3

0x00_0012 Low-Power Interrupt Control Register (LPICR)

0x00_0013 Core Watchdog Service Register (CWSR)

3

32

8

8

8

R/W

R/W

R/W

R/W

0x00000000

0x00

0x00

9.2.1/9-2

10.5.2/10-4

10.5.1/10-3

9.2.2/9-6


0x00_0021 Peripheral Power Management Set Register (PPMRS)

8

32

8

R/W

R/W

W

0x00000001

0x00

13.5.5/13-10

9.2.1.1/9-4

9.2.3/9-8

0x00_0022 Peripheral Power Management Clear Register (PPMRC) 32 R/W 0x00

9.2.4/9-8

1

2


The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when accessing the LPCR.




3

The CRSR, CWCR, and CWSR are described in the System Control Module. They are shown here only to warn against accidental writes to these registers when accessing the LPICR.

Table 9-2.

IPSBAR Offset [31:24] [23:16] [15:8] [7:0]

0x00_000C

0x00_0010 Core Reset Status

Register (CRSR)

1

PPMRH[63:32]

Core Watchdog Control

Register (CWCR)

3

Low-Power Interrupt

Control Register

(LPICR)

Core Watchdog

Service Register

(CWSR)

3

0x00_0018 PPMRL[31:0]

0x00_0020

0x11_0004

— PPMRS

Chip Configuration Register (CCR)

2

PPMRC

Reserved

—

Low-Power Control

Register (LPCR)

1

2

The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register when accessing the LPCR.

9.2.1

Peripheral Power Management Registers (PPMRH, PPMRL)

The PPMRH and PPMRL registers provide a bit map for controlling the generation of the module clocks for each decoded address space associated with the IPS controller. The PPMR x provides a unique control bit for each of these address spaces that defines whether the module clock for the given space is enabled or disabled.

NOTE

It is software’s responsibility to appropriately disable module clocks using the PPMR x only when a module is completely unused or quiescent.

Since the operation of the IPS controller and the system control module (SCM) are fundamental to the operation of the system, the clocks for these three modules cannot be disabled.

The individual bits of the PPMR x can be modified using a read-modify-write to this register directly or indirectly through writes to the PPMRS and PPMRC registers to set/clear individual bits.

See Figure 7-2 and

Table 9-3

for the PPMRH definition.

9-2




IPSBAR

Offset:

0x00_000C (PPMRH)

31

0 R

W

Reset 0

30

0

0

23

0

22

0 R

W

Reset 0

15

0

0

14

0 R

W

Reset 0 0

29

0

0

21

0

0

13

CDRNGA

0

28

0

0

20

0

0

12

CDEPHY

0

27

0

0

19

0

0

11

CDCFM

0

26

0

0

18

0

0

10

CDFCAN

0

25

0

0

17

0

Access: read/write

0

9

CDPWM

0

24

0

0

16

0

0

8

CDGPT

0

R

W

Reset

7

CDADC

0

6

0

5

0

4

CDPIT1

3

CDPIT0

2

0

0 0 0 0 0

Figure 9-1. Peripheral Power Management Register High (PPMRH)

1 0

CDEPORT CDPORTS

0 0

Field

31–14

13

CDEPHY

12

CDRNGA

11

CDCFM

10

CDFCAN

9

CDPWM

8

CDGPT

Table 9-3. PPMRH Field Descriptions

Description


Disable clock to the EPHY (Ethernet PHY Module))

0 EPHY module clock is enabled

1 EPHY module clock is disabled

Disable clock to the RNGA (Random Number Generator Accelerator Module)

0 RNGA module clock is enabled

1 RNGA module clock is disabled

Disable clock to the CFM (Common Flash Module)

0 CFM module clock is enabled

1 CFM module clock is disabled

Disable clock to the FlexCAN module.

0 FlexCAN module clock is enabled

1 FlexCAN module clock is disabled

Disable clock to the PWM module.

0 PWM module clock is enabled

1 PWM module clock is disabled

Disable clock to the 16 bit general purpose timer module (GPT).

0 ICOC module clock is enabled

1 ICOC module clock is disabled




Field

7

CDADC

6–5

4

CDPIT1

3

CDPIT0

2

1

CDEPORT

0

CDPORTS

Table 9-3. PPMRH Field Descriptions (continued)

Description

Disable clock to the ADC module.

0 ADC module clock is enabled

1 ADC module clock is disabled


Disable clock to the PIT1 module.

0 PIT0 module clock is enabled

1 PIT1 module clock is disabled

Disable clock to the PIT0 module.

0 PIT0 module clock is enabled

1 PIT0 module clock is disabled


Disable clock to both EPORT modules.

0 EPORT module clock is enabled

1 EPORT module clock is disabled

Disable clock to the Ports module.

0 Ports module clock is enabled

1 Ports module clock is disabled

9.2.1.1

Peripheral Power Management Register Low (PPMRL)

IPSBAR

Offset:

0x00_0018 (PPMRL)

31

0 R

W

Reset 0

30

0

0

29

0

0

28

0

0

27

0

0

26

0

0

25

0

Access: read/write

0

R

W

Reset

23

0

0

R

W

Reset

15

CDTMR2

0

22

0

0

14

CDTMR1

0

21

CDFEC0

0

13

CDTMR0

0

20

0

0

12

CDRTC

0

19

0

0

11

0

18

CDINTC1

0

10

CDQSPI

0

17

CDINTC0

0

9

CDI2C

0 0

R

W

Reset

7

CDUART2

0

6

CDUART1

5

CDUART0

4

CDDMA

3

0

2

0

0 0 0 1 0

Figure 9-2. Peripheral Power Management Register Low (PPMRL)

1

CDG

0

24

0

0

16

CDTMR3

0

8

0

0

0

0

0

9-4



Field

31–22

21

CDFEC0

20–19

18

CDINTC0

17

CDINTC0

16

CDTMR3

15

CDTMR2

14

CDTMR1

13

CDTMR0

12

CDRTC

11

10

CDQSPI

9

CDI2C

8

—

7

CDUART2

6

CDUART1

Table 9-4. PPMRL Field Descriptions

Description


Disable clock to the FEC (Fast Ethernet Controller) module.

0 FEC module clock is enabled

1 FEC module clock is disabled


Disable clock to the INTC1 module.

0 INTC1 module clock is enabled

1 INTC1 module clock is disabled

Disable clock to the INTC0 module.

0 INTC0 module clock is enabled

1 INTC0 module clock is disabled

Disable clock to the DTIM3 module.

0 TMR3 module clock is enabled

1 TMR3 module clock is disabled










Disable clock to the RTC (Real-Time Clock) module.

0 RTC module clock is enabled

1 RTC module clock is disabled


Disable clock to the QSPI module.

0 QSPI module clock is enabled

1 QSPI module clock is disabled

Disable clock to the I2C module.

0 I2C module clock is enabled

1 I2C module clock is disabled


Disable clock to the UART2 module.

0 UART1 module clock is enabled

1 UART2 module clock is disabled





Freescale Semiconductor Preliminary


9-5


Field

5

CDUART0

4

CDDMA

3–2

1

CDG

0

Table 9-4. PPMRL Field Descriptions (continued)

Description




Disable clock to the DMA module.

0 DMA module clock is enabled

1 DMA module clock is disabled


Disable clock to the Global off-platform modules.

0 Global off-platform module clocks are enabled

1 Global off-platform module clocks are disabled


9.2.2

Low-Power Interrupt Control Register (LPICR)

Implementation of low-power stop mode and exit from a low-power mode via an interrupt require communication between the CPU and logic associated with the interrupt controller. The LPICR is an 8-bit register that enables entry into low-power stop mode, and includes the setting of the interrupt level needed to exit a low-power mode.

NOTE

The setting of the low-power mode select (LPMD) field in the power management module’s low-power control register (LPCR) determines which low-power mode the device enters when a STOP instruction is issued.

If this field is set to enter stop mode, then the ENBSTOP bit in the LPICR must also be set.

The following is the sequence of operations needed to enable this functionality:

1. The LPICR is programmed, setting the ENBSTOP bit (if stop mode is the desired low-power mode) and loading the appropriate interrupt priority level.

2. At the appropriate time, the processor executes the privileged STOP instruction. Once the processor has stopped execution, it asserts a specific Processor Status (PST) encoding. Issuing the

STOP instruction when the LPICR[ENBSTOP] bit is set causes the SCM to enter stop mode.

3. The entry into a low-power mode is processed by the low-power mode control logic, and the appropriate clocks (usually those related to the high-speed processor core) are disabled.

4. After entering the low-power mode, the interrupt controller enables a combinational logic path which evaluates any unmasked interrupt requests. The device waits for an event to generate an interrupt request with a priority level greater than the value programmed in

LPICR[XLPM_IPL[2:0]].

9-6




NOTE

Only a fixed (external) interrupt can bring a device out of stop mode. To exit from other low-power modes, such as doze or wait, either fixed or programmable interrupts may be used; however, the module generating the interrupt must be enabled in that particular low-power mode.

5. Once an appropriately high interrupt request level arrives, the interrupt controller signals its presence, and the SCM responds by asserting the request to exit low-power mode.

6. The low-power mode control logic senses the request signal and re-enables the appropriate clocks.

7. With the processor clocks enabled, the core processes the pending interrupt request.

Access: read/write IPSBAR

Offset:

0x00_0012 (LPICR)

7

R

W

Reset:

ENBSTOP

0

6 5

XLPM_IPL[2:0]

4 3

0

2

0

0 0 0 0 0

Figure 9-3. Low-Power Interrupt Control Register (LPICR)

1

0

0

0

0

0

Table 9-5. LPICR Field Description


7

ENBSTOP

Enable low-power stop mode.

0 Low-power stop mode disabled

1 Low-power stop mode enabled. Once the core is stopped and the signal to enter stop mode is asserted, processor clocks can be disabled.

6–4

XLPM_IPL

[2:0]

Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the low-power mode.Refer to

Table 9-6 .

3–0

—


XLPM_IPL[2:0]

000

001

010

011

100

101

11x

Table 9-6. XLPM_IPL Settings

Interrupts Level Needed to Exit Low-Power Mode

Any interrupt request exits low-power mode

Interrupt request levels 2–7 exit low-power mode





Interrupt request level 7 exits low-power mode




9.2.3

Peripheral Power Management Set Register (PPMRS)

The PPMRS register provides a simple memory-mapped mechanism to set a given bit in the PPMR x registers to disable the clock for a given IPS module without the need to perform a read-modify-write on the PPMR. The data value on a register write causes the corresponding bit in the PPMR x register to be set.

A data value of 64 to 127 provides a global set function, forcing the entire contents of the PPMR x to be set, disabling all IPS module clocks. Reads of this register return all zeroes. See

Figure 9-4

and

Table 9-7

for the PPMRS definition.

IPSBAR

Offset:

0x00_0021 (PPMRS)

R

W

Reset:

7

0

6 5 4 3 2 1

0 0 0 0

PPMRS

0 0

Figure 9-4. Peripheral Power Management Set Register (PPMRS)

0

Access: write-only

0

0

Field

7

6–0

PPMRS

Table 9-7. PPMRS Field Descriptions

Description


Set Module Clock Disable

0–63 Set corresponding bit in PPMR x , disabling the module clock

64–127 Set all bits in PPMR x , disabling all the module clocks

9.2.4

Peripheral Power Management Clear Register (PPMRC)

The PPMRC register provides a simple memory-mapped mechanism to clear a given bit in the PPMR x registers to enable the clock for a given IPS module without the need to perform a read-modify-write on the PPMR x . The data value on a register write causes the corresponding bit in the PPMR x register to be cleared. A data value of 64 to 127 provides a global clear function, forcing the entire contents of the

PPMR x to be zeroed, enabling all IPS module clocks. In the event on simultaneous writes of the PPMRS

and PPMRC, the write to the PPMRC takes priority. Reads of this register return all zeroes. See Figure 9-5

and Table 9-8 for the PPMRC definition.

IPSBAR

Offset:

0x00_0022 (PPMRC)

R

W

Reset:

7

0

6 5 4 3 2 1

0 0 0 0

PPMRC

0 0

Figure 9-5. Peripheral Power Management Clear Register (PPMRC)

0

Access: write-only

0

0

9-8




Field

7

6–0

PPMRC

Table 9-8. PPMRC Field Descriptions

Description


Clear Module Clock Disable

0–63 Clear corresponding bit in PPMR x , enabling the module clock

64–127 Clear all bits in PPMR x , enabling all the module clocks

9.2.4.1

Low-Power Control Register (LPCR)

The LPCR controls chip operation and module operation during low-power modes. The low-power control register (LPCR) specifies the low-power mode entered when the STOP instruction is issued, and controls clock activity in this low-power mode.


Offset:

0x11_0007 (LPCR)

7

R

W

Reset: 0

LPMD

6 5

0

4

0

3

STPMD

0 0 0 0 0

Figure 9-6. Low-Power Control Register (LPCR)

2

0

1

0

0

0

0

0

Field

7–6

LPMD

Table 9-9. LPCR Field Descriptions

Description

Low-power mode select. Used to select the low-power mode the chip enters once the ColdFire CPU executes the

STOP instruction. These bits must be written prior to instruction execution for them to take effect. The LPMD[1:0] bits are readable and writable in all modes. Below illustrates the four different power modes that can be configured with the LPMD bit field.

5–4

3

STPMD

2–0

LPMD[1:0]

11

10

01

00

Mode

STOP

WAIT

DOZE

RUN

Note: If LPCR[LPMD] is cleared, then the device will stop executing code upon issue of a STOP instruction.

However, no clocks will be disabled.


CLKOUT stop mode. Controls CLKOUT operation during stop mode.

0 CLKOUT enabled during stop mode.

1 CLKOUT disabled during stop mode.





9.3

IPS Bus Timeout Monitor

The IPS controller implements a bus timeout monitor to insure that every IPS bus cycle is properly terminated within a programmed period of time. The monitor continually checks for termination of each

IPS bus cycle and completes the cycle if there is no response when the programmed monitor cycle count is reached. The error termination is propagated onto the system bus and eventually back to the ColdFire

Core.

The monitor can be programmed from 8–1024 system bus cycles under control of the IPS Bus Monitor

Timeout Register (IPSBMT). The timeout value must be selected so that it is larger than the response time of the slowest IPS peripheral device. The bus timeout monitor begins counting on the initial assertion of any IPS module enable and continues to count until the bus cycle is terminated via the negation of ips_xfr_wait . If the programmed timeout value is reached before a termination, the bus monitor completes the cycle with an error termination. At reset, the IPSBMT is enabled with a maximum timeout value. See

Figure 9-7 and Table 9-10 for the IPSBMT definition.

0x00_0023 (IPSBMT)

31

R 0

W

Reset 0

30

0

0

29

0

0

28

0

0

27

0

0

26

0

0

25

0

0

24

0

0

23

0

0

22

0

0

21

0

0

20

0

0

19

0

0

18

0

Access: read/write

17

0

16

0

0 0 0

15

R 0

W

Reset 0

14

0

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

0 0 0 0 0 0 0 0 0 0

Figure 9-7. IPS Bus Timeout Monitor (IPSBMT) Register

3

BME

1

2

0

1

BMT

0

0

0

Field

15–4

3

BME

2–0

BMT[2:0]

Table 9-10. IPSBMT Field Description

Description


Bus Timeout Monitor Enable

0 The bus timeout monitor is disabled.

1 The bus timeout monitor is enabled.

Bus Monitor Timeout. This field selects the timeout period (measured in system bus clock cycles) for the bus monitor.

000 1024 cycles

001 512 cycles

010 256 cycles

011 128 cycles

100 64 cycles

101 32 cycles

110 16 cycles

111 8 cycles

9-10




9.4


The functions and characteristics of the low-power modes, and how each module is affected by, or affects these modes are discussed in this section.

9.4.1

Low-Power Modes

The system enters a low-power mode by executing a STOP instruction. Which mode the device actually enters (either stop, wait, or doze) depends on what is programmed in LPCR[LPMD]. Entry into any of these modes idles the CPU with no cycles active, powers down the system and stops all internal clocks appropriately. During stop mode, the system clock is stopped low.

For entry into stop mode, the LPICR[ENBSTOP] bit must be set before a STOP instruction is issued.

A wakeup event is required to exit a low-power mode and return to run mode. Wakeup events consist of any of these conditions:

• Any type of reset

• Any valid, enabled interrupt request

Exiting from low power mode via an interrupt request requires:

• An interrupt request whose priority is higher than the value programmed in the XLPM_IPL field of the LPICR.

• An interrupt request whose priority higher than the value programmed in the interrupt priority mask (I) field of the core’s status register.

• An interrupt request from a source which is not masked in the interrupt controller’s interrupt mask register.

• An interrupt request which has been enabled at the module of the interrupt’s origin.

9.4.1.1

Run Mode

Run mode is the normal system operating mode. Current consumption in this mode is related directly to the system clock frequency.

9.4.1.2

Wait Mode

Wait mode is intended to be used to stop only the CPU and memory clocks until a wakeup event is detected. In this mode, peripherals may be programmed to continue operating and can generate interrupts, which cause the CPU to exit from wait mode.

9.4.1.3

Doze Mode

Doze mode affects the CPU in the same manner as wait mode, except that each peripheral defines individual operational characteristics in doze mode. Peripherals which continue to run and have the capability of producing interrupts may cause the CPU to exit the doze mode and return to run mode.

Peripherals which are stopped will restart operation on exit from doze mode as defined for each peripheral.




9.4.1.4

Stop Mode

Stop mode affects the CPU in the same manner as the wait and doze modes, except that all clocks to the system are stopped and the peripherals cease operation.

Stop mode must be entered in a controlled manner to ensure that any current operation is properly terminated. When exiting stop mode, most peripherals retain their pre-stop status and resume operation.

The following subsections specify the operation of each module while in and when exiting low-power modes.

9.4.1.5

Peripheral Shut Down

Most peripherals may be disabled by software in order to cease internal clock generation and remain in a static state. Each peripheral has its own specific disabling sequence (refer to each peripheral description for further details). A peripheral may be disabled at any time and will remain disabled during any low-power mode of operation.

9.4.2

Peripheral Behavior in Low-Power Modes

9.4.2.1

ColdFire Core

The ColdFire core is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.

9.4.2.2

Static Random-Access Memory (SRAM)

SRAM is disabled during any low-power mode. No recovery time is required when exiting any low-power mode.

9.4.2.3

Flash

9.4.2.4

The Flash module is in a low-power state if not being accessed. No recovery time is required after exit from any low-power mode. System Control Module (SCM)

The SCM’s core watchdog timer can bring the device out of all low-power modes except stop mode. In stop mode, all clocks stop, and the core watchdog does not operate.

When enabled, the core watchdog can bring the device out of low-power mode via a core watchdog interrupt. This system setup must meet the conditions specified in

Section 9.4.1, “Low-Power Modes

” for the core watchdog interrupt to bring the part out of low-power mode.

9.4.2.5

DMA Controller (DMA0–DMA3)

In wait and doze modes, the DMA controller is capable of bringing the device out of a low-power mode by generating an interrupt either upon completion of a transfer or upon an error condition. The completion of transfer interrupt is generated when DMA interrupts are enabled by the setting of the DCR[INT] bit, and an interrupt is generated when the DSR[DONE] bit is set. The interrupt upon error condition is

9-12



Power Management generated when the DCR[INT] bit is set, and an interrupt is generated when either the CE, BES or BED bit in the DSR becomes set.

The DMA controller is stopped in stop mode and thus cannot cause an exit from this low-power mode.

9.4.2.6

UART Modules (UART0, UART1, and UART2)

In wait and doze modes, the UART may generate an interrupt to exit the low-power modes.

• Clearing the transmit enable bit (TE) or the receiver enable bit (RE) disables UART functions.

• The UARTs are unaffected by wait mode and may generate an interrupt to exit this mode.

In stop mode, the UARTs stop immediately and freeze their operation, register values, state machines, and external pins. During this mode, the UART clocks are shut down. Coming out of stop mode returns the

UARTs to operation from the state prior to the low-power mode entry.

9.4.2.7

I

2

C Module

When the I mode, the I

2

2

C Module is enabled by the setting of the I2CR[IEN] bit and when the device is not in stop

C module is operable and may generate an interrupt to bring the device out of a low-power mode. For an interrupt to occur, the I2CR[IIE] bit must be set to enable interrupts, and the setting of the

I2SR[IIF] generates the interrupt signal to the CPU and interrupt controller. The setting of I2SR[IIF] signifies either the completion of one byte transfer or the reception of a calling address matching its own specified address when in slave receive mode.

In stop mode, the I

2

C Module stops immediately and freezes operation, register values, and external pins.

Upon exiting stop mode, the I

2

C resumes operation unless stop mode was exited by reset.

9.4.2.8


In wait and doze modes, the queued serial peripheral interface (QSPI) may generate an interrupt to exit the low-power modes.

• Clearing the QSPI enable bit (SPE) disables the QSPI function.

• The QSPI is unaffected by wait mode and may generate an interrupt to exit this mode.

In stop mode, the QSPI stops immediately and freezes operation, register values, state machines, and external pins. During this mode, the QSPI clocks are shut down. Coming out of stop mode returns the QSPI to operation from the state prior to the low-power mode entry.

9.4.2.9


In wait and doze modes, the DMA timers may generate an interrupt to exit a low-power mode. This interrupt can be generated when the DMA Timer is in either input capture mode or reference compare mode.

In input capture mode, where the capture enable (CE) field of the timer mode register (DTMR) has a non-zero value and the DMA enable (DMAEN) bit of the DMA timer extended mode register (DTXMR) is cleared, an interrupt is issued upon a captured input. In reference compare mode, where the output



Power Management reference request interrupt enable (ORRI) bit of DTMR is set and the DTXMR[DMAEN] bit is cleared, an interrupt is issued when the timer counter reaches the reference value.

DMA timer operation is disabled in stop mode, but the DMA timer is unaffected by either the wait or doze modes and may generate an interrupt to exit these modes. Upon exiting stop mode, the timer will resume operation unless stop mode was exited by reset.

9.4.2.10

Interrupt Controllers (INTC0, INTC1)

The interrupt controller is not affected by any of the low-power modes. All logic between the input sources and generating the interrupt to the processor will be combinational to allow the ability to wake up the CPU processor during low-power stop mode when all system clocks are stopped.

An interrupt request will cause the CPU to exit a low-power mode only if that interrupt’s priority level is at or above the level programmed in the interrupt priority mask field of the CPU’s status register (SR). The interrupt must also be enabled in the interrupt controller’s interrupt mask register as well as at the module from which the interrupt request would originate.

9.4.2.11

I/O Ports

The I/O ports are unaffected by entry into a low-power mode. These pins may impact low-power current draw if they are configured as outputs and are sourcing current to an external load. If low-power mode is exited by a reset, the state of the I/O pins will revert to their default direction settings.

9.4.2.12

Reset Controller

A power-on reset (POR) will always cause a chip reset and exit from any low-power mode.

In wait and doze modes, asserting the external RESET pin for at least four clocks will cause an external reset that will reset the chip and exit any low-power modes.

In stop mode, the RESET pin synchronization is disabled and asserting the external RESET pin will asynchronously generate an internal reset and exit any low-power modes. Registers will lose current values and must be reconfigured from reset state if needed.

If the phase lock loop (PLL) in the clock module is active and if the appropriate (LOCRE, LOLRE) bits in the synthesizer control register are set, then any loss-of-clock or loss-of-lock will reset the chip and exit any low-power modes.

If the watchdog timer is still enabled during wait or doze modes, then a watchdog timer timeout may generate a reset to exit these low-power modes.

When the CPU is inactive, a software reset cannot be generated to exit any low-power mode.

9.4.2.13

Chip Configuration Module

The Chip Configuration Module is unaffected by entry into a low-power mode. If low-power mode is exited by a reset, chip configuration may be executed if configured to do so.

9-14




9.4.2.14

Clock Module

In wait and doze modes, the clocks to the CPU, Flash, and SRAM will be stopped and the system clocks to the peripherals are enabled. Each module may disable the module clocks locally at the module level. In stop mode, all clocks to the system will be stopped.

During stop mode, the PLL continues to run. The external CLKOUT signal may be enabled or disabled when the device enters stop mode, depending on the LPCR[STPMD] bit settings.The external CLKOUT output pin may be disabled to lower power consumption via the SYNCR[DISCLK] bit. The external

CLKOUT pin function is enabled by default at reset.

9.4.2.15

Edge Port

In wait and doze modes, the edge port continues to operate normally and may be configured to generate interrupts (either an edge transition or low level on an external pin) to exit the low-power modes.

In stop mode, there is no system clock available to perform the edge detect function. Thus, only the level detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit the stop mode.

9.4.2.16

Programmable Interrupt Timers (PIT0–PIT1)

In stop mode (or in doze mode, if so programmed), the programmable interrupt timer (PIT) ceases operation, and freezes at the current value. When exiting these modes, the PIT resumes operation from the stopped value. It is the responsibility of software to avoid erroneous operation.

When not stopped, the PIT may generate an interrupt to exit the low-power modes.

9.4.2.17

FlexCAN

When enabled, the FlexCAN module is capable of generating interrupts and bringing the device out of a low-power mode. The module has 35 interrupt sources (32 sources due to message buffers and 3 sources due to Bus-off, Error and Wake-up).

When in stop mode, a recessive to dominant transition on the CAN bus causes the WAKE-INT bit in the error & status register to be set. This event can cause a CPU interrupt if the WAKE-MASK bit in module configuration register (MCR) is set.

When setting stop mode in the FlexCAN (by setting the MCR[STOP] bit), the FlexCAN checks for the

CAN bus to be either idle or waits for the third bit of intermission and checks to see if it is recessive. When this condition exists, the FlexCAN waits for all internal activity other than in the CAN bus interface to complete and then the following occurs:

• The FlexCAN shuts down its clocks, stopping most of the internal circuits, to achieve maximum possible power saving.

• The internal bus interface logic continues operation, enabling CPU to access the MCR register.

• The FlexCAN ignores its Rx input pin, and drives its Tx pins as recessive.

• FlexCAN loses synchronization with the CAN bus, and STOP_ACK and NOT_RDY bits in MCR register are set.




Exiting stop mode is done in one of the following ways:

• Reset the FlexCAN (either by hard reset or by asserting the SOFT_RST bit in MCR).

• Clearing the STOP bit in the MCR.

• Self-wake mechanism. If the SELF-WAKE bit in the MCR is set at the time the FlexCAN enters stop mode, then upon detection of recessive to dominant transition on the CAN bus, the FlexCAN resets the STOP bit in the MCR and resumes its clocks.

Recommendations for, and features of, FlexCAN’s stop mode operation are as follows:

• Upon stop/self-wake mode entry, the FlexCAN tries to receive the frame that caused it to wake; that is, it assumes that the dominant bit detected is a start-of-frame bit. It does not arbitrate for the

CAN bus then.

• Before asserting stop Mode, the CPU should disable all interrupts in the FlexCAN, otherwise it may be interrupted while in stop mode upon a non-wake-up condition. If desired, the

WAKE-MASK bit should be set to enable the WAKE-INT.

• If stop mode is asserted while the FlexCAN is BUSOFF (see error and status register), then the

FlexCAN enters stop mode and stops counting the synchronization sequence; it continues this count once stop mode is exited.

• The correct flow to enter stop mode with SELF-WAKE:

— assert SELF-WAKE at the same time as STOP.

— wait for STOP_ACK bit to be set.

• The correct flow to negate STOP with SELF-WAKE:

— negate SELF-WAKE at the same time as STOP.

— wait for STOP_ACK negation.

• SELF-WAKE should be set only when the MCR[STOP] bit is negated and the FlexCAN is ready; that is, the NOT_RDY bit in the MCR is negated.

• If STOP and SELF_WAKE are set and if a recessive to dominant edge immediately follows on the

CAN bus, the STOP_ACK bit in the MCR may never be set, and the STOP bit in the MCR is reset.

• If the user does not want to have old frames sent when the FlexCAN is awakened (STOP with

Self-Wake), the user should disable all Tx sources, including remote-response, before stop mode entry.

• If halt mode is active at the time the STOP bit is set, then the FlexCAN assumes that halt mode should be exited; hence it tries to synchronize to the CAN bus (11 consecutive recessive bits), and only then does it search for the correct conditions to stop.

• Trying to stop the FlexCAN immediately after reset is allowed only after basic initialization has been performed.

If stop with self-wake is activated, and the FlexCAN operates with single system clock per time-quanta, then there are extreme cases in which FlexCAN's wake-up upon recessive to dominant edge may not conform to the standard CAN protocol, in the sense that the FlexCAN synchronization is shifted one time quanta from the required timing. This shift lasts until the next recessive to dominant edge, which re-synchronizes the FlexCAN back to conform to the protocol. The same holds for auto-power save mode upon wake-up by recessive to dominant edge.

9-16




The auto-power save mode in the FlexCAN is intended to enable NORMAL operation with optimized power saving. Upon setting the AUTO POWER SAVE bit in the MCR register, the FlexCAN looks for a set of conditions in which there is no need for clocks to run. If all these conditions are met, then the

FlexCAN stops its clocks, thus saving power. While its clocks are stopped, if any of the conditions below is not met, the FlexCAN resumes its clocks. It then continues to monitor the conditions and stops/resumes its clocks appropriately.

The following are conditions for the automatic shut-off of FlexCAN clocks:

• No Rx/Tx frame in progress.

• No moving of Rx/Tx frames between SMB and MB and no Tx frame is pending for transmission in any MB.

• No host access to the FlexCAN module.

• The FlexCAN is neither in halt mode (MCR bit 8), in stop mode (MCT bit 15), nor in BUSOFF.

9.4.2.18

PWM Module

The PWM module is user programmable as to how it behaves when the device enters wait mode

(PWMCTL[PSWAI]) and doze mode (PWMCTL[PFRZ]). If either of these bits are set the PWM input clock to the prescalar will be disabled during the respective low power mode.

In stop mode the input clock is disabled and PWM generation is halted.

9.4.2.19

BDM

Entering halt mode via the BDM port (by asserting the external BKPT pin) will cause the CPU to exit any low-power mode.

9.4.2.20

JTAG

The JTAG (Joint Test Action Group) controller logic is clocked using the TCLK input and is not affected by the system clock. The JTAG cannot generate an event to cause the CPU to exit any low-power mode.

Toggling TCLK during any low-power mode will increase the system current consumption.

9.4.3

Summary of Peripheral State During Low-Power Modes

The functionality of each of the peripherals and CPU during the various low-power modes is summarized

in Table 9-11 . The status of each peripheral during a given mode refers to the condition the peripheral

automatically assumes when the STOP instruction is executed and the LPCR[LPMD] field is set for the particular low-power mode. Individual peripherals may be disabled by programming its dedicated control bits. The wakeup capability field refers to the ability of an interrupt or reset by that peripheral to force the

CPU into run mode.




Module

Table 9-11. CPU and Peripherals in Low-Power Modes

Peripheral Status

1

/ Wakeup Capability

Wait Mode Doze Mode Stop Mode

CPU

SRAM

Flash

System Control Module

Random Number Generator Accelerator

DMA Controller

UART0, UART1 and UART2

I

2

C Module

Stopped

Stopped

Stopped

Enabled

Enabled

Enabled

Enabled

Enabled

No

No

No

Yes

3

No

Yes

Yes

2

Yes

2

Yes

2

Yes

2

Yes

2

Stopped

Stopped

Stopped

Enabled

Stopped

Enabled

Enabled

Enabled

No

No

No

Yes

3

No

Yes

Yes

2

Yes

2

Yes

2

Yes

2

Yes

2

Stopped

Stopped

Stopped

Stopped

Stopped

Stopped

Stopped

Stopped

No

No

No

No

No

No

No

No

QSPI

DMA Timers

Interrupt Controller

I/O Ports

Reset Controller

Chip Configuration Module

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

No

Yes

3

No

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

No

Yes

3

No

Stopped

Stopped

Enabled

Enabled

Enabled

Stopped

No

No

Yes

2

No

Yes

No

3

Power Management

Clock Module

Real-Time Clock Module

Edge port

Programmable Interrupt Timers

ADC

General Purpose Timer

FlexCAN

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Enabled

Yes

2

Yes

2

Yes

2

Yes

2

No

Yes

2

Yes

2

Yes

2

No

Yes

4

Enabled

Enabled

Enabled

Enabled

Program

Program

Enabled

Enabled

Yes

2

Yes

2

Yes

2

Yes

2

No

Yes

2

Yes

2

Yes

2

No

Yes

4

Stopped

Enabled

Enabled

Stopped

Stopped

Stopped

Stopped

Stopped

No

Yes

???

Yes

No

No

No

No

2

2

PWM

BDM

Program

Enabled

Program

Enabled

Stopped

Enabled

No

Yes

4

JTAG Enabled No Enabled No Enabled No

3

4

1

2

“Program” Indicates that the peripheral function during the low-power mode is dependent on programmable bits in the peripheral register map.

These modules can generate a interrupt which will exit a low-power mode. The CPU will begin to service the interrupt exception after wakeup.

These modules can generate a reset which will exit any low-power mode.

The BDM logic is clocked by a separate TCLK clock. Entering halt mode via the BDM port exits any low-power mode.

Upon exit from halt mode, the previous low-power mode will be re-entered and changes made in halt mode will remain in effect.

9-18







9-20



Chapter 10


10.1

Introduction

The reset controller is provided to determine the cause of reset, assert the appropriate reset signals to the system, and keep a history of what caused the reset. The low voltage detection module, which generates low-voltage detect (LVD) interrupts and resets, is implemented within the reset controller module.

10.2

Features

Module features include the following:

• Seven sources of reset:

— External reset input

— Power-on reset (POR)

— Phase locked-loop (PLL) loss of lock

— PLL loss of clock

— Software

— Low-voltage detector (LVD)

— JTAG CLAMP, HIGHZ and EXTEST instructions

• Software-assertable RSTO pin independent of chip reset state

• Software-readable status flags indicating the cause of the last reset

• LVD control and status bits for setup and use of LVD reset or interrupt

10.3

Block Diagram

Figure 10-1

illustrates the reset controller and is explained in the following sections.



Preliminary

10-1


RSTI

Pin

Power-On

Reset

PLL

Loss of Clock

PLL

Loss of Lock

Software

Reset

LVD

Detect

Reset

Controller

RSTO

Pin

To Internal Resets

Figure 10-1. Reset Controller Block Diagram

10.4

Signals

Table 10-1

provides a summary of the reset controller signal properties. The signals are described in the following sections.

Table 10-1. Reset Controller Signal Properties

Name Direction

Input

Hysteresis

RSTI I Yes

RSTO O —

1

RSTI is always synchronized except when in low-power stop mode.

Input

Synchronization

Yes

1

—

10.4.1

RSTI

Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be recognized and latched.

10.4.2

RSTO

This active-low output signal is driven low when the internal reset controller module resets the chip. When

RSTO is active, the user can drive override options on the data bus.

10.5


The reset controller programming model consists of these registers:

• Reset control register (RCR)—selects reset controller functions

• Reset status register (RSR)—reflects the state of the last reset source

10-2



Preliminary


See Table 10-2 for the memory map and the following paragraphs for a description of the registers.

Table 10-2. Reset Controller Memory Map

IPSBAR

Offset

1

Register

0x11_0000 Reset Control Register (RCR)

Width

(bits)


8 R/W

0x11_0001 Reset Status Register (RSR) 8 R

1


0x05

10.5.1/10-3

10.5.2/10-4

10.5.1

Reset Control Register (RCR)

The RCR allows software control for requesting a reset, independently asserting the external RSTO pin, and controlling low-voltage detect (LVD) functions.

Access: User read/write IPSBAR

Offset:

0x11_0000 (RCR)

7

R

W

Reset:

SOFTRST

0

6

FRCRSTO

UT

5

0

4

LVDF

3

LVDIE

2

LVDRE

0 0 0 0

Figure 10-2. Reset Control Register (RCR)

1

1

0

0

0

LVDE

1

Table 10-3. RCR Field Descriptions


7

SOFTRST

Allows software to request a reset. The reset caused by setting this bit clears this bit.

1 Software reset request

0 No software reset request

6

FRCRSTOUT

Allows software to assert or negate the external RSTO pin.

1 Assert RSTO pin

0 Negate RSTO pin

CAUTION: External logic driving reset configuration data during reset needs to be considered when asserting the RSTO pin when setting FRCRSTOUT.


5

—

4

LVDF

LVD flag. Indicates the low-voltage detect status if LVDE is set. Write a 1 to clear the LVDF bit.

1 Low voltage has been detected

0 Low voltage has not been detected

NOTE: The setting of this flag causes an LVD interrupt if LVDE and LVDIE bits are set and LVDRE is cleared when the supply voltage V

DD

drops below V

DD

(minimum). The vector for this interrupt is shared with INT0 of the EPORT module. Interrupt arbitration in the interrupt service routine is necessary if both of these interrupts are enabled. Also, LVDF is not cleared at reset, however it will always initialize to a zero since the part will not come out of reset while in a low-power state (LVDE/LVDRE bits are enabled out of reset).



Preliminary

10-3


Field

3

LVDIE

2

LVDRE

1

—

0

LVDE

Table 10-3. RCR Field Descriptions (continued)

Description

LVD interrupt enable. Controls the LVD interrupt if LVDE is set. This bit has no effect if the LVDE bit is a logic 0.

1 LVD interrupt enabled

0 LVD interrupt disabled

LVD reset enable. Controls the LVD reset if LVDE is set. This bit has no effect if the LVDE bit is a logic 0. LVD reset has priority over LVD interrupt, if both are enabled.

1 LVD reset enabled

0 LVD reset disabled


Controls whether the LVD is enabled.

1 LVD is enabled

0 LVD is disabled

10.5.2

Reset Status Register (RSR)

The RSR contains a status bit for every reset source. When reset is entered, the cause of the reset condition is latched, along with a value of 0 for the other reset sources that were not pending at the time of the reset condition. These values are then reflected in RSR. One or more status bits may be set at the same time.

The cause of any subsequent reset is also recorded in the register, overwriting status from the previous reset condition.

RSR can be read at any time. Writing to RSR has no effect.

Access: User read-only IPSBAR

Offset:

0x11_0001 (RSR)

R

W

7

0

Reset: Reset Dependent

6

LVD

5

SOFT

4

0

3

POR

Figure 10-3. Reset Status Register (RSR)

2

EXT

1

LOC

0

LOL

Field

7

—

6

LVD

Table 10-4. RSR Field Descriptions


Description

5

SOFT

Low voltage detect. Indicates that the last reset state was caused by an LVD reset.

1 Last reset state was caused by an LVD reset

0 Last reset state was not caused by an LVD reset

Software reset flag. Indicates that the last reset was caused by software.

1 Last reset caused by software

0 Last reset not caused by software

10-4



Preliminary

Field

4

—

3

POR

2

EXT

1

LOC

0

LOL


Table 10-4. RSR Field Descriptions (continued)

Description


Power-on reset flag. Indicates that the last reset was caused by a power-on reset.

1 Last reset caused by power-on reset

0 Last reset not caused by power-on reset

External reset flag. Indicates that the last reset was caused by an external device asserting the external RSTI pin.

1 Last reset state caused by external reset

0 Last reset not caused by external reset

Loss-of-clock reset flag. Indicates that the last reset state was caused by a PLL loss of clock.

1 Last reset caused by loss of clock

0 Last reset not caused by loss of clock

Loss-of-lock reset flag. Indicates that the last reset state was caused by a PLL loss of lock.

1 Last reset caused by a loss of lock

0 Last reset not caused by loss of lock

10.6


10.6.1

Reset Sources

Table 10-5

defines the sources of reset and the signals driven by the reset controller.

Table 10-5. Reset Source Summary

Type Source

Power on

External RSTI pin (not stop mode)

External RSTI pin (during stop mode)

Loss-of-clock

Loss-of-lock

Software

LVD reset

Asynchronous

Synchronous

Asynchronous

Asynchronous

Asynchronous

Synchronous

Asynchronous

To protect data integrity, a synchronous reset source is not acted upon by the reset control logic until the end of the current bus cycle. Reset is then asserted on the next rising edge of the system clock after the cycle is terminated. Whenever the reset control logic must synchronize reset to the end of the bus cycle, the internal bus monitor is automatically enabled regardless of the BME bit state in the chip configuration register (CCR). Then, if the current bus cycle is not terminated normally, the bus monitor terminates the cycle based on the length of time programmed in the BMT field of the CCR.

Internal byte, word, or longword writes are guaranteed to complete without data corruption when a synchronous reset occurs. External writes, including longword writes to 16-bit ports, are also guaranteed to complete.



Preliminary

10-5


Asynchronous reset sources usually indicate a catastrophic failure. Therefore, the reset control logic does not wait for the current bus cycle to complete. Reset is asserted immediately to the system.

10.6.1.1

Power-On Reset

At power up, the reset controller asserts RSTO. RSTO continues to be asserted until V

DD

has reached a minimum acceptable level and, if PLL clock mode is selected, until the PLL achieves phase lock. Then after approximately another 512 cycles, RSTO is negated and the part begins operation.

10.6.1.2

External Reset

Asserting the external RSTI for at least four rising CLKOUT edges causes the external reset request to be recognized and latched. The bus monitor is enabled and the current bus cycle is completed. The reset controller asserts RSTO for approximately 512 cycles after RSTI is negated and the PLL has acquired lock.

The part then exits reset and begins operation.

In low-power stop mode, the system clocks are stopped. Asserting the external RSTI in stop mode causes an external reset to be recognized.

10.6.1.3

Loss-of-Clock Reset

This reset condition occurs in PLL clock mode when the LOCRE bit in the SYNCR is set and either the

PLL reference or the PLL itself fails. The reset controller asserts RSTO for approximately 512 cycles after the PLL has acquired lock. The device then exits reset and begins operation.

10.6.1.4

Loss-of-Lock Reset

This reset condition occurs in PLL clock mode when the LOLRE bit in the SYNCR is set and the PLL loses lock. The reset controller asserts RSTO for approximately 512 cycles after the PLL has acquired lock. The device then exits reset and resumes operation.

10.6.1.5

Software Reset

A software reset occurs when the SOFTRST bit is set. If the RSTI is negated and the PLL has acquired lock, the reset controller asserts RSTO for approximately 512 cycles. Then the device exits reset and resumes operation.

10.6.1.6

LVD Reset

The LVD reset will occur when the supply input voltage, V

DD, drops below V

LVD

(minimum).

10.6.2

Reset Control Flow

The reset logic control flow is shown in

Figure 10-4

. In this figure, the control state boxes have been numbered, and these numbers are referred to (within parentheses) in the flow description that follows. All cycle counts given are approximate.

10-6



Preliminary


0 POR OR LVD

12

NEGATE RSTO

1

LOSS OF CLOCK?

Y

N

2

LOSS OF LOCK?

Y

N

3 RSTI

PIN OR WD TIMEOUT

OR SW RESET?

Y

N

5

ENABLE BUS MONITOR

6

BUS CYCLE

COMPLETE?

Y

7

ASSERT RSTO AND

LATCH RESET STATUS

N

8

RSTI NEGATED?

N

Y

9

PLL MODE?

N

10

WAIT 512 CLKOUT CYCLES

Y

11

RCON ASSERTED?

Y

N

Figure 10-4. Reset Control Flow

4

ASSERT RSTO AND

LATCH RESET STATUS

9A

PLL LOCKED?

Y

N

11A

LATCH CONFIGURATION



Preliminary

10-7


10.6.2.1

Synchronous Reset Requests

In this discussion, the references in parentheses refer to the state numbers in

Figure 10-4

. All cycle counts given are approximate.

If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges (3) and if software requests a reset, the reset control logic latches the reset request internally and enables the bus monitor (5). When the current bus cycle is completed (6), RSTO is asserted (7). The reset control logic waits until the RSTI signal is negated (8) and for the PLL to attain lock (9, 9A) before waiting 512

CLKOUT cycles (1). The reset control logic may latch the configuration according to the RCON signal level (11, 11A) before negating RSTO (12).

If the external RSTI signal is asserted by an external device for at least four rising CLKOUT edges during the 512 count (10) or during the wait for PLL lock (9A), the reset flow switches to (8) and waits for the

RSTI signal to be negated before continuing.

10.6.2.2

Internal Reset Request

If reset is asserted by an asynchronous internal reset source, such as loss of clock (1) or loss of lock (2), the reset control logic asserts RSTO (4). The reset control logic waits for the PLL to attain lock (9, 9A) before waiting 512 CLKOUT cycles (1). Then the reset control logic may latch the configuration according to the RCON pin level (11, 11A) before negating RSTO (12).

If loss of lock occurs during the 512 count (10), the reset flow switches to (9A) and waits for the PLL to lock before continuing.

10.6.2.3

Power-On Reset/Low-Voltage Detect Reset

When the reset sequence is initiated by power-on reset (0), the same reset sequence is followed as for the other asynchronous reset sources.

10.6.3

Concurrent Resets

This section describes the concurrent resets. As in the previous discussion, references in parentheses refer

to the state numbers in Figure 10-4 .

10.6.3.1

Reset Flow

If a power-on reset or low-voltage detect condition is detected during any reset sequence, the reset sequence starts immediately (0).

If the external RSTI pin is asserted for at least four rising CLKOUT edges while waiting for PLL lock or the 512 cycles, the external reset is recognized. Reset processing switches to wait for the external RSTI pin to negate (8).

If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete

(5, 6) for an external reset request, the cycle is terminated. The reset status bits are latched (7) and reset processing waits for the external RSTI pin to negate (8).

10-8



Preliminary


If a loss-of-clock or loss-of-lock condition is detected during the 512 cycle wait, the reset sequence continues after a PLL lock (9, 9A).

10.6.3.2

Reset Status Flags

For a POR reset, the POR and LVD bits in the RSR are set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared even if another type of reset condition is detected during the reset sequence for the POR.

If a loss-of-clock or loss-of-lock condition is detected while waiting for the current bus cycle to complete

(5, 6) for an external reset request, the EXT, SOFT, and/or WDR bits along with the LOC and/or LOL bits are set.

If the RSR bits are latched (7) during the EXT, SOFT, and/or WDR reset sequence with no other reset conditions detected, only the EXT, SOFT, and/or WDR bits are set.

If the RSR bits are latched (4) during the internal reset sequence with the RSTI pin not asserted and no

SOFT or WDR event, then the LOC and/or LOL bits are the only bits set.

For a LVD reset, the LVD bit in the RSR is set, and the SOFT, WDR, EXT, LOC, and LOL bits are cleared to 0, even if another type of reset condition is detected during the reset sequence for LVD.



Preliminary

10-9


10-10



Preliminary

Chapter 11


11.1

Introduction

This chapter describes the on-chip static RAM (SRAM) implementation, including general operations, configuration, and initialization. It also provides information and examples showing how to minimize power consumption when using the SRAM.

11.1.1

Features

The major features include the following:

• One 256-Kbyte SRAM (128 Kbyte for MCF52230 and MCF52231)

• Single-cycle access

• Physically located on the processor's high-speed local bus

• Memory location programmable on any 0-modulo- Kbyte address

• Byte, word, and longword address capabilities

11.1.2

Operation

The SRAM module provides a general-purpose memory block that the ColdFire processor can access in a single cycle. The location of the memory block can be specified to any 0-modulo-K address within the

256-byte address space. The memory is ideal for storing critical code or data structures or for use as the system stack. Because the SRAM module is physically connected to the processor's high-speed local bus, it can service processor-initiated accesses or memory-referencing commands from the debug module.

The SRAM is dual-ported to provide access. The SRAM is partitioned into two physical memory arrays to allow simultaneous access to both arrays by the processor core and another bus master. See Chapter 10,

“System Control Module (SCM),” for more information.

11.2

Memory Map/Register Description

The SRAM programming model, shown in

Table 11-1

, includes a description of the SRAM base address register (RAMBAR), SRAM initialization, and power management.



Preliminary

11-1


Table 11-1. SRAM Programming Model

CPU Space

(Rc)

0xC05

Register

Width

(bits)


Written w/ MOVEC

Section/Page


RAM Base Address Register (RAMBAR) 32 R/W 0x0000_0000 Yes

11.2.1/11-2

11.2.1

SRAM Base Address Register (RAMBAR)

The configuration information in the SRAM base address register (RAMBAR) controls the operation of the SRAM module.

• The RAMBAR holds the base address of the SRAM. The MOVEC instruction provides write-only access to this register.

• The RAMBAR can be read or written from the debug module.

• All undefined bits in the register are reserved. These bits are ignored during writes to the

RAMBAR and return zeroes when read from the debug module.

• The RAMBAR valid bit is cleared by reset, disabling the SRAM module. All other bits are unaffected.

Section 10.5.2, “Memory Base Address Register (RAMBAR).” The RAMBAR contains several control

fields. These fields are shown in Figure 11-1

.

Address: CPU @ 0x0C05 Access: Core write-only

Debug read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

10

0

0

9 8 7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 0

Figure 11-1. SRAM Base Address Register (RAMBAR)

Field

31–

BA

–12

Table 11-2. RAMBAR Field Descriptions

Description

Base address. Defines the 0-modulo-K base address of the SRAM module (0-modulo-16 for the MCF5211).

By programming this field, the SRAM may be located on any -Kbyte boundary within the processor’s byte address space (16-Kbyte boundary for the MCF5211). Bit 14 is reserved on the MCF5212 and MCF5213 devices and should be cleared.


11-2



Preliminary


Table 11-2. RAMBAR Field Descriptions (continued)

Field

11–10

PRIU

PRIL

Description

Priority bit. PRIU determines if or CPU has priority in the upper K bank of memory. PRIL determines if or

CPU has priority in the lower K bank of memory. If a bit is set, the CPU has priority. If a bit is cleared, has priority. Priority is determined according to the following table:

PRIU,PRIL Upper Bank Priority Lower Bank Priority

00

01

10

11

CPU

CPU

CPU

CPU

Note: The recommended setting (maximum performance) for the priority bits is 00.

8

WP

Write protect. Allows only read accesses to the SRAM. When this bit is set, any attempted write access from the core will generate an access error exception to the ColdFire processor core.

0 Allows core read and write accesses to the SRAM module

1 Allows only core read accesses to the SRAM module

Note: Non-core write accesses are not affected by this bit.


7

5–1

C/I, SC, SD, UC,

UD

Address space masks (AS n ). These five bit fields allow certain types of accesses to be “masked,” or inhibited from accessing the SRAM module. The address space mask bits are:

C/I = CPU space/interrupt acknowledge cycle mask

SC = Supervisor code address space mask

SD = Supervisor data address space mask

UC = User code address space mask

UD = User data address space mask

0

V

For each address space bit:

0 An access to the SRAM module can occur for this address space

1 Disable this address space from the SRAM module. If a reference using this address space is made, it is inhibited from accessing the SRAM module, and is processed like any other non-SRAM reference.

These bits are useful for power management as detailed in Section 11.3.2, “Power Management.”

In most applications the C/I bit is set

Valid. When set, this bit enables the SRAM module; otherwise, the module is disabled. A hardware reset clears this bit.

11.3


After a hardware reset, the contents of the SRAM module are undefined. The valid bit of the RAMBAR is cleared, disabling the module. If the SRAM requires initialization with instructions or data, the following steps should be performed:

1. Load the RAMBAR, mapping the SRAM module to the desired location within the address space.

2. Read the source data and write it to the SRAM. There are various instructions to support this function, including memory-to-memory move instructions, or the MOVEM opcode. The MOVEM instruction is optimized to generate line-sized burst fetches on 0-modulo-16 addresses, so this opcode generally provides maximum performance.



Preliminary

11-3


3. After the data has been loaded into the SRAM, it may be appropriate to load a revised value into the RAMBAR with a new set of attributes. These attributes consist of the write-protect and address space mask fields.

The ColdFire processor or an external debugger using the debug module can perform these initialization functions.

11.3.1

SRAM Initialization Code

The following code segment describes how to initialize the SRAM. The code sets the base address of the

SRAM at 0x000_0000 and initializes the SRAM to zeros.

RAMBASE EQU 0x0000000 ;set this variable to 0x0000000 move.l movec.l

#RAMBASE+RAMVALID,D0

D0, RAMBAR

;load RAMBASE + valid bit into D0.

;load RAMBAR and enable SRAM

The following loop initializes the entire SRAM to zero: lea.l move.l

RAMBASE,A0

#,D0

;load pointer to SRAM

;load loop counter into D0 (SRAM size/4)

SRAM_INIT_LOOP: clr.l subq.l bne.b

(A0)+

#1,D0

SRAM_INIT_LOOP

;clear 4 bytes of SRAM

;decrement loop counter

;if done, then exit; else continue looping

11.3.2


If the SRAM is used only for data operands, setting the AS n bits associated with instruction fetches can decrease power dissipation. Additionally, if the SRAM contains only instructions, masking operand accesses can reduce power dissipation.

Table 11-3

shows some examples of typical RAMBAR settings.

Table 11-3. Typical RAMBAR Setting Examples

Data Contained in SRAM

Instruction Only

Data Only

Both Instructions and Data

RAMBAR[7:0]

0x2B

0x35

0x21

11-4



Preliminary

Chapter 12


12.1

Introduction

This chapter describes the various operating configurations of the device. It provides a description of signals used by the CCM and a programming model.

12.1.1

Block Diagram

The chip configuration module (CCM) controls the chip configuration and mode of operation for the

MCF52235.

Clock Mode

Selection

Output Pad

Strength Selection

Chip Configuration Register

Reset Configuration Register

Chip Identification Register

Chip Test Register

Figure 12-1. Chip Configuration Module Block Diagram

12.1.2

Features

The CCM selects the following:

• External clock or phase-lock loop (PLL) mode with internal or external reference

• Output pad drive strength

• Low-power configuration

• Processor status (PSTAT) and processor debug data (DDATA) functions

• BDM or JTAG mode



Preliminary

12-1


12.2

External Signal Descriptions

Table 12-1

provides an overview of the CCM signals.


RCON

Name Function

Reset configuration select

Reset State

Internal weak pull-up device

12.2.1

RCON

If the external RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins (see

Section 12.4, “Functional Description

”). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration.

12.3


This subsection provides a description of the memory map and registers.

12.3.1

Programming Model

The CCM programming model consists of these registers:

• The chip configuration register (CCR) controls the main chip configuration.

• The reset configuration register (RCON) indicates the default chip configuration.

• The chip identification register (CIR) contains a unique part number.

Some control register bits are implemented as write-once bits. These bits are always readable, but once the bit has been written, additional writes have no effect, except during debug and test operations.

Some write-once bits can be read and written while in debug mode. When debug mode is exited, the chip configuration module resumes operation based on the current register values. If a write to a write-once register bit occurs while in debug mode, the register bit remains writable on exit from debug or test mode.

Table 12-2

shows the accessibility of write-once bits.

Table 12-2. Write-Once Bits Read/Write Accessibility

Configuration

All configurations

Debug operation

Read/Write Access

Read-always

Write-always

12-2



Preliminary


12.3.2

Memory Map

Table 12-3. Chip Configuration Module Memory Map

IPSBAR

Offset

1

Register

Width

(bits)



0x11_0004 Chip Configuration Register (CCR)

0x11_0007 Low-Power Control Register (LPCR)

2

0x11_0008 Reset Configuration Register (RCON)

16

8

R

R/W

0x0001

0x00

8.3.3.1/8-3

7.2.4.1/7-12

16 R 0x0000

12.3.3.2/12-4

0x11_000A Chip Identification Register (CIR) 16 R 0x2000

12.3.3.3/12-5

0x11_0010 Unimplemented

3

—

1

2

3


See Chapter 8, “Power Management,” for a description of the LPCR. It is shown here only to warn against accidental writes to this register.

Accessing an unimplemented address has no effect and causes a cycle termination transfer error.

NOTE

To safeguard against unintentionally activating test logic, write 0x0000 to the above reserved location during initialization (immediately after reset) to lock out test features. Setting any bits in the CCR may lead to unpredictable results.

12.3.3


The following section describes the CCM registers.

12.3.3.1

Chip Configuration Register (CCR)

IPSBAR

Offset:

0x11_0004 (CCR)

15

R

W

Reset 0

14

0

0

13

0

0

12

0

11

0

10

0

9

0

8

0

0 0 0 0 0 0 0 0

Figure 12-2. Chip Configuration Register (CCR)

0

Access: Supervisor read-only

7 6 5 4 3

0 SZEN PSTEN 0 BME

0

2

0

1

BMT

0

0

1



Preliminary

12-3


Field

1–

—

6

SZEN

5

PSTEN

TSIZ[1:0] enable. This read/write bit enables the TSIZ[1:0] function of the external pins.

0 TSIZ[1:0] function disabled.

1 TSIZ[1:0] function enabled.

PST[3:0]/DDATA[3:0] enable. This read/write bit enables the Processor Status (PST) and Debug Data (DDATA) functions of the external pins.

0 PST/DDATA function disabled.

1 PST/DDATA function enabled.


4

—

3

BME

2–0

BMT

Table 12-4. CCR Field Descriptions


Description

Bus monitor enable. This read/write bit enables the bus monitor to operate during external bus cycles.

0 Bus monitor disabled for external bus cycles.

1 Bus monitor enabled for external bus cycles.

Table 12-2

shows the read/write accessibility of this write-once bit.

Bus monitor timing. This field selects the timeout period (in system clocks) for the bus monitor.

000 65536

001 32768

010 16384

011 8192

100 4096

101 2048

110 1024

111 512

Table 12-2

shows the read/write accessibility of this write-once bit.

12.3.3.2

Reset Configuration Register (RCON)

At reset, RCON determines the default operation of certain chip functions. All default functions defined by the RCON values can only be overridden during reset configuration (see

Section 12.4.1, “Reset

Configuration ”) if the external RCON pin is asserted. RCON is a read-only register.

Access: Supervisor read-only IPSBAR

Offset:

0x11_0008 (RCON)

15

R

W

Reset 0

14

0

0

13

0

0

12

0

11

0

10

0

9

0

8

0

7

0

6 5 4

0 RLOAD 0

0 0 0 0 0 0 0 0

Figure 12-3. Reset Configuration Register (RCON)

0

3

0

0

2

0

0

1 0

0 MODE

0 0

12-4



Preliminary


Field

15–6

—

5

RLOAD

4–1

—

0

MODE

Table 12-5. RCON Field Descriptions


Description

Pad driver load. Reflects the default pad driver strength configuration.

0 artial drive strength (This is the default value.)

1 ull drive strength


Chip configuration mode. Reflects the default chip configuration mode.

0

1 .

The default mode can be overridden during reset configuration.

12.3.3.3

Chip Identification Register (CIR)

IPSBAR

Offset:

0x11_000A (CIR)

14 13 15

R

W

Reset X X X

12 11

PIN

10 9 8 7 6 5 4

X X X X X X X X

Figure 12-4. Chip Identification Register (CIR)

X

3

PRN

2

X X

Access: read-only

1 0

X X

Field

15–6

PIN

Table 12-6. CIR Field Description

Description

Part identification number. Contains a unique identification number for the device.

MCF52230 = 0x48

MCF52233 = 0x4A

MCF52234 = 0x4B

MCF52235 = 0x4C

Part revision number. This number is increased by one for each new full-layer mask set of this part. The revision numbers are assigned in chronological order, beginning with zero.

5–0

PRN

12.4


Three functions are defined within the chip configuration module:

• Reset configuration

• Output pad strength configuration

• Clock mode selections

These functions are described in the following sections.



Preliminary

12-5


12.4.1

Reset Configuration

During reset, the pins for the reset override functions are immediately configured to known states.

Table 12-7

shows the states of the external pins while in reset.

Table 12-7. Reset Configuration Pin States During Reset

Pin

Pin

Function

1

I/O

Output

State

Input

State

RCON RCON function for all modes

2

Input — Internal weak pull-up device

1

2

If the external RCON pin is not asserted during reset, pin functions are determined by the default operation mode defined in the RCON register. If the external RCON pin is asserted, pin functions are determined by the override values driven on the external data bus pins.

During reset, the external RCON pin assumes its RCON pin function, but this pin changes to the function defined by the chip operation mode immediately after reset. See

Table 12-8

.

If the RCON pin is not asserted during reset, the chip configuration and the reset configuration pin functions after reset are determined by RCON or fixed defaults, regardless of the states of the external data pins. The internal configuration signals are driven to levels specified by the RCON register’s reset state for default module configuration.

If the RCON pin is asserted during reset, then various chip functions, including the reset configuration pin functions after reset, are configured according to the levels driven onto the external data pins (see

Table 12-8

). The internal configuration signals are driven to reflect the levels on the external configuration pins to allow for module configuration.

Table 12-8. Configuration During Reset

1

Pin(s) Affected

Default

Configuration

Override Pins in Reset

2,

Function

All output pins RCON[5] = 1 0

1

Partial strength

Full strength

4

1

2

Modifying the default configurations is possible only if the external RCON pin is asserted.

The external reset override circuitry drives the data bus pins with the override values while RSTOUT is asserted. It must stop driving the data bus pins within one CLKOUT cycle after RSTOUT is negated. To prevent contention with the external reset override circuitry, the reset override pins are forced to inputs during reset and do not become outputs until at least one CLKOUT cycle after RSTOUT is negated. RCON must also be negated within one cycle after

RSTOUT is negated.

12.4.2

Output Pad Strength Configuration

Output pad strength is determined during reset configuration.

12.5

Reset

Reset initializes CCM registers to a known startup state as described in

Section 12.3, “Memory

Map/Register Definition.”

The CCM controls chip configuration at reset as described in Section 12.4,

“Functional Description.”

12-6



Preliminary

Chapter 13


13.1

Introduction

This section details the functionality of the system control module (SCM) that provides the programming model for the system access control unit (SACU), system bus arbiter, 32-bit core watchdog timer (CWT), and system control registers and logic. Specifically, the system control includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port RAM base address register

(RAMBAR), and system control registers that include the core watchdog timer control.

13.2

Overview

The SCM provides the control and status for a variety of functions including base addressing and address space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core memory spaces

(RAMBAR). The CPU core supports two memory banks, one for the internal SRAM and the other for the internal Flash.

The SACU provides the mechanism needed to implement secure bus transactions to the system address space.

The programming model for the system bus arbitration resides in the SCM. The SCM sources the necessary control signals to the arbiter for bus master management.

The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special software service sequence. If periodic software servicing action does not occur, the CWT times out with a programmed response (system reset or interrupt) to allow recovery or corrective action to be taken.

13.3

Features

The SCM includes these distinctive features:

• IPS base address register (IPSBAR)

— Base address location for 1-Gbyte peripheral space

— User control bits

• Processor-local memory base address register (RAMBAR)

• System control registers

— Core reset status register (CRSR) indicates type of last reset

— Core watchdog service register (CWSR) services watchdog timer

— Core watchdog control register (CWCR) for watchdog timer control

• System bus master arbitration programming model (MPARK)



Preliminary

13-1


• System access control unit (SACU) programming model

— Master privilege register (MPR)

— Peripheral access control registers (PACRs)

— Grouped peripheral access control registers (GPACR0, GPACR1)

13.4

Memory Map and Register Definition

The memory map for the SCM registers is shown in

Table 13-1 . All the registers in the SCM are

memory-mapped as offsets within the 1-Gbyte IPS address space and accesses are controlled to these registers by the control definitions programmed into the SACU.

Table 13-1. SCM Register Map

IPSBAR

Offset

1

Register

Width

(bits)


0x00_0000 IPS Base Address Register (IPSBAR)

0x00_0008 Memory Base Address Register (RAMBAR)


2

0x00_0010 Core Reset Status Register (CRSR)

0x00_0011 Core Watchdog Control Register (CWCR)

0x00_0012 Low-Power Interrupt Control Register (LPICR)

0x00_0013 Core Watchdog Service Register (CWSR)

0x00_0014 DMA Request Control Register (DMAREQC)


2

0x00_001C Default Bus Master Park Register (MPARK)

0x00_0020 Master Privilege Register (MPR)

0x00_0021 Peripheral Power Management Set Register (PPMRS)

2

0x00_0022 Peripheral Power Management Clear Register (PPMRC)

2

0x00_0023 IPS Bus Timeout Monitor Register (IPSBMT)

2,3

0x00_0024 Peripheral Access Control Register (PACR0)





0x00_002A Peripheral Access Control Register (PACR5)

0x00_002B Peripheral Access Control Register (PACR6)

0x00_002C Peripheral Access Control Register (PACR7)

32

32

8

8

32

32

8

8

8

32

8

8

32

32

32

8

8

8

8

8

8

8

R/W

R/W

R/W

R/W

R/W

R/W

R/W 0x40000001

13.5.1/13-3

R/W 0x00000000

13.5.2/13-4

R/W 0x00000000

R/W

7.2.1/7-2

13.5.3/13-7

R/W

R/W

0x00

0x00

13.5.4/13-8

7.2.2/7-9

R/W

13.5.5/13-10

R/W 0x00000000 14.4.1/14-5

R/W 0x00000001 7.2.1.1/7-5

R/W 0x30E10000

13.6.3/13-12

R/W

W

0x03

0x00

13.7.3.1/13-16

7.2.3/7-11

R/W 0x00

R/W 0x00000008

R/W

R/W

0x00

0x00

7.2.4/7-11

7.3/7-13

13.7.3.2/13-17

13.7.3.2/13-17

0x00

0x00

0x00

0x00

0x00

0x00

13.7.3.2/13-17

13.7.3.2/13-17

13.7.3.2/13-17

13.7.3.2/13-17

13.7.3.2/13-17

13.7.3.2/13-17

13-2



Preliminary


Table 13-1. SCM Register Map (continued)

IPSBAR

Offset

1

Register

Width

(bits)


0x00_002E Peripheral Access Control Register (PACR8)

0x00_0030 GPACR0 Register

8

8

R/W

R/W

0x00

0x00

13.7.3.2/13-17

13.7.3.3/13-18

0x00_0031 GPACR1 Register 8 R/W 0x00

13.7.3.3/13-18

2

3

1


The PPMRH, LPICR, PMRL, PPMRS, PPMRC, and IPSBMT are described in Chapter 7, “Power Management.”

Register must be addressed as a byte.

Table 13-2.

IPSBAR

Offset

[31:24] [23:16] [15:8] [7:0]

0x00_0000

0x00_0004

IPSBAR

—

0x00_0008

0x00_000C

0x00_0010

0x00_0014

CRSR

RAMBAR

PPMRH

1

CWCR LPICR

1

DMAREQC

2

PPMRL

1

CWSR

0x00_0018

0x00_001C MPARK

2

3

0x00_0020

0x00_0024

0x00_0028

0x00_002c

0x00_0030

0x00_0034

1

0x00_0038

0x00_003C

MPR

PACR0

PACR4

PACR8

GPACR0

—

—

—

PPMRS

PACR1

PACR5

—

GPACR1

—

—

—

1

PPMRC

PACR2

PACR6

—

—

—

—

—

1

IPSBMT

PACR3

PACR7

—

—

—

—

—

The LPICR is described in Chapter 7, “Power Management.”

The DMAREQC register is described in Chapter 14, “DMA Controller Module .”

Register must be addressed as a byte.

1,3

13.5


13.5.1

Internal Peripheral System Base Address Register (IPSBAR)

The IPSBAR specifies the base address for the 1-Gbyte memory space associated with the on-chip peripherals. At reset, the base address is loaded with a default location of 0x4000_0000 and marked as valid (IPSBAR[V]=1). If desired, the address space associated with the internal modules can be moved by loading a different value into the IPSBAR at a later time.



Preliminary

13-3


NOTE

Accessing reserved IPSBAR memory space could result in an unterminated bus cycle that causes the core to hang. Only a hard reset will allow the core to recover from this state. Therefore, all bus accesses to IPSBAR space should fall within a module’s memory map space.

If an address hits in overlapping memory regions, the following priority is used to determine what memory is accessed:

1. IPSBAR

2. RAMBAR

NOTE

This is the list of memory access priorities when viewed from the processor core.

See Figure 13-1 and Table 13-3

for descriptions of the bits in IPSBAR.

IPSBAR

Offset:

0x000 (IPSBAR)

31 30

R

BA31 BA30

W

Reset 0 1

29

0

0

28

0

0

27

0

0

26

0

0

25

0

0

24

0

0

23

0

0

22

0

0

21

0

0

20

0

0

19

0

0

Access: read/write

18

0

0

17

0

0

16

0

0

15

R 0

W

Reset 0

14

0

0

13

0

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3

0

0

2

0

0

1

0

0

0

V

1 0 0 0 0 0 0 0 0

Figure 13-1. IPS Base Address Register (IPSBAR)

0

Table 13-3. IPSBAR Field Description


31–30

BA

Base address. Defines the base address of the 1-Gbyte internal peripheral space. This is the starting address for the

IPS registers when the valid bit is set.

29–1 Reserved, should be cleared.

0

V

Valid. Enables/disables the IPS Base address region. V is set at reset.

0 IPS Base address is not valid.

1 IPS Base address is valid.

13.5.2

Memory Base Address Register (RAMBAR)

The device supports dual-ported local SRAM memory. This processor-local memory can be accessed directly by the core and/or other system bus masters. Since this memory provides single-cycle accesses at processor speed, it is ideal for applications where double-buffer schemes can be used to maximize

13-4



Preliminary

System Control Module (SCM) system-level performance. For example, a DMA channel in a typical double-buffer application (also known as a ping-pong scheme) may load data into one portion of the dual-ported SRAM while the processor is manipulating data in another portion of the SRAM. Once the processor completes the data calculations, it begins processing the just-loaded buffer while the DMA moves out the just-calculated data from the other buffer, and reloads the next data block into the just-freed memory region. The process repeats with the processor and the DMA ping-ponging between alternate regions of the dual-ported

SRAM.

The device design implements the dual-ported SRAM in the memory space defined by the RAMBAR register. There are two physical copies of the RAMBAR register: one located in the processor core and accessible only via the privileged MOVEC instruction at CPU space address 0xC05 and another located in the SCM at IPSBAR + 0x008. ColdFire core accesses to this memory are controlled by the processor-local copy of the RAMBAR, while module accesses are enabled by the SCM's RAMBAR.

The physical base address programmed in both copies of the RAMBAR is typically the same value; however, they can be programmed to different values. By definition, the base address must be a

0-modulo-size value.

IPSBAR

Offset:

0x008 (RAMBAR) Access: read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

R

BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

15

R 0

W

Reset 0

14

0

0

13

0

12

0

11

0

10

0

9

BDE

8

0

7

0

6

0

5

0

4

0

0 0 0 0 0 0 0 0 0 0

Figure 13-2. Memory Base Address Register (RAMBAR)

3

0

0

2

0

0

1

0

0

0

0

0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19 BA18 BA17 BA16

Reset

R/W

0000_0000_0000_0000

R/W

15 0

Field

Reset

R/W

Address

—

10 9

BDE

8

0000_0000_0000_0000

R/W

IPSBAR + 0x008

Figure 13-3.

—



Preliminary

13-5


Table 13-4. RAMBAR Field Description


31–16

BA

Base address. Defines the memory module's base address on a 64-Kbyte boundary corresponding to the physical array location within the 4 Gbyte address space supported by ColdFire.


9

BDE

Back door enable. Qualifies the module accesses to the memory.

0 Disables module accesses to the module.

1 Enables module accesses to the module.

NOTE: The SPV bit in the CPU’s RAMBAR must also be set to allow dual port access to the SRAM. For more

information, see Section 11.2.1, “SRAM Base Address Register (RAMBAR)

.”


13-6



Preliminary


The SRAM modules are configured through the RAMBAR shown in

Figure 13-2

.

• RAMBAR specifies the base address of the SRAM.

• All undefined bits are reserved. These bits are ignored during writes to the RAMBAR and return zeros when read.

• The back door enable bit, RAMBAR[BDE], is cleared at reset, disabling the module access to the

SRAM.

NOTE

The RAMBAR default value of 0x0000_0000 is invalid. The RAMBAR located in the processor’s CPU space must be initialized with the valid bit set before the CPU (or modules) can access the on-chip SRAM (see

Chapter 11, “Static RAM (SRAM),”

for more information.

For details on the processor's view of the local SRAM memories, see Section 11.2.1, “SRAM Base

Address Register (RAMBAR).”

13.5.3

Core Reset Status Register (CRSR)

The CRSR contains a bit that indicates the reset source to the CPU. When the EXT bit (bit 7) reads as 1, an external device driving RSTI has caused the most recent reset. The CRSR is updated by the control logic when the reset is complete. Only one bit is set at any one time in the CRSR. The register reflects the cause of the most recent reset. To clear a bit, a logic 1 must be written to the bit location; writing a zero has no effect. Unused bits are reserved and should not be written.

NOTE

The reset status register (RSR) in the reset controller module provides indication of all reset sources except the core watchdog timer (see

Chapter 9, “Reset Controller Module” ).

IPSBAR

Offset:

0x010 (CRSR) Access: read/write

R

W

7

EXT

6

0

5

0

4

0

3

0

2

0

1

0

Reset: See Note 0 0 0 0 0 0

Note: The reset value of EXT depend on the last reset source. All other bits are initialized to zero.

Figure 13-4. Core Reset Status Register (CRSR)

0

0

0



Preliminary

13-7


Table 13-5. CRSR Field Descriptions


7

EXT

External reset.

1 An external device driving RSTI caused the last reset. Assertion of reset by an external device causes the processor core to initiate reset exception processing. All registers are forced to their initial state.

6–0 Reserved, should read as 0. Do not write to these locations.

13.5.4

Core Watchdog Control Register (CWCR)

The core watchdog timer prevents system lockup if the software becomes trapped in a loop with no controlled exit. The core watchdog timer can be enabled or disabled through CWCR[CWE]. It is disabled by default. If enabled, the watchdog timer requires the periodic execution of a core watchdog servicing sequence. If this periodic servicing action does not occur, the timer times out, resulting in a watchdog timer interrupt or a hardware reset, as programmed, by CWCR[CWRI]. If the timer times out and the core watchdog transfer acknowledge enable bit (CWCR[CWTA]) is set, a watchdog timer interrupt is asserted.

If a core watchdog timer interrupt acknowledge cycle has not occurred after another timeout, CWT TA is asserted in an attempt to allow the interrupt acknowledge cycle to proceed by terminating the bus cycle.

The setting of CWCR[CWTAVAL] indicates that the watchdog timer TA was asserted.

When the core watchdog timer times out and CWCR[CWRI] is programmed for a software reset, an internal reset is asserted and CRSR[CWDR] is set. To prevent the core watchdog timer from interrupting or resetting, the CWSR must be serviced by performing the following sequence:

1. Write 0x55 to CWSR.

2. Write 0xAA to the CWSR.

Both writes must occur in order before the time-out, but any number of instructions can be executed between the two writes. This order allows interrupts and exceptions to occur, if necessary, between the two writes. Caution should be exercised when changing CWCR values after the software watchdog timer has been enabled with the setting of CWCR[CWE], because it is difficult to determine the state of the core watchdog timer while it is running. The countdown value is constantly compared with the time-out period specified by CWCR[CWT]. The following steps must be taken to change CWT:

1. Disable the core watchdog timer by clearing CWCR[CWE].

2. Reset the counter by writing 0x55 and then 0xAA to CWSR.

3. Update CWCR[CWT].

4. Re-enable the core watchdog timer by setting CWCR[CWE]. This step can be performed in step 3.

The CWCR controls the software watchdog timer, time-out periods, and software watchdog timer transfer acknowledge. The register can be read at any time, but can be written only if the CWT is not pending. At system reset, the software watchdog timer is disabled.

13-8



Preliminary


IPSBAR

Offset:

0x011 (CWCR)

7

R

W

Reset:

CWE

0

6

CWRI

5 4

CWT[2:0]

3 2

CWTA

0 0 0 0 0

Figure 13-5. Core Watchdog Control Register (CWCR)

1

CWTAVAL

0

Access: read/write

0

CWTIC

0

Table 13-6. CWCR Field Description

Field

CWT [2:0]

100

101

110

111

000

001

010

011

Description

7

CWE

6

CWRI

Core watchdog enable.

0 SWT disabled.

1 SWT enabled.

Core watchdog interrupt select.

0 If a time-out occurs, the CWT generates an interrupt to the processor core. The interrupt level for the CWT is programmed in the interrupt control register 7 (ICR7) of INTC0.

1 Reserved. If a one is written undetermined behavior will result.

Note: If a core reset is required, the watchdog interrupt should set the soft reset bit in the interrupt controller.

5–3

CWT[2:0]

Core watchdog timing delay. These bits select the timeout period for the CWT as shown in the following table. At system reset, the CWT field is cleared signaling the minimum time-out period but the watchdog is disabled

(CWCR[CWE] = 0). the following table shows the core watchdog timer delay.

C WT Time-Out Period

2

9

Bus clock frequency

2

11

Bus clock frequency

2

13

Bus clock frequency

2

15

Bus clock frequency

2

19

Bus clock frequency

2

23

Bus clock frequency

2

27

Bus clock frequency

2

31

Bus clock frequency

2

CWTA

Core watchdog transfer acknowledge enable.

0 CWTA Transfer acknowledge disabled.

1 CWTA Transfer Acknowledge enabled. After one CWT time-out period of the unacknowledged assertion of the

CWT interrupt, the transfer acknowledge asserts, which allows CWT to terminate a bus cycle and allow the interrupt acknowledge to occur.



Preliminary

13-9


Table 13-6. CWCR Field Description (continued)

1

CWTAVA

L

Core watchdog transfer acknowledge valid.

0 CWTA Transfer Acknowledge has not occurred.

1 CWTA Transfer Acknowledge has occurred. Write a 1 to clear this flag bit.

0

CWTIF

Core watchdog timer interrupt flag.

0 CWT interrupt has not occurred

1 CWT interrupt has occurred. Write a 1 to clear the interrupt request.

13.5.5

Core Watchdog Service Register (CWSR)

The software watchdog service sequence must be performed using the CWSR as a data register to prevent a CWT time-out. The service sequence requires two writes to this data register: first a write of 0x55 followed by a write of 0xAA. Both writes must be performed in this order prior to the CWT time-out, but any number of instructions or accesses to the CWSR can be executed between the two writes. If the CWT

has already timed out, writing to this register has no effect in negating the CWT interrupt. Figure 13-6

illustrates the CWSR. At system reset, the contents of CWSR are uninitialized.


Offset:

0x013 (CWSR)

7

R

W

Reset: Uninitialized

6 5 4

CWSR[7:0]

3 2

Figure 13-6. Core Watchdog Service Register (CWSR)

1 0

13-10



Preliminary


13.6

Internal Bus Arbitration

The internal bus arbitration is performed by the on-chip bus arbiter, which containing the arbitration logic that controls which of up to four MBus masters (M0–M3 in

Figure 13-7

) has access to the external buses.

The function of the arbitration logic is described in this section.

Figure 13-7. Arbiter Module Functions

“back door” to SRAM and Flash

SRAM1

MPARK RAMBAR

CPU

M0

DMA

M2

Internal

Bus

Master

M1

MARB

Internal

Modules

13.6.1

Overview

The basic functionality is that of a 2-port, pipelined internal bus arbitration module with the following attributes:

• The master pointed to by the current arbitration pointer may get on the bus with zero latency if the address phase is available. All other requesters face at least a one cycle arbitration pipeline delay in order to meet bus timing constraints on address phase hold.

• If a requester will get an immediate address phase (that is, it is pointed to by the current arbitration pointer and the bus address phase is available), it will be the current bus master and is ignored by arbitration. All remaining requesting ports are evaluated by the arbitration algorithm to determine the next-state arbitration pointer.

• There are two arbitration algorithms: fixed and round-robin. Fixed arbitration sets the next-state arbitration pointer to the highest priority requester. Round-robin arbitration sets the next-state arbitration pointer to the highest priority requester (calculated by adding a requester's fixed priority to the current bus master’s fixed priority and then taking this sum modulo the number of possible bus masters).

• The default priority is DMA (M2) > internal master (M1) > CPU (M0), where M2 is the highest and M0 the lowest priority.

• There are two actions for an idle arbitration cycle, either leave the current arbitration pointer as is or set it to the lowest priority requester.



Preliminary

13-11


• The anti-lock-out logic for the fixed priority scheme forces the arbitration algorithm to round-robin if any requester has been held for longer than a specified cycle count.

13.6.2

Arbitration Algorithms

There are two modes of arbitration: fixed and round-robin. This section discusses the differences between them.

13.6.2.1

Round-Robin Mode

Round-robin arbitration is the default mode after reset. This scheme cycles through the sequence of masters as specified by MPARK[M n _PRTY] bits. Upon completion of a transfer, the master is given the lowest priority and the priority for all other masters is increased by one.

M2 =01 M1 = 10 M0 = 00 next +1 M2 =10 M1 = 11 M0 = 01 next +2 M2 =11 M1 = 00 M0 = 10 next +3 M2 =00 M1 = 01 M0 = 11

If no masters are requesting, the arbitration unit must park, pointing at one of the masters. There are two possibilities: park the arbitration unit on the last active master, or park pointing to the highest priority master. Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked on the highest priority master. In round-robin mode, programming the timeout enable and lockout bits MPARK[13,11:8] will have no effect on the arbitration.

13.6.2.2

Fixed Mode

In fixed arbitration, the master with highest priority (as specified by the MPARK[M n _PRTY] bits) will win the bus. That master will relinquish the bus when all transfers to that master are complete.

If MPARK[TIMEOUT] is set, a counter will increment for each master for every cycle it is denied access.

When a counter reaches the limit set by MPARK[LCKOUT_TIME], the arbitration algorithm will be changed to round-robin arbitration mode until all locks are cleared. The arbitration will then return to fixed mode and the highest priority master will be granted the bus.

As in round-robin mode, if no masters are requesting, the arbitration pointer will park on the highest priority master if MPARK[PRK_LAST] is set, or will park on the master whose last requested the bus if cleared.

13.6.3

Bus Master Park Register (MPARK)

The MPARK controls the operation of the system bus arbitration module. The platform bus master connections are defined as the following:

• Master 2 (M2): 4-channel DMA

• Master 1 (M1): Internal Bus Master (not used in normal user operation)

• Master 0 (M0): V2 ColdFire Core

13-12



Preliminary


IPSBAR

Offset:

0x01C (MPARK)

31

R 0

W

Reset 0

30

0

0

29

0

1

28

0

1

27

0

0

26

0

0

25 24

M2_P

_EN

BCR2

4BIT

0 0

23

0

1

22

0

1

Access: read/write

21 20

M2_PRTY

1 0

19 18

M0_PRTY

0 0

3

0

2

0

15

R 0

W

Reset 0

14

FIXED

13

TIME

OUT

12

PRKL

AST

0 0 0

11 10 9

LCKOUT_TIME

8 7

0

6

0

5

0

4

0

0 0 0 0 0 0 0 0

Figure 13-8. Default Bus Master Park Register (MPARK)

0 0

17 16

M1_PRTY

0 1

1

0

0

0

0 0

Field

31–26

25

M2_P_EN

24

BCR24BIT

23–22

21–20

M2_PRTY

19–18

M0_PRTY

17–16

15

14

FIXED

Table 13-7. MPARK Field Description

Description


DMA bandwidth control enable

0 disable the use of the DMA's bandwidth control to elevate the priority of its bus requests.

1 enable the use of the DMA's bandwidth control to elevate the priority of its bus requests.

Enables the use of 24 bit byte count registers in the DMA module

0 DMA BCRs function as 16 bit counters.

1 DMA BCRs function as 24 bit counters.


Master priority level for master 2 (DMA Controller)

00 fourth (lowest) priority

01 third priority

10 second priority

11 first (highest) priority

Master priority level for master 0 (ColdFire Core)


01 third priority

10 second priority

11 first (highest) priority

Master priority level for master 1 (Not used in user mode)


01 third priority

10 second priority

11 first (highest) priorityReserved, should be cleared.


Fixed or round robin arbitration

0 round robin arbitration

1 fixed arbitration



Preliminary

13-13


Table 13-7. MPARK Field Description (continued)


13

TIMEOUT

12

PRKLAST

Timeout Enable

0 disable count for when a master is locked out by other masters.

1 enable count for when a master is locked out by other masters and allow access when LCKOUT_TIME is reached.

Park on the last active master or highest priority master if no masters are active

0 park on last active master

1 park on highest priority master

11–8

LCKOUT_TIME

Lock-out Time. Lock-out time for a master being denied the bus.

The lock out time is defined as 2^ LCKOUT_TIME[3:0].


The initial state of the master priorities is M3 > M2 > M1 > M0. System software should guarantee that the programmed M n _PRTY fields are unique, otherwise the hardware defaults to the initial-state priorities.

NOTE

The M1_PRTY field should not be set for a priority higher than third

(default).

13.7

System Access Control Unit (SACU)

This section details the functionality of the system access control unit (SACU), which provides the mechanism needed to implement secure bus transactions to the address space mapped to the internal modules.

13.7.1

Overview

The SACU supports the traditional model of two privilege levels: supervisor and user. Typically, memory references with the supervisor attribute have total accessibility to all the resources in the system, while user mode references cannot access system control and configuration registers. In many systems, the operating system executes in supervisor mode, while application software executes in user mode.

The SACU further partitions the access control functions into two parts: one control register defines the privilege level associated with each bus master, and another set of control registers define the access levels associated with the peripheral modules and memory space.

The SACU’s programming model is physically implemented as part of the system control module (SCM) with the actual access control logic included as part of the arbitration controller. Each bus transaction targeted for the IPS space is first checked to see if its privilege rights allow access to the given memory space. If the privilege rights are correct, the access proceeds on the bus. If the privilege rights are insufficient for the targeted memory space, the transfer is immediately aborted and terminated with an exception, and the targeted module is not accessed.

13-14



Preliminary


13.7.2

Features

Each bus transfer can be classified by its privilege level and the reference type. The complete set of access types includes the following:

• Supervisor instruction fetch

• Supervisor operand read

• Supervisor operand write

• User instruction fetch

• User operand read

• User operand write

Instruction fetch accesses are associated with the execute attribute.

It should be noted that while the bus does not implement the concept of reference type (code versus data) and only supports the user/supervisor privilege level, the reference type attribute is supported by the system bus. Accordingly, the access checking associated with both privilege level and reference type is performed in the IPS controller using the attributes associated with the reference from the system bus.

The SACU partitions the access control mechanisms into three distinct functions:

• Master privilege register (MPR)

— Allows each bus master to be assigned a privilege level:

– Disable the master’s user/supervisor attribute and force to user mode access

– Enable the master’s user/supervisor attribute

— The reset state provides supervisor privilege to the processor core (bus master 0).

— Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at reset. This is intended to support the concept of a trusted bus master, and also controls the ability of a bus master to modify the register state of any of the SACU control registers; that is, only trusted masters can modify the control registers.

• Peripheral access control registers (PACRs)

— Provide read/write access rights, supervisor/user privilege levels.

— Reset state provides supervisor-only read/write access to these modules.

— Nine 8-bit registers control access to 17 of the on-chip peripheral modules

• Grouped peripheral access control registers (GPACR0, GPACR1)

— Provide read/write/execute access rights, supervisor/user privilege levels.

— One single register (GPACR0) controls access to 14 of the on-chip peripheral modules.

— One register (GPACR1) controls access for IPS reads and writes to the Flash module.

— Reset state provides supervisor-only read/write access to each of these peripheral spaces.

13.7.3


The memory map for the SACU program-visible registers within the system control module (SCM) is shown in

Figure 13-8

. The MPR, PACR, and GPACRs are 8 bits wide.



Preliminary

13-15


IPSBAR

Offset

0x020

0x024

0x028

0x02c

0x030

0x034

0x038

0x03C

[31:28] [27:24]

MPR

PACR0

PACR4

PACR8

GPACR0

—

—

—

Table 13-8. SACU Register Memory Map

[23:20] [19:16]

PPMRS

PACR1

PACR5

—

GPACR1

—

—

—

[15:12]

PPMRC

PACR2

PACR6

—

—

—

—

—

[11:8] [7:4]

IPSBMT

PACR3

PACR7

—

—

—

—

—

[3:0]

13.7.3.1

Master Privilege Register (MPR)

The MPR specifies the access privilege level associated with each bus master in the platform. The register provides one bit per bus master, where bit 3 corresponds to master 3 (fast Ethernet controller), bit 2 to master 2 (DMA Controller), bit 1 to master 1 (internal bus master), and bit 0 to master 0 (ColdFire core).


Offset:

0x020 (MPR)

7

0 R

W

Reset: 0

6

0

5

0

4

0

3 2

MPR[3:0]

1

1

0

1 0 0 0 0

Figure 13-9. Master Privilege Register (MPR)

0

Table 13-9. MPR[n] Field Descriptions


7–4 Reserved. Should be cleared.

3–0

MPR

Each 1-bit field defines the access privilege level of the given bus master

0 All bus master accesses are in user mode.

1 All bus master accesses use the sourced user/supervisor attribute.

n .

Only trusted bus masters can modify the access control registers. If a non-trusted bus master attempts to write any of the SACU control registers, the access is aborted with an error termination and the registers remain unaffected.

The processor core is connected to bus master 0 and is always treated as a trusted bus master. Accordingly,

MPR[0] is forced to 1 at reset.

13-16



Preliminary


13.7.3.2

Peripheral Access Control Registers (PACR0–PACR8)

Access to several on-chip peripherals is controlled by shared peripheral access control registers. A single

PACR defines the access level for each of the two modules. These modules only support operand reads

and writes. Each PACR follows the format illustrated in Figure 13-10 . For a list of PACRs and the modules

that they control, refer to

Table 13-12

.

IPSBAR

Offset:

0x24 + Offset (PACR n )

7 6

R

W

Reset:

LOCK1

0

5

ACCESS_CTRL1

4 3

LOCK0

2

ACCESS_CTRL0

0 0 0 0 0

Figure 13-10. Peripheral Access Control Register (PACR n )

1

0

Access: read/write

0

0

Table 13-10. PACR Field Descriptions


7

LOCK1

6–4

ACCESS_CTRL1

This 3-bit field defines the access control for the given platform peripheral.

The encodings for this field are shown in

Table 13-11 .

3

LOCK0

This bit, when set, prevents subsequent writes to ACCESSCTRL1. Any attempted write to the PACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag.

This bit, when set, prevents subsequent writes to ACCESSCTRL0. Any attempted write to the PACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag.

2–0

ACCESS_CTRL0

This 3-bit field defines the access control for the given platform peripheral.

The encodings for this field are shown in

Table 13-11 .

Table 13-11. PACR ACCESSCTRL Bit Encodings

Bits

100

101

110

111

000

001

010

011

Supervisor Mode

Read/Write

Read

Read

Read

Read/Write

Read/Write

Read/Write

No Access

User Mode

No Access

No Access

Read

No Access

Read/Write

Read

Read/Write

No Access



Preliminary

13-17


Table 13-12. Peripheral Access Control Registers (PACRs)

Modules Controlled

IPSBAR Offset Name

0x024

0x025

0x026

0x027

0x028

0x029

0x02a

0x02b

0x02c

0x02d

0x02e

PACR0

PACR1

PACR2

PACR3

PACR4

—

PACR6

PACR7

PACR8

—

—

ACCESS_CTRL1

SCM

—

UART0

UART2

I

2

C

—

DTIM0

DTIM2

INTC0

—

—

ACCESS_CTRL0

—

DMA

UART1

—

QSPI

—

DTIM1

DTIM3

—

—

—

At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. If an instruction fetch access to any of these peripheral modules is attempted, the IPS bus cycle is immediately terminated with an error.

13.7.3.3

Grouped Peripheral Access Control Registers (GPACR0 & GPACR1)

The on-chip peripheral space starting at IPSBAR is subdivided into 16 64-Mbyte regions. Each of the first two regions has a unique access control register associated with it. The other 14 regions are in reserved space; the access control registers for these regions are not implemented. Bits [29:26] of the address select the specific GPACRn to be used for a given reference within the IPS address space. These access control registers are 8 bits wide so that read, write, and execute attributes may be assigned to the given IPS region.

NOTE

The access control for modules with memory space protected by

PACR0–PACR8 are determined by the PACR0–PACR8 settings. The access control is not affected by GPACR0, even though the modules are mapped in its 64-Mbyte address space.


Offset:

0x030, IPSBAR + 0x31 (GPACR)

7 6

0 R

W

Reset:

LOCK

0 0

5

0

4

0

3

0 0 0

Figure 13-11. GPACR Register

2 1

ACCESS_CTRL

0 0

0

0

13-18



Preliminary


Table 13-13. Grouped Peripheral Access Control Register (GPACR) Field Descriptions


7

LOCK

6–4

This bit, once set, prevents subsequent writes to the GPACR. Any attempted write to the GPACR generates an error termination and the contents of the register are not affected. Only a system reset clears this flag.


3–0

ACCESS_CTRL

This 4-bit field defines the access control for the given memory region.

The encodings for this field are shown in Table 13-14

.

At reset, these on-chip modules are configured to have only supervisor read/write access capabilities. Bit

encodings for the ACCESS_CTRL field in the GPACR are shown in Table 13-14 .

Table 13-15

shows the memory space protected by the GPACRs and the modules mapped to these spaces.

Table 13-14. GPACR ACCESS_CTRL Bit Encodings

Bits

1000

1001

1010

1011

1100

1101

1110

1111

0000

0001

0010

0011

0100

0101

0110

0111

Supervisor Mode

Read / Write

Read

Read

Read

Read / Write

Read / Write

Read / Write

No Access

Read / Write / Execute

Read / Execute

Read / Execute

Execute



Read / Write


User Mode

No Access

No Access

Read

No Access

Read / Write

Read

Read / Write

No Access

No Access

No Access

Read / Execute

No Access


Read / Execute

Read

Execute



Preliminary

13-19


Register

GPACR0

GPACR1

Table 13-15. GPACR Address Space

Space Protected

(IPSBAR Offset)

0x0000_0000–

0x03FF_FFFF

Modules Protected

0x0400_0000–

0x07FF_FFFF

Ports, CCM, PMM, Reset controller, Clock,

EPORT, WDOG, PIT0–PIT3, QADC, GPTA,

GPTB, FlexCAN, CFM (Control)

CFM (Flash module’s backdoor access for programming or access by a bus master other than the core)

13-20



Preliminary

Chapter 14


14.1

Introduction

Many of the pins associated with the external interface may be used for several different functions. When not used for their primary function, many of the pins may be used as general-purpose digital I/O pins. In some cases, the pin function is set by the operating mode, and the alternate pin functions are not supported.

The digital I/O pins are grouped into 8-bit ports. Some ports do not use all 8 bits. Each port has registers that configure, monitor, and control the port pins.

Figure 14-1

is a block diagram of the MCF52235 ports.



Preliminary

14-1


PORT DD

PORT AS

PORT QS

PORT TA

DDATA[3:0] / PDD[7:4]

PST[3:0] / PDD[3:0]

CANTX / PAS[3] / SYNCB

CANRX / PAS[2] / SYNCA

SDA / PAS[1] / CANRX / RXD2

SCL / PAS[0] / CANTX / TXD2

QSPI_PCS3 / PQS[6] / SYNCA / SYNCB

QSPI_PCS2 / PQS[5]

QSPI_PCS1 / PQS[4]

QSPI_PCS0 / PQS[3] / SDA / CTS1

QSPI_SCK / PQS[2] / SCL / RTS1

QSPI_DIN / PQS[1] / CANRX / RXD1

QSPI_DOUT / PQS[0] / CANTX TXD1

GPT[3] / PTA[3] / PWM7




PORT TD

PORT TC

PWM7 / PTD[3]

PWM5 / PTD[2]

PWM3 / PTD[1]

PWM1 / PTD[0]

DTIN3 / PTC[3] / DTOUT3 / PWM6




PORT UC

PORT UB

PORT UA

PORT AN

PORT NQ

PORT LD

PORT GP

CTS2 / PUC[3]

RTS2 / PUC[2]

RXD2 / PUC[1]

TXD2 / PUC[0]

CTS1 / PUB[3] / SYNCA / RXD2

RTS1 / PUB[2] / SYNCB / TXD2

RXD1 / PUB[1]

TXD1 / PUB[0]

Figure 14-1. General Purpose I/O Module Block Diagram

14.2

Overview

The MCF52235 ports module controls the configuration for the following external pins:

• External bus accesses

• Chip selects

• Debug data

• Processor status

• FlexCAN transmit/receive data

• I

2

C serial control

• QSPI

• UART transmit/receive

• 32-bit DMA timers

CTS0 / PUA[3] / CANRX

RTS0 / PUA[2] / CANTX

RXD0 / PUA[1]

TXD0 / PUA[0]

AN0 / PAN[0]

AN1 / PAN[1]

AN2 / PAN[2]

AN3 / PAN[3]

AN4 / PAN[4]

AN5 / PAN[5]

AN6 / PAN[6]

AN7 / PAN[7]

IRQ1 / PNQ[1] / SYNCA / PWM1

IRQ2 / PNQ[2]

IRQ3 / PNQ[3]

IRQ4 / PNQ[4]

IRQ5 / PNQ[5]

IRQ6 / PNQ[6]

IRQ7 / PNQ[7]

ACTLED / PLD[0]

LNKLED / PLD[1]

SPDLED / PLD[2]

DUPLED / PLD[3]

COLLED / PLD[4]

RXLED / PLD[5]

TXLED / PLD[6]

IRQ8 / PGP[0]

IRQ9 / PGP[1]

IRQ10 / PGP[2]

IRQ11 / PGP[3]

IRQ12 / PGP[4]

IRQ13 / PGP[5]

14-2



Preliminary


14.3

Features

The MCF52235 ports includes these distinctive features:

• Control of primary function use on all ports

• Digital I/O support for all ports; registers for:

— Storing output pin data

— Controlling pin data direction

— Reading current pin state

— Setting and clearing output pin data registers

14.4


Refer to Chapter 2, “Signal Descriptions ,” for more detailed information on the different signals and pins.



Preliminary

14-3


14.5


14.5.1

Ports Memory Map

14-4



Preliminary


Table 14-1. Ports Module Memory Map

Offset 1 31–24 23–16 15–8 7–0 Access 2

Port Output Data Registers

$0000

$0004

$0008

$000C

$0010

$0014

PORTNQ

PORTQS

PORTTD

PORTDD

Port Data Direction Registers

$0018

$001C

$0020

$0024

$0028

$002C

DDRNQ

DDRQS

DDRTD

DDRDD

Port Pin Data/Set Data Registers

$0030

$0034

$0038

$003C

$0040

$0044

PORTNQP/SETNQ

PORTQSP/SETQS

PORTTDP/SETTD

PORTDDP/SETDD

Port Clear Output Data Registers

$0048

$004C

$0050

$0054

$0058

$005C

CLRNQ

CLRQS

CLRTD

CLRDD

Reserved

Reserved

PORTUA

PORTLD

Reserved

Reserved

DDRUA

DDRLD

Reserved

Reserved

Reserved

Reserved

CLRUA

CLRLD

Reserved

Reserved

Reserved

Reserved

PORTUAP/SETUA

PORTLDP/SETLD

Reserved

Reserved

PORTAN

PORTTA

PORTUB

PORTGP

DDRAN

DDRTA

DDRUB

DDRGP

PORTANP/SETAN

PORTTAP/SETTA

PORTUBP/SETUB

PORTGPP/SETGP

Reserved

Reserved

CLRAN

CLRTA

CLRUB

CLRGP

PORTAS

PORTTC

PORTUC

Reserved

DDRAS

DDRTC

DDRUC

Reserved

PORTASP/SETAS

PORTTCP/SETTC

PORTUCP/SETUC

Reserved

CLRAS

CLRTC

CLRUC

Reserved

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

S/U

Port Pin Assignment Registers

$0060

$0064

$0068 PNQPAR

PQSPAR $006C

$0070

$0074

PTDPAR

PDDPAR

Port Pad Control Registers

PUAPAR

PLDPAR

Reserved

Reserved

PANPAR

PTAPAR

PUBPAR

PGPPAR

PASPAR

PTCPAR

PUCPAR

Reserved

S/U

S/U

S/U

S/U

S/U

S/U

$0078

$007C

PWOR[15:0]

PDSR[31:0]

PDRR[37:32] S/U

S/U

1

The register address is the sum of the IPSBAR address and the base address offset.

2

S/U = supervisor or user mode access. User mode accesses to supervisor-only addresses have no effect and cause a cycle termination transfer error.

S/U

S/U

S/U

S/U

S/U

S/U



Preliminary

14-5


14.6


14.6.1

Port Output Data Registers (PORT

n

)

The PORT n registers store the data to be driven on the corresponding port n pins when the pins are configured for digital output.

The PORT n registers with a full 8-bit implementation are shown in Figure 11-2 . The remaining PORT n registers use fewer than 8 bits. Their bit definitions are shown in Figure 11-3 , Figure 11-4 , Figure 11-5 , and Figure 11-6 .

The PORT n registers are read/write. At reset, all bits in the PORT n registers are set.

Reading a PORT n register returns the current values in the register, not the port n pin values.

PORT n bits can be set by setting the PORT n register, or by setting the corresponding bits in the

PORT n P/SET n register. They can be cleared by clearing the PORT n register, or by clearing the corresponding bits in the CLR n register.

IPSBAR

Offset:

Base + $000A (PORTAN)

Base + $0014 (PORTDD)

Base + $0016 (PORTGP)

7 6

R

W

Reset:

PORT

1 n 7 PORT n 6

5

PORT n 5

4

PORT n 4

3

PORT n 3

2

PORT n 2

1 1 1 1 1

Figure 14-2. — Port Output Data Registers [7:0]


1

PORT n 1 PORT n 0

1

0

1

IPSBAR

Offset:

Base + $000B (PORTAS)

Base + $000E (PORTTA)

Base + $000F (PORTTC)

Base + $0010 (PORTTD)

Base + $0011 (PORTUA)

Base + $0012 (PORTUB)

Base + $0013 (PORTUC)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3

PORT n 3

2

PORT n 2

0 0 0 1 1



1 0

PORT n 1 PORT n 0

1 1

14-6



Preliminary


IPSBAR

Offset:

Base + $000C (PORTQS)

Base + $0015 (PORTLD)

6 7

0

R

W

Reset: 0

5

PORT n 6 PORT n 5

4

PORT n 4

3

PORT n 3

2

PORT n 2

1 1 1 1 1



1

PORT n 1 PORT n 0

1

0

1

IPSBAR

Offset:

Base + $0008 (PORTNQ)

7 6 5 4 3 2

R

W

Reset:

PORT n 7 PORT n 6 PORT n 5 PORT n 4 PORT n 3 PORT n 2

1 1 1 1 1 1


PORTn

Port n output data bits.

Drive 1 when port n pin is digital output.

Drive 0 when port n pin is digital output.


1

PORT n 1

1

0

0

0

14.6.2

Port Data Direction Registers (DDR

n)

The DDR n registers control the direction of the port n pin drivers when the pins are configured for digital

I/O.

The DDR n registers are read/write. At reset, all bits in the DDR n registers are cleared to 0s.

Setting any bit in a DDR n register configures the corresponding port n pin as an output. Clearing any bit in a DDR n register configures the corresponding pin as an input.

IPSBAR

Offset:

Base + $0022 (DDRAN)

Base + $002C (DDRDD)

Base + $002E (DDRGP)

7 6

R

W

Reset:

DDR

0 n 7 DDR n 6

5

DDR n 5

4

DDR n 4

3

DDR n 3

2

DDR n 2

0 0 0 0 0

Figure 14-6. — Port Data Direction Registers [7:0]


1

DDR n 1

0

0

DDR n 0

0



Preliminary

14-7


IPSBAR

Offset:

Base + $0023 (DDRAS)

Base + $0026 (DDRTA)

Base + $0027 (DDRTC)

Base + $0028 (DDRTD)

Base + $0029 (DDRUA)

Base + $002A (DDRUB)

Base + $002B (DDRUC)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3

DDR n 3

2

DDR n 2

0 0 0 0 0



1

DDR n 1

0

0

DDR n 0

0

IPSBAR

Offset:

Base + $0024 (DDRQS)

Base + $002D (DDRLD)

R

W

Reset:

7

0

6

DDR n 6

5

DDR n 5

4

DDR n 4

3

DDR n 3

2

DDR n 2

0 0 0 0 0 0


DDR n

IPSBAR

Offset:

Base + $001C (DDRNQ)

7 6 5 4 3 2

R

W

Reset:

DDR n 7 DDR n 6 DDR n 5 DDR n 4 DDR n 3 DDR n 2

0 0 0 0 0 0


Port n data direction bits.

1 = Port n pin configured as output.

0 = Port n pin configured as input.


1

DDR n 1

0

1

DDR n 1

0

DDR n 0

0


0

0

0

0

14.6.3

Port Pin Data/Set Data Registers (PORT

n

P/SET

n

)

The PORT n P/SET n registers reflect the current pin states and control the setting of output pins when the pin is configured for digital I/O.

The PORT n P/SET n registers are read/write. At reset, the bits in the PORT n P/SET n registers are set to the current pin states.

Reading a PORT n P/SET n register returns the current state of the port n pins.

14-8



Preliminary


Writing 1s to a PORT n P/SET n register sets the corresponding bits in the PORT n register. Writing 0s has no effect.

IPSBAR

Offset:

Base + $003A (PORTAN/SETAN)

Base + $0044 (PORTDD/SETDD)

Base + $0046 (PORTGPP/SETGP)


7 6 5 4 3 2 1 0

R

W

Reset:

PORT n P7 PORT n P6 PORT n P5 PORT n P4 PORT n P3 PORT n P2 PORT n P1 PORT n P0

1 1 1 1 1 1 1 1

Figure 14-10. PORT n P/SET n — Port Pin Data/Set Data Registers [7:0]

IPSBAR

Offset:

Base + $003B (PORTAS/SETAS)

Base + $003E (PORTTA/SETTA)

Base + $003F (PORTTC/SETTC)

Base + $0040 (PORTTD/SETTD)

Base + $0041 (PORTUA/SETUA)

Base + $0042 (PORTUB/SETUB)

Base + $0043 (PORTUC/SETUC)

7

0

6

0

R

W

Reset:

5

0

4

0

3 2


1 0

PORT n P3 PORT n P2 PORT n P1 PORT n P0

0 0 0 0 1 1 1


1

IPSBAR

Offset:

Base + $003C (PORTQS/SETQS)

Base + $0045 (PORTLD/SETLD)

6 5 7

0

R

W

Reset:

4 3 2


1 0

PORT n P6 PORT n P5 PORT n P4 PORT n P3 PORT n P2 PORT n P1 PORT n P0

1 0 1 1 1 1 1 1


IPSBAR

Offset:

Base + $0038 (PORTNQ/SETNQ) Access: User read/write

7 6 5 4 3 2 1

R

W

Reset:

PORT n P7 PORT n P6 PORT n P5 PORT n P4 PORT n P3 PORT n P2 PORT n P1

1 1 1 1 1 1 1

Figure 14-13. /SET n — Port Pin Data/Set Data Registers [7:1]

0

0

0



Preliminary

14-9


PORT n P/SET n

Port n pin data/set data bits.

1 = Port n pin state is 1 (read); set corresponding PORT n bit (write).

0 = Port n pin state is 0 (read).

14.6.4

Port Clear Output Data Registers (CLR

n

)

Writing 0s to a CLR n register clears the corresponding bits in the PORT n register. Writing 1s has no effect.

Reading the CLR n register returns 0s.

The CLR n registers are read/write.

IPSBAR

Offset:

Base + $005C (CLRDD)

Base + $0052 (CLRAN)

Base + $0054 (CLRGP)

7 6

R

W

Reset:

CLR

0 n 7 CLR n 6

5

CLR n 5

4

CLR n 4

3

CLR n 3

2

CLR n 2

0 0 0 0 0

Figure 14-14. — Port Clear Output Data Registers [7:0]


1

CLR n 1

0

0

CLR n 0

0

IPSBAR

Offset:

Base + $0053 (CLRAS)

Base + $0056 (CLRTA)

Base + $0057 (CLRTC)

Base + $0058 (CLRTD)

Base + $0059 (CLRUA)

Base + $005A (CLRUB)

Base + $005B (CLRUC)

7

0

6

0

R

W

Reset: 0

5

0

4

0

3

CLR n 3

2

CLR n 2

0 0 0 0 0



1

CLR n 1

0

0

CLR n 0

0

IPSBAR

Offset:

Base + $0054 (CLRQS)

Base + $005D (CLRLD)

6 7

0

R

W

Reset: 0

CLR n 6

5

CLR n 5

4

CLR n 4

3

CLR n 3

2

CLR n 2

0 0 0 0 0



1

CLR n 1

0

0

CLR n 0

0

14-10



Preliminary


IPSBAR

Offset:

Base + $0050 (CLRNQ) Access: User read/write

7 6 5 4 3 2

R

W

Reset:

CLR n 7 CLR n 6 CLR n 5 CLR n 4 CLR n 3 CLR n 2

0 0 0 0 0 0


CLR n

Port n clear output data register bits.

1 = Never returned for reads; no effect for writes.

0 = Always returned for reads; clears corresponding PORT n bit for writes.

1

CLR n 1

0

0

0

0

14.6.5

Pin Assignment Registers

All pin assignment registers are read/write.

If multiple pins are configured for the one function, then the result is undefined.

14.6.5.1

Dual Function Pin Assignment Registers

The dual function pin assignment registers allow each pin controlled by each register bit to be configured between the GPIO function and the primary function


Offset:

Base + $006A (PANPAR)

Base + $0074 (PDDPAR)

Base + $0076 (PGPPAR)

7 6 5 4 3 2 1 0

R

W

Reset:

P n PAR7 P n PAR6 P n PAR5 P n PAR4 P n PAR3 P n PAR2 P n PAR1 P n PAR0

0 0 0 0 0 0 0

Figure 14-18. P n PAR — Port n Pin Assignment Registers Dual [7:0]

0

IPSBAR

Offset:

Base + $0075 (PLDPAR)

6 7

0 R

W

Reset: 0

P n PAR6

5

P n PAR5

4

P n PAR4

3

P n PAR3

2

P n PAR2

0 0 0 0 0

Figure 14-19. — Port n Pin Assignment Registers Dual [6:0]


1

P n PAR1

0

0

P n PAR0

0



Preliminary

14-11


IPSBAR

Offset:

Base + $0070 (PTDPAR)

Base + $0073 (PUCPAR)


R

W

Reset:

7

0

6

0

5

0

4

0

3

P n PAR3

2

P n PAR2

1

P n PAR1

0 0 0 0 0 0

Figure 14-20. P n PAR — Port n Pin Assignment Registers Dual [3:0]

0

P n PAR

Port n pin assignment register bits.

1 = Pin assumes the primary function for that pin.

0 = Pin assumes the GPIO function for that pin.

0

P n PAR0

0

14.6.5.2

Quad Function Pin Assignment Registers

The quad function pin assignment registers allow each pin controlled by each register bit to be configured between the GPIO function, primary function, alternate 1 function, and the alternate 2 function


Offset:

Base + $0068 (PNQPAR)

15 14

R

W

Reset 0

P n PAR7

0

13

0

P n PAR6

12

0

11

0

P n PAR5

10

0

9

0

P n PAR4

8

0

R

W

Reset

7 6 5 4 3 2

P n PAR3 P n PAR2 P n PAR1

0 0 0 0 0 0

Figure 14-21. P n PAR — Port n Pin Assignment Registers Quad [15:2]

0

1

0

0

0

0

IPSBAR

Offset:

Base + $006C (PQSPAR)

15

0

14

0 R

W

Reset 0 0

R

W

Reset

7

0

13

P n PAR6

12

0 0

11

P n PAR5

10

0 0


9

P n PAR4

0

8

0

P n PAR3

6 5

P n PAR2

4 3

P n PAR1

2

0 0 0 0 0


0

1

P n PAR0

0

0

14-12



Preliminary


IPSBAR

Offset:

Base + $006B (PASPAR)

Base + $006E (PTAPAR)

Base + $006F (PTCPAR)

Base + $0071 (PUAPAR)

Base + $0072 (PUBPAR)


7 6 5 4 3 2 1 0

R

W

Reset:

P n PAR3 P n PAR2 P n PAR1

0 0 0 0 0 0


0

P n PAR

Port n pin assignment register bits.

Table 14-2. Double Bit Pin Assignment Register Bit

Bit Value

00

01

10

11

Pin Assignment

GPIO function

Primary function

Alternate 1 function

Alternate 2 function

P n PAR0

0

14.6.5.3

Pin Wired OR Register

The Pin Wired OR register is read/write and each bit resets to logic 0. Refer to Table 2-1 for details of

which Pin Wired OR register bit controls which pin.


Offset:

Base + $0078 (PWOR)

14

R

W

Reset

15

PWOR15

0

PWOR14

0

13

PWOR13

0

12 11 10

PWOR 12 PWOR11 PWOR 10

0 0 0

9

PWOR9

0

8

PWOR 8

0

R

W

Reset

7

PWOR7

6

PWOR

6

5

PWOR5

4

PWOR

4

3

PWOR3

2

PWOR

2

1

PWOR1

0 0 0 0 0 0


0

A logic 1 configures the selected bit for Wired OR operation

A logic 0 configures the selected bit for normal operation.

0

PWOR

0

0



Preliminary

14-13


14.6.5.4

Pin Drive Strength Register

The pin drive strength register is read/write, and each bit resets to logic 0 in single chip mode (MCF52235 default) and logic 1 in EzPort and FAST mode.

IPSBAR

Offset:

0x00_007A (PDSR)

R

W

Reset

47

PDSR47

1)

46

PDSR46

45

PDSR45

44

PDSR44

43

PDSR43

42

PDSR42


41

PDSR41

40

PDSR40

33

PDSR33

32

PDSR32

R

W

Reset

39

PDSR39

R

W

Reset

31

PDSR31

1)

R

W

Reset

23

PDSR23

1)

R

W

Reset

15

PDSR15

1)

38

PDSR38

30

PDSR30

22

PDSR22

14

PDSR14

37

PDSR37

29

PDSR29

21

PDSR21

13

PDSR13

36

PDSR36

28

PDSR28

20

PDSR20

12

PDSR12

35

PDSR35

27

PDSR27

19

PDSR19

11

PDSR11

34

PDSR34

26

PDSR26

18

PDSR18

10

PDSR10

7 6 5 4 3

R

W

Reset

PDSR7

1)

PDSR6 PDSR5 PDSR4 PDSR3

1)Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode.

2

PDSR2

Figure 14-25. PDSR — Pin Drive Strength Register [31:0]

25

PDSR25

17

PDSR17

9

PDSR9

1

PDSR1

24

PDSR24

16

PDSR16

8

PDSR8

0

PDSR0

14-14



Preliminary


.

Base + $007A (PDSR) Upper 16bits

Field

Reset

R/W

47

PDSR47

46

PDSR46

45

PDSR45

44

PDSR44

1

43

PDSR43

42

PDSR42

41

PDSR41

40

PDSR40

39 38 37 36

R/W

35 34

Field

Reset

R/W R/W

1

Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode.

33 32

PDSR39 PDSR38 PDSR37 PDSR36 PDSR35 PDSR34 PDSR33 PDSR32

1


.

Base + $007C (PDSR) Low 32 bits

Field

Reset

R/W

31

PDSR31

30

PDSR30

29

PDSR29

28

PDSR28

1

27

PDSR27

26

PDSR26

25

PDSR25

24

PDSR24

Field

Reset

R/W

23

PDSR23

22

PDSR22

21

PDSR21

20

PDSR20

R/W

1

19

PDSR19

18

PDSR18

Field

Reset

R/W

15

PDSR15

14

PDSR14

13

PDSR13

12

PDSR12

R/W

1

11

PDSR11

10

PDSR10

Field

Reset

R/W

7

PDSR7

6

PDSR6

5

PDSR5

4

PDSR4

R/W

1

R/W

3

PDSR3

2

PDSR2

1

Each bit resets to logic 0 in Single Chip mode and logic 1 in EzPort/FAST mode.

17

PDSR17

9

PDSR9

1

PDSR1

16

PDSR16

8

PDSR8

0

PDSR0


PDSR

Pin drive strength register control bits.

1 = Pin is configured for high drive strength (10mA).

0 = Pin is configured for low drive strength (2mA).

14.7

Ports Interrupts

The ports module does not generate interrupt requests.



Preliminary

14-15


14-16



Preliminary

Chapter 15


This section details the functionality for the MCF52235 interrupt controllers (INTC0, INTC1). The general features of each of the interrupt controller include the following:

• 63 interrupt sources per controller

— fully-programmable interrupt sources

— 7 fixed-level interrupt sources

• Each of the 63 sources has a unique interrupt control register (ICR nx ) to define the software-assigned levels and priorities within the level

• Unique vector number for each interrupt source

• Ability to mask any individual interrupt source, plus global mask-all capability

• Supports both hardware and software interrupt acknowledge cycles

• Wake-up signal from low-power stop modes

The 56 fully-programmable and 7 fixed-level interrupt sources for each interrupt controller handle the complete set of interrupt sources from all of the modules on the device. This section describes how the interrupt sources are mapped to the interrupt controller logic and how interrupts are serviced.

15.1

68K/ColdFire Interrupt Architecture Overview

Before continuing with the specifics of the interrupt controllers, a brief review of the interrupt architecture of the 68K/ColdFire family is appropriate.

The interrupt architecture of ColdFire is exactly the same as the M68000 family, where there is a 3-bit encoded interrupt priority level sent from the interrupt controller to the core, providing 7 levels of interrupt requests. Level 7 represents the highest priority interrupt level, while level 1 is the lowest priority. The processor samples for active interrupt requests once per instruction by comparing the encoded priority level against a 3-bit interrupt mask value (I) contained in bits 10:8 of the machine’s status register (SR). If the priority level is greater than the SR[I] field at the sample point, the processor suspends normal instruction execution and initiates interrupt exception processing. Level 7 interrupts are treated as non-maskable and edge-sensitive within the processor, while levels 1–6 are treated as level-sensitive and may be masked depending on the value of the SR[I] field. For correct operation, ColdFire requires that the interrupt source, once asserted, remains asserted until explicitly disabled by the interrupt service routine.

During the interrupt exception processing, the CPU enters supervisor mode, disables trace mode, and then fetches an 8-bit vector from the interrupt controller. This byte-sized operand fetch is known as the interrupt acknowledge (IACK) cycle, with the ColdFire implementation using a special encoding of the transfer type and transfer modifier attributes to distinguish this data fetch from a normal memory access. The fetched data provides an index into the exception vector table, which contains 256 addresses, each pointing



Preliminary

15-1

Interrupt Controller Module to the beginning of a specific exception service routine. In particular, vectors 64–255 of the exception vector table are reserved for user interrupt service routines. The first 64 exception vectors are reserved for the processor to handle reset, error conditions (access, address), arithmetic faults, system calls, etc. Once the interrupt vector number has been retrieved, the processor continues by creating a stack frame in memory. For ColdFire, all exception stack frames are 2 longwords in length and contain 32 bits of vector and status register data, along with the 32-bit program counter value of the instruction that was interrupted

(see Section 3.5, “Exception Stack Frame Definition,”

for more information on the stack frame format).

After the exception stack frame is stored in memory, the processor accesses the 32-bit pointer from the exception vector table using the vector number as the offset, and then jumps to that address to begin execution of the service routine. After the status register is stored in the exception stack frame, the SR[I] mask field is set to the level of the interrupt being acknowledged, effectively masking that level and all lower values while in the service routine. For many peripheral devices, the processing of the IACK cycle directly negates the interrupt request, while other devices require that request to be explicitly negated during the processing of the service routine.

For this device, the processing of the interrupt acknowledge cycle is fundamentally different than previous

68K/ColdFire cores. In the new approach, all IACK cycles are directly handled by the interrupt controller, so the requesting peripheral device is not accessed during IACK. As a result, the interrupt request must be explicitly cleared in the peripheral during the interrupt service routine. For more information, see

Section 15.1.1.3, “Interrupt Vector Determination .”

Unlike the M68000 family, all ColdFire processors guarantee that the first instruction of the service routine is executed before sampling for interrupts is resumed. By making this initial instruction a load of the SR, interrupts can be safely disabled if required.

During the execution of the service routine, the appropriate actions must be performed on the peripheral to negate the interrupt request.

For more information on exception processing, see the ColdFire Programmer’s Reference Manual at http://www.freescale.com/coldfire .

15.1.1

Interrupt Controller Theory of Operation

To support the interrupt architecture of the 68K/ColdFire programming model, the combined 63 interrupt sources are organized as 7 levels, with each level supporting up to 9 prioritized requests. Consider the

priority structure within a single interrupt level (from highest to lowest priority) as shown in Table 15-1

.

Table 15-1. Interrupt Priority Within a Level

ICR[2:0]

111

110

101

100

—

Priority

7 (Highest)

6

5

4

Fixed Midpoint Priority

Interrupt

Sources

8–63

8–63

8–63

8–63

1–7

15-2



Preliminary


Table 15-1. Interrupt Priority Within a Level (continued)

ICR[2:0]

011

010

001

000

Priority

3

2

1

0 (Lowest)

Interrupt

Sources

8–63

8–63

8–63

8–63

The level and priority is fully programmable for all sources except interrupt sources 1–7. Interrupt source

1–7 (from the edgeport module) are fixed at the corresponding level’s midpoint priority. Thus, a maximum of 8 fully-programmable interrupt sources are mapped into a single interrupt level. The fixed interrupt source is hardwired to the given level and represents the mid-point of the priority within the level. For the fully-programmable interrupt sources, the 3-bit level and the 3-bit priority within the level are defined in the 8-bit interrupt control register (ICR nx ).

The operation of the interrupt controller can be broadly partitioned into three activities:

• Recognition

• Prioritization

• Vector determination during IACK

15.1.1.1

Interrupt Recognition

The interrupt controller continuously examines the request sources and the interrupt mask register to determine if there are active requests. This is the recognition phase.

15.1.1.2

Interrupt Prioritization

As an active request is detected, it is translated into the programmed interrupt level, and the resulting 7-bit decoded priority level (IRQ[7:1]) is driven out of the interrupt controller.

15.1.1.3

Interrupt Vector Determination

Once the core has sampled for pending interrupts and begun interrupt exception processing, it generates an interrupt acknowledge (IACK) cycle. The IACK transfer is treated as a memory-mapped byte read by the processor and routed to the appropriate interrupt controller. Next, the interrupt controller extracts the level being acknowledged from address bits 4:2, determines the highest priority interrupt request active for that level, and returns the 8-bit interrupt vector for that request to complete the cycle. The 8-bit interrupt vector is formed using the following algorithm:

For INTC0, vector_number = 64 + interrupt source number

Recall vector_numbers 0–63 are reserved for the ColdFire processor and its internal exceptions. Thus, the following mapping of bit positions to vector numbers applies for the INTC0: if interrupt source 1 is active and acknowledged, if interrupt source 2 is active and acknowledged,

...

then vector_number = 65 then vector_number = 66



Preliminary

15-3

Interrupt Controller Module if interrupt source 8 is active and acknowledged, if interrupt source 9 is active and acknowledged,

...

if interrupt source 62 is active and acknowledged, then vector_number = 72 then vector_number = 73 then vector_number = 126

The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector number.

If there is no active interrupt source for the given level, a special spurious interrupt vector

(vector_number = 24) is returned. It is the responsibility of the service routine to handle this error situation.

Note this protocol implies the interrupting peripheral is not accessed during the acknowledge cycle since the interrupt controller completely services the acknowledge. This means the interrupt source must be explicitly disabled in the interrupt service routine. This design provides unique vector capability for all interrupt requests, regardless of the complexity of the peripheral device.

15.2

Memory Map

The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In the following discussion, there are a number of program-visible registers greater than 32 bits. For these control fields, the physical register is partitioned into two 32-bit values: a register high (the upper longword, represented by an appended “H”) and a register low (the lower longword, represented by an appended “L”).

The registers and their locations are defined in

Table 15-3 . The offsets listed start from the base address

for each interrupt controller. The base addresses for the interrupt controllers are listed below.

Table 15-2. Interrupt Controller Base Addresses

Interrupt Controller Number

INTC

INTC1

Base Address

IPSBAR + 0xC00

IPSBAR + 0xD00

Module Offset

IPSBAR + 0x0C00

IPSBAR + 0x0C04

IPSBAR + 0x0C08

IPSBAR + 0x0C0c

IPSBAR + 0x0C10

IPSBAR + 0x0C14

IPSBAR + 0x0C18

IPSBAR + 0x0C1C–

IPSBAR + 0x0C3C

Table 15-3. Interrupt Controller Memory Map

Bits[31:24]

IRLR[7:1]

Bits[23:16] Bits[15:8]

Interrupt Pending Register High (IPRH), [63:32]

Interrupt Pending Register Low (IPRL), [31:1]

Interrupt Mask Register High (IMRH), [63:32]

Interrupt Mask Register Low (IMRL), [31:0]

Interrupt Force Register High (INTFRCH), [63:32]

Interrupt Force Register Low (INTFRCL), [31:1]

IACKLPR[7:0]

Reserved

Reserved

Bits[7:0]

15-4



Preliminary


Module Offset

IPSBAR + 0x0C40

IPSBAR + 0x0C44

IPSBAR + 0x0C48

IPSBAR + 0x0Cx4C

IPSBAR + 0x0C50

IPSBAR + 0x0C54

IPSBAR + 0x0C58

IPSBAR + 0x0C5C

IPSBAR + 0x0C60

IPSBAR + 0x0C64

IPSBAR + 0x0C68

IPSBAR + 0x0C6C

IPSBAR + 0x0C70

IPSBAR + 0x0C74

IPSBAR + 0x0C78

IPSBAR + 0x0C7C

IPSBAR + 0x0C80–

IPSBAR + 0x0CDC

IPSBAR + 0x0CE0

IPSBAR + 0x0CE4

IPSBAR + 0x0CE8

IPSBAR + 0x0CEC

IPSBAR + 0x0CF0

IPSBAR + 0x0CF4

IPSBAR + 0x0CF8

IPSBAR + 0x0CFC

Table 15-3. Interrupt Controller Memory Map (continued)

Bits[31:24]

ICR32

ICR36

ICR40

ICR44

ICR48

ICR52

ICR56

ICR60

Reserved

ICR04

ICR08

ICR12

ICR16

ICR20

ICR24

ICR28

Bits[23:16]

ICR33

ICR37

ICR41

ICR45

ICR49

ICR53

ICR57

ICR61

ICR01

ICR05

ICR09

ICR13

ICR17

ICR21

ICR25

ICR29

Reserved

Bits[15:8]

ICR34

ICR38

ICR42

ICR46

ICR50

ICR54

ICR58

ICR62

ICR02

ICR06

ICR10

ICR14

ICR18

ICR22

ICR26

ICR30

SWIACK

L1IACK

L2IACK

L3IACK

L4IACK

L5IACK

L6IACK

L7IACK

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

15.3


The interrupt controller registers are described in the following sections.

Bits[7:0]

ICR35

ICR39

ICR43

ICR47

ICR51

ICR55

ICR59

ICR63

ICR03

ICR07

ICR11

ICR15

ICR19

ICR23

ICR27

ICR31

15.3.1

Interrupt Pending Registers (IPRH

n

, IPRL

n

)

The IPRH n and IPRL n registers,

Figure 15-1 and Figure 15-2 , each 32 bits, provide a bit map for each

interrupt request to indicate if there is an active request (1 = active request, 0 = no request) for the given source. The state of the interrupt mask register does not affect the IPR n . The IPR n is cleared by reset. The



Preliminary

15-5


IPR n is a read-only register, so any attempted write to this register is ignored. Bit 0 is not implemented and reads as a zero.

Access: read-only IPSBAR

Offset:

0xC00( (IPRH n )

30 31

R

W

Reset 0 0

29

0

28

0

27

0

26

0

25

0

24 23

INT[63:48]

0 0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

R

W

Reset 0

14

0

13 12 11 10 9 8 7

INT[47:32]

6 5 4 3

0

2

0

1

0

0

0 0 0 0 0 0 0 0 0 0 0

Figure 15-1. Interrupt Pending Register High (IPRH n )

Table 15-4. IPRH n Field Descriptions


31–0

INT

Interrupt pending. Each bit corresponds to an interrupt source. The corresponding IMRH n bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRH n samples the signal generated by the interrupting source. The corresponding IPRH n bit reflects the state of the interrupt signal even if the corresponding

IMRH n bit is set.

0 The corresponding interrupt source does not have an interrupt pending

1 The corresponding interrupt source has an interrupt pending

IPSBAR

Offset:

0xC04 (IPSBMT)

30 29 31

R

W

Reset 0 0 0

15

R

W

Reset 0

14

0

13

0

28

0

12

27

0

11

26

0

10

25 24 23

INT[31:16]

22

0 0 0

9 8

INT[16:1]

7

0

6

21

0

5

20

0 0 0 0 0 0 0 0

Figure 15-2. Interrupt Pending Register Low (IPRL n )

0

0

4

19 18

0

3

0

0

2

0

Access: read-only

17

0

1

0

16

0

0

0

0

15-6



Preliminary


Table 15-5. IPRL n Field Descriptions


31–1

INT

Interrupt Pending. Each bit corresponds to an interrupt source. The corresponding IMRL n bit determines whether an interrupt condition can generate an interrupt. At every system clock, the IPRL n samples the signal generated by the interrupting source. The corresponding IPRL n bit reflects the state of the interrupt signal even if the corresponding

IMRL n bit is set.

0 The corresponding interrupt source does not have an interrupt pending

1 The corresponding interrupt source has an interrupt pending

0 Reserved, should be cleared.

15.3.2

Interrupt Mask Register (IMRH

n

, IMRL

n

)

The IMRH n and IMRL n registers are each 32 bits and provide a bit map for each interrupt to allow the request to be disabled (1 = disable the request, 0 = enable the request). The IMR n is set to all ones by reset, disabling all interrupt requests. The IMR n can be read and written. A write that sets bit 0 of the IMR forces the other 63 bits to be set, disabling all interrupt sources, and providing a global mask-all capability.


Offset:

0xC08( (IMRH n )

30 31

R

W

Reset 1 1

29

1

28

1

27

1

26

1

25 24 23

INT_MASK[63:48]

22

1 1 1 1

21

1

20

1

19

1

18

1

17

1

16

1

15

R

W

Reset 1

14

1

13

1

12 11 10 9 8 7

INT_MASK[47:32]

6 5 4

1 1 1 1 1 1 1 1

Figure 15-3. Interrupt Mask Register High (IMRH n )

1

3

1

2

1

1

1

0

1

Table 15-6. IMRH n Field Descriptions


31–0

INT_MASK

Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRH n bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRH n bit reflects the state of the interrupt signal even if the corresponding IMRH n bit is set.

0 The corresponding interrupt source is not masked

1 The corresponding interrupt source is masked



Preliminary

15-7


IPSBAR

Offset:

0xC0C( (IMRL n )

30 31

R

W

Reset 1 1

29

1

15

R

W

Reset 1

14

1

13

1

28 27 26 25 24 23

INT_MASK[31:16]

22

1 1 1 1

21 20

1 1 1 1 1

12 11 10 9 8 7

INT_MASK[16:1]

6 5 4

1 1 1 1 1 1 1 1

Figure 15-4. Interrupt Mask Register Low (IMRL n )

1

19 18

1

3

1 1

1

2

Access: read/write

17 16

1

1

1

1

0

MAS

KALL

1

Table 15-7. IMRL n Field Descriptions


31–1

INT_MASK

Interrupt mask. Each bit corresponds to an interrupt source. The corresponding IMRL n bit determines whether an interrupt condition can generate an interrupt. The corresponding IPRL n bit reflects the state of the interrupt signal even if the corresponding IMRL n bit is set.

0 The corresponding interrupt source is not masked

1 The corresponding interrupt source is masked

0

MASKALL

Mask all interrupts. Setting this bit will force the other 63 bits of the IMRH n and IMRL n to ones, disabling all interrupt sources, and providing a global mask-all capability.

NOTE

A spurious interrupt may occur if an interrupt source is being masked in the interrupt controller mask register (IMR) or a module’s interrupt mask register while the interrupt mask in the status register (SR[I]) is set to a value lower than the interrupt’s level. This is because by the time the status register acknowledges this interrupt, the interrupt has been masked. A spurious interrupt is generated because the CPU cannot determine the interrupt source.

To avoid this situation for interrupts sources with levels 1–6, first write a higher level interrupt mask to the status register, before setting the mask in the IMR or the module’s interrupt mask register. After the mask is set, return the interrupt mask in the status register to its previous value. Since level 7 interrupts cannot be disabled in the status register prior to masking, use of the IMR or module interrupt mask registers to disable level seven interrupts is not recommended.

15.3.3

Interrupt Force Registers (INTFRCH

n

, INTFRCL

n

)

The INTFRCH n and INTFRCL n registers, each 32 bits, provide a mechanism to allow software generation of interrupts for each possible source for functional or debug purposes. The system design may reserve one

15-8



Preliminary

Interrupt Controller Module or more sources to allow software to self-schedule interrupts by forcing one or more of these bits (1 = force request, 0 = negate request) in the appropriate INTFRC n register. The assertion of an interrupt request via the INTFRC n register is not affected by the interrupt mask register. The INTFRC n register is cleared by reset.


Offset:

0xC10( (INTFRCH n )

30 29 31

R

W

Reset 0 0 0

28

0

27

0

26

0

25 24 23

INTFRCH[63:48]

22

0 0 0 0

21

0

20

0

19

0

18

0

17

0

16

0

15

R

W

Reset 0

14

0

13 12 11 10 9 8 7

INTFRCH[47:32]

6 5 4

0 0 0 0 0 0 0 0 0 0

Figure 15-5. Interrupt Force Register High (INTFRCH n )

3

0

2

0

1

0

0

0

Table 15-8. INTFRCH n Field Descriptions


31–0

INTFRCH

Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.

0 No interrupt forced on corresponding interrupt source

1 Force an interrupt on the corresponding source

IPSBAR

Offset:

0xC14( (INTFRCL n )

30 29 31

R

W

Reset 0 0 0

28

0

15

R

W

Reset 0

14

0

13 12

27

0

11

26

0

10

25 24 23

INTFRCL[31:16]

22

0 0 0 0

9 8 7

INTFRCL[16:1]

6

21

0

5

20

0

4

0 0 0 0 0 0 0 0 0 0

Figure 15-6. Interrupt Force Register Low (INTFRCL n )

19 18

0

3

0

0

2

0

Access: read/write

17

0

1

0

16

0

0

0

0



Preliminary

15-9


.

31 16

Field

Reset

R/W

INTFRCL[31:16]

0000_0000_0000_0000

R/W

Field

Reset

R/W

15

INTFRCL[16:1]

0000_0000_0000_0000

R/W

IPSBAR + 0xC14

Figure 15-7. Interrupt Force Register Low (INTFRCL n )

Table 15-9. INTFRCL n Field Descriptions

1 0

—


31–1

INTFRCL

Interrupt force. Allows software generation of interrupts for each possible source for functional or debug purposes.

0 No interrupt forced on corresponding interrupt source

1 Force an interrupt on the corresponding source


read/

15.3.4

Interrupt Request Level Register (IRLR

n

)

This 7-bit register is updated each machine cycle and represents the current interrupt requests for each interrupt level, where bit 7 corresponds to level 7, bit 6 to level 6, etc.

IPSBAR

Offset:

0xC18 (IRLR n )

7

R

W

Reset: 0

6 5 4

IRQ[7:1]

3 2

0 0 0 0 0

Figure 15-8. Interrupt Request Level Register (IRLR n )

1

0

Access: read-only

0

0

0

15-10



Preliminary


Table 15-10. IRLR n Field Descriptions


7–1

IRQ

0

Interrupt requests. Represents the prioritized active interrupts for each level.

0 There are no active interrupts at this level

1 There is an active interrupt at this level

Reserved

15.3.5

Interrupt Acknowledge Level and Priority Register (IACKLPR

n

)

Each time an IACK is performed, the interrupt controller responds with the vector number of the highest priority source within the level being acknowledged. In addition to providing the vector number directly for the byte-sized IACK read, this 8-bit register is also loaded with information about the interrupt level and priority being acknowledged. This register provides the association between the acknowledged physical interrupt request number and the programmed interrupt level/priority. The contents of this

read-only register are described in Figure 15-9 and Table 15-11

.

Access: read-only IPSBAR

Offset:

0xC19 (IACKLPR n )

7

0 R

W

Reset: 0

6 5

LEVEL

4 3 2

PRI

0 0 0 0 0

Figure 15-9. IACK Level and Priority Register (IACKLPR n )

1

0

0

0

Table 15-11. IACKLPR n Field Descriptions


7 Reserved

6–4

LEVEL

Interrupt level. Represents the interrupt level currently being acknowledged.

3–0

PRI

Interrupt Priority. Represents the priority within the interrupt level of the interrupt currently being acknowledged.

0 Priority 0

1 Priority 1

2 Priority 2

3 Priority 3

4 Priority 4

5 Priority 5

6 Priority 6

7 Priority 7

8 Mid-Point Priority associated with the fixed level interrupts only



Preliminary

15-11


15.3.6

Interrupt Control Register (ICR

nx

)

Each ICR nx , where x = 1, 2,..., 63, specifies the interrupt level (1–7) and the priority within the level (0–7).

All ICR nx registers can be read, but only ICR n 8 to ICR n 63 can be written. It is software’s responsibility to program the ICR nx registers with unique and non-overlapping level and priority definitions. Failure to program the ICR nx registers in this manner can result in undefined behavior. If a specific interrupt request is completely unused, the ICR nx value can remain in its reset (and disabled) state.

IPSBAR

Offset:

See Table 15-2

and

Table 15-3

for register offsets (ICR nx )

7

0

6

0

5 4

R

W

Reset: 0

IL

3

Access: R/W (Read only for ICR n 1-ICR n 7)

2

0 0 0 0

Figure 15-10. Interrupt Control Register (ICR nx )

0

1

IP

0

0

0

Table 15-12. ICR nx Field Descriptions



5–3

IL

Interrupt level. Indicates the interrupt level assigned to each interrupt input.

2–0

IP

Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level assignment. 000b represents the lowest priority and 111b represents the highest. For the fixed level interrupt sources, the priority is fixed at the midpoint for the level, and the IP field will always read as 000b.

15-12



Preliminary


18

19

20

21

22

Source Module

13

14

15

16

9

10

11

12

7

8

5

6

3

4

1

2

EPORT

SCM

DMA

UART0

UART1

UART2

17 I

2

C

QSPI

DTIM0

DTIM1

DTIM2

DTIM3

15.3.6.1

Interrupt Sources

Table 15-13

shows the interrupt sources for each interrupt request line on Interrupt Controller 0.

Table 15-13. Interrupt Source Assignment For Interrupt Controller 0

Flag Source Description Flag Clearing Mechanism

IIF

INT

INT

INT

INT

INT

EPF1

EPF2

EPF3

EPF4

EPF5

EPF6

EPF7

SWTI

Edge port flag 1

Edge port flag 2

Edge port flag 3

Edge port flag 4

Edge port flag 5

Edge port flag 6

Edge port flag 7

Software watchdog timeout

Write EPF1 = 1

Write EPF2 = 1

Write EPF3 = 1

Write EPF4 = 1

Write EPF5 = 1

Write EPF6 = 1

Write EPF7 = 1

Cleared when service complete.

DONE DMA Channel 0 transfer complete Write DONE = 1




INT

INT

INT

UART0 interrupt

UART1 interrupt

UART2 interrupt

Automatically cleared



Not used (Reserved)

I

2

C interrupt

QSPI interrupt

DTIM0 interrupt

DTIM1 interrupt

DTIM2 interrupt

DTIM3 interrupt

Write IIF = 0

Write 1 to appropriate QIR bit

Write 1 to appropriate DTER0 bit






Preliminary

15-13


Source Module

51

52

53

47

48

49

50

43

44

45

46

39

40

41

42

35

36

37

38

31

32

33

34

27

28

29

30

23

24

25

26

FEC

EPHY

GPT

PMM

ADC

PWM

RNGA

Table 15-13. Interrupt Source Assignment For Interrupt Controller 0 (continued)


X_INTF Transmit frame interrupt

X_INTB Transmit buffer interrupt

UN

RL

Transmit FIFO underrun

Collision retry limit

R_INTF Receive frame interrupt

RINTB Receive buffer interrupt

MII

LC

MII interrupt

Late Collision

HBERR Heartbeat error

GRA Graceful stop complete

EBERR Ethernet bus error

BABT Babbling transmit error

BABR Babbling receive error

EPHY EPHY interrupt

Write X_INTF = 1

Write X_INTB = 1

Write UN = 1

Write RL = 1

Write R_INTF = 1

Write R_INTB = 1

Write MII = 1

Write LC = 1

Write HBERR = 1

Write GRA = 1

Write EBERR = 1

Write BABT = 1

Not Used

Not Used

Write BABR = 1

Write EPHYIF = 1

TOF

PAIF

Timer overflow

Pulse accumulator input

PAOVF Pulse accumulator overflow

C0F Timer channel 0

Not Used

Not Used

Write TOF = 1 or access TIMCNTH/L if TFFCA = 1

Write PAIF = 1 or access PAC if TFFCA = 1

Write PAOVF = 1 or access PAC if TFFCA = 1

Write C0F = 1 or access IC/OC if TFFCA = 1

C1F

C2F

Timer channel 1

Timer channel 2

C3F Timer channel 3

LVDF LVD

Write 1 to C1F or access IC/OC if TFFCA = 1



Write LVDF = 1

ADCA ADCA conversion complete

ADCB ADCB conversion complete

ADCINT ADC Interrupt

PWM PWM Interrupt

RNGA RNGA Interrupt

Write 1 to EOSI0

Write 1 to EOSI1

Write 1 to ZCI, LLMTI and HLMTI

Write PWMIF = 1

Clears after one cycle of module reset

15-14



Preliminary


Table 15-13. Interrupt Source Assignment For Interrupt Controller 0 (continued)

Source Module

58

59

60

61

54

55

56

57

62

63

PIT0

PIT1

CFM

CFM

CFM

CFM

RTC


PIF

PIF

PIT interrupt flag

PIT interrupt flag

Not used (Reserved)

Write PIF = 1 or write PMR

Write PIF = 1 or write PMR

Not Used (Reserved)

Not Used (Reserved)

CBEIF SGFM buffer empty

CCIF

PVIF

SGFM command complete

Protection violation

Write CBEIF = 1

Cleared automatically


AEIF

RTC

Access error

RTC Interrupt


Write 1 to appropriate bit.

4

5

2

3

6

7

.

Table 15-14

shows the interrupt sources for each interrupt request line on Interrupt Controller 1

Table 15-14. Interrupt Source Assignment For Interrupt Controller 1

Source Module

1

Flag Source Description

Not Used

Flag Clearing Mechanism

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used



Preliminary

15-15


36

37

38

39

32

33

34

35

28

29

30

31

24

25

26

27

20

21

22

23

16

17

18

19

12

13

14

15

10

11

8

9

Source Module Flag Source Description

BUF0I Message Buffer 2 Interrupt








FLEXCAN







BUF14I Error Interrupt


ERR_INT Message Buffer 3 Interrupt

BOFF_INT Bus-Off Interrupt

EPORT

EPF0

EPF1

EPF2

EPF3

EPF4

EPF5

EPF6

EPF7

Edge port flag 0

Edge port flag 1

Edge port flag 2

Edge port flag 3

Edge port flag 4

Edge port flag 5

Edge port flag 6

Edge port flag 7

Write 1 to BUF2I after reading as 1














Read reported error bits in ESR or write 0 to ERR_INT



Write 0 to BOFF_INT

Not Used

Not Used

Not Used

Not Used

Not Used

Flag Clearing Mechanism

Not Used

Write EPF0 = 1

Write EPF1 = 1

Write EPF2 = 1

Write EPF3 = 1

Write EPF4 = 1

Write EPF5 = 1

Write EPF6 = 1

Write EPF7 = 1

15-16



Preliminary

Source Module

52

53

54

55

48

49

50

51

44

45

46

47

40

41

42

43

60

61

62

63

56

57

58

59

Flag


Flag Clearing Mechanism Source Description

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

Not Used

15.3.7

Software and Level

n

IACK Registers (SWIACK, L

n

IACK)

The 8 IACK registers can be explicitly addressed via the , or implicitly addressed via a processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt controller’s actions are very similar.

When a leveln IACK arrives in the interrupt controller, the controller examines all the currently-active level n interrupt requests, determines the highest priority within the level, and then responds with the unique vector number corresponding to that specific interrupt source. The vector number is supplied as the data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller



Preliminary

15-17

Interrupt Controller Module also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved later.

This interrupt controller design also supports the concept of a software IACK. A software IACK allows an interrupt service routine to determine if there are other pending interrupts so that the overhead associated with interrupt exception processing (including machine state save/restore functions) can be minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to the appropriate service routine, but without taking another interrupt exception.

When the interrupt controller receives a software IACK read, it returns the vector number associated with the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR register is also loaded as the software IACK is performed. If there are no active sources, the interrupt controller returns an all-zero vector as the operand. For this situation, the IACKLPR register is also cleared.

In addition to the software IACK registers within each interrupt controller, there are global software IACK registers. A read from the global SWIACK will return the vector number for the highest level and priority unmasked interrupt source from all interrupt controllers. A read from one of the L n IACK registers will return the vector for the highest priority unmasked interrupt within a level for all interrupt controllers.

IPSBAR

Offset:

See Table 15-2 and Table 15-3

for register offsets

(SWIACK, L n IACK)

7 6 5 4

VECTOR

3

R

W

Reset:

2 1

0 0 0 0 0 0 0

Figure 15-11. Software and Level n IACK Registers (SWIACK, L n IACK)

Access: read-only

0

0

Table 15-15. SWIACK and L n IACK Field Descriptions


7–0

VECTOR

Vector number. A read from the SWIACK register returns the vector number associated with the highest level, highest priority unmasked interrupt source. A read from one of the L n IACK registers returns the highest priority unmasked interrupt source within the level.

15.4

Low-Power Wakeup Operation

The system control module (SCM) contains an 8-bit low-power interrupt control register (LPICR) used explicitly for controlling the low-power stop mode. This register must explicitly be programmed by software to enter low-power mode.

15-18



Preliminary


The interrupt controller provides a special combinatorial logic path to provide a special wake-up signal to exit from the low-power stop mode. This special mode of operation works as follows:

1. LPICR[6:4] is loaded with the mask level that will be specified while the core is in stop mode.

LPICR[7] must be set to enable this mode of operation.

NOTE

The wakeup mask level taken from LPICR[6:4] is adjusted by hardware to allow a level 7 IRQ to generate a wakeup. That is, the wakeup mask value used by the interrupt controller must be in the range of 0–6.

2. The processor executes a STOP instruction which places it in stop mode. Once the processor is stopped, each interrupt controller enables a special logic path that evaluates the incoming interrupt sources in a purely combinatorial path; that is, there are no clocked storage elements. If an active interrupt request is asserted and the resulting interrupt level is greater than the mask value contained in LPICR[6:4], then each interrupt controller asserts the wake-up output signal, which is routed to the SCM and PLL module to re-enable the device’s clock trees and resume processing.



Preliminary

15-19


15-20



Preliminary

Chapter 16


16.1

Introduction

Although this device has two edge port modules, the description included herein treats each module as a single entity. Pay particular attention to the note below, as the two modules are not completely identical.

Specifically, edge port module 0 has seven interrupt inputs while module 1 contains eight. The edge port module (EPORT) has seven external interrupt pins, IRQ7–IRQ1.

Each pin can be configured individually as a level-sensitive interrupt pin, an edge-detecting interrupt pin (rising edge, falling edge, or both), or a general-purpose input/output (I/O) pin.

NOTE

Not all EPORT signals may be output from the device. See Chapter 2,

“Signal Descriptions,” to determine which signals are available.

Stop

Mode

EPPAR[2n, 2n + 1]

Edge Detect

Logic

EPFR n D0

D1

Q D0

D1

Q

To Interrupt

Controller

EPPDR n

Synchronizer

EPIER n

Rising Edge of System Clock

EPDR n

EPDDR n

IRQ n pin

Figure 16-1. EPORT Block Diagram



Preliminary

16-1


NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module” ) prior to configuring the edge port module.

16.2

Low-Power Mode Operation

This section describes the operation of the EPORT module in low-power modes. For more information on low-power modes, see Chapter 8, “Power Management.”

Table 16-1 shows EPORT module operation in

low-power modes, and describes how this module may exit from each mode.

NOTE

The low-power control register (CR) in the system control module specifies the interrupt level at or above which is needed to bring the device out of a low-power mode.

Table 16-1. Edge Port Module Operation in Low-power Modes

Low-power Mode

Wait

Doze

Stop

EPORT Operation

Normal

Normal

Level-sensing only

Mode Exit

Any IRQ n interrupt at or above level in LPCR

Any IRQ n interrupt at or above level in LPCR

Any IRQ n interrupt set for level-sensing at or above level in LPCR. See note below.

In wait and doze modes, the EPORT module continues to operate as it does in run mode. It may be configured to exit the low-power modes by generating an interrupt request on either a selected edge or a low level on an external pin. In stop mode, there are no clocks available to perform the edge-detect function. Only the level-detect logic is active (if configured) to allow any low level on the external interrupt pin to generate an interrupt (if enabled) to exit stop mode.

NOTE

In stop mode, the input pin synchronizer is bypassed for the level-detect logic since no clocks are available.

16.3

Interrupt/GPIO Pin Descriptions

All EPORT pins default to general-purpose input pins at reset. The pin value is synchronized to the rising edge of CLKOUT when read from the EPORT pin data register (EPPDR). The values used in the edge/level detect logic are also synchronized to the rising edge of CLKOUT. These pins use

Schmitt-triggered input buffers that have built-in hysteresis designed to decrease the probability of generating false, edge-triggered interrupts for slow rising and falling input signals.

When a pin is configured as an output, it is driven to a state whose level is determined by the corresponding bit in the EPORT data register (EPDR). All bits in the EPDR are set at reset.

16-2



Preliminary


16.4


This subsection describes the memory map and register structure. Refer to Table 16-2 for a description of

the EPORT memory map.EPORT0 has an IPSBAR offset base address of 0x0013_0000 while EPORT1 has an IPSBAR offset of 0x0014_0000.

Table 16-2. Edge Port Module Memory Map

IPSBAR

Offset

Register

Width

(bits)



1

EPORT Pin Assignment Register (EPPAR) 16 R/W 0x0000

16.4.1/16-3

0x13_0000

0x14_0000

0x13_0002

0x14_0002

0x13_0003

0x14_0003

EPORT Data Direction Register (EPDDR)

EPORT Interrupt Enable Register (EPIER)

8

8

R/W

R/W


0x13_0004

0x14_0004

0x13_0005

0x14_0005

EPORT Data Register (EPDR)

EPORT Pin Data Register (EPPDR)

8

8

R/W

R

0x13_0006

0x14_0006

EPORT Flag Register (EPFR) 8 R/W

1

User access to supervisor only address locations have no effect and result in a bus error

0x00

0x00

0xFF

See Section

0x00

16.4.2/16-4

16.4.3/16-4

16.4.4/16-5

16.4.5/16-5

16.4.6/16-6

16.4.1

EPORT Pin Assignment Register (EPPAR)

The EPORT pin assignment register (EPPAR) controls the function of each pin individually.

Offset

Address:

0x13_0000 (EPPAR0)

0x14_0000 (EPPAR1)

13 15 14

R

W

Reset 0

EPPA7

0

12

EPPA6

11 10

EPPA5

9

EPPA4

8 7

EPPA3

6 5

EPPA2

4

0 0 0 0 0 0 0 0 0 0

Figure 16-2. EPORT Pin Assignment Register (EPPAR)


3

0

EPPA1

2

0

1

0

0

0



Preliminary

16-3


Table 16-3. EPPAR Field Descriptions


15–2

EPPA n

1–0

EPORT pin assignment select fields. The read/write EPPA n fields configure EPORT pins for level detection and rising and/or falling edge detection.

Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request).

Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged, the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected to bring the device out of stop mode with an IRQ n interrupt.

Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin configured for edge detection can trigger an interrupt regardless of its configuration as input or output.

Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR functionality is independent of the selected pin direction.

Reset clears the EPPA n fields.

00 Pin IRQ n level-sensitive

01 Pin IRQ n rising edge triggered

10 Pin IRQ n falling edge triggered

11 Pin IRQ n both falling edge and rising edge triggered


16.4.2

EPORT Data Direction Register (EPDDR)

The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually.

Offset

Address:

0x13_0002 (EPDDR0)

0x14_0002 (EPDDR1)

13 15 14

R

W

EPDD7

Reset 0 0

EPDD6

0

12

0

11

EPDD5

0

10

0

9

EPDD4

0

8

0

7

EPDD3

0

6

0

5

EPDD2

0

4

0

Figure 16-3. EPORT Data Direction Register (EPDDR)


3

EPDD1

0

2

0

1

0

0

0

Table 16-4. EPDDR Field Descriptions


7–1

EPDD n

Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears

EPDD7–EPDD1.

To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.

Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output.

0 Corresponding EPORT pin configured as input

1 Corresponding EPORT pin configured as output


16.4.3

Edge Port Interrupt Enable Register (EPIER)

The EPORT interrupt enable register (EPIER) enables interrupt requests for each pin individually.

16-4



Preliminary


Offset

Address:

0x13_0003 (EPIER0)

0x14_0003 (EPIER1)

7 6

R

W

Reset:

EPIE7

0

EPIE6

5

EPIE5

4

EPIE4

3

EPIE3

2

EPIE2

0 0 0 0 0

Figure 16-4. EPORT Port Interrupt Enable Register (EPIER)


1

EPIE1

0

0

0

0

Table 16-5. EPIER Field Descriptions


7–1

EPIE n

0

Edge port interrupt enable bits enable EPORT interrupt requests. If a bit in EPIER is set, EPORT generates an interrupt request when:

• The corresponding bit in the EPORT flag register (EPFR) is set or later becomes set.

• The corresponding pin level is low and the pin is configured for level-sensitive operation.

Clearing a bit in EPIER negates any interrupt request from the corresponding EPORT pin. Reset clears

EPIE7–EPIE1.

0 Interrupt requests from corresponding EPORT pin disabled

1 Interrupt requests from corresponding EPORT pin enabled


16.4.4

Edge Port Data Register (EPDR)

The EPORT data register (EPDR) holds the data to be driven to the pins.

Offset

Address:

0x13_0004 (EPDR0)

0x14_0004 (EPDR1)

7 6

R

W

Reset:

EPD7

1

EPD6

5

EPD5

4

EPD4

3

EPD3

2

EPD2

1 1 1 1

Figure 16-5. EPORT Port Data Register (EPDR)

1


1

EPD1

1

0

0

1

Table 16-6. EPDR Field Descriptions

Field

7–1

EPD n

0

Description

Edge port data bits. Data written to EPDR is stored in an internal register; if any pin of the port is configured as an output, the bit stored for that pin is driven onto the pin. Reading EDPR returns the data stored in the register. Reset sets EPD7–EPD1.


16.4.5

Edge Port Pin Data Register (EPPDR)

The EPORT pin data register (EPPDR) reflects the current state of the pins.



Preliminary

16-5


Offset

Address:

0x13_0005 (EPPDR0)

0x14_0005 (EPPDR1)

7

EPPD7

6

EPPD6 R

W

Reset: [IRQ7]

5

EPPD5

4

EPPD4

3

EPPD3

2

EPPD2

[IRQ6] [IRQ5] [IRQ4] [IRQ3] [IRQ2]

Figure 16-6. EPORT Port Pin Data Register (EPPDR)

Table 16-7. EPPDR Field Descriptions


1

EPPD1

[IRQ1]

0

0

0


7–1

EPPD n

Edge port pin data bits. The read-only EPPDR reflects the current state of the EPORT pins IRQ7–IRQ1. Writing to

EPPDR has no effect, and the write cycle terminates normally. Reset does not affect EPPDR.


16.4.6

Edge Port Flag Register (EPFR)

The EPORT flag register (EPFR) individually latches EPORT edge events.

Offset

Address:

0x13_0006 (EPFR0)

0x14_0006 (EPFR1)

7 6

R

W

Reset:

EPF7

0

EPF6

5

EPF5

4

EPF4

3

EPF3

2

EPF2

0 0 0 0

Figure 16-7. EPORT Port Flag Register (EPFR)

0


1

EPF1

0

0

0

0

Table 16-8. EPFR Field Descriptions

Field

7–1

EPF n

0

Description

Edge port flag bits. When an EPORT pin is configured for edge triggering, its corresponding read/write bit in EPFR indicates that the selected edge has been detected. Reset clears EPF7–EPF1.

Bits in this register are set when the selected edge is detected on the corresponding pin. A bit remains set until cleared by writing a 1 to it. Writing 0 has no effect. If a pin is configured as level-sensitive (EPPAR n = 00), pin transitions do not affect this register.

0 Selected edge for IRQ n pin has not been detected.

1 Selected edge for IRQ n pin has been detected.


16-6



Preliminary

Chapter 17


17.1

Introduction

17.1.1

Overview

The ColdFire Flash Module (CFM) is a non-volatile memory (NVM) module for integration with a CPU.

The CFM provides 256 Kbytes of 32-bit Flash memory serving as electrically erasable and programmable, non-volatile memory. The Flash memory is ideal for program and data storage for single-chip applications, allowing for field reprogramming without requiring external programming voltage sources.

The common Flash bus interface executes read operations to the Flash memory using one or two system bus cycles to access each Flash physical block, with access latency depending on the factory setting of the

CLKSEL bits in the CFMCLKSEL register. Flash physical blocks are interleaved between odd and even addresses to form a Flash logical block. Interleaving allows back-to-back read operations to the Flash memory at an effective access rate of one system bus cycle per word after the initial two-cycle access if the CLKSEL bits are not set for single cycle access.

It is not possible to read from any Flash logical block while the same logical block is being erased, programmed, or verified. Flash logical blocks are divided into multiple logical pages that can be erased separately. An erased bit reads 1 and a programmed bit reads 0.



Preliminary

17-1


COMMON FLASH BUS

EVEN ODD

COMMON FLASH BUS INTERFACE

EVEN BLOCK ODD BLOCK

ARRAY 0 ARRAY 1 ARRAY 2 ARRAY 3

FLASH MEMORY CONTROLLER

FLASH COMMAND CONTROLLER

INTERNAL FLASH BUS INTERFACE

INTERNAL FLASH BUS

Figure 17-1. CFM Block Diagram

17.1.2

Features

• 256 Kbytes of 32-bit Flash memory

• Automated program, erase, and verify operations

• Single power supply for program and erase operations

• Software programmable interrupts on command completion, access violations, or protection violations

• Fast page erase operation

• Fast word program operation

17-2



Preliminary


• Protection scheme to prevent accidental program or erase of Flash memory

• Access restriction control for supervisor/user and data/instruction operations

• Security feature to prevent unauthorized access to the Flash memory

17.2

External Signal Description

The CFM contains no signals that connect off-chip for the end customer.

17.3

Memory Map and Register Definition

This section describes the CFM memory map and registers.

17.3.1

Memory Map

The memory map for the CFM Flash memory is shown in Figure 17-2 . The starting address of the Flash

memory is determined by the Flash array base address as defined by the system level configuration. The

Flash memory map shows how a pair of 32-bit Flash physical blocks (even and odd) interleave every 4 bytes to form a contiguous memory space as follows:

Flash Block 0 includes byte addresses (PROGRAM_ARRAY_BASE+$0000_0000) to

(PROGRAM_ARRAY_BASE+$0003_FFFF).

(PROGRAM_ARRAY_BASE + $0003_FFFF)

•

•

•

256kBytes

(PROGRAM_ARRAY_BASE + $0000_0000)

Configuration Field

(PROGRAM_ARRAY_BASE+$400) to

(PROGRAM_ARRAY_BASE+$417)

BLOCK ODD (4Bytes)

BLOCK EVEN (4Bytes)

BLOCK ODD (4Bytes)

BLOCK EVEN (4Bytes)

Figure 17-2. CFM Flash Memory Map

The CFM has hardware interlocks that protect data from accidental corruption using program or erase operations. A flexible scheme allows the protection of any combination of Flash logical sectors as

described in Section 17.3.2.4, “CFMPROT — CFM Protection Register .” A similar scheme is available to

control supervisor/user and data/instruction access to these Flash logical sectors.

Security information that allows the MCU to prevent intrusive access to the Flash memory is stored in the

Flash configuration field. The Flash configuration field is composed of 24 bytes of reserved memory space within the Flash memory, which contains information that determines the CFM protection and access restriction scheme out of reset. A description of each byte found in the Flash configuration field is given

in Table 17-1 .



Preliminary

17-3


Address Offset

(from PROGRAM_ARRAY_BASE)

$0400 - $0407

$0408 - $040B

$040C - $040F

$0410 - $0413

$0414 - $0417

Table 17-1. CFM Configuration Field

Size

(bytes)

8

4

4

4

4

Description

Backdoor Comparison Key

Flash Protection Bytes

(see Section 17.3.2.4, “CFMPROT —

CFM Protection Register ”)

Flash SUPV Access Bytes

(see Section 17.3.2.5, “CFMSACC —

CFM Supervisor Access Register ”)

Flash DATA Access Bytes

(see Section 17.3.2.6, “CFMDACC —

CFM Data Access Register

”)

Flash Security Word

(see

Section 17.3.2.3, “CFMSEC —

CFM Security Register

”)

Factory

Default

$FFFF_FFFF_FFFF_FFFF

$FFFF_FFFF

$FFFF_FFFF

$FFFF_FFFF

$FFFF_FFFF

The CFM contains a set of control and status registers located at the register base address as defined by the

system level configuration. A summary of the CFM registers is given in Table 17-2

.

Table 17-2. CFM Register Address Map

1

Address Offset

(from REGISTER_BASE)

$0x0000

$0x0004

$0x0008

$0x000C

$0x0010

$0x0014

$0x0018

$0x001C

$0x0020

$0x0024

$0x0028

$0x002C

$0x0030

$0x0034

$0x0038

$0x003C

$0x0040

$0x0044

$0x0048

Register Bits

31 - 24

CFMMCR

CFMUSTAT

CFMCMD

RESERVED

23 - 16

1

15 - 8

CFMCLKD

RESERVED

1

CFMSEC

RESERVED

1

CFMPROT

CFMSACC

CFMDACC

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

RESERVED

1

CFMCLKSEL

7 - 0

RESERVED

1

Access to reserved address locations generate a cycle termination transfer error.

17-4



Preliminary


17.3.2


17.3.2.1

CFMMCR — CFM Module Configuration Register

The CFMMCR register is used to configure and control the operation of the internal bus interface.

IPSBAR

Offset:

0x0000 ( CFMMCR ) Access: User read/write

15

R 0

W

Reset 0

14

0

13

0

12

0

11 10 9 8 7

0 LOCK PVIE AEIE CBEI

E

6 5

CCIE KEYA

CC

4

0

3

0

2

0

1

0

0

0

0 0 0 0 0 0 0 0 0 0 0

Figure 17-3. CFM Module Configuration Register (CFMMCR)

0 0 0 0

CFMMCR register bits [10:5] are readable and writable with restrictions, while the remaining bits read 0 and are not writable.

Field

15-11

10

LOCK

9

PVIE

8

AEIE

7

CBEIE

6

CCIE

Table 17-3. CFMMCR Field Descriptions

Description

Reserved, will read as 0

Write lock control. The LOCK bit is always readable and is set once.

1 = CFMPROT, CMFSACC, and CFMDACC registers are write-locked.

0 = CFMPROT, CMFSACC, and CFMDACC registers are writable.

Protection violation interrupt enable

The PVIE bit is always readable and writable. The PVIE bit enables an interrupt in case the protection violation flag, PVIOL in the CFMUSTAT register, is set.

1 = An interrupt will be requested whenever the PVIOL flag is set.

0 = PVIOL interrupt disabled.

Access error interrupt enable

The AEIE bit is always readable and writable. The AEIE bit enables an interrupt in case the access error flag, ACCERR in the CFMUSTAT register, is set.

1 = An interrupt will be requested whenever the ACCERR flag is set.

0 = ACCERR interrupt disabled.

Command buffer empty interrupt enable

The CBEIE bit is always readable and writable. The CBEIE bit enables an interrupt in case the command buffer empty flag, CBEIF in the CFMUSTAT register, is set.

1 = An interrupt will be requested whenever the CBEIF flag is set.

0 = CBEIF interrupt disabled.

Command complete interrupt enable

The CCIE bit is always readable and writable. The CCIE bit enables an interrupt in case the command completion flag, CCIF in the CFMUSTAT register, is set.

1 = An interrupt will be requested whenever the CCIF flag is set.

0 = CCIF interrupt disabled.



Preliminary

17-5


Field

5

KEYACC

4-0-

Table 17-3. CFMMCR Field Descriptions (continued)

Description

Enable security key writing

The KEYACC bit is readable and only writable if the KEYEN bits in the CFMSEC register are set to enable backdoor key access.

1 = Writes to CFM Flash memory are interpreted as keys to release security.

0 = Writes to CFM Flash memory are interpreted as the start of a command write sequence.

Reserved, will read as 0

17.3.2.2

CFMCLKD — CFM Clock Divider Register

The CFMCLKD register is used to control the period of the clock used for timed events in program and erase algorithms.

IPSBAR

Offset:

0x0002 (CFMCLKD) Access: User read/write

R

W

Reset:

7

DIVLD

6

PRDIV8

5 4 3

DIV

2 1

0 0 0 0 0 0 0

Figure 17-4. CFM Clock Divider Register (CFMCLKD)

All CFMCLKD register bits are readable, while bits [6:0] write once and bit 7 is not writable.

Table 17-4. CFMCLKD Field Descriptions

0

0

Field

7

DIVLD

6

PRDIV8

5-0

DIV

Description

Clock divider loaded

1 = CFMCLKD register has been written to since the last reset.

0 = CFMCLKD register has not been written.

Enable prescalar by 8

1 = Enables a prescalar to divide the internal Flash bus clock by 8 before feeding into the clock divider.

0 = The internal Flash bus clock is directly fed into the clock divider.

Clock divider bits

The combination of PRDIV8 and DIV effectively divides the internal Flash bus clock down to a frequency of 150 KHz - 200 KHz. The internal Flash bus clock frequency range is 150 KHz < internal Flash bus clock

< 102.4 MHz.

The CFMCLKD register bits PRDIV8 and DIV must be set with appropriate values before programming

or erasing the CFM Flash memory Section 17.4.2.3.1, “Writing the CFMCLKD Register

.”

17.3.2.3

CFMSEC — CFM Security Register

The CFMSEC register is used to store the Flash security word and CFM security state.

17-6



Preliminary


1

2

IPSBAR

Offset:

0x0008 (CFMSEC)

31 30 29

R KEYEN SECSTAT 0

W

Reset F

1

-

2

0

28

0

27

0

26

0

25

0

24

0

23

0

22

0

21

0

0 0 0 0 0 0 0 0

R

W

Reset

15 14 13 12 11 10 9 8

SEC

7 6 5

0 0 0 0 0 0 0 0 0 0 0

Figure 17-5. CFM Security Register (CFMSEC)

Reset state loaded from Flash configuration field during reset.

Reset state determined by security state of CFM.

20

0

0

4

0


19

0

0

3

0

18

0

0

2

0

17

0

0

1

0

16

0

0

0

0

CFMSEC register bits [31:30,15:0] are readable, while remaining bits read 0 and all bits are not writable.

Field

31

KEYEN

30

SECSTAT

29-16

15 - 0

SEC

Table 17-5.

Description

Enable backdoor key access to unlock security

1 = Backdoor key access to Flash module is enabled.

0 = Backdoor key access to Flash module is disabled.

Flash memory security status

1 = Flash security is enabled.

0 = Flash security is disabled.

Reserved, should read 0

Flash memory security bits

The SEC bits define the security state of the MCU as shown in

Table 17-6

, which defines the single code that enables the security feature in the CFM

The CFMSEC register is loaded from the Flash configuration field in the Flash block at offset $0414 during the reset sequence, indicated by “F” in Figure 16-5 .

Table 17-6. CFM Security States

• SEC[15:0]

$4AC8

1

• Description

Flash Memory Secured

1

All other combinations Flash Memory Unsecured

This value was chosen because it represents the ColdFire HALT instruction, making it unlikely that a user compiled code accidentally programmed at the security configuration field location would unintentionally secure the Flash memory.



Preliminary

17-7


The CFM Flash security operation is described in

Section 17.4.3, “Flash Security Operation

.

17.3.2.4

CFMPROT — CFM Protection Register

The CFMPROT register defines which Flash logical sectors are protected against program and erase operations.

IPSBAR

Offset:

0x0010 (CFMPROT) Access: User read/write

22 21 20 19 18 17 16

1

31 30 29 28 27 26 25 24 23

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

PROTECT

F

1

F

1

15 14 13 12 11 10 9 8 7

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

PROTECT


F

1

F

1

F

1

6

F

1

F

1

5

F

1

F

1

4

F

1

F

1

3

F

1

F

1

2

F

1

F

1

1

F

1

F

1

0

F

1

Figure 17-6. CFM Protection Register (CFMPROT)

All CFMPROT register bits are readable and only writable when LOCK=0.

The Flash memory is divided into logical sectors for the purpose of data protection using the CFMPROT register. The Flash memory consists of thirty-two 8-Kbyte sectors, as shown in

Figure 17-7

.

In order to change the Flash memory protection on a temporary basis, the CFMPROT register should be written after the LOCK bit in the CFMMCR register has been cleared. To change the Flash memory protection that will be loaded during the reset sequence, the Flash logical sector containing the Flash configuration field must first be unprotected, then the Flash protection bytes must be programmed with the desired value.

Table 17-7.

Field

31 - 0

PROTECT

Description

Each Flash logical sector can be protected from program and erase operations by setting the

PROTECT[M] bit.

PROTECT[M] = 1: Flash logical sector M is protected.

PROTECT[M] = 0: Flash logical sector M is not protected.

17-8



Preliminary


PROTECT[31:0] —

(PROGRAM_ARRAY_BASE + $0003_FFFF)

PROTECT[31]

SECTOR 31

(PROGRAM_ARRAY_BASE + $0003_E000)


•

•

•

SECTOR 16


SECTOR 15

(PROGRAM_ARRAY_BASE + $0001_E000)


PROTECT[0]

•

•

•

SECTOR 0


8kBytes

Flash Logical Sectors -

8kBytes

protection defined by CFMPROT

8kBytes

8kBytes

Figure 17-7. CFMPROT Protection Diagram

17.3.2.5

CFMSACC — CFM Supervisor Access Register

The CFMSACC register is used to control supervisor/user access to the Flash memory.

IPSBAR

Offset:

0x0014 (CFMSACC) Access: User read/write

23 22 21 20 19 18 17 16

1

31 30 29 28 27 26 25 24

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

SUPV

F

1

15 14 13 12 11 10 9 8

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

SUPV


F

1

F

1

7

F

1

F

1

6

F

1

F

1

5

F

1

F

1

4

F

1

F

1

3

F

1

F

1

2

F

1

F

1

1

F

1

F

1

0

F

1

Figure 17-8. CFM Supervisor Access Register (CFMSACC)

All CFMSACC register bits are readable and only writable when LOCK=0.

In order to change the Flash supervisor access on a temporary basis, the CFMSACC register should be written after the LOCK bit in the CFMMCR register has been cleared. To change the Flash supervisor access that will be loaded during the reset sequence, the Flash logical sector containing the Flash configuration field must first be unprotected, then the Flash supervisor access bytes must be programmed



Preliminary

17-9

ColdFire Flash Module (CFM) with the desired value. Each Flash logical sector may be mapped into supervisor or unrestricted address space (see

Figure 17-7

for details on Flash sector mapping).

Table 17-8.

Field

31 - 0

SUPV

Description

Flash address space assignment for supervisor/user access

SUPV[M] = 1: Flash logical sector M is placed in supervisor address space.

SUPV[M] = 0: Flash logical sector M is placed in unrestricted address space.

17.3.2.6

CFMDACC — CFM Data Access Register

The CFMDACC register is used to control data/instruction access to the Flash memory.

IPSBAR

Offset:

0x0018 (CFMDACC) Access: User read/write

23 22 21 20 19 18 17 16

1

31 30 29 28 27 26 25 24

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

DACC

F

1

15 14 13 12 11 10 9 8

R

W

Reset F

1

F

1

F

1

F

1

F

1

F

1

F

1

DACC


F

1

F

1

7

F

1

F

1

6

F

1

F

1

5

F

1

F

1

4

F

1

F

1

3

F

1

F

1

2

F

1

F

1

1

F

1

F

1

0

F

1

Figure 17-9. CFM Data Access Register (CFMDACC)

All CFMDACC register bits are readable and only writable when LOCK=0.

In order to change the Flash data access on a temporary basis, the CFMDACC register should be written after the LOCK bit in the CFMMCR register has been cleared. To change the Flash data access that will be loaded during the reset sequence, the Flash logical sector containing the Flash configuration field must first be unprotected, then the Flash data access bytes must be programmed with the desired value. Each

Flash logical sector may be mapped into data or both data and instruction address space (see Figure 17-7

for details on Flash sector mapping).

Table 17-9.

Field

31 - 0

DACC

Description

Flash memory address space assignment for data/instruction access

DACC[M] = 1: Flash logical sector M is placed in data address space.

DACC[M] = 0: Flash logical sector M is placed in data and instruction address space.

17-10



Preliminary


17.3.2.7

CFMUSTAT — CFM User Status Register

The CFMUSTAT register defines the Flash command controller status and Flash memory access, protection and verify status.

IPSBAR

Offset:

0x0020 (CFMUSTAT) Access: User read/write

7 6

CCIF

5 4 3

0

2 1

0

0

0 R

W

Reset:

CBEIF

1 1

PVIOL ACCERR

0 0 0

BLANK

0 0 0

Figure 17-10. CFM User Status Register (CFMUSTAT)

CFMUSTAT register bits CBEIF, PVIOL, ACCERR, and BLANK are readable and writable while CCIF is readable but not writable, and remaining bits read 0 and are not writable.

The CFMUSTAT register bits CBEIF, CCIF, PVIOL, ACCERR, and BLANK are available as external signals cfm_status_bits[7:4,2] on the module boundary.

NOTE

Only one CFMUSTAT register bit can be cleared at a time.

Table 17-10.

Field

7

CBEIF

6

CCIF

5

PVIOL

Description

Command buffer empty interrupt flag

The CBEIF flag, set by the Flash command controller, indicates that the address, data and command buffers are empty so that a new command write sequence can be started. The CBEIF flag is cleared by writing a 1 to CBEIF as part of a command write sequence. Writing a 0 to the CBEIF flag has no effect on CBEIF but can be used to abort a command write sequence. The CBEIF flag can generate an interrupt if the CBEIE bit in the CFMMCR register is set.

1 = Buffers are ready to accept a new command write sequence.

0 = Buffers are full.

Command complete interrupt flag

The CCIF flag, set by the Flash command controller, indicates that there are no more commands pending.

The CCIF flag is cleared by the Flash command controller when CBEIF is cleared and sets upon completion of all active and pending commands. Writing to the CCIF flag has no effect on CCIF. The CCIF flag can generate an interrupt if the CCIE bit in the CFMMCR register is set.

1 = All commands are completed.

0 = Command in progress.

Protection violation

The PVIOL flag, set by the Flash command controller, indicates an attempt was made to program or erase an address in a protected Flash logical sector. The PVIOL flag is cleared by writing a 1 to PVIOL. Writing a 0 to the PVIOL flag has no effect on PVIOL. While the PVIOL flag is set, it is not possible to launch a command or start a command write sequence.

1 = Protection violation has occurred.

0 = No protection violation has been detected.



Preliminary

17-11


Field

4

ACCERR

3

2

BLANK

1 -0

Table 17-10.

Description

Access error

The ACCERR flag, set by the Flash command controller, indicates an illegal access was made to the

Flash memory or registers caused by an illegal command write sequence. The ACCERR flag is cleared by writing a 1 to the ACCERR flag. Writing a 0 to the ACCERR flag has no effect on ACCERR. While the

ACCERR flag is set, it is not possible to launch a command or start a command write sequence. See

Section 17.4.2.3.5, “Flash Normal Mode Illegal Operations

” for details on what action sets the ACCERR flag.

1 = Access error has occurred.

0 = No access error has been detected.


All Flash memory locations or the selected Flash logical page have been verified as erased

The BLANK flag, set by the Flash command controller, indicates that a blank check or page erase verify operation has checked all Flash memory locations or the selected Flash logical page and found them to be erased. The BLANK flag is cleared by writing a 1 to BLANK. Writing a 0 to the BLANK flag has no effect on BLANK.

1 = All Flash memory locations or selected logical page verify as erased.

0 = If a blank check or page erase verify command has been executed, and the CCIF flag is set, then a

0 in the BLANK flag indicates that all Flash memory locations are not erased or the selected Flash logical page is not erased.


17.3.2.8

CFMCMD — CFM Command Register

The CFMCMD register is the Flash command register.

IPSBAR

Offset:

0x0024 (CFMCMD)

7

0

6 5 4

R

W

Reset: 0 0 0 0

3

CMD

0

2


1 0

0 0 0

Figure 17-11. CFM Command Buffer and Register (CFMCMD)

All CFMCMD register bits are readable and writable except bit 7, which reads zero and is not writable.

Table 17-11.

Field

7

6 - 0

CMD

Description


Valid Flash memory commands are shown in

Table 17-12 . Writing a command other than those listed in

Table 17-12 during a command write sequence will cause the ACCERR flag in the CFMUSTAT register

to set.

17-12



Preliminary


Table 17-12. CFM Flash Memory Commands

CMD[6:0]

$05

$06

$20

$40

$41

Description

Blank Check

Page Erase Verify

Word Program

Page Erase

Mass Erase

17.3.2.9

CFMCLKSEL — CFM Clock Select Register

The CFMCLKSEL register reflects the factory setting for read access latency from the system bus to the

Flash block.

IPSBAR

Offset:

0x004A( CFMCLKSEL ) Access: User read/write

R

15

0

14

0

13

0

W

Reset 0 0 0

1

Reset state set by factory.

12

0

0

11

0

0

10

0

0

9

0

0

8

0

0

7

0

0

6

0

0

5

0

0

4

0

0

3

0

0

2

0

0

1 0

CLKSEL

F

1

F

1

Figure 17-12. CFM Clock Select Register (CFMCLKSEL)

CFMCLKSEL register bits [1:0] are read-only, while the remaining bits read 0 and are not writable.

Table 17-13.

Field

15 - 2

1 - 0

CLKSEL

Description


Flash read access latency select

The CLKSEL bits set the read access latency to the Flash block.

Table 17-14 describes the setting that

selects between single-cycle and two-cycle Flash block read access.

CLKSEL[1:0]

2’b10

All other combinations

Table 17-14. Clock Select States

Description

Single-Cycle Flash Block Read Access

Two-cycle Flash Block Read Access

Burst Read Access

1-1-1-1

2-1-1-1



Preliminary

17-13


17.4


17.4.1

General

The following modes and operations are described in the following sections:

1. Flash normal mode ( Section 17.4.2, “Flash Normal Mode ”)

a) Read operation (

Section 17.4.2.1, “Read Operation

”)

b) Write operation ( Section 17.4.2.2, “Write Operation ”) c) Program, erase, and verify operations ( Section 17.4.2.3, “Program, Erase, and Verify

Operations ”)

d) Stop mode (

Section 17.4.2.4, “Stop Mode ”)

2. Flash security operation ( Section 17.4.3, “Flash Security Operation ”)

17.4.2

Flash Normal Mode

In Flash normal mode, the user can access the CFM registers and the CFM Flash memory (see

Section 17.3.1, “Memory Map ”).

17.4.2.1

Read Operation

A valid read operation occurs whenever a transfer request is initiated, the address is equal to an address within the valid range of the CFM Flash memory space and the read/write control indicates a read cycle.

17.4.2.2

Write Operation

A valid write operation occurs whenever a transfer request is initiated, the address is equal to an address within the valid range of the CFM Flash memory space and the read/write control indicates a write cycle.

The action taken on a valid Flash array write depends on the subsequent user command issued as part of a valid command write sequence. Only 32-bit write operations are allowed to the Flash memory space. Byte and half-word write operations to the Flash memory space will result in a cycle termination transfer error.

17.4.2.3

Program, Erase, and Verify Operations

Write and read operations are both used for the program, erase, and verify algorithms described in this section. These algorithms are controlled by the Flash memory controller whose timebase, for program and erase operations, is derived from the internal Flash bus clock via a programmable counter.. The command register as well as the associated address and data registers operate as a buffer and a register (2-stage

FIFO), so that a new command along with the necessary data and address can be stored to the buffer while the previous command is still in progress. This buffering operation provides time optimization when programming more than one word on a physical row in the Flash memory as the high voltage generation can be kept active in between two programming operations, thereby saving the time overhead needed for setup of the high voltage charge pumps. Buffer empty as well as command completion are signaled by flags in the CFMUSTAT register with interrupts generated, if enabled.

The next four sections describe the following:

17-14



Preliminary


• How to write the CFMCLKD register

• Command write sequences used to program, erase, and verify the Flash memory

• Valid Flash commands

• Errors resulting from illegal command write sequences to the Flash memory

17.4.2.3.1

Writing the CFMCLKD Register

Prior to issuing any command, it is first necessary to write the CFMCLKD register to divide the input clock to within the 150 KHz to 200 KHz range. The CFMCLKD register bits PRDIV8 and DIV are set as follows:

For frequencies of the input clock greater than 12.8 MHz, the CFMCLKD bit PRDIV8 must be set.

CFMCLKD DIV bit field must be chosen such that the following equation is valid:

If PRDIV8 == 1 then FCLK = input clock / 8, else FCLK = input clock

If (FCLK[KHz] / 200KHz) is integer then DIV = (FCLK[KHz] / 200KHz) - 1, else DIV = INT (FCLK[KHz] / 200kHz)

FCLK, the clock to the Flash block timing control, is therefore:

FCLK = (input clock) / (DIV + 1)

150KHz < FCLK <= 200KHz

For example, if the input clock frequency is 33 MHz, the CFMCLKD DIV field should be set to $14 and bit PRDIV8 set to 1. The resulting FCLK is 196.4 KHz. As a result, the Flash memory program and erase algorithm timings are increased over the optimum target by:

(200 - 196.4) / 200 x 100% = 1.78%

Remark: INT(X) means taking the integer part of X

Example: INT(33MHz/8/200KHz) = 20

CAUTION

Programming the Flash with input clock < 150 KHz should be avoided.

Setting CFMCLKD to a value such that FCLK < 150 KHz can destroy the

Flash memory due to overstress. Setting CFMCLKD to a value such that

FCLK > 200 KHz can result in incomplete programming or erasure of the

Flash memory array cells.

NOTE

Program and Erase command execution time will increase proportionally with the period of FCLK.

If the CFMCLKD register is written, the DIVLD bit is set automatically. If the DIVLD bit is 0, the

CFMCLKD register has not been written since the last reset. No command can be executed if the

CFMCLKD register has not been written to Section 17.4.2.3.5, “Flash Normal Mode Illegal Operations

.”

17.4.2.3.2

Command Write Sequence

The Flash command controller is used to supervise the command write sequence to execute blank check, page erase verify, program, page erase, and mass erase algorithms.



Preliminary

17-15


Before starting a command write sequence, the ACCERR and PVIOL flags in the CFMUSTAT register must be clear and the CBEIF flag should be tested to determine the state of the address, data, and command buffers. If the CBEIF flag is set, indicating the buffers are empty, a new command write sequence can be executed.

A command write sequence consists of three steps which must be strictly adhered to, because writes to the

CFM are not permitted between steps. However, Flash register and array reads are allowed during a command write sequence. The basic command write sequence is as follows:

1. Write to one or more addresses in the Flash memory.

2. Write a valid command to the CFMCMD register.

3. Clear CBEIF flag by writing a 1 to CBEIF to launch the command.

When the CBEIF flag is cleared, the CCIF flag will be cleared on the same bus cycle by the Flash command controller indicating that the command was successfully launched. The CBEIF flag will be set again indicating that the address, data, and command buffers are ready for a new command write sequence to begin. A buffered command will wait for the active command to be completed before being launched.

The CCIF flag in the CFMUSTAT register will set upon completion of all active and buffered commands.

A command write sequence can be aborted at anytime prior to clearing the CBEIF flag in the CFMUSTAT register by writing a 0 to the CBEIF flag. The ACCERR flag in the CFMUSTAT register will be set after successfully aborting a command write sequence and the ACCERR flag must be cleared prior to starting a new command write sequence.

17.4.2.3.3

Bus Arbitration During Write Operations

Once a command has been successfully launched, the CFM will signal the core platform to hold off read accesses to any active Flash physical block until all active and buffered commands have completed

(CCIF=1). A Flash write operation from the internal Flash bus will hold off the Core platform until it is completed.

17.4.2.3.4

Flash Normal Mode Commands

Table 17-15 summarizes the valid Flash normal mode commands.

Table 17-15. CFM Flash Memory Command Description

CFMCMD

$05

$06

$20

$40

$41

Meaning Description

Blank Check Verify that the entire Flash memory is erased. If all bits are erased, the BLANK bit will set

in the CFMUSTAT register, Figure 17-10 , upon command completion.

Page Erase

Verify

Program

Verifies that a Flash logical page is erased. If the Flash logical page is erased, the BLANK

bit will set in the CFMUSTAT register,

Program a 32-bit word.

Figure 17-10 , upon command completion.

Page Erase Erase a Flash logical page.

Mass Erase Erase the entire Flash memory. All Flash memory protection must be disabled.

17-16



Preliminary


Blank Check

The blank check operation will verify that all Flash memory addresses in the CFM are erased.

An example flow to execute the blank check command is shown in

Figure 17-13

. The blank check command write sequence is as follows:

1. Write to any Flash memory address to start the command write sequence for the blank check command. The specific address and data written during the blank check command write sequence will be ignored.

2. Write the blank check command, $05, to the CFMCMD register.

3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the blank check command.

Because all Flash physical blocks are verified simultaneously, the number of internal Flash bus cycles required to execute the blank check operation on a fully erased Flash memory is equal to the number of word addresses in a Flash logical block plus 15 internal Flash bus cycles as measured from the time the

CBEIF flag is cleared until the CCIF flag is set in the CFMUSTAT register. Upon completion of the blank check operation (CCIF=1), the BLANK flag will set in the CFMUSTAT register if the entire Flash memory is erased. If any Flash memory location is not erased, the blank check operation will terminate and the

BLANK flag will remain clear.



Preliminary

17-17


START

Clock Register

Written

Check

Read: Register CFMCLKD

Bit

DIVLD

Set?

yes no

Write: Register CFMCLKD

Read: Register CFMUSTAT

Address, Data,

Command

Buffer Empty Check

Bit

CBEIF

Set?

yes no

Access Error and

Protection Violation

Check

1.

Bit

ACCERR/PVIOL

Set?

yes Write: Register CFMUSTAT

Clear bit ACCERR/PVIOL $30 no

Write: Array Address

and Data

2.

3.

Write: Register CFMCMD

Blank Check Command $05

Write: Register CFMUSTAT

Clear bit CBEIF $80

NOTE: command write sequence aborted by writing $00 to

CFMUSTAT register.


CFMUSTAT register.


Bit Polling for

Command Completion

Check

Bit

CCIF

Set?

no yes


Blank Check

Verify Status

Bit

BLANK

Set?

no yes


Clear bit BLANK $04

Flash Memory

Erased

EXIT EXIT

Flash Memory

Not Erased

Figure 17-13. Example Blank Check Command Flow

17-18



Preliminary


Page Erase Verify

The page erase verify operation will verify that all memory addresses in a Flash logical page are erased.

An example flow to execute the page erase verify operation is shown in Figure 17-14 . The page erase

verify command write sequence is as follows:

1. Write to any word address in a Flash logical page to start the command write sequence for the page erase verify command. The address written will determine the Flash logical page to be verified, while the data written during the page erase verify command write sequence will be ignored.

2. Write the page erase verify command, $06, to the CFMCMD register.

3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the page erase verify command.

Since the word addresses in even and odd Flash blocks are interleaved, pages from adjacent interleaving

Flash physical blocks will automatically be erase verified at the same time. The number of internal Flash bus cycles required to execute the page erase verify operation on a fully erased Flash logical page is equal to the number of word addresses in a Flash logical page plus 15 internal Flash bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set in the CFMUSTAT register.

Upon completion of any page erase verify operation (CCIF=1), the BLANK flag in the CFMUSTAT register will be set if all addresses in the selected Flash logical page are verified to be erased. If any address in the selected Flash logical page is not erased, the page erase verify operation will terminate and the

BLANK flag will remain clear.



Preliminary

17-19


START

Clock Register

Written

Check


Bit

DIVLD

Set?

yes no



Address, Data,

Command

Buffer Empty Check

Bit

CBEIF

Set?

yes no

Access Error and


Check

1.

Bit

ACCERR/PVIOL

Set?

yes Write: Register CFMUSTAT

Clear bit ACCERR/PVIOL $30 no

Write: Logical Page Address

and Dummy Data

2.

3.


Page Erase Verify Command $06


Clear bit CBEIF $80


CFMUSTAT register.


CFMUSTAT register.


Bit Polling for

Command Completion

Check

Bit

CCIF

Set?

no yes


Page Erase

Verify Status

Bit

BLANK

Set?

no yes


Clear bit BLANK $04

Flash Logical Page

Erased

EXIT EXIT

Flash Logical Page

Not Erased

Figure 17-14. Example Page Erase Verify Command Flow

17-20



Preliminary


Program

The program operation will program a previously erased address in the Flash memory using an embedded algorithm.

An example flow to execute the program operation is shown in

Figure 17-15

. The program command write sequence is as follows:

1. Write to a word address in a Flash physical block to start the command write sequence for the program command. The word address written will determine the Flash physical block address to program while the data written during the program command write sequence will determine the data stored at that address. The same relative address in multiple program Flash physical blocks may be programmed simultaneously by writing to the relative address in Flash physical block order: even block, odd block. The Flash physical block written to in the first array write limits the ability to simultaneously program in block order only those Flash physical blocks that remain.

2. Write the program command, $20, to the CFMCMD register.

3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the program command.

If the address to be programmed is in a protected sector of the Flash memory, the PVIOL flag in the

CFMUSTAT register will set and the program command will not launch. Once the program command has successfully launched, the CCIF flag in the CFMUSTAT register will set after the program operation has completed unless a new command write sequence has been buffered.



Preliminary

17-21


START


Clock Register

Written

Check

Bit

DIVLD

Set?

yes no



Bit

CBEIF

Set?

yes no

Access Error and


Check

1.

Bit

ACCERR/PVIOL

Set?

no yes Write: Register CFMUSTAT

Clear bit ACCERR/PVIOL $30

Write: Array Address and

Data

2.

3.


Program Command $20


Clear bit CBEIF $80


CFMUSTAT register.


CFMUSTAT register.


Protection

Violation Check

Address, Data,

Command

Buffer Empty Check

Bit

PVIOL

Set?

no

Bit

CBEIF

Set?

yes yes no



Clear bit PVIOL $20

Change Protection

•

Bit Polling for

Command

Completion Check

Bit

CCIF

Set?

yes

EXIT no yes

Next Write? no

Figure 17-15. Example Program Command Flow

Page Erase

The page erase operation will erase all memory addresses in a Flash logical page using an embedded algorithm.

17-22



Preliminary


An example flow to execute the page erase operation is shown in

Figure 17-16

. The page erase command write sequence is as follows:

1. Write to any word address in a Flash logical page to start the command write sequence for the page erase command. The word address written will determine the Flash logical page to erase while the data written during the page erase command write sequence will be ignored.

2. Write the page erase command, $40, to the CFMCMD register.

3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the page erase command.

If the Flash logical page to be erased is in a protected sector of the Flash memory, the PVIOL flag in the

CFMUSTAT register will set and the page erase command will not launch. Once the page erase command has successfully launched, the CCIF flag in the CFMUSTAT register will set after the page erase operation has completed, unless a new command write sequence has been buffered.



Preliminary

17-23


START


Clock Register

Written

Check

Bit

DIVLD

Set?

yes no



Bit

CBEIF

Set?

yes no

Access Error and


Check

1.

Bit

ACCERR/PVIOL

Set?

no yes Write: Register CFMUSTAT


Write: Logical Page Address

and Dummy Data

2.

3.


Page Erase Command $40


Clear bit CBEIF $80


CFMUSTAT register.


CFMUSTAT register.


Protection

Violation Check

Address, Data,

Command

Buffer Empty Check

Bit

PVIOL

Set?

no

Bit

CBEIF

Set?

yes yes no



Clear bit PVIOL $20

Change Protection

•

Bit Polling for

Command

Completion Check

Bit

CCIF

Set?

yes

EXIT no yes

Next Write? no

Figure 17-16. Example Page Erase Command Flow

Mass Erase

The mass erase operation will erase all Flash memory addresses using an embedded algorithm.

17-24



Preliminary


An example flow to execute the mass erase command is shown in

Figure 17-17

. The mass erase command write sequence is as follows:

1. Write to any Flash memory address to start the command write sequence for the mass erase command. The specific address and data written during the mass erase command write sequence will be ignored.

2. Write the mass erase command, $41, to the CFMCMD register.

3. Clear the CBEIF flag by writing a 1 to CBEIF to launch the mass erase command.

If any Flash logical sector is protected, the PVIOL flag in the CFMUSTAT register will set during the command write sequence and the mass erase command will not launch. Once the mass erase command has successfully launched, the CCIF flag in the CFMUSTAT register will set after the mass erase operation has completed, unless a new command write sequence has been buffered.



Preliminary

17-25


START


Clock Register

Written

Check

Bit

DIVLD

Set?

yes no



Bit

CBEIF

Set?

yes no

Access Error and


Check

1.

Bit

ACCERR/PVIOL

Set?

yes no



Write: Array Address and

Dummy Data

2.

3.


Mass Erase Command $41


Clear bit CBEIF $80


CFMUSTAT register.


CFMUSTAT register.


Protection

Violation Check

Bit

PVIOL

Set?

no yes

Address, Data,

Command

Buffer Empty Check

Bit

CBEIF

Set?

yes no



Clear bit PVIOL $20

Change Protection

•

Bit Polling for

Command

Completion Check

Bit

CCIF

Set?

yes

EXIT no yes

Next Write? no

Figure 17-17. Example Mass Erase Command Flow

17-26



Preliminary


17.4.2.3.5

Flash Normal Mode Illegal Operations

The ACCERR flag will be set during the command write sequence if any of the following illegal operations are performed, causing the command write sequence to immediately abort:

1. Writing to the Flash memory before initializing CFMCLKD.

2. Writing to the Flash memory while CBEIF is not set.

3. Writing to a Flash block with a data size other than 32 bits.

4. After writing to the Flash even block, writing an additional word to the Flash memory during the

Flash command write sequence other than the Flash odd block.

5. Writing an invalid Flash normal mode command to the CFMCMD register.

6. Writing to any CFM register other than CFMCMD after writing to the Flash memory.

7. Writing a second command to the CFMCMD register before executing the previously written command.

8. Writing to any CFM register other than CFMUSTAT (to clear CBEIF) after writing to the command register, CFMCMD.

9. The part enters stop mode and any command is in progress. Upon entering STOP mode, any active command is aborted.

10. Aborting a command write sequence by writing a 0 to the CBEIF flag after writing to the Flash memory or after writing a command to the CFMCMD register but before the command is launched.

The PVIOL flag will be set during the command write sequence if any of the following illegal operations are performed, causing the command write sequence to immediately abort:

1. Writing a program command if the address to program is in a protected Flash logical sector.

2. Writing a page erase command if the address to erase is in a protected Flash logical sector.

3. Writing a mass erase command while any protection is enabled .

If a read operation is attempted on a Flash logical block while a command is active on that logical block

(CCIF=0), the read operation will return invalid data and the ACCERR flag in the CFMUSTAT register will not be set.

17.4.2.4

Stop Mode

If a command is active (CCIF=0) when the MCU enters stop mode, the Flash command controller and

Flash memory controller will perform the following:

1. The active command will be aborted, and the data being programmed or erased is lost.

2. The high voltage circuitry to the Flash arrays will be switched off.

3. Any buffered command (CBEIF=0) will not be executed once the MCU exits stop mode.

4. The CCIF and ACCERR flags will be set if a command is active when the MCU enters stop mode.

CAUTION

As active commands are immediately aborted when the MCU enters stop mode, it is strongly recommended that the user does not execute the stop instruction during program and erase operations.



Preliminary

17-27


If a command is not active (CCIF=1) when the MCU enters stop mode, the ACCERR flag will not set.

17.4.3

Flash Security Operation

The CFM provides security information to the Integration module and the rest of the MCU. This security information is stored within a word in the Flash configuration field. This security word is read automatically after each reset and stored in the CFMSEC register.

In Flash normal mode, the user can bypass the security via a backdoor access sequence using an 8-byte long key. Upon successful completion of the backdoor access sequence, the SECSTAT bit in the CFMSEC register is cleared indicating that the MCU is unsecured.

The CFM may be unsecured via one of the following methods:

1. Executing a backdoor access sequence.

2. Passing a blank check operation on the Flash memory.

17.4.3.1

Backdoor Access Sequence

If the KEYEN bits in the CFMSEC register are set to the enabled state, the user can bypass security by performing the following:

1. Setting the KEYACC bit in the CFMMCR register.

2. Writing the correct 8-byte backdoor comparison key to the Flash memory at offset $0400 - $0407.

This operation must be composed of two 32-bit writes to address $0400 and $0404 in that order.

The two backdoor write cycles can be separated by any number of internal Flash bus cycles.

NOTE

Any attempt to use a key of all zeros or all ones will lock the backdoor access sequence until the CFM is reset.

3. Clearing the KEYACC bit.

4. If all 8 bytes written match the Flash memory content at offset $0400 - $0407, then security is bypassed until the next reset.

In the unsecured state, the user has full control of the contents of the 8-byte backdoor comparison key by programming the bytes at offset $0400 - $0407 of the Flash configuration field. If at any time a key of all

0s or all 1s is received, the backdoor access sequence is terminated and cannot be successfully restarted until after the CFM is reset.

Note that the security of the CFM as defined in the Flash security word at address offset $0414 is not changed by the executing the backdoor access sequence to unsecure the device. After the next reset sequence, the CFM is secured again and the same backdoor key is in effect unless the Flash configuration field was changed by program or erase prior to reset. The backdoor access sequence to unsecure the device has no effect on the program and erase protections defined in the CFM protection register.

The contents of the Flash security word at address offset $0414 must be changed by programming that address when the device is unsecured and the sector containing the Flash configuration field is unprotected.

17-28



Preliminary

.


17.4.3.2

Blank Check

A secured CFM can be unsecured by verifying that the entire Flash memory is erased. If required, the mass erase command can be executed on the Flash memory. The blank check command must then be executed on the Flash memory. The CFM will be unsecured if the blank check operation determines that the entire

Flash memory is erased. After the next reset sequence, the security state of the CFM is determined by the

Flash security word at address offset $0414. For further details on security, see the MCU security specification.

17.4.3.3

JTAG Lockout Recovery

A secured CFM can be unsecured by mass erasing the Flash memory via a sequence of JTAG commands, as specified in the system level security documentation followed by a reset of the MCU.



Preliminary

17-29


17-30



Preliminary

Chapter 18


This chapter provides a feature-set overview and a functional block diagram. Additionally, detailed descriptions of operation and the programming model are included.

18.1

Overview

The Ethernet Media Access Controller (MAC) is designed to support both 10 and 100 Mbps

Ethernet/IEEE 802.3 networks. The MAC must be used in conjunction with the on-board transceiver interface and transceiver function to complete the interface to the media.

18.1.1

Features

The FEC incorporates the following features:

• IEEE 802.3 full duplex flow control

• Programmable max frame length supports IEEE 802.1 VLAN tags and priority

• Support for full-duplex operation (200Mbps throughput) with a minimum system clock rate of

50MHz

• Support for half-duplex operation (100Mbps throughput) with a minimum system clock rate of 25

MHz

• Retransmission from transmit FIFO following a collision (no processor bus utilization)

• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address recognition rejects (no processor bus utilization)

• Address recognition

— Frames with broadcast address may be always accepted or always rejected

— Exact match for single 48-bit individual (unicast) address

— Hash (64-bit hash) check of individual (unicast) addresses

— Hash (64-bit hash) check of group (multicast) addresses

— Promiscuous mode

18.2


The primary operational modes are described in this section.

18.2.1

Full and Half Duplex Operation

Full duplex mode is intended for use on point to point links between switches or end node to switch. Half duplex mode is used in connections between an end node and a repeater or between repeaters. Selection of the duplex mode is controlled by TCR[FDEN].

When configured for full duplex mode, flow control may be enabled. Refer to the TCR[RFC_PAUSE] and

TCR[TFC_PAUSE] bits, the RCR[FCE] bit, and

Section 18.4.10, “Full Duplex Flow Control ,” for more

details.




18.2.2

Interface Options

The following interface options are supported. A detailed discussion of the interface configurations is provided in

Section 18.4.5, “Network Interface Options

”.

18.2.2.1

10 Mbps and 100 Mbps MII Interface

MII is the Media Independent Interface defined by the IEEE 802.3 standard for 10/100 Mbps operation.

The MAC-PHY interface may be configured to operate in MII mode by asserting RCR[MII_MODE].

The speed of operation is determined by the ETXCLK and ERXCLK pins which are driven by the external transceiver. The transceiver will either auto-negotiate the speed or it may be controlled by software via the serial management interface (EMDC/EMDIO pins) to the transceiver. Refer to the MMFR and MSCR register descriptions as well as the section on the MII for a description of how to read and write registers in the transceiver via this interface.

18.2.3

Address Recognition Options

The address options supported are promiscuous, broadcast reject, individual address (hash or exact match),

and multicast hash match. Address recognition options are discussed in detail in Section 18.4.8, “Ethernet

Address Recognition

”.

18.2.4

Internal Loopback

Internal loopback mode is selected via RCR[LOOP]. Loopback mode is discussed in detail in

Section 18.4.13, “Internal and External Loopback ”.

18-2



FEC Top-Level Functional Diagram

18.3

FEC Top-Level Functional Diagram

The block diagram of the FEC is shown below. The FEC is implemented with a combination of hardware and microcode. The off-chip (Ethernet) interfaces are compliant with industry and IEEE 802.3 standards.

SIF

Bus

Controller

Descriptor

Controller

(RISC + microcode)

CSR

RAM

RAM I/F

FIFO

Controller

DMA

MIB

Counters

Transmit Receive

FEC Bus

MII

MDO

MDEN

MDI

I/O

PAD

EMDIO EMDC

ETXEN

ETXD[3:0]

ETXER

ETCLK

ECRS,ECOL

MII/7-WIRE DATA

OPTION

Figure 18-1. FEC Block Diagram

ERXCLK

ERXDV

ERXD[3:0]

ERXER

The descriptor controller is a RISC-based controller that provides the following functions in the FEC:

• Initialization (those internal registers not initialized by the user or hardware)

• High level control of the DMA channels (initiating DMA transfers)

• Interpreting buffer descriptors

• Address recognition for receive frames

• Random number generation for transmit collision backoff timer




NOTE

DMA references in this section refer to the FEC’s DMA engine. This DMA engine is for the transfer of FEC data only, and is not related to the DMA controller described in Chapter 16, “DMA Controller Module ,” nor to the

DMA timers described in Chapter 21, “DMA Timers (DTIM0–DTIM3) .”

The RAM is the focal point of all data flow in the Fast Ethernet Controller and is divided into transmit and receive FIFOs. The FIFO boundaries are programmable using the FRSR register. User data flows to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO into the transmit block and receive data flows from the receive block into the receive FIFO.

The user controls the FEC by writing, through the SIF (Slave Interface) module, into control registers located in each block. The CSR (control and status register) block provides global control (e.g. Ethernet reset and enable) and interrupt handling registers.

The MII block provides a serial channel for control/status communication with the external physical layer device (transceiver). This serial channel consists of the EMDC (Management Data Clock) and EMDIO

(Management Data Input/Output) lines of the MII interface.

The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data and receive descriptor accesses to run independently.

The Transmit and Receive blocks provide the Ethernet MAC functionality (with some assist from microcode).

The Message Information Block (MIB) maintains counters for a variety of network events and statistics.

It is not necessary for operation of the FEC but provides valuable counters for network management. The counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE 802.3

counters. See Section 18.5.3, “MIB Block Counters Memory Map ” for more information.

18.4


This section describes the operation of the FEC, beginning with the hardware and software initialization sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.

Following the software initialization and operation sections are sections providing a detailed description of the functions of the FEC.

18.4.1

Initialization Sequence

This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC, and what locations the user must initialize prior to enabling the FEC.

18.4.1.1

Hardware Controlled Initialization

In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset deasserts output signals and resets general configuration bits.

Other registers reset when the ECR[ETHER_EN] bit is cleared. ECR[ETHER_EN] is deasserted by a hard reset or may be deasserted by software to halt operation. By deasserting ECR[ETHER_EN], the configuration control registers such as the TCR and RCR will not be reset, but the entire data path will be reset.

18-4




Table 18-1. ECR[ETHER_EN] De-Assertion Effect on FEC

Register/Machine

XMIT block

RECV block

DMA block

RDAR

TDAR

Descriptor Controller block

Reset Value

Transmission is aborted (bad CRC appended)

Receive activity is aborted

All DMA activity is terminated

Cleared

Cleared

Halt operation

18.4.2

User Initialization (Prior to Asserting ECR[ETHER_EN])

The user needs to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values will depend on the particular application. The sequence is not important.

Ethernet MAC registers requiring initialization are defined in

Table 18-2 .

Table 18-2. User Initialization (Before ECR[ETHER_EN])

Description

Initialize EIMR

Clear EIR (write 0xFFFF_FFFF)

TFWR (optional)

IALR / IAUR

GAUR / GALR

PALR / PAUR

OPD (only needed for full duplex flow control)

RCR

TCR

MSCR (optional)

Clear MIB_RAM (locations IPSBAR + 0x1200-0x12FC)

FEC FIFO/DMA registers that require initialization are defined in Table 18-3

.

Table 18-3. FEC User Initialization (Before ECR[ETHER_EN])

Description

Initialize FRSR (optional)

Initialize EMRBR

Initialize ERDSR

Initialize ETDSR

Initialize (Empty) Transmit Descriptor ring

Initialize (Empty) Receive Descriptor ring




18.4.3

Microcontroller Initialization

In the FEC, the descriptor control RISC initializes some registers after ECR[ETHER_EN] is asserted.

After the microcontroller initialization sequence is complete, the hardware is ready for operation.

Table 18-4

shows microcontroller initialization operations.

Table 18-4. Microcontroller Initialization

Description

Initialize BackOff Random Number Seed

Activate Receiver

Activate Transmitter

Clear Transmit FIFO

Clear Receive FIFO

Initialize Transmit Ring Pointer

Initialize Receive Ring Pointer

Initialize FIFO Count Registers

18.4.4

User Initialization (After Asserting ECR[ETHER_EN])

After asserting ECR[ETHER_EN], the user can set up the buffer/frame descriptors and write to the TDAR

and RDAR. Refer to Section 18.6, “Buffer Descriptors


18.4.5

Network Interface Options

The FEC supports both an MII interface for 10/100 Mbps Ethernet and a 7-wire serial interface for 10

Mbps Ethernet. The interface mode is selected by the RCR[MII_MODE] bit. In MII mode

(RCR[MII_MODE] = 1), there are 18 signals defined by the IEEE 802.3 standard and supported by the

EMAC. These signals are shown in Table 18-5 below.

Table 18-5. MII Mode

Signal Description

Transmit Clock

Transmit Enable

Transmit Data

Transmit Error

Collision

Carrier Sense

Receive Clock

Receive Data Valid

Receive Data

Receive Error

EMAC pin

ETXCLK

ETXEN

ETXD[3:0]

ETXER

ECOL

ECRS

ERXCLK

ERXDV

ERXD[3:0]

ERXER

18-6




Table 18-5. MII Mode (continued)


Management Data Clock

Management Data

Input/Output

EMAC pin

EMDC

EMDIO

The 7-wire serial mode interface (RCR[MII_MODE] = 0) operates in what is generally referred to as the

“AMD” mode. 7-wire mode connections to the external transceiver are shown in Table 18-6

.

Table 18-6. 7-Wire Mode Configuration

SIGNAL DESCRIPTION

Transmit Clock

Transmit Enable

Transmit Data

Collision

Receive Clock

Receive Data Valid

Receive Data

EMAC PIN

ETXCLK

ETXEN

ETXD[0]

ECOL

ERXCLK

ERXDV

ERXD[0]

18.4.6

FEC Frame Transmission

The Ethernet transmitter is designed to work with almost no intervention from software. Once

ECR[ETHER_EN] is asserted and data appears in the transmit FIFO, the Ethernet MAC is able to transmit onto the network.

When the transmit FIFO fills to the watermark (defined by the TFWR), the MAC transmit logic will assert

ETXEN and start transmitting the preamble (PA) sequence, the start frame delimiter (SFD), and then the frame information from the FIFO. However, the controller defers the transmission if the network is busy

(ECRS asserts). Before transmitting, the controller waits for carrier sense to become inactive, then determines if carrier sense stays inactive for 60 bit times. If so, the transmission begins after waiting an additional 36 bit times (96 bit times after carrier sense originally became inactive). See

Section 18.4.14.1,

“Transmission Errors ” for more details.

If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved from system memory in case of a collision. This improves bus utilization and latency in case immediate retransmission is necessary.

When all the frame data has been transmitted, the FCS (Frame Check Sequence or 32-bit Cyclic

Redundancy Check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the

ABC bit is set in the transmit frame control word, a bad CRC will be appended to the frame data regardless of the TC bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status information to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit in the transmit buffer descriptor for the end of frame buffer = 1).




Both buffer (TXB) and frame (TFINT) interrupts may be generated as determined by the settings in the

EIMR.

The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If the transmit frame length exceeds MAX_FL bytes the BABT interrupt will be asserted, however the entire frame will be transmitted (no truncation).

To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS] is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues transmission until the current frame either finishes or terminates with a collision. After the transmitter has stopped the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes transmission with the next frame.

The Ethernet controller transmits bytes least significant bit first.

18.4.7

FEC Frame Reception

The FEC receiver is designed to work with almost no intervention from the host and can perform address recognition, CRC checking, short frame checking, and maximum frame length checking.

When the driver enables the FEC receiver by asserting ECR[ETHER_EN], it will immediately start processing receive frames. When ERXDV asserts, the receiver will first check for a valid PA/SFD header.

If the PA/SFD is valid, it will be stripped and the frame will be processed by the receiver. If a valid PA/SFD is not found, the frame will be ignored.

In serial mode, the first 16 bit times of RX_D0 following assertion of ERXDV are ignored. Following the first 16 bit times the data sequence is checked for alternating 1/0s. If a 11 or 00 data sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is detected, the PA/SFD sequence is complete.

In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes may occur, but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.

After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.

Once a collision window (64 bytes) of data has been received and if address recognition has not rejected the frame, the receive FIFO is signalled that the frame is “accepted” and may be passed on to the DMA.

If the frame is a runt (due to collision) or is rejected by address recognition, the receive FIFO is notified to “reject” the frame. Thus, no collision fragments are presented to the user except late collisions, which indicate serious LAN problems.

During reception, the Ethernet controller checks for various error conditions and once the entire frame is written into the FIFO, a 32-bit frame status word is written into the FIFO. This status word contains the

M, BC, MC, LG, NO, CR, OV and TR status bits, and the frame length. See

Section 18.4.14.2, “Reception

Errors ” for more details.

Receive Buffer (RXB) and Frame Interrupts (RFINT) may be generated if enabled by the EIMR register.

A receive error interrupt is babbling receiver error (BABR). Receive frames are not truncated if they exceed the max frame length (MAX_FL); however, the BABR interrupt will occur and the LG bit in the

Receive Buffer Descriptor (RxBD) will be set. See Section 18.6.2, “Ethernet Receive Buffer Descriptor

(RxBD) ” for more details.

When the receive frame is complete, the FEC sets the L-bit in the RxBD, writes the other frame status bits into the RxBD, and clears the E-bit. The Ethernet controller next generates a maskable interrupt (RFINT bit in EIR, maskable by RFIEN bit in EIMR), indicating that a frame has been received and is in memory.

The Ethernet controller then waits for a new frame.

18-8




The Ethernet controller receives serial data LSB first.

18.4.8

Ethernet Address Recognition

The FEC filters the received frames based on destination address (DA) type — individual (unicast), group

(multicast), or broadcast (all-ones group address). The difference between an individual address and a group address is determined by the I/G bit in the destination address field. A flowchart for address recognition on received frames is illustrated in the figures below.

Address recognition is accomplished through the use of the receive block and microcode running on the microcontroller. The flowchart shown in

Figure 18-2

illustrates the address recognition decisions made by

the receive block, while Figure 18-3 illustrates the decisions made by the microcontroller.

If the DA is a broadcast address and broadcast reject (RCR[BC_REJ]) is deasserted, then the frame will

be accepted unconditionally, as shown in Figure 18-2 . Otherwise, if the DA is not a broadcast address, then

the microcontroller runs the address recognition subroutine, as shown in Figure 18-3 .

If the DA is a group (multicast) address and flow control is disabled, then the microcontroller will perform a group hash table lookup using the 64-entry hash table programmed in GAUR and GALR. If a hash match occurs, the receiver accepts the frame.

If flow control is enabled, the microcontroller will do an exact address match check between the DA and the designated PAUSE DA (01:80:C2:00:00:01). If the receive block determines that the received frame is a valid PAUSE frame, then the frame will be rejected. Note the receiver will detect a PAUSE frame with the DA field set to either the designated PAUSE DA or the unicast physical address.

If the DA is the individual (unicast) address, the microcontroller performs an individual exact match comparison between the DA and 48-bit physical address that the user programs in the PALR and PAUR registers. If an exact match occurs, the frame is accepted; otherwise, the microcontroller does an individual hash table lookup using the 64-entry hash table programmed in registers, IAUR and IALR. In the case of an individual hash match, the frame is accepted. Again, the receiver will accept or reject the frame based on PAUSE frame detection, shown in

Figure 18-2

.

If neither a hash match (group or individual), nor an exact match (group or individual) occur, then if promiscuous mode is enabled (RCR[PROM] = 1), then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.

Similarly, if the DA is a broadcast address, broadcast reject (RCR[BC_REJ]) is asserted, and promiscuous mode is enabled, then the frame will be accepted and the MISS bit in the receive buffer descriptor is set; otherwise, the frame will be rejected.

In general, when a frame is rejected, it is flushed from the FIFO.




Accept/Reject

Frame

True

Broadcast Addr

?

False

Receive

Address

Recognition

False

Receive Frame

Set BC bit in RCV BD

BC_REJ = 1

?

True

False

Reject Frame

Flush from FIFO

PROM = 1

?

True

Hash Match

?

True

False

Exact Match

?

Receive Frame

Set MC bit in RCV BD if multicast

True

False

Pause Frame

?

False

True

Reject Frame

Flush from FIFO

Receive Frame Receive Frame

Set M (Miss) bit in Rcv BD

Set MC bit in Rcv BD if multicast

Set BC bit in Rcv BD if broadcast

NOTES:

BC_REJ - field in RCR register (BroadCast REJect)

PROM - field in RCR register (PROMiscous mode)

Pause Frame - valid PAUSE frame received

Figure 18-2. Ethernet Address Recognition—Receive Block Decisions

18-10




Receive Address

Recognition

Group

I/G Address

?

FCE

?

False

False

True

Pause Address

?

True

Receive Frame

Hash Search

Group Table

Individual

False

Hash Search

Individual Table

Exact Match

?

True

Receive Frame

Match

?

False

True

Receive Frame

True

Match

?

False

Reject Frame

Flush from FIFO

Receive Frame

Reject Frame

Flush from FIFO

NOTES:

FCE - field in RCR register (Flow Control Enable)

I/G - Individual/Group bit in Destination Address (least significant bit in first byte received in MAC frame)

Figure 18-3. Ethernet Address Recognition—Microcode Decisions

18.4.9

Hash Algorithm

The hash table algorithm used in the group and individual hash filtering operates as follows. The 48-bit destination address is mapped into one of 64 bits, which are represented by 64 bits stored in GAUR, GALR

(group address hash match) or IAUR, IALR (individual address hash match). This mapping is performed by passing the 48-bit address through the on-chip 32-bit CRC generator and selecting the 6 most significant bits of the CRC-encoded result to generate a number between 0 and 63. The MSB of the CRC result selects GAUR (MSB = 1) or GALR (MSB = 0). The least significant 5 bits of the hash result select the bit within the selected register. If the CRC generator selects a bit that is set in the hash table, the frame is accepted; otherwise, it is rejected.

For example, if eight group addresses are stored in the hash table and random group addresses are received, the hash table prevents roughly 56/64 (or 87.5%) of the group address frames from reaching memory.

Those that do reach memory must be further filtered by the processor to determine if they truly contain one of the eight desired addresses.

The effectiveness of the hash table declines as the number of addresses increases.

The hash table registers must be initialized by the user. The CRC32 polynomial to use in computing the hash is:




X 32 + X 26 + X 23 + X 22 + X 16 + X 12 + X 11 + X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X 1

A table of example Destination Addresses and corresponding hash values is included below for reference.

Table 18-7. Destination Address to 6-Bit Hash

48-bit DA

27:ff:ff:ff:ff:ff

07:ff:ff:ff:ff:ff

57:ff:ff:ff:ff:ff

77:ff:ff:ff:ff:ff f7:ff:ff:ff:ff:ff c7:ff:ff:ff:ff:ff

97:ff:ff:ff:ff:ff a7:ff:ff:ff:ff:ff

99:ff:ff:ff:ff:ff b9:ff:ff:ff:ff:ff f9:ff:ff:ff:ff:ff c9:ff:ff:ff:ff:ff

65:ff:ff:ff:ff:ff

55:ff:ff:ff:ff:ff

15:ff:ff:ff:ff:ff

35:ff:ff:ff:ff:ff b5:ff:ff:ff:ff:ff

95:ff:ff:ff:ff:ff d5:ff:ff:ff:ff:ff f5:ff:ff:ff:ff:ff db:ff:ff:ff:ff:ff fb:ff:ff:ff:ff:ff bb:ff:ff:ff:ff:ff

8b:ff:ff:ff:ff:ff

0b:ff:ff:ff:ff:ff

3b:ff:ff:ff:ff:ff

7b:ff:ff:ff:ff:ff

5b:ff:ff:ff:ff:ff

Hash Decimal

Value

20

21

22

23

16

17

18

19

24

25

26

27

12

13

14

15

10

11

8

9

6

7

4

5

2

3

0

1

6-bit Hash (in hex)

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x18

0x19

0x1a

0x1b

0xc

0xd

0xe

0xf

0x8

0x9

0xa

0xb

0x4

0x5

0x6

0x7

0x0

0x1

0x2

0x3

18-12



bf:ff:ff:ff:ff:ff

9f:ff:ff:ff:ff:ff df:ff:ff:ff:ff:ff ef:ff:ff:ff:ff:ff

93:ff:ff:ff:ff:ff b3:ff:ff:ff:ff:ff f3:ff:ff:ff:ff:ff d3:ff:ff:ff:ff:ff

53:ff:ff:ff:ff:ff

73:ff:ff:ff:ff:ff

23:ff:ff:ff:ff:ff

13:ff:ff:ff:ff:ff

3d:ff:ff:ff:ff:ff

0d:ff:ff:ff:ff:ff

5d:ff:ff:ff:ff:ff

7d:ff:ff:ff:ff:ff

59:ff:ff:ff:ff:ff

79:ff:ff:ff:ff:ff

29:ff:ff:ff:ff:ff

19:ff:ff:ff:ff:ff d1:ff:ff:ff:ff:ff f1:ff:ff:ff:ff:ff b1:ff:ff:ff:ff:ff

91:ff:ff:ff:ff:ff

11:ff:ff:ff:ff:ff

31:ff:ff:ff:ff:ff

71:ff:ff:ff:ff:ff

51:ff:ff:ff:ff:ff

7f:ff:ff:ff:ff:ff

4f:ff:ff:ff:ff:ff

1f:ff:ff:ff:ff:ff

3f:ff:ff:ff:ff:ff

Table 18-7. Destination Address to 6-Bit Hash (continued)

48-bit DA


0x34

0x35

0x36

0x37

0x38

0x39

0x3a

0x3b

0x2c

0x2d

0x2e

0x2f

0x30

0x31

0x32

0x33

0x24

0x25

0x26

0x27

0x28

0x29

0x2a

0x2b

0x1c

0x1d

0x1e

0x1f

0x20

0x21

0x22

0x23

Hash Decimal

Value

56

57

58

59

52

53

54

55

48

49

50

51

44

45

46

47

40

41

42

43

36

37

38

39

32

33

34

35

28

29

30

31


Freescale Semiconductor Preliminary


18-13


Table 18-7. Destination Address to 6-Bit Hash (continued)

48-bit DA fd:ff:ff:ff:ff:ff dd:ff:ff:ff:ff:ff

9d:ff:ff:ff:ff:ff bd:ff:ff:ff:ff:ff


0x3c

0x3d

0x3e

0x3f

Hash Decimal

Value

60

61

62

63

18.4.10 Full Duplex Flow Control

Full-duplex flow control allows the user to transmit pause frames and to detect received pause frames.

Upon detection of a pause frame, MAC data frame transmission stops for a given pause duration.

To enable pause frame detection, the FEC must operate in full-duplex mode (TCR[FDEN] asserted) and flow control enable (RCR[FCE]) must be asserted. The FEC detects a pause frame when the fields of the incoming frame match the pause frame specifications, as shown in the table below. In addition, the receive status associated with the frame should indicate that the frame is valid.

Table 18-8. PAUSE Frame Field Specification

48-bit Destination Address

48-bit Source Address

16-bit Type

16-bit Opcode

16-bit PAUSE Duration

0x0180_c200_0001 or Physical Address

Any

0x8808

0x0001

0x0000 to 0xFFFF

Pause frame detection is performed by the receiver and microcontroller modules. The microcontroller runs an address recognition subroutine to detect the specified pause frame destination address, while the receiver detects the type and opcode pause frame fields. On detection of a pause frame, TCR[GTS] is asserted by the FEC internally. When transmission has paused, the EIR[GRA] interrupt is asserted and the pause timer begins to increment. Note that the pause timer makes use of the transmit backoff timer hardware, which is used for tracking the appropriate collision backoff time in half-duplex mode. The pause timer increments once every slot time, until OPD[PAUSE_DUR] slot times have expired. On

OPD[PAUSE_DUR] expiration, TCR[GTS] is deasserted allowing MAC data frame transmission to resume. Note that the receive flow control pause (TCR[RFC_PAUSE]) status bit is asserted while the transmitter is paused due to reception of a pause frame.

To transmit a pause frame, the FEC must operate in full-duplex mode and the user must assert flow control pause (TCR[TFC_PAUSE]). On assertion of transmit flow control pause (TCR[TFC_PAUSE]), the transmitter asserts TCR[GTS] internally. When the transmission of data frames stops, the EIR[GRA]

(graceful stop complete) interrupt asserts. Following EIR[GRA] assertion, the pause frame is transmitted.

On completion of pause frame transmission, flow control pause (TCR[TFC_PAUSE]) and TCR[GTS] are deasserted internally.

The user must specify the desired pause duration in the OPD register.

Note that when the transmitter is paused due to receiver/microcontroller pause frame detection, transmit flow control pause (TCR[TFC_PAUSE]) still may be asserted and will cause the transmission of a single pause frame. In this case, the EIR[GRA] interrupt will not be asserted.

18-14




18.4.11 Inter-Packet Gap (IPG) Time

The minimum inter-packet gap time for back-to-back transmission is 96 bit times. After completing a transmission or after the backoff algorithm completes, the transmitter waits for carrier sense to be negated before starting its 96 bit time IPG counter. Frame transmission may begin 96 bit times after carrier sense is negated if it stays negated for at least 60 bit times. If carrier sense asserts during the last 36 bit times, it will be ignored and a collision will occur.

The receiver receives back-to-back frames with a minimum spacing of at least 28 bit times. If an inter-packet gap between receive frames is less than 28 bit times, the following frame may be discarded by the receiver.

18.4.12 Collision Handling

If a collision occurs during frame transmission, the Ethernet controller will continue the transmission for at least 32 bit times, transmitting a JAM pattern consisting of 32 ones. If the collision occurs during the preamble sequence, the JAM pattern will be sent after the end of the preamble sequence.

If a collision occurs within 512 bit times, the retry process is initiated. The transmitter waits a random number of slot times. A slot time is 512 bit times. If a collision occurs after 512 bit times, then no retransmission is performed and the end of frame buffer is closed with a Late Collision (LC) error indication.

18.4.13 Internal and External Loopback

Both internal and external loopback are supported by the Ethernet controller. In loopback mode, both of the FIFOs are used and the FEC actually operates in a full-duplex fashion. Both internal and external loopback are configured using combinations of the LOOP and DRT bits in the RCR register and the FDEN bit in the TCR register.

For both internal and external loopback set FDEN = 1.

For internal loopback set RCR[LOOP] = 1 and RCR[DRT] = 0. ETXEN and ETXER will not assert during internal loopback. During internal loopback, the transmit/receive data rate is higher than in normal operation because the internal system clock is used by the transmit and receive blocks instead of the clocks from the external transceiver. This will cause an increase in the required system bus bandwidth for transmit and receive data being DMA’d to/from external memory. It may be necessary to pace the frames on the transmit side and/or limit the size of the frames to prevent transmit FIFO underrun and receive FIFO overflow.

For external loopback set RCR[LOOP] = 0, RCR[DRT] = 0 and configure the external transceiver for loopback.

18.4.14 Ethernet Error-Handling Procedure

The Ethernet controller reports frame reception and transmission error conditions using the FEC RxBDs, the EIR register, and the MIB block counters.




18.4.14.1 Transmission Errors

18.4.14.1.1 Transmitter Underrun

If this error occurs, the FEC sends 32 bits that ensure a CRC error and stops transmitting. All remaining buffers for that frame are then flushed and closed. The UN bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.

The “UN” interrupt will be asserted if enabled in the EIMR register.

18.4.14.1.2 Retransmission Attempts Limit Expired

When this error occurs, the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the RL bit is set in the EIR. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.

The “RL” interrupt will be asserted if enabled in the EIMR register.

18.4.14.1.3 Late Collision

When a collision occurs after the slot time (512 bits starting at the Preamble), the FEC terminates transmission. All remaining buffers for that frame are flushed and closed, and the LC bit is set in the EIR register. The FEC will then continue to the next transmit buffer descriptor and begin transmitting the next frame.

The “LC” interrupt will be asserted if enabled in the EIMR register.

18.4.14.1.4 Heartbeat

Some transceivers have a self-test feature called “heartbeat” or “signal quality error.” To signify a good self-test, the transceiver indicates a collision to the FEC within 4 microseconds after completion of a frame transmitted by the Ethernet controller. This indication of a collision does not imply a real collision error on the network, but is rather an indication that the transceiver still seems to be functioning properly. This is called the heartbeat condition.

If the HBC bit is set in the TCR register and the heartbeat condition is not detected by the FEC after a frame transmission, then a heartbeat error occurs. When this error occurs, the FEC closes the buffer, sets the HB bit in the EIR register, and generates the HBERR interrupt if it is enabled.

18.4.14.2 Reception Errors

18.4.14.2.1 Overrun Error

If the receive block has data to put into the receive FIFO and the receive FIFO is full, the FEC sets the OV bit in the RxBD. All subsequent data in the frame will be discarded and subsequent frames may also be discarded until the receive FIFO is serviced by the DMA and space is made available. At this point the receive frame/status word is written into the FIFO with the OV bit set. This frame must be discarded by the driver.

18.4.14.2.2 Non-Octet Error (Dribbling Bits)

The Ethernet controller handles up to seven dribbling bits when the receive frame terminates past an non-octet aligned boundary. Dribbling bits are not used in the CRC calculation. If there is a CRC error,

18-16



Programming Model then the frame non-octet aligned (NO) error is reported in the RxBD. If there is no CRC error, then no error is reported.

18.4.14.2.3 CRC Error

When a CRC error occurs with no dribble bits, the FEC closes the buffer and sets the CR bit in the RxBD.

CRC checking cannot be disabled, but the CRC error can be ignored if checking is not required.

18.4.14.2.4 Frame Length Violation

When the receive frame length exceeds MAX_FL bytes the BABR interrupt will be generated, and the LG bit in the end of frame RxBD will be set. The frame is not truncated unless the frame length exceeds 2047 bytes).

18.4.14.2.5 Truncation

When the receive frame length exceeds 2047 bytes the frame is truncated and the TR bit is set in the receive

BD.

18.5


This section gives an overview of the registers, followed by a description of the buffers.

The FEC is programmed by a combination of control/status registers (CSRs) and buffer descriptors. The

CSRs are used for mode control and to extract global status information. The descriptors are used to pass data buffers and related buffer information between the hardware and software.

18.5.1

Top Level Module Memory Map

The FEC implementation requires a 1-Kbyte memory map space. This is divided into 2 sections of 512 bytes each. The first is used for control/status registers. The second contains event/statistic counters held

in the MIB block. Table 18-9 defines the top level memory map.

Table 18-9. Module Memory Map

Address

IPSBAR + 0x1000-11FF

IPSBAR + 0x1200-13FF

Function

Control/Status Registers

MIB Block Counters

18.5.2

Detailed Memory Map (Control/Status Registers)

Table 18-10

shows the FEC register memory map with each register address, name, and a brief description.

Table 18-10. FEC Register Memory Map

IPSBAR

Offset

0x1004

0x1008

0x1010

0x1014

Name

EIR

EIMR

RDAR

TDAR

Width

32

32

32

32

Description

Interrupt Event Register

Interrupt Mask Register

Receive Descriptor Active Register

Transmit Descriptor Active Register




0x1120

0x1124

0x1144

0x114C

0x1150

0x1180

0x1184

0x1188

IPSBAR

Offset

0x1024

0x1040

0x1044

0x1064

0x1084

0x10C4

0x10E4

0x10E8

0x10EC

0x1118

0x111C

Table 18-10. FEC Register Memory Map (continued)

GAUR

GALR

TFWR

FRBR

FRSR

ERDSR

ETDSR

EMRBR

Name

ECR

MDATA

MSCR

MIBC

RCR

TCR

PALR

PAUR

OPD

IAUR

IALR

Width Description

32

32

32

32

32

32

32

32

32

32

32

32

Ethernet Control Register

MII Data Register

MII Speed Control Register

MIB Control/Status Register

Receive Control Register

Transmit Control Register

Physical Address Low Register

Physical Address High+ Type Field

32

32

32

32

32 Opcode + Pause Duration

32 Upper 32 bits of Individual Hash Table

32 Lower 32 Bits of Individual Hash

Table

Upper 32 bits of Group Hash Table

Lower 32 bits of Group Hash Table

Transmit FIFO Watermark

FIFO Receive Bound Register

FIFO Receive FIFO Start Registers

Pointer to Receive Descriptor Ring

Pointer to Transmit Descriptor Ring

Maximum Receive Buffer Size

18.5.3

MIB Block Counters Memory Map

Table 18-11 defines the MIB Counters memory map which defines the locations in the MIB RAM space

where hardware maintained counters reside. These fall in the 0x1200-0x13FF address offset range. The counters are divided into two groups.

RMON counters are included which cover the Ethernet Statistics counters defined in RFC 1757. In addition to the counters defined in the Ethernet Statistics group, a counter is included to count truncated frames as the FEC only supports frame lengths up to 2047 bytes. The RMON counters are implemented independently for transmit and receive to insure accurate network statistics when operating in full duplex mode.

IEEE counters are included which support the Mandatory and Recommended counter packages defined in section 5 of ANSI/IEEE Std. 802.3 (1998 edition). The IEEE Basic Package objects are supported by the

FEC but do not require counters in the MIB block. In addition, some of the recommended package objects which are supported do not require MIB counters. Counters for transmit and receive full duplex flow control frames are included as well.

18-18



IPSBAR

Offset

0x1260

0x1264

0x1268

0x126C

0x1270

0x1274

0x1284

0x1288

0x1240

0x1244

0x1248

0x124C

0x1250

0x1254

0x1258

0x125c

0x1220

0x1224

0x1228

0x122C

0x1230

0x1234

0x1238

0x123C

0x1200

0x1204

0x1208

0x120C

0x1210

0x1214

0x1218

0x121C


Table 18-11. MIB Counters Memory Map

Mnemonic

RMON_T_DROP

RMON_T_PACKETS

RMON_T_BC_PKT

RMON_T_MC_PKT

RMON_T_CRC_ALIGN

RMON_T_UNDERSIZE

RMON_T_OVERSIZE

RMON_T_FRAG

RMON_T_JAB

RMON_T_COL

RMON_T_P64

RMON_T_P65TO127

RMON_T_P128TO255

RMON_T_P256TO511

RMON_T_P512TO1023

RMON_T_P1024TO2047

RMON_T_P_GTE2048

RMON_T_OCTETS

IEEE_T_DROP

IEEE_T_FRAME_OK

IEEE_T_1COL

IEEE_T_MCOL

IEEE_T_DEF

IEEE_T_LCOL

IEEE_T_EXCOL

IEEE_T_MACERR

IEEE_T_CSERR

IEEE_T_SQE

IEEE_T_FDXFC

IEEE_T_OCTETS_OK

RMON_R_PACKETS

RMON_R_BC_PKT

Description

Count of frames not counted correctly

RMON Tx packet count

RMON Tx Broadcast Packets

RMON Tx Multicast Packets

RMON Tx Packets w CRC/Align error

RMON Tx Packets < 64 bytes, good crc

RMON Tx Packets > MAX_FL bytes, good crc

RMON Tx Packets < 64 bytes, bad crc

RMON Tx Packets > MAX_FL bytes, bad crc

RMON Tx collision count

RMON Tx 64 byte packets

RMON Tx 65 to 127 byte packets





RMON Tx packets w > 2048 bytes

RMON Tx Octets


Frames Transmitted OK

Frames Transmitted with Single Collision

Frames Transmitted with Multiple Collisions

Frames Transmitted after Deferral Delay

Frames Transmitted with Late Collision

Frames Transmitted with Excessive Collisions

Frames Transmitted with Tx FIFO Underrun

Frames Transmitted with Carrier Sense Error

Frames Transmitted with SQE Error

Flow Control Pause frames transmitted

Octet count for Frames Transmitted w/o Error

RMON Rx packet count

RMON Rx Broadcast Packets




IPSBAR

Offset

0x12AC

0x12B0

0x12B4

0x12B8

0x12BC

0x12C0

0x12C4

0x12C8

0x128C

0x1290

0x1294

0x1298

0x129C

0x12A0

0x12A4

0x12A8

0x12CC

0x12D0

0x12D4

0x12D8

0x12DC

0x12E0

Table 18-11. MIB Counters Memory Map (continued)

Mnemonic

RMON_R_MC_PKT

RMON_R_CRC_ALIGN

RMON_R_UNDERSIZE

RMON_R_OVERSIZE

RMON_R_FRAG

RMON_R_JAB

RMON_R_RESVD_0

RMON_R_P64

RMON_R_P65TO127

RMON_R_P128TO255

RMON_R_P256TO511

RMON_R_P512TO1023

RMON_R_P1024TO2047

RMON_R_P_GTE2048

RMON_R_OCTETS

IEEE_R_DROP

IEEE_R_FRAME_OK

IEEE_R_CRC

IEEE_R_ALIGN

IEEE_R_MACERR

IEEE_R_FDXFC

IEEE_R_OCTETS_OK

Description

RMON Rx Multicast Packets

RMON Rx Packets w CRC/Align error

RMON Rx Packets < 64 bytes, good crc

RMON Rx Packets > MAX_FL bytes, good crc

RMON Rx Packets < 64 bytes, bad crc

RMON Rx Packets > MAX_FL bytes, bad crc

RMON Rx 64 byte packets

RMON Rx 65 to 127 byte packets





RMON Rx packets w > 2048 bytes

RMON Rx Octets


Frames Received OK

Frames Received with CRC Error

Frames Received with Alignment Error

Receive Fifo Overflow count

Flow Control Pause frames received

Octet count for Frames Rcvd w/o Error

18.5.4

Registers

The following sections describe each register in detail.

18.5.4.1

Ethernet Interrupt Event Register (EIR)

When an event occurs that sets a bit in the EIR, an interrupt will be generated if the corresponding bit in the interrupt mask register (EIMR) is also set. The bit in the EIR is cleared if a one is written to that bit position; writing zero has no effect. This register is cleared upon hardware reset.

These interrupts can be divided into operational interrupts, transceiver/network error interrupts, and internal error interrupts. Interrupts which may occur in normal operation are GRA, TXF, TXB, RXF, RXB, and MII. Interrupts resulting from errors/problems detected in the network or transceiver are HBERR,

BABR, BABT, LC and RL. Interrupts resulting from internal errors are HBERR and UN.

18-20




Some of the error interrupts are independently counted in the MIB block counters. Software may choose to mask off these interrupts since these errors will be visible to network management via the MIB counters.

• HBERR - IEEE_T_SQE

• BABR - RMON_R_OVERSIZE (good CRC), RMON_R_JAB (bad CRC)

• BABT - RMON_T_OVERSIZE (good CRC), RMON_T_JAB (bad CRC)

• LATE_COL - IEEE_T_LCOL

• COL_RETRY_LIM - IEEE_T_EXCOL

• XFIFO_UN - IEEE_T_MACERR

31 30 29 28 27 26 25 24 23 22 21 20 19

Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR LC RL UN

Reset 0000_0000_0000_0000

R/W R/W

18

—

16

15 0

Field

Reset

R/W

Address

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1004

Figure 18-4. Ethernet Interrupt Event Register (EIR)

Bits

31

30

29

28

Name

HBERR

BABR

BABT

GRA

Table 18-12. EIR Field Descriptions

Description

Heartbeat error. This interrupt indicates that HBC is set in the TCR register and that the COL input was not asserted within the

Heartbeat window following a transmission.

Babbling receive error. This bit indicates a frame was received with length in excess of RCR[MAX_FL] bytes.

Babbling transmit error. This bit indicates that the transmitted frame length has exceeded RCR[MAX_FL] bytes. This condition is usually caused by a frame that is too long being placed into the transmit data buffer(s). Truncation does not occur.

Graceful stop complete. This interrupt will be asserted for one of three reasons. Graceful stop means that the transmitter is put into a pause state after completion of the frame currently being transmitted.

1) A graceful stop, which was initiated by the setting of the

TCR[GTS] bit is now complete.

2) A graceful stop, which was initiated by the setting of the

TCR[TFC_PAUSE] bit is now complete.

3) A graceful stop, which was initiated by the reception of a valid full duplex flow control “pause” frame is now complete. Refer to the “Full Duplex Flow Control” section of the Functional

Description chapter.




Bits

27

26

25

24

23

22

21

20

19

18–0

Table 18-12. EIR Field Descriptions (continued)

Name

TXF

TXB

RXF

RXB

MII

EBERR

LC

RL

UN

—

Description

Transmit frame interrupt. This bit indicates that a frame has been transmitted and that the last corresponding buffer descriptor has been updated.

Transmit buffer interrupt. This bit indicates that a transmit buffer descriptor has been updated.

Receive frame interrupt. This bit indicates that a frame has been received and that the last corresponding buffer descriptor has been updated.

Receive buffer interrupt. This bit indicates that a receive buffer descriptor has been updated that was not the last in the frame.

MII interrupt. This bit indicates that the MII has completed the data transfer requested.

Ethernet bus error. This bit indicates that a system bus error occurred when a DMA transaction was underway. When the

EBERR bit is set, ECR[ETHER_EN] will be cleared, halting frame processing by the FEC. When this occurs software will need to insure that the FIFO controller and DMA are also soft reset.

Late collison. This bit indicates that a collision occurred beyond the collision window (slot time) in half duplex mode. The frame is truncated with a bad CRC and the remainder of the frame is discarded.

Collision retry limit. This bit indicates that a collision occurred on each of 16 successive attempts to transmit the frame. The frame is discarded without being transmitted and transmission of the next frame will commence. Can only occur in half duplex mode.

Transmit FIFO underrun. This bit indicates that the transmit FIFO became empty before the complete frame was transmitted. A bad

CRC is appended to the frame fragment and the remainder of the frame is discarded.


18-22




18.5.4.2

Interrupt Mask Register (EIMR)

The EIMR register controls which interrupt events are allowed to generate actual interrupts. All implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the corresponding bits in both the EIR and EIMR registers are set, the interrupt will be signalled to the CPU.

The interrupt signal will remain asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the EIMR bit.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 16

Field HBERR BABR BABT GRA TXF TXB RXF RXB MII EBERR LC RL UN —

Reset 0000_0000_0000_0000

R/W R/W

15

Field

Reset

R/W

Address

Bits

31–19

18–0

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1008

Figure 18-5. Interrupt Mask Register (EIMR)

Table 18-13. EIMR Field Descriptions

Name Description

See

Figure 18-5

and Table 18-12

.

Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At every processor clock, the EIR samples the signal generated by the interrupting source. The corresponding EIR bit reflects the state of the interrupt signal even if the corresponding

EIMR bit is set.

0 The corresponding interrupt source is masked.

1 The corresponding interrupt source is not masked.

— Reserved, should be cleared.

0

18.5.4.3

Receive Descriptor Active Register (RDAR)

RDAR is a command register, written by the user, that indicates that the receive descriptor ring has been updated (empty receive buffers have been produced by the driver with the empty bit set).

Whenever the register is written, the RDAR bit is set. This is independent of the data actually written by the user. When set, the FEC will poll the receive descriptor ring and process receive frames (provided

ECR[ETHER_EN] is also set). Once the FEC polls a receive descriptor whose empty bit is not set, then the FEC will clear the RDAR bit and cease receive descriptor ring polling until the user sets the bit again, signifying that additional descriptors have been placed into the receive descriptor ring.

The RDAR register is cleared at reset and when ECR[ETHER_EN] is cleared.




Field

Reset

R/W

Field

Reset

R/W

Address

31

15

Bits

31–25

24

—

25 24

R_DES_ACTIVE

0000_0000_0000_0000

R/W

23

—

16

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1010

Figure 18-6. Receive Descriptor Active Register (RDAR)

Table 18-14. RDAR Field Descriptions



R_DES_ACTIVE Set to one when this register is written, regardless of the value written.

Cleared by the FEC device whenever no additional “empty” descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.


0

23–0

18.5.4.4

Transmit Descriptor Active Register (TDAR)

The TDAR is a command register which should be written by the user to indicate that the transmit descriptor ring has been updated (transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).

Whenever the register is written, the TDAR bit is set. This value is independent of the data actually written by the user. When set, the FEC will poll the transmit descriptor ring and process transmit frames (provided

ECR[ETHER_EN] is also set). Once the FEC polls a transmit descriptor whose ready bit is not set, then the FEC will clear the TDAR bit and cease transmit descriptor ring polling until the user sets the bit again, signifying additional descriptors have been placed into the transmit descriptor ring.

The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.

18-24




Field

Reset

R/W

31

—

25 24

X_DES_ACTIVE

0000_0000_0000_0000

R/W

23

—

16

15 0

Field

Reset

R/W

Address

Bits

31–25

24

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1014

Figure 18-7. Transmit Descriptor Active Register (TDAR)

Table 18-15. TDAR Field Descriptions



X_DES_ACTIVE Set to one when this register is written, regardless of the value written.

Cleared by the FEC device whenever no additional “ready” descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.


23–0

18.5.4.5

Ethernet Control Register (ECR)

ECR is a read/write user register, though both fields in this register may be altered by hardware as well.

The ECR is used to enable/disable the FEC.

16

Field

Reset

R/W

31

Field

Reset

R/W

Address

15

—

1111_0000_0000_0000

R/W

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1024

Figure 18-8. Ethernet Control Register (ECR)

1 0

ETHER_EN RESET




Bits

31-2

1

0

Table 18-16. ECR Field Descriptions


— Reserved.

ETHER_EN When this bit is set, the FEC is enabled, and reception and transmission are possible. When this bit is cleared, reception is immediately stopped and transmission is stopped after a bad CRC is appended to any currently transmitted frame. The buffer descriptor(s) for an aborted transmit frame are not updated after clearing this bit. When ETHER_EN is deasserted, the DMA, buffer descriptor, and FIFO control logic are reset, including the buffer descriptor and FIFO pointers. The ETHER_EN bit is altered by hardware under the following conditions:

• ECR[RESET] is set by software, in which case ETHER_EN will be cleared

• An error condition causes the EIR[EBERR] bit to set, in which case ETHER_EN will be cleared

RESET When this bit is set, the equivalent of a hardware reset is performed but it is local to the FEC. ETHER_EN is cleared and all other FEC registers take their reset values. Also, any transmission/reception currently in progress is abruptly aborted.

This bit is automatically cleared by hardware during the reset sequence. The reset sequence takes approximately 8 system clock cycles after RESET is written with a 1.

18.5.4.6

MII Management Frame Register (MMFR)

The MMFR is accessed by the user and does not reset to a defined value. The MMFR register is used to communicate with the attached MII compatible PHY device(s), providing read/write access to their MII registers. Performing a write to the MMFR will cause a management frame to be sourced unless the MSCR has been programmed to 0. In the case of writing to MMFR when MSCR = 0, if the MSCR register is then written to a non-zero value, an MII frame will be generated with the data previously written to the MMFR.

This allows MMFR and MSCR to be programmed in either order if MSCR is currently zero.

RA

18 17 16

TA Field

Reset

R/W

31

ST

30

15

Field

Reset

R/W

Address

29

OP

28 27

PA

Undefined

R/W

23 22

DATA

Undefined

R/W

IPSBAR + 0x1040

Figure 18-9. MII Management Frame Register (MMFR)

0

18-26




Bit

31–30

29–28

27–23

22–18

17–16

15–0

Table 18-17. MMFR Field Descriptions

Name

ST

OP

PA

RA

TA

DATA

Description

Start of frame delimiter. These bits must be programmed to 01 for a valid MII management frame.

Operation code. This field must be programmed to 10 (read) or

01 (write) to generate a valid MII management frame. A value of 11 will produce “read” frame operation while a value of 00 will produce “write” frame operation, but these frames will not be

MII compliant.

PHY address. This field specifies one of up to 32 attached PHY devices.

Register address. This field specifies one of up to 32 registers within the specified PHY device.

Turn around. This field must be programmed to 10 to generate a valid MII management frame.

Management frame data. This is the field for data to be written to or read from the PHY register.

To perform a read or write operation on the MII Management Interface, the MMFR register must be written by the user. To generate a valid read or write management frame, the ST field must be written with a 01 pattern, and the TA field must be written with a 10. If other patterns are written to these fields, a frame will be generated but will not comply with the IEEE 802.3 MII definition.

To generate an IEEE 802.3-compliant MII Management Interface write frame (write to a PHY register), the user must write {01 01 PHYAD REGAD 10 DATA} to the MMFR register. Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted and will be unpredictable if read by the user. Once the write management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written.

To generate an MII Management Interface read frame (read a PHY register) the user must write {01 10

PHYAD REGAD 10 XXXX} to the MMFR register (the content of the DATA field is a don’t care). Writing this pattern will cause the control logic to shift out the data in the MMFR register following a preamble generated by the control state machine. During this time the contents of the MMFR register will be altered as the contents are serially shifted, and will be unpredictable if read by the user. Once the read management frame operation has completed, the MII interrupt will be generated. At this time the contents of the MMFR register will match the original value written except for the DATA field whose contents have been replaced by the value read from the PHY register.

If the MMFR register is written while frame generation is in progress, the frame contents will be altered.

Software should use the MII_STATUS register and/or the MII interrupt to avoid writing to the MMFR register while frame generation is in progress.

18.5.4.7

MII Speed Control Register (MSCR)

The MSCR provides control of the MII clock (EMDC pin) frequency, allows a preamble drop on the MII management frame, and provides observability (intended for manufacturing test) of an internal counter used in generating the EMDC clock signal.




31 16

Field

Reset

R/W

Field

Reset

R/W

Address

15

—

0000_0000_0000_0000

R/W

—

8 7

DIS_PREAMBLE

6

0000_0000_0000_0000

R/W

IPSBAR + 0x1044

Figure 18-10. MII Speed Control Register (MSCR)

MII_SPEED

1 0

—

Bits

31–8

7

6–1

Table 18-18. MSCR Field Descriptions



DIS_PREAMBLE Asserting this bit will cause preamble (32 1’s) not to be prepended to the MII management frame. The MII standard allows the preamble to be dropped if the attached PHY device(s) does not require it.

MII_SPEED MII_SPEED controls the frequency of the MII management interface clock (EMDC) relative to the system clock. A value of 0 in this field will “turn off” the EMDC and leave it in low voltage state. Any non-zero value will result in the EMDC frequency of

1/(MII_SPEED*2) of the system clock frequency.


0

The MII_SPEED field must be programmed with a value to provide an EMDC frequency of less than or equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to a non-zero value in order to source a read or write management frame. After the management frame is complete the MSCR register may optionally be set to zero to turn off the EMDC. The EMDC generated will have a 50% duty cycle except when MII_SPEED is changed during operation (change will take effect following either a rising or falling edge of EMDC).

If the system clock is 25 MHz, programming this register to 0x0000_0005 will result in an EMDC frequency of 25 MHz * 1/10 = 2.5 MHz. A table showing optimum values for MII_SPEED as a function of system clock frequency is provided below.

Table 18-19. Programming Examples for MSCR

System Clock Frequency

25 MHz

33 MHz

40 MHz

MII_SPEED (field in reg)

0x5

0x7

0x8

EMDC frequency

2.5 MHz

2.36 MHz

2.5 MHz

18-28




Table 18-19. Programming Examples for MSCR (continued)

System Clock Frequency

50 MHz

66 MHz

MII_SPEED (field in reg)

0xA

0xD

EMDC frequency

2.5 MHz

2.5 MHz

18.5.4.8

MIB Control Register (MIBC)

The MIBC is a read/write register used to provide control of and to observe the state of the MIB block.

This register is accessed by user software if there is a need to disable the MIB block operation. For example, in order to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See

Table 18-11

for the locations of the MIB counters.

16 31 30

Field MIB_DISABLE MIB_IDLE

Reset

R/W

15

Field

Reset

R/W

Address

1100_0000_000_000

R/W

—

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1064

Figure 18-11. MIB Control Register (MIBC)

Bits

31

30

29–0

Table 18-20. MIBC Field Descriptions


MIB_DISABLE A read/write control bit. If set, the MIB logic will halt and not update any MIB counters.

MIB_IDLE

—

A read-only status bit. If set the MIB block is not currently updating any MIB counters.

Reserved.

0




18.5.4.9

Receive Control Register (RCR)

The RCR is programmed by the user. The RCR controls the operational mode of the receive block and should be written only when ECR[ETHER_EN] = 0 (initialization time).

Field

Reset

R/W

31

Field

Reset

R/W

Address

15

Bits

31–27

26–16

15–6

5

4

3

2

—

27 26 16

MAX_FL

0000_0101_1110_1110

R/W

—

6 5 4 3 2 1 0

FCE BC_REJ PROM MII_MODE DRT LOOP

0000_0000_0000_0001

R/W

IPSBAR + 0x1084

Figure 18-12. Receive Control Register (RCR)

Table 18-21. RCR Field Descriptions

Name

—

MAX_FL

—

FCE

BC_REJ

PROM

MII_MODE

Description


Maximum frame length. Resets to decimal 1518. Length is measured starting at DA and includes the CRC at the end of the frame. Transmit frames longer than MAX_FL will cause the BABT interrupt to occur. Receive Frames longer than

MAX_FL will cause the BABR interrupt to occur and will set the LG bit in the end of frame receive buffer descriptor. The recommended default value to be programmed by the user is 1518 or 1522 (if VLAN Tags are supported).


Flow control enable. If asserted, the receiver will detect

PAUSE frames. Upon PAUSE frame detection, the transmitter will stop transmitting data frames for a given duration.

Broadcast frame reject. If asserted, frames with DA

(destination address) = FF_FF_FF_FF_FF_FF will be rejected unless the PROM bit is set. If both BC_REJ and

PROM = 1, then frames with broadcast DA will be accepted and the M (MISS) bit will be set in the receive buffer descriptor.

Promiscuous mode. All frames are accepted regardless of address matching.

Media independent interface mode. Selects external interface mode. Setting this bit to one selects MII mode, setting this bit equal to zero selects 7-wire mode (used only for serial 10 Mbps). This bit controls the interface mode for both transmit and receive blocks.

18-30



Bits

1

0


Table 18-21. RCR Field Descriptions (continued)

Name

DRT

LOOP

Description

Disable receive on transmit.

0 Receive path operates independently of transmit (use for full duplex or to monitor transmit activity in half duplex mode).

1 Disable reception of frames while transmitting (normally used for half duplex mode).

Internal loopback. If set, transmitted frames are looped back internal to the device and the transmit output signals are not asserted. The system clock is substituted for the ETXCLK when LOOP is asserted. DRT must be set to zero when asserting LOOP.

18.5.4.10 Transmit Control Register (TCR)

The TCR is read/write and is written by the user to configure the transmit block. This register is cleared at system reset. Bits 2 and 1 should be modified only when ECR[ETHER_EN] = 0.

Field

Reset

R/W

31

Field

Reset

R/W

Address

15

16

—

0000_0000_0000_0000

R/W

—

R/W

5 4 3 2 1 0

RFC_PAUSE TFC_PAUSE FDEN HBC GTS

0000_0000_0000_0000

R

IPSBAR + 0x10C4

R/W

Figure 18-13. Transmit Control Register (TCR)




Bits

31–5

4

3

2

1

0

Table 18-22. TCR Field Descriptions



RFC_PAUSE Receive frame control pause. This read-only status bit will be asserted when a full duplex flow control pause frame has been received and the transmitter is paused for the duration defined in this pause frame. This bit will automatically clear when the pause duration is complete.

TFC_PAUSE Transmit frame control pause. Transmits a PAUSE frame when asserted. When this bit is set, the MAC will stop transmission of data frames after the current transmission is complete. At this time, the GRA interrupt in the EIR register will be asserted. With transmission of data frames stopped, the MAC will transmit a

MAC Control PAUSE frame. Next, the MAC will clear the

TFC_PAUSE bit and resume transmitting data frames. Note that if the transmitter is paused due to user assertion of GTS or reception of a PAUSE frame, the MAC may still transmit a MAC

Control PAUSE frame.

FDEN Full duplex enable. If set, frames are transmitted independent of carrier sense and collision inputs. This bit should only be modified when ETHER_EN is deasserted.

HBC

GTS

Heartbeat control. If set, the heartbeat check is performed following end of transmission and the HB bit in the status register will be set if the collision input does not assert within the heartbeat window. This bit should only be modified when

ETHER_EN is deasserted.

Graceful transmit stop. When this bit is set, the MAC will stop transmission after any frame that is currently being transmitted is complete and the GRA interrupt in the EIR register will be asserted. If frame transmission is not currently underway, the

GRA interrupt will be asserted immediately. Once transmission has completed, a “restart” can be accomplished by clearing the

GTS bit. The next frame in the transmit FIFO will then be transmitted. If an early collision occurs during transmission when

GTS = 1, transmission will stop after the collision. The frame will be transmitted again once GTS is cleared. Note that there may be old frames in the transmit FIFO that will be transmitted when

GTS is reasserted. To avoid this deassert ECR[ETHER_EN] following the GRA interrupt.

18.5.4.11 Physical Address Low Register (PALR)

The PALR is written by the user. This register contains the lower 32 bits (bytes 0,1,2,3) of the 48-bit address used in the address recognition process to compare with the DA (Destination Address) field of receive frames with an individual DA. In addition, this register is used in bytes 0 through 3 of the 6-byte source address field when transmitting PAUSE frames. This register is not reset and must be initialized by the user.

18-32




Field

Reset

R/W

31

Field

Reset

R/W

Address

15

Bits

31–0

PADDR1

Uninitialized

R/W

PADDR1

Uninitialized

R/W

IPSBAR + 0x10E4

Figure 18-14. Physical Address Low Register (PALR)

Table 18-23. PALR Field Descriptions

Name

PADDR1

Description

Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8) and 3 (bits

7:0) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames.

16

0

18.5.4.12 Physical Address High Register (PAUR)

The PAUR is written by the user. This register contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition process to compare with the DA (destination address) field of receive frames with an individual DA. In addition, this register is used in bytes 4 and 5 of the 6-byte Source

Address field when transmitting PAUSE frames. Bits 15:0 of PAUR contain a constant type field (0x8808) used for transmission of PAUSE frames. This register is not reset and bits 31:16 must be initialized by the user.

16

Field

Reset

R/W

31

Field

Reset

R/W

Address

15

PADDR2

Uninitialized

R/W

TYPE

1000_1000_0000_1000

R

IPSBAR + 0x10E8

Figure 18-15. Physical Address High Register (PAUR)

0




BIts

31–16

15–0

Table 18-24. PAUR Field Descriptions

Name

PADDR2

TYPE

Description

Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address to be used for exact match, and the Source Address field in PAUSE frames.

Type field in PAUSE frames. These 16-bits are a constant value of 0x8808.

18.5.4.13 Opcode/Pause Duration Register (OPD)

The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node detects a PAUSE frame, that node will pause transmission for the duration specified in the pause duration field. This register is not reset and must be initialized by the user.

31 16

Field

Reset

R/W

OPCODE

0000_0000_0000_0001

R

15 0

Field

Reset

R/W

Address

Bits

31–16

15–0

PAUSE_DUR

Uninitialized

R/W

IPSBAR + 0x10EC

Figure 18-16. Opcode/Pause Duration Register (OPD)

Table 18-25. OPD Field Descriptions

Name

OPCODE

PAUSE_DUR

Description

Opcode field used in PAUSE frames.

These bits are a constant, 0x0001.

Pause Duration field used in PAUSE frames.

18.5.4.14 Descriptor Individual Upper Address Register (IAUR)

The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user.

18-34




31

Field

Reset

R/W

IADDR1

Uninitialized

R/W

Field

Reset

R/W

Address

15

IADDR1

Uninitialized

R/W

IPSBAR + 0x1118

Figure 18-17. Descriptor Individual Upper Address Register (IAUR)

Bits

31–0

Table 18-26. IAUR Field Descriptions

Name

IADDR1

Descriptions

The upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR1 contains hash index bit

63. Bit 0 of IADDR1 contains hash index bit 32.

16

0

18.5.4.15 Descriptor Individual Lower Address (IALR)

The IALR register is written by the user. This register contains the lower 32 bits of the 64-bit individual address hash table used in the address recognition process to check for possible match with the DA field of receive frames with an individual DA. This register is not reset and must be initialized by the user.

31 16

Field

Reset

R/W

IADDR2

Uninitialized

R/W

15 0

Field

Reset

R/W

Address

IADDR2

Uninitialized

R/W

IPSBAR + 0x111C

Figure 18-18. Descriptor Individual Lower Address Register (IALR)




Bits

31–0

Table 18-27. IALR Field Descriptions

Name

IADDR2

Description

The lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a unicast address. Bit 31 of IADDR2 contains hash index bit

31. Bit 0 of IADDR2 contains hash index bit 0.

18.5.4.16 Descriptor Group Upper Address (GAUR)

The GAUR is written by the user. This register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user.

16 31

Field

Reset

R/W

GADDR1

Uninitialized

R/W

Field

Reset

R/W

Address

15

Bits

31–0

GADDR1

Uninitialized

R/W

IPSBAR + 0x1120

Figure 18-19. Descriptor Group Upper Address Register (GAUR)

Table 18-28. GAUR Field Descriptions

Name

GADDR1

Description

The GADDR1 register contains the upper 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR1 contains hash index bit 63. Bit 0 of GADDR1 contains hash index bit 32.

0

18.5.4.17 Descriptor Group Lower Address (GALR)

The GALR register is written by the user. This register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. This register must be initialized by the user.

18-36




31

Field

Reset

R/W

GADDR2

Uninitialized

R/W

Field

Reset

R/W

Address

15

Bits

31–0

GADDR2

Uninitialized

R/W

IPSBAR + 0x1124

Figure 18-20. Descriptor Group Lower Address Register (GALR)

Table 18-29. GALR Field Descriptions

Name

GADDR2

Description

The GADDR2 register contains the lower 32 bits of the 64-bit hash table used in the address recognition process for receive frames with a multicast address. Bit 31 of GADDR2 contains hash index bit 31. Bit 0 of GADDR2 contains hash index bit 0.

16

0

18.5.4.18 FIFO Transmit FIFO Watermark Register (TFWR)

The TFWR is a 2-bit read/write register programmed by the user to control the amount of data required in the transmit FIFO before transmission of a frame can begin. This allows the user to minimize transmit latency (TFWR = 0x) or allow for larger bus access latency (TFWR = 11) due to contention for the system bus. Setting the watermark to a high value will minimize the risk of transmit FIFO underrun due to contention for the system bus. The byte counts associated with the TFWR field may need to be modified to match a given system requirement (worst case bus access latency by the transmit data DMA channel).

31 16

Field

Reset

R/W

—

0000_0000_0000_0000

R/W

15 2 1 0

X_WMRK Field

Reset

R/W

Address

—

0000_0000_0000_0000

R/W

IPSBAR + 0x1144

Figure 18-21. FIFO Transmit FIFO Watermark Register (TFWR)




Bits

31–2

1–0

Table 18-30. TFWR Field Descriptions

Name

—

X_WMRK

Descriptions


Number of bytes written to transmit FIFO before transmission of a frame begins

0x 64 bytes written

10 128 bytes written

11 192 bytes written

18.5.4.19 FIFO Receive Bound Register (FRBR)

The FRBR is an 8-bit register that the user can read to determine the upper address bound of the FIFO

RAM. Drivers can use this value, along with the FRSR to appropriately divide the available FIFO RAM between the transmit and receive data paths.

31 16

Field

Reset

R/W

Field

Reset

R/W

Address

15

Bits

31–10

9–2

1–0

—

0000_0000_0000_0000

Read Only

—

10 9

R_BOUND

0000_0110_0000_0000

Read Only

IPSBAR + 0x114C

Figure 18-22. FIFO Receive Bound Register (FRBR)

Table 18-31. FRBR Field Descriptions

Name

—

R_BOUND

—

2

Descriptions

Reserved, read as 0 (except bit 10, which is read as 1).

Read-only. Highest valid FIFO RAM address.


1

—

0

18-38




18.5.4.20 FIFO Receive Start Register (FRSR)

The FRSR is an 8-bit register programmed by the user to indicate the starting address of the receive FIFO.

FRSR marks the boundary between the transmit and receive FIFOs. The transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.

The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default value.

31 16

Field

Reset

R/W

Field

Reset

R/W

Address

15

Bits

31–10

9–2

1–0

—

0000_0000_0000_0000

R/W

—

10 9

R_FSTART

0000_0101_0000_0000

R/W

IPSBAR + 0x1150

Figure 18-23. FIFO Receive Start Register (FRSR)

Table 18-32. FRSR Field Descriptions

Name

—

R_FSTART

—

2

Descriptions

Reserved, read as 0 (except bit 10, which is read as 1).

Address of first receive FIFO location. Acts as delimiter between receive and transmit FIFOs.

Reserved, read as 0.

1

—

0

18.5.4.21 Receive Descriptor Ring Start (ERDSR)

The ERDSR is written by the user. It provides a pointer to the start of the circular receive buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made

128-bit aligned (evenly divisible by 16).

This register is not reset and must be initialized by the user prior to operation.




31

Field

Reset

R/W

R_DES_START

Uninitialized

R/W

Field

Reset

R/W

Address

15

Bits

31–2

1–0

R_DES_START

Uninitialized

R/W

IPSBAR + 0x1180

Figure 18-24. Receive Descriptor Ring Start Register (ERDSR)

Table 18-33. ERDSR Field Descriptions

Name Descriptions

R_DES_START Pointer to start of receive buffer descriptor queue.


2

16

1

—

0

18.5.4.22 Transmit Buffer Descriptor Ring Start (ETSDR)

The ETSDR is written by the user. It provides a pointer to the start of the circular transmit buffer descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it be made

128-bit aligned (evenly divisible by 16). Bits 1 and 0 should be written to 0 by the user. Non-zero values in these two bit positions are ignored by the hardware.

This register is not reset and must be initialized by the user prior to operation.

16 31

Field

Reset

R/W

X_DES_START

Uninitialized

R/W

Field

Reset

R/W

Address

15

X_DES_START

Uninitialized

R/W

IPSBAR + 0x1184

Figure 18-25. Transmit Buffer Descriptor Ring Start Register (ETDSR)

2 1

—

0

18-40




Bits

31–2

1–0

Table 18-34. ETDSR Field Descriptions


X_DES_START Pointer to start of transmit buffer descriptor queue.


18.5.4.23 Receive Buffer Size Register (EMRBR)

The EMRBR is a 9-bit register programmed by the user. The EMRBR register dictates the maximum size of all receive buffers. Note that because receive frames will be truncated at 2k-1 bytes, only bits 10–4 are used. This value should take into consideration that the receive CRC is always written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to RCR[MAX_FL] or larger.

The EMRBR must be evenly divisible by 16. To insure this, bits 3-0 are forced low. To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater than or equal to 256 bytes.

The EMRBR register does not reset, and must be initialized by the user.

31 16

Field

Reset

R/W

Field

Reset

R/W

Address

15

Bits

30–11

10–4

3–0

—

Uninitialized

R/W

11 10 4

— R_BUF_SIZE

Uninitialized

R/W

IPSBAR + 0x11B8

Figure 18-26. Receive Buffer Size Register (EMRBR)

3

Table 18-35. EMRBR Field Descriptions


— Reserved, should be written to 0 by the host processor.

R_BUF_SIZE Receive buffer size.

— Reserved, should be written to 0 by the host processor.

—

0




18.6

Buffer Descriptors

This section provides a description of the operation of the driver/DMA via the buffer descriptors. It is followed by a detailed description of the receive and transmit descriptor fields.

18.6.1

Driver/DMA Operation with Buffer Descriptors

The data for the FEC frames must reside in memory external to the FEC. The data for a frame is placed in one or more buffers. Associated with each buffer is a buffer descriptor (BD) which contains a starting address (pointer), data length, and status/control information (which contains the current state for the buffer). To permit maximum user flexibility, the BDs are also located in external memory and are read in by the FEC DMA engine.

Software “produces” buffers by allocating/initializing memory and initializing buffer descriptors. Setting the RxBD[E] or TxBD[R] bit “produces” the buffer. Software writing to either the TDAR or RDAR tells the FEC that a buffer has been placed in external memory for the transmit or receive data traffic, respectively. The hardware reads the BDs and “consumes” the buffers after they have been produced. After the data DMA is complete and the buffer descriptor status bits have been written by the DMA engine, the

RxBD[E] or TxBD[R] bit will be cleared by hardware to signal the buffer has been “consumed.” Software may poll the BDs to detect when the buffers have been consumed or may rely on the buffer/frame interrupts. These buffers may then be processed by the driver and returned to the free list.

The ECR[ETHER_EN] signal operates as a reset to the BD/DMA logic. When ECR[ETHER_EN] is deasserted the DMA engine BD pointers are reset to point to the starting transmit and receive BDs. The buffer descriptors are not initialized by hardware during reset. At least one transmit and receive buffer descriptor must be initialized by software before the ECR[ETHER_EN] bit is set.

The buffer descriptors operate as two separate rings. ERDSR defines the starting address for receive BDs and ETDSR defines the starting address for transmit BDs. The last buffer descriptor in each ring is defined by the Wrap (W) bit. When set, W indicates that the next descriptor in the ring is at the location pointed to by ERDSR and ETDSR for the receive and transmit rings, respectively. Buffer descriptor rings must start on a 32-bit boundary; however, it is recommended they are made 128-bit aligned.

18.6.1.1

Driver/DMA Operation with Transmit BDs

Typically a transmit frame will be divided between multiple buffers. An example is to have an application payload in one buffer, TCP header in a 2nd buffer, IP header in a 3rd buffer, Ethernet/IEEE 802.3 header in a 4th buffer. The Ethernet MAC does not prepend the Ethernet header (destination address, source address, length/type field(s)), so this must be provided by the driver in one of the transmit buffers. The

Ethernet MAC can append the Ethernet CRC to the frame. Whether the CRC is appended by the MAC or by the driver is determined by the TC bit in the transmit BD which must be set by the driver.

The driver (TxBD software producer) should set up Tx BDs in such a way that a complete transmit frame is given to the hardware at once. If a transmit frame consists of three buffers, the BDs should be initialized with pointer, length and control (W, L, TC, ABC) and then the TxBD[R] bits should be set = 1 in reverse order (3rd, 2nd, 1st BD) to insure that the complete frame is ready in memory before the DMA begins. If the TxBDs are set up in order, the DMA Controller could DMA the first BD before the 2nd was made available, potentially causing a transmit FIFO underrun.

In the FEC, the DMA is notified by the driver that new transmit frame(s) are available by writing to the

TDAR register. When this register is written to (data value is not significant) the FEC RISC will tell the

DMA to read the next transmit BD in the ring. Once started, the RISC + DMA will continue to read and interpret transmit BDs in order and DMA the associated buffers, until a transmit BD is encountered with the R bit = 0. At this point the FEC will poll this BD one more time. If the R bit = 0 the second time, then

18-42



Buffer Descriptors the RISC will stop the transmit descriptor read process until software sets up another transmit frame and writes to TDAR.

When the DMA of each transmit buffer is complete, the DMA writes back to the BD to clear the R bit, indicating that the hardware consumer is finished with the buffer.

18.6.1.2

Driver/DMA Operation with Receive BDs

Unlike transmit, the length of the receive frame is unknown by the driver ahead of time. Therefore the driver must set a variable to define the length of all receive buffers. In the FEC, this variable is written to the EMRBR register.

The driver (RxBD software producer) should set up some number of “empty” buffers for the Ethernet by initializing the address field and the E and W bits of the associated receive BDs. The hardware (receive

DMA) will consume these buffers by filling them with data as frames are received and clearing the E bit and writing to the L (1 indicates last buffer in frame) bit, the frame status bits (if L = 1) and the length field.

If a receive frame spans multiple receive buffers, the L bit is only set for the last buffer in the frame. For non-last buffers, the length field in the receive BD will be written by the DMA (at the same time the E bit is cleared) with the default receive buffer length value. For end of frame buffers the receive BD will be written with L = 1 and information written to the status bits (M, BC, MC, LG, NO, CR, OV, TR). Some of the status bits are error indicators which, if set, indicate the receive frame should be discarded and not given to higher layers. The frame status/length information is written into the receive FIFO following the end of the frame (as a single 32-bit word) by the receive logic. The length field for the end of frame buffer will be written with the length of the entire frame, not just the length of the last buffer.

For simplicity the driver may assign the default receive buffer length to be large enough to contain an entire frame, keeping in mind that a malfunction on the network or out of spec implementation could result in giant frames. Frames of 2k (2048) bytes or larger are truncated by the FEC at 2047 bytes so software is guaranteed never to see a receive frame larger than 2047 bytes.

Similar to transmit, the FEC will poll the receive descriptor ring after the driver sets up receive BDs and writes to the RDAR register. As frames are received the FEC will fill receive buffers and update the associated BDs, then read the next BD in the receive descriptor ring. If the FEC reads a receive BD and finds the E bit = 0, it will poll this BD once more. If the BD = 0 a second time the FEC will stop reading receive BDs until the driver writes to RDAR.

18.6.2

Ethernet Receive Buffer Descriptor (RxBD)

In the RxBD, the user initializes the E and W bits in the first longword and the pointer in second longword.

When the buffer has been DMA’d, the Ethernet controller will modify the E, L, M, BC, MC, LG, NO, CR,

OV, and TR bits and write the length of the used portion of the buffer in the first longword. The M, BC,

MC, LG, NO, CR, OV and TR bits in the first longword of the buffer descriptor are only modified by the

Ethernet controller when the L bit is set.

Figure 18-27. Receive Buffer Descriptor (RxBD)




Offset + 0

15 14 13 12 11

E RO1 W RO2 L

10

—

Offset + 2

Offset + 4

Offset + 6

9

—

8

M

7 6 5 4 3 2 1 0

BC MC LG NO — CR OV TR

Data Length

Rx Data Buffer Pointer - A[31:16]

Rx Data Buffer Pointer - A[15:0]

Word

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Table 18-36. Receive Buffer Descriptor Field Definitions

Location

Bit 15

Bit 14

Bit 13

Bit 12

Bit 11

Bits 10–9

Bit 8

Bit 7

Bit 6

Field Name

E

RO1

W

RO2

L

—

M

BC

MC

Description

Empty. Written by the FEC (=0) and user (=1).

0 The data buffer associated with this BD has been filled with received data, or data reception has been aborted due to an error condition. The status and length fields have been updated as required.

1 The data buffer associated with this BD is empty, or reception is currently in progress.

Receive software ownership.

This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.

Wrap. Written by user.

0 The next buffer descriptor is found in the consecutive location

1 The next buffer descriptor is found at the location defined in

ERDSR.

Receive software ownership.

This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.

Last in frame. Written by the FEC.

0 The buffer is not the last in a frame.

1 The buffer is the last in a frame.

Reserved.

Miss. Written by the FEC. This bit is set by the FEC for frames that were accepted in promiscuous mode, but were flagged as a “miss” by the internal address recognition. Thus, while in promiscuous mode, the user can use the M-bit to quickly determine whether the frame was destined to this station. This bit is valid only if the L-bit is set and the PROM bit is set.

0 The frame was received because of an address recognition hit.

1 The frame was received because of promiscuous mode.

Will be set if the DA is broadcast (FF-FF-FF-FF-FF-FF).

Will be set if the DA is multicast and not BC.

18-44



Word

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 2

0ffset + 4


Table 18-36. Receive Buffer Descriptor Field Definitions (continued)

Location

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Bits [15:0]

Bits [15:0]

Field Name Description

LG

NO

Rx frame length violation. Written by the FEC. A frame length greater than RCR[MAX_FL] was recognized. This bit is valid only if the L-bit is set. The receive data is not altered in any way unless the length exceeds 2047 bytes.

Receive non-octet aligned frame. Written by the FEC. A frame that contained a number of bits not divisible by 8 was received, and the CRC check that occurred at the preceding byte boundary generated an error. This bit is valid only if the L-bit is set. If this bit is set the CR bit will not be set.

—

CR

OV

TR

Reserved.

Receive CRC error. Written by the FEC. This frame contains a

CRC error and is an integral number of octets in length. This bit is valid only if the L-bit is set.

Overrun. Written by the FEC. A receive FIFO overrun occurred during frame reception. If this bit is set, the other status bits, M,

LG, NO, CR, and CL lose their normal meaning and will be zero. This bit is valid only if the L-bit is set.

Will be set if the receive frame is truncated (frame length >

2047 bytes). If the TR bit is set the frame should be discarded and the other error bits should be ignored as they may be incorrect.

Data Length Data length. Written by the FEC. Data length is the number of octets written by the FEC into this BD’s data buffer if L = 0 (the value will be equal to EMRBR), or the length of the frame including CRC if L = 1. It is written by the FEC once as the BD is closed.

A[31:16] RX data buffer pointer, bits [31:16]

1

Offset + 6 Bits [15:0] A[15:0] RX data buffer pointer, bits [15:0]

1

The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC. This value is never modified by the

Ethernet controller.

NOTE

Whenever the software driver sets an E bit in one or more receive descriptors, the driver should follow that with a write to RDAR.

18.6.3

Ethernet Transmit Buffer Descriptor (TxBD)

Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.

The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first longword, and the buffer pointer in the second longword.

The FEC will set the R bit = 0 in the first longword of the BD when the buffer has been DMA’d. Status bits for the buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is



Fast Ethernet Controller (FEC) indicated via individual interrupt bits (error conditions) and in statistic counters in the MIB block. See

Section 18.5.3, “MIB Block Counters Memory Map


3 2 1 0

Offset + 0

15 14 13 12

R TO1 W TO2

11

L

Offset + 2

10 9

TC ABC

8 7

Data Length

6

Offset + 4

5

Tx Data Buffer Pointer - A[31:16]

Offset + 6

Tx Data Buffer Pointer - A[15:0]

4

Word

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Offset + 0

Figure 18-28. Transmit Buffer Descriptor (TxBD)

Table 18-37. Transmit Buffer Descriptor Field Definitions

Location

Bit 15

Bit 14

Bit 13

BIt 12

Bit 11

Bit 10

Bit 9

Bits [8:0]

Field Name

R

TO1

W

TO2

L

TC

ABC

—

Description

Ready. Written by the FEC and the user.

0 The data buffer associated with this BD is not ready for transmission. The user is free to manipulate this BD or its associated data buffer. The FEC clears this bit after the buffer has been transmitted or after an error condition is encountered.

1 The data buffer, which has been prepared for transmission by the user, has not been transmitted or is currently being transmitted. No fields of this BD may be written by the user once this bit is set.

Transmit software ownership. This field is reserved for software use. This read/write bit will not be modified by hardware, nor will its value affect hardware.

Wrap. Written by user.

0 The next buffer descriptor is found in the consecutive location

1 The next buffer descriptor is found at the location defined in

ETDSR.

Transmit software ownership. This field is reserved for use by software. This read/write bit will not be modified by hardware, nor will its value affect hardware.

Last in frame. Written by user.

0 The buffer is not the last in the transmit frame.

1 The buffer is the last in the transmit frame.

Tx CRC. Written by user (only valid if L = 1).

0 End transmission immediately after the last data byte.

1 Transmit the CRC sequence after the last data byte.

Append bad CRC. Written by user (only valid if L = 1).

0 No effect

1 Transmit the CRC sequence inverted after the last data byte

(regardless of TC value).

Reserved.

18-46




Table 18-37. Transmit Buffer Descriptor Field Definitions (continued)

Word Location Field Name Description

Offset + 2

Offset + 4

Bits [15:0]

Bits [15:0]

Data Length Data Length, written by user.

Data length is the number of octets the FEC should transmit from this BD’s data buffer. It is never modified by the FEC. Bits

[15:5] are used by the DMA engine, bits[4:0] are ignored.

A[31:16] Tx data buffer pointer, bits [31:16]

1

Offset + 6 Bits [15:0] A[15:0] Tx data buffer pointer, bits [15:0].

1

The transmit buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC. This value is never modified by the

Ethernet controller.

NOTE

Once the software driver has set up the buffers for a frame, it should set up the corresponding BDs. The last step in setting up the BDs for a transmit frame should be to set the R bit in the first BD for the frame. The driver should follow that with a write to TDAR which will trigger the FEC to poll the next BD in the ring.




18-48



Chapter 19


19.1

Introduction

The Ethernet physical transceiver (Ethernet physical interface) is an IEEE 802.3 compliant

10BASE-T/100BASE-TX Ethernet PHY transceiver. The Ethernet physical interface module supports both the medium-independent interface (MII) and the MII management interface. The EPHY requires a

25-MHz crystal for its basic operation.

19.1.1

Features

• IEEE 802.3 compliant

• Full-/half-duplex support in all modes

• Medium-independent interface (MII), which has these characteristics:

— Capable of supporting both 10 Mbps and 100 Mbps data rates

— Data and delimiters are synchronous to clock references

— Provides independent four-bit wide transmit and receive data paths

— Provides a simple management interface

• Supports auto-negotiation

• Auto-negotiation next page ability

• Single RJ45 connection

• 1:1 common transformer

• Baseline wander correction

• Digital adaptive equalization

• Integrated wave-shaping circuitry

• Far-end fault detect

• MDC rates up to 25 MHz

• Supports MDIO preamble suppression

• Jumbo packet

• 2.5 V CMOS

• 2.5 V MII interface

• 125 MHz clock generator and timing recovery

• Loopback modes



Preliminary

19-1


.

19.1.2

Block Diagram

PHY_TXP

PHY_TXN

PHY_RXP

PHY_RXN

PHY_RBIAS

PHY SUB BLOCK

IP BUS

REGISTERS

Figure 19-1. Ethernet Physical Transceiver (EPHY) Block Diagram

MII_RXCLK

MII_RXDV

MII_RXD[3:0]

MII_RXER

MII_TXCLK

MII_TXEN

MII_TXD[3:0]

MII_TXER

MII_CRS

MII_COL

MII_MDC

MII_MDIO

MII INTERFACE

IP BUS

SIGNALS

REF CLOCK

19-2



Preliminary


RXP

RXN

10BASE-T

RECEIVER

POLARITY CORRECTION

SQUELCH

LINK DETECT

CLOCK RECOVERY

MANCHESTER DECODE

TXP

100BASE-TX

LOOPBACK

TXN

RBIAS

100BASE-TX

RECEIVER

10BASE-T

DRIVER

100BASE-TX

DRIVER

VGA CONTROL

(COARSE EQUALIZER)

DIGITAL EQUALIZER

SLICER

TIMING CONTROL

BLW CONTROL

10BASE-T

DIG LOOP B

MLT-3 DECODE

DESCRAMBLER

AUTO

NEGOTIATE

4B/5B

DECODE

COLLISION

CARRIER SENSE

MANCHESTER ENCODER

DIGITAL WAVE SHAPING

100BASE-TX

DIG LOOP B

SCRAMBLER

MLT-3 ENCODE

4B / 5B

ENCODE

MII

LOOPBACK

MII

VOLTAGE/ CURRENT

REFERENCES

10BASE-T

PLL

100BASE-TX

PLL

REF

CLOCK

MANAGEMENT

(MII)

CONFIGURATION

REGISTERS

MDIO

Figure 19-2. PHY Sub Block Diagram

19.2


This section contains the EPHY external pin descriptions.

19.2.1

PHY_TXP — EPHY Twisted Pair Output +

Ethernet twisted-pair output pin. This pin is high-impedance out of reset.

19.2.2

PHY_TXN — EPHY Twisted Pair Output –

Ethernet twisted-pair output pin. This pin is high-impedance out of reset.

19.2.3

PHY_RXP — EPHY Twisted Pair Input +

Ethernet twisted-pair input pin. This pin is high-impedance out of reset.



Preliminary

19-3


19.2.4

PHY_RXN — EPHY Twisted Pair Input –

Ethernet twisted-pair input pin. This pin is high-impedance out of reset.

19.2.5

PHY_RBIAS — EPHY Bias Control Resistor

Connect a 1.0% external resistor, RBIAS (see Electrical Characteristics chapter), between the

PHY_RBIAS pin and analog ground. Place this resistor as near to the chip pin as possible. Stray capacitance must be kept to less than 10 pF (>50 pF will cause instability). No high-speed signals are permitted in the region of RBIAS.

19.2.6

PHY_VDDRX, PHY_VSSRX — Power Supply Pins for EPHY Receiver

Power is supplied to the EPHY receiver through PHY_VDDRX and PHY_VSSRX. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if V

DDR

is tied to ground.

19.2.7

PHY_VDDTX, PHY_VSSTX — Power Supply Pins for EPHY

Transmitter

External power is supplied to the EPHY transmitter through PHY_VDDTX and PHY_VSSTX. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if V

DDR

is tied to ground.

19.2.8

PHY_VDDA, PHY_VSSA — Power Supply Pins for EPHY Analog

Power is supplied to the EPHY PLLs through PHY_VDDA and PHY_VSSA. This 2.5 V supply is derived from the internal voltage regulator. There is no static load on those pins allowed. The internal voltage regulator is turned off, if V

DDR

is tied to ground.

19.2.9

COLLED — Collision LED

Flashes in half-duplex mode when a collision occurs on the network if EPHYCTL0 LEDEN bit is set.

19.2.10 DUPLED — Duplex LED

Indicates the duplex of the link, which can be full-duplex or half-duplex if EPHYCTL0 LEDEN bit is set.

19.2.11 SPDLED — Speed LED

Indicates the speed of a link, which can be 10 Mbps or 100 Mbps if EPHYCTL0 LEDEN bit is set.

19.2.12 LNKLED — Link LED

Indicates whether a link is established with another network device if EPHYCTL0 LEDEN bit is set.

19-4



Preliminary

Memory Map and Register Descriptions

19.2.13 ACTLEC — Activity LED

Flashes when data is received by the device if EPHYCTL0 LEDEN bit is set.

19.3


This section provides a detailed description of all registers accessible in the Ethernet physical interface.

19.3.1

Module Memory Map

Table 19-1

gives an overview of all registers in the Ethernet physical interface memory map. The Ethernet physical interface occupies 48 bytes in the memory space. The register address results from the addition of base address and address offset.

The base address is determined at the MCU level. The address offset is defined at the module level.

Table 19-1. EPHY Module Memory Map

Address

Offset

$__00

$__01

$__02

$__03

Use

Ethernet Physical Transceiver Control Register 0 (EPHYCTL0)

Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)

Ethernet Physical Transceiver Status Register (EPHYSR)

RESERVED

Access

R/W

R/W

R/W

R

19.3.2


19.3.2.1

Ethernet Physical Transceiver Control Register 0 (EPHYCTL0)

Module Base + $0x0000

7 6

R

W

RESET:

EPHYEN

0

ANDIS

1

5

DIS100

1

4

DIS10

1

3 2

LEDEN EPHYWAI

0 0

1

0

0

0

EPHYIEN

0


Figure 19-3. Ethernet Physical Transceiver Control Register 0 (EPHYCTL0)

Read: Anytime

Write: See each bit description

EPHYEN — EPHY Enable

This bit can be written anytime.

1 = Enables EPHY

0 = Disables EPHY



Preliminary

19-5


ANDIS — Auto Negotiation Disable

This bit can be written anytime, but the value is latched in the ANE bit of the MII PHY control register

(MII address 0.12) only when the EPHYEN bit transitions from 0 to 1.

1 = Auto negotiation is disabled after start-up. A 0 is latched in the ANE bit of the MII PHY control register (MII address 0.12), and upon completion of the start-up delay (t

Start-up

), the EPHY will bypass auto-negotiation. The mode of operation will be determined by the manual setting of

MII registers.

0 = Auto negotiation is enabled after start-up. A 1 is latched in the ANE bit of the MII PHY control register (MII address 0.12), and upon completion of the start-up delay (t

Start-up

), the EPHY will enter auto-negotiation. The mode of operation will be automatically determined.

DIS100 — Disable 100 BASE-TX PLL

This bit can be written anytime. Allows user to power down the clock generation PLL for

100BASE-TX clocks.

1 = Disables 100BASE-TX PLL

0 = 100BASE-TX PLL state determined by EPHY operation mode

DIS10 — Disable 10BASE-T PLL

This bit can be written anytime. Allows user to power down the clock generation PLL for 10BASE-T clocks.

1 = Disables 10BASE-T PLL

0 = 10 BASE-T PLL state determined by EPHY operation mode

LEDEN — LED Drive Enable


1 = Enables the EPHY to drive LED signals.

0 = Disables the EPHY to drive LED signals.

EPHYWAI — EPHY Module Stops While in Wait


1 = Disables the EPHY module while the MCU is in wait mode. EPHY interrupts cannot be used to bring the MCU out of wait.

0 = Allows the EPHY module to continue running during wait.

EPHYIEN — EPHY Interrupt Enable


1 = Enables EPHY module interrupts

0 = Disables EPHY module interrupts

19.3.2.2

Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)


7

0

R

W

RESET: 0

6

0

0

5

0

0

4 3 2 1 0

PHYADD4 PHYADD3 PHYADD2 PHYADD1 PHYADD0

0 0 0 0 0


Figure 19-4. Ethernet Physical Transceiver Control Register 1 (EPHYCTL1)

19-6



Preliminary


Read: Anytime

Write: See each bit description

PHYADD[4:0] — EPHY Address for MII Requests

These bits can be written anytime, but the EPHY address is latched to the MII PHY address register

(MII address 21.4:0) only when the EPHYEN bit transitions from 0 to 1. PHYADD4 is the MSB of the of the EPHY address.

19.3.2.3

Ethernet Physical Transceiver Status Register (EPHYSR)


7

0

R

W

RESET: 0

6

0

0

5

100DIS

1

4

10DIS

1

3

0

0

2

0

0

1

0

0

0

EPHYIF

0


Figure 19-5. Ethernet Physical Transceiver Status Register (EPHYSR)

Read: Anytime

Write: See bit descriptions

100DIS — EPHY Port 100BASE-TX mode status

This bit is not writable — read only. Output to indicate EPHY port Base100-TX mode status.

1 = EPHY port 100BASE-TX disabled

0 = EPHY port 100BASE-TX enabled

10DIS — EPHY Port 10BASE-T mode status

This bit is not writable. Output to indicate EPHY port 10BASE-T mode status.

1 = EPHY port 10BASE-T disabled

0 = EPHY port 10BASE-T enabled

EPHYIF — EPHY Interrupt Flag

EPHYIF indicates that interrupt conditions have occurred. To clear the interrupt flag, write a 1 to this bit after reading the interrupt control register via the MII management interface.

1 = EPHY interrupt has occurred

0 = EPHY interrupt has not occurred



Preliminary

19-7


12

13

14

15

8

9

10

11

16

17

18

6

7

4

5

2

3

0

1

19.3.3

MII Registers

Table 19-2

gives an overview of all registers in the Ethernet physical interface that are accessible via the

MII management interface. These registers are not part of the MCU memory map.

Table 19-2. MII Registers

Address

$0x0000

$0x0001

$0x0002

$0x0003

$0x0004

$0x0005

$0x0006

$0x0007

$0x0008

$0x0009

$0x000A

$0x000B

$0x000C

$0x000D

$0x000E

$0x000F

$0x0010

$0x0011

$0x0012

Use

Control Register

Status Register

PHY Identification Register 1

PHY Identification Register 2

Auto-Negotiation Advertisement Register

Auto-Negotiation Link Partner Ability Register

Auto-Negotiation Expansion Register

Auto-Negotiation Next Page Transmit

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

RESERVED

Interrupt Control Register

Proprietary Status Register

Proprietary Control Register

Access

Read/Write

Read/Write

4

Read/Write

4

Read/Write

4

Read/Write

Read/Write

4

Read/Write

4

Read/Write

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

1

Read/Write

Read/Write

4

Read/Write

1. Always read $00

2. Writable only in special modes (test_mode = 1)

4. Write has no effect.

NOTE

Bit notation for MII registers is: Bit 20.15 refers to MII register address 20 and bit number 15.

19.3.3.1

EPHY Control Register

MII Register Address 0 ($00000)

15 14 13 12

R

W

RESET:

11 10

RESET

0

LOOP

BACK

DATA

RATE

ANE PDWN ISOL

0 1 X 0


0

9

RAN

0

8

DPLX

1

7

COL

TEST

0

6

0

0

Figure 19-6. Control Register

Read: Anytime

Write: Anytime

5

0

0

4

0

0

3

0

0

2

0

0

1

0

0

0

0

0

19-8



Preliminary


RESET — EPHY Reset

Resetting a port is accomplished by setting this bit to 1.

1 = The PHY will reset the port’s status and registers to the default values. The PHY will also reset the PHY to its initial state. After the reset is complete, the PHY clears this bit automatically.

The reset process will be completed within 1.3 ms of this bit being set. While the preamble is suppressed, the management interface must not receive an ST within three MDC clock cycles following a software reset.

0 = No effect

LOOPBACK — Digital Loopback Mode

Determines Digital Loopback Mode

1 = Enables digital loopback mode. Port will be placed in loopback mode. Loopback mode will allow the TXD data to be sent to the RXD data circuitry within 512 bit times. The PHY will be isolated from the medium (no transmit or receive to the medium allowed) and the MII_COL signal will remain de-asserted, unless this bit is set.

0 = Disables digital loopback mode

DATARATE — Speed Selection

The link speed will be selected either through the auto-negotiation process or by manual speed selection. ANE allows manual speed selection while it is set to 0. While auto-negotiation is enabled,

DATARATE can be read or written but its value is not required to reflect speed of the link.

1 = While auto-negotiation is disabled, selects 100 Mbps operation

0 = While auto-negotiation is disabled, selects 10 Mbps operation

ANE — Auto-Negotiation Enable

The ANE bit determines whether the A/N process is enabled. When auto-negotiation is disabled,

DATARATE and DPLX determine the link configuration. While auto-negotiation is enabled, bits

DATARATE and DPLX do not affect the link.

1 = Enables auto-negotiation

0 = Disables auto-negotiation

PDWN — Power Down

When this bit is set, the port is placed in a low power consumption mode.

1 = Port is placed in a low power consumption mode. Normal operation will be allowed within 0.5 s after PDWN and ISOL are changed to 0. During a transition to power-down mode (or if already in power down mode), the port will respond only to management function requests through the

MI interface. All other port operations will be disabled. When power-down mode is exited, all register values are maintained. The port will start its operation based on the register values.

0 = Normal operation

ISOL — Isolate

1 = Isolates the port’s data path signals from the MII. The port will not respond to changes on

MII_TXDx, MII_TXEN, and MII_TXER inputs, and it will present high impedance on

MII_TXCLK, MII_RXCLK, MII_RXDV, MII_RXER, MII_RXDx, MII_COL, and MII_CRS outputs. The port will respond to management transactions while in isolate mode.




Preliminary

19-9


RAN — Restart Auto-Negotiation

The RAN bit determines when the A/N process can start processing.

1 = When auto-negotiation is enabled (ANE=1), the auto-negotiation process will be restarted.

After auto-negotiation indicates that it has been initialized, this bit is cleared. When bit ANE is cleared to indicate auto-negotiation is disabled, RAN must also be 0.

0 = Normal operation.

DPLX — Duplex Mode

This mode can be selected by either the auto-negotiation process or manual duplex selection. Manual duplex selection is allowed only while the auto-negotiation process is disabled (ANE=0). While the auto-negotiation process is enabled (ANE = 1), the state of DPLX has no effect on the link configuration. While loopback mode is asserted (LOOPBACK =1), the value of DPLX will have no effect on the PHY.

1 = Indicates full-duplex mode

0 = Indicates half-duplex mode

COLTEST — Collision Test

The collision test function will be enabled only if the loopback mode of operation is also selected

(LOOPBACK = 1).

1 = Forces the PHY to assert the MII_COL signal within 512 bit times from the assertion of

MII_TXEN and de-assert MII_COL within 4 bit times of MII_TXEN being de-asserted.


19.3.3.2

Status Register

This register advertises the capabilities of the port to the MII.

MII Register Address 1 (%00001)

15

R

100

T4

W

RESET: 0

14

100X

FD

1

13

100X

HD

1

12

10T

FD

1

11

10T

HD

1

10

0

0

9

0

0

8

0

0

7

0

0

6

SUP

PRE

5

AN

COMP

4

REM

FLT

3

AN

ABL

2

LNK

STST

1

JAB

DT

1 0 0 1 0 0

0

EX

CAP

1


Figure 19-7. Status Register

Read: Anytime

Write: Writes have no effect

100T4 —100BASE-T4

1 = Indicates PHY supports 100BASE-T4 transmission

0 = Indicates the PHY does not support 100BASE-T4 transmission

This function is not implemented in the EPHY module.

100XFD —100BASE-TX Full-Duplex

1 = Indicates PHY supports 100BASE-TX full-duplex mode

0 = Indicates PHY does not support 100BASE-TX full-duplex mode

19-10



Preliminary


100XHD —100BASE-TX Half-Duplex

1 = Indicates the PHY supports 100BASE-TX half-duplex mode

0 = Indicates the PHY does not support 100BASE-TX half-duplex mode

10TFD —10BASE-T Full-Duplex

1 = Indicates the PHY supports 10BASE-T full-duplex mode

0 = Indicates the PHY does not support 10BASE-T full-duplex mode

10THD —10BASE-T Half-Duplex

1 = Indicates the PHY supports 10BASE-T half-duplex mode

0 = Indicates the PHY does not support 10BASE-T half-duplex mode

SUPPRE —MF Preamble Suppression

1 = Indicates that management frames are not required to contain the preamble stream

0 = Indicates that management frames are required to contain the preamble stream

ANCOMP —Auto-Negotiation Complete

To inform the management interface (MI) that it has completed processing, ANCOMP is set by the

A/N process. After it has been started, the auto-negotiation process uses link code words to exchange capability information and establish the highest common denominator (HCD) for link transactions.

1 = Indicates that the auto-negotiation process has completed and that the contents of registers 4 through 7 are valid.

0 = Indicates that the auto-negotiation process has not completed and that the contents of registers

4 through 7 are not valid

REMFLT — Remote Fault

Possible remote faults (RF) a) The link partner transmits the RF bit (5.13=1) b) Link partner protocol is not 00001 (5.4:0) c) Link partner advertises only T4 capability (5.9:5) d) No common operation mode found between PHY and the link partner.

After it is set, REMFLT is cleared each time register 1 is read via the management interface. REMFLT is also cleared by a PHY reset.

1 = Indicates that a remote fault condition has been detected.

0 = No fault detected

ANABL — Auto-Negotiation Ability

1 = Indicates that PHY has auto-negotiation ability

0 = Indicates that PHY does not have auto-negotiation ability

LNKSTST — Link Status

The PHY sets this bit when it determines that a valid link has been established. The occurrence of a link failure will cause LNKSTST to be cleared. After it has been cleared, it remains cleared until it is read via the management interface.

1 = Indicates a valid link has been established

0 = Indicates a valid link has NOT been established



Preliminary

19-11


JABDT —Jabber Detect

After it is set, JABDT is cleared each time register 1 is read via the management interface. JABDT is also cleared by a PHY reset. For 100BASE-TX operation, this signal will always be cleared.

1 = Indicates that a jabber condition has been detected

0 = Indicates that no jabber condition has been detected

EXCAP — Extended capability

1 = Indicates that the extended register set (registers 2–31) has been implemented in the PHY.

0 = Indicates that the extended register set (registers 2–31) has NOT been implemented in the PHY

19.3.3.3

EPHY Identifier Register 1

Registers $_02 and $_03 provide the PHY identification code.

MII Register Address 2 ($0x0002)

15

R

W

RESET: 0

14

0

13

0

12

0

11

01

10

0

9

0

8

PHYID

7

0 0

6

0


Figure 19-8. EPHY Identifier Register 1

Read: Anytime

Write: Writes have no effect — Read only

PHYID — PHY ID Number

Composed of bits 3:18 of the organization unique identifier (OUI).

5

1

4

0

3

1

2

1

1

0

0

0

19.3.3.4

EPHY Identifier Register 2

Registers $_02 and $_03 provide the PHY identification code.


15 14 13

PHYID

12

R

W

RESET: 0

11 10 9 8 7 6

MODELNUMBER

5

0 0 0 0


0 0 0 0 0

Figure 19-9. EPHY Identifier Register 2

0

4

1

Read: Anytime

Write: Writes have no effect — Read only

PHYID — PHY ID number organization unique identifier. Composed of bits 15:10.

MODELNUMBER — Manufacturers model number. Composed of bits 9:4.

REVISIONNUMBER — Manufacturers revision number. Composed of bits 3:0.

3 2 1

REVISIONNUMBER

0

0 0 0 1

19-12



Preliminary


19.3.3.5

Auto-Negotiate (A/N) Advertisement Register

The auto-negotiation (A/N) process requires four registers to communicate link information with its link partner: A/N advertisement register (MII register 4), A/N link partner ability register (MII register 5), A/N expansion register (MII register 6), and the A/N next page transmit register (MII register 7).

Figure 19-10

shows the contents of the A/N advertisement register. On power-up, before A/N starts, the register sets the selector field, bits 4.4:0, to 00001 to indicate that it is IEEE Standard 802.3 compliant. The technology ability fields (4.9:5) are set according to the values in the MII status register (1.15:11). The MI can set the technology ability field bits before renegotiations to allow management to auto-negotiate to an alternate common mode.


R

W

RESET:

15

NXTP

1

14

0

0

13

RFLT

0

12

0

0

11

0

0

10

FLCTL

0

9

0

0

8

TAF

100FD

1

7

TAF

100HD

1

6

TAF

10FD

1

5

TAF

10HD

1

4

0

3 2 1

SELECTORFIELD[4:0]

0 0 0

0

1


Figure 19-10. Auto Negotiate Advertisement Register

Read: Anytime

Write: Never

NXTP — Next Page

1 = Capable of sending next pages

0 = Not capable of sending next pages

RFLT — Remote Fault

1 = Remote fault

0 = No remote fault

FLCTL — Flow Control

1 = Advertise implementation of the optional MAC control sublayer and pause function as specified in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect except to set the corresponding bit in the FLP stream

0 = No MAC-based flow control

TAF100FD — 100BASE-TX Full-Duplex

1 = 100BASE-TX full -duplex capable

0 = Not 100BASE-TX full-duplex capable

TAF100HD — 100BASE-TX Half-Duplex

1 = 100BASE-TX half-duplex capable

0 = Not 100BASE-TX half-duplex capable

TAF10FD — 10BASE-T Full-Duplex

1 = 10BASE-T full-duplex capable

0 = Not 10BASE-T full-duplex capable



Preliminary

19-13


TAF10HD — 10BASE-T Half-Duplex

1 = 10BASE-T half-duplex capable

0 = Not 10BASE-T half-duplex capable

19.3.3.6

Auto Negotiation Link Partner Ability (Base Page)

Figure 19-11 shows the contents of the A/N link partner ability register. The register can only be read by

the MI and will be written by the auto-negotiation process when it receives a link code word advertising the capabilities of the link partner. This register has a dual purpose: exchange of base page information as shown in

Figure 19-11 , and exchange of next page information as shown in

Figure 19-12

.

MII Register Address 5 ($0x0005) (Base Page)

15 14 13 12 11 10

R

W

RESET:

NXTP

X

ACK RFLT TAF[1:0] FCTL

X X X X


X

9

TAF

100T4

X

8

TAF

100FD

7

TAF

100HD

X X

6

TAF

10FD

X

5

TAF

10HD

X

4

X

3 2 1

SELECTORFIELD[4:0]

X

Figure 19-11. Auto Negotiation Link Partner Ability Register (Base Page)

X X

0

X

Read:

Write:

NXTP — Next Page

1 = Link partner capable of sending next pages

0 = Link partner not capable of sending next pages

ACK — Acknowledge

1 = Link Partner has received link code word

0 = Link Partner has not received link code word

RFLT — Remote Fault

1 = Remote fault

0 = No remote fault

FLCTL — Flow Control

1 = Advertises implementation of the optional MAC control sublayer and pause function as specified in IEEE standard clause 31 and anex 31B of 802.3. Setting FLCTL has no effect on the PHY.

0 = No MAC-based flow control

TAF100T4 — 100BASE-T4 Full-Duplex

1 = Link partner is 100BASE-T4 capable

0 = Link partner is not 100BASE-T4 capable

This function is not implemented in the EPHY.

TAF100FD — 100BASE-TX Full-Duplex

1 = Link partner is 100BASE-TX full-duplex capable

0 = Link partner is not 100BASE-TX full-duplex capable

19-14



Preliminary


TAF100HD — 100BASE-TX Half-Duplex

1 = Link partner is 100BASE-TX half-duplex capable

0 = Link partner is not 100BASE-TX half-duplex capable

TAF10FD — 10BASE-T Full-Duplex

1 = Link partner is10BASE-T full-duplex capable

0 = Link partner is not 10BASE-T full-duplex capable

TAF10HD — 10BASE-T Half-Duplex

1 = Link partner is 10BASE-T half-duplex capable

0 = Link partner is not 10BASE-T half-duplex capable

19.3.3.7

Auto Negotiation Link Partner Ability (Next Page)

MII Register Address 5 ($0x0005) (Next Page)

R

W

RESET:

15

NXTP

X

14 13 12

ACK MSGP ACK2

11

TGL

10

X X X X


X

9

X

8

X

7 6 5 4 3

Message/Unformatted Code Field [10:0]

X X X X X

Figure 19-12. Auto Negotiation Link Partner Ability Register (Next Page)

2

X

1

X

0

X

Read: Anytime

Write: See each field description

NXTP — Next Page

1 = Additional next pages will follow

0 = Last page transmitted

ACK — Acknowledge

ACK is used to acknowledge receipt of information.

1 = Link partner has received link code word

0 = Link partner has not received link code word

MSGP — Message Page

1 = Message page

0 = Unformatted page

ACK2 — Acknowledge 2

ACK2 is used to indicate that the receiver is able to act on the information (or perform the task) defined in the message.

1 = Receiver is able to perform the task defined in the message

0 = Receiver is unable to perform the task defined in the message

TGL — Toggle

1 = Previous value of the transmitted link code word equalled 0




Preliminary

19-15


Message/Unformatted Code Field

Message code field — Predefined code fields defined in IEEE 802.3u-1995 Annex 28C

Unformatted code filed — 11-bit field containing an arbitrary value

19.3.3.8

Auto-Negotiation Expansion Register

Figure 19-13

shows the contents of the A/N expansion register. The MI process can only read this register.

This register contains information about the A/N capabilities of the port’s link partner and information on the status of the parallel detection mechanism.


R

W

RESET:

15

0

0

14

0

13

0

12

0

11

0

10

0

0 0 0 0


0

9

0

0

8

0

0

7

0

0

6

0

0

5

0

0

4 3 2 1 0

PDFLT LPNPA NXTPA PRCVD LPANA

Figure 19-13. Auto-Negotiation Expansion Register

0 0 1 0 0

Read: Anytime

Write: Never

PDFLT — Parallel Detection Fault

This bit is used to indicate that zero or more than one of the NLP receive link integrity test function for

100BASE-TX have indicated that the link is ready (link_status=READY) when the A/N wait timer has expired. PDFLT will be reset to 0 after a read of register 6.

1 = Parallel detection fault has occurred

0 = Parallel detection fault has not occurred

LPNPA — Link Partner Next Page Able

Bit to indicate whether the link partner has the capability of using NP.

1 = Link partner is next page able

0 = Link partner is not next page able

NXTPA — Next Page Able

This bit is used to inform the MI and the link partner whether the port has next page capabilities.

1 = The port has next page capabilities

0 = The port does not have next page capabilities

PRCVD — Page Received

Bit is used to indicate whether a new link code word has been received and stored in the A/N link partner ability register (MII register 5). PRCVD is reset to 0 after register 6 is read.

1 = Three identical and consecutive link code words have been received from link partner

0 = Three identical and consecutive link code words have not been received from link partner

19-16



Preliminary


LPANA — Link Partner A/N Able

Indicates whether the link partner has A/N capabilities.

1 = Link partner is A/N able

0 = Link partner is not A/N able

19.3.3.9

Auto Negotiation Next Page Transmit

Figure 19-14

shows the contents of the A/N next page transmit register. The MI writes to this register if it needs to exchange more information with the link partner. The PHY defaults to sending only a NULL message page to the link partner unless the STA overrides the values in the register. Next pages will be transmitted until the link partner has no more pages to transmit and bit 7.15 has been cleared by the STA.


15 14

0

13 12

R

W

RESET:

NXTP

0 0

MSGP ACK2

1 0

11

TGL

0

10

0

9

0

8

0

7 6 5 4 3

Message/Unformatted Code Field [10:0]

0 0 0 0 0

2

0

1

0

0

1


Figure 19-14. Auto Negotiation Next Page Transmit Register

Read: Anytime

Write: Never

NXTP — Next Page

1 = Additional next pages will follow

0 = Last page to transmit

MSGP — Message Page

1 = Message page

0 = Unformatted page

ACK2 — Acknowledge 2

ACK2 is used to indicate that the receiver is able to act on the information (or perform the task) defined in the message.

1 = Receiver is able to perform the task defined in the message

0 = Receiver is unable to perform the task defined in the message

TGL — Toggle



Message/Unformatted Code Field

Message code field — Predefined code fields defined in IEEE 802.3u-1995 Annex 28C

Unformatted code field — Eleven bit field containing an arbitrary value



Preliminary

19-17


19.3.4

PHY-Specific Registers

PHY also contains a number of registers to set its internal mode of operation. These registers can be set through the external management interface to determine capabilities such as speed, test-mode, circuit bypass mode, interrupt setting, etc. The PHY register set includes registers 16 through 29. These registers are not part of the MCU memory map.

19.3.4.1

Interrupt Control Register


15

0

14 13 12

R

W

RESET: 0

ACKIE PRIE

0 0

LCIE

0

11

ANIE PDFIE RFIE JABIE

0

10

0

9

0

8

0

7

0

0

6 5

ACKR PGR

4

LKC

3

ANC

2

PDF

1 0

RMTF JABI

0 0 0 0 0 0 0


Figure 19-15. Interrupt Control Register

Read: Anytime

Write: Anytime

ACKIE — Acknowledge Bit Received Interrupt Enable

1 = Enable interrupt when the acknowledge bit is received from the link partner

0 = Disable interrupt when acknowledge bit is received

PRIE — Page Received INT Enable

1 = Enable interrupt when a new page is received

0 = Disable interrupt when a page is received

LCIE — Link Changed Enable

1 = Enable interrupt when the link status changes

0 = Disable interrupt when the link status changes

ANIE — Auto-Negotiation Changed Enable

1 = Enable interrupt when the state of the auto-negotiation state machine has changed since the last access of this register

0 = Disable interrupt when the state of the auto-negotiation state machine has changed since the last access of this register

PDFIE — Parallel Detect Fault Enable

1 = Enable interrupt on a parallel detect fault

0 = Disable interrupt on a parallel detect fault

RFIE — Remote Fault Interrupt Enable

1 = Enable interrupt on a parallel detect fault

0 = Disable interrupt on a parallel detect fault

JABIE — Jabber Interrupt Enable

1 = Enable setting interrupt on detection of a jabber condition

0 = Disable setting interrupt on detection of a jabber condition

19-18



Preliminary


ACKR — Acknowledge Bit Received

1 = Acknowledge bit has been received from the link partner

0 = Acknowledge bit has not been received since the last access of this register. (ACK bit 14 of the auto-negotiation link partner ability register was set by receipt of link code word)

PGR — Page Received

1 = A new page has been received from the link partner

0 = A new page has not been received from the link partner since the last access of this register (Bit

1 was set by a page received event)

LKC — Link Changed

1 = The link status has changed since the last access of this register

0 = The link status has not changed since the last access of this register. (LNK bit 14 of the proprietary status register was changed)

ANC — Auto-Negotiation Changed

1 = The auto-negotiation status has changed since the last access of this register

0 = The auto-negotiation status has not changed since the last access of this register

PDF — Parallel Detect Fault

1 = A parallel-detect fault has occurred since the last access of this register

0 = A parallel-detect fault has not been detected since the last access of this register. (Bit 4 was set by rising edge of parallel detection fault)

RMTF — Remote Fault

1 = A remote fault condition has been detected since the last access of this register

0 = A remote fault condition has not been detected since the last access of this register. (RMTF bit 4 of the status register was set by rising edge of a remote fault)

JABI — Jabber Interrupt

1 = A jabber condition has been detected since the last access of this register

0 = A jabber condition has not been detected since the last access of this register (JABD bit 1 of the status register was set by rising edge of jabber condition)

19.3.4.2

Proprietary Status Register


15 14 13 12 11

R

W

RESET:

0

0

LNK DPMD SPD 0

10 9

ANNC PRCVD

8

ANC

MODE

7

0

6

0

5

PLR

1 1 1 0


0 0 (1) 0 0 0

Figure 19-16. Proprietary Status Register

Read: Anytime

Write:

4

0

0

3

0

0

2

0

0

1

0

0

0

0

0



Preliminary

19-19


LNK — Link Status

This is a duplicate of LNKSTAT bit 2 of the status register (1.2).

1 = Link is down

0 = Link is up

DPMD — Duplex Mode

1 = Full-duplex

0 = Half-duplex

SPD — Speed

1 = 100 Mbps

0 = 10 Mbps

ANNC — Auto-Negotiation Complete

This is a duplicate of ANCOMP bit 5 of the status register (1.5)

1 = A-N complete

0 = A-N not complete

PRCVD — Page Received

1 = Three identical and consecutive link code words have been received

0 = Three identical and consecutive link code words have not been received

ANCMODE — Auto-Negotiation (A-N) Common Operating Mode

This bit is only valid while the ANNC bit 10 is 1

1 = A common operation mode was not found

0 = A-N is complete and a common operation mode has been found

PLR — Polarity Reversed (10BASE-T)

1 = 10BASE-T receive polarity is reversed

0 = 10BASE-T receive polarity is normal

19.3.4.3

Proprietary Control Register


R

W

RESET:

15

0

0

14

FE

FLTD

0

13

MIILBD

1

12

0

0

11

1

1

10

JBDE

1

9

LNK

TSTD

0

8

POL

CORD

0

7

ALGD

0

6

ENC

BYP

0

5

SCR

BYP

0

4

TRD

ANALB

0

3

TR

TST

0

2

0

0


Figure 19-17. Proprietary Control Register

The miscellaneous (EMISC) register provides visibility of internal counters used by the EMAC.

Read: Anytime

Write: Anytime

1

0

0

0

0

0

19-20



Preliminary


FEFLTD — Far End Fault Disable

1 = Far end fault detect is disabled

0 = Far end fault detect on receive and transmit is enabled. This applies only while auto-negotiation is disabled

MIILBO — MII Loopback Disable

1 = Disable MII loopback

0 = MII transmit data is looped back to the MII receive pins

JBDE — Jabber Detect Enable (10BASE-T)

1 = Enable jabber detection

0 = Disable jabber detection

LNKTSTD — Link Test Disable (10BASE-T)

1 = Disable 10BASE-T link integrity test

0 = 10BASE-T link integrity test enabled

POLCORD — Disable Polarity Correction (10BASE-T)

1 = 10BASE-T receive polarity correction is disabled

0 = 10BASE-T receive polarity is automatically corrected

ALGD — Disable Alignment

1 = Un-aligned mode. Available only in symbol mode

0 = Aligned mode

ENCBYP — Encoder Bypass

1 = Symbol mode and bypass 4B/5B encoder and decoder

0 = Normal mode

SCRBYP — Scrambler Bypass Mode (100BASE-TX)

1 = Bypass the scrambler and de-scrambler

0 = Normal

TRDANALB — Transmit and Receive Disconnect and Analog Loopback

1 = High-impedance twisted pair transmitter. Analog loopback mode overrides and forces this bit


TRTST — Transmit and Receive Test (100BASE-TX)

1 = Transmit and receive data regardless of link status


19.4


The Ethernet physical interface is an IEEE 802.3 compliant 10/100 Ethernet physical transceiver. The

Ethernet physical interface can be configured to support 10BASE-T or 100BASE-TX applications. The

Ethernet physical interface is configurable via internal registers which are accessible through the MII management interface as well as limited configurability using the EPHY register map.

There are five basic modes of operation for the EPHY:

• Power down/initialization

• Auto-negotiate



Preliminary

19-21


• 10BASE-T

• 100BASE-TX

• Low-power

19.4.1

Power Down/Initialization

Upon reset, the EPHYEN bit, in the Ethernet physical transceiver control register 0 (EPHYCTL0), is cleared and EPHY is in its lowest power consumption state. All analog circuits are powered down. The twisted-pair transmitter and receiver pins (PHY_TXP, PHY_TXN, PHY_RXP, and PHY_RXN) are high-impedance. The MII management interface is not accessible. All MII registers are initialized to their reset state. The ANDIS, DIS100, and DIS10 bits, in the EPHYCTL0 register, have no effect until the

EPHYEN bit is set.

The EPHYEN bit can be set or cleared by a register write at any time. Prior to enabling the EPHY, setting

EPHYEN to 1, the MII PHY address PHYADD[4:0] must be set in the Ethernet physical transceiver control register 1 (EPHYCTL1), and the ANDIS, DIS100, DIS10 bits, in the EPHYCTL0 register, must be configured for the desired start-up operation. Whenever the EPHYEN bit transitions from 0 to 1, MDIO communications must be delayed until the completion of a start-up delay period (t

Start-up

Figure 19-19

).

, see

19-22



Preliminary

RESET or EPHYEN=0

Set PHYADD[4:0], and

ANDIS, DIS100, DIS10

Set EPHYEN=1

PHYADD[4:0] and ANDIS become latched in MII registers

Delay for t

Start-up

Configure MII registers via MDIO

Initialization Complete

Figure 19-18. EPHY Start-Up / Initialization Sequence


EPHYEN

MDIO t

Start-up

Figure 19-19. EPHY Start-Up Delay



Preliminary

19-23


If the auto-negotiation mode of operation is desired, the ANDIS bit in the EPHYCTL0 must be set to 0 and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. Refer to

Section 19.4.2,

“Auto-Negotiation,”

for more information on auto-negotiation operation.

If the mode of operation will be set manually, the ANDIS bit must be set to 1 in the EPHYCTL0 register and the DIS100 and DIS10 bits must be cleared prior to setting EPHYEN to 1. After the EPHYEN bit has been set and the start-up delay period is completed, the mode of operation can be configured through the

MII registers. Table 19-3 summarizes the MII register configuration and operational modes.

Table 19-3. Operational Configuration While Auto-Negotiation is Disabled

1

Bit 0.12

Auto

Neg.

0

0

0

0

0

0

0

Bit 0.13

Data

Rate

1

1

0

0

1

1

1

Bit 0.8

Duplex

1

1

1

0

1

1

1

0 1 0

1

Symbol mode is not supported.

Bit 18.6

Encoder

Bypass

0

1

X

X

Bit 18.5

Scrambler

Bypass

0

0

X

X

1

1

1

0

0

1

1

0

Bit 18.7

Symbol

Unalign

0

0

X

X

1

0

1

0

Operation

10BASE-T full-duplex

10BASE-T half-duplex

100BASE-TX full-duplex

100BASE-TX full-duplex with encoder bypass (symbol mode) — aligned

100BASE-TX full-duplex with encoder bypass (symbol mode) — unaligned

100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), aligned

100BASE-TX full-duplex with scrambler and encoder bypassed (symbol mode), unaligned

100BASE-TX half-duplex

19.4.2

Auto-Negotiation

Auto-negotiation is used to determine the capabilities of the link partner. Auto-negotiation is compliant with IEEE 802.3 clause 28. In this case, the PHY will transmit fast link pulse (FLP) bursts to share its capabilities with the link partner.

If the link partner is also capable of performing auto-negotiation, it will also send FLP bursts. The information shared through the FLP bursts will allow both link partners to find the highest common mode

(if it exists).

If no common mode is found, the remote fault bit (1.4) will be set. A remote fault is defined as a condition in which the PHY and the link partner cannot establish a common operating mode. Configuring auto-negotiation advertisement register sets the different auto-negotiation advertisement modes.

If the link partner does not support auto-negotiation, it will transmit either normal link pulses (NLP) for

10 Mbps operation, or 100 Mbps idle symbols. Based on the received signal, the PHY determines whether the link partner is 10 Mbps capable or 100 Mbps capable. The ability to do this is called parallel detection.

If using parallel detection, the link will be configured as a half-duplex link. After parallel detection has established the link configuration, the remote fault bit will be set if the operating mode does not match the pre-set operating modes.

19-24



Preliminary


Figure 19-20

shows the main blocks used in the auto-negotiation function. The transmit block allows transmission of fast link pulses to establish communications with partners that are auto-negotiation able.

The receive block determines the capabilities of the link partner and writes to the link partner ability register (register 5). The arbitration block determines the highest common mode of operation to establish the link.

MR_ADV_ABILITY[15:0] MR_PARALLEL_DETECTION_FAULT

MR_AUTONEG_COMPLETE

MR_ADV_ABILITY[3:0]

MR_LP_ADV_ABILITY[15:0]

MR_LP_ADV_ABILITY[3:0]

CLK

POWER_ON

MR_MAIN_RESET

MR_AUTONEG_ENABLE

TRANSMIT complete_ack transmit_ability transmit_ack transmit_disable flp_link_good ack_finished

ARBITRATION flp_receive_idle match_wo_ack match_w_ack receive_done flp_link_good

RECEIVE

1

2

1 LP_LINK_CONTROL[1:0]

2 LP_LINK_STATUS[1:0]

NLP RECEIVE LINK

INTEGRITY TEST

TD_AUTONEG TX_LINK_CONTROL[1:0]

TX_LINK_STATUS[1:0]

DO RD

LINK_TEST_RECEIVE

Figure 19-20. Auto-Negotiation

LINKPULSE

19.4.3

10BASE-T

The 10BASE-T interface implements the physical layer specification for a 10 Mbps over two pairs of twisted-pair cables. The specifications are given in clause 14 of the IEEE 802.3 standard.

In 10BASE-T mode, Manchester encoding is used. When transmitting, nibbles from the MII are converted to a serial bit stream and then Manchester encoded. When receiving, the Manchester encoded bit stream is decoded and converted to nibbles for presentation to the MII.



Preliminary

19-25


A 2.5 MHz internal clock is used for nibble wide transactions. A 10 MHz internal clock is used for serial transactions.

TX

MII

PARALLEL

TO

SERIAL

MANCHESTER

ENCODER

DIGITAL

FILTER

PHY_TXN

PHY_TXP

CARRIER

SENSE JABBER

DIGITAL

LOOPBACK

(bit 0.14)

LINE TRANSMITTER/

LINE RECEIVER

RX

MII

SERIAL

TO

PARALLEL

MANCHESTER

DECODER

AND

TIMING

RECOVERY

POLARITY

CHECK

SQUELCH

Figure 19-21. 10BASE-T Block Diagram

PHY_RXN

PHY_RXP

Parallel to Serial: Converts the 4-bit wide nibbles from the MII to serial format before the information is processed by subsequent blocks.

Manchester Encoder: Allows encoding of both the clock and data in one bit stream. A logical one is encoded as a zero when the clock is high and a one when the clock is low. A logical zero is encoded as a one when the clock is high and a zero when the clock is low.

Digital Filter: Performs pre-emphasis and low pass filtering of the input Manchester data.

DAC: Converts the digital data to an analog format before transmission on the media.

Carrier Sense: In half-duplex operation, carrier is asserted when either the transmit or receive medium is active. In full-duplex operation, carrier asserted only on reception of data. During receive, carrier sense is asserted during reception of a valid preamble, and de-asserted after reception of an EOF.

Loopback: Enabled when bit 0.14 is asserted. This loopback mode allows for the Manchester encoded and filtered data to be looped back to the squelch block in the receive path. All the 10BASE-T digital functions are exercised during this mode. The transmit and receive channels are disconnected from the media.

MII loopback (18.13) must be disabled to allow for correct operation of the digital loopback (0.14).

Link Generator: Generates a 100 ns duration pulse at the end of every 12 ms period of the transmission path being idle (TXEN de-asserted). This pulse is used to keep the 10BASE-T link operational in the absence of data transmission.

19-26



Preliminary


Link Integrity Test: Used to determine whether the 10BASE-T link is operational. If neither data nor a link pulse is received for 64 ms, then the link is considered down. While the link is down, the transmit, loopback, collision detect, and SQE functions are disabled. The link down state is exited after receiving data or four link pulses.

Jabber: Prevents the transmitter from erroneously transmitting for too long a period. The maximum time the device can transmit is 50,000 bit times. When the jabber timer is exceeded, the transmit output goes idle for 0.525 s.

This function can be disabled with the jabber inhibit register bit (18.10).

Squelch: Used to determine whether active data, a link pulse, or an idle condition exists on the 10BASE-T receive channel. While an idle or link pulse condition exists, a higher squelch level is used for greater noise immunity. The squelch output is used to determine when the Manchester decoder should operate. The output is also used to determine when an end of packet is received.

Polarity Check: By examining the polarity of the received link pulses, EPHY can determine whether the received signal is inverted. If the pulses are inverted, this function changes the polarity of the signal.This feature is activated if eight inverted link pulses are received or four frames with inverted EOF are encountered.

Manchester Decoder and Timing Recovery: Decodes the Manchester encoded data. The receive data and clock are recovered during this process.

Serial to Parallel: Converts the serial bit stream from the Manchester decoder to the required MII parallel format.

PMD Sublayer: Transmits and receives signals compliant with IEEE 802.3, Section 14.

Line Transmitter and Line Receiver: These analog blocks allow the EPHY to drive and receive data from the 10BASE-T media.

19.4.4

100BASE-TX

100BASE-TX specifies operation over two pairs of category 5 unshielded twisted-pair cable (UTP).

The EPHY implementation includes the physical coding sublayer (PCS), the physical medium attachment

(PMA), and the physical medium dependent (PMD) sublayer.

The block diagram for 100BASE-TX operation is shown in Figure 19-22 .



Preliminary

19-27


PMA

TX

PCS

4B5B

ENCODER

PARALLEL

TO

SERIAL

SCRAMBLER

PMD

MLT3

ENCODER

SLOPE

CONTROL

MII

CARRIER

SENSE

PMA

LINE

DRIVER

DIGITAL

LOOPBACK

(bit 0.14)

ANALOG

LOOPBACK

(bit 18.4)

LINK

MONITOR

RX

4B5B

DECODER

SERIAL TO

PARALLEL

AND SYMBOL

ALIGNMENT

DESCRAMBLER

MLT3

DECODER

EQUALIZER

AND

TIMING

RECOVERY

BASELINE

WANDER

Figure 19-22. 100BASE-TX Block Diagram

19.4.4.1

Sublayers

19.4.4.1.1

PCS Sublayer

The PCS sublayer is the MII interface that provides a uniform interface to the reconciliation sublayer.

The services provided by the PCS include:

• Encoding/decoding of MII data nibbles to/from 5-bit code-groups (4B/5B)

• Carrier sense and collision indications

• Serialization/deserialization of code-groups for transmission/reception on the PMA

• Mapping of transmit, receive, carrier sense, and collision detection between the MII and the underlying PMA

Serial to Parallel and Symbol Alignment: This block looks for the occurrence of the JK symbol to align the serial bit stream and convert it to a parallel format.

Carrier Sense: In full-duplex mode, carrier sense is only asserted while the receive channel is active . The carrier sense examines the received data bit stream looking for the SSD, the JK symbol pair. In the idle state, IDLE symbols (all logic ones) will be received. If the first 5-bit symbols received after an idle stream forms the J symbol (11000) it asserts the CRS signal. At this point the second symbol is checked to confirm the K symbol (10001). If successful, the following aligned data (symbols) are presented to the 4B/5B decoder. If the JK pair is not confirmed, the false carrier detect is asserted and the idle state is re-entered.

Carrier sense is de-asserted when the ESD (end-of-stream) delimiter, the TR symbol pair, is found, or when an idle state is detected.

In half-duplex, CRS is also asserted on transmit.

Parallel to Serial: This block takes parallel data and converts it to serial format.

19-28



Preliminary


4B/5B Encoder/Decoder : The 4B/5B encoder converts the 4-bit nibbles from the reconciliation sublayer to a 5-bit code group.

19.4.4.1.2

PMA Sublayer

The PMA provides medium-independent means for the PCS and other bit-oriented clients (e.g., repeaters) to support the use of a range of physical media. For 100BASE-TX the PMA performs these functions:

• Mapping of transmit and receive code-bits between the PMA’s client and the underlying PMD

• Generating a control signal indicating the availability of the PMD to a PCS or other client

• Synchronization with the auto-negotiation function

• Generating indications of carrier activity and carrier errors from the PMD

• Recovery of clock from the NRZI data supplied by the PMD

19.4.4.1.3

PMD Sublayer

For 100BASE-TX, the ANSI X3.263: 199X (TP-PMD) standard is used. These signalling standards, called PMD sublayers, define 125 Mbps, full-duplex signalling systems that use STP and UTP wiring.

Scrambler/De-scrambler: The scrambler and de-scrambler used in EPHY meet the ANSI Standard

X3.263-1995 FDDI TP-PMD. The purpose of the scrambler is to randomize the 125 Mbps data on transmission resulting in a reduction of the peak amplitudes in the frequency spectrum. The de-scrambler restores the received 5-bit code groups to their unscrambled values.

The scrambler input data (plaintext) is encoded by modulo 2 addition of a key stream to produce a ciphertext bit stream. The key stream is a periodic sequence of 2047 bits generated by the recursive linear function X[n] = X[n-11] + X[n-9] (modulo 2).

If not transmitting data, the scrambler encodes and transmits idles. This allows a pattern to use by the de-scrambler to synchronize and decode the scrambled data.

The implementation of the scrambler and de-scrambler is as shown in Appendix G of the ANSI Standard

X3.263-1995.

For test, the scrambler can be bypassed by setting bit 18.5. Scrambler bypass mode is a special type of interface for 100BASE-TX operation that bypasses the scrambler and de-scrambler operation. This mode is typically used for test so that input and output test vectors match. In this mode, idles are not sent and the

MAC must provide idles.

MLT-3 Encoder/Decoder: An MLT-3 encoder is used in the transmit path to convert NRZ bit stream data from the PMA sublayer into a three-level code. This encoding results in a reduction in the energy over the critical frequency range. The MLT-3 decoder converts the received three-level code back to an NRZ bit stream.

Baseline Wander: The use of the scrambler and MLT-3 encoding can cause long run lengths of 0s and 1s that can produce a DC component. The DC component cannot be transmitted through the isolation transformers and results in baseline wander. Baseline wander reduces noise immunity because the base line moves nearer to either the positive or negative signal comparators. To correct for this EPHY uses DC



Preliminary

19-29

Ethernet Physical Transceiver (EPHY) Block Description restoration to restore the lost DC component of the recovered digital data to correct the baseline wander problem.

Timing Recovery : The timing recovery block locks onto the incoming data stream, extracts the embedded clock, and presents the data synchronized to the recovered clock.

In the event that the receive path is unable to converge to the receive signal, it resets the MSE-good (bit

25.15) signal. The clock synthesizer provides a center frequency reference for operation of the clock recovery circuit in the absence of data.

Adaptive Equalizer: At a data rate of 125 Mbps, the cable introduces significant distortion due to high frequency roll off and phase shift. The high frequency loss is mainly due to skin effect, which causes the conductor resistance to rise as the square of the frequency.

The adaptive equalizer will compensate for signal amplitude and phase distortion incurred from transmitting with different cable lengths.

Loopback : If asserted by bit 0.14, data encoded by the MLT3 encoder block is looped back to the MLT3 decoder block while the transmit and receive paths are disconnected from the media.

A second loopback mode for 100BASE-TX is available by setting bit 18.13 (MII loopback) to a logical 1.

This loopback mode takes the MII transmit data and loops it directly back to the MII receive pins. Again, the transmit and receive paths are disconnected from the media.

MII loopback has precedence over the digital loopback if both are enabled at the same time.

A third loopback mode is available by setting bit 18.4 high. This analog loopback mode takes the MLT3 encoded data and loops it back through the base line wander and analog receive circuits.

Line Transmitter and Line Receiver: These analog blocks allow EPHY to drive and receive data to/from the 100BASE-TX media. The transmitter is designed to drive a 100Ω UTP cable.

Link Monitor : The link monitor process is responsible for determining whether the underlying receive channel is providing reliable data. If a failure is found, normal operation will be disabled. As specified in the IEEE 802.3 standard, the link is operating reliably if a signal is detected for a period of 330 µ s.

Far End Fault : While the auto-negotiation function is disabled, this function is used to exchange fault information between the PHY and the link partner.

19.4.5

Low Power Modes

There are several reduced power configurations available for the EPHY.

19.4.5.1

Stop Mode

If the MCU executes a STOP instruction, the EPHY will be powered down and all internal MII registers reset to their default state. Upon exiting stop mode, the EPHY will exit the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers. The MII registers will have to be re-initialized after the start-up delay (t

Start-up

) has expired.

19-30



Preliminary


19.4.5.2

Wait Mode

If the MCU executes a WAIT instruction with the EPHYWAI bit set, the EPHY will be powered down and all internal MII registers reset to their default state. Upon exiting STOP mode the EPHY will exit the power-down state and latch the values previously written to the EPHYCTL0 and EPHYCTL1 registers.

The MII registers must be re-initialized after the start-up delay (t

Start-up

) has expired.

19.4.5.3

MII Power Down

This mode disconnects the PHY from the network interface (three-state receiver and driver pins).

Setting bit 0.11 of the port enters this mode. In this mode, the management interface is accessible but all internal chip functions are in a zero power state.

In this mode all analog blocks except the PLL clock generator and band gap reference are in low power mode. All digital blocks except the MDIO interface and management registers are inactive.



Preliminary

19-31


19-32



Preliminary

Chapter 20


20.1

Introduction

This chapter describes the direct memory access (DMA) controller module. It provides an overview of the module and describes in detail its signals and registers. The latter sections of this chapter describe operations, features, and supported data transfer modes in detail.

NOTE

The designation ‘ n ’ is used throughout this section to refer to registers or signals associated with one of the four identical DMA channels: DMA0,

DMA1, DMA2, or DMA3.

20.1.1

Overview

The DMA controller module enables fast transfers of data, providing an efficient way to move blocks of data with minimal processor interaction. The DMA module, shown in

Figure 20-1

, has four channels that allow byte, word, longword, or 16-byte burst data transfers. Each channel has a dedicated source address register (SAR n ), destination address register (DAR n ), byte count register (BCR n ), control register

(DCR n ), and status register (DSR n ). Transfers are dual address to on-chip devices, such as UART and

GPIOs.




MADDR[31:0]

MWDATA[31:0]

MRDATA[31:0]

MRSTH

MRW

MSIZ[1:0]

MTT[1:0]

MTM[2:0]

MTA

MTEA

MPL

#

#

#

MAP

MDP

MAH

* MTS

# - Version 3 Mbus signal

* - Version 2 Mbus signal

DMA

SADDR[4:2]

SDATA[31:0]

SSRSTH

SMEN[3:0]

SBE[3:0]

SOE

SWE

SIVOE

SINT[3:0]

EXT_REQ[3:0]

20-2



DREQ0 DREQ1 DREQ2 DREQ3

Internal

Bus

Channel

Requests

Channel 0 Channel 1 Channel 2 Channel 3

SAR0

DAR0

BCR0

DCR0

DSR0

SAR1

DAR1

BCR1

DCR1

DSR1

SAR2

DAR2

BCR2

DCR2

DSR2

SAR3

DAR3

BCR3

DCR3

DSR3

Channel

Attributes

Channel

Enables

MUX

Control

MUX

Interrupts

System Bus Address

System Bus Size

Current Master Attributes


Read Data Bus

Data Path

Data Path

Control

Write Data Bus

Arbitration/

Control

Bus Interface

Registered

Bus Signals

Figure 20-1. DMA Signal Diagram

NOTE

Throughout this chapter, the terms ‘external request’ and ‘DREQ’ are used to refer to a DMA request from one of the on-chip UARTS, DMA timers.

For details on the connections associated with DMA request inputs, see

Section 20.4.1, “DMA Request Control (DMAREQC) .”

20.1.2

Features

The DMA controller module features the following:

• Four independently programmable DMA controller channels

• Auto-alignment feature for source or destination accesses

• Dual-address transfers

• External request per channel

• Channel arbitration on transfer boundaries

• Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer

• Continuous-mode or cycle-steal transfers

• Independent transfer widths for source and destination

• Independent source and destination address registers

• Modulo addressing on source and destination addresses




• Automatic channel linking

20.2

M-bus Priority Level (MPL)

This output signal indicates to the bus arbiter that the DMA has been programmed to have priority on the transfer. This signal is a decode of the BWC bits. Depending on the M-bus arbiter architecture, this signal may be ignored.

20.3

DMA Transfer Overview

The DMA module can transfer data faster than the ColdFire core. The term “direct memory access” refers to a fast method of moving data within system memory (including memory and peripheral devices) with minimal processor intervention, greatly improving overall system performance. The DMA module consists of four independent, functionally equivalent channels, so references to DMA in this chapter apply to any of the channels. It is not possible to implicitly address all four channels at once.

The processor generates DMA requests internally by setting DCR[START]; the UART modules and DMA timers can generate a DMA request by asserting internal DREQ signals. The processor can program bus bandwidth for each channel. The channels support cycle-steal and continuous transfer modes; see

Section 20.5.1, “Transfer Requests (Cycle-Steal and Continuous Modes) .”

The DMA controller supports dual-address transfers. The DMA channels support up to 32 data bits.

• Dual-address transfers—A dual-address transfer consists of a read followed by a write and is initiated by an internal request using the START bit or by a peripheral DMA request. Two types of

transfer can occur: a read from a source device or a write to a destination device. See Figure 20-2


Control and Data

Memory/

Peripheral

Memory/

Peripheral

Control and Data

Figure 20-2. Dual-Address Transfer

Any operation involving the DMA module follows the same three steps:

1. Channel initialization—Channel registers are loaded with control information, address pointers, and a byte-transfer count.

2. Data transfer—The DMA accepts requests for operand transfers and provides addressing and bus control for the transfers.

20-4




3. Channel termination—Occurs after the operation is finished, either successfully or due to an error.

The channel indicates the operation status in the channel’s DSR, described in Section 20.4.4.1,

“DMA Status Registers (DSRn)

.”

20.4


This section describes each internal register and its bit assignment. Note that modifying DMA control

registers during a DMA transfer can result in undefined operation. Table 20-1

shows the mapping of DMA controller registers.

Table 20-1. Memory Map for DMA Controller Module Registers

DMA

Channel

IPSBAR Offset [31:24] [23:16] [15:8]

—

0

1

0x00_0014

0x00_0100

0x00_0104

0x00_0108

0x00_010C

0x00_0110

0x00_0114

Status Register 0

(DSR0)

DMA Request Control Register (DMAREQC)

1

Source Address Register 0 (SAR0)

Destination Address Register 0 (DAR0)

Byte Count Register 0 (BCR0)

Control Register 0 (DCR0)



0x00_0118

Status Register 1

(DSR1)

2

0x00_011C

0x00_0120

0x00_0124

0x00_0128

Status Register 2

(DSR2)

3

0x00_012C

0x00_0130

0x00_0134

0x00_0138

Status Register 3

(DSR3)

0x00_013C

1

Located within the SCM, but listed here for clarity.











[7:0]

20.4.1

DMA Request Control (DMAREQC)

The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller.

Writing to this register determines the exact routing of the DMA request to the four channels of the DMA modules.




IPSBAR

Offset:

0x00_0014 (DMAREQC)

30 29 28 31

R

W

R 0

W

Reset 0

0

0

0

0

0

0

27 26

Off-Platform DMAREQ Control

0

0

0

0

25

0

0

15

R

W

Reset 0

14 13

DMAC3

0

12 11 10 9

DMAC2

24

0

0

8

23

0

0

7

22

0

0

21

0

0

6 5

DMAC1

20

0

0

4

0

3

0 0 0 0 0 0 0 0 0 0

Figure 20-3. DMA Request Control Register (DMAREQC)

0

19 18 17

DMAREQC_EXT

16

0 0 0 0

0

Access: read/write

0

2 1

DMAC0

0 0

0

0

0

IPSBAR

Offset

0x00_0014

31

R

W

R 0

W

Reset 0

30 29 28 27 26

Off-Platform DMAREQ Control

25

0

0

0

0

0

0

0

0

0

0

0

0

15

R

W

Reset 0

14 13

DMAC3

0

12 11 10 9

DMAC2

24

0

0

8

23

0

0

0

7

22

0

0

21

0

0

0 0

6 5

DMAC1

20

0

0

0

4

19 18 17

DMAREQC_EXT

16

0 0 0 0 0 0 0 0 0 0

Figure 20-4. DMA Request Control Register (DMAREQC)

0

0

3

0 0

2 1

DMAC0

0

—

0

0

0

0

Table 20-2. DMAREQC Field Description


OFP_DMA

REQC

This 8-bit field is reserved for an SoC-dependent specification involving off-platform DMA requests.

—

31–16

—

Reserved. Should be cleared.


20-6




Table 20-2. DMAREQC Field Description (continued)

Field

15–0

DMAC n

Description

DMA channel n . Each four bit field defines the logical connection between the DMA requesters and that DMA channel.There are ten possible requesters (4 DMA Timers and 6 UARTs). Any request can be routed to any of the DMA channels. Effectively, the DMAREQC provides a software-controlled routing matrix of the 10 DMA request signals to the 4 channels of the DMA module. DMAC3 controls DMA channel 3, DMAC2 controls DMA channel 2, etc.

0100 DMA Timer 0.

0101 DMA Timer 1.

0110 DMA Timer 2.

0111 DMA Timer 3.

1000 UART0 Receive.

1001 UART1 Receive.

1010 UART2 Receive.

1100 UART0 Transmit.



All other values are reserved and will not generate a DMA request.

20.4.2

Source Address Registers (SAR0–SAR3)

SAR n , shown in

Figure 20-5

, contains the address from which the DMA controller requests data.


Offset:

0x00_0100 (DMA0)

0x00_0110 (DMA1)

0x00_0120 (DMA2)

0x00_0130 (DMA3)

30 29 31

R

W

Reset 0 0 0

28

0

27

0

26

0

25

0

24

SAR

23

0 0

22

0

21

0

20

0

19

0

18

0

17

0

16

0

15

R

W

Reset 0

14

0

13

0

12 11 10 9 8

SAR

7 6 5 4

0 0 0 0 0 0 0 0

Figure 20-5. Source Address Registers (SAR n )

0

3

0

2

0

1

0

0

0




IPSBAR

Offset

0x00_0100 (DMA0)

0x00_0110 (DMA1)

0x00_0120 (DMA2)

0x00_0130 (DMA3)

30 29 31

R

W

Reset 0 0 0

28

0

27 26 25 24

SAR

23 22 21 20 19 18 17

0 0 0 0 0 0 0 0 0 0 0

15

R

W

Reset 0

14 13 12 11 10 9 8

SAR

7 6 5 4 3 2

0 0 0 0 0 0 0

Figure 20-6.

0 0 0 0 0 0

NOTE

The backdoor enable bit must be set in the SCM RAMBAR as well as the secondary port valid bit in the core RAMBAR in order to enable backdoor accesses from the DMA to SRAM. See Section 10.5.2, “Memory Base

Address Register (RAMBAR),” and

Section 11.2.1, “SRAM Base Address

Register (RAMBAR),”

for more details.

1

0

16

0

0

0

20.4.3

Destination Address Registers (DAR0–DAR3)

DAR n , shown in

Figure 20-7

, holds the address to which the DMA controller sends data.

IPSBAR

Offset:

0x00_0104 (DMA0)

0x00_0114 (DMA1)

0x00_0124 (DMA2)

0x00_0134 (DMA3)

30 29 31

R

W

Reset 0 0 0

28

0

27

0

26

0

25

0

24

DAR

23

0 0

22

0

21

0

20

0

19

0

Access: read/write

18

0

17

0

16

0

15

R

W

Reset 0

14

0

13

0

12 11 10 9 8

DAR

7 6 5 4

0 0 0 0 0 0 0 0 0

Figure 20-7. Destination Address Registers (DAR n )

3

0

2

0

1

0

0

0

20-8




IPSBAR

Offset

0x00_0104 (DMA0)

0x00_0114 (DMA1)

0x00_0124 (DMA2)

0x00_0134 (DMA3)

30 29 31

R

W

Reset 0 0

14

0

13 15

R

W

Reset 0 0 0

28

0

12

0

27

0

11

0

26 25

0

10

0

9

24

DAR

23

0

8

DAR

0

7

0 0 0

Figure 20-8.

0

22 21 20 19 18 17 16

0

6

0

0

5

0

0

4

0

0

3

0

0

2

0

0

1

0 0

0

0

20.4.4

Byte Count Registers (BCR

n

) and DMA Status Registers (DSR

n

)

BCR n

, shown in Figure 20-9 , contains the number of bytes yet to be transferred for a given block. BCR

n decrements on the successful completion of the address transfer of a write transfer. BCR n decrements by

1, 2, 4, or 16 for byte, word, longword, or line accesses, respectively.


Offset:

0x00_0108 (DMA0)

0x00_0118 (DMA1)

0x00_0128 (DMA2)

0x00_0138 (DMA3)

30 29 31

R

W

Reset 0 0 0

28

DSR

27

0 0

26

0

25

0

24

0

23

0

22

0

21

0

20

BCR

19

0 0

18

0

17

0

16

0

15

R

W

Reset 0

14 13 12 11 10 9 8 7 6 5 4 3 2

BCR

0 0 0 0 0 0 0 0 0 0 0 0

Figure 20-9. Byte Count Registers (BCR n ) and Status Registers (DSR n )

0

1

0

0

0




IPSBAR

Offset

0x00_0108 (DMA0)

0x00_0118 (DMA1)

0x00_0128 (DMA2)

0x00_0138 (DMA3)

30 29 31

R

W

Reset 0 0 0

28

DSR

27

0 0

26 25 24 23 22 21 20

BCR

19 18 17 16

0 0 0 0 0 0 0 0 0 0 0

15

R

W

Reset 0

14 13 12 11 10 9 8

BCR

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

Figure 20-10.

0 0 0 0 0 0 0

DSR n [DONE], shown in

Figure 20-11 , is set when the block transfer is complete.

When a transfer sequence is initiated and BCR n [BCR] is not a multiple of 16, 4, or 2 when the DMA is configured for line, longword, or word transfers, respectively, DSR n [CE] is set and no transfer occurs. See

Section 20.4.4.1, “DMA Status Registers (DSRn).”

20.4.4.1

DMA Status Registers (DSR n )

In response to an event, the DMA controller writes to the appropriate DSR n bit,

Figure 20-11 . Only a write

to DSR n [DONE] results in action.


Offset:

See Figure 20-9

(DSR n )

6 7

0 R

W

Reset: 0

CE

5

BES

4

BED

3

0

2

REQ

0 0 0 0

Figure 20-11. DMA Status Registers (DSR n )

0

1

BSY

0

0

DONE

0

20-10




Field

7

6

CE

5

BES

4

BED

3

2

REQ

1

BSY

0

DONE

IPSBAR

Offset

See Figure 20-9

7

0

6

CE R

W

Reset 0 0

5

BES

4

BED

0 0

Figure 20-12.

0

3

0

2

REQ

0

1 0

BSY DONE

0 0

Table 20-3. DSR n Field Descriptions

Description


Configuration error. Occurs when BCR, SAR, or DAR does not match the requested transfer size, or if BCR = 0 when the DMA receives a start condition. CE is cleared at hardware reset or by writing a 1 to DSR[DONE].

0 No configuration error exists.

1 A configuration error has occurred.

Bus error on source

0 No bus error occurred.

1 The DMA channel terminated with a bus error during the read portion of a transfer.

Bus error on destination

0 No bus error occurred.

1 The DMA channel terminated with a bus error during the write portion of a transfer.


Request

0 No request is pending or the channel is currently active. Cleared when the channel is selected.

1 The DMA channel has a transfer remaining and the channel is not selected.

Busy

0 DMA channel is inactive. Cleared when the DMA has finished the last transaction.

1 BSY is set the first time the channel is enabled after a transfer is initiated.

Transactions done. Set when all DMA controller transactions complete, as determined by transfer count or error conditions. When BCR reaches zero, DONE is set when the final transfer completes successfully. DONE can also be used to abort a transfer by resetting the status bits. When a transfer completes, software must clear DONE before reprogramming the DMA.

0 Writing or reading a 0 has no effect.

1 DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and can be used in an interrupt handler to clear the DMA interrupt and error bits.

20.4.5

DMA Control Registers (DCR0–DCR3)

DCR n , shown in

Figure 20-13

, is used for configuring the DMA controller module.




IPSBAR

Offset:

0x00_010C (DMA0)

0x00_011C (DMA1)

0x00_012C (DMA2)

0x00_013C (DMA3)

31 30 29

R

W

INT

Reset 0

EEXT

0

CS

0

28

AA

0

15

R

W

Reset 0

14

SMOD

13

0 0

27

0

26

BWC

0

25

0

24

0

0

23

0

0

22

SINC

21

SSIZE

20

0 0 0

19

DINC

0

18

DSIZE

17

0 0

16

0

START

0

12 11 10

DMOD

9 8 7

D_REQ

6

0

5 4

LINKCC

0 0 0 0 0 0 0 0

Figure 20-13. DMA Control Registers (DCR n )

0

3

LCH1

2

0 0

Access: read/write

1

LCH2

0

0 0

IPSBAR

Offset

0x00_010C (DMA0)

0x00_011C (DMA1)

0x00_012C (DMA2)

0x00_013C (DMA3)

31 30 29 28

R INT EEXT CS AA

W

Reset 0 0 0 0

15

R

W

Reset 0

14

SMOD

13

0 0

12

0

Field

31

INT

30

EEXT

29

CS

27 26

BWC

25

0

11

0 0

10

DMOD

9

24

0

23

0

22

SINC

0

21 20

SSIZE

19

DINC

0 0 0

18 17

DSIZE

0 0

16

0

START

0 0

8

0

7 6

D_REQ 0

5 4

LINKCC

3

LCH1

2 1

LCH2

0

0 0 0 0 0

Figure 20-14.

0 0 0 0 0 0 0

Table 20-4. DCR n Field Descriptions

Description

Interrupt on completion of transfer. Determines whether an interrupt is generated by completing a transfer or by the occurrence of an error condition.

0 No interrupt is generated.

1 SINT asserts Internal interrupt signal is enabled.

Enable external request. Care should be taken because a collision can occur between the START bit and DREQ n when EEXT = 1.

0 External request is ignored.

1 Enables external request to initiate transfer. The internal request (initiated by setting the START bit) is always enabled.

Cycle steal.

0 DMA continuously makes read/write transfers until the BCR decrements to 0.

1 Forces a single read/write transfer per request.

20-12



Field

28

AA

27–25

BWC


Table 20-4. DCR n Field Descriptions (continued)

Description

Auto-align. AA and SIZE determine whether the source or destination is auto-aligned, that is, transfers are optimized based on the address and size. See

Section 20.5.4.1, “Auto-Alignment .”

0 Auto-align disabled

1 If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.

Bandwidth control. Indicates the number of bytes in a block transfer. Decoded for internal bandwidth control.

When the byte count reaches a multiple of the BWC value, the DMA releases the bus.the request signal to the internal arbiter, MAP, is negated until the access completes. This lets the arbiter give bus access to another device.

BWC

000

001

010

011

100

101

110

111

Number of kilobytes per block

DMA has priority and does not negate its request until transfer completes.

16 Kbytes

32 Kbytes

64 Kbytes

128 Kbytes

256 Kbytes

512 Kbytes

1024 Kbytes

24-23

22

SINC

21–20

SSIZE

19

DINC

18–17

DSIZE

16

START


Source increment. Controls whether a source address increments after each successful transfer.

0 No change to SAR after a successful transfer.

1 The SAR increments by 1, 2, 4, or 16, as determined by the transfer size.

Source size. Determines the data size of the source bus cycle for the DMA control module.

00 Longword

01 Byte

10 Word

11 Line (16-byte burst)

Destination increment. Controls whether a destination address increments after each successful transfer.

0 No change to the DAR after a successful transfer.

1 The DAR increments by 1, 2, 4, or 16, depending upon the size of the transfer.

Destination size. Determines the data size of the destination bus cycle for the DMA controller.

00 Longword

01 Byte

10 Word

11 Line (16-byte burst)

Start transfer.

0 DMA inactive

1 The DMA begins the transfer in accordance to the values in the control registers. START is cleared automatically after one system clock and is always read as logic 0.




Field

15–12

SMOD


Description

Source address modulo. Defines the size of the source data circular buffer used by the DMA controller. If enabled

(SMOD is non-zero), the buffer base address will be located on a boundary of the buffer size. The value of this boundary is based upon the initial source address (SAR). The base address should be aligned to a 0-modulo- circular buffer size boundary. Misaligned buffers are not possible. The boundary will be forced to the value determined by the upper address bits in the field selection.

11–8

DMOD

0 Source address modulo feature is disabled.

non-0

The value defines each address bit which is selected to be either the value after next-state SAR calculation is performed or the current SAR register value. This feature provides the ability to easily implement circular data queues. For data queues requiring power-of-2 “size” bytes, the queue should be based at a 0-modulo-size address and the SMOD field set to the appropriate value to effectively freeze the upper address bits. The bit select is defined as ((1 << SMOD+3) - 1) where a resulting 1 in a bit location selects the next state address for the corresponding address bit location and a 0 selects the original register value for the corresponding address bit location.

The modulo implementation includes 32 one-bit 2-to-1 muxes connected to the source address register and the output of an adder used to generate the next-state address. The adder sums the source address register with an offset calculated based on the transfer size and increment control (DCRn[SSIZE, SINC]). The 32-bit wide select vector is formed using the expression noted above and is then used to select either the source address register bit (select = 0) or the corresponding bit position from the adder output (select = 1) for each bit of the next-state source address.

This functionality supports circular queues ranging in size from 16 bytes (SMOD = 1) to 256 KBytes (SMOD = 15).

Destination address modulo. Defines the size of the destination data circular buffer used by the DMA controller.

If enabled (DMOD value is non-zero), the buffer base address will be located on a boundary of the buffer size.

The value of this boundary depends on the initial destination address (DAR). The base address should be aligned to a 0-modulo- circular buffer size boundary. Misaligned buffers are not possible. The boundary will be forced to the value determined by the upper address bits in the field selection.

Same functionality as SMOD, except it is applied to the destination address generation

.

DMOD

0000

0001

0010

...

1111

Circular Buffer Size

Buffer Disabled

16 Bytes

32 Bytes

...

256 Kbytes

20-14





Field

7

D_REQ

Description

Disable request.

If this flag is set, the DMA hardware automatically clears the corresponding DCR n [EEXT] bit when the byte count register reaches zero.

6

5–4

LINKCC

0 The channel’s EEXT bit is not affected.

1 The channel’s EEXT bit is cleared when the BCR is exhausted.


Link channel control. Allows DMA channels to have their transfers linked. The current DMA channel will trigger a

DMA request to the linked channels (LCH1 or LCH2) depending on the condition described by the LINKCC bits.

The LINKCC field provides a 2-bit encoded value defining the applicable channel-to-channel linking.

00 No channel-to-channel linking

01 Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to zero.

10 Perform a link to channel LCH1 after each cycle-steal transfer

11 Perform a link to channel LCH1 after the BCR decrements to zero

3–2

LCH1

1–0

LCH2

If not in cycle steal mode (DCR n [CS]=0) and LINKCC=01 or 10, then no link to LCH1 will occur.

The link channel (LCH1, LCH2) number cannot be the same as the currently-executing channel, and generates a configuration error if this is attempted (DSRn[CE] is set). This type of configuration error sets both DSRn[7:6].

The DSRn[CE] bit is set the standard configuration error flag, while DSRn[7] is a new flag to explicitly signal an linking configuration error.

If LINKCC = 01, a link to LCH1 is created after each cycle-steal transfer performed by the current DMA channel except the last one is completed. As the last cycle-steal is performed and the BCR reaches zero is done, then the link to LCH1 is closed and a link to LCH2 is created.

If the LINKCC field is non-zero, the contents of the bandwidth control field (DCRn[BWC]) are ignored and effectively forced to zero by the DMA hardware. This is done to prevent any non-zero bandwidth control settings from allowing channel arbitration while any type of link is to be performed.

Link channel 1. Indicates the DMA channel assigned as link channel 1. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR n [CE] is set).

The 2-bit link channel number under control of the encoded link control field, LINKCC.

00 DMA Channel 0

01 DMA Channel 1

10 DMA Channel 2

11 DMA Channel 3

Link channel 2. Indicates the DMA channel assigned as link channel 2. The link channel number cannot be the same as the currently executing channel, and generates a configuration error if this is attempted (DSR n [CE] is set).

The 2-bit link channel number under control of the encoded link control field, LINKCC.

00 DMA Channel 0

01 DMA Channel 1

10 DMA Channel 2

11 DMA Channel 3




20.5


In the following discussion, the term ‘DMA request’ implies that DCR n [START] or DCR n [EEXT] is set, followed by assertion of an internal or external DMA request. The START bit is cleared when the channel begins an internal access.

Before initiating a dual-address access, the DMA module verifies that DCR n [SSIZE,DSIZE] are consistent with the source and destination addresses. If they are not consistent, the configuration error bit,

DSR n [CE], is set. If misalignment is detected, no transfer occurs, DSR n [CE] is set, and, depending on the

DCR configuration, an interrupt event is issued. Note that if the auto-align bit, DCR n [AA], is set, error checking is performed on the appropriate registers.

A read/write transfer reads bytes from the source address and writes them to the destination address. The number of bytes is the larger of the sizes specified by DCR n [SSIZE] and DCR n [DSIZE]. See

Section 20.4.5, “DMA Control Registers (DCR0–DCR3) .”

Source and destination address registers (SAR n and DAR n ) can be programmed in the DCR n to increment at the completion of a successful transfer. BCR n decrements when an address transfer write completes for a single-address access (DCR n [SAA] = 0), or when SAA = 1.A successful address phase implies that

XMAP is asserted, XMAH is negated, and the current data phase is not incurring wait states. In the case of a Version 2 I

2

C, the address phase and data phase are identical;

20.5.1

Transfer Requests (Cycle-Steal and Continuous Modes)

The DMA channel supports internal and external requests. A request is issued by setting DCR n [START] or when a UART or DMA timer asserts a DMA request. Setting DCR n [EEXT] enables recognition of external DMA requests. Selecting between cycle-steal and continuous modes minimizes bus usage for either internal or external requests.

• Cycle-steal mode (DCR n [CS] = 1)—Only one complete transfer from source to destination occurs for each request. If DCR n [EEXT] is set, a request can be either internal or external. An internal request is selected by setting DCR n [START]. An external request is initiated by an on-chip peripheral while DCR n [EEXT] is set.

• Continuous mode (DCR n [CS] = 0)—After an internal or external request, the DMA continuously transfers data until BCR n reaches zero or a multiple of DCR n [BWC] or until DSR n [DONE] is set.

If BCR n is a multiple of BWC, the DMA request signal is negated until the bus cycle terminates to allow the internal arbiter to switch masters. DCR n [BWC] = 000 specifies the maximum transfer rate; other values specify a transfer rate limit.

The DMA performs the specified number of transfers, then relinquishes bus control. The DMA negates its internal bus request on the last transfer before BCR n reaches a multiple of the boundary specified in BWC. Upon completion, the DMA reasserts its bus request to regain mastership at the earliest opportunity. The DMA loses bus control for a minimum of one bus cycle.

20-16




20.5.2

Dual-Address Data Transfer Mode

Each channel supports dual-address transfers. Dual-address transfers consist of a source data read and a destination data write. The DMA controller module begins a dual-address transfer sequence during a DMA request. If no error condition exists, DSR n [REQ] is set.

• Dual-address read—The DMA controller drives the SAR n value onto the internal address bus. If

DCR n [SINC] is set, the SAR n increments by the appropriate number of bytes upon a successful read cycle. When the appropriate number of read cycles complete (multiple reads if the destination size is larger than the source), the DMA initiates the write portion of the transfer.

If a termination error occurs, DSR n [BES,DONE] are set and DMA transactions stop.

• Dual-address write—The DMA controller drives the DAR n value onto the address bus. If

DCR n [DINC] is set, DAR n increments by the appropriate number of bytes at the completion of a successful write cycle. BCR n decrements by the appropriate number of bytes. DSR n [DONE] is set when BCR n reaches zero. If the BCR n is greater than zero, another read/write transfer is initiated.

If the BCR n is a multiple of DCR n [BWC], the DMA request signal is negated until termination of the bus cycle to allow the internal arbiter to switch masters. In the case of a Version 2 I

2

C, there is an idle clock before the next assertion of MTS

If a termination error occurs, DSR n [BED,DONE] are set and DMA transactions stop.

20.5.3

Channel Initialization and Startup

Before a block transfer starts, channel registers must be initialized with information describing configuration, request-generation method, and the data block.

20.5.3.1

Channel Prioritization

The four DMA channels are prioritized in ascending order (channel 0 having highest priority and channel

3 having the lowest) or in an order determined by DCR n [BWC]. If the BWC encoding for a DMA channel is 000, that channel has priority only over the channel immediately preceding it. For example, if

DCR3[BWC] = 000, DMA channel 3 has priority over DMA channel 2 (assuming DCR2[BWC] ≠ 000), but not over DMA channel 1.

If DCR0[BWC] = DCR1[BWC] = 000, DMA0 still has priority over DMA1. In this case, DCR1[BWC] =

000 does not affect prioritization.

Simultaneous external requests are prioritized either in ascending order or in an order determined by each channel’s DCR n [BWC] bits.

20.5.3.2

Programming the DMA Controller Module

Note the following general guidelines for programming the DMA:

• No mechanism exists within the DMA module itself to prevent writes to control registers during

DMA accesses.

• If the DCR n [BWC] value of sequential channels are equal, the channels are prioritized in ascending order.




The DMAREQC register is configured to assign peripheral DMA requests to the individual DMA channels.

The SAR n is loaded with the source (read) address. If the transfer is from a peripheral device to memory, the source address is the location of the peripheral data register. If the transfer is from memory to either a peripheral device or memory, the source address is the starting address of the data block. This can be any aligned byte address.

The DAR n should contain the destination (write) address. If the transfer is from a peripheral device to memory, or from memory to memory, the DAR n is loaded with the starting address of the data block to be written. If the transfer is from memory to a peripheral device, DAR n is loaded with the address of the peripheral data register. This address can be any aligned byte address.

SAR n and DAR n change after each cycle depending on DCR n [SSIZE,DSIZE,

SINC,DINC,SMOD,DMOD] and on the starting address. Increment values can be 1, 2, 4, or 16 for byte, word, longword, or 16-byte line transfers, respectively. If the address register is programmed to remain unchanged (no count), the register is not incremented after the data transfer.

BCR n [BCR] must be loaded with the number of byte transfers to occur. It is decremented by 1, 2, 4, or 16 at the end of each transfer, depending on the transfer size. DSR n [DONE] must be cleared for channel startup.

As soon as the channel has been initialized, it is started by writing a one to DCR n [START] or a peripheral

DMA request, depending on the status of DCR n [EEXT]. Programming the channel for internal requests causes the channel to request the bus and start transferring data immediately. If the channel is programmed for external request, a peripheral DMA request must be asserted before the channel requests the bus.

Changes to DCR n are effective immediately while the channel is active. To avoid problems with changing a DMA channel setup, write a one to DSR n [DONE] to stop the DMA channel.

20.5.4

Data Transfer

This section describes auto-alignment and bandwidth control for DMA transfers.

20.5.4.1

Auto-Alignment

Auto-alignment allows block transfers to occur at the optimal size based on the address, byte count, and programmed size. To use this feature, DCR n [AA] must be set. The source is auto-aligned if DCR n [SSIZE] indicates a transfer size larger than DCR n [DSIZE]. Source alignment takes precedence over the destination when the source and destination sizes are equal. Otherwise, the destination is auto-aligned. The address register chosen for alignment increments regardless of the increment value. Configuration error checking is performed on registers not chosen for alignment.

If BCR n is greater than 16, the address determines transfer size. Bytes, words, or longwords are transferred until the address is aligned to the programmed size boundary, at which time accesses begin using the programmed size.

If BCR n is less than 16 at the start of a transfer, the number of bytes remaining dictates transfer size. For example, AA = 1, SAR n = 0x0001, BCR n = 0x00F0, SSIZE = 00 (longword), and DSIZE = 01 (byte).

20-18




Because SSIZE > DSIZE, the source is auto-aligned. Error checking is performed on destination registers.

The access sequence is as follows:

1. Read byte from 0x0001—write 1 byte, increment SAR n .

2. Read word from 0x0002—write 2 bytes, increment SAR n .

3. Read longword from 0x0004—write 4 bytes, increment SAR n .

4. Repeat longwords until SAR n = 0x00F0.

5. Read byte from 0x00F0—write byte, increment SAR n .

If DSIZE is another size, data writes are optimized to write the largest size allowed based on the address, but not exceeding the configured size.

20.5.4.2

Bandwidth Control

Bandwidth control makes it possible to force the DMA off the bus to allow access to another device.

DCR n [BWC] provides seven levels of block transfer sizes. If the BCR n decrements to a multiple of the decode of the BWC, the DMA bus request negates until the bus cycle terminates. If a request is pending, the arbiter may then pass bus mastership to another device. If auto-alignment is enabled, DCR n [AA] = 1, the BCR n may skip over the programmed boundary, in which case, the DMA bus request is not negated.

If BWC = 000, the request signal remains asserted until BCR n reaches zero. DMA has priority over the core. Note that in this scheme, the arbiter can always force the DMA to relinquish the bus. See

Section 10.6.3, “Bus Master Park Register (MPARK).”

20.5.5

Termination

An unsuccessful transfer can terminate for one of the following reasons:

•

Error conditions—When the DMA encounters a read or write cycle that terminates with an error

condition, DSR n [BES] is set for a read and DSR n [BED] is set for a write before the transfer is halted. If the error occurred in a write cycle, data in the internal holding register is lost.

• Interrupts—If DCR n [INT] is set, the DMA drives the appropriate internal interrupt signal. The processor can read DSR n to determine whether the transfer terminated successfully or with an error. DSR n [DONE] is then written with a one to clear the interrupt and the DONE and error bits.




20-20



Chapter 21

EzPort

EzPort is a serial Flash programming interface that allows the Flash memory contents on a 32-bit general purpose microcontroller to be read, erased, and programmed from off-chip in a compatible format to many standalone Flash memory chips.

21.1

Features

The EzPort includes the following features:

• Serial interface that is compatible with a subset of the SPI format

• Ability to read, erase, and program Flash memory

• Ability to reset the micro-controller, allowing it to boot from the Flash memory after the memory has been configured

The EzPort allows the Flash memory internal to the controller to be programmed like standard SPI flash memories available from ST Microelectronics, Macronix, Spansion, and other vendors. The EzPort implements the same command set as devices from these vendors, so existing microcontroller or automated test equipment code used to program these devices can also be used to program the device with little or no modification. In essence, the EzPort eliminates the need to use the background debug mode interface to download and run user-developed flash programming code to initialize

21.2


The EzPort can operate in one of two different modes:

• Enabled—When enabled, the EzPort steals access to the Flash memory, preventing access from other cores or peripherals. The rest of the micro-controller is disabled when the EzPort is enabled to avoid conflicts.

• Disabled—When the EzPort is disabled, the rest of the micro-controller can access Flash memory as normal.



Preliminary

21-1

EzPort

Figure 21-1

is a block diagram of the EzPort.

EzPort Enabled

G

Flash

Controller

EzPort

EZPCS

EZPCK

EZPD

EZPQ

Flash Memory

Microcontroller

Core

Reset

Reset Out

Reset Controller

Figure 21-1. EzPort Block Diagram

21.3


21.3.1

Overview

Table 21-1

contains a list of EzPort external signals.

Name

EZPCK

EZPCS

EZPD

EZPQ

Table 21-1. Signal Descriptions

Description

EzPort Clock

EzPort Chip Select

EzPort Serial Data In

EzPort Serial Data Out

I/O

Input

Input

Input

Output

21.3.2

Detailed Signal Descriptions

21.3.2.1

EZPCK — EzPort Clock

EzPort clock (EZPCK) is the serial clock for data transfers. Serial data in (EZPD) and chip select (EZPCS) are registered on the rising edge of EZPCK while serial data out (EZPQ) is driven on the falling edge of

21-2



Preliminary

EzPort

EZPCK.The maximum frequency of the EzPort clock is half the system clock frequency for all commands except when executing the read data command. When executing the Read Data command, the EzPort clock has a maximum frequency of one eighth the system clock frequency.

21.3.2.2

EZPCS — EzPort Chip Select

EzPort chip select (EZPCS) is the chip select for signalling the start and end of serial transfers. If EZPCS is asserted during and when the micro-controller’s reset out signal is negated, then EzPort is enabled out of reset; otherwise it is disabled. Once EzPort is enabled, asserting EZPCS commences a serial data transfer, which continues until EZPCS is negated again. The negation of EZPCS indicates the current command is finished and resets the EzPort state machine so that it is ready to receive the next command.

21.3.2.3

EZPD — EzPort Serial Data In

EzPort serial data in (EZPD) is the serial data in for data transfers. It is registered on the rising edge of

EZPCK. All commands, addresses, and data are shifted in most significant bit first. When EzPort is driving output data on EZPQ, the data shifted in EZPD is ignored.

21.3.2.4

EZPQ — EzPort Serial Data Out

EzPort serial data out (EZPQ) is the serial data out for data transfers. It is driven on the falling edge of

EZPCK. It is tri-stated, unless EZPCS is asserted and the EzPort is driving data out. All data is shifted out most significant bit first.

21.4

Command Definition

The EzPort receives commands from an external device and translates those commands into Flash memory accesses.

Table 21-2

lists the supported commands.

Table 21-2. EzPort Commands

Command Description Code

Address

Bytes

Dummy

Bytes

0 0 WREN

WRDI

RDSR

WRCR

READ

FAST_READ

PP

SE

BE

Write Enable

Write Disable

Read Status Register

Write Config Register

Read Data

Read Data at High Speed

Page Program

Sector Erase

Bulk Erase

0x06

0x04

0x05

0x01

0x03

0x0B

0x02

0xD8

0xC7

0

0

0

3

3

3

3

0

RESET Reset Chip 0xB9 0

1

Lists the compatible commands on the ST Microelectronics Serial Flash Memory parts.

0

0

1

0

0

0

0

0

0

Data

Bytes

0

1

1+

0

0

0

1

1+

4 to 256

0

Compatible

Commands

1

WREN

WRDI

RDSR

WRSR

READ

FAST_READ

PP

SE

BE

DP



Preliminary

21-3

EzPort

21.4.1

Command Descriptions

21.4.1.1

Write Enable

The Write Enable command sets the write enable register bit in the status register. The write enable bit must be set for a Write Configuration Register (WRCR), Page Program (PP), Sector Erase (SE), or Bulk Erase

(BE) command to be accepted. The write enable register bit clears on reset, on a Write Disable command, and at the completion of a write, program, or erase command.

This command should not be used if a write is already in progress.

21.4.1.2

Write Disable

The Write Disable command clears the write enable register bit in the status register.

This command should not be used if a write is already in progress.

21.4.1.3

Read Status Register

The Read Status Register command returns the contents of the EzPort Status register.

IPSBAR

Offset:

R

W

Reset:

7

FS

6

WEF

5

CRL

4 3

0/1

1

0 0 0 0

Figure 21-2. EzPort Status Register

1

Reset value reflects if Flash Security is enabled or disabled out of reset.

2

0

Access: read/write

1

WEN

0

0

WIP

0

21-4

Field

7

FS

6

WEF

Table 21-3. EzPort Status Register Field Description

Descriptions

Flash Security. Status flag that indicates if the Flash memory is in secure mode. In secure mode, the following commands are not accepted: Read (READ), Fast Read (FAST_READ), Page Program (PP), Sector Erase

(SE). Secure mode can be exited by performing a Bulk Erase (BE) command, which erases the entire contents of the Flash memory.

0 Flash is not in secure mode.

1 Flash is in secure mode.

Write Error Flag. Status flag that indicates if there has been an error with an erase or program instruction inside the Flash controller due to attempting to program or erase a protected sector, or if there is an error in the Flash memory after performing a Bulk Erase command. The flag clears after a Read Status Register (RDSR) command.

0 No error on previous erase/program command.

1 Error on previous erase/program command.



Preliminary

Field

5

CRL

EzPort

Table 21-3. EzPort Status Register Field Description (continued)

Descriptions

Configuration Register Loaded. Status flag that indicates if the configuration register has been loaded. The configuration register initializes the Flash controllers clock configuration register to generate a divided down clock from the system clock that runs at a frequency of 150 kHz to 200 kHz. This register must be initialized before any erase or program commands are accepted.

0 Configuration register has not been loaded; erase and program commands are not accepted.

1 Configuration register has been loaded; erase and program commands are accepted.


4–2

—

1

WEN

0

WIP

Write Enable. Control bit that must be set before a Write Configuration Register (WRCR), Page Program (PP),

Sector Erase (SE), or Bulk Erase (BE) command is accepted. Is set by the Write Enable (WREN) command and cleared by reset or a Write Disable (WRDI) command. It also clears on completion of a write, erase, or program command.

0 Disables the following write, erase, or program command.

1 Enables the following write, erase, or program command.

Write In Progress. Status flag that sets after a Write Configuration Register (WRCR), Page Program (PP),

Sector Erase (SE), or Bulk Erase (BE) command is accepted and clears once the Flash memory erase or program is completed. Only the Read Status Register (RDSR) command is accepted while a write is in progress.

0 Write is not in progress. Accept any command.

1 Write is in progress. Only accept RDSR command.

21.4.1.4

Write Configuration Register

The Write Configuration Command updates the Flash controller’s clock configuration register. The clock configuration register divides down the Flash controller’s internal system clock to a 150 kHz to 200 kHz clock. This register must be initialized before any erase or program commands are issued to the Flash controller.

This command should not be used if the write error flag is set, a write is in progress, or the configuration register has already been loaded (as it is a write-once register).

IPSBAR

Offset:

Access: read/write

7 6 5 4 3 2 1 0

R

W

Reset: 0

PRDIV8

0 0 0 0

DIV[5:0]

Figure 21-3. EzPort Configuration Register

0 0 0



Preliminary

21-5

EzPort

Field

7

—

6

PRDIV

5–0

DIV[5:0]

Table 21-4. EzPort Configuration Register Field Description


Descriptions

Enables prescaler divide by 8.

0 The system clock is fed directly into the divider.

1 Enables a prescaler that divides the system clock by 8 before it enters the divider.

Clock divider field. The combination of PRDIV8 and DIV[5:0] effectively divides the system clock down to a frequency between 150 kHz and 200 kHz.

21.4.1.5

Read Data

The Read Data command returns data from the Flash memory, starting at the address specified in the command word. Data will continue being returned for as long as the EzPort chip select (EZPCS) is asserted, with the address automatically incrementing. When the address reaches the highest Flash memory address, it will wrap around to the lowest Flash memory address. In this way, the entire contents of the Flash memory can be returned by one command.

For this command to return the correct data, the EzPort Clock (EZPCK) must run at no more than divide by eight of the internal system clock.

This command should not be used if the write error flag is set, or a write is in progress. This command is not accepted if Flash security is enabled.

21.4.1.6

Read Data at High Speed

This command is identical to the Read Data command, except for the inclusion of a dummy byte following the address bytes and before the first data byte is returned.

This allows the command to run at any frequency of the EzPort Clock (EZPCK) up to and including half the internal system clock frequency of the micro-controller.This command should not be used if the write error flag is set, or a write is in progress. This command is not accepted if Flash security is enabled.

21.4.1.7

Page Program

The Page Program command programs locations in Flash memory that have previously been erased. The starting address of the memory to program is sent after the command word and must be a 32-bit aligned address (the two LSBs must be zero). After every four bytes of data are received by the EzPort, that 32-bit word is programmed into Flash memory with the address automatically incrementing after each write. For this reason, the number of bytes to program must be a multiple of four. Only a maximum of 256 bytes can be programmed at a time; when the address reaches the highest address within any given 256-byte space of memory, it will wrap around to the lowest address in that same space.

This command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set, or the configuration register has not been written.This command is not accepted if Flash security is enabled.

The write error flag will set if there is an attempt to program a protected area of the Flash memory.

21-6



Preliminary

EzPort

21.4.1.8

Sector Erase

The Sector Erase command erases the contents of a 2-Kbyte space of Flash memory. The 3-byte address sent after the command byte can be any address within the space to erase.

This command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set, or the configuration register has not been written. This command is not accepted if Flash security is enabled.

The write error flag will set if there is an attempt to erase a protected area of the Flash memory.

21.4.1.9

Bulk Erase

The Bulk Erase command erases the entire contents of Flash memory, ignoring any protected sectors or

Flash security. The write error flag will set if the Bulk Erase command does not successfully erase the entire contents of Flash memory. Flash security will be disabled if the Bulk Erase command is followed by a Reset Chip command.

This command should not be used if the write error flag is set, a write is in progress, the write enable bit is not set, or the configuration register has not been written.

21.4.1.10 Reset Chip

The Reset Chip command forces the chip into the reset state. If the EzPort chip select (EZPCS) pin is asserted at the end of the reset period, then EzPort will be enabled; otherwise it will be disabled.

This command allows the chip to boot up from Flash memory after it has been programmed by an external source.

This command should not be used if a write is in progress.

21.5


The EzPort provides a simple interface to connect an external device to the Flash memory on board a 32 bit microcontroller.

The interface itself is compatible with the SPI interface (with the EzPort operating as a slave) running in either of the two following modes with data transmitted most significant bit first:

• CPOL = 0, CPHA = 0

• CPOL = 1, CPHA = 1

Commands are issued by the external device to erase, program, or read the contents of the Flash memory.

The serial data out from the EzPort is tri-stated unless data is being driven, allowing the signal to be shared among several different EzPort (or compatible) devices in parallel, provided they have different chip selects.



Preliminary

21-7

EzPort

21.6


Prior to issuing any program or erase commands, the clock configuration register must be written to set the Flash state machine clock (FCLK). The Flash controller module runs at the system clock frequency divide by 2, but FCLK must be divided down from this frequency to a frequency between 150 kHz and

200 kHz. Use the following procedure to set the PRDIV8 and DIV[5:0] bits in the clock configuration register.

1. If f

SYS

is greater than 25.6 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.

2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result and discard any fraction. Do not round the result.

DIV =

(

Fsys

2x200kHzx 1 + ( PRDIV8x7 )

3. Thus the Flash state machine clock will be:

Fclk =

) (

Fsys x 1 + PRDIV8x7 ) )

So, for Fsys = 66 MHz, writing 0x54 to the clock configuration register will set Fclk to 196.43 kHz, which is a valid frequency for the timing of program and erase operations.

For proper program and erase operations, it is critical to set Fclk between 150 kHz and 200 kHz. Array damage due to overstress can occur when Fclk is less than 150 kHz. Incomplete programming and erasure can occur when Fclk is greater than 200 kHz.

21-8



Preliminary

Chapter 22


22.1

Introduction

This chapter describes the operation of the two programmable interrupt timer modules: PIT0–PIT1.

22.1.1

Overview

Each PIT is a 16-bit timer that provides precise interrupts at regular intervals with minimal processor intervention. The timer can either count down from the value written in the modulus register, or it can be a free-running down-counter.

22.1.2

Block Diagram

Internal Bus

Internal Bus

Clock (f sys/

)

Prescaler

EN

PRE[3:0]

DOZE

DBG

16-bit PCNTR n

16-bit PIT Counter

OVW

16-bit PMR n

COUNT = 0

Load

Counter

RLD

PIF

PIE

To Interrupt

Controller

Internal Bus

Figure 22-1. PIT Block Diagram

22.1.3


This subsection describes the operation of the PIT modules in low-power modes and debug mode of operation. Low-power modes are described in the power management module, Chapter 8, “Power

Management.”

Table 22-1

shows the PIT module operation in low-power modes, and how it can exit from each mode.



Preliminary

22-1


NOTE

The low-power interrupt control register (LPICR) in the system control module specifies the interrupt level at or above which the device can be brought out of a low-power mode.

Table 22-1. PIT Module Operation in Low-power Modes

Low-power Mode

Wait

Doze

Stop

Debug

PIT Operation Mode Exit

Normal N/A

Normal if PCSR n [DOZE] cleared, stopped otherwise

Any interrupt at or above level in LPICR, will exit doze mode if PCSR n [DOZE] is set. Otherwise interrupt assertion has no effect.

Stopped No

Normal if PCSR n [DBG] cleared, stopped otherwise

No. Any interrupt will be serviced upon normal exit from debug mode

In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the low-power mode by generating an interrupt request. In doze mode with the PCSR n [DOZE] bit set, PIT module operation stops. In doze mode with the PCSR n [DOZE] bit cleared, doze mode does not affect PIT operation. When doze mode is exited, the PIT continues to operate in the state it was in prior to doze mode.

In stop mode, the internal bus clock is absent, and PIT module operation stops.

In debug mode with the PCSR n [DBG] bit set, PIT module operation stops. In debug mode with the

PCSR n [DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT continues to operate in its pre-debug mode state, but any updates made in debug mode remain.

22.2


This section contains a memory map, shown in Table 22-2

, and describes the register structure for

PIT0–PIT1.

Table 22-2. Programmable Interrupt Timer Modules Memory Map

IPSBAR Offset

PIT 0

PIT 1

Register

Width

(bits)

Access


2

PIT Control and Status Register (PCSR n ) 16 R/W 0x15_0000

0x16_0000

0x15_0002

0x16_0002

PIT Modulus Register (PMR n ) 16 R/W

1

Reset Value Section/Page

0x0000

0xFFFF

22.2.1/22-3

22.2.2/22-4

0x15_0004

0x16_0004

User/Supervisor Access Registers

PIT Count Register (PCNTR n ) 16 R 0xFFFF

22.2.3/22-5

22-2



Preliminary


1

2

Accesses to reserved address locations have no effect and result in a cycle termination transfer error.

User mode accesses to supervisor only addresses have no effect and result in a cycle termination transfer error.

22.2.1

PIT Control and Status Register (PCSR

n

)

The PCSR n registers configure the corresponding timer’s operation.

IPSBAR

Offset:

0x15_0000 (PCSR0)

0x16_0000 (PCSR

1

)

15

R 0

W

Reset 0

14

0

0

13

0

0

12

0

11 10

PRE

9 8 7

0

6 5 4

0 0 0 0 0 0 0 0 0

Figure 22-2. PIT Control and Status Register (PCSR n )

3

DOZE DBG OVW PIE

0


1 0 2

PIF w1c

0

RLD

0

EN

0

Table 22-3. PCSR n Field Descriptions



11–8

PRE

Prescaler. The read/write prescaler bits select the internal bus clock divisor to generate the PIT clock. To accurately predict the timing of the next count, change the PRE[3:0] bits only when the enable bit (EN) is clear. Changing

PRE[3:0] resets the prescaler counter. System reset and the loading of a new value into the counter also reset the prescaler counter. Setting the EN bit and writing to PRE[3:0] can be done in this same write cycle. Clearing the EN bit stops the prescaler counter.

PRE

0000

0001

0010

...

1101

1110

1111

Internal Bus Clock

Divisor

2

0

2

1

2

2

...

2

13

2

14

2

15

Decimal

Equivalent

1

2

4

...

8192

16384

32768

7

6

DOZE


Doze mode bit. The read/write DOZE bit controls the function of the PIT in doze mode. Reset clears DOZE.

0 PIT function not affected in doze mode

1 PIT function stopped in doze mode. When doze mode is exited, timer operation continues from the state it was in before entering doze mode.



Preliminary

22-3


Table 22-3. PCSR n Field Descriptions (continued)

Field

5

DBG

4

OVW

3

PIE

2

PIF

1

RLD

0

EN

Description

Debug mode bit. Controls the function of the PIT in halted/debug mode. Reset clears DBG. During debug mode, register read and write accesses function normally. When debug mode is exited, timer operation continues from the state it was in before entering debug mode, but any updates made in debug mode remain.

0 PIT function not affected in debug mode

1 PIT function stopped in debug mode

Note: Changing the DBG bit from 1 to 0 during debug mode starts the PIT timer. Likewise, changing the DBG bit from

0 to 1 during debug mode stops the PIT timer.

Overwrite. Enables writing to PMR n to immediately overwrite the value in the PIT counter.

0 Value in PMR n replaces value in PIT counter when count reaches 0x0000.

1 Writing PMR n immediately replaces value in PIT counter.

PIT interrupt enable. This read/write bit enables the PIF flag to generate interrupt requests.

0 PIF interrupt requests disabled

1 PIF interrupt requests enabled

PIT interrupt flag. This read/write bit is set when the PIT counter reaches 0x0000. Clear PIF by writing a 1 to it or by writing to PMR. Writing 0 has no effect. Reset clears PIF.

0 PIT count has not reached 0x0000.

1 PIT count has reached 0x0000.

Reload bit. The read/write reload bit enables loading the value of PMR n into the PIT counter when the count reaches

0x0000.

0 Counter rolls over to 0xFFFF on count of 0x0000

1 Counter reloaded from PMR n on count of 0x0000

PIT enable bit. Enables PIT operation. When the PIT is disabled, the counter and prescaler are held in a stopped state. This bit is read anytime, write anytime.

0 PIT disabled

1 PIT enabled

22.2.2

PIT Modulus Register (PMR

n

)

The 16-bit read/write PMR n contains the timer modulus value that is loaded into the PIT counter when the count reaches 0x0000 and the PCSR n [RLD] bit is set.

When the PCSR n [OVW] bit is set, PMR n is transparent, and the value written to PMR n is immediately loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into the PIT counter and also during reset. Reading the PMR n returns the value written in the modulus latch.

Reset initializes PMR n to 0xFFFF.

IPSBAR

Offset:

0x15_0002 (PMR0)

0x16_0002 (PMR 1 )

14 13 15

R

W

Reset 1 1 1

12 11 10 9 8

PM

7 6 5 4

1

3

1 1 1 1 1 1 1 1 1 1 1 1

Figure 22-3. PIT Modulus Register (PMR n )


2 1 0

22-4



Preliminary


22.2.3

PIT Count Register (PCNTR

n

)

The 16-bit, read-only PCNTR n contains the counter value. Reading the 16-bit counter with two 8-bit reads is not guaranteed to be coherent. Writing to PCNTR n has no effect, and write cycles are terminated normally.

Access: User read only IPSBAR

Offset:

0x15_0004 (PCNTR0)

0x16_0004 (PCNTR 1 )

14 13 15

R

W

Reset 1 1 1

12 11 10 9 8

PC

7 6 5

1 1 1 1 1 1 1 1

Figure 22-4. PIT Count Register (PCNTR n )

4

1

3

1

2

1

1

1

0

1

22.3


This section describes the PIT functional operation.

22.3.1

Set-and-Forget Timer Operation

This mode of operation is selected when the RLD bit in the PCSR register is set.

When the PIT counter reaches a count of 0x0000, the PIF flag is set in PCSR n . The value in the modulus register is loaded into the counter, and the counter begins decrementing toward 0x0000. If the PCSR n [PIE] bit is set, the PIF flag issues an interrupt request to the CPU.

When the PCSR n [OVW] bit is set, the counter can be directly initialized by writing to PMR n without having to wait for the count to reach 0x0000.

PIT CLOCK

COUNTER

MODULUS

PIF

0x0002 0x0001

0x0005

0x0000 0x0005

Figure 22-5. Counter Reloading from the Modulus Latch

22.3.2

Free-Running Timer Operation

This mode of operation is selected when the PCSR n [RLD] bit is clear. In this mode, the counter rolls over from 0x0000 to 0xFFFF without reloading from the modulus latch and continues to decrement.

When the counter reaches a count of 0x0000, the PCSR n [PIF] flag is set. If the PCSR n [PIE] bit is set, the

PIF flag issues an interrupt request to the CPU.



Preliminary

22-5


When the PCSR n [OVW] bit is set, the counter can be directly initialized by writing to PMR n without having to wait for the count to reach 0x0000.

PIT CLOCK

COUNTER

MODULUS

PIF

0x0002 0x0001

0x0005

0x0000 0xFFFF

Figure 22-6. Counter in Free-Running Mode

22.3.3

Timeout Specifications

The 16-bit PIT counter and prescaler supports different timeout periods. The prescaler divides the internal bus clock period as selected by the PCSR n [PRE] bits. The PMR n [PM] bits select the timeout period.

22.3.4

Interrupt Operation

Table 22-4

shows the interrupt request generated by the PIT.

Table 22-4. PIT Interrupt Requests

Interrupt Request

Timeout

Flag

PIF

Enable Bit

PIE

The PIF flag is set when the PIT counter reaches 0x0000. The PIE bit enables the PIF flag to generate interrupt requests. Clear PIF by writing a 1 to it or by writing to the PMR.

22-6



Preliminary

Chapter 23


23.1

Introduction

This device has one 4-channel general purpose timer module (GPT). It consists of a 16-bit counter driven by a 7-stage programmable prescaler.

A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Each of the four timer channels can be configured for input capture, which can capture the time of a selected transition edge, or for output compare, which can generate output waveforms and timer software delays. These functions allow simultaneous input waveform measurements and output waveform generation.

Additionally, channel 3 can be configured as a 16-bit pulse accumulator that can operate as a simple event counter or as a gated time accumulator. The pulse accumulator uses the GPT channel 3 input/output pin in either event mode or gated time accumulation mode.

23.2

Features

Features of the general-purpose timer include the following:

• Four 16-bit input capture/output compare channels

• 16-bit architecture

• Programmable prescaler

• Pulse widths variable from microseconds to seconds

• Single 16-bit pulse accumulator

• Toggle-on-overflow feature for pulse-width modulator (PWM) generation

• External timer clock input (SYNCA/SYNCB)



Preliminary

23-1


23.3

Block Diagram

CLK[1:0]

System

Clock

Divide by 2

PR[2:0]

Prescaler

PACLK

PACLK/256

PACLK/65536

MUX

X

Channel 3 Output Compare

TCRE

SYNCx

Pin

GPTCNTH:GPTCNTL

16-Bit Counter

Clear Counter

TOF

TOI

CxI

CxF

Interrupt

Logic

Interrupt

Request

TE

Channel 0

16-Bit Comparator

GPTC0H:GPTC0L

16-Bit Latch

CHANNEL 1

16-Bit Comparator

GPTC1H:GPTC1L

16-Bit Latch

C0F

EDG0A

EDG0B

C1F

EDG1A

EDG1B

Edge

Detect

Edge

Detect

IOS0

OM:OL0

TOV0

IOS1

OM:OL1

TOV1

PT0

LOGIC

PT1

LOGIC

CH. 0 Capture

CH. 0 Compare

CH. 1 Capture

CH. 1 Compare

GPTx0

Pin

GPTx1

Pin

Channel 2

Channel3

16-Bit Comparator

GPTC3H:GPTC3L

16-Bit Latch

C3F

EDG3A

EDG3B

Edge

Detect

IOS3

OM:OL3

TOV3

PT3

LOGIC

CH.3 Capture

PA Input

CH. 3 Compare

PAOVF GPTPACNTH:GPTPACNTL

PEDGE

PAE

EDGE

DETECT

PACLK/65536

PACLK/256

Interrupt

Request

PAOVI

PAOVF

16-Bit Counter

Interrupt

Logic

PACLK

MUX

PAMOD

Divide-by-64

PAI

PAIF

Figure 23-1. GPT Block Diagram

PAIF

Divide by 2

GPTx3

Pin

System

Clock

23-2



Preliminary


23.4


This subsection describes the operation of the general purpose time module in low-power modes and halted mode of operation. Low-power modes are described in Chapter 7, “Power Management

.”

Table 23-1

shows the general purpose timer module operation in the low-power modes, and shows how this module may facilitate exit from each mode.

Table 23-1. Watchdog Module Operation in Low-power Modes

Low-power Mode

Wait

Doze

Stop

Halted

Watchdog Operation

Normal

Normal

Stopped

Normal

Mode Exit

No

No

No

No

General purpose timer operation stops in stop mode. When stop mode is exited, the general purpose timer continues to operate in its pre-stop mode state.

23.5


Table 23-2

provides an overview of the signal properties.


Pin

Name

GPTPORT

Register Bit

Function Reset State Pull-up

GPT0

GPT1

GPT2

PORTT

PORTT

PORTT n n n

0

1

2

GPT channel 0 IC/OC pin



Input

Input

Input

Active

Active

Active

GPT3 PORTT n 3 GPT channel 3 IC/OC or PA pin Input Active

SYNC n PORTE[3:0]

1

GPT counter synchronization Input Active

1

SYNCA is available on either PORTE3 or PORTE1; SYNCB is available on either PORTE2 or

PORTE0.

23.5.1

GPT[2:0]

The GPT[2:0] pins are for channel 2–0 input capture and output compare functions. These pins are available for general-purpose input/output (I/O) when not configured for timer functions.

23.5.2

GPT3

The GPT3 pin is for channel 3 input capture and output compare functions or for the pulse accumulator input. This pin is available for general-purpose I/O when not configured for timer functions.



Preliminary

23-3


23.5.3

SYNC

n

The SYNC n pin is for synchronization of the timer counter. It can be used to synchronize the counter with externally-timed or clocked events. A high signal on this pin clears the counter.

23.6


Table 18-4 shows the memory map of the GPT module. The base address for GPT is IPSBAR +

0x1A_0000.

NOTE

Reading reserved or unimplemented locations returns zeros. Writing to reserved or unimplemented locations has no effect.

Table 23-3. QSPI Memory Map

IPSBAR

Offset

1

Register

Width

(bits)


0x1A_0000 GPT IC/OC Select Register (GPTIOS)

0x1A_0001 GPT Compare Force Register (GPTCFORC)

0x1A_0002 GPT Output Compare 3 Mask Register (GPTOC3M)

0x1A_0003 GPT Output Compare 3 Data Register (GPTOC3D)

0x1A_0004 GPT Counter Register High (GPTCNTH)

2

0x1A_0005 GPT Counter Register Low (GPTCNTL)

2

0x1A_0006 GPT System Control Register 1 (GPTSCR1)

0x1A_0008 GPT Toggle-on-Overflow Register (GPTTOV)

0x1A_0009 GPT Control Register 1 (GPTCTL1)

0x1A_000B GPT Control Register 2 (GPTCTL2)

0x1A_000C GPT Interrupt Enable Register (GPTIE)

0x1A_000D GPT System Control Register 2 (GPTSCR2)

0x1A_000E GPT Flag Register 1 (GPTFLG1)

0x1A_000F GPT Flag Register 2 (GPTFLG2)

0x1A_0010 GPT Channel 0 Register High (GPTC0H)

2

0x1A_0011 GPT Channel 0 Register Low (GPTC0L)

2


2


2


2


2


2


8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

R/W

R/W

R/W

R/W

R

R

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

0x00

23.6.1/23-5

23.6.2/23-6

23.6.3/23-6

23.6.4/23-7

23.6.5/23-7

23.6.5/23-7

23.6.6/23-8

23.6.7/23-9

23.6.8/23-9

23.6.9/23-10

23.6.10/23-10

23.6.11/23-11

23.6.12/23-12

23.6.13/23-12

23.6.14/23-13

23.6.14/23-13

23.6.14/23-13

23.6.14/23-13

23.6.14/23-13

23.6.14/23-13

23.6.14/23-13

23-4



Preliminary


Table 23-3. QSPI Memory Map (continued)

IPSBAR

Offset

1

Register


2

Width

(bits)

Access

0x1A_0018 Pulse Accumulator Control Register (GPTPACTL)

0x1A_0019

0x1A_001A Pulse Accumulator Counter Register High

(GPTPACNTH)

2

0x1A_001B Pulse Accumulator Counter Register Low (GPTPACNTL)

2

0x1A_001D GPT Port Data Register (GPTPORT)

0x1A_001E

Pulse Accumulator Flag Register (GPTPAFLG)

GPT Port Data Direction Register (GPTDDR)

8

8

8

8

8

8

8

R/W

R/W

R/W

R/W

R/W

R/W

0x1A_001F GPT Test Register (GPTTST) 8

1

2


This register is 16 bits wide, and should be read using only word accesses.

Reset Value

0x00

0x00

0x00

0x00

Section/Page

23.6.14/23-13

18.6.15/18-19

23.6.16/23-14

23.6.17/23-15

23.6.17/23-15

23.6.18/23-16

23.6.19/23-16

23.6.1

GPT Input Capture/Output Compare Select Register (GPTIOS)

IPSBAR

Offset:

0x1A_0000 (GPTIOS)

7

0 R

W

Reset:

6

0

5

0

4

0

3 2


IOS

1

0 0 0 0 0 0 0

Figure 23-2. GPT Input Capture/Output Compare Select Register (GPTIOS)

0

0

Table 23-4. GPTIOS Field Descriptions



3–0

IOS

I/O select. The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels.

These bits are read anytime (always read 0x00), write anytime.

1 Output compare enabled

0 Input capture enabled



Preliminary

23-5


23.6.2

GPT Compare Force Register (GPCFORC)

IPSBAR

Offset:

0x1A_0001 (GPCFORC)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3 2


FOC

0 0 0 0 0

Figure 23-3. GPT Input Compare Force Register (GPCFORC)

1

0

0

0

Table 23-5. GPTCFORC Field Descriptions



3–0

FOC

Force output compare.Setting an FOC bit causes an immediate output compare on the corresponding channel.

Forcing an output compare does not set the output compare flag. These bits are read anytime, write anytime.

1 Force output compare

0 No effect

NOTE

A successful channel 3 output compare overrides any compare on channels

2:0. For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit.

23.6.3

GPT Output Compare 3 Mask Register (GPTOC3M)

IPSBAR

Offset:

0x1A_0002 (GPTOC3M)

7

0

6

0 R

W

Reset:

5

0

4

0

3 2


OC3M

1

0 0 0 0 0 0

Figure 23-4. GPT Output Compare 3 Mask Register (GPTOC3M)

0

0

0

23-6



Preliminary


Table 23-6. GPTOC3M Field Descriptions



3–0

OC3M

Output compare 3 mask. Setting an OC3M bit configures the corresponding PORTT

(IOSx = 1). The OC3M n bits do not change the state of the PORTT n DDR bits. These bits are read anytime, write anytime.

1 Corresponding PORTT n pin configured as output

0 No effect n pin to be an output. OC3M n makes the GPT port pin an output regardless of the data direction bit when the pin is configured for output compare

23.6.4

GPT Output Compare 3 Data Register (GPTOC3D)

IPSBAR

Offset:

0x1A_0003 (GPTOC3D)

7

0

6

0 R

W

Reset:

5

0

4

0

3 2


OC3D

1

0 0 0 0 0 0

Figure 23-5. GPT Output Compare 3 Data Register (GPTOC3D)

0

0

0

Table 23-7. GPTOC3D Field Descriptions



3–0

OC3D

Output compare 3 data. When a successful channel 3 output compare occurs, these bits transfer to the PORTT data register if the corresponding OC3M n bits are set. These bits are read anytime, write anytime.

n

NOTE

A successful channel 3 output compare overrides any channel 2:0 compares.

For each OC3M bit that is set, the output compare action reflects the corresponding OC3D bit.

23.6.5

GPT Counter Register (GPTCNT)

IPSBAR

Offset:

0x1A_0004 (GPTCNT)

14 13 15

R

W

Reset 0 0 0

12 11 10 9 8

CNTR

7 6 5

0 0 0 0 0 0 0 0

Figure 23-6. GPT Counter Register (GPTCNT)

4

0

Access: Supervisor read-only

3

0

2

0

1

0

0

0



Preliminary

23-7


Table 23-8. GPTCNT Field Descriptions


15–0

CNTR

Read-only field that provides the current count of the timer counter. To ensure coherent reading of the timer counter, such that a timer rollover does not occur between two back-to-back 8-bit reads, it is recommended that only word

(16-bit) accesses be used.

A write to GPTCNT may have an extra cycle on the first count because the write is not synchronized with the prescaler clock. The write occurs at least one cycle before the synchronization of the prescaler clock.

These bits are read anytime. They should be written to only in test (special) mode; writing to them has no effect in normal modes.

23.6.6

GPT System Control Register 1 (GPTSCR1)

IPSBAR

Offset:

0x1A_0006 (GPTSCR1)

7 6

0 R

W

Reset:

GPTEN

0

5 4

TFFCA

3

0

2

0


0 0 0 0 0

Figure 23-7. GPT System Control Register 1 (GPTSCR1)

1

0

0

0

0

0

Table 23-9. GPTSCR1 Field Descriptions


7

GPTEN

Enables the general purpose timer. When the timer is disabled, only the registers are accessible. Clearing GPTEN reduces power consumption. These bits are read anytime, write anytime.

1 GPT enabled

0 GPT and GPT counter disabled


4

TFFCA

Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers (GPTFLG1 and GPTFLG2) and the PA flag register (GPTPAFLG). TFFCA eliminates the software overhead of a separate clear sequence. See

Figure 23-8

.

When TFFCA is set:

• An input capture read or a write to an output compare channel clears the corresponding channel flag, CxF.

• Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag.

• Any access of the PA counter registers (GPTPACNT) clears both the PAOVF and PAIF flags in GPTPAFLG.

Writing logic 1s to the flags clears them only when TFFCA is clear.

1 Fast flag clearing

0 Normal flag clearing


23-8



Preliminary


Write GPTFLG1 Register

Data Bit n

C n F

Clear

C n F Flag

TFFCA

Read GPTC n Registers

Write GPTC n Registers

Figure 23-8. Fast Clear Flag Logic

23.6.7

GPT Toggle-On-Overflow Register (GPTTOV)

IPSBAR

Offset:

0x1A_0008 (GPTTOV)

7

0 R

W

Reset: 0

6

0

5

0

4

0

3 2


TOV

0 0 0 0 0

Figure 23-9. GPT Toggle-On-Overflow Register (GPTTOV)

1

0

0

0

Table 23-10. GPTTOV Field Description



3–0

TOV

Toggles the output compare pin on overflow for each channel. This feature only takes effect when in output compare mode. When set, it takes precedence over forced output compare but not channel 3 override events. These bits are read anytime, write anytime.

1 Toggle output compare pin on overflow feature enabled

0 Toggle output compare pin on overflow feature disabled

23.6.8

GPT Control Register 1 (GPTCTL1)

IPSBAR

Offset:

0x1A_0009 (GPTCTL1)

7 6

R

W

Reset:

OM3

0

OL3

5

OM2

4

OL2

3

OM1

2

OL1

0 0 0 0 0

Figure 23-10. GPT Control Register 1 (GPTCTL1)


1

OM0

0

0

OL0

0



Preliminary

23-9


Table 23-11. GPTCL1 Field Descriptions


7–0

OMx/OLx

Output mode/output level. Selects the output action to be taken as a result of a successful output compare on each channel. When either OM n or OL n is set and the IOS n bit is set, the pin is an output regardless of the state of the corresponding DDR bit. These bits are read anytime, write anytime.

00 GPT disconnected from output pin logic

01 Toggle OC n output line

10 Clear OC n output line

11 Set OC n line

Note: Channel 3 shares a pin with the pulse accumulator input pin. To use the PAI input, clear both the OM3 and

OL3 bits and clear the OC3M3 bit in the output compare 3 mask register.

23.6.9

GPT Control Register 2 (GPTCTL2)

IPSBAR

Offset:

0x1A_000B (GPTCTL2)

7 6

R

W

Reset:

EDG3B

0

EDG3A

5

EDG2B

4

EDG2A

3

EDG1B

2


EDG1A

0 0 0 0 0

Figure 23-11. GPT Control Register 2(GPTCTL2)

1

EDG0B

0

0

EDG0A

0

Table 23-12. GPTLCTL2 Field Descriptions


7–0

EDGn[B:A]

Input capture edge control. Configures the input capture edge detector circuits for each channel. These bits are read anytime, write anytime.

00 Input capture disabled

01 Input capture on rising edges only

10 Input capture on falling edges only

11 Input capture on any edge (rising or falling)

23.6.10 GPT Interrupt Enable Register (GPTIE)

IPSBAR

Offset:

0x1A_000C (GPTIE)

7

0 R

W

Reset: 0

6

0

5

0

4

0

3 2


0 0 0 0 0

Figure 23-12. GPT Interrupt Enable Register (GPTIE)

CI

1

0

0

0

23-10



Preliminary


Table 23-13. GPTIE Field Descriptions



3–0

C n l

Channel interrupt enable. Enables the C[3:0]F flags in GPT flag register 1 to generate interrupt requests for each channel. These bits are read anytime, write anytime.

1 Corresponding channel interrupt requests enabled

0 Corresponding channel interrupt requests disabled

23.6.11 GPT System Control Register 2 (GPTSCR2)

IPSBAR

Offset:

0x1A_000D (GPTSCR2)

7 6

0 R

W

Reset:

TOI

0

5

PUPT

4

RDPT

3

TCRE

2


0 0 0 0 0

Figure 23-13. GPT System Control Register 2 (GPTSCR2)

1

PR

0

0

0

Table 23-14. GPTSCR2 Field Descriptions

Field

7

TOI

6

5

PUPT

4

RDPT

3

TCRE

Description

Enables timer overflow interrupt requests.

1 Overflow interrupt requests enabled

0 Overflow interrupt requests disabled


Enables pull-up resistors on the GPT ports when the ports are configured as inputs.

1 Pull-up resistors enabled

0 Pull-up resistors disabled

GPT drive reduction. Reduces the output driver size.

1 Output drive reduction enabled

0 Output drive reduction disabled

Enables a counter reset after a channel 3 compare.

1 Counter reset enabled

0 Counter reset disabled

Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT counter registers remain at

0x0000 all the time. When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to 0x0000.



Preliminary

23-11


Field

2–0

PR

Table 23-14. GPTSCR2 Field Descriptions (continued)

Description

Prescaler bits. Select the prescaler divisor for the GPT counter.

000 Prescaler divisor 1








Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled clock when the clock count transitions to 0x0000.)

23.6.12 GPT Flag Register 1 (GPTFLG1)

IPSBAR

Offset:

0x1A_000E (GPTFLG1)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3 2

0 0 0 0

Figure 23-14. GPT Flag Register 1 (GPTFLG1)

0


CF

1

0

0

0

Table 23-15. GPTFLG1 Field Descriptions



3–0

C n F

Channel flags. A channel flag is set when an input capture or output compare event occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0 has no effect).

Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, an input capture read or an output compare write clears the corresponding channel flag. When a channel flag is set, it does not inhibit subsequent output compares or input captures.

23.6.13 GPT Flag Register 2 (GPTFLG2)

IPSBAR

Offset:

0x1A_000F (GPTFLG2)

7 6

0 R

W

Reset:

TOF

0

5

0

4

0

3 2

0 0 0 0

Figure 23-15. GPT Flag Register 2 (GPTFLG2)

0


CF

1

0

0

0

23-12



Preliminary


Table 23-16. GPTFLG2 Field Descriptions


7

TOF

Timer overflow flag. Set when the GPT counter rolls over from 0xFFFF to 0x0000. If the TOI bit in GPTSCR2 is also set, TOF generates an interrupt request. This bit is read anytime, write anytime (writing 1 clears the flag, and writing

0 has no effect).

1 Timer overflow

0 No timer overflow

Note: When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the

GPT counter registers go from 0xFFFF to 0x0000. When TOF is set, it does not inhibit subsequent overflow events.


3–0

C n F

Channel flags. A channel flag is set when an input capture or output compare event occurs. These bits are read anytime, write anytime (writing 1 clears the flag, writing 0 has no effect).

Note: When the fast flag clear all bit, GPTSCR1[TFFCA], is set, any access to the GPT counter registers clears GPT flag register 2.

23.6.14 GPT Channel Registers (GPTC

n

)

IPSBAR

Offset:

0x1A_0010, 0x1A_0012, 0x1A_0014, 0x1A_0016, (GPTC n )

14 13 12 11 10 9 8 15

R

W

Reset 0 0 0 0 0 0 0 0

CCNT

7

0

6

0

5

0

Figure 23-16. GPT Channel[0:3] Register (GPTC n )

4

0

3

0


2 1 0

0 0 0

Table 23-17. GPTC n Field Descriptions


15–0

CCNT

When a channel is configured for input capture (IOS n = 0), the GPT channel registers latch the value of the free-running counter when a defined transition occurs on the corresponding input capture pin.

When a channel is configured for output compare (IOS n = 1), the GPT channel registers contain the output compare value.

To ensure coherent reading of the GPT counter, such that a timer rollover does not occur between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime (for the output compare channel); writing to the input capture channel has no effect.

23.6.15 Pulse Accumulator Control Register (GPTPACTL)

IPSBAR

Offset:

0x1A_0018 (GPTPACTL)

6 7

0 R

W

Reset:

PAE

5

PAMOD

4

PEDGE

3

CLK

2


1

PAOVI

0 0 0 0 0 0

Figure 23-17. Pulse Accumulator Control Register (GPTPACTL)

0

0

PAI

0



Preliminary

23-13


Table 23-18. GPTPACTL Field Descriptions


7

6

PAE

5

PAMOD

Pulse accumulator mode. Selects event counter mode or gated time accumulation mode.

1 Gated time accumulation mode

0 Event counter mode

4

PEDGE

Pulse accumulator edge. Selects falling or rising edges on the PAI pin to increment the counter.

In event counter mode (PAMOD = 0):

1 Rising PAI edge increments counter

0 Falling PAI edge increments counter

In gated time accumulation mode (PAMOD = 1):

1 Low PAI input enables divide-by-64 clock to pulse accumulator and trailing rising edge on PAI sets PAIF flag.

0 High PAI input enables divide-by-64 clock to pulse accumulator and trailing falling edge on PAI sets PAIF flag.

Note: The timer prescaler generates the divide-by-64 clock. If the timer is not active, there is no divide-by-64 clock.

To operate in gated time accumulation mode:

1. Apply logic 0 to RSTI pin.

2. Initialize registers for pulse accumulator mode test.

3. Apply appropriate level to PAI pin.

4. Enable GPT.

3–2

CLK

Select the GPT counter input clock. Changing the CLK bits causes an immediate change in the GPT counter clock input.

00 GPT prescaler clock (When PAE = 0, the GPT prescaler clock is always the GPT counter clock.)

01 PACLK

10 PACLK/256

11 PACLK/65536

1

PAOVI

0

PAI


Enables the pulse accumulator.

1 Pulse accumulator enabled

0 Pulse accumulator disabled

Note: The pulse accumulator can operate in event mode even when the GPT enable bit, GPTEN, is clear.

Pulse accumulator overflow interrupt enable. Enables the PAOVF flag to generate interrupt requests.

1 PAOVF interrupt requests enabled

0 PAOVF interrupt requests disabled

Pulse accumulator input interrupt enable. Enables the PAIF flag to generate interrupt requests.

1 PAIF interrupt requests enabled

0 PAIF interrupt requests disabled

23.6.16 Pulse Accumulator Flag Register (GPTPAFLG)

IPSBAR

Offset:

0x1A_0019 (GPTPAFLG)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3

0

2

0


0 0 0 0 0

Figure 23-18. Pulse Accumulator Flag Register (GPTPAFLG)

1

PAOVF

0

0

PAIF

0

23-14



Preliminary


Table 23-19. GPTPAFLG Field Descriptions



1

PAOVF

Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the

GPTPACTL[PAOVI] bit is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write anytime. (Writing 1 clears the flag; writing 0 has no effect.)

1 Pulse accumulator overflow

0 No pulse accumulator overflow

0

PAIF

Pulse accumulator input flag. Set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the

PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to it.

1 Active PAI input

0 No active PAI input

NOTE

When the fast flag clear all enable bit (GPTSCR1[TFFCA]) is set, any access to the pulse accumulator counter registers clears all the flags in

GPTPAFLG.

23.6.17 Pulse Accumulator Counter Register (GPTPACNT)

IPSBAR

Offset:

0x1A_001A (GPTPACNT)

14 13 12 15

R

W

Reset 0 0 0 0

11

0

10

0

9

0

8

0

7

PACNT

0

6

0

5

0

4

0

3

0

Figure 23-19. Pulse Accumulator Counter Register (GPTPACNT)


2 1 0

0 0 0

Table 23-20. GPTPACR Field Descriptions


15–0

PACNT

Contains the number of active input edges on the PAI pin since the last reset.

Note: Reading the pulse accumulator counter registers immediately after an active edge on the PAI pin may miss the last count since the input first has to be synchronized with the bus clock.

To ensure coherent reading of the PA counter, such that the counter does not increment between back-to-back 8-bit reads, it is recommended that only word (16-bit) accesses be used. These bits are read anytime, write anytime.



Preliminary

23-15


23.6.18 GPT Port Data Register (GPTPORT)

IPSBAR

Offset:

0x1A_001D (GPTPORT)

7

0

6

0 R

W

Reset: 0

5

0

4

0

3 2

0 0 0 0 0

Figure 23-20. GPT Port Data Register (GPTPORT)


PORTT

1

0

0

0

Table 23-21. GPTPORT Field Descriptions



3–0

PORTT

GPT port input capture/output compare data. Data written to GPTPORT is buffered and drives the pins only when they are configured as general-purpose outputs.

Reading an input (DDR bit = 0) reads the pin state; reading an output (DDR bit = 1) reads the latched value. Writing to a pin configured as a GPT output does not change the pin state. These bits are read anytime (read pin state when corresponding PORTT n bit is 0, read pin driver state when corresponding GPTDDR bit is 1), write anytime.

23.6.19 GPT Port Data Direction Register (GPTDDR)

Field

GPT Function

7 6

—

—

5 4 3

Pulse Accumulator Function —

PAI

Reset

R/W

Address

0000_0000

R/W

IPSBAR + 0x1A_001E

Figure 23-21. GPT Port Data Direction Register (GPTDDR)

DDRT

IC/OC

—

Table 23-22. GPTDDR Field Descriptions

Bit(s)

7–4

3–0

Name

—

DDRT

0

Description


Control the port logic of PORTT n . Reset clears the PORTT n data direction register, configuring all GPT port pins as inputs. These bits are read anytime, write anytime.

1 Corresponding pin configured as output

0 Corresponding pin configured as input

23-16



Preliminary


23.7


The general purpose timer (GPT) module is a 16-bit, 4-channel timer with input capture and output compare functions and a pulse accumulator.

23.7.1

Prescaler

The prescaler divides the module clock by 1 or 16. The PR[2:0] bits in GPTSCR2 select the prescaler divisor.

23.7.2

Input Capture

Clearing an I/O select bit (IOS n ) configures channel n as an input capture channel. The input capture function captures the time at which an external event occurs. When an active edge occurs on the pin of an input capture channel, the timer transfers the value in the GPT counter into the GPT channel registers

(GPTC n ).

The minimum pulse width for the input capture input is greater than two module clocks.

The input capture function does not force data direction. The GPT port data direction register controls the data direction of an input capture pin. Pin conditions such as rising or falling edges can trigger an input capture only on a pin configured as an input.

An input capture on channel n sets the C n F flag. The C n I bit enables the C n F flag to generate interrupt requests.

23.7.3

Output Compare

Setting an I/O select bit (IOS n ) configures channel n as an output compare channel. The output compare function can generate a periodic pulse with a programmable polarity, duration, and frequency. When the

GPT counter reaches the value in the channel registers of an output compare channel, the timer can set, clear, or toggle the channel pin. An output compare on channel n sets the C n F flag. The C n I bit enables the

C n F flag to generate interrupt requests.

The output mode (OM n) and level bits (OL n) select, set, clear, or toggle on output compare. Clearing both

OM n and OL n disconnects the pin from the output logic.

Setting a force output compare bit (FOC n ) causes an output compare on channel n . A forced output compare does not set the channel flag.

A successful output compare on channel 3 overrides output compares on all other output compare channels. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, depending on the output compare 3 mask register. The output compare 3 mask register masks the bits in the output compare 3 data register. The GPT counter reset enable bit, TCRE, enables channel 3 output compares to reset the GPT counter. A channel 3 output compare can reset the

GPT counter even if the OC3/PAI pin is being used as the pulse accumulator input.

An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit.



Preliminary

23-17


Writing to the PORTT n bit of an output compare pin does not affect the pin state. The value written is stored in an internal latch. When the pin becomes available for general-purpose output, the last value written to the bit appears at the pin.

23.7.4

Pulse Accumulator

The pulse accumulator (PA) is a 16-bit counter that can operate in two modes:

1. Event counter mode: counts edges of selected polarity on the pulse accumulator input pin, PAI

2. Gated time accumulation mode: counts pulses from a divide-by-64 clock

The PA mode bit (PAMOD) selects the mode of operation.

The minimum pulse width for the PAI input is greater than two module clocks.

23.7.5

Event Counter Mode

Clearing the PAMOD bit configures the PA for event counter operation. An active edge on the PAI pin increments the PA. The PA edge bit (PEDGE) selects falling edges or rising edges to increment the PA.

An active edge on the PAI pin sets the PA input flag (PAIF). The PA input interrupt enable bit (PAI) enables the PAIF flag to generate interrupt requests.

NOTE

The PAI input and GPT channel 3 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 3 output mode and output level bits, OM3 and OL3. Also clear the channel 3 output compare 3 mask bit (OC3M3).

The PA counter register (GPTPACNT) reflects the number of active input edges on the PAI pin since the last reset.

The PA overflow flag (PAOVF) is set when the PA rolls over from 0xFFFF to 0x0000. The PA overflow interrupt enable bit (PAOVI) enables the PAOVF flag to generate interrupt requests.

NOTE

The PA can operate in event counter mode even when the GPT enable bit

(GPTEN) is clear.

23.7.6

Gated Time Accumulation Mode

Setting the PAMOD bit configures the PA for gated time accumulation operation. An active level on the

PAI pin enables a divide-by-64 clock to drive the PA. The PA edge bit (PEDGE) selects low levels or high levels to enable the divide-by-64 clock.

The trailing edge of the active level at the PAI pin sets the PA input flag (PAIF). The PA input interrupt enable bit (PAI) enables the PAIF flag to generate interrupt requests.

23-18



Preliminary


NOTE

The PAI input and GPT channel 3 use the same pin. To use the PAI input, disconnect it from the output logic by clearing the channel 3 output mode

(OM3) and output level (OL3) bits. Also clear the channel 3 output compare mask bit (OC3M3).

The PA counter register (GPTPACNT) reflects the number of pulses from the divide-by-64 clock since the last reset.

NOTE

The GPT prescaler generates the divide-by-64 clock. If the timer is not active, there is no divide-by-64 clock.

PULSE

ACCUMULATOR

PAD

CHANNEL 3 OUTPUT COMPARE

OM3

OL3

OC3M3

Figure 23-22. Channel 3 Output Compare/Pulse Accumulator Logic

23.7.7

General-Purpose I/O Ports

An I/O pin used by the timer defaults to general-purpose I/O unless an internal function that uses that pin is enabled.

The PORTT n pins can be configured for either an input capture function or an output compare function.

The IOS n bits in the GPT IC/OC select register configure the PORTT n pins as either input capture or output compare pins.

The PORTT n data direction register controls the data direction of an input capture pin. External pin conditions trigger input captures on input capture pins configured as inputs.

To configure a pin for input capture:

1. Clear the pin’s IOS bit in GPTIOS.

2. Clear the pin’s DDR bit in PORTT n DDR.

3. Write to GPTCTL2 to select the input edge to detect.

PORTT n DDR does not affect the data direction of an output compare pin. The output compare function overrides the data direction register but does not affect the state of the data direction register.

To configure a pin for output compare:

1. Set the pin’s IOS bit in GPTIOS.

2. Write the output compare value to GPTC n .



Preliminary

23-19


3. Clear the pin’s DDR bit in PORTT n DDR.

4. Write to the OM n /OL n bits in GPTCTL1 to select the output action.

Table 23-23

shows how various timer settings affect pin functionality.

Table 23-23. GPT Settings and Pin Functions

GPTEN DDR

1

GPTIOS

EDGx

[B:A]

OMx/

OLx

2

OC3Mx

3

Pin

Data

Dir.

Pin

Driven by

Pin

Function

Comments

0 0 X

4

X X X In Ext.

Digital input GPT disabled by GPTEN = 0

0

1

1

1

1

0

1

0

X

0 (IC)

0

0

X

0 (IC disabled)

0

<> 0

X

X

X

X

X

0

0

0

Out Data reg.

Digital output GPT disabled by GPTEN = 0

In Ext.

Digital input Input capture disabled by EDG setting n

Out Data reg.

Digital output Input capture disabled by EDG n setting

In Ext.

IC and digital input

Normal settings for input capture

1

1

1

0

0

0

<> 0

<> 0

X

X

0

1

Out Data reg.

Digital output Input capture of data driven to output pin by CPU

In Ext.

IC and digital input

OC3M setting has no effect because

IOS = 0

1 1 0 <> 0 X 1 Out Data reg.

Digital output OC3M setting has no effect because

IOS = 0; input capture of data driven to output pin by CPU

1

1

1

1

1

0

1

0

1

0

1 (OC)

1

1

1

1

X

(3)

X

X

X

X

0

0

5

<> 0

<> 0

X

0

0

0

0

1

In Ext.

Digital input Output compare takes place but does not affect the pin because of the OM n /OL n setting

Out Data reg.

Digital output Output compare takes place but does not affect the pin because of the OM n /OL n setting

Out OC action Output compare

Pin readable only if DDR = 0

(5)

Out OC action Output compare

Pin driven by OC action

(5)

Out OC action/

OC3D n

Output compare

(ch 3)

Pin readable only if DDR = 0

6

1 1 1 X X 1 Out OC action/

OC3D n

Output compare/

OC3D n

(ch 3)

Pin driven by channel OC action and

OC3D n via channel 3 OC

(6)

1

2

When DDR set the pin as input (0), reading the data register will return the state of the pin. When DDR set the pin as output

(1), reading the data register will return the content of the data latch. Pin conditions such as rising or falling edges can trigger an input capture on a pin configured as an input.

OM n /OL n bit pairs select the output action to be taken as a result of a successful output compare. When either OM n or OL n is set and the IOS n bit is set, the pin is an output regardless of the state of the corresponding DDR bit.

23-20



Preliminary


3

4

5

6

Setting an OC3M bit configures the corresponding PORTT n pin to be output. OC3M n makes the PORTT n pin an output regardless of the data direction bit when the pin is configured for output compare (IOS n = 1). The OC3M n bits do not change the state of the PORTT n DDR bits.

X = Don’t care

An output compare overrides the data direction bit of the output compare pin but does not change the state of the data direction bit. Enabling output compare disables data register drive of the pin.

A successful output compare on channel 3 causes an output value determined by OC3D n value to temporarily override the output compare pin state of any other output compare channel.The next OC action for the specific channel will still be output to the pin. A channel 3 output compare can cause bits in the output compare 3 data register to transfer to the GPT port data register, depending on the output compare 3 mask register.

23.8

Reset

Reset initializes the GPT registers to a known startup state as described in Section 23.6, “Memory Map and Registers

.”

23.9

Interrupts

Table 23-24

lists the interrupt requests generated by the timer.

Table 23-24. GPT Interrupt Requests

Interrupt Request

Channel 3 IC/OC

Channel 2 IC/OC

Channel 1 IC/OC

Channel 0 IC/OC

PA overflow

PA input

Timer overflow

Flag

C3F

C2F

C1F

C0F

PAOVF

PAIF

TOF

Enable Bit

C3I

C2I

C1I

C0I

PAOVI

PAI

TOI

23.9.1

GPT Channel Interrupts (C

n

F)

A channel flag is set when an input capture or output compare event occurs. Clear a channel flag by writing a 1 to it.

NOTE

When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, an input capture read or an output compare write clears the corresponding channel flag.

When a channel flag is set, it does not inhibit subsequent output compares or input captures

23.9.2

Pulse Accumulator Overflow (PAOVF)

PAOVF is set when the 16-bit pulse accumulator rolls over from 0xFFFF to 0x0000. If the PAOVI bit in

GPTPACTL is also set, PAOVF generates an interrupt request. Clear PAOVF by writing a 1 to this flag.



Preliminary

23-21


NOTE


GPTPAFLG.

23.9.3

Pulse Accumulator Input (PAIF)

PAIF is set when the selected edge is detected at the PAI pin. In event counter mode, the event edge sets

PAIF. In gated time accumulation mode, the trailing edge of the gate signal at the PAI pin sets PAIF. If the

PAI bit in GPTPACTL is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to this flag.

NOTE


GPTPAFLG.

23.9.4

Timer Overflow (TOF)

TOF is set when the GPT counter rolls over from 0xFFFF to 0x0000. If the GPTSCR2[TOI] bit is also set,

TOF generates an interrupt request. Clear TOF by writing a 1 to this flag.

NOTE

When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get set even though the GPT counter registers go from 0xFFFF to

0x0000.

When the fast flag clear all bit (GPTSCR1[TFFCA]) is set, any access to the

GPT counter registers clears GPT flag register 2.

When TOF is set, it does not inhibit future overflow events.

23-22



Preliminary

Chapter 24


24.1

Introduction

This chapter describes the configuration and operation of the four direct memory access (DMA) timer modules (DTIM0, DTIM1, DTIM2, and DTIM3). These 32-bit timers provide input capture and reference compare capabilities with optional signaling of events using interrupts or DMA triggers. Additionally, programming examples are included.

NOTE

The designation ‘ n ’ is used throughout this section to refer to registers or signals associated with one of the four identical timer modules: DTIM0,

DTIM1, DTIM2, or DTIM3.

24.1.1

Overview

Each DMA timer module has a separate register set for configuration and control. The timers can be configured to operate from the internal bus clock or from an external clocking source using the DT n IN signal. If the internal bus clock is selected, it can be divided by 16 or 1. The selected clock source is routed to an 8-bit programmable prescaler that clocks the actual DMA timer counter register (DTCN n ). Using the

DTMR n , DTXMR n , DTCR n , and DTRR n registers, the DMA timer may be configured to assert an output signal, generate an interrupt, or initiate a DMA transfer on a particular event.

NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module” ) prior to configuring the DMA Timers.



Preliminary

24-1


Figure 24-1

is a block diagram of one of the four identical timer modules.

Internal Bus Clock

(÷1 or ÷16 )

DT n IN

DMA Timer

Clock

Generator clock

15 0

DMA Timer Mode Register (DTMR n )

Prescaler Mode Bits

7 0

DMA Timer Extended Mode

Register (DTXMR n )

Divider

Capture

Detection

31

DMA Timer Counter Register (DTCN n )

(contains incrementing value)

0

31

DMA Timer Capture Register (DTCR n )

(latches DTCN value when triggered by DT n IN)

0 31

DMA Timer Reference Register (DTRR n )

(reference value for comparison with DTCN)

0

7

DMA Timer Event Register (DTER n )

(indicates capture or when DTCN = DTRR n )

0

DT n OUT

To Interrupt controller

DMA Request

Figure 24-1. DMA Timer Block Diagram

24.1.2

Features

Each DMA timer module has the following features:

• Maximum timeout period of 266,521 seconds at 66 MHz (~74 hours)

• 15-ns resolution at 66 MHz

• Programmable sources for the clock input, including external clock

• Programmable prescaler

• Input-capture capability with programmable trigger edge on input pin

• Programmable mode for the output pin on reference compare

• Free run and restart modes

• Programmable interrupt or DMA request on input capture or reference-compare

24.2


The timer module registers, shown in Table 24-1

, can be modified at any time.

24-2



Preliminary


Table 24-1. DMA Timer Module Memory Map

IPSBAR Offset

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

0x00_0400

0x00_0440

0x00_0480

0x00_04C0

0x00_0402

0x00_0442

0x00_0482

0x00_04C2

0x00_0403

0x00_0443

0x00_0483

0x00_04C3

0x00_0404

0x00_0444

0x00_0484

0x00_04C4

0x00_0408

0x00_0448

0x00_0488

0x00_04C8

0x00_040C

0x00_044C

0x00_048C

0x00_04CC

Register

DMA Timer n Mode Register (DTMR n )

Width

(bits)

16

DMA Timer n Extended Mode Register (DTXMR n ) 8

DMA Timer n Event Register (DTER n )

DMA Timer n Reference Register (DTRR n )

DMA Timer n Capture Register (DTCR n )

DMA Timer n Counter Register (DTCN n )

8

32

32

32


R/W

R/W

R/W

R/W

R/W

R

0x0000

0x00

0x00

0x1111_1111

0x0000_0000

0x0000_0000

24.2.1/24-3

24.2.2/24-4

24.2.3/24-5

24.2.4/24-7

24.2.5/24-7

24.2.6/24-7

24.2.1

DMA Timer Mode Registers (DTMR

n

)

DTMRs, shown in

Figure 24-2

, program the prescaler and various timer modes.

IPSBAR

Offset:

0x00_0400 (

DTMR0

)

0x00_0440 ( DTMR1 )

0x00_0480 (

DTMR2

)

0x00_04C0 ( DTMR3 )

14 13 15

R

W

Reset 0 0 0

12

PS

11 10 9 8 7

CE

6 5 4 3


OM ORRI FRR

0 0 0 0 0 0 0 0

Figure 24-2. DMA Timer Mode Registers (DTMR n )

0 0

2

0

CLK

1

0

0

RST

0



Preliminary

24-3


Table 24-2. DTMR n Field Descriptions

Field

15–8

PS

7–6

CE

5

OM

4

ORRI

3

FRR

2–1

CLK

0

RST

Description

Prescaler value. The prescaler is programmed to divide the clock input (internal bus clock/(16 or 1) or clock on

DT n IN) by values from 1 (PS = 0x00) to 256 (PS = 0xFF).

Capture edge.

00 Disable capture event output

01 Capture on rising edge only

10 Capture on falling edge only

11 Capture on any edge

Output mode.

0 Active-low pulse for one internal bus clock cycle (-ns resolution at MHz).

1 Toggle output.

Output reference request, interrupt enable. If ORRI is set when DTER n [REF] = 1, a DMA request or an interrupt occurs, depending on the value of DTXMR n [DMAEN] (DMA request if =1, interrupt if =0).

0 Disable DMA request or interrupt for reference reached (does not affect DMA request or interrupt on capture function).

1 Enable DMA request or interrupt upon reaching the reference value.

Free run/restart

0 Free run. Timer count continues to increment after reaching the reference value.

1 Restart. Timer count is reset immediately after reaching the reference value.

Input clock source for the timer

00 Stop count

01 Internal bus clock divided by 1

10 Internal bus clock divided by 16. Note that this clock source is not synchronized with the timer; thus successive time-outs may vary slightly.

11 DT n IN pin (falling edge)

Reset timer. Performs a software timer reset similar to an external reset, although other register values can still be written while RST = 0. A transition of RST from 1 to 0 resets register values. The timer counter is not clocked unless the timer is enabled.

0 Reset timer (software reset)

1 Enable timer

24.2.2

DMA Timer Extended Mode Registers (DTXMR

n

)

The DTXMR n register programs DMA request and increment modes for the timers.

24-4



Preliminary


IPSBAR

Offset:

0x 00_04 02 ( DTXMR0 )

0x

00_044

2

(

DTXMR1

)

0x 00_048 2 ( DTXMR2 )

0x

00_04C

2

(

DTXMR3

)

7 6

0 R

W

R

W

Reset:

DMAEN

DMAEN

0

HALTED

5

0

0

4

0

0

3

0

0

2

0

0

0 0 0 0 0

Figure 24-3. DMA Timer Extended Mode Registers (DTXMR n )


1

0

0

0

0

MODE16

MODE16

0

Table 24-3. DTXMR n Field Descriptions


7

DMAEN

DMA request. Enables DMA request output on counter reference match or capture edge event.

0 DMA request disabled

1 DMA request enabled

6

HALTED

Controls the counter when the core is stopped. This allows debug mode to be entered without timer interrupts affecting the debug flow.

0 Timer function is not affected by core halt.

1 Timer stops counting while the core is halted.

Note: This bit is only applicable in reference compare mode.


0

MODE16

Selects the increment mode for the timer. MODE16 = 1 is intended to exercise the upper bits of the 32-bit timer in diagnostic software without requiring the timer to count through its entire dynamic range. When set, the counter’s upper 16 bits mirror its lower 16 bits. All 32 bits of the counter are still compared to the reference value.

0 Increment timer by 1

1 Increment timer by 65,537

24.2.3

DMA Timer Event Registers (DTER

n

)

DTER n , shown in

Figure 24-4

, reports capture or reference events by setting DTER n [CAP] or

DTER n [REF]. This reporting is done regardless of the corresponding DMA request or interrupt enable values, DTXMR n [DMAEN] and DTMR n [ORRI,CE].

Writing a 1 to either DTER n [REF] or DTER n [CAP] clears it (writing a 0 does not affect bit value); both bits can be cleared at the same time. If configured to generate an interrupt request, the REF and CAP bits should be cleared early in the interrupt service routine so the timer module can negate the interrupt request signal to the interrupt controller. If configured to generate a DMA request, the processing of the DMA data transfer automatically clears both the REF and CAP flags via the internal DMA ACK signal.



Preliminary

24-5


IPSBAR

Offset:

0x00_0403 (DTER0)

0x00_0443 (DTER1)

0x00_0483 (DTER2)

0x00_04C3 (DTER3)

7

0 R

W

Reset: 0

6

0

5

0

4

0

3

0

2

0

0 0 0 0 0

Figure 24-4. DMA Timer Event Registers (DTER n )

Table 24-4. DTER n Field Descriptions


1

REF w1c

0

0

CAP w1c

0

Field

7–2

1

REF

Description


Output reference event. The counter value, DTCN n, equals the reference value, DTRR n . Writing a one to REF clears the event condition. Writing a zero has no effect.

REF DTMR n [ORRI] DTXMR n [DMAEN]

1

1

0

1

1

X

0

0

1

1

X

0

1

0

1

No event

No request asserted

No request asserted

Interrupt request asserted

DMA request asserted

0

CAP

Capture event. The counter value has been latched into DTCR n . Writing a one to CAP clears the event condition.

Writing a zero has no effect.

CAP DTMR n [CE]

DTXMR n

[DMAEN]

1

1

1

1

1

1

1

0

1

01

10

10

11

11

XX

00

00

01

1

0

1

0

1

1

0

X

0

No event

Disable capture event output

Disable capture event output

Capture on rising edge & trigger interrupt

Capture on rising edge & trigger DMA

Capture on falling edge & trigger interrupt

Capture on falling edge & trigger DMA

Capture on any edge & trigger interrupt

Capture on any edge & trigger DMA

24-6



Preliminary


24.2.4

DMA Timer Reference Registers (DTRR

n

)

Each DTRR n

, shown in Figure 24-5 , contains the reference value compared with the respective

free-running timer counter (DTCN n ) as part of the output-compare function. The reference value is not matched until DTCN n equals DTRR n , and the prescaler indicates that DTCN n should be incremented again. Thus, the reference register is matched after DTRR n +1 time intervals.

IPSBAR

Offset:

0x

00_04

04

(

DTRR0

)

0x 00_044 4 ( DTRR1 )

0x

00_048

4

(

DTRR2

)

0x 00_04C 4 ( DTRR3 )


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

REF (32-bit reference value)

W

Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 24-5. DMA Timer Reference Registers (DTRR n )

24.2.5

DMA Timer Capture Registers (DTCR

n

)

Each DTCR n latches the corresponding DTCN n value during a capture operation when an edge occurs on

DT n IN, as programmed in DTMR n . The internal bus clock is assumed to be the clock source. DT n IN cannot simultaneously function as a clocking source and as an input capture pin. Indeterminate operation will result if DT n IN is set as the clock source when the input capture mode is used.

IPSBAR

Offset:

0x 00_04 08 ( DTCR0 )

0x

00_044

8

(

DTCR1

)

0x 00_048 8 ( DTCR2 )

0x

00_04C

8

(

DTCR3

)


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R CAP (32-bit capture counter value)

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 24-6. DMA Timer Capture Registers (DTCR n )

24.2.6

DMA Timer Counters (DTCN

n

)

The current value of the 32-bit DTCNs can be read at anytime without affecting counting. Any write to

DTCN n clears it. The timer counter increments on the clock source rising edge (internal bus clock ÷ 1, internal bus clock ÷ 16, or DT n IN).



Preliminary

24-7


IPSBAR

Offset:

0x 00_04 0C ( DTCN0 )

0x

00_044

C

(

DTCN1

)

0x 00_048 C ( DTCN2 )

0x

00_04C

C

(

DTCN3

)


31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W

CNT (32-bit timer counter value count)

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 24-7. DMA Timer Counters (DTCN n )

24.3


24.3.1

Prescaler

The prescaler clock input is selected from the internal bus clock (f sys

divided by 1 or 16) or from the corresponding timer input, DT n IN. DT n IN is synchronized to the internal bus clock, and the synchronization delay is between two and three internal bus clocks. The corresponding DTMR n [CLK] selects the clock input source. A programmable prescaler divides the clock input by values from 1 to 256.

The prescaler output is an input to the 32-bit counter, DTCN n .

24.3.2

Capture Mode

Each DMA timer has a 32-bit timer capture register (DTCR n ) that latches the counter value when the corresponding input capture edge detector senses a defined DT n IN transition. The capture edge bits

(DTMR n [CE]) select the type of transition that triggers the capture and sets the timer event register capture event bit, DTER n [CAP]. If DTER n [CAP] is set and DTXMR n [DMAEN] is one, a DMA request is asserted. If DTER n [CAP] is set and DTXMR n [DMAEN] is zero, an interrupt is asserted.

24.3.3

Reference Compare

Each DMA timer can be configured to count up to a reference value, at which point DTER n [REF] is set.

If DTMR n [ORRI] is one and DTXMR n [DMAEN] is zero, an interrupt is asserted. If DTMR n [ORRI] is one and DTXMR n [DMAEN] is one, a DMA request is asserted. If the free run/restart bit DTMR n [FRR] is set, a new count starts. If it is clear, the timer keeps running.

24.3.4

Output Mode

When a timer reaches the reference value selected by DTRR, it can send an output signal on DT n OUT.

DT n OUT can be an active-low pulse or a toggle of the current output, as selected by the DTMR n [OM] bit.

24.4


The general-purpose timer modules typically, but not necessarily, follow this program order:

• The DTMR n and DTXMR n registers are configured for the desired function and behavior.

— Count and compare to a reference value stored in the DTRR n register

24-8



Preliminary


— Capture the timer value on an edge detected on DT n IN

— Configure DT n OUT output mode

— Increment counter by 1 or by 65,537 (16-bit mode)

— Enable/disable interrupt or DMA request on counter reference match or capture edge

• The DTMR n [CLK] register is configured to select the clock source to be routed to the prescaler.

— Internal bus clock (can be divided by 1 or 16)

— DT n IN, the maximum value of DT n IN is 1/5 of the internal bus clock, as described in the device’s electrical characteristics

NOTE

DT n IN may not be configured as a clock source when the timer capture mode is selected, or indeterminate operation will result.

• The 8-bit DTMR n [PS] prescaler value is set.

• Using DTMR n [RST], the counter is cleared and started.

• Timer events are either handled with an interrupt service routine, a DMA request, or by a software polling mechanism.

24.4.1

Code Example

The following code provides an example of how to initialize and use DMA Timer0 for counting time-out periods.

DTMR0 EQU IPSBARx+0x400 ;Timer0 mode register

DTMR1 EQU IPSBARx+0x440 ;Timer1 mode register

DTRR0 EQU IPSBARx+0x404 ;Timer0 reference register

DTRR1 EQU IPSBARx+0x444 ;Timer1 reference register

DTCR0 EQU IPSBARx+0x408 ;Timer0 capture register

DTCR1 EQU IPSBARx+0x448 ;Timer1 capture register

DTCN0 EQU IPSBARx+0x40C ;Timer0 counter register

DTCN1 EQU IPSBARx+0x44C ;Timer1 counter register

DTER0 EQU IPSBARx+0x403 ;Timer0 event register

DTER1 EQU IPSBARx+0x443 ;Timer1 event register

* TMR0 is defined as: *

*[PS] = 0xFF, divide clock by 256

*[CE] = 00

*[OM] = 0 disable capture event output output=active-low pulse

*[ORRI] = 0,

*[FRR] = 1,

*[CLK] = 10,

*[RST] = 0, disable ref. match output restart mode enabled internal bus clock/16 timer0 disabled move.w #0xFF0C,D0 move.w D0,TMR0 move.l #0x0000,D0;writing to the timer counter with any move.l DO,TCN0 ;value resets it to zero move.l #0xAFAF,DO ;set the timer0 reference to be move.l #D0,TRR0 ;defined as 0xAFAF

The simple example below uses Timer0 to count time-out loops. A time-out occurs when the reference value, 0xAFAF, is reached.



Preliminary

24-9

DMA Timers (DTIM0–DTIM3) timer0_ex clr.l DO clr.l D1 clr.l D2 move.l #0x0000,D0 move.l D0,TCN0 move.b #0x03,D0 move.b D0,TER0 move.w TMR0,D0 bset #0,D0 move.w D0,TMR0

T0_LOOP move.b TER0,D1 btst #1,D1 beq T0_LOOP addi.l #1,D2 cmp.l #5,D2 beq T0_FINISH move.b #0x02,D0 move.b D0,TER0 jmp T0_LOOP

T0_FINISH

HALT

;reset the counter to 0x0000

;writing ones to TER0[REF,CAP]

;clears the event flags

;save the contents of TMR0 while setting

;the 0 bit. This enables timer 0 and starts counting

;load the value back into the register, setting TMR0[RST]

;load TER0 and see if

;TER0[REF] has been set

;Increment D2

;Did D2 reach 5? (i.e. timer ref has timed)

;If so, end timer0 example. Otherwise jump back.

;writing one to TER0[REF] clears the event flag

;End processing. Example is finished

24.4.2

Calculating Time-Out Values

The formula below determines time-out periods for various reference values:

Timeout period = ( ) × ( 1 or 16 ) × ( DTMR n [PS] 1 ) × ( DTRR n [REF] 1 )

When calculating time-out periods, add 1 to the prescaler to simplify calculating, because

DTMR n [PS] = 0x00 yields a prescaler of 1, and DTMR n [PS] = 0xFF yields a prescaler of 256.

Eqn. 24-1

For example, if a 66-MHz timer clock is divided by 16, DTMR n [PS] = 0x7F, and the timer is referenced at 0xFBC5 (64453 decimal), the time-out period is as follows:

Timeout period =

1

6

× 16 × ( + ) × ( 64453 1 ) = 2.00s

Eqn. 24-2

24-10



Preliminary

Chapter 25


25.1

Introduction

This chapter describes the queued serial peripheral interface (QSPI) module. Following a feature set overview is a description of operation including details of the QSPI’s internal RAM organization. The chapter concludes with the programming model and a timing diagram.

25.1.1

Block Diagram

Figure 25-1

illustrates the QSPI module.

Queue Control

Block

Queue

Pointer

4

Comparator

80-byte

QSPI

RAM

End Queue

Pointer

Done

QSPI

Address

Register

4

QSPI

Data

Register

Control Logic

Status

Regs

Control

Regs

Chip

Selects

Logic

Array 4

Command msb lsb

8/16 Bit Shift Reg.

Rx/Tx Data Reg.

QSPI_DIN

QSPI_DOUT

QSPI_CS[:0]

Delay

Counter

Internal Bus

Internal Bus

Clock (f sys

)

Divide by 2

Baud Rate

Generator

Figure 25-1. QSPI Block Diagram

QSPI_CLK



Preliminary

25-1


25.1.2

Overview

The queued serial peripheral interface module provides a serial peripheral interface with queued transfer capability. It allows users to queue up to 16 transfers at once, eliminating CPU intervention between transfers. Transfer RAM in the QSPI is indirectly accessible using address and data registers.

NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module” ) prior to configuring the QSPI Module.

25.1.3

Features

Features include the following:

• Programmable queue to support up to 16 transfers without user intervention

• Supports transfer sizes of 8 to 16 bits in 1-bit increments

• Four peripheral chip-select lines for control of up to 15 devices (All four chip selects may not be available on all devices. See Chapter 2, “Signal Descriptions,” for details on which chip-selects are pinned-out.)

• Baud rates from 129.4 Kbps to 16.6 Mbps at 66 MHz internal bus frequency

• Programmable delays before and after transfers

• Programmable QSPI clock phase and polarity

• Supports wraparound mode for continuous transfers

25.1.4


Because the QSPI module only operates in master mode, the master bit in the QSPI mode register

(QMR[MSTR]) must be set for the QSPI to function properly. If the master bit is not set, QSPI activity will be indeterminate. The QSPI can initiate serial transfers but cannot respond to transfers initiated by other QSPI masters.

25.2


The module provides access to as many as 15 devices with a total of seven signals: QSPI_DOUT,

QSPI_DIN, QSPI_CLK, QSPI_CS0, QSPI_CS1, and QSPI_CS2, and QSPI_CS3.

Peripheral chip-select signals, QSPI_CS n , are used to select an external device as the source or destination for serial data transfer. Signals are asserted whenever a command in the queue is executed. More than one chip-select signal can be asserted simultaneously.

Although QSPI_CS n will function as simple chip selects in most applications, up to 15 devices can be selected by decoding them with an external 4-to-16 decoder.

25-2



Preliminary


Table 25-1. QSPI Input and Output Signals and Functions

Signal Name

QSPI Data Output (QSPI_DOUT)

QSPI Data Input (QSPI_DIN)

Serial Clock (QSPI_CLK)

Peripheral Chip Selects (QSPI_CS n )

Hi-Z or Actively Driven

Configurable

N/A

Actively driven

Actively driven

Function

Serial data output from QSPI

Serial data input to QSPI

Clock output from QSPI

Peripheral selects

25.3


Table 25-2

is the QSPI register memory map. Reading reserved locations returns zeros.

Table 25-2. QSPI Memory Map

IPSBAR

Offset

1

0x00_0340

0x00_0344

0x00_0348

0x00_034C

Register

QSPI Mode Register (QMR)

QSPI Delay Register (QDLYR)

QSPI Wrap Register (QWR)

QSPI Interrupt Register (QIR)

Width

(bits)


16

16

16

16

R/W

R/W

R/W

2

R/W

2

R/W

2

0x00_0350 QSPI Address Register (QAR) 16

0x00_0354 QSPI Data Register (QDR) 16 R/W

1

2


See the register description for special cases. Some bits may be read- or write-only.

0x0104

0x0404

0x0000

0x0000

0x0000

0x0000

25.3.1/25-3

25.3.2/25-5

25.3.3/25-6

25.3.4/25-6

25.3.5/25-8

25.3.6/25-8

25.3.1

QSPI Mode Register (QMR)

The QMR, shown in

Figure 25-2

, determines the basic operating modes of the QSPI module. Parameters such as QSPI_CLK polarity and phase, baud rate, master mode operation, and transfer size are determined by this register. The data output high impedance enable, DOHIE, controls the operation of QSPI_DOUT between data transfers. When DOHIE is cleared, QSPI_DOUT is actively driven between transfers. When

DOHIE is set, QSPI_DOUT assumes a high impedance state.

NOTE

Because the QSPI does not operate in slave mode, the master mode enable bit (QMR[MSTR]) must be set for the QSPI module to operate correctly.


Offset:

0x00_0340

15 14

R

MSTR DOHIE

W

Reset 0 0

13

0

12

BITS

11 10 9 8

CPOL CPHA

7 6 5

0 0 0 0 1 0 0

Figure 25-2. QSPI Mode Register (QMR)

0

4

BAUD

3

0 0

2

1

1

0

0

0



Preliminary

25-3


Table 25-3. QMR Field Descriptions


15

MSTR

14

DOHIE

13–10

BITS

Master mode enable.

0 Reserved, do not use.

1 The QSPI is in master mode. Must be set for the QSPI module to operate correctly.

Data output high impedance enable. Selects QSPI_DOUT mode of operation.

0 Default value after reset. QSPI_DOUT is actively driven between transfers.

1 QSPI_DOUT is high impedance between transfers.

Transfer size. Determines the number of bits to be transferred for each entry in the queue.

BITS Bits per Transfer

0000

0001–0111

1000

1001

1010

1011

1100

1101

1110

1111

16

Reserved

8

9

10

11

12

13

14

15

9

CPOL

8

CPHA

7–0

BAUD

Clock polarity. Defines the clock polarity of QSPI_CLK.

0 The inactive state value of QSPI_CLK is logic level 0.

1 The inactive state value of QSPI_CLK is logic level 1.

Clock phase. Defines the QSPI_CLK clock-phase.

0 Data captured on the leading edge of QSPI_CLK and changed on the following edge of QSPI_CLK.

1 Data changed on the leading edge of QSPI_CLK and captured on the following edge of QSPI_CLK.

Baud rate divider. The baud rate is selected by writing a value in the range 2–255. A value of zero disables the QSPI.

A value of 1 is an invalid setting. The desired QSPI_CLK baud rate is related to the internal bus clock and

QMR[BAUD] by the following expression:

QMR[BAUD] = f sys/

/ (2 ×

[desired QSPI_CLK baud rate])

25-4



Preliminary

Figure 25-3

shows an example of a QSPI clocking and data transfer.

QSPI_CLK


QSPI_DOUT 15 14 13 12 11 10 msb

9 8 7 6 5 4 3 2 1 0

QSPI_DIN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A

B

QSPI_CS

QMR[CPOL] = 0

QMR[CPHA] = 1

QCR[CONT] = 0

Chip selects are active low

A = QDLYR[QCD]

B = QDLYR[DTL]

Figure 25-3. QSPI Clocking and Data Transfer Example

25.3.2

QSPI Delay Register (QDLYR)

IPSBAR

Offset:

0x00_0344

14 15

R

SPE

W

Reset 0 0

13

0

12 11

QCD

10 9 8 7 6 5

0 0 1 0 0 0 0 0

Figure 25-4. QSPI Delay Register (QDLYR)

Table 25-4. QDLYR Field Descriptions

4

0

DTL

3

0


2

1

1

0

0

0

Field

15

SPE

14–8

QCD

7–0

DTL

Description

QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in the command RAM.

Automatically cleared by the QSPI when a transfer completes. The user can also clear this bit to abort transfer unless

QIR[ABRTL] is set. The recommended method for aborting transfers is to set QWR[HALT].

QSPI_CLK delay. When the DSCK bit in the command RAM is set this field determines the length of the delay from assertion of the chip selects to valid QSPI_CLK transition. See

Section 25.4.3, “Transfer Delays”

for information on setting this bit field.

Delay after transfer. When the DT bit in the command RAM is set this field determines the length of delay after the serial transfer.



Preliminary

25-5


25.3.3

QSPI Wrap Register (QWR)

IPSBAR

Offset:

0x00_0348

15 14 13 12

R

HALT WREN WRTO CSIV

W

Reset 0 0 0 0

11 10 9

ENDQP

8 7 6 5

CPTQP

0 0 0 0 0 0

Figure 25-5. QSPI Wrap Register (QWR)

0

4

0

3

0


2 1

NEWQP

0 0

0

0

Table 25-5. QWR Field Descriptions


15

HALT

14

WREN

13

WRTO

12

CSIV

Halt transfers. Assertion of this bit causes the QSPI to stop execution of commands once it has completed execution of the current command.

Wraparound enable. Enables wraparound mode.

0 Execution stops after executing the command pointed to by QWR[ENDQP].

1 After executing command pointed to by QWR[ENDQP], wrap back to entry zero, or the entry pointed to by

QWR[NEWQP] and continue execution.

Wraparound location. Determines where the QSPI wraps to in wraparound mode.

0 Wrap to RAM entry zero.

1 Wrap to RAM entry pointed to by QWR[NEWQP].

QSPI_CS inactive level.

0 QSPI chip select outputs return to zero when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 0, chip selects are active high).

1 QSPI chip select outputs return to one when not driven from the value in the current command RAM entry during a transfer (that is, inactive state is 1, chip selects are active low).

11–8

ENDQP

End of queue pointer. Points to the RAM entry that contains the last transfer description in the queue.

7–4

CPTQP

Completed queue entry pointer. Points to the RAM entry that contains the last command to have been completed.

This field is read only.

3–0

NEWQP

Start of queue pointer. This 4-bit field points to the first entry in the RAM to be executed on initiating a transfer.

25.3.4

QSPI Interrupt Register (QIR)

IPSBAR

Offset:

0x00_034C

15 14

R

WCEFB ABRTB

W

Reset 0 0

13

0

0

12

0

11

0

10

ABRTL WCEFE ABRTE

0

9

0

0

8

SPIFE

0

7

0

0

6

0

0

Figure 25-6. QSPI Interrupt Register (QIR)

0

5

0


4 3 2 1 0

0 WCEF ABRT 0 SPIF

0 w1c w1c

0 0 0 w1c

0

25-6



Preliminary


Table 25-6. QIR Field Descriptions


15

WCEFB

Write collision access error enable. A write collision occurs during a data transfer when the RAM entry containing the current command is written to by the CPU with the QDR. When this bit is asserted, the write access to QDR results in an access error.

14

ABRTB

Abort access error enable. An abort occurs when QDLYR[SPE] is cleared during a transfer. When set, an attempt to clear QDLYR[SPE] during a transfer results in an access error.

13

12

ABRTL


Abort lock-out. When set, QDLYR[SPE] cannot be cleared by writing to the QDLYR. QDLYR[SPE] is only cleared by the QSPI when a transfer completes.

7–4

3

WCEF

2

ABRT

1

0

SPIF

11

WCEFE

Write collision (WCEF) interrupt enable.

0 Write collision interrupt disabled

1 Write collision interrupt enabled

10

ABRTE

Abort (ABRT) interrupt enable.

0 Abort interrupt disabled

1 Abort interrupt enabled

9

8

SPIFE


QSPI finished (SPIF) interrupt enable.

0 SPIF interrupt disabled

1 SPIF interrupt enabled


Write collision error flag. Indicates that an attempt has been made to write to the RAM entry that is currently being executed. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.

Abort flag. Indicates that QDLYR[SPE] has been cleared by the user writing to the QDLYR rather than by completion of the command queue by the QSPI. Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.


QSPI finished flag. Asserted when the QSPI has completed all the commands in the queue. Set on completion of the command pointed to by QWR[ENDQP], and on completion of the current command after assertion of

QWR[HALT]. In wraparound mode, this bit is set every time the command pointed to by QWR[ENDQP] is completed.

Writing a 1 to this bit (w1c) clears it and writing 0 has no effect.

The command and data RAM in the QSPI are indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.

A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes the value in QAR to increment.

Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR].

This also causes QAR to increment. A read access requires a single wait state.

NOTE

The QAR does not wrap after the last queue entry within each section of the

RAM. The application software must handle address range errors.



Preliminary

25-7


25.3.5

QSPI Address Register (QAR)

The QAR is used to specify the location in the QSPI RAM that read and write operations affect. As shown

in Section 25.4.1, “QSPI RAM”

, the transmit RAM is located at addresses 0x0 to 0xF, the receive RAM is located at 0x10 to 0x1F, and the command RAM is located at 0x20 to 0x2F. These addresses refer to the

QSPI RAM space, not the device memory map.


Offset:

0x0x00_0350

15

R 0

W

Reset 0

14

0

0

13

0

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0 0 0

1

0

0

0 0 0 0 0 0 0 0

Figure 25-7. QSPI Address Register (QAR)

3

ADDR

2

25.3.6

QSPI Data Register (QDR)

The QDR, shown in Figure 25-8 , is used to access QSPI RAM indirectly. The CPU reads and writes all

data from and to the QSPI RAM through this register.


Offset:

0x0x00_0354

14 15

R

W

Reset 0 0

13

0

12

0

11 10 9 8

DATA

7 6 5

0 0 0 0 0 0

Figure 25-8. QSPI Data Register (QDR)

0

4

0

3

0

2

0

1

0

0

0

25.3.7

Command RAM Registers (QCR0–QCR15)

The command RAM is accessed using the upper byte of the QDR; the QSPI cannot modify information in command RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip select field enables external peripherals for transfer. The command field provides transfer operations.

NOTE

The command RAM is accessed only using the most significant byte of

QDR and indirect addressing based on QAR[ADDR].

Address: QAR[ADDR] Access: CPU write-only

15 14 13 12

R

W CONT BITSE DT DSCK

Reset — — — —

11

—

10 9

QSPI_CS

— —

8

—

7 6 5 4 3 2 1 0

0 0 0 0 0 0 0 0

— — — — — — — —

Figure 25-9. Command RAM Registers (QCR0–QCR15)

25-8



Preliminary


Table 25-7. QCR0–QCR15 Field Descriptions


15

CONT

14

BITSE

13

DT

Continuous.

0 Chip selects return to inactive level defined by QWR[CSIV] when a single word transfer is complete.

1 Chip selects return to inactive level defined by QWR[CSIV] only after the transfer of the queue entries (max of 16 words).

Note: In order to keep the chip selects asserted for transfers beyond 16 words, the QWR[CSIV] bit must be set to control the level that the chip selects return to after the first transfer.

Bits per transfer enable.

0 Eight bits

1 Number of bits set in QMR[BITS]

Delay after transfer enable.

0 Default reset value.

1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have a latency requirement. The delay between transfers is determined by QDLYR[DTL].

12

DSCK

Chip select to QSPI_CLK delay enable.

0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.

1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.

11–8

QSPI_CS

Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be active at once, and more than one device can be connected to each chip select. Bits 11-8 map directly to the corresponding QSPI_CS n pins. If more than four chip selects are needed, then an external demultiplexor can be used with the QSPI_CS n pins.

Note: Not all chip selects may be available on all device packages. See Chapter 2, “Signal Descriptions,” for details on which chip selects are pinned-out.




Preliminary

25-9


QSPI_CS n

(active-low)

QSPI_CLK

QS1

QS2

QSPI_DOUT

QS3 QS4 QS5

QSPI_DIN

QS1: QSPI_CS to QSPI_CLK

QS2: QSPI_CLK to QSPI_DOUT VALID

QS3: QSPI_CLK to QSPI_DOUT HOLD

QS4: QSPI_DIN to QSPI_CLK SETUP

QS5: QSPI_DIN to QSPI_CLK HOLD

1T1 is defined as the clock period in ns.

Min

1T1

0 ns

10 ns

10 ns

Max

20 ns

Figure 25-10. QSPI Timing

25.4


The QSPI uses a dedicated 80-byte block of static RAM accessible to both the module and CPU to perform queued operations. The RAM is divided into three segments:

• 16 command control bytes (command RAM)

• 32 transmit data bytes (transfer RAM)

• 32 receive data bytes (transfer RAM)

The RAM is organized so that 1 byte of command control data, 1 word of transmit data, and 1 word of receive data comprise 1 of the 16 queue entries (0x0–0xF).

NOTE

Throughout ColdFire documentation, the term ‘word’ is used to designate a

16-bit data unit. The only exceptions to this appear in discussions of serial communication modules such as QSPI that support variable-length data units. To simplify these discussions, the functional unit is referred to as a

‘word’ regardless of length.

25-10



Preliminary


The user initiates QSPI operation by loading a queue of commands in command RAM, writing transmit data into transmit RAM, and then enabling the QSPI data transfer. The QSPI executes the queued commands and sets the completion flag in the QSPI interrupt register (QIR[SPIF]) to signal their completion. As another option, QIR[SPIFE] can be enabled to generate an interrupt.

The QSPI uses four queue pointers. The user can access three of them through fields in QSPI wrap register

(QWR):

• New queue pointer (QWR[NEWQP])—points to the first command in the queue

• Internal queue pointer—points to the command currently being executed

• Completed queue pointer (QWR[CPTQP])—points to the last command executed

• End queue pointer (QWR[ENDQP]) —points to the final command in the queue

The internal pointer is initialized to the same value as QWR[NEWQP]. During normal operation, the following sequence repeats:

1. The command pointed to by the internal pointer is executed.

2. The value in the internal pointer is copied into QWR[CPTQP].

3. The internal pointer is incremented.

Execution continues at the internal pointer address unless the QWR[NEWQP] value is changed. After each command is executed, QWR[ENDQP] and QWR[CPTQP] are compared. When a match occurs,

QIR[SPIF] is set and the QSPI stops unless wraparound mode is enabled. Setting QWR[WREN] enables wraparound mode.

QWR[NEWQP] is cleared at reset. When the QSPI is enabled, execution begins at address 0x0 unless another value has been written into QWR[NEWQP]. QWR[ENDQP] is cleared at reset but is changed to show the last queue entry before the QSPI is enabled. QWR[NEWQP] and QWR[ENDQP] can be written at any time. When the QWR[NEWQP] value changes, the internal pointer value also changes unless a transfer is in progress, in which case the transfer completes normally. Leaving QWR[NEWQP] and

QWR[ENDQP] set to 0x0 causes a single transfer to occur when the QSPI is enabled.

Data is transferred relative to QSPI_CLK, which can be generated in any one of four combinations of phase and polarity using QMR[CPHA,CPOL]. Data is transferred with the most significant bit (msb) first.

The number of bits transferred defaults to 8, but can be set to any value between 8 and 16 by writing a value into the BITSE field of the command RAM (QCR[BITSE]).

25.4.1

QSPI RAM

The QSPI contains an 80-byte block of static RAM that can be accessed by both the user and the QSPI.

This RAM does not appear in the device memory map, because it can only be accessed by the user indirectly through the QSPI address register (QAR) and the QSPI data register (QDR). The RAM is divided into three segments with 16 addresses each:

• Receive data RAM—the initial destination for all incoming data

• Transmit data RAM—a buffer for all out-bound data

• Command RAM—where commands are loaded



Preliminary

25-11


The transmit and command RAM are user write-only. The receive RAM is user read-only. Figure 25-11

shows the RAM configuration. The RAM contents are undefined immediately after a reset.

The command and data RAM in the QSPI is indirectly accessible with QDR and QAR as 48 separate locations that comprise 16 words of transmit data, 16 words of receive data, and 16 bytes of commands.

A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR] and causes the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.

Relative

Address

0x00

0x01

...

0x0F

Register Function

QTR0 Transmit RAM

QTR1

...

QTR15

16 bits wide

0x10

0x11

...

0x1F

QRR0 Receive RAM

QRR1

...

QRR15

16 bits wide

0x20

0x21

...

0x2F

QCR0 Command RAM

QCR1

...

QCR15

8 bits wide

Figure 25-11. QSPI RAM Model

25.4.1.1

Receive RAM

Data received by the QSPI is stored in the receive RAM segment located at 0x10 to 0x1F in the QSPI RAM space. The user reads this segment to retrieve data from the QSPI. Data words with less than 16 bits are stored in the least significant bits of the RAM. Unused bits in a receive queue entry are set to zero upon completion of the individual queue entry.

QWR[CPTQP] shows which queue entries have been executed. The user can query this field to determine which locations in receive RAM contain valid data.

25.4.1.2

Transmit RAM

Data to be transmitted by the QSPI is stored in the transmit RAM segment located at addresses 0x0 to 0xF.

The user normally writes 1 word into this segment for each queue command to be executed. The user cannot read data in the transmit RAM.

25-12



Preliminary


Outbound data must be written to transmit RAM in a right-justified format. The unused bits are ignored.

The QSPI copies the data to its data serializer (shift register) for transmission. The data is transmitted most significant bit first and remains in transmit RAM until overwritten by the user.

25.4.1.3

Command RAM

The CPU writes one byte of control information to this segment for each QSPI command to be executed.

Command RAM, referred to as QCR0–15, is write-only memory from a user’s perspective.

Command RAM consists of 16 bytes, each divided into two fields. The peripheral chip select field controls the QSPI_CS signal levels for the transfer. The command control field provides transfer options.

A maximum of 16 commands can be in the queue. Queue execution proceeds from the address in

QWR[NEWQP] through the address in QWR[ENDQP].

The QSPI executes a queue of commands defined by the control bits in each command RAM entry that sequence the following actions:

• Chip-select pins are activated.

• Data is transmitted from transmit RAM and received into the receive RAM.

• The synchronous transfer clock QSPI_CLK is generated.

Before any data transfers begin, control data must be written to the command RAM, and any out-bound data must be written to transmit RAM. Also, the queue pointers must be initialized to the first and last entries in the command queue.

Data transfer is synchronized with the internally generated QSPI_CLK, whose phase and polarity are controlled by QMR[CPHA] and QMR[CPOL]. These control bits determine which QSPI_CLK edge is used to drive outgoing data and to latch incoming data.

25.4.2

Baud Rate Selection

The maximum QSPI clock frequency is one-fourth the clock frequency of the internal bus clock (f sys

).

Baud rate is selected by writing a value from 2–255 into QMR[BAUD]. The QSPI uses a prescaler to derive the QSPI_CLK rate from the internal bus clock divided by two.

A baud rate value of zero turns off the QSPI_CLK.

The desired QSPI_CLK baud rate is related to the internal bus clock and QMR[BAUD] by the following expression:

QMR[BAUD] = f

----------------------------------------------------------------------------------Eqn. 25-1



Preliminary

25-13


Table 25-8. QSPI_CLK Frequency as Function of Internal Bus Clock and Baud Rate

Internal Bus Clock = 66 MHz

QMR [BAUD]

8

16

2

4

32

255

QSPI_CLK

16.5 MHz

8.25 MHz

4.1 MHz

2.06 MHz

1.0 MHz

12.9 kHz

25.4.3

Transfer Delays

The QSPI supports programmable delays for the QSPI_CS signals before and after a transfer. The time between QSPI_CS assertion and the leading QSPI_CLK edge, and the time between the end of one transfer and the beginning of the next, are both independently programmable.

The chip select to clock delay enable bit in command RAM, QCR[DSCK], enables the programmable delay period from QSPI_CS assertion until the leading edge of QSPI_CLK. QDLYR[QCD] determines the period of delay before the leading edge of QSPI_CLK. The following expression determines the actual delay before the QSPI_CLK leading edge:

QSPI_CS-to-QSPI_CLK delay =

QDLYR[QCD] has a range of 1–127.

f sys

Eqn. 25-2

When QDLYR[QCD] or QCR[DSCK] equals zero, the standard delay of one-half the QSPI_CLK period is used.

The command RAM delay after transmit enable bit, QCR[DT], enables the programmable delay period from the negation of the QSPI_CS signals until the start of the next transfer. The delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. There are two transfer delay options: the user can choose to delay a standard period after serial transfer is complete or can specify a delay period.

Writing a value to QDLYR[DTL] specifies a delay period. QCR[DT] determines whether the standard delay period (DT = 0) or the specified delay period (DT = 1) is used. The following expression is used to calculate the delay when DT = 1:

Delay after transfer =

32 QDLYR[DTL] f sys

(DT = 1) Eqn. 25-3 where QDLYR[DTL] has a range of 1–255. A zero value for DTL causes a delay-after-transfer value of

8192/f sys/

. Standard delay period (DT = 0) is calculated by the following:

Standard delay after transfer = f

17

(DT = 0) sys

Eqn. 25-4

Adequate delay between transfers must be specified for long data streams because the QSPI module requires time to load a transmit RAM entry for transfer. Receiving devices need at least the standard delay

25-14



Preliminary

Queued Serial Peripheral Interface (QSPI) between successive transfers. If the internal bus clock is operating at a slower rate, the delay between transfers must be increased proportionately.

25.4.4

Transfer Length

There are two transfer length options. The user can choose a default value of 8 bits or a programmed value of 8 to 16 bits. The programmed value must be written into QMR[BITS]. The command RAM bits per transfer enable field, QCR[BITSE], determines whether the default value (BITSE = 0) or the BITS[3–0] value (BITSE = 1) is used. QMR[BITS] indicates the required number of bits to be transferred, with the default value of 16 bits.

25.4.5

Data Transfer

The transfer operation is initiated by setting QDLYR[SPE]. Shortly after QDLYR[SPE] is set, the QSPI executes the command at the command RAM address pointed to by QWR[NEWQP]. Data at the pointer address in transmit RAM is loaded into the data serializer and transmitted. Data that is simultaneously received is stored at the pointer address in receive RAM.

When the proper number of bits has been transferred, the QSPI stores the working queue pointer value in

QWR[CPTQP], increments the working queue pointer, and loads the next data for transfer from the transmit RAM. The command pointed to by the incremented working queue pointer is executed next unless a new value has been written to QWR[NEWQP]. If a new queue pointer value is written while a transfer is in progress, the current transfer is completed normally.

When the CONT bit in the command RAM is set, the QSPI_CS signals are asserted between transfers.

When CONT is cleared, QSPI_CS n are negated between transfers. Note, the QSPI_CS signals are not high impedance.

When the QSPI reaches the end of the queue, it asserts the SPIF flag, QIR[SPIF]. If QIR[SPIFE] is set, an interrupt request is generated when QIR[SPIF] is asserted. Then the QSPI clears QDLYR[SPE] and stops, unless wraparound mode is enabled.

Wraparound mode is enabled by setting QWR[WREN]. The queue can wrap to pointer address 0x0, or to the address specified by QWR[NEWQP], depending on the state of QWR[WRTO].

In wraparound mode, the QSPI cycles through the queue continuously, even while requesting interrupt service. QDLYR[SPE] is not cleared when the last command in the queue is executed. New receive data overwrites previously received data in the receive RAM. Each time the end of the queue is reached,

QIR[SPIFE] is set. QIR[SPIF] is not automatically reset. If interrupt driven QSPI service is used, the service routine must clear QIR[SPIF] to abort the current request. Additional interrupt requests during servicing can be prevented by clearing QIR[SPIFE].

There are two recommended methods of exiting wraparound mode: clearing QWR[WREN] or setting

QWR[HALT]. Exiting wraparound mode by clearing QDLYR[SPE] is not recommended because this may abort a serial transfer in progress. The QSPI sets SPIF, clears QDLYR[SPE], and stops the first time it reaches the end of the queue after QWR[WREN] is cleared. After QWR[HALT] is set, the QSPI finishes the current transfer, then stops executing commands. After the QSPI stops, QDLYR[SPE] can be cleared.



Preliminary

25-15


25.5


The following steps are necessary to set up the QSPI 12-bit data transfers and a QSPI_CLK of 4.125 MHz.

The QSPI RAM is set up for a queue of 16 transfers. All four QSPI_CS signals are used in this example.

1. Write the QMR with 0xB308 to set up 12-bit data words with the data shifted on the falling clock edge, and a QSPI_CLK frequency of 4.125 MHz (assuming a 66-MHz internal bus clock).

2. Write QDLYR with the desired delays.

3. Write QIR with 0xD00F to enable write collision, abort bus errors, and clear any interrupts.

4. Write QAR with 0x0020 to select the first command RAM entry.

5. Write QDR with 0x7E00, 0x7E00, 0x7E00, 0x7E00, 0x7D00, 0x7D00, 0x7D00, 0x7D00, 0x7B00,

0x7B00, 0x7B00, 0x7B00, 0x7700, 0x7700, 0x7700, and 0x7700 to set up four transfers for each chip select. The chip selects are active low in this example.

6. Write QAR with 0x0000 to select the first transmit RAM entry.

7. Write QDR with sixteen 12-bit words of data.

8. Write QWR with 0x0F00 to set up a queue beginning at entry 0 and ending at entry 15.

9. Set QDLYR[SPE] to enable the transfers.

10. Wait until the transfers are complete. QIR[SPIF] is set when the transfers are complete.

11. Write QAR with 0x0010 to select the first receive RAM entry.

12. Read QDR to get the received data for each transfer.

13. Repeat steps 5 through 13 to do another transfer.

25-16



Preliminary

Chapter 26

UART Modules

26.1

Introduction

This chapter describes the use of the three universal asynchronous receiver/transmitters (UARTs) and includes programming examples.

NOTE

The designation ‘ n ’ is used throughout this section to refer to registers or signals associated with one of the three identical UART modules: UART0,

UART1, or UART2.

26.1.1

Overview

Each of the three independent UARTs can be clocked by the internal bus clock, eliminating the need for an external UART clock. As

Figure 26-1

shows, each UART module interfaces directly to the CPU and consists of the following:

• Serial communication channel

• Programmable clock generation

• Interrupt control logic and DMA request logic

• Internal channel control logic

UART

Internal Channel

Control Logic

Serial

Communications

Channel

U n CTS

U n RTS

U n RXD

U n TXD

Interrupt Request

(to Interrupt Controller)

Interrupt Control

Logic

Transmit DMA Request

Receive DMA Request

(To DMA Controller)

DMA Request

Logic

Programmable

Clock

Generation

Internal Bus Clock or External clock (DT n IN)

Figure 26-1. UART Block Diagram

NOTE

UART n can be clocked by the DT n IN pin. However, if the timers are used, then input capture mode is not available for that timer.



Preliminary

26-1

UART Modules

The serial communication channel provides a full-duplex asynchronous/synchronous receiver and transmitter deriving an operating frequency from the internal bus clock or an external clock using the timer pin. The transmitter converts parallel data from the CPU to a serial bit stream, inserting appropriate start, stop, and parity bits. It outputs the resulting stream on the transmitter serial data output (U n TXD). See

Section 26.4.2.1, “Transmitter

.”

The receiver converts serial data from the receiver serial data input (U n RXD) to parallel format, checks for a start, stop, and parity bits, or break conditions, and transfers the assembled character onto the bus during read operations. The receiver may be polled, interrupt driven, or use DMA requests for servicing.

See Section 26.4.2.2, “Receiver

.”

NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module” ) prior to configuring the UART module.

26.1.2

Features

The device contains three independent UART modules with the following features:

• Each clocked by an external clock or by the internal bus clock (eliminating a need for an external

UART clock)

• Full-duplex asynchronous/synchronous receiver/transmitter

• Quadruple-buffered receiver

• Double-buffered transmitter

• Independently programmable receiver and transmitter clock sources

• Programmable data format:

— 5–8 data bits plus parity

— Odd, even, no parity, or force parity

— One, one-and-a-half, or two stop bits

• Each serial channel programmable to normal (full-duplex), automatic echo, local loop-back, or remote loop-back mode

• Automatic wake-up mode for multidrop applications

• Four maskable interrupt conditions

• All three UARTs have DMA request capability

• Parity, framing, and overrun error detection

• False-start bit detection

• Line-break detection and generation

• Detection of breaks originating in the middle of a character

• Start/end break interrupt/status

26-2



Preliminary

UART Modules

26.2


Figure 26-1

shows both the external and internal signal groups.

An internal interrupt request signal is provided to notify the interrupt controller of an interrupt condition.

The output is the logical NOR of unmasked UISR n bits. The interrupt level and priority are programmed in the interrupt controller. See Chapter 14, “Interrupt Controller Modules” for more information.

Note that the UARTs can also be configured to automatically transfer data by using the DMA rather than interrupting the core. When there is data in the receiver FIFO or when the transmit holding register is empty, a DMA request can be issued. For more information on generating DMA requests, refer to

Section 26.4.6.1.2, “Setting up the UART to Request DMA Service ,” and

Chapter 16, “Enhanced Direct

Memory Access (eDMA).”

Table 26-1

briefly describes the UART module signals.

NOTE

The terms ‘assertion’ and ‘negation’ are used to avoid confusion between active-low and active-high signals. ‘Asserted’ indicates that a signal is active, independent of the voltage level; ‘negated’ indicates that a signal is inactive.

Table 26-1. UART Module Signals


Transmitter Serial

Data Output

(U n TXD)

Receiver Serial

Data Input

(U n RXD)

Clear-to- Send

(U n CTS)

Request-to-Send

(U n RTS)

U n TXD is held high (mark condition) when the transmitter is disabled, idle, or operating in the local loop-back mode. Data is shifted out on U n TXD on the falling edge of the clock source, with the least significant bit (lsb) sent first.

Data received on U n RXD is sampled on the rising edge of the clock source, with the lsb received first.

This input can generate an interrupt on a change of state.

This output can be programmed to be negated or asserted automatically by either the receiver or the transmitter. When connected to a transmitter’s U n CTS, U n RTS can control serial data flow.

Figure 26-2

shows a signal configuration for a UART/RS-232 interface.

UART RS-232 Transceiver

U n RTS

U n CTS

U n TXD

U n RXD

DI2

DO2

DI1

DO1

Figure 26-2. UART/RS-232 Interface



Preliminary

26-3

UART Modules

26.3


This section contains a detailed description of each register and its specific function. Flowcharts in

Section 26.4.6, “Programming ,” describe basic UART module programming. The operation of the UART

module is controlled by writing control bytes into the appropriate registers.

Table 26-2 is a memory map

for UART module registers.

NOTE

UART registers are accessible only as bytes.

NOTE

Interrupt can mean either an interrupt request asserted to the CPU or a DMA request.

Table 26-2. UART Module Memory Map

ISPBAR

Offset

UART0

UART1

UART2

0x00_0200

0x00_0240

0x00_0280

0x00_0204

0x00_0244

0x00_0284

0x00_0208

0x00_0248

0x00_0288

0x00_020C

0x00_024C

0x00_028C

0x00_0210

0x00_0250

0x00_0290

0x00_0214

0x00_0254

0x00_0294

0x00_0218

0x00_0258

0x00_0298

0x00_021C

0x00_025C

0x00_029C

Register

UART Mode Registers

1

(UMR1 n ), (UMR2 n )

UART Status Register (USR n ) 8

UART Clock Select Register

1

(UCSR n ) 8

UART Command Registers (UCR n )

UART Receive Buffers (URB n )

UART Transmit Buffers (UTB n )

UART Input Port Change Register (UIPCR n )

UART Auxiliary Control Register (UACR n )

UART Interrupt Status Register (UISR n )

UART Interrupt Mask Register (UIMR n )

UART Baud Rate Generator Register (UBG1 n )

UART Baud Rate Generator Register (UBG2 n )

Width

(bit)

8

8

8

8

8

8

8

8

8

8


R/W

R

W

W

R

W

R

W

R

W

W

W

2

2

0x00

0x00

0x00

0x00

0xFF

0x00

See Section

0x00

0x00

0x00

0x00

0x00

26.3.1/26-5

26.3.2/26-6

26.3.3/26-8

26.3.4/26-9

26.3.5/26-10

26.3.6/26-12

26.3.7/26-13

26.3.8/26-13

26.3.9/26-14

26.3.10/26-14

26.3.11/26-16

26.3.11/26-16

26-4



Preliminary

UART Modules

Table 26-2. UART Module Memory Map (continued)

ISPBAR

Offset

Register

Width

(bit)


UART0

UART1

UART2

0x00_0234

0x00_0274

0x00_02B4

UART Input Port Register (UIP n ) 8 R 0xFF

26.3.12/26-16

0x00_0238

0x00_0278

0x00_02B8

UART Output Port Bit Set Command Register (UOP1 n ) 8 W

2

0x00

26.3.13/26-17

0x00_023C

0x00_027C

0x00_02BC

UART Output Port Bit Reset Command Register (UOP0 n ) 8 W

2

0x00

26.3.13/26-17

1

2

UMR1 n , UMR2 n , and UCSR n should be changed only after the receiver/transmitter is issued a software reset command. That is, if operation is not disabled, undesirable results may occur.

Reading this register results in undesired effects and possible incorrect transmission or reception of characters. Register contents may also be changed.

26.3.1

UART Mode Registers 1 (UMR1

n

)

The UMR1 n registers control configuration. UMR1 n can be read or written when the mode register pointer points to it, at RESET or after a RESET MODE REGISTER POINTER command using UCR n [MISC]. After

UMR1 n is read or written, the pointer points to UMR2 n .


1

Address: 0x00_0200 (UMR10)

0x00_0240 (UMR11)

0x00_0280 (UMR12)

7 6 5 4 3

R

W

RXRTS

RXIRQ/

FFULL

ERR PM

Reset: 0 0 0 0 0

1

After UMR1 n is read or written, the pointer points to UMR2 n

Figure 26-3. UART Mode Registers 1 (UMR1 n )

2

PT

0

1

0

B/C

0

0



Preliminary

26-5

UART Modules

Table 26-3. UMR1 n Field Descriptions


7

RXRTS

Receiver request-to-send. Allows the U n RTS output to control the U n CTS input of the transmitting device to prevent receiver overrun. If both the receiver and transmitter are incorrectly programmed for U n RTS control, U n RTS control is disabled for both. Transmitter RTS control is configured in UMR2 n [TXRTS].

0 The receiver has no effect on U n RTS.

1 When a valid start bit is received, U n RTS is negated if the UART's FIFO is full. U n RTS is reasserted when the

FIFO has an empty position available.

6

RXIRQ/

FFULL

Receiver interrupt select.

0 RXRDY is the source that generates interrupt or DMA requests.

1 FFULL is the source that generates interrupt or DMA requests.

5

ERR

Error mode. Configures the FIFO status bits, USR n [RB,FE,PE].

0 Character mode. The USR n values reflect the status of the character at the top of the FIFO. ERR must be 0 for correct A/D flag information when in multidrop mode.

1 Block mode. The USR n values are the logical OR of the status for all characters reaching the top of the FIFO since the last RESET ERROR STATUS

command for the UART was issued. See Section 26.3.5, “UART Command

Registers (UCRn) .”

4–3

PM

2

PT

Parity mode. Selects the parity or multidrop mode for the UART. The parity bit is added to the transmitted character, and the receiver performs a parity check on incoming data. The value of PM affects PT, as shown below.

Parity type. PM and PT together select parity type (PM = 0x) or determine whether a data or address character is transmitted (PM = 11).

PM

00

01

10

11

Parity Mode

With parity

Force parity

No parity

Multidrop mode

Parity Type (PT= 0) Parity Type (PT= 1)

Even parity

Low parity

Odd parity

High parity

N/A

Data character Address character

1–0

B/C

Bits per character. Selects the number of data bits per character to be sent. The values shown do not include start, parity, or stop bits.

00 5 bits

01 6 bits

10 7 bits

11 8 bits

26.3.2

UART Mode Register 2 (UMR2

n

)

The UMR2 n registers control UART module configuration. UMR2 n can be read or written when the mode register pointer points to it, which occurs after any access to UMR1 n . UMR2 n accesses do not update the pointer.

26-6



Preliminary

UART Modules

Address: 0x00_0200 (UMR20)

0x00_0240 (UMR21)

0x00_0280 (UMR22)

7 6 5 4 3

R

W

CM TXRTS TXCTS

Reset: 0 0 0 0 0

1

After UMR1 n is read or written, the pointer points to UMR2 n

Figure 26-5. UART Mode Register 2 (UMR2 n )

2

0

SB


1

1

0

0

0

Table 26-4. UMR2 n Field Descriptions


7–6

CM

Channel mode. Selects a channel mode. Section 26.4.3, “Looping Modes ,” describes individual modes.

00 Normal

01 Automatic echo

10 Local loop-back

11 Remote loop-back

5

TXRTS

Transmitter ready-to-send. Controls negation of U n RTS to automatically terminate a message transmission.

Attempting to program a receiver and transmitter in the same UART for U n RTS control is not permitted and disables

U n RTS control for both.

0 The transmitter has no effect on U n RTS.

1 In applications where the transmitter is disabled after transmission completes, setting this bit automatically clears

UOP[RTS] one bit time after any characters in the transmitter shift and holding registers are completely sent, including the programmed number of stop bits.



Preliminary

26-7

UART Modules

Table 26-4. UMR2 n Field Descriptions (continued)


4

TXCTS

Transmitter clear-to-send. If both TXCTS and TXRTS are set, TXCTS controls the operation of the transmitter.

0 U n CTS has no effect on the transmitter.

1 Enables clear-to-send operation. The transmitter checks the state of U n CTS each time it is ready to send a character. If U n CTS is asserted, the character is sent; if it is deasserted, the signal U n TXD remains in the high state and transmission is delayed until U n CTS is asserted. Changes in U n CTS as a character is being sent do not affect its transmission.

3–0

SB

Stop-bit length control. Selects the length of the stop bit appended to the transmitted character. Stop-bit lengths of

9/16 to 2 bits are programmable for 6–8 bit characters. Lengths of 1-1/16 to 2 bits are programmable for 5-bit characters. In all cases, the receiver checks only for a high condition at the center of the first stop-bit position, that is, one bit time after the last data bit or after the parity bit, if parity is enabled. If an external 1x clock is used for the transmitter, clearing bit 3 selects one stop bit and setting bit 3 selects two stop bits for transmission.

SB

0000

0001

0010

0011

0100

0101

0110

0111

5 Bits 6–8 Bits

1.063

1.125

1.188

1.250

1.313

1.375

1.438

1.500

0.563

0.625

0.688

0.750

0.813

0.875

0.938

1.000

SB

1000

1001

1010

1011

1100

1101

1110

1111

5–8 Bits

1.563

1.625

1.688

1.750

1.813

1.875

1.938

2.000

26.3.3

UART Status Registers (USR

n

)

The USR n registers, shown in

Figure 26-6

, show the status of the transmitter, the receiver, and the FIFO.

Access: User read-only Address: 0x00_0204 (UCSR0)

0x00_0244 (UCSR1)

0x00_0284 (UCSR2)

7

RB R

W

Reset: 0

6

FE

5

PE

4

OE

3

TXEMP

2

TXRDY

0 0 0 0

Figure 26-6. UART Status Register (USR n )

0

1

FFULL

0

0

RXRDY

0

26-8



Preliminary

UART Modules

Table 26-5. USR n Field Descriptions


7

RB

6

FE

5

PE

4

OE

Received break. The received break circuit detects breaks that originate in the middle of a received character.

However, a break in the middle of a character must persist until the end of the next detected character time.

0 No break was received.

1 An all-zero character of the programmed length was received without a stop bit. Only a single FIFO position is occupied when a break is received. Further entries to the FIFO are inhibited until U n RXD returns to the high state for at least one-half bit time, which is equal to two successive edges of the UART clock. RB is valid only when

RXRDY = 1.

Framing error.

0 No framing error occurred.

1 No stop bit was detected when the corresponding data character in the FIFO was received. The stop-bit check occurs in the middle of the first stop-bit position. FE is valid only when RXRDY = 1.

Parity error. Valid only if RXRDY = 1.

0 No parity error occurred.

1 If UMR1 n [PM] = 0 x (with parity or force parity), the corresponding character in the FIFO was received with incorrect parity. If UMR1 n [PM] = 11 (multidrop), PE stores the received address or data (A/D) bit. PE is valid only when RXRDY = 1.

Overrun error. Indicates whether an overrun occurs.

0 No overrun occurred.

1 One or more characters in the received data stream have been lost. OE is set upon receipt of a new character when the FIFO is full and a character is already in the shift register waiting for an empty FIFO position. When this occurs, the character in the receiver shift register and its break detect, framing error status, and parity error, if any, are lost. OE is cleared by the RESET ERROR STATUS command in UCR n .

3

TEMP

2

TXRDY

1

FFULL

Transmitter empty.

0 The transmit buffer is not empty. Either a character is being shifted out, or the transmitter is disabled. The transmitter is enabled/disabled by programming UCR n [TC].

1 The transmitter has underrun (both the transmitter holding register and transmitter shift registers are empty). This bit is set after transmission of the last stop bit of a character if there are no characters in the transmitter holding register awaiting transmission.

Transmitter ready.

0 The CPU loaded the transmitter holding register or the transmitter is disabled.

1 The transmitter holding register is empty and ready for a character. TXRDY is set when a character is sent to the transmitter shift register or when the transmitter is first enabled. If the transmitter is disabled, characters loaded into the transmitter holding register are not sent.

FIFO full.

0 The FIFO is not full but may hold up to two unread characters.

1 A character was received and the receiver FIFO is now full. Any characters received when the FIFO is full are lost.

0

RXRDY

Receiver ready.

0 The CPU has read the receive buffer and no characters remain in the FIFO after this read.

1 One or more characters were received and are waiting in the receive buffer FIFO.

26.3.4

UART Clock Select Registers (UCSR

n

)

The UCSRs select an external clock on the DTIN input (divided by 1 or 16) or a prescaled internal bus clock as the clocking source for the transmitter and receiver. See

Section 26.4.1, “Transmitter/Receiver

Clock Source

.” The transmitter and receiver can use different clock sources. To use the internal bus clock for both, set UCSR n to 0xDD.



Preliminary

26-9

UART Modules

Field

7–4

RCS

Address: 0x00_0204 (UCSR0)

0x00_0244 (UCSR1)

0x00_0284 (UCSR2)

7 6

R

W

Reset: 0

RCS

5 4 3 2

0 0 0 0 0

Figure 26-7. UART Clock Select Register (UCSR n )

TCS

Access: User write-only

1

0

0

0

3–0

TCS

Table 26-6. UCSR n Field Descriptions

Description

Receiver clock select. Selects the clock source for the receiver.

1101 Prescaled internal bus clock (f sys/2

)

1110 DTIN divided by 16

1111 DTIN

Transmitter clock select. Selects the clock source for the transmitter.

1101 Prescaled internal bus clock (f sys/2

)

1110 DTIN divided by 16

1111 DTIN

26.3.5

UART Command Registers (UCR

n

)

The UCRs, shown in Figure 26-8 , supply commands to the UART. Only multiple commands that do not

conflict can be specified in a single write to a UCR n . For example,

RESET TRANSMITTER

and

ENABLE

TRANSMITTER

cannot be specified in one command.

Access: User write-only Address: 0x00_0208 (UCR0)

0x00_0248 (UCR1)

0x00_0288 (UCR2)

7 6

R

W

Reset:

0

0

5 4 3 2

0

MISC

0 0 0

TC

Figure 26-8. UART Command Register (UCR n )

0

1

0

RC

0

0

26-10



Preliminary

UART Modules

Table 26-7

describes UCR n

fields and commands. Examples in Section 26.4.2, “Transmitter and Receiver

Operating Modes

,” show how these commands are used.

Table 26-7. UCR n Field Descriptions

Field

7

6–4

MISC


MISC Field (this field selects a single command)

Description

Command Description

000 NO COMMAND —

001 RESET MODE

REGISTER POINTER

Causes the mode register pointer to point to UMR1 n .

010

011

111

RESET

RESET

TRANSMITTER

STOP

RECEIVER

BREAK

Immediately disables the receiver, clears USR n [FFULL,RXRDY], and reinitializes the receiver FIFO pointer. No other registers are altered. Because it places the receiver in a known state, use this command instead of RECEIVER DISABLE when reconfiguring the receiver.

Immediately disables the transmitter and clears USR n [TXEMP,TXRDY]. No other registers are altered. Because it places the transmitter in a known state, use this command instead of TRANSMITTER DISABLE when reconfiguring the transmitter.

Clears USR n [RB,FE,PE,OE]. Also used in block mode to clear all error bits after a data block is received.

100 RESET ERROR

STATUS

101 RESET BREAK –

CHANGE INTERRUPT

Clears the delta break bit, UISR n [DB].

110 START BREAK Forces U n TXD low. If the transmitter is empty, the break may be delayed up to one bit time. If the transmitter is active, the break starts when character transmission completes. The break is delayed until any character in the transmitter shift register is sent. Any character in the transmitter holding register is sent after the break. The transmitter must be enabled for the command to be accepted. This command ignores the state of U n CTS.

Causes U n TXD to go high (mark) within two bit times. Any characters in the transmit buffer are sent.



Preliminary

26-11

UART Modules

Table 26-7. UCR n Field Descriptions (continued)

Field

3–2

TC

TC Field (This field selects a single command)

Description


00 NO ACTION TAKEN Causes the transmitter to stay in its current mode: if the transmitter is enabled, it remains enabled; if the transmitter is disabled, it remains disabled.

01 TRANSMITTER

ENABLE

Enables operation of the UART’s transmitter. USR n [TXEMP,TXRDY] are set. If the transmitter is already enabled, this command has no effect.

10 TRANSMITTER

DISABLE

11 —

Terminates transmitter operation and clears USR transmitter becomes inactive. If the transmitter is already disabled, the command has no effect.

Reserved, do not use.

n [TXEMP,TXRDY]. If a character is being sent when the transmitter is disabled, transmission completes before the

1–0

RC

RC (This field selects a single command)


00 NO ACTION TAKEN Causes the receiver to stay in its current mode. If the receiver is enabled, it remains enabled; if disabled, it remains disabled.

01 RECEIVER ENABLE If the UART module is not in multidrop mode (UMR1 n [PM]

≠

11), RECEIVER ENABLE enables the UART's receiver and forces it into search-for-start-bit state. If the receiver is already enabled, this command has no effect.

10 RECEIVER DISABLE Disables the receiver immediately. Any character being received is lost. The command does not affect receiver status bits or other control registers. If the

UART module is programmed for local loop-back or multidrop mode, the receiver operates even though this command is selected. If the receiver is already disabled, the command has no effect.

11 — Reserved, do not use.

26.3.6

UART Receive Buffers (URB

n

)

The receive buffers (shown in Figure 26-9

) contain one serial shift register and three receiver holding registers, which act as a FIFO. U n RXD is connected to the serial shift register. The CPU reads from the top of the FIFO while the receiver shifts and updates from the bottom when the shift register is full (see

Figure 26-20

). RB contains the character in the receiver.

26-12



Preliminary

UART Modules

Address: 0x00_020C (URB0)

0x00_024C (URB1)

0x00_028C (URB2)

7 6

R

W

Reset: 1

5 4

RB

3 2

1 1 1 1

Figure 26-9. UART Receive Buffer (URB n )

1


1

1

0

1

26.3.7

UART Transmit Buffers (UTB

n

)

The transmit buffers consist of the transmitter holding register and the transmitter shift register. The holding register accepts characters from the bus master if UART’s USR n [TXRDY] is set. A write to the transmit buffer clears USR n [TXRDY], inhibiting any more characters until the shift register can accept more data. When the shift register is empty, it checks if the holding register has a valid character to be sent

(TXRDY = 0). If there is a valid character, the shift register loads it and sets USR n [TXRDY] again. Writes to the transmit buffer when the UART’s TXRDY = 0 and the transmitter is disabled have no effect on the transmit buffer.

Figure 26-10

shows UTB n . TB contains the character in the transmit buffer.

Access: User write-only Address: 0x00_020C (UTB0)

0x00_024C (UTB1)

0x00_028C (UTB2)

7 6

R

W

Reset: 0

5 4 3 2

TB

0 0 0 0

Figure 26-10. UART Transmit Buffer (UTB n )

0

1

0

0

0

26.3.8

UART Input Port Change Registers (UIPCR

n

)

The UIPCRs, shown in Figure 26-11

, hold the current state and the change-of-state for U n CTS.

Address: 0x00_0210 (UIPCR0)

0x00_0250 (UIPCR1)

0x00_0290 (UIPCR2)

7

0 R

W

Reset: 0

6

0

5

0

4

COS

3

1

2

1

0 0 0 1 1

Figure 26-11. UART Input Port Change Register (UIPCR n )


1

1

1

0

CTS

U n CTS



Preliminary

26-13

UART Modules

Table 26-8. UIPCR n Field Descriptions

Field

7–5

4

COS

3–1

0

CTS

Description

Reserved

Change of state (high-to-low or low-to-high transition).

0 No change-of-state since the CPU last read UIPCR n . Reading UIPCR n clears UISR n [COS].

1 A change-of-state longer than 25–50

µ s occurred on the U n CTS input. UACR n can be programmed to generate an interrupt to the CPU when a change of state is detected.

Reserved

Current state of clear-to-send. Starting two serial clock periods after reset, CTS reflects the state of U n CTS. If

U n CTS is detected asserted at that time, COS is set, which initiates an interrupt if UACR n [IEC] is enabled.

0 The current state of the U n CTS input is asserted.

1 The current state of the U n CTS input is deasserted.

26.3.9

UART Auxiliary Control Register (UACR

n

)

The UACRs, shown in Figure 26-9 , control the input enable.

Address: 0x00_0210 (UACR0)

0x00_0250 (UACR1)

0x00_0290 (UACR2)

7 6

R

W

Reset:

0

0

0

0

5

0

0

4

0

0

3

0

0

2

0

0

Figure 26-12. UART Auxiliary Control Register (UACR n )


1

0

0

0

IEC

0

Field

7–1

0

IEC

Table 26-9. UACR n Field Descriptions

Description


Input enable control.

0 Setting the corresponding UIPCR n bit has no effect on UISR n [COS].

1 UISR n [COS] is set and an interrupt is generated when the UIPCR n [COS] is set by an external transition on the

U n CTS input (if UIMR n [COS] = 1).

26.3.10 UART Interrupt Status/Mask Registers (UISR

n

/UIMR

n

)

The UISRs, shown in Figure 26-13 , provide status for all potential interrupt sources. UISR

n contents are masked by UIMR n . If corresponding UISR n and UIMR n bits are set, the internal interrupt output is asserted. If a UIMR n bit is cleared, the state of the corresponding UISR n bit has no effect on the output.

The UISR n and UIMR n registers share the same space in memory. Reading this register provides the user with interrupt status, while writing controls the mask bits.

26-14



Preliminary

UART Modules

NOTE

True status is provided in the UISR n regardless of UIMR n settings. UISR n is cleared when the UART module is reset.

Address: 0x00_0214 (UISR0)

0x00_0254 (UISR1)

0x00_0294 (UISR2)

R

(UISR n )

W

(UIMR n )

Reset:


7

COS

COS

6

0

0

5

0

0

4

0

0

3

0

0

2

DB

DB

1

FFULL/

RXRDY

FFULL/

RXRDY

0 0 0 0 0 0 0

Figure 26-13. UART Interrupt Status/Mask Registers (UISR n /UIMR n )

0

TXRDY

TXRDY

0

Table 26-10. UISR n /UIMR n Field Descriptions


7

COS

Change-of-state.

0 UIPCR n [COS] is not selected.

1 Change-of-state occurred on U n CTS and was programmed in UACR n [IEC] to cause an interrupt.


6–3

2

DB

Delta break.

0 No new break-change condition to report.

Section 26.3.5, “UART Command Registers (UCRn) ,” describes the

RESET BREAK CHANGE INTERRUPT command.

1 The receiver detected the beginning or end of a received break.

1

FFULL/

RXRDY

Status of FIFO or receiver, depending on UMR1[FFULL/RXRDY] bit. Duplicate of USR n [FIFO] & USR n [RXRDY]

UMR1 n [FFULL/RXRDY]

UIMR n

[FFULL/RXRDY]

UISR n

[FFULL/RXRDY]

0 (RXRDY) 1 (FIFO)

0

1

0

1

0

0

1

1

Receiver not ready

Receiver not ready

Receiver is ready,

Do not interrupt

Receiver is ready, interrupt

FIFO not full

FIFO not full

FIFO is full,

Do not interrupt

FIFO is full, interrupt

0

TXRDY

Transmitter ready. This bit is the duplication of USR n [TXRDY].

0 The transmitter holding register was loaded by the CPU or the transmitter is disabled. Characters loaded into the transmitter holding register when TXRDY = 0 are not sent.

1 The transmitter holding register is empty and ready to be loaded with a character.



Preliminary

26-15

UART Modules

26.3.11 UART Baud Rate Generator Registers (UBG1

n

/UBG2

n

)

The UBG1 n registers hold the MSB, and the UBG2 n registers hold the LSB of the preload value. UBG1 n and UBG2 n concatenate to provide a divider to the internal bus clock for transmitter/receiver operation,

as described in Section 26.4.1.2.1, “Internal Bus Clock Baud Rates .”

Address: 0x00_0218 (UBG10)

0x00_0258 (UBG11)

0x00_0298 (UBG12)

7 6

R

W

Reset: 0 0

5

0

4 3

Divider MSB

0 0

2

0

Figure 26-14. UART Baud Rate Generator Register (UBG1 n )


1

0

0

0

Address: 0x00_021C (UBG20)

0x00_025C (UBG21)

0x00_029C (UBG22)

7 6

R

W

Reset:

5 4 3 2


1

0 0 0 0

Divider LSB

0 0 0

Figure 26-15. UART Baud Rate Generator Register (UBG2 n )

NOTE

The minimum value that can be loaded on the concatenation of UBG1 n with

UBG2 n is 0x0002. The UBG2 n reset value of 0x00 is invalid and must be written to before the UART transmitter or receiver are enabled. Both

UBG1 n and UBG2 n are write-only and cannot be read by the CPU.

0

0

26.3.12 UART Input Port Register (UIP

n

)

The UIP n registers, shown in

Figure 26-17

, show the current state of the U n CTS input.

26-16



Preliminary

UART Modules

Field

7–1

0

CTS

Address: 0x00_0234 (UIP0)

0x00_0274 (UIP1)

0x00_02B4 (UIP2)

7

1 R

W

Reset: 1

6

1

5

1

4

1

3

1

1 1 1 1

Figure 26-17. UART Input Port Register (UIP n )

1

2

1


1

1

1

0

CTS

1

Table 26-12. UIP n Field Descriptions

Description

Reserved

Current state of clear-to-send. The U n CTS value is latched and reflects the state of the input pin when UIP n is read.

Note: This bit has the same function and value as UIPCR n [RTS].

0 The current state of the U n CTS input is logic 0.

1 The current state of the U n CTS input is logic 1.

26.3.13 UART Output Port Command Registers (UOP1

n

/UOP0

n

)

The U n RTS output can be asserted by writing a 1 to UOP1 n [RTS] and negated by writing a 1 to

UOP0 n

[RTS]. See Figure 26-18 .

Address: 0x00_0238 (UOP10)

0x00_023C (UOP00)

0x00_0278 (UOP11)

0x00_027C (UOP01)

0x00_02B8 (UOP12)

0x00_02BC (UOP02)

7 6

R

W

Reset:

0

0

0

0

5

0

0

4

0

0

3

0

0

2

0

0


1

0

0

Figure 26-18. UART Output Port Command Registers (UOP1 n /UOP0 n )

0

RTS

0

Table 26-13. UOP1 n /UOP0 n Field Descriptions

Field

7–1

0

RTS

Description


Output port output. Controls assertion (UOP1)/negation (UOP0) of U n RTS output.

0 Not affected.

1 Asserts U n RTS in UOP1. Negates U n RTS in UOP0.



Preliminary

26-17

UART Modules

26.4


This section describes operation of the clock source generator, transmitter, and receiver.

26.4.1

Transmitter/Receiver Clock Source

The internal bus clock serves as the basic timing reference for the clock source generator logic, which consists of a clock generator and a programmable 16-bit divider dedicated to each UART. The clock generator might not produce standard baud rates if the internal bus clock is used, so the user must enable the 16-bit divider.

26.4.1.1

Programmable Divider

As Figure 26-19 shows, the UART

n transmitter and receiver can use the following clock sources:

• An external clock signal on the DT n IN pin.

When not divided, DT

n

IN provides a synchronous clock; when divided by 16, it is asynchronous.

• The internal bus clock supplies an asynchronous clock source that is divided by 32 and then divided by the 16-bit value programmed in UBG1 n and UBG2 n

. See Section 26.3.11, “UART Baud Rate

Generator Registers (UBG1n/UBG2n) .”

The choice of DTIN or internal bus clock is programmed in the UCSR.

DT n OUT

DT n IN

On-Chip

Timer Module

U n TXD

Tx Buffer

UART

Clocking sources programmed in UCSR

÷

1

TIN

Tx

÷

16

TIN

Rx

Clock

Generator

16-Bit

Divider

÷

32

U n RXD Rx Buffer

Figure 26-19. Clocking Source Diagram

NOTE

If DT n IN is a clocking source for either the timer or UART, that timer module cannot use DT n IN for timer input capture.

Internal

Bus Clock f sys

26-18



Preliminary

UART Modules

26.4.1.2

Calculating Baud Rates

The following sections describe how to calculate baud rates.

26.4.1.2.1

Internal Bus Clock Baud Rates

When the internal bus clock is the UART clocking source, it goes through a divide-by-32 prescaler and then passes through the 16-bit divider of the concatenated UBG1 n and UBG2 n registers. The baud-rate calculation is as follows:

Baudrate

=

[ f

-----------------------------------

32 x divider

]

Using a 66 MHz internal bus clock and letting baud rate = 9600, then

Eqn. 26-1

Divider =

[

66

MHz

32 x 9600

]

=

215 ( decimal

)

=

0x00D6 ( hexadecimal

)

Therefore, UBG1 n = 0x00 and UBG2 n = 0xD6.

Eqn. 26-2

26.4.1.2.2

External Clock

An external source clock (DT n IN) passes through a divide-by-1 or 16 prescaler. If f extc frequency, then the baud rate can be described with this equation:

is the external clock

Baudrate = f

(16 or 1)

Eqn. 26-3

26.4.2

Transmitter and Receiver Operating Modes

Figure 26-20

is a functional block diagram of the transmitter and receiver showing the command and operating registers, which are described generally in the following sections. For detailed descriptions, refer

to Section 26.3, “Memory Map/Register Definition

.”



Preliminary

26-19

UART Modules

UART n

UART Command Register (UCR n ) W

UART Mode Register 1 (UMR1 n )

UART Mode Register 2 (UMR2 n )

R/W

R/W

UART Status Register (USR n )

R

UART

Transmit Buffer

(UTB n )

(2 Registers)

Transmitter Holding Register

Transmitter Shift Register

W

UART Receive

Buffer (URB n )

(4 Registers)

Receiver Holding Register 1



Receiver Shift Register

R

FIFO

Figure 26-20. Transmitter and Receiver Functional Diagram

U n TXD

External

Interface

U n RXD

26.4.2.1

Transmitter

The transmitter is enabled through the UART command register (UCR n ). When it is ready to accept a character, the UART sets USR n [TXRDY]. The transmitter converts parallel data from the CPU to a serial bit stream on U n TXD. It automatically sends a start bit followed by the programmed number of data bits, an optional parity bit, and the programmed number of stop bits. The lsb is sent first. Data is shifted from the transmitter output on the falling edge of the clock source.

After the stop bits are sent, if no new character is in the transmitter holding register, the U n TXD output remains high (mark condition) and the transmitter empty bit (USR n [TXEMP]) is set. Transmission resumes and TXEMP is cleared when the CPU loads a new character into the UART transmit buffer

(UTB n ). If the transmitter receives a disable command, it continues until any character in the transmitter shift register is completely sent.

If the transmitter is reset through a software command, operation stops immediately (see

Section 26.3.5,

“UART Command Registers (UCRn)

”). The transmitter is reenabled through the UCR n to resume operation after a disable or software reset.

If the clear-to-send operation is enabled, U n CTS must be asserted for the character to be transmitted. If

U n CTS is negated in the middle of a transmission, the character in the shift register is sent and U n TXD remains in mark state until U n CTS is reasserted. If the transmitter is forced to send a continuous low condition by issuing a SEND BREAK command, the transmitter ignores the state of U n CTS.

26-20



Preliminary

UART Modules

If the transmitter is programmed to automatically negate U n RTS when a message transmission completes,

U n RTS must be asserted manually before a message is sent. In applications in which the transmitter is disabled after transmission is complete and U n RTS is appropriately programmed, U n RTS is negated one bit time after the character in the shift register is completely transmitted. The transmitter must be manually reenabled by reasserting U n RTS before the next message is to be sent.

Figure 26-21

shows the functional timing information for the transmitter.

C1 in transmission

U n TXD C1

1

C2 C3 Break C4 C6

Transmitter

Enabled

USR n [TXRDY] internal module select

U n CTS

3

W

2

C1

1

W

C2

W W

C3 Start break

W W W

C4 Stop break

C5 not transmitted

W

C6

U n RTS

4 Manually asserted by BIT SET command

1

C n = transmit characters

2

W = write

3

UMR2 n [TXCTS] = 1

4

UMR2 n [TXRTS] = 1

Figure 26-21. Transmitter Timing Diagram

Manually asserted

26.4.2.2

Receiver

The receiver is enabled through its UCR n

, as described in Section 26.3.5, “UART Command Registers

(UCRn) .”

When the receiver detects a high-to-low (mark-to-space) transition of the start bit on U n RXD, the state of

U n RXD is sampled eight times on the edge of the bit time clock starting one-half clock after the transition

(asynchronous operation) or at the next rising edge of the bit time clock (synchronous operation). If

U n RXD is sampled high, the start bit is invalid and the search for the valid start bit begins again.

If U n RXD is still low, a valid start bit is assumed and the receiver continues sampling the input at one-bit time intervals, at the theoretical center of the bit, until the proper number of data bits and parity, if any, is assembled and one stop bit is detected. Data on the U n RXD input is sampled on the rising edge of the



Preliminary

26-21

UART Modules programmed clock source. The lsb is received first. The data is then transferred to a receiver holding register and USR n [RXRDY] is set. If the character is less than 8 bits, the most significant unused bits in the receiver holding register are cleared.

After the stop bit is detected, the receiver immediately looks for the next start bit. However, if a non-zero character is received without a stop bit (framing error) and U n RXD remains low for one-half of the bit period after the stop bit is sampled, the receiver operates as if a new start bit were detected. Parity error, framing error, overrun error, and received break conditions set the respective PE, FE, OE, and RB error and break flags in the USR n at the received character boundary. They are valid only if USR n [RXRDY] is set.

If a break condition is detected (U n RXD is low for the entire character including the stop bit), a character of all zeros is loaded into the receiver holding register and USR n [RB,RXRDY] are set. U n RXD must return to a high condition for at least one-half bit time before a search for the next start bit begins.

The receiver detects the beginning of a break in the middle of a character if the break persists through the next character time. If the break begins in the middle of a character, the receiver places the damaged character in the Rx FIFO and sets the corresponding USR n error bits and USR n [RXRDY]. Then, if the break lasts until the next character time, the receiver places an all-zero character into the Rx FIFO and sets

USR n [RB,RXRDY].

Figure 26-22

shows receiver functional timing.

U n TXD C1 C2 C3 C4 C5 C6 C7 C8

C6, C7, and C8 will be lost

Receiver

Enabled

USR n [RXRDY]

USR n [FFULL] internal module select Status

Data

(C1)

Overrun

USR n [OE]

U n RTS

1

Manually asserted first time, automatically negated if overrun occurs

UOP0[RTS] = 1

1

UMR2 n [TXRTS] = 1

C5 will be lost

Figure 26-22. Receiver Timing

Status

Data

(C2)

Status

Data

Status

Data

(C3) (C4)

Reset by command

Automatically asserted when ready to receive

26-22



Preliminary

UART Modules

26.4.2.3

FIFO

The FIFO is used in the UART’s receive buffer logic. The FIFO consists of three receiver holding registers.

The receive buffer consists of the FIFO and a receiver shift register connected to the U n RXD (see

Figure 26-20

). Data is assembled in the receiver shift register and loaded into the top empty receiver holding register position of the FIFO. Thus, data flowing from the receiver to the CPU is quadruple-buffered.

In addition to the data byte, three status bits—parity error (PE), framing error (FE), and received break

(RB)—are appended to each data character in the FIFO; overrun error (OE) is not appended. By programming the ERR bit in the UART’s mode register (UMR1 n ), status is provided in character or block modes.

USR n [RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the

FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. Either the

RXRDY or FFULL bit can be selected to cause an interrupt and either TXRDY or RXRDY can be used to generate a DMA request.

The two error modes are selected by UMR1 n [ERR]:

• In character mode (UMR1 n [ERR] = 0, status is given in the USR n for the character at the top of the FIFO.

• In block mode, the USR n shows a logical OR of all characters reaching the top of the FIFO since the last RESET ERROR STATUS command. Status is updated as characters reach the top of the FIFO.

Block mode offers a data-reception speed advantage where the software overhead of error-checking each character cannot be tolerated. However, errors are not detected until the check is performed at the end of an entire message—the faulting character is not identified.

In either mode, reading the USR n does not affect the FIFO. The FIFO is popped only when the receive buffer is read. The USR n should be read before reading the receive buffer. If all three receiver holding registers are full, a new character is held in the receiver shift register until space is available. However, if a second new character is received, the contents of the character in the receiver shift register is lost, the

FIFOs are unaffected, and USR n [OE] is set when the receiver detects the start bit of the new overrunning character.

To support flow control, the receiver can be programmed to automatically negate and assert U n RTS, in which case the receiver automatically negates U n RTS when a valid start bit is detected and the FIFO is full. The receiver asserts U n RTS when a FIFO position becomes available; therefore, overrun errors can be prevented by connecting U n RTS to the U n CTS input of the transmitting device.

NOTE

The receiver can still read characters in the FIFO if the receiver is disabled.

If the receiver is reset, the FIFO, U n RTS control, all receiver status bits, and interrupts, and DMA requests are reset. No more characters are received until the receiver is reenabled.



Preliminary

26-23

UART Modules

26.4.3

Looping Modes

The UART can be configured to operate in various looping modes, as shown in Figure 26-22 . These modes

are useful for local and remote system diagnostic functions. The modes are described in the following

paragraphs and in Section 26.3, “Memory Map/Register Definition

.”

The UART’s transmitter and receiver should be disabled when switching between modes. The selected mode is activated immediately upon mode selection, regardless of whether a character is being received or transmitted.

26.4.3.1

Automatic Echo Mode

In automatic echo mode, shown in

Figure 26-23

, the UART automatically resends received data bit by bit.

The local CPU-to-receiver communication continues normally, but the CPU-to-transmitter link is disabled. In this mode, received data is clocked on the receiver clock and re-sent on U n TXD. The receiver must be enabled, but the transmitter need not be.

Rx U n RXD Input

CPU

Disabled

Tx

Disabled

U n TXD Output

Figure 26-23. Automatic Echo

Because the transmitter is inactive, USR n [TXEMP,TXRDY] are inactive and data is sent as it is received.

Received parity is checked but not recalculated for transmission. Character framing is also checked, but stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected.

26.4.3.2

Local Loop-back Mode

Figure 26-24

shows how U n TXD and U n RXD are internally connected in local loop-back mode. This mode is for testing the operation of a UART by sending data to the transmitter and checking data assembled by the receiver to ensure proper operations.

Rx

Disabled

U n RXD Input

CPU

Tx

Disabled

U n TXD Output

Figure 26-24. Local Loop-back

Features of this local loop-back mode are as follows:

• Transmitter and CPU-to-receiver communications continue normally in this mode.

• U n RXD input data is ignored.

• U n TXD is held marking.

• The receiver is clocked by the transmitter clock. The transmitter must be enabled, but the receiver need not be.

26-24



Preliminary

UART Modules

26.4.3.3

Remote Loop-back Mode

In remote loop-back mode, shown in Figure 26-25

, the UART automatically transmits received data bit by bit on the U n TXD output. The local CPU-to-transmitter link is disabled. This mode is useful in testing receiver and transmitter operation of a remote UART. For this mode, the transmitter uses the receiver clock.

Because the receiver is not active, received data cannot be read by the CPU and all status conditions are inactive. Received parity is not checked and is not recalculated for transmission. Stop bits are sent as they are received. A received break is echoed as received until the next valid start bit is detected.

Disabled

CPU

Disabled

Rx

Disabled

Tx

Disabled

Figure 26-25. Remote Loop-back

U n RXD Input

U n TXD Input

26.4.4

Multidrop Mode

Setting UMR1 n [PM] programs the UART to operate in a wake-up mode for multidrop or multiprocessor applications. In this mode, a master can transmit an address character followed by a block of data characters targeted for one of up to 256 slave stations.

Although slave stations have their receivers disabled, they continuously monitor the master’s data stream.

When the master sends an address character, the slave receiver notifies its respective CPU by setting

USR n [RXRDY] and generating an interrupt (if programmed to do so). Each slave station CPU then compares the received address to its station address and enables its receiver if it wishes to receive the subsequent data characters or block of data from the master station. Unaddressed slave stations continue monitoring the data stream. Data fields in the data stream are separated by an address character. After a slave receives a block of data, its CPU disables the receiver and repeats the process. Functional timing

information for multidrop mode is shown in Figure 26-26 .



Preliminary

26-25

UART Modules

U n TXD

Transmitter

Enabled

A/D

ADD1 1

Master Station

A/D

C0

A/D

ADD2 1

USR n [TXRDY] internal module select

UMR1 n [PM] = 11

UMR1 n [PT] = 1

ADD 1 C0

UMR1 n [PT] = 0

ADD 2

UMR1 n [PT] = 2

Peripheral Station

A/D A/D A/D

U n RXD 0 ADD1 1 C0

Receiver

Enabled

A/D

ADD2 1

A/D

0

USR n [RXRDY] internal module select

UMR1 n [PM] = 11

UMR1 n [PM] = 11

ADD 1 Status Data

(C0)

Figure 26-26. Multidrop Mode Timing Diagram

Status Data

(ADD 2)

A character sent from the master station consists of a start bit, a programmed number of data bits, an address/data (A/D) bit flag, and a programmed number of stop bits. A/D = 1 indicates an address character;

A/D = 0 indicates a data character. The polarity of A/D is selected through UMR1 n [PT]. UMR1 n should be programmed before enabling the transmitter and loading the corresponding data bits into the transmit buffer.

In multidrop mode, the receiver continuously monitors the received data stream, regardless of whether it is enabled or disabled. If the receiver is disabled, it sets the RXRDY bit and loads the character into the receiver holding register FIFO provided the received A/D bit is a one (address tag). The character is discarded if the received A/D bit is zero (data tag). If the receiver is enabled, all received characters are transferred to the CPU through the receiver holding register during read operations.

In either case, the data bits are loaded into the data portion of the FIFO while the A/D bit is loaded into the status portion of the FIFO normally used for a parity error (USR n [PE]).

Framing error, overrun error, and break detection operate normally. The A/D bit takes the place of the parity bit; therefore, parity is neither calculated nor checked. Messages in this mode may still contain error detection and correction information. If 8-bit characters are not required, one way to provide error detection is to use software to calculate parity and append it to the 5-, 6-, or 7-bit character.

26-26



Preliminary

UART Modules

26.4.5

Bus Operation

This section describes bus operation during read, write, and interrupt acknowledge cycles to the UART module.

26.4.5.1

Read Cycles

The UART module responds to reads with byte data. Reserved registers return zeros.

26.4.5.2

Write Cycles

The UART module accepts write data as bytes only. Write cycles to read-only or reserved registers complete normally without exception processing, but data is ignored.

26.4.6

Programming

The software flowchart,

Figure 26-27

, consists of the following:

• UART module initialization—These routines consist of SINIT and CHCHK (See Sheet 1 p. 26-30 and Sheet 2 p. 26-31). Before SINIT is called at system initialization, the calling routine allocates

2 words on the system FIFO. On return to the calling routine, SINIT passes UART status data on the FIFO. If SINIT finds no errors, the transmitter and receiver are enabled. SINIT calls CHCHK to perform the checks. When called, SINIT places the UART in local loop-back mode and checks for the following errors:

— Transmitter never ready

— Receiver never ready

— Parity error

— Incorrect character received

• I/O driver routine—This routine (See Sheet 4 p. 26-33 and Sheet 5 p. 26-34) consists of INCH, the terminal input character routine which gets a character from the receiver, and OUTCH, which sends a character to the transmitter.

• Interrupt handling—This consists of SIRQ (See Sheet 4 p. 26-33), which is executed after the

UART module generates an interrupt caused by a change-in-break (beginning of a break). SIRQ then clears the interrupt source, waits for the next change-in-break interrupt (end of break), clears the interrupt source again, then returns from exception processing to the system monitor.

26.4.6.1

Interrupt and DMA Request Initialization

26.4.6.1.1

Setting up the UART to Generate Core Interrupts

The list below gives the steps needed to properly initialize the UART to generate an interrupt request to the core. See Section 14.2.9.1, “Interrupt Sources,” for details on interrupt assignments for the UART modules.

1. Initialize the appropriate ICR x register in the interrupt controller.

2. Unmask appropriate bits in IMR in the interrupt controller.



Preliminary

26-27

UART Modules

3. Unmask appropriate bits in the core’s status register (SR) to enable interrupts.

4. If TXRDY or RXRDY are being used to generate interrupt requests, then verify that DMAREQC

(in the SCM) does not also assign the UART’s TXRDY and RXRDY into DMA channels.

5. Initialize interrupts in the UART, see

Table 26-14

.

Table 26-14. UART Interrupts

Register

UMR1 n

UIMR n

UIMR n

UIMR n

UIMR n

Bit

2

1

6

7

0

Interrupt

RxIRQ

Change of State (COS)

Delta Break

RxFIFO Full

TXRDY

26.4.6.1.2

Setting up the UART to Request DMA Service

The UART is capable of generating two different DMA request signals: transmit and receive.

The transmit DMA request signal is asserted when the TXRDY (transmitter ready) in the UART interrupt status register (UISR n [TXRDY]) is set. When the transmit DMA request signal is asserted, the DMA can initiate a data copy, reading the next character to be transmitted from memory and writing it into the UART transmit buffer (UTB n ). This would allow the DMA channel to stream data from memory to the UART for transmission without processor intervention. Once the entire message has been moved into the UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) could query the UART programming model to determine the end-of-transmission status.

Similarly, the receive DMA request signal is asserted when the FIFO full or receive ready

(FFULL/RXRDY) flag in the interrupt status register (UISR n [FFULL/RXRDY]) is set. When the receive

DMA request signal is asserted, the DMA can initiate a data move, reading the appropriate characters from the UART receive buffer (URB n ) and storing them in memory. This allows the DMA channel to stream data from the UART receive buffer into memory without processor intervention. Once the entire message has been moved from the UART, the DMA would typically generate an end-of-data-transfer interrupt request to the CPU. The resulting interrupt service routine (ISR) should query the UART programming model to determine the end-of-transmission status. In typical applications, the receive DMA request should be configured to use RXRDY directly (and not FFULL) to remove any complications related to retrieving the final characters from the FIFO buffer.

The implementation described in this section allows independent DMA processing of transmit and receive data while still supporting interrupt notification to the processor for CTS change-of-state and delta break error handling.

26-28



Preliminary

UART Modules

To configure the UART for DMA requests:

1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA channels. For example; setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to

DMA channel 1; setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA channel 2; and so on. It is possible to independently map transmit based and receive based UART

DMA requests in the DMAREQC.

2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared so that interrupt requests are disabled for those conditions for which a DMA request is desired. For example; to generate transmit DMA requests from UART1, then UIMR1[TXRDY] should be cleared. This will prevent TXRDY from generating an interrupt request while a transmit DMA request is generated.

3. Configure the GPACR and appropriate PACR registers located in the SCM for DMA access to

IPSBAR space.

4. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a source and destination size of one byte. This will cause a single byte to be transferred for each UART DMA request.

Table 26-15

shows the DMA requests.

Table 26-15. UART DMA Requests

Register

UISR n

UISR n

Bit

1

0

Receive DMA request

Transmit DMA request

DMA Request

26.4.6.2

UART Module Initialization Sequence

Table 26-16

shows the UART module initialization sequence.

Table 26-16. UART Module Initialization Sequence

Register Setting

UCR n

UIMR n

UACR n

Reset the receiver and transmitter.

Reset the mode pointer (MISC[2–0] = 0b001).

Enable the desired interrupt sources.

Initialize the input enable control (IEC bit).

UCSR n Select the receiver and transmitter clock. Use timer as source if required.

UMR1 n If preferred, program operation of receiver ready-to-send (RXRTS bit).

Select receiver-ready or FIFO-full notification (RXRDY/FFULL bit).

Select character or block error mode (ERR bit).

Select parity mode and type (PM and PT bits).

Select number of bits per character (B/Cx bits).



Preliminary

26-29

UART Modules

Table 26-16. UART Module Initialization Sequence (continued)

Register Setting

UMR2 n Select the mode of operation (CMx bits).

If preferred, program operation of transmitter ready-to-send (TXRTS).

If preferred, program operation of clear-to-send (TXCTS bit).

Select stop-bit length (SBx bits).

UCR n Enable transmitter and/or receiver.

Serial Module

SINIT

Initiate:

Channel

Interrupts

CHK1

Call CHCHK

Save Channel

Status

Enable

Any

Errors?

N

Enable Receiver

Y

Assert

Request To Send

SINITR

Return

Figure 26-27. UART Mode Programming Flowchart (Sheet 1 of 5)

26-30



Preliminary

UART Modules

CHCHK

CHCHK

Place Channel In

Local Loopback

Mode

Enable

Transmitter Clear

Status Word

TxCHK

Is

Transmitter

Ready?

SNDCHR Y

Send Character

To Transmitter

RxCHK

Has

Character Been

Received?

Y

A

N

N

N

Waited

Too Long?

N

Waited

Too Long?

Y Set Transmitter-

Never-ready Flag

Y

Set Receiver-

Never-ready Flag


B



Preliminary

26-31

UART Modules

A

FRCHK

Have

Framing Error?

N

Set Framing

Error Flag

PRCHK

Have

Parity Error?

Y

Set Parity

Error Flag

CHRCHK

Get Character

From Receiver

N

Same As

Transmitted

Character?

N

Set Incorrect

Character Flag

Y

RSTCHN

B

Disable

Transmitter

Restore

To Original Mode

Return

B


26-32



Preliminary

ABRKI

SIRQ

Was

IRQ Caused

By Beginning

Of A Break?

Y

Clear Change-in-

Break Status Bit

ABRKI1

Has

End-of-break

IRQ Arrived

Yet?

Y

Clear Change-in-

Break Status Bit

N

N

Remove Break

Character From

Receiver FIFO

INCH

Does

Channel A

Receiver Have A

Character?

Y

Place Character

In D0

N

Return

Replace Return

Address On System

Stack And Monitor

Warm Start Address

SIRQR

RTE


UART Modules



Preliminary

26-33

UART Modules

OUTCH

Is

Transmitter

Ready?

Y

Send Character

To Transmitter

N

Return


26-34



Preliminary

I

Chapter 27

2

C Interface

27.1

Introduction

This chapter describes the I

2

C module, clock synchronization, and I

2 also provides extensive programming examples.

C programming model registers. It

27.2

Overview

I

2

C is a two-wire, bidirectional serial bus that provides a simple, efficient method of data exchange, minimizing the interconnection between devices. This bus is suitable for applications that require occasional communication between many devices over a short distance. The flexible I

2

C bus allows additional devices to be connected to the bus for expansion and system development.

The interface is designed to operate up to 100 Kbps with maximum bus loading and timing. The device is capable of operating at higher baud rates, up to a maximum of the internal bus clock divided by 20, with reduced bus loading. The maximum communication length and the number of devices that can be connected are limited by a maximum bus capacitance of 400 pF.

The I

2

C system is a true multiple-master bus; it uses arbitration and collision detection to prevent data corruption in the event that multiple devices attempt to control the bus simultaneously. This feature supports complex applications with multiprocessor control and can be used for rapid testing and alignment of end products through external connections to an assembly-line computer.

The I

2

NOTE

C module is designed to be compatible with the Philips I

2

C bus protocol. For information on system configuration, protocol, and restrictions, see The I

2

C Bus Specification, Version 2.1

.

NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 13, “General Purpose I/O Module” ) prior to configuring the I

2

C module.

27.3

Features

The I

2

C module has the following key features:

• Compatibility with I

2

C bus standard version 2.1

• Support for 3.3-V tolerant devices

• Multiple-master operation



Preliminary

27-1

I

2

C Interface

• Software-programmable for one of 50 different serial clock frequencies

• Software-selectable acknowledge bit

• Interrupt-driven, byte-by-byte data transfer

• Arbitration-lost interrupt with automatic mode switching from master to slave

• Calling address identification interrupt

• START and STOP signal generation/detection

• Repeated START signal generation

• Acknowledge bit generation/detection

• Bus-busy detection

Figure 27-1

is a block diagram of the I

2

C module.

IRQ

Internal Bus

Address Data

Registers and ColdFire Interface

Address Decode Data MUX

I

2

C Frequency

Divider Register

(IFDR)

Clock

Control

I

2

C Control

Register

(I2CR)

Start, Stop, and

Arbitration

Control

I

2

C Status

Register

(I2SR)

I

2

C Data

I/O Register

(I2DR)

I

2

C Address

Register

(IADR)

In/Out

Data

Shift

Register

Input

Sync

Address

Compare

I2C_SCL I2C_SDA

Figure 27-1. I

2

C Module Block Diagram

Figure 27-1

shows the I

Definition”

:

2

C registers, which are described in Section 27.5, “Memory Map/Register

• I

2

C address register (I2ADR)

• I

2

C frequency divider register (I2FDR)

27-2



Preliminary

I

2

C Interface

• I

2

C control register (I2CR)

• I

2

C status register (I2SR)

• I

2

C data I/O register (I2DR)

27.4

I

2

C System Configuration

The I

2

C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For

I

2

C compliance, all devices connected to these two signals must have open drain or open collector outputs.

The logic AND function is exercised on both lines with external pull-up resistors.

Out of reset, the I

2

C default state is as a slave receiver. Thus, when not programmed to be a master or responding to a slave transmit address, the I

2

C module should return to the default slave receiver state. See

Section 27.6.1, “Initialization Sequence,”

for exceptions.

Normally, a standard communication is composed of four parts: START signal, slave address transmission, data transfer, and STOP signal. These are discussed in the following sections.

27.4.1

START Signal

When no other device is bus master (both I2C_SCL and I2C_SDA lines are at logic high), a device can initiate communication by sending a START signal (see A in

Figure 27-2

). A START signal is defined as a high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data transfer (each data transfer can be several bytes long) and awakens all slaves.

I2C_SCL msb

1 2 3 4 5 6

Interrupt bit set

(Byte complete)

I2C_SCL held low while

Interrupt is serviced lsb

7 8 msb

2 3 4 5 6 lsb

7 8

I2C_SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

A

START

Signal

XXX D7 D6 D5 D4 D3 D2 D1 D0

Calling Address

B

E

Data Byte

R/W ACK

C

Bit

D

Figure 27-2. I

2

C Standard Communication Protocol

No

ACK

Bit

STOP

Signal

F

27.4.2

Slave Address Transmission

The master sends the slave address in the first byte after the START signal (B). After the seven-bit calling address, it sends the R/W bit (C), which tells the slave data transfer direction (0 = write transfer, 1 = read transfer).

Each slave must have a unique address. An I

2

C master must not transmit its own slave address; it cannot be master and slave at the same time.



Preliminary

27-3

I

2

C Interface

The slave whose address matches that sent by the master pulls I2C_SDA low at the ninth serial clock (D) to return an acknowledge bit.

27.4.3

Data Transfer

When successful slave addressing is achieved, the data transfer can proceed (see E in

Figure 27-2

) on a byte-by-byte basis in the direction specified by the R/W bit sent by the calling master.

Data can be changed only while I2C_SCL is low and must be held stable while I2C_SCL is high, as

Figure 27-2

shows. I2C_SCL is pulsed once for each data bit, with the msb being sent first. The receiving device must acknowledge each byte by pulling I2C_SDA low at the ninth clock; therefore, a data byte

transfer takes nine clock pulses. See Figure 27-3 .

I2C_SCL

I2C_SCL Held Low while

Interrupt is Serviced

1 2 3 4 5 6 7 8 9

I2C_SDA

START

Signal

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1

Bit0

R/W

Slave Address

ACK from

Receiver

1 2 3 4 5 6 7 8 9

Interrupt Bit Set

(Byte Complete)

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Data Byte

No

ACK

Bit

STOP

Signal

Figure 27-3. Data Transfer

27.4.4

Acknowledge

The transmitter releases the I2C_SDA line high during the acknowledge clock pulse as shown in

Figure 27-4

. The receiver pulls down the I2C_SDA line during the acknowledge clock pulse so that it remains stable low during the high period of the clock pulse.

If it does not acknowledge the master, the slave receiver must leave I2C_SDA high. The master can then generate a STOP signal to abort the data transfer or generate a START signal (repeated start, shown in

Figure 27-5 and discussed in Section 27.4.6, “Repeated START”

) to start a new calling sequence.

27-4



Preliminary

I

2

C Interface

I2C_SCL

I2C_SDA by Transmitter

I2C_SDA by Receiver

1 2 3 4 5 6 7 8 9

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1

Bit0

R/W

START Signal

Figure 27-4. Acknowledgement by Receiver

ACK

If the master receiver does not acknowledge the slave transmitter after a byte transmission, it means end-of-data to the slave. The slave releases I2C_SDA for the master to generate a STOP or START signal

(

Figure 27-4

).

27.4.5

STOP Signal

The master can terminate communication by generating a STOP signal to free the bus. A STOP signal is defined as a low-to-high transition of I2C_SDA while I2C_SCL is at logical high (see F in

Figure 27-2

).

The master can generate a STOP even if the slave has generated an acknowledgment, at which point the slave must release the bus. The master may also generate a START signal following a calling address, without first generating a STOP signal. Refer to

Section 27.4.6, “Repeated START.”

27.4.6

Repeated START

A repeated START signal is a START signal generated without first generating a STOP signal to terminate the communication. The master uses a repeated START to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus.

I2C_SCL msb

1 2 3 4 5 lsb

6 7 8 9 msb

1 2 3 4 5 lsb

6 7 8 9

I2C_SDA AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XX AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

START

Signal

Calling Address

R/W ACK

Bit

Repeated

START

Signal

A

New Calling Address

Stop

Figure 27-5. Repeated START

R/W No

ACK

Bit

STOP

Signal

Various combinations of read/write formats are then possible:

• The first example in

Figure 27-6

is the case of master-transmitter transmitting to slave-receiver.

The transfer direction is not changed.



Preliminary

27-5

I

2

C Interface

•

The second example in Figure 27-6

is the master reading the slave immediately after the first byte.

At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the slave-receiver becomes slave-transmitter.

•

In the third example in Figure 27-6 , the START condition and slave address are both repeated using

the repeated START signal. This is to communicate with same slave in a different mode without releasing the bus. The master transmits data to the slave first, and then the master reads data from slave by reversing the R/W bit.

ST = Start

SP = Stop

A = Acknowledge (I2C_SDA low)

A = Not Acknowledge (I2C_SDA high)

Rept ST = Repeated Start

From Master to Slave

From Slave to Master

Example 1:

ST 7bit Slave Address

R/W

0 A Register Address A DATA A/A SP

Example 2:

ST 7bit Slave Address

Note: No acknowledge on the last byte

R/W

1 A DATA A DATA A SP

Example 3:

ST

7-bit Slave

Address

R/W

1 A DATA A

Rept

ST

R/W

7-bit Slave 0

Address

A DATA A DATA A/A SP

Master Reads from Slave Master Writes to Slave

Figure 27-6. Data Transfer, Combined Format

27.4.7

Clock Synchronization and Arbitration

I

2

C is a true multi-master bus that allows more than one master to be connected to it. If two or more master devices simultaneously request control of the bus, a clock synchronization procedure determines the bus clock. Because wire-AND logic is performed on the I2C_SCL line, a high-to-low transition on the

I2C_SCL line affects all the devices connected on the bus. The devices start counting their low period and once a device’s clock has gone low, it holds the I2C_SCL line low until the clock high state is reached.

However, the change of low to high in this device’s clock may not change the state of the I2C_SCL line if another device clock is still within its low period. Therefore, synchronized clock I2C_SCL is held low by the device with the longest low period.

Devices with shorter low periods enter a high wait state during this time (see

Figure 27-8

). When all devices concerned have counted off their low period, the synchronized clock (I2C_SCL) line is released and pulled high. At this point, the device clocks and the I2C_SCL line are synchronized, and the devices start counting their high periods. The first device to complete its high period pulls the I2C_SCL line low again.

27-6



Preliminary

I

2

C Interface

The relative priority of the contending masters is determined by a data arbitration procedure. A bus master loses arbitration if it transmits logic 1 while another master transmits logic 0. The losing masters

immediately switch over to slave receive mode and stop driving I2C_SDA output (see Figure 27-7 ). In this

case the transition from master to slave mode does not generate a STOP condition. Meanwhile, hardware sets I2SR[IAL] to indicate loss of arbitration.

I2C_SCL

I2C_SDA by

Master1

I2C_SDA by

Master2

I2C_SDA

Master 2 Loses Arbitration, and becomes slave-receiver

Figure 27-7. Arbitration Procedure

Wait

Start counting high period

I2C_SCL1

I2C_SCL2

I2C_SCL

Internal Counter Reset

Figure 27-8. Clock Synchronization

27.4.8

Handshaking and Clock Stretching

The clock synchronization mechanism can be used as a handshake in data transfers. Slave devices can hold

I2C_SCL low after completing one byte transfer. In such a case, the clock mechanism halts the bus clock and forces the master clock into wait states until the slave releases I2C_SCL.

Slaves may also slow down the transfer bit rate. After the master has driven I2C_SCL low, the slave can drive I2C_SCL low for the required period and then release it. If the slave I2C_SCL low period is longer than the master I2C_SCL low period, the resulting I2C_SCL bus signal low period is stretched.

27.5


Table 27-1

lists the configuration registers used in the I

2

C interface.



Preliminary

27-7

I

2

C Interface

Table 27-1. I

2

C Module Memory Map

IPSBAR

Offset

Register

0x00_0300 I

2

C Address Register (I2ADR)

0x00_0304 I

2

C Frequency Divider Register (I2FDR)

0x00_0308 I

2

C Control Register (I2CR)

0x00_030C I

2

C Status Register (I2SR)

0x00_0310 I

2

C Data I/O Register (I2DR)


R/W

R/W

R/W

R/W

R/W

0x00

0x00

0x00

0x81

0x00

27.5.1/27-8

27.5.2/27-8

27.5.3/27-9

27.5.4/27-10

27.5.5/27-11

27.5.1

I

2

C Address Register (I2ADR)

The I2ADR holds the address the I

2

C responds to when addressed as a slave. Note that it is not the address sent on the bus during the address transfer when the module is performing a master transfer.

Address: 0x00_0300 (I2ADR)

7 6

R

W

Reset: 0

5 4

ADR

3 2

0 0 0 0

Figure 27-9. I

2

C Address Register (I2ADR)

0

Table 27-2. I2ADR Field Descriptions


1 0

0

0 0

Field

7–1

ADR

0

Description

Slave address. Contains the specific slave address to be used by the I

2

C module. Slave mode is the default I

2

C mode for an address match on the bus.


27.5.2

I

2

C Frequency Divider Register (I2FDR)

The I2FDR, shown in Figure 27-10 , provides a programmable prescaler to configure the I

2

C clock for bit-rate selection.


1 0

Address: 0x00_0304 (I2FDR)

7

0 R

W

Reset: 0

6

0

5 4 3

IC

2

0 0 0 0 0

Figure 27-10. I

2

C Frequency Divider Register (I2FDR)

0 0

27-8



Preliminary

I

2

C Interface

Table 27-3. I2FDR Field Descriptions

Field

7–6

5–0

IC

Description


I

2

C clock rate. Prescales the clock for bit-rate selection. The serial bit clock frequency is equal to the internal bus clock divided by the divider shown below. Due to potentially slow I2C_SCL and I2C_SDA rise and fall times, bus signals are sampled at the prescaler frequency.

IC

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

0x00

0x01

0x02

0x03

0x04

0x05

0x06

0x07

Divider

144

160

192

240

80

88

104

128

44

48

56

68

28

30

34

40

IC

0x18

0x19

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

Divider IC

1152

1280

1536

1920

2304

2560

3072

3840

576

640

768

960

288

320

384

480

0x28

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

0x2F

0x20

0x21

0x22

0x23

0x24

0x25

0x26

0x27

Divider

80

96

112

128

48

56

64

72

28

32

36

40

20

22

24

26

IC

0x38

0x39

0x3A

0x3B

0x3C

0x3D

0x3E

0x3F

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

Divider

640

768

896

1024

1280

1536

1792

2048

320

384

448

512

160

192

224

256

27.5.3

I

2

C Control Register (I2CR)

The I2CR is used to enable the I

2

C module and the I

2

C interrupt. It also contains bits that govern operation as a slave or a master.

Address: 0x00_0308 (I2CR)

7

R

W

Reset:

IEN

0

6

IIEN

5

MSTA

4

MTX

3

TXAK

2

RSTA

0 0 0 0

Figure 27-11. I

2

C Control Register (I2CR)

0


1

0

0

0

0 0



Preliminary

27-9

I

2

C Interface

Table 27-4. I2CR Field Descriptions

Field

7

IEN

6

IIEN

5

MSTA

4

MTX

3

TXAK

2

RSTA

1–0

Description

I

2

C enable. Controls the software reset of the entire I

2

C module. If the module is enabled in the middle of a byte transfer, slave mode ignores the current bus transfer and starts operating when the next START condition is detected.

Master mode is not aware that the bus is busy; so initiating a start cycle may corrupt the current bus cycle, ultimately causing either the current master or the I

2

C module to lose arbitration, after which bus operation returns to normal.

0 The I

2

C module is disabled, but registers can still be accessed.

1 The I

2

C module is enabled. This bit must be set before any other I2CR bits have any effect.

I

2

C interrupt enable.

0 I

2

C module interrupts are disabled, but currently pending interrupt condition is not cleared.

1 I

2

C module interrupts are enabled. An I

2

C interrupt occurs if I2SR[IIF] is also set.

Master/slave mode select bit. If the master loses arbitration, MSTA is cleared without generating a STOP signal.

0 Slave mode. Changing MSTA from 1 to 0 generates a STOP and selects slave mode.

1 Master mode. Changing MSTA from 0 to 1 signals a START on the bus and selects master mode.

Transmit/receive mode select bit. Selects the direction of master and slave transfers.

0 Receive

1 Transmit. When the device is addressed as a slave, software should set MTX according to I2SR[SRW]. In master mode, MTX should be set according to the type of transfer required. Therefore, when the MCU addresses a slave device, MTX is always 1.

Transmit acknowledge enable. Specifies the value driven onto I2C_SDA during acknowledge cycles for both master and slave receivers. Note that writing TXAK applies only when the I

2

C bus is a receiver.

0 An acknowledge signal is sent to the bus at the ninth clock bit after receiving one byte of data.

1 No acknowledge signal response is sent (that is, acknowledge bit = 1).

Repeat start. Always read as 0. Attempting a repeat start without bus mastership causes loss of arbitration.

0 No repeat start

1 Generates a repeated START condition.


27.5.4

I

2

C Status Register (I2SR)

This I2SR contains bits that indicate transaction direction and status.

Address: 0x00_030C (I2SR)

7

ICF R

W

Reset: 1

6

IAAS

5

IBB

4

IAL

3

0

0 0 0 0

Figure 27-12. I

2

C Status Register (I2SR)

2

SRW

0


1 0

RXAK

IIF

0 1

27-10



Preliminary

I

2

C Interface

Table 27-5. I2SR Field Descriptions

Field

7

ICF

6

IAAS

5

IBB

4

IAL

3

2

SRW

1

IIF

0

RXAK

Description

I

2

C Data transferring bit. While one byte of data is transferred, ICF is cleared.

0 Transfer in progress

1 Transfer complete. Set by the falling edge of the ninth clock of a byte transfer.

I

2

C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set its TX/RX mode accordingly. Writing to I2CR clears this bit.

0 Not addressed.

1 Addressed as a slave. Set when its own address (IADR) matches the calling address.

I

2

C bus busy bit. Indicates the status of the bus.

0 Bus is idle. If a STOP signal is detected, IBB is cleared.

1 Bus is busy. When START is detected, IBB is set.

I

2

C arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero to it.)

• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.

• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.

• A start cycle is attempted when the bus is busy.

• A repeated start cycle is requested in slave mode.

• A stop condition is detected when the master did not request it.


Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated, and the I

2

C module is a slave and has an address match.

0 Slave receive, master writing to slave.

1 Slave transmit, master reading from slave.

I

2

C interrupt. Must be cleared by software by writing a zero in the interrupt routine.

0 No I

2

C interrupt pending

1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following occurs:

• Complete one byte transfer (set at the falling edge of the ninth clock)

• Reception of a calling address that matches its own specific address in slave-receive mode

• Arbitration lost

Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.

0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus

1 No acknowledge signal was detected at the ninth clock.

27.5.5

I

2

C Data I/O Register (I2DR)

In master-receive mode, reading the I2DR allows a read to occur and for the next data byte to be received.

In slave mode, the same function is available once the I

2

C has received its slave address.



Preliminary

27-11

I

2

C Interface

Address: 0x00_0310 (I2DR)

7

R

W

Reset: 0

6 5 4

DATA

3 2

0 0 0 0

Figure 27-13. I

2

C Data I/O Register (I2DR)

0


1 0

0 0

Field

7–0

DATA

Table 27-6. I2DR Field Description

Description

I

2

C data. In master transmit mode, when data is written to this register, a data transfer is initiated. The most significant bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data.

In slave mode, the same functions are available after an address match has occurred.

Note: In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for the address transfer and should comprise the calling address (in position D7–D1) concatenated with the required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must provide the appropriate R/W bit.

Note: I2CR[MSTA] generates a start when a master does not already own the bus. I2CR[RSTA] generates a start

(restart) without the master first issuing a stop (i.e., the master already owns the bus). In order to start the read of data, a dummy read to this register starts the read process from the slave. The next read of the I2DR register contains the actual data.

27.6

I

2

C Programming Examples

The following examples show programming for initialization, signaling START, post-transfer software response, signaling STOP, and generating a repeated START.

27.6.1

Initialization Sequence

Before the interface can transfer serial data, registers must be initialized:

1. Set I2FDR[IC] to obtain I2C_SCL frequency from the system bus clock. See Section 27.5.2, “I2C

Frequency Divider Register (I2FDR).”

2. Update the I2ADR to define its slave address.

3. Set I2CR[IEN] to enable the I

2

C bus interface system.

4. Modify the I2CR to select or deselect master/slave mode, transmit/receive mode, and interrupt-enable or not.

NOTE

If I2SR[IBB] is set when the I

2

C bus module is enabled, execute the following pseudocode sequence before proceeding with normal initialization code. This issues a STOP command to the slave device, placing it in idle state as if it were just power-cycled on.

I2CR = 0x0

I2CR = 0xA0 dummy read of I2DR

27-12



Preliminary

I

2

C Interface

I2SR = 0x0

I2CR = 0x0

27.6.2

Generation of START

After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. On a multiple-master bus system, I2SR[IBB] must be tested to determine whether the serial bus is free. If the bus is free (IBB = 0), the START signal and the first byte (the slave address) can be sent. The data written to the data register comprises the address of the desired slave and the lsb indicates the transfer direction.

The free time between a STOP and the next START condition is built into the hardware that generates the

START cycle. Depending on the relative frequencies of the system clock and the I2C_SCL period, it may be necessary to wait until the I2C is busy after writing the calling address to the I2DR before proceeding with the following instructions.

The following example signals START and transmits the first byte of data (slave address):

CHFLAG MOVE.B I2SR,-(A0)

BTST.B #5, (A0)+

BNE.S CHFLAG

TXSTART MOVE.B I2CR,-(A0)

BSET.B #4,(A0)

MOVE.B (A0)+, I2CR

MOVE.B I2CR, -(A0)

BSET.B #5, (A0)

MOVE.B (A0)+, I2CR

IFREE

MOVE.B CALLING,-(A0)

MOVE.B (A0)+, I2DR

MOVE.B I2SR,-(A0)

;Check I2SR[MBB]

;If I2SR[MBB] = 1, wait until it is clear

;Set transmit mode

;Set master mode

;Generate START condition

;Transmit the calling address, D0=R/W

;Check I2SR[MBB]

;If it is clear, wait until it is set.

BTST.B #5, (A0)+

BEQ.S IFREE;

27.6.3

Post-Transfer Software Response

Sending or receiving a byte sets the I2SR[ICF], which indicates one byte communication is finished.

I2SR[IIF] is also set. An interrupt is generated if the interrupt function is enabled during initialization by setting I2CR[IIEN]. Software must first clear I2SR[IIF] in the interrupt routine. I2SR[ICF] is cleared either by reading from I2DR in receive mode or by writing to I2DR in transmit mode.

Software can service the I2C I/O in the main program by monitoring the IIF bit if the interrupt function is disabled. Polling should monitor IIF rather than ICF, because that operation is different when arbitration is lost.

When an interrupt occurs at the end of the address cycle, the master is always in transmit mode; that is, the address is sent. If master receive mode is required, I2CR[MTX] should be toggled.

During slave-mode address cycles (I2SR[IAAS] = 1), I2SR[SRW] is read to determine the direction of the next transfer. MTX is programmed accordingly. For slave-mode data cycles (IAAS = 0), SRW is invalid.

MTX should be read to determine the current transfer direction.



Preliminary

27-13

I

2

C Interface

The following is an example of a software response by a master transmitter in the interrupt routine (see

Figure 27-14

).

I2SR LEA.L I2SR,-(A7)

BCLR.B #1,(A7)+

MOVE.B I2CR,-(A7)

BTST.B #5,(A7)+

BEQ.S SLAVE

MOVE.B I2CR,-(A7)

BTST.B #4,(A7)+

BEQ.S RECEIVE

MOVE.B I2SR,-(A7)

BTST.B #0,(A7)+

BNE.B END

TRANSMIT MOVE.B DATABUF,-(A7)

MOVE.B (A7)+, I2DR

;Load effective address

;Clear the IIF flag

;Push the address on stack,

;check the MSTA flag

;Branch if slave mode

;Push the address on stack

;check the mode flag

;Branch if in receive mode

;Push the address on stack,

;check ACK from receiver

;If no ACK, end of transmission

;Stack data byte

;Transmit next byte of data

27.6.4

Generation of STOP

A data transfer ends when the master signals a STOP, which can occur after all data is sent, as in the following example.

MASTX ;If no ACK, branch to end

END

MOVE.B I2SR, -(A7)

BTST.B #0,(A7)+

BNE.B END

MOVE.B TXCNT,D0

BEQ.S END

MOVE.B DATABUF,-(A7)

MOVE.B (A7)+,I2DR

MOVE.B TXCNT,D0

SUBQ.L #1,D0

MOVE.B D0,TXCNT

BRA.S EMASTX;Exit

LEA.L I2CR,-(A7)

BCLR.B #5,(A7)+

EMASTX RTE

;Get value from the transmitting counter

;If no more data, branch to end

;Transmit next byte of data

;Decrease the TXCNT

;Generate a STOP condition

;Return from interrupt

For a master receiver to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last data byte. This is done by setting I2CR[TXAK] before reading the next-to-last byte. Before the last byte is read, a STOP signal must be generated, as in the following example.

MASR MOVE.B RXCNT,D0

SUBQ.L #1,D0

MOVE.B D0,RXCNT

BEQ.S ENMASR

MOVE.B RXCNT,D1

EXTB.L D1

SUBI.L #1,D1;

BNE.S NXMAR

LAMAR BSET.B #3,I2CR

BRA NXMAR

ENMASR BCLR.B #5,I2CR

NXMAR MOVE.B I2DR,RXBUF

;Decrease RXCNT

;Last byte to be read

;Check second-to-last byte to be read

;Not last one or second last

;Disable ACK

;Last one, generate STOP signal

;Read data and store RTE

27-14



Preliminary

I

2

C Interface

27.6.5

Generation of Repeated START

After the data transfer, if the master still wants the bus, it can signal another START followed by another slave address without signaling a STOP, as in the following example.

;Repeat START (RESTART) RESTART MOVE.B I2CR,-(A7)

BSET.B #2, (A7)

MOVE.B (A7)+, I2CR



MOVE.B (A7)+, I2DR

;Transmit the calling address, D0=R/W-

27.6.6

Slave Mode

In the slave interrupt service routine, software should poll the I2SR[IAAS] bit to determine if the controller has received its slave address. If IAAS is set, software should set the transmit/receive mode select bit

(I2CR[MTX]) according to the I2SR[SRW]. Writing to the I2CR clears the IAAS automatically. The only time IAAS is read as set is from the interrupt at the end of the address cycle where an address match occurred; interrupts resulting from subsequent data transfers will have IAAS cleared. A data transfer can now be initiated by writing information to I2DR for slave transmits, or read from I2DR in slave-receive mode. A dummy read of I2DR in slave/receive mode releases I2C_SCL, allowing the master to send data.

In the slave transmitter routine, I2SR[RXAK] must be tested before sending the next byte of data. Setting

RXAK means an end-of-data signal from the master receiver, after which software must switch it from transmitter to receiver mode. Reading I2DR then releases I2C_SCL so that the master can generate a STOP signal.

27.6.7

Arbitration Lost

If several devices try to engage the bus at the same time, one becomes master. Hardware immediately switches devices that lose arbitration to slave receive mode. Data output to I2C_SDA stops, but I2C_SCL is still generated until the end of the byte during which arbitration is lost. An interrupt occurs at the falling edge of the ninth clock of this transfer with I2SR[IAL] = 1 and I2CR[MSTA] = 0.

If a device that is not a master tries to transmit or execute a START, hardware will inhibit the transmission, clear MSTA without signaling a STOP, generate an interrupt to the CPU, and set IAL to indicate a failed attempt to engage the bus. When considering these cases, the slave service routine should first test IAL and software should clear it if it is set.



Preliminary

27-15

I

2

C Interface

Clear

IIF

Y Master

Mode?

N

TX TX/Rx

?

RX Y

Arbitration

Lost?

N

Last Byte

Transmitted

?

N

Y

Y

RXAK= 0

?

Y

N

End of

ADDR Cycle

(Master RX)

?

N

Write Next

Byte to I2DR

Last

Byte to be

Read ?

N

Y

Y

2nd Last

Byte to be

Read?

N

Set TXAK =1

Generate

STOP Signal

Clear IAL

N

IAAS=1

?

Address

Cycle

Y

(Read) Y

Y

SRW=1

?

N (WRITE)

IAAS=1

?

N

Data

Cycle

Tx/Rx

?

TX

RX

Set TX

Mode

Write Data to I2DR

Y

Tx Next

Byte

ACK from

Receiver

?

N

Read Data from I2DR and Store

Switch to

Rx Mode

Set RX

Mode

Switch to

Rx Mode

Dummy Read from I2DR

Generate

STOP Signal

Read Data from I2DR

And Store



RTE

Figure 27-14. Flow-Chart of Typical I

2

C Interrupt Routine

27-16



Preliminary

Chapter 28


28.1

Introduction

The analog-to-digital converter (ADC) consists of two separate and complete ADCs, each with their own sample and hold circuits. The converters share a common voltage reference and common digital control module.

28.2

Features

The ADC’s characteristics include the following:

• 12-bit resolution

• Maximum ADC clock frequency of 5.0 MHz, 200ns period

• Sampling rate up to 1.66 million samples per second

1

• Single conversion time of 8.5 ADC clock cycles (8.5 × 200ns = 1.7

µ s)

• Additional conversion time of 6 ADC clock cycles (6 × 200ns = 1.2

µ s)

• Eight conversions in 26.5 ADC clocks (26.5

× 200ns = 5.3

µ s) using simultaneous mode

• Ability to simultaneously sample and hold 2 inputs

• Ability to sequentially scan and store up to 8 measurements

• Internal multiplex to select two of 8 inputs

• Power savings modes allow automatic shutdown/startup of all or part of ADC

• Those inputs not selected tolerate injected/sourced current without affecting ADC performance, supporting operation in noisy industrial environments.

• Optional interrupts at the end of a scan, if an out-of-range limit is exceeded (high or low), or at zero crossing

• Optional sample correction by subtracting a pre-programmed offset value

• Signed or unsigned result

• Single ended or differential inputs for all input pins with support for an arbitrary mix of input types

28.3

Block Diagram

The ADC function, shown in

Figure 28-1 ,

consists of two four-channel input select functions, interfacing with two independent Sample and Hold (S/H) circuits, which feed two 12-bit ADCs. The two converters store their results in a buffer, awaiting further processing.

1. Once in loop mode, the time between each conversion is 6 ADC clock cycles (1.2

µ s at 5.0 MHz). Using simultaneous conversion, two samples are captured in 1.2

µ s, providing an overall sample rate of 1.66 million samples per second.



Preliminary

28-1


V

REFH

V

REFL

Voltage

Reference

Circuit

Scaling & Cyclic

Converter A

12

Scaling & Cyclic

Converter B

12

Digital Output

Storage Registers

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

MUX

MUX

Sample/Hold

16

SYNCx Controller Bus Interface

IRQ

Data

Figure 28-1. Dual ADC Block Diagram

28.4


The ADC’s conversion process is either initiated by a sync signal from one of two input pins (SYNCx) or by writing 1 to a START n bit.

Starting a single conversion actually begins a sequence of conversions, or a scan of up to 8 single-ended or differential samples one at a time in sequential scan mode. The operation of the module in sequential

scan mode is shown in Figure 28-2 .

28-2



Preliminary


HILIM[0:3]

>

ADC0

ADC1

ADC2

LOLIM[0:3]

AN0

AN1

AN2

AN3

V

REFL

V+

V–

ADCA

Test Data

(From CPU)

12

12

Zero Crossing Logic

<

12

+

–

+

13

OFFST[0:3]

RSLT[0:3]

End of

Scan A

Interrupt

Channel Select

Single-Ended vs

Differential

Zero Crossing or Error Limit

Interrupt

HILIM[4:7]

AN4

AN5

AN6

AN7

V

REFL

Crossbars allow AN0-3 to be stored in samples 4-7, or AN4-7 to be stored in samples 0-3

LOLIM[4:7]

>

<

Zero Crossing Logic

V+

V–

ADCB

12

12

Channel Select

Single-Ended vs

Differential

Test Data

(From CPU)

12

+

–

+

13

OFFST[4:7]

RSLT[4:7]

Figure 28-2. Sequential Mode Operation of the ADC

End of

Scan B

Interrupt

Scan sequence is determined by defining 8 sample slots in ADLST1/2 registers, processed in order

SAMPLE0-7 during sequential scan, or in order SAMPLE0-3 by converter A and in order SAMPLE4-7 by converter B in parallel scan. SAMPLE slots may be disabled using the SDIS register.

The following pairs of analog inputs can be configured as a differential pair: AN0-1, AN2-3, AN4-5, and

AN6-7. When configured as a differential pair, a reference to either member of the differential pair by a sample slot results in a differential measurement using that differential pair.

Parallel scan can be simultaneous or non-simultaneous. During simultaneous scan, the scans in the two converters are done simultaneously and always result in simultaneous pairs of conversions, one by converter A and one by converter B. The two converters share the same start, stop, sync, end-of-scan interrupt enable control, and interrupt. Scanning in both converters is terminated when either converter encounters a disabled sample. In non-simultaneous scan, the parallel scans in the two converters are achieved independently. The two converters have their own start, stop, sync, end-of-scan interrupt enable controls, and end-of-scan interrupts. Scanning in either converter terminates only when that converter encounters a disabled sample in its part of SDIS register (DS0-DS3 for A, DS4-DS7 for B).



Preliminary

28-3


HILIM[0:3]

>

ADC0

ADC1

ADC2

LOLIM[0:3]

AN0

AN1

AN2

AN3

V

REFL

V+

V–

ADCA

Test Data

(From CPU)

12

12

Zero Crossing Logic

<

12

+

–

+

13

OFFST[0:3]

RSLT[0:3]

End of

Scan A

Interrupt

Channel Select

Single-Ended vs

Differential


Interrupt

HILIM[4:7]

Crossbars do not operate in this mode

LOLIM[4:7]

>

AN4

AN5

AN6

AN7

V

REFL

End of

Scan B

Interrupt

<

Zero Crossing Logic

V+

V–

ADCB

12

12

Channel Select

Single-Ended vs

Differential

Test Data

(From CPU)

12

+

–

+

13

OFFST[4:7]

RSLT[4:7]

Figure 28-3. Parallel Mode Operation of the ADC

The ADC can be configured to perform a single scan and halt, perform a scan whenever triggered, or perform the scan sequence repeatedly until manually stopped. The single scan (once mode) differs from the triggered mode only in that SYNC input signals must be re-armed after each using a once mode scan, and subsequent SYNC inputs are ignored until the SYNC input is re-armed. This arming can occur anytime after the SYNC pulse occurs, even while the scan it initiated is still in process.

Optional interrupts can be generated at the end of a scan sequence. Interrupts are available simply to indicate the scan ended, that a sample was out of range, or at several different zero crossing conditions.

Out-of-range is determined by the high and low limit registers.

To understand the operation of the ADC, it is important to understand the features and limitations of each of the functional parts.

28-4



Preliminary


28.4.1

Input MUX Function

The input MUX function is shown in Figure 28-4 .

The channel select and single ended vs. differential switches are indirectly controlled based on settings within the LIST1, LIST2, and SDIS registers, and the

CHNCFG field of the CTRL1 register.

1. MUXing for Sequential mode, single-ended conversions—During each conversion cycle (sample), any one input of the two muxes can be directed to any RSLT n register.

2. MUXing for sequential mode, differential conversions—During any conversion cycle (sample), either member of a differential pair may be referenced as a SAMPLE, resulting in a differential measurement on that pair being stored in the corresponding RSLT n register.

3. MUXing for parallel mode, single-ended conversions—During any conversion cycle (sample), any of AN0-AN3 can be directed to an RSLT0-3 Result register and any of AN4-AN7 can be directed to the RSLT4-7.

4. MUXing for parallel mode, differential conversions—During any conversion cycle (sample), either member of differential pair AN0/1 or either member of differential pair AN2/3 can be referenced as a SAMPLE, resulting in a differential measurement of that pair being stored in one of the RSLT0-3 registers. Likewise, either member of differential pair AN4/5 or either member of differential pair AN6/7 can be referenced as a SAMPLE, resulting in a differential measurement of that pair being stored in one of the RSLT4-7 registers.

Details of switch operation is shown in Table 28-2 .

Internally, all measurements are performed differentially. During single ended measurements, V

REFL the selected analog input is used as the positive ( + ) input.

is used as the negative (-) input voltage, while

Table 28-2. Analog MUX Controls for Each Conversion Mode

Conversion Mode

Sequential, Single Ended

Sequential, Differential

Parallel, Single Ended

Parallel, Differential

Channel Select Switches Single Ended Differential Switches

The two 1-of-4 select muxes can be set for the appropriate input line.

The lower switch selects V

REFL

for the

V- input of the A/D. The upper switch is always closed so that any of the four inputs can get to the V+ A/D input.

The channel select switches are turned on in pairs, providing a dual

1-of-2 select function, such that either of the two differential channels can be routed to the A/D input.

The upper switch is open and the bottom switch selects the differential channel for the V- input of the A/D.

The two 1-of-4 select muxes can be set for the appropriate input line.

The lower switch selects V

REFL

for the

V- input of the A/D. The upper switch is always closed so that any of the four inputs can get to the V+ A/D input.

The channel select switches are turned on in pairs, providing a dual

1-of-2 select function, such that either of the two differential channels can be routed to the A/D input.

The upper and lower switches are open and the middle switch is closed, providing the differential channel to the differential input of the A/D.



Preliminary

28-5


MUX Configuration for Single-Ended vs MUX Configuration for Differential

AN0

AN1

AN2

AN3

V

REFL

Channel

Select

V+

V–

Single-Ended

Channel Select

Single-Ended vs

Differential

To

Converter A

Interface

Function

AN0

AN1

AN2

AN3

V

REFL

Channel

Select

V+

V–

Differential

Channel Select

Single-Ended vs

Differential

To

Converter A

Interface

Function

AN4

AN5

AN6

AN7

V

REFL

Channel

Select

Channel

Select

V+

V–

To

Converter B

Interface

Function

AN4

AN5

AN6

AN7

V

REFL

Single-Ended

Channel Select

Single-Ended vs

Differential

Figure 28-4. Input Select Mux

V+

V–

Differential

Channel Select

Single-Ended vs

Differential

To

Converter B

Interface

Function

28.4.2

ADC Sample Conversion

The ADC consists of a cyclic, algorithmic architecture using two recursive sub-ranging sections (RSD#1

and RSD#2), shown in Figure 28-5 .

Each sub-ranging section resolves a single bit for each conversion clock, resulting in an overall conversion rate of two bits per clock cycle. Each sub-ranging section is designed to run at a maximum clock speed of 5.0 MHz. Thus a complete 12-bit conversion takes 6 ADC clocks (1.2ms), not including sample or post processing time.

28-6



Preliminary


ADCA

Cyclic ADC Core

AN0

AN1

AN2

AN3

V

REFL

V+

V–

V+

V–

Channel Select

Single-Ended vs

Differential

Interface

Function

MUX

RSD#1

θ

1

RSD#2

θ

2

ADCB

Cyclic ADC Core

AN4

AN5

AN6

AN7

V

REFL

V+

V–

V+

V–

Interface

Function

MUX

RSD#1

θ

1

RSD#2

θ

2

Channel Select

Single-Ended vs

Differential

Figure 28-5. Cyclic ADC — Top Level Block Diagram

The input mode for a given sample is determined by the CHNCFG field of the CTRL1 register. The ADC has two input modes:

1. Single-ended mode (CHNCFG bit=0)—In single-ended mode, input mux of the ADC selects one of the analog inputs and directs it to the plus terminal of the A/D core. The minus terminal of the

A/D core is connected to the V

REFL

reference during this mode. The ADC measures the voltage of the selected analog input and compares it against the (V

REFH

- V

REFL

) reference voltage range.

2. Differential mode (CHNCFG bit = 1)—In differential mode, the ADC measures the voltage difference between two analog inputs and compares that against the (V

REFH

- V

REFL

) voltage range. The input is selected as an input pair: AN0/1, AN2/3, AN4/5, or AN6/7. In this mode, the plus terminal of the A/D core is connected to the even analog input, while the minus terminal is connected to the odd analog input.

A mix and match combination of differential and single-ended configurations may exist.

Examples:

• AN0 and AN1 differential, AN2 and AN3 single-ended

• AN4 and AN5 differential, AN6 and AN7 single-ended

28.4.2.1

Single-Ended Samples

The ADC module performs a ratio metric conversion. For single ended measurements, the digital result is proportional to the ratio of the analog input to the reference voltage in the following formula:



Preliminary

28-7


SingleEndedValue

= round (

V

V IN –

REFH

V

–

REFLO

V REFLO

× 4095 )

× 8

VIN = Applied voltage at the input pin

VREFH and VREFL = Voltage at the external reference pins on the device (typically VREFH = VSSA and

VREFL = VDDA)

Note: The 12-bit result is rounded to the nearest LSB.

Note: The ADC is a 12-bit function with 4096 possible states. However, the 12 bits have been left shifted three bits on the 16-bit data bus so its magnitude, as read from the data bus, is now

32760.

28.4.2.2

Differential Samples

For differential measurements, the digital result is proportional to the ratio of the difference in the inputs to the difference in the reference voltages (V

REFH for differential inputs.

and V

REFL

). Figure 28-6

shows typical configurations

When converting differential measurements, the following formula is useful:

DifferentialValue

= round (

V

V IN 1 V

REFH – V

IN 2

REFLO

× 4095 )

× 8

V

IN

= Applied voltage at the input pin

V

REFH and V

REFL

= Voltage at the external reference pins on the device (typically V

REFH

= V

SSA

and V

REFL

=

V

DDA

)

Note: The 12-bit result is rounded to the nearest LSB.

Note: The ADC is a 12-bit function with 4096 possible states. However, the 12 bits have been left shifted three bits on the 16-bit data bus so its magnitude, as read from the data bus, is now

32760.

28-8



Preliminary


V

REFH

Potential

AN+

+

–

AN–

Differential buffer will center about mid-point

AN+

NOTE: Normally, V

REFL set to V

SSA

= 0V

is

AN–

V

REF

/2

Center tap held at (V

REFH

+ V

REFL

) /2

Figure 28-6. Typical Connections for Differential Measurements

28.4.3

ADC Data Processing

As shown in Figure 28-7 , the raw result of the ADC conversion process is sent to an adder for offset

correction. The adder subtracts the ADOFS n register value from each sample and the result is stored in the corresponding result register (RSLT n ). Concurrent to this the raw ADC value is checked for limit violations, and the RSLT n values are checked for zero-crossing. Appropriate interrupts are asserted, if enabled.

The sign of the result is calculated from the ADC unsigned result minus the respective offset register. If the offset register is programmed with a value of zero, the result register value is unsigned and equals the cyclic converter unsigned result. The range of the result (RSLT) register is $0000–$7FF8, assuming the offset (ADOFS n ) register is set to zero.

The processor can write to the result registers whenever the ADC is in stop mode or powered down. The data from this write operation is treated as if it came from the ADC analog core; so the limit checking, zero crossing, and the offset registers function as if in normal mode. For example, if the ADC is stopped and the processor writes to RSLT5 register, the data written to the RSLT5 register is muxed to the ADC digital logic inputs, processed, and stored into RSLT5, as if the analog core had provided the data. This test data must be left justified by 3 bits (as shown in the RSLT register definition) and does not include the sign bit.

The sign bit (SEXT) is calculated during subtraction of the corresponding ADOFS n offset value.



Preliminary

28-9


V+

V–

ADCA

Test Data

(From CPU)

12

12

HILIM[0:3]

LOLIM[0:3]

Zero Crossing Logic

<

12

+

–

+

13

OFFST[0:3]

>

RSLT[0:3]

End of

Scan A

Interrupt

ADC0

ADC1

ADC2


Interrupt

V+

V–

ADCB

12

12

HILIM[4:7]

>

LOLIM[4:7]

Zero Crossing Logic

<

12

+

–

+

13

OFFST[4:7]

RSLT[4:7]

Test Data

(From CPU)

Figure 28-7. Result Register Data Manipulation

End of

Scan B

Interrupt

28.4.4

Sequential vs. Parallel Sampling

All scan modes make use of the 8 SAMPLE slots in the ADLST1 and ADLST2 registers. These slots are used to define which single-ended input or differential input pair is measured at each step in a scan sequence. The SDIS register is used to disable unneeded slots.

Differential measurements are made on input pairs AN0/1, AN2/3, AN4/5, and AN6/7 using the CHNCFG field of the CTRL1 register. A single ended measurement will be made if a SAMPLE slot refers to an input not configured as a member of a differential pair by CHNCFG. A differential measurement will be made if a SAMPLE slot refers to either member of a differential pair. Refer to the CHNCFG field description in the CTRL1 register for details of differential and single ended measurement.

Scan modes are either sequential or parallel, as defined by the SMODE field of the CTRL1 register. In sequential scans, up to 8 SAMPLE slots are sampled one at a time in the order SAMPLE 0-7. Each

SAMPLE slot may refer to any of the 8 analog inputs (AN0-7), thus the same input may be referenced by

28-10



Preliminary

Analog-to-Digital Converter (ADC) more than one SAMPLE slot. Scanning is initiated when the START0 bit is written as 1 or, if the SYNC0 bit is 1, when the SYNC0 input goes high. A scan ends when the first disabled sample slot is encountered in the SDIS register. Completion of the scan triggers the EOSI0 interrupt if the interrupt is enabled by the

EOSIE0 bit. The START0 bit and SYNC0 input are ignored while a scan is in process. Scanning stops and cannot be initiated when the STOP0 bit is set.

Parallel scans differ in that converter A collects up to 4 samples (SAMPLE 0-3) in parallel to converter B collecting up to 4 samples (SAMPLE 4-7). SAMPLEs 0-3 may only reference inputs AN0-3, and

SAMPLEs 4-7 may only reference inputs AN4-7. Within these constraints, any sample may reference any pin and the same input may be referenced by more than one sample slot.

By default (when SIMULT=1), parallel scans of the converters are initiated together when the START0 bit is written as 1 or, if the SYNC0 bit is 1, when the SYNC0 input goes high. The scan in both converters terminates when either converter encounters a disabled sample slot in SDIS. Completion of a scan triggers the EOSI0 interrupt provided the EOSIE0 interrupt enable is set. Samples are always taken simultaneously in both the A and B converters. Setting the STOP0 bit stops and prevents the initiation of scanning in both converters.

Setting SIMULT=0 (non-simultaneous mode) causes parallel scanning to operate independently in the A and B converter. Each converter has its own set of START n , STOP n , SYNC n , and EOSIE n control bits,

SYNC n input, EOSI n interrupt, and CIP n status indicators ( n = 0 for converter A, n = 1 for converter B).

Though still operating in parallel, the scans in the A and B converter start and stop independently according to their own controls. They may be simultaneous, phase shifted, or asynchronous, depending on when scans are initiated on the respective converters. The A and B converter may be of different length

(still up to a maximum of four) and each converter’s scan completes when a disabled sample is encountered in that converters sample list only. STOP0 only stops the A converter, and STOP1 only stops the B converter. Looping scan modes repeat independently, with the A converter capturing SAMPLE 0-3, and B converter capturing SAMPLE 4-7. In loop modes, each converter independently restarts its scan after capturing its samples.

28.4.5

Scan Sequencing

Scan modes break down into three types based on how they repeat: once, triggered, or loop. Be certain to

read Section 28.4.4 “Sequential vs. Parallel Sampling

” to understand the operation of sequential and parallel scan modes before proceeding.

During a once mode scan, a single sequential or parallel scan is executed. Once scan modes differ from triggered scan modes in that they must be re-armed after each use. While all scan modes ignore sync pulses occurring while a scan is in process, once scan modes will continue to ignore sync pulses even after the scan completes until re-armed. However, re-arming can occur any time, including during the scan, by writing to a CTRL n register. If operating in a sequential mode or simultaneous parallel, write to the CTRL1 register. If operating in a non-simultaneous parallel mode, re-arm converter A by writing to the CTRL1 register and converter B by writing to the CTRL2 register.

Triggered scan modes are identical to the corresponding once scan modes, except that re-arming of sync inputs is not necessary.



Preliminary

28-11


Loop scan modes automatically restart a scan as soon as the previous scan completes. In the loop sequential mode, up to 8 samples are captured in each loop, and the next scan starts immediately after the completion of the previous scan. In loop parallel scan modes, both converters restart together if

SIMULT=1 and restart independently if SIMULT=0. All subsequent start and sync pulses will be ignored after the scan begins. Scanning can only be terminated by setting a STOP n bit. Use STOP0 in the CTRL1 register if operating in a sequential or simultaneous parallel mode. If operating in a non-simultaneous parallel mode, use STOP0 to stop converter A and STOP1 in the CTRL2 register to stop converter B.

28.4.6


The five supported power modes are described below. They are in order of highest to lowest power

utilization at the expense of increased conversion latency and/or startup delay. Please see Section 28.4.7

“ADC Clock

” for details of the various clocks referenced below.

28.4.6.1

Power Management Modes

1. Normal power mode

This mode operates when:

— At least one ADC converter is powered up (PD0 or PD1=0 in the POWER register);

— Both auto power-down and auto standby modes are disabled (APD=0, ASB=0 in

ADCPOWER);

— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register).

In this mode, the ADC uses the conversion clock as the ADC clock source both when active or idle. To minimize conversion latency, it is recommended the conversion clock be configured to 5.0 MHz. No startup delay (defined by PUDELAY in the POWER register) is imposed.

2. Auto power-down mode



— Auto power-down mode is enabled (APD=1 in the POWER register);

— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register).

Auto power-down and standby modes can be used together by setting APD=1 in the above configuration.

This hybrid mode converts at an ADC clock rate of 100 kHz using standby current mode when active, and gates off the ADC clock and powers down the converters when idle. A startup delay of PUDELAY ADC clock cycles execute at the start of all scans while the ADC engages the conversion clock and the ADC powers up, stabilizing in the standby current mode. This provides the lowest possible power configuration for ADC operation.

3. Auto standby mode



— Auto power-down is disabled (APD=0 in the POWER register);

— Auto standby is enabled (ASB=1 in the POWER register);

28-12



Preliminary


— The ADC’s clock is enabled (ADC=1 in the SIM module’s SIM_PCE register);

— Either the relaxation oscillator must be enabled for 8-MHz operation or the external oscillator clock must be running at 8 MHz in this mode.

In auto standby mode, the ADC uses the conversion clock when active and the100 kHz Standby clock when idle. The standby (low current) state automatically engages when the ADC is idle. The ADC will execute a startup delay of PUDELAY ADC clocks at the start of all scans, allowing the ADC to switch to the Conversion clock and to revert from standby to normal current mode.

It is recommended the conversion clock be configured at or near 5.0 MHz to minimize conversion latency when active. In this mode, the ADC uses the conversion clock when active and gates off the conversion clock and powers down the converters when idle. A startup delay of PUDELAY ADC clocks is executed at the start of all scans, allowing the ADC to stabilize when switching to normal current mode from a completely powered off condition. This mode uses less power than normal and more power than auto standby. It requires more startup latency than auto standby when leaving the idle state to start a scan (higher

PUDELAY value).

4. POWER-DOWN MODE


— Both ADC converters are powered down (PD0=PD1=1 in the POWER register);

— The ADC’s clock is disabled (ADC=0 in the SIM module’s SIM_PCE register).

In this configuration, the clock trees to the ADC and all of its analog components are shut down and the ADC uses no power.

28.4.6.2

Power Management Details

The ADC voltage reference and converters are powered down (PDn=1 in the POWER register) on reset.

Individual converters can be manually powered down when not in use (PD0=1 or PD1=1), and the voltage reference can be automatically powered down when no converter is in use (PD2=1) or manually powered up when no converters are powered (PD2=0). When the ADC voltage reference is powered down, output reference voltages are set to low (V

SSA

).

A delay of PUDELAY ADC clock cycles is imposed whenever PD0 or PD1 are cleared to power-up a converter and whenever the ADC goes from an idle (neither converter has a scan in process) to an active state when not operating in normal power mode. The ADC is active when at least one converter has a scan in process. A device recommends the use of two PUDELAY values: a large value for full power-up and a smaller value for going from standby current levels to full power-up. The following paragraphs provide an explanation of how to use PUDELAY when starting the ADC up or changing modes.

When starting up in normal mode, first set PUDELAY to the large power-up value. Next, clear the PD0 and or PD1 bits to power-up the required converters. Poll the status bits (PSTS n in the POWER register) until all required converters are powered up. Following polling, start scan operations. The value in

PUDELAY will provide a power-up delay before scans begin. Since normal mode does not use PUDELAY at start of scans, no further delays will be imposed.

When starting up using auto standby mode, first use the normal mode startup procedure. Before starting scan operations, set PUDELAY to the smaller value, then set ASB in the POWER register. Auto standby



Preliminary

28-13

Analog-to-Digital Converter (ADC) mode will automatically reduce current levels until active and then impose a PUDELAY wait to allow current levels to rise from standby to normal levels.

When starting up using auto power-down mode, first use the normal mode startup procedure. Before starting scan operations, set PUDELAY to the large power-up value. Next, set APD in the POWER register. Finally, clear the PD0 and or PD1 bits for the required converters. Converters remain powered off until scanning goes active, at which time the large PUDELAY executes as the ADC goes from powered down to fully powered at the start of the scan.

In auto power-down mode, when the ADC goes from idle to active, a converter is only powered up if it is required for the scan, as determined by the ADLST1, ADLST2, and SDIS registers.

It is recommended to power-off both converters (PD0=PD1=1 in the POWER register) when re-configuring clocking or power controls to avoid generating bad samples and ensure proper delays are applied when powering up or starting scans.

Attempts to start a scan during the PUDELAY time-out will be ignored until the appropriate PSTS n bits are cleared in the POWER register.

Any attempt to use a converter when powered down or with the voltage reference disabled results in invalid results. It is possible to read ADC result registers after converter power down to see results calculated before power-down. However, a new scan sequence must be started with a SYNC n pulse or a write to the START n bit before new results will be available.

28.4.6.3

ADC STOP Mode of Operation

Any conversion sequence in progress can be stopped by setting the relevant STOP n bit. Any further sync pulses or writes to the START n bit are ignored until the STOP n bit is cleared. Once in this stop mode, the results registers can be modified by writes from the processor. Any write to RSLT n registers in the ADC stop mode is treated as if the analog core supplied the data, so limit checking, zero crossing, and associated interrupts can occur if enabled.

28.4.7

ADC Clock

28.4.7.1

General

The ADC has two external clock inputs used to drive two clock domains within the ADC module.

Table 28-3. ADC Clock Summary

Clock input Source Characteristics

Peripheral Clock

(=System Clock)

1/2 Core clock Maximum rate is PLL output divided by 2 if PLL enabled. When PLL disabled, max rate is oscillator clock divided by 2.

ADC 8MHz Clock Relaxation

Oscillator (8Mhz),

Crystal Oscillator

(1-16MHz), or external Oscillator

Provides 8Mhz for auto standby power saving mode.

28-14



Preliminary


28.4.7.2

Description of Clock Operation

As shown in Figure 28-8 ,

the conversion clock is the primary source for the ADC clock and is always selected as the ADC clock when conversions are in process. The DIV value in the CTRL2 register should be configured so the conversion clock frequency falls between 100 kHz and 5.0 MHz. Operating the ADC at out-of-spec clock frequencies will degrade conversion accuracy. Similarly, modifying the parameters affect clock rates or power modes while the regulators are powered up (PD0=0 or PD1=0) will also degrade conversion accuracy.

The conversion clock ADC uses for sampling is calculated using the IPBus clock and the clock divisor bits

within the CTRL2 register. Please see Section 28.5.1 “Control 1 Register (CTRL1) ” or

Section 28.5.2

“Control 2 Register (CTRL2) Under Sequential Scan Modes

” .

The ADC clock is active 100% of the time while in loop modes, or if power management is set to normal. It is also active during all ADC power-up for a period of time determined by the PUDELAY field in the power (POWER) register. After the power-up delay times out, the ADC clock continues until the completion of the ADC n scan when operating in auto standby or auto power-down modes.

Auto Standby

Enabled (ASB=1)

Auto Power-Down

Disabled (APD=0)

ADC Idle

Standby Current Mode Status

CTRL2:DIV

0

Peripheral (System) Clock

1/2 Core Frequency

Oscillator Clock

(8MHz)

(+80)

0

1

DIV

(+2 x [DIV+1])

Auto Standby Clock

(100kHz)

ADC

Conversion

Clock

0

1

ADC Bit in SIM_PCE

ADC Clock

Figure 28-8. ADC Clock Generation

The oscillator clock feeds an 80:1 divider, generating the auto standby clock. The auto standby clock is selected as the ADC clock during the auto standby power mode when both converters are idle. The auto standby power mode requires an 8 MHz oscillator clock from the relaxation oscillator, crystal oscillator, or external oscillator.

28.4.7.3

ADC Clock Resynchronization at Start of Scan

At the fastest ADC speed, each ADC clock period is 6 system clock periods long. When asserting the start of a scan, either by writing to a START n bit or by a SYNC n signal, the ADC clock is re-synchronized to align it to the system clock. This allows the commanded scan to begin as soon as possible rather than wait

up to 5 additional system clocks for the start of the next ADC clock period. This is shown in Figure 28-9

for both sequential and simultaneous parallel modes of operation. In these modes, both ADC operate off of the same start signal.



Preliminary

28-15


In a parallel scan mode when SIMULT=0, both ADCs operate using independent START n bits and

SYNC n signals. As shown in

Figure 28-10

, the first scan started will be re-synchronized to the system clock, but the second scan may wait up to 5 additional system clocks before starting. Also, note that which converter is synchronized to the system clock depends on which convert first starts to use the ADC. The case shown has ADCA synchronized, but one could easily imagine the case where the ADCA start comes after instead of before the ADCB start. In this case, ADCAs start would be delayed up to 5 additional system clock periods instead of ADCBs.

If there is a known timing relationship between ADCA and ADCB when operating in a non-simultaneous parallel mode, then the application can control which ADC starts first and gets the re-synchronized clock.

The application can also control the delay to starting the second ADC scan so that its start signal aligns with the ADC clock, and the start of the second ADC is not delayed.

START0

Asserted

ADC Conversion Clock Resynchronized

ADC Scans Start

System Clock

Old ADC Clock

ADC Clock After

Resynchronization

ADCA Scan

ADCB Scan

Figure 28-9. ADC Clock Resynchronization for

Sequential and Simultaneous Parallel Modes

28-16



Preliminary


ADC Conversion Clock Resynchronized

ADCA Scan Start

START1 Asserted

ADCB Scan Should Start Here

ADCB Scan Start

System Clock

START0

Asserted

Old ADC Clock

Wait for next rising edge of ADC

Conversion Clock

ADC Clock After

Resynchronization

ADCA Scan

ADCB Scan

Delay in start because ADC Clock cannot be resynchronized: 5 System Clocks

Figure 28-10. ADC Clock Resynchronization for

Non-Simultaneous Parallel Modes

28.4.8

Voltage Reference Pins V

REFH

& V

REFL

The voltage difference between V

REFH

and V

REFL

provides the reference voltage that all analog inputs are measured against. The reference voltage should be provided from a low noise filtered source capable of providing up to 1mA of reference current.

1.0mH

0.1µF

External

Reference

Voltage

V

REFH

V

RH

V

RL

SEL_VREFH

V

REFH

to ADC

V

REFL

to ADC

SEL_VREFL

V

REFL

Figure 28-11. ADC Voltage Reference Circuit

When tying V

REFH

to the same potential as V the amplitude of V

DDA

DDA,

relative measurements are being made with respect to

. It is imperative that special precautions be taken to assure the voltage applied to



Preliminary

28-17


V

REFH

is as noise-free as possible. Any noise residing on the V

REFH

voltage is directly transferred to the digital result.

Figure 28-11 illustrates the internal workings of the ADC voltage reference circuit. V

REFH filtered; a minimum configuration is shown in the figure.

must be noise

28.4.9

Supply Pins V

DDA

and V

SSA

Dedicated power supply pins are provided for the purposes of reducing noise coupling and to improve accuracy. The power provided to these pins is suggested to come from a low noise filtered source.

Uncoupling capacitors ought to be connected between V

DDA

and V

SSA

.

28.5

Register Definitions

A register address is the sum of a base address and an address offset. The base address is defined at the device level, and the address offset is defined at the module level.

Table 28-5

lists the ADC registers in ascending address order, including their acronyms and address offset of each register. ADC uses ADC n _BASE plus the given offset depending on the ADC being used. The

ADC peripheral has 43 registers.

Table 28-4. ADC Memory Map

IPSBAR Offset

1

Register

Width

(bits)



0x0019_0000 Control Register 1 (CTRL1)

0x0019_0002 Control Register 2 (CTRL2)

0x0019_0004 Zero Crossing Control Register (ADZCC)

0x0019_0006 Channel List Register 1 (ADLST1)

0x0019_0008 Channel List Register 2 (ADLST2)

0x0019_000A Sample Disable Register (ADSDIS)

0x0019_000C Status Register (ADSTAT)

0x0019_000E Limit Status Register (ADLSTAT)

16

16

16

16

16

16

16

16

0x0019_0010 Zero Crossing Status Register (ADZCSTAT)

0x0019_0012–20 Result Registers 0-7 (ADRSLT0-7)

0x0019_0022–30 Low Limit Registers 0-7 ()

0x0019_0032–40 High Limit Registers 0-7 (ADLLMT0-7)

16

16

16

16

0x0019_0042–50 Offset Registers 0-7 (ADOFS0-7)

0x0019_0052 Power Control Register (POWER)

16

16

R/W

R/W

0x0019_0054 Voltage Reference Register (CAL) 16 R/W

1


R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0x5005

0x0002

0x0000

0x3210

0x7654

0x0000

0x0000

0x0000

0x0000

0x0000

0x0000

0x0000

0x0000

0x00D7

0x0000

28.5.2/28-25

28.5.2/28-25

28.5.4/28-29

28.5.5/28-29

28.5.5/28-29

28.5.6/28-31

28.5.7/28-32

28.5.8/28-35

28.5.9/28-35

28.5.10/28-36

28.5.11/28-37

28.5.11/28-37

28.5.12/28-38

28.5.13/28-39

28.5.14/28-42

28-18



Preliminary


IPSBAR Offset

0x0019_0000

0x0019_0002

Acronym

CTRL1

CTRL2

Table 28-5. ADC Register Summary

Register Name

Control Register 1

Control Register 2

Access Type

Read/Write

Read/Write

ADZCC

ADLST1

ADLST2

ADSDIS

ADSTAT

ADLSTAT

ADZCSTAT

ADRSLT0-7

ADLLMT0-7

ADHLMT0-7

ADOFS0-7

POWER

CAL

Zero Crossing Control Register

Channel List Register 1

Channel List Register 2

Sample Disable Register

Status Register

Limit Status Register

Zero Crossing Status Register

Result Registers 0-7

Low Limit Registers 0-7

High Limit Registers 0-7

Offset Registers 0-7

Power Control Register

Voltage Reference Register

Location

Section 28.5.1

Section 28.5.2

Section 28.5.3

Section 28.5.4

Section 28.5.5

0x0019_0004

0x0019_0006

0x0019_0008

0x0019_000A

0x0019_000C

0x0019_000E

0x0019_0010

0x0019_0012–20

0x0019_0022–30

0x0019_0032–40

0x0019_0042–50

0x0019_0052

0x0019_0054

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Read/Write

Section 28.5.6

Section 28.5.7

Section 28.5.8

Section 28.5.9

Section 28.5.10

Section 28.5.11

Section 28.5.12

Section 28.5.13

Section 28.5.14

Bits of each of the 43 registers are summarized in

Figure 28-12 .

Details of each follow.



Preliminary

28-19


Add. Offset

$0019_0000

$0019_0002

$0019_0004

$0019_0006

$0019_0008

$0019_000A

Register

Acronym

CTRL 1

CTRL 2

Simultaneous Mode

R

W

R

CTRL 2

Parallel Mode

W

ADZCC

ADLST1

ADLST2

ADSDIS

W

R

R

W

R

W

R

W

R

W

15

0

0

0

0

0

0

14 13 12 11 10 9 8

0

STOP0

START

0

SYNC

0

EOSIE

0

ZCIE

LLMTI

E

HLMTI

E

0 0 0 0 0 0 0

0

STOP1

START

1

SYNC

1

EOSIE

1

ZCE7

0

ZCE6

SAMPLE3

SAMPLE7

0 0

0

0

0

ZCE5

0

0

0

SAMPLE2

SAMPLE6

0

ZCE4

0

0

7

0

0

0

0

ZCE3

6 5

CHNCFG

0

0

0

SIMULT

ZCE2

SAMPLE1

SAMPLE5

4 3

0

0

0

ZCE1

2

DIV

DIV

1

SMODE

ZCE0

SAMPLE0

SAMPLE4

0

DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0

Figure 28-12. ADC Register Map Summary

28-20



Preliminary


R CIP0 CIP1 0

EOSI

1

EOSI

0

ZCI LLMTI HLMT RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0

$0019_0006 ADSTAT

$0019_0007

$0019_0008

$0019_0009-10

ADLSTAT

ADZCSTAT

ADRSLT n

$0019_0011-$18 ADLLMT n

W

R

W

R

W

HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 HLS0 LLS7 LLS6 LLS5 LLS4 LLS3 LLS2 LLS1 LLS0

R 0 0 0 0 0 0 0 0

ZCS7 ZCS6 ZCS5 ZCS4 ZCS3 ZCS2 ZCS1 ZCS0

W

R

SEXT

W

0

RSLT

TEST_DATA

LLMT

0

0

0

0

0

0

$0019_0019-$20 ADHLMT n

R

W

0

HLMT

0 0 0

$0019_0021-$28 ADOFS n

R

W

0

OFFSET

0 0 0

$0019_0029 POWER

R

ASB

0 0

PSTS

2

PSTS

1

PSTS

0

PUDELAY APD PD2 PD1 PD0

W

0 0 0 0 0 0 0 0 0 0 0 0 0 0

$0019_002A CAL

R

W

SEL_V

REFH

SEL_V

REFL

R

W

0 Read as 0

Reserved

Figure 28-12. ADC Register Map Summary (continued)

28.5.1

Control 1 Register (CTRL1)

Bits 14, 13, 12, and 11 in CTRL1 control all types of scans except parallel scans in the B converter when

SIMULT=0 in the CTRL2 register. SIMULT=0 bits 14, 13, 12, and 11 in CTRL are used to control converter B scans in parallel scan modes, while the equivalent bits in CTRL1 are used for converter A.


Offset:

0x19_0000 (CTRL1)

15

R 0

W

Reset 0

14 13 12 11

STOP0

START0

SYNC0

EOSI

E0

1 0 1 0

10

ZCIE

9 8

LLMT

IE

HLMT

IE

0 0 0

7

0

6

0

Figure 28-13. Control 1 (CTRL1) Register

5

CHNCFG

0

4

0

3

0

2 1

SMODE

0

1 0 1

28.5.1.1

Reserved—Bit 15

This bit is reserved or not implemented. It is read as 0 and cannot be modified by writing.



Preliminary

28-21


28.5.1.2

STOP 0 (STOP0)—Bit 14

When STOP0 is asserted, the current scan is stopped and no further scans can start. Any further SYNC0 input pulses (see SYNC0 bit 12) or writes to the START0 bit are ignored until the STOP0 bit is cleared.

After the ADC is in stop mode, the result registers can be modified by the processor. Any changes to the result registers in stop mode are treated as if the analog core supplied the data. Therefore, limit checking, zero crossing, and associated interrupts can occur if enabled.

NOTE

This is not the same as the device’s STOP mode.

• 0 = Normal operation

• 1 = Stop mode

28.5.1.3

Start Conversion (START0)—Bit 13

A scan is started by writing 1 to the START0 bit. This is a write-only bit. Writing 1 to the START0 bit again will be ignored until the end of the current scan.

• 0 = No action

• 1 = Start command is issued

The ADC must be in a stable power configuration prior to writing the START bit. Refer to the functional description of power modes for further details.

28.5.1.4

Synchronization 0 Enable (SYNC0)—Bit 12

A conversion may be initiated by asserting a positive edge on the SYNC0 input. Any subsequent SYNC0 input pulses while the scan remains in process are ignored.

• 0 = Scan is initiated by a write to START0 bit only

• 1 = Use a SYNC0 input pulse or START0 bit to initiate a scan

The ADC must be in a stable power mode prior to SYNC0 input assertion. Refer to the functional description of power modes for further details.

In “ OnCE Sequential” and “ OnCE Parallel” scan modes, only the first SYNC0 input pulse is honored.

Subsequent SYNC0 input pulses are ignored until SYNC0 input is re-armed by writing to the CTRL1 register, usually by simply rewriting 1 to SYNC0. This is achieved at any time, even during the execution of the scan.

28.5.1.5

End Of Scan Interrupt Enable 0 (EOSIE0)—Bit 11

This bit enables an EOSI0 interrupt to be generated upon completion of the scan. For looping scan modes, the interrupt will trigger after the completion of each iteration of the loop.

• 0 = Interrupt disabled

• 1 = Interrupt enabled

28-22



Preliminary


28.5.1.6

Zero Crossing Interrupt Enable (ZCIE)—Bit 10

This bit enables the zero crossing interrupt if the current result value has a sign change from the previous result as configured by the ADZCC register.



28.5.1.7

Low Limit Interrupt Enable (LLMTIE)—Bit 9

This bit enables the low limit exceeded interrupt when the current result value is less than the low limit register value. The raw result value is compared to the LOLIM register, bits LLMT[11:0], before the offset register value is subtracted.



28.5.1.8

High Limit Interrupt Enable (HLMTIE)—Bit 8

This bit enables the high limit exceeded interrupt if the current result value is greater than the high limit register value. The raw result value is compared to the high limit (HILIM) register, bits HLMT[11:0], before the offset register value is subtracted.



28.5.1.9

Channel Configure (CHNCFG)—Bits 7 – 4

The inputs can be configured for either single-ended or differential conversions.

Table 28-6. CHNCFG Bit Settings

Bit Settings xxx1 xxx0 xx1x xx0x x1xx x0xx

1xxx

0xxx

Inputs

AN0 – AN1

AN2 – AN3

AN4 – AN5

AN6 – AN7

Description

Configured as differential pair (AN0 is + and AN1 is – )

Both configured as single ended inputs







Differential measurements return the max value 32760 (= 4095 × 8) when the plus ( + ) input is V the minus ( −) input is V

REFL

, return 0 when the plus ( + ) input is at V

REFL

V

REFL measurements return the max value 32760 when the input is at V

REFH

REFH

and

and the minus ( −) input is at

, and scale linearly between based on the voltage difference between the two signals. Single-ended

, return 0 when the input is at V and scale linearly between based on the amount by which the input exceeds V

REFL

.

REFL

,



Preliminary

28-23


28.5.1.10 Scan Mode Control (SMODE)—Bits 2-0

SMODE controls the scan mode of the ADC module. All scan modes make use of the 8 sample slots defined by the ADLST1 and ADLST2 registers. A scan is the process of stepping through these sample slots, converting the analog input indicated by that slot, and storing the result. Slots that are not required may be disabled by writing 1 to the appropriate bits of the SDIS register.

Input pairs AN0-1, AN2-3, AN4-5, and AN6-7 may be configured as differential pairs using the CHNCFG field. When a slot in CLST n refers to either member of a differential pair, a differential measurement on that pair will be made; otherwise, a single-ended measurement will be taken on that input. The details of differential and single-ended measurement are described in the description of the CHNCFG field.

SMODE determines whether the slots are used to perform a sequential scan of up to 8 samples or 2 parallel scans up to 4 samples. SMODE controls how these scans are initiated and terminated. It also controls whether the scans are performed once or repetitively. For more details, please see

Section Figure 28-3.

“Parallel Mode Operation of the ADC

” .

Parallel scans may be simultaneous (SIMULT=1) or non-simultaneous (SIMULT=0). During simultaneous parallel scans, A and B converters scan synchronously using one set of shared controls

(CTRL1 register). During non-simultaneous scans, the A and B converters operate asynchronously with each converter using its own independent set of controls (CTRL1 for A and CTRL2 for B). Refer to the

SIMULT bit description for further details.

NOTE

The SIMULT bit only applies to parallel operating modes and is ignored during sequential operating modes.

• 000 = Once sequential

Upon START or an enabled sync signal, samples are taken one at a time starting with SAMPLE0 until a first disabled sample is encountered. If no disabled sample is encountered in SDIS register, conversion concludes after SAMPLE7. If the scan is initiated by a sync signal, only one scan will be completed until the converter is rearmed by writing to the CTRL1 register.

• 001 = Once parallel

Upon START or an armed and enabled sync signal, converter A will capture samples 0-3 and converter B will capture samples 4-7. By default (SIMULT=1), samples are taken simultaneously

(synchronously), and scanning stops when either converter encounters a disabled sample or both converters complete all 4 samples. When SIMULT=0, samples are taken asynchronously, and scanning stops when each converter encounters a disabled sample in its part of the SDIS register or completes all 4 samples. If the scan is initiated by a sync signal, only one scan will be completed till the converter is re-armed by writing to the CTRL1 register. (When SIMULT=0, the B converter must be re-armed separately by writing to the CTRL2 register.)

• 010 = Loop sequential

Upon an initial start or enabled sync pulse, up to 8 samples are taken one at a time until a disabled sample is encountered. The process repeats until the STOP0 bit is set. While a loop mode is running, any additional start commands or sync pulses are ignored. If auto standby

(POWER:ASB=1) or auto power-down (POWER:APD=1) is the selected power mode control, the power-up delay defined by PUDELAY will be applied only on the first conversion.

28-24



Preliminary


• 011= Loop parallel

Upon an initial start or enabled sync pulse, converter A will capture Samples 0-3, and converter B will capture Samples 4-7. Each time a converter completes its current scan, it immediately restarts its scan sequence. This continues until a STOP n bit is asserted. While a loop is running, any additional start commands or sync pulses are ignored. By default (SIMULT=1), samples are taken simultaneously (synchronously), and scanning stops when either converter encounters a disabled sample or both converters complete all 4 samples. When SIMULT=0, samples are taken asynchronously, and scanning stops when each converter encounters a disabled sample in its part of the SDIS register or completes all 4 samples. If auto standby or auto power-down is the selected power mode control, the power-up delay defined by PUDELAY will be applied only on the first conversion.

• 100 = Triggered sequential

Upon START or an enabled sync signal, samples are taken one at a time starting with SAMPLE0 until a first disabled sample is encountered. If no disabled sample is encountered, conversion concludes after SAMPLE7. If external sync is enabled, new scans will be started for each sync pulse that is non-overlapping with a current scan in progress.

• 101 = Triggered parallel (default)

Upon START or an enabled sync signal, converter A will convert Samples 0-3, and converter B will convert Samples 4-7 in parallel. By default (SIMULT=1), samples are taken simultaneously

(synchronously), and scanning stops when either converter encounters a disabled sample or both converters complete all 4 samples. When SIMULT=0, samples are taken asynchronously, and scanning stops when each converter encounters a disabled sample in its part of the SDIS register or completes all 4 samples. If external sync is enabled (SYNC0=1), new scans will be started for each sync pulse as long as the ADC has completed the previous scan (STAT:CIP n =0).

• 110 = Reserved use

• 111 = Reserved use

28.5.2

Control 2 Register (CTRL2) Under Sequential Scan Modes

Operating mode dependencies occur when the ADC’s scan mode (SMODE in the CTRL1 register) is set to once sequential, loop sequential, or triggered sequential. Bits 15

–

5 are reserved. Only the DIV field is available.

IPSBAR

Offset:

0x19_0001 (CTRL2)

15

R 0

W

Reset 0

14

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4 3

0 0 0 0 0 0 0 0 0 0 0 0

Figure 28-14. Control 2 (CTRL2) Register Under Sequential Scan Modes

Access: read/write

2

DIV

0

1

1

0

0

28.5.2.1

Reserved—Bits 15–5

This bit field is reserved and should not be modified by writing.



Preliminary

28-25


28.5.2.2

Clock Divisor Select (DIV)—Bits 4 – 0

The divider circuit generates the ADC clock by dividing the system clock by 2 × (DIV[4:0]+1). A DIV value must be chosen so the ADC clock does not exceed 5.0 MHz. The following table shows ADC clock frequency based on the value of DIV for several configurations.

Table 28-7. ADC Clock Frequency for Various Conversion Clock Sources

DIV

0_0000

0_0001

0_0010

0_0011

0_0100

—

—

1_1111

Divisor

10

—

—

64

6

8

2

4

ROSC Standby

400 Khz

200 kHz Sys Clock

100K

100K

100K

100K

100K

—

—

100K

ROSC Normal

8 Mhz

4 MHz Sys Clock

2.00M

1.00M

500K

250K

125K

—

—

62.5K

PLL

64 Mhz

32 MHz Sys Clock

16.0M

8.00M

5.33M

4.00M

3.20M

—

—

500K

External CLK

CLK/2 Sys Clock

CLK/4

CLK/8

CLK/12

CLK/16

CLK/20

—

—

CLK/128

28.5.3

Control 2 Register (CTRL2) Under Parallel Scan Modes

Operating mode dependencies of this register occur when the ADC’s scan mode (SMODE in the CTRL1 register) is set to once parallel, loop parallel, or triggered parallel. Bits 14

–

11 and 5 are no longer reserved and are used to control the operation of converter B.

By default, SIMULT=1 and converter B operates together with converter A. In this case bits, 14, 13, 12, and 11 in CTRL2 do not affect converter B operation. When SIMULT=0 and SMODE is a parallel scan, bits 14

–

11 in CTRL2 along with the SYNC1 input are used to control the converter B scan. In this case,

EOSIE1 enables the EOSI1 interrupt, signaling the end of a B converter scan. Also, the CIP1 bit in the

STAT register is used to indicate a converter B scan is active.


Offset:

0x19_0001 (CTRL2)

15

R 0

W

Reset 0

14 13 12 11

STOP1

1

START1

SYNC1 EOSIE1

0 1 0

10

0

0

9

0

0

8

0

0

7

0

0

6

0

0

5

SIMU

LT

0

4

0

3

0

Figure 28-15. Control 2 (CTRL2) Register Under Parallel Scan Modes(

2

DIV

0

1

1

0

0

28.5.3.1



28-26



Preliminary


28.5.3.2

Stop (STOP1)—Bit 14

During parallel scan modes when SIMULT=0, setting STOP1 stops parallel scans in the B converter and prevents new ones from starting. Any further SYNC1 input pulses (please see SYNC1 bit) or writes to the

START1 bit are ignored until the STOP1 bit is cleared. After the ADC is in Stop mode, the B converter results registers can be modified by the processor. Any changes to the Result registers in Stop mode are treated as if the analog core supplied the data. Therefore, limit checking, zero crossing, and associated interrupts can occur if enabled. This is not the same as the device’s STOP mode .

• 0 = Normal operation

• 1 = Stop command issued

28.5.3.3

Start Conversion (START1)—Bit 13

During parallel scan modes when SIMULT=0, a B converter parallel scan is started by writing 1 to the

START1 bit. This is a write-only bit. Writing 1 to the START1 bit again will be ignored until the end of the current scan.

• 0 = No action

• 1 = Start a B converter parallel scan

The ADC must be in a stable power configuration prior to writing the start bit. Refer to the functional description of power modes for further details.

28.5.3.4

SYNC1 Enable (SYNC1)—Bit 12

During parallel scan modes when SIMULT=0, setting SYNC1 to 1 permits a B converter parallel scan to be started by asserting the SYNC1 input for at least one ADC clock cycle. Any additional SYNC1 input pulses will be ignored until the end of the scan.

• 0 = B converter parallel scan is initiated by a write to START1 bit only

• 1 = Use a SYNC1 input pulse or START1 bit to initiate a B converter parallel scan

The ADC must be in a stable power mode prior to SYNC1 input assertion. Please refer to the functional description of power modes for further details.

In “ Once Sequential” and “ Once Parallel” scan modes, only a first SYNC1 input pulse is honored.

Subsequent SYNC1 input pulses are ignored until the SYNC1 input is re-armed by writing to the CTRL2

Register, usually by simply rewriting 1 to SYNC1. This can be done at any time, including while the scan remains in process.

28.5.3.5

Reserved—Bits 10–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

28.5.3.6

End Of Scan Interrupt Enable 1 (EOSIE1)—Bit 11

During parallel scan modes when SIMULT=0, this bit enables an EOSI1 interrupt to be generated upon completion of a B converter parallel scan. For looping scan mode, the interrupt will trigger upon the completion of each iteration of the loop .



Preliminary

28-27




28.5.3.7

Simultaneous Mode (SIMULT)—Bit 5

This bit only affects parallel scan modes.

When SIMULT=1 (default value) parallel scans operate in simultaneous mode. The scans in the A and B converter operate simultaneously and always result in pairs of simultaneous conversions in the A and B converter. START0, STOP0, SYNC0, and EOSIE0 control bits and the SYNC0 input are used to start and stop scans in both converters simultaneously. A scan ends in both converters when either converter encounters a disabled sample slot. When the parallel scan completes, the EOSI0 triggers if EOSIE0 is set.

The CIP0 status bit indicates that a parallel scan is in process.

When SIMULT=0, parallel scans in the A and B converters operate independently. The B converter has its own independent set of the above controls (START1, STOP1, SYNC1, EOSIE1, SYNC1) designed to control its operation and report its status. Each converter

’ s scan continues until its sample list is exhausted

(four samples) or a disabled sample is encountered. For looping parallel scan mode, each converter starts its next iteration as soon as the previous iteration in that converter is complete and continues until the

STOP bit for that converter is asserted.

• 0 = Parallel scans done independently

• 1 = Parallel scans done simultaneously (default)

28.5.3.8

Clock Divisor Select (DIV)—Bits 4 – 0

The divider circuit generates the ADC clock by dividing the system clock by 2 × (DIV[4:0]+1). A DIV

value must be chosen so the ADC clock does not exceed 5.0Mhz. Table 28-8 shows ADC clock frequency

based on the value of DIV for various configurations.

Table 28-8. ADC Clock Frequency for Various Conversion Clock Sources

DIV

0_0000

0_0001

0_0010

0_0011

0_0100

—

—

1_1111

Divisor

10

—

—

64

6

8

2

4

ROSC Standby

400Khz

200kHz Sys Clock

100K

100K

100K

100K

100K

—

—

100K

ROSC Normal

8Mhz

4MHz Sys Clock

2.00M

1.00M

500K

250K

125K

—

—

62.5K

PLL

64 Mhz

32MHz Sys Clock

16.0M

8.00M

5.33M

4.00M

3.20M

—

—

500K

External CLK

CLK/2 Sys Clock

CLK/4

CLK/8

CLK/12

CLK/16

CLK/20

—

—

CLK/128

28-28



Preliminary


28.5.4

Zero Crossing Control Register (ADZCC)

The ADC zero crossing control (ADZCC) register provides the ability to monitor the selected channels and determine the direction of zero crossing triggering the optional interrupt. Zero crossing logic monitors only the sign change between current and previous sample. The ZCE0 bit monitors the sample stored in

ADRSLT0, ZCE1 bit monitors ADRSLT1, and ZCE7 bit monitors ADRSLT7. When the zero crossing is disabled for a selected result register, sign changes are not monitored or updated in the ADZCSTAT register.


Offset:

0x19_0002 (ADZCC)

13 15 14

R

W

Reset 0

ZCE7

0

ZCE6

12 11

ZCE5

10 9

ZCE4

8 7

ZCE3

6 5

ZCE2

4

0 0 0 0 0 0 0 0 0 0

Figure 28-16. Zero Crossing Control (ADZCC) Register

3

ZCE1

2

0 0

1

ZCE0

0

0 0

28.5.4.1

Zero Crossing Enable n ( ZCE n )—Bits 15–0

For each channel, n , setting the ZCE n field allows detection of the indicated zero crossing condition, provided the corresponding offset register (ADOFS n ) has a value offset , 0 < offset < 0x7FF8.

• 00 = Zero crossing disabled

• 01 = Zero crossing enabled for positive to negative sign change

• 10 = Zero crossing enabled for negative to positive sign change

• 11 = Zero crossing enabled for any sign change

28.5.5

Channel List 1 and 2 Registers (ADLST1 and ADLST2)

The channel list register contains an ordered list of the analog input channels to be converted when the next scan is initiated. If all samples are enabled in the SDIS register, a sequential scan of inputs proceeds in order of SAMPLE0 through SAMPLE7. If one of the parallel sampling modes is selected instead, the converter A sampling order is SAMPLE0-3, and the converter B sampling order is SAMPLE4-7.


Offset:

0x19_0003 (ADLST1)

14 13 15

R

W

Reset 0 0

SAMPLE3

1

12 11 10 9

SAMPLE2

8 7 6 5

SAMPLE1

4

1 0 0 1 0 0 0 0

Figure 28-17. Channel List 1 (ADLST1) Register

1

3

0

2 1

SAMPLE0

0

0 0 0



Preliminary

28-29


IPSBAR

Offset:

0x19_0004 (ADLST2)

14 13 15

R

W

Reset 0 1

SAMPLE7

1

12 11 10 9

SAMPLE6

8 7 6 5

SAMPLE5

4

1 0 1 1 0 0 1 0

Figure 28-18. Channel List 2 (ADLST2) Register

1

3

0

Access: read/write

2 1

SAMPLE4

0

1 0 0

28.5.5.1

Reserved—Bits 15, 11, 7 and 3

These bits are reserved or are not implemented. They are read as 0 and cannot be modified by writing.

28.5.5.2

SAMPLE n (SAMPLE4)—Bits 2, 1, and 0

The value of the SAMPLE n field is used to select the input channel to be sampled.

Table 28-9. ADC Input Conversion for Sample Bits

SAMPLE n [2:0]

ADC Input Pins Selected

Sequential Mode n =0,1,2,...,7

000

001

010

011

100

101

110

111 n =0,1,2,3

(Conv. A)

000

001

010

011

Parallel Mode n =4,5,6,7

(Conv. B)

100

101

110

111

Single Ended

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Differential

AN0+, AN1 –

AN2+, AN3 –

AN4+, AN5 –

AN6+, AN7 –

In sequential modes, the sample slots are converted in order from SAMPLE0 to SAMPLE7. Analog input pins can be sampled in any order, including sampling the same input pin more than once.

In parallel modes, converter A processes sample slots SAMPLE0 through SAMPLE3, while converter B processes sample slots SAMPLE4 through SAMPLE7. Since converter A only has access to analog inputs

AN0 through AN3, sample slots SAMPLE0-3 should only contain binary values between 000 and 011.

Likewise, since converter B only has access to analog inputs AN4 through AN7, sample slots SAMPLE4-7 should only contain binary values between 100 and 111. No damage will occur if this constraint is violated but results are undefined.

28-30



Preliminary


When inputs are configured as differential pairs, a reference to either analog input in a differential pair by a sample slot implies a differential measurement on the pair. The details of single ended and differential measurement are described under the CHNCFG field. Sample slots are disabled using the SDIS register.

28.5.6

Sample Disable Register (SDIS)

This register is an extension to the ADLST1and ADLST2, providing the ability to enable only the desired samples programmed in the SAMPLE0–SAMPLE7. At reset, all samples are enabled. For example, if in sequential mode and bit DS5 is set to 1, SAMPLE0 through SAMPLE4 are sampled. However, if in parallel mode and bits DS5 or DS1 are set to 1, only SAMPLE0 and SAMPLE4 are sampled.


Offset:

0x19_0005 (SDIS)

15

R 0

W

Reset 0

14

0

0

13

0

0

12

0

0

11

0

0

10

0

0

9

0

8

0

7 6 5 4 3 2 1 0

DS7 DS6 DS5 DS4 DS3 DS2 DS1 DS0

0 0

Figure 28-19.

0 0 0 0 0 0 0 0

28.5.6.1

Reserved—Bits 15 – 8




Preliminary

28-31


28.5.6.2

Disable Sample (DS n )—Bits 7 – 0

The respective SAMPLE n field can be enabled or disabled where n = 0

–

7.

• 0 = Enable SAMPLE n

• 1 = Disable SAMPLE n and all subsequent samples. Which samples are actually disabled will depend on the conversion mode, sequential/parallel, and the value of SIMULT.

28.5.7

Status Register (STAT)

This register provides the current status of the ADC module. RDY n bits are cleared by reading their corresponding result (ADRSLT n ) registers. HLMTI and LLMTI bits are cleared by writing 1 to each asserted bit in the ADC limit status (ADLSTAT) register. Likewise, the ZCI bit, bit-10, is cleared by writing 1 to each asserted bit in the ADC zero crossing status (ADZCSTAT) register. The EOSI n bits are cleared by writing 1 to them. Please see Figure 23-25 for more information regarding the operation of interrupts.

Except for CIP0 and CIP1 all bits in the STAT Register are sticky—once set to a 1 state, they require some specific action to clear them. They are not cleared automatically on the next scan sequence.

IPSBAR

Offset:

0x19_0006 (STAT)

15 14 13

R CIP0 CIP1 0

W

Reset 0 0 0 0 0 0

Access: read/write

12 11

EOSI1 EOSI0

10 9 8 7 6 5 4 3 2 1 0

ZCI LLMTI HLMTI RDY7 RDY6 RDY5 RDY4 RDY3 RDY2 RDY1 RDY0

0 0 0 0 0 0 0 0 0

Figure 28-20. Status (STAT) Register

0

28.5.7.1

Conversion in Progress 0 (CIP0)—Bit 15

This bit indicates when a scan is in progress.

• 0 = Idle state

• 1 = A scan cycle is in progress. The ADC will ignore all sync pulses or start commands

This bit supports any sequential scan or parallel scan with SIMULT=1. When executing a parallel scan with SIMULT = 0, this bit services the scan of converter A while the CIP1 bit services the scan of converter

B.

28.5.7.2

Conversion in Progress 1 (CIP1)—Bit 14

This bit indicates when a scan is in progress.

• 0 = Idle state

• 1 = A scan cycle is in progress. The ADC will ignore all sync pulses or start commands

This refers only to a B converter scan in non-simultaneous (SIMULT=0) parallel scan modes.

28-32



Preliminary


28.5.7.3



28.5.7.4

End of Scan Interrupt 1 (EOSI1)—Bit 12

This bit indicates whether a scan of analog inputs have been completed since the last read of the STAT register or a reset. The EOSI1 bit is cleared by writing 1 to it. This bit cannot be set by software.

• 0 = A scan cycle has not been completed, no end of scan IRQ pending

• 1 = A scan cycle has been completed, end of scan IRQ pending

In looping scan modes, this interrupt is triggered at the completion of each iteration of the loop. This interrupt is triggered only by the completion of a B converter scan in non-simultaneous (SIMULT=0) parallel scan modes. In this case the EOSI0 interrupt is triggered when converter A completes its scan.

28.5.7.5

End of Scan Interrupt 0 (EOSI0)—Bit 11

This bit indicates whether a scan of analog inputs has been completed since the last read of the STAT register or a reset. The EOSI0 bit is cleared by writing 1 to it. This bit cannot be set by software. EOSI0 is the preferred bit to poll for scan completion if interrupts are not enabled.

• 0 = A scan cycle has not been completed, no end of scan IRQ pending

• 1 =A scan cycle has been completed, end of scan IRQ pending

In looping scan modes, this interrupt is triggered at the completion of each iteration of a loop.

This interrupt is triggered upon the completion of any sequential scan or parallel scan with SIMULT=1.

When executing parallel scans with SIMULT = 0, this interrupt is triggered when converter A completes its scan while the EOSI1 interrupt services converter B.

28.5.7.6

Zero Crossing Interrupt (ZCI)—Bit 10

This bit is asserted at the completion of an individual conversion experiencing a zero crossing enabled in the ADC zero crossing control (ADZCC) register. The bit is set as soon as an enabled zero crossing event occurs rather than at the end of the ADC scan.

The ZCI bit is cleared by writing 1 to all active ZCS[7:0] bits in the ADZCSTAT register.

• 0 = No ZCI interrupt request

• 1 = Zero crossing encountered; IRQ pending if ZCIE is set

28.5.7.7

Low Limit Interrupt (LLMTI)—Bit 9

If any low limit (LOLIM n ) register is enabled by having a value other than $0000, low limit checking is enabled. This bit is set at the completion of an individual conversion which may or may not be the end of a scan.



Preliminary

28-33


The LLMTI bit is cleared by writing 1 to all active LLS[7:0] bits in the ADLSTAT register.

• 0 = No low limit interrupt request

• 1 = Low limit exceeded, IRQ pending if LLMTIE is set

28.5.7.8

High Limit Interrupt (HLMTI)—Bit 8

If any high limit (HILIM n ) register is enabled by having a value other than 0x7FF8, high limit checking is enabled. This bit is set at the completion of an individual conversion which may or may not be the end of a scan.

The HLMTI bit is cleared by writing 1 to all active HLS[7:0] bits in the ADLSTAT register.

• 0 = No high limit interrupt request

• 1 = High limit exceeded, IRQ pending if HLMTIE is set

28.5.7.9

Ready Sample 7 – 0 (RDY n )—Bits 7 – 0

These bits indicate samples 7-0 are ready to be read. The RDY n bits are set as the individual channel conversions are completed and stored in a ADRSLT n register. These bits are cleared after a read from the corresponding ADC results (ADRSLT n ) register. If polling the RDY n bits to determine if a particular sample is executed, care should be taken to not start a new scan until all enabled samples are completed.

NOTE

RDY n bits can be cleared when the debugger reads the corresponding

Results register during a debug session.

• 0 = Sample not ready or has been read

• 1 = Sample ready to be read

Figure 28-21

illustrates how five interrupts sources are combined into three entries in the interrupt vector table.

EOSI0

EOSIE0

EOSI1

EOSIE1

ZCI

ZCIE

LLMTI

LLMTIE

HLMTI

HLTMIE

ADCA Conversion Complete

(ADC_CC0_INT)

ADCB Conversion Complete

(ADC_CC1_INT)

ADC Zero Crossing or Limit Error

(ADC_ERR_INT)

Figure 28-21. ADC Interrupt Sources

28-34



Preliminary


28.5.8

Limit Status Register (ADLSTAT)

The ADC limit status (ADLSTAT) register latches in the result of the comparison between the result of the sample in the ADRSLT n register and the respective limit register, HILIM n or LOLIM n .

For example, if the result for ADRSLT0 is greater than the value programmed into the HILIM0, then set the HLS0 bit to 1. An interrupt is generated if the HLMTIE bit is set in CTRL1. These bits are sticky—once set, the bits require a specific modification to clear them. They are not cleared automatically by subsequent conversions. A bit may only be cleared by writing a value of one to that specific bit.

IPSBAR

Offset:

0x19_0007 (ADLSTAT) Access: read/write

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

HLS7 HLS6 HLS5 HLS4 HLS3 HLS2 HLS1 HLS0 LLS7 LLS6 LLS5 LLS4 LLS3 LLS2 LLS1 LLS0

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 28-22. Limit Status (ADLSTAT) Register

28.5.9

Zero Crossing Status Register (ADZCSTAT)

The ADC zero crossing status (ADZCSTAT) register latches in the result of the comparison between the current result of the sample and the previous result of the same results register. For example, if the result for the channel programmed in SAMPLE0 changes sign from the previous conversion, and the respective

ZCE bit in ADZCC register is set to 11b (any edge change), then set the ZCS0 bit to 1. An interrupt is generated if the ZCIE bit is set in the CTRL1 register. These bits are sticky—once set, they require a write to clear them. They are not cleared automatically by subsequent conversions. A bit may only be cleared by writing a value of 1 to that specific bit.

IPSBAR

Offset:

0x19_0008 (ADZCSTAT)

W

15

R 0

Reset 0

14

0

0

13

0

12

0

11

0

10

0

9

0

8

0

7 6 5 4

0 0 0 0 0 0 0 0 0 0

Figure 28-23. Zero Crossing Status (ADZCSTAT) Register

3

ZCS7 ZCS6 ZCS5 ZCS4 ZCS3 ZCS2 ZCS1 ZCS0

0

Access: read/write

2

0

1

0

0

0

28.5.9.1

Reserved—Bits 15 – 8




Preliminary

28-35


28.5.9.2

Zero Crossing Status (ZCS[7:0])—Bits 7 – 0

The zero crossing condition is determined by examining the ADC value after it has been adjusted by the offset for the result register. Please see

Figure 28-7 .

Each bit of the register is cleared by writing 1 to that register bit.

• 0 = a. A sign change did not occur in a comparing the current ADRSLT n value and the previous

ADRSLT n value, or b. Zero crossing control is disabled for sample n in the ADC zero crossing control

(ADZCC) register

• 1 = In a comparison between the current channelx result and the previous channelx result, a sign change condition occurred as defined in the ADC zero crossing control (ADZCC) register

28.5.10 Result 0-7 Registers (ADRSLT0–7)

The 8 result registers contain the converted results from a scan. The SAMPLE0 result is loaded into

ADRSLT0 register, SAMPLE1 result in ADRSLT1 register, and so on. In a simultaneous parallel scan mode, the first channel pair, designated by SAMPLE0 and SAMPLE4 in register LIST1/2, is stored in

ADRSLT0 and ADRSLT4, respectively.

When writing to this register, only the RSLT portion of the value written is used. This value is modified as shown in

Figure 28-7

and the result of the subtraction is stored. The SEXT bit is only set as a result of this subtraction and is not directly determined by the value written.

ADC Result Register 0

—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:

ADC_BASE + $12

ADC_BASE + $14

ADC_BASE + $16

ADC_BASE + $18

ADC_BASE + $1A

ADC_BASE + $1C

ADC_BASE + $1E

ADC_BASE + $20

IPSBAR

Offset:

0x19_0009 - 0x19_0010 (ADRSLT0–7)

14 13 12 11 10 15

R SEXT

W

Reset 0 0 0 0

9

RSLT

8 7 6 5

0 0 0 0 0 0 0

Figure 28-24. Result (ADRSLT0

–

7) Registers

0

4 3

0

Access: read/write

2

0

0

1

0

0

0

0

0

28-36



Preliminary


28.5.10.1 Sign Extend (SEXT)—Bit 15

SEXT is the sign-extend bit of the result. When the SEXT bit is set to 1, it implies a negative result. When the SEXT bit is set to 0, it implies a positive result. If only positive results are required, then the respective

ADC Offset (ADOFS n ) register must be set to a value of 0.

28.5.10.2 Digital Result of the Conversion (RSLT)—Bits 14 – 3

RSLT can be interpreted as either a signed integer or a signed fixed point (fractional) number. As a fixed point number, the RSLT can be used directly. As a signed integer, one has the option to right shift with sign extend (ASR) three places to fit it into the range [0,4095]. Or one can accept the number as presented in the register, knowing there are missing codes, because the lower three LSBs are always zero.

Negative results, SEXT = 1, are always presented in twos complement format. If it is a requirement of an application that the result registers always be positive, the offset register (ADOFS n) must always be set to

0.

The interpretation of the numbers programmed into the ADC limit and offset (LOLIM n , HILIM n , and

ADOFS n ) registers should match your interpretation of the result register.

28.5.10.3 Test Data (Test_Data)—Bits 14 – 3

When the ADC is stopped or in power-down mode, this field can be written by accessing the register in the memory map. Please see

Section 28.4.3 “ADC Data Processing ” more information.

28.5.10.4 Reserved—Bits 2 – 0


28.5.11 Low and High Limit Registers (LOLIM0-7 and HILIM0-7)

Each ADC sample is compared against the values in the limit registers. The comparison is based upon the

raw conversion value before the offset correction is applied. Refer to Figure 28-7 .

ADC limit registers

(LOLIM n and HILIM n) correspond to results (ADRSLT n ) registers. The high limit register is used for the comparison of result > high limit. The low limit register is used for the comparison of result < low limit.

The limit checking can be disabled by programming the respective limit register with 0x7FF8 for the high limit and 0x0000 for the low limit. At reset, limit checking is disabled.

ADC Low Limit Register 0

—

Address: ADC_BASE + $22


—



—



—



—

Address: ADC_BASE + $2A


—

Address: ADC_BASE + $2C


—

Address: ADC_BASE + $2E


—




Preliminary

28-37


IPSBAR

Offset:

0x19_0011 - 0x19_0018 (LOLIM0–7)

14 13 12 11 15

R 0

W

Reset 0 0 0 0 0

10

0

9

LLMT

8 7 6

0 0

Figure 28-25.

0 0

ADC High Limit Register 0

—



—



—



—



—

Address: ADC_BASE + $3A


—

Address: ADC_BASE + $3C


—

Address: ADC_BASE + $3E


—


5

0

IPSBAR

Offset:

0x19_0019 - 0x19_0020 (HILIM0–7)

14 13 12 11 15

R 0

W

Reset 0 0 0 0

10 9

HLMT

8 7 6 5

0 0 0 0 0 0 0

Figure 28-26. High Limit Register (HILIM0–7)

4

0

4

0

3

0

3

0

Access: read/write

2

0

0

2

0

1

0

1

0

0

0

0

0

Access: read/write

0

0

0

0

0

28.5.12 Offset Registers (ADOFS0–7)

Value of the offset (ADOFS n ) register is used to correct the ADC result before it is stored in the ADRSLT n registers.

ADC Offset Register 0

—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:


—

Address:

ADC_BASE + $42

ADC_BASE + $44

ADC_BASE + $46

ADC_BASE + $48

ADC_BASE + $4A

ADC_BASE + $4C

ADC_BASE + $4E

ADC_BASE + $50

28-38



Preliminary


IPSBAR

Offset:

0x19_0021 - 0x19_0028 (ADOFS0–7)

14 13 12 11 15

R 0

W

Reset 0 0 0 0 0

10

0

9

OFFSET

0

8

0

7

0

6

0

5

0

Figure 28-27. Offset 0-7 (ADOFS0-7) Registers

4

0

3

0

Access: read/write

2

0

0

1

0

0

0

0

0

The offset value is subtracted from the ADC result. In order to obtain unsigned results, the respective offset register should be programmed with a value of $0000, thus giving a result range of $0000 to $7FF8.

28.5.13 Power Control Register (POWER)

This register controls the power management features of the ADC module. There are manual power-down control bits for the two ADC converters and the shared voltage reference generator. There are also 5 distinct power modes with related controls:

1. Powered-down state

Each converter and the voltage reference generator can individually be put into a powered down state. When powered down, the unit consumes no power. Results of scans referencing a powered down converter are undefined. The voltage reference generator and at least one converter must be powered up to use the ADC module.

2. Manual power-down controls

Each converter and the voltage reference generator have a manual power control bit capable of forcing that component into the power down state. Also, each converter and the voltage reference generator can be powered up/down automatically as part of ADC operation.

3. Idle state

The ADC module is idle when neither of the two converters has a scan in process.

4. Active state

The ADC module is active when at least one of the two converters has a scan in process.

5. Current mode

• Normal current mode is used to power the converters at clock rates above 100 kHz.

• Standby current mode uses less power and is engaged only when the ADC clock is at 100 kHz. The current mode active does not affect the number of ADC clock cycles required to do a conversion or the accuracy of a conversion. The ADC module may change the current mode when idle as part of the power saving strategy. Both converters will be in the same current mode at all times.

In addition to the power modes, there is startup delay:

• Auto power-down and auto standby power modes cause a startup delay when the ADC module goes between the idle and active states to allow time to switch clocks or power configurations. The number of ADC clocks used in the startup delay is defined by the PUDELAY field.

See the discussion of power modes in the Functional Description

Section 28.4 “Functional Description ”

for details of the 5 power modes and how to configure them. See Section 28.4.7 “ADC Clock ” for a more

detailed description of the clocking system and the control of current mode.



Preliminary

28-39


IPSBAR

Offset:

0x19_0029 (POWER)

15

R

W

ASB

Reset 0

14

0

0

13 12 11 10

0 PSTS2 PSTS1 PSTS0

0 0

9 8 7 6

PUDELAY

5

0 0 0 0 1 1 0

Figure 28-28. Power Control (POWER) Register

4

1

Access: read/write

3 2 1 0

APD PD2 PD1 PD0

0 1 1 1

28.5.13.1 Auto Standby (ASB)—Bit 15

The ASB bit selects auto standby mode. ASB is ignored if APD is 1. When the ADC is idle, auto standby mode selects the standby clock as the ADC clock source and puts the converters into standby current mode.

At the start of any scan, the conversion clock is selected as the ADC clock and a delay of PUDELAY ADC clock cycles is imposed for current levels to stabilize. After this delay, the ADC will initiate the scan.

When the ADC returns to the idle state, the standby clock is again selected and the converters revert to the standby current state.

• 0 = Auto standby mode disabled

• 1 = Auto standby mode enabled

28.5.13.2 Reserved—Bits 14–13


28.5.13.3 Voltage Reference Power Status 2 (PSTS2)—Bit 12

PSTS2 is a read-only bit. It simply reflects whether the voltage reference circuit is currently enabled.

• 0 = Voltage reference circuit is currently powered up

• 1 = Voltage reference circuit is currently powered down

28.5.13.4 Converter B Power Status 1 (PSTS1)—Bit 11

PSTS1 is a read-only bit. It is asserted immediately following a write of 1 to PD1. It is deasserted

PUDELAY ADC clock cycles after writing 0 to PD1 if APD is 0. This bit can be read as a status bit to determine when the ADC is ready for operation. During auto power-down mode, this bit indicates the current powered state of converter B.

• 0 = ADC converter B is currently powered up

• 1 = ADC converter B is currently powered down

28.5.13.5 Converter A Power Status 0 (PSTS0)—Bit 10

PSTS0 is a read-only bit. It is asserted immediately following a write of 1 to PD0. It is deasserted

PUDELAY ADC clock cycles after writing 0 to PD0 if APD is 0. This bit can be read as a status bit to determine when the ADC is ready for operation. During auto power-down mode, this bit indicates the current powered state of converter A.

28-40



Preliminary


• 0 = ADC converter A is currently powered up

• 1 = ADC converter A is currently powered down

28.5.13.6 Power-Up Delay (PUDELAY)—Bits 9–4

This 6-bit field determines the number of ADC clocks provided to power-up an ADC converter (after setting PD0 or PD1 to 0) before allowing a scan to start. It also determines the number of ADC clocks of delay provided in auto power-down (APD) and auto standby (ASB) modes between when the ADC goes from the idle to active state and when the scan is allowed to start. The default value is 13 ADC clocks.

Accuracy of the initial conversions in a scan will be degraded if PUDELAY is set to too small a value.

NOTE

PUDELAY defaults to a value typically sufficient for any power mode. The latency of a scan can be reduced by reducing PUDELAY to the lowest value for which accuracy is not degraded. Please refer to the Device Data Sheet for further details.

28.5.13.7 Auto Power-Down (APD)—Bit 3

Auto power-down mode powers down converters when not in use for a scan. APD takes precedence over

ASB. When a scan is started in APD mode, a delay of PUDELAY ADC clock cycles is imposed during which the needed converter(s), if idle, are powered up. The ADC will then initiate a scan equivalent to when APD is not active. When the scan is completed, the converter(s) are powered down again.

• 0 = Auto power-down mode is not active

• 1 = Auto power-down mode is active

NOTE

If ASB or APD is asserted while a scan is in progress, that scan is unaffected and the ADC will wait to enter its low power state until after all conversions are complete and both ADCs are idle.

NOTE

ASB and APD are not useful in looping modes. The continuous nature of scanning means the low power state can never be entered.

28.5.13.8 Power-Down Control for Voltage Reference Circuit 2 (PD2)—Bit 2

This bit controls the power-down of the ADC’s voltage reference current.

• 0 = Manually power-up voltage reference circuit

• 1 = Power-down voltage reference circuit is controlled by PD0 and PD1 (default)

The voltage reference circuit is shared by both converters. When PD2=1 the voltage reference will be activated whenever PD1 or PD0 are powered up. It is not usually necessary to modify this bit, since powering down both converter A and converter B will automatically power-down the voltage reference.



Preliminary

28-41


28.5.13.9 Manual Power-Down for Converter B (PD1)—Bit 1

This bit forces ADC converter B to power-down.

• 0 = Power-up ADC converter B

• 1 = Power-down ADC converter B

Asserting PD1 powers down converter B immediately. The results of a scan using converter B will be invalid while PD1 is asserted. When PD1 is cleared, converter B is either continuously powered up (APD

= 0) or automatically powered up when needed (APD=1).

When clearing PD1 in any power mode except auto power-down (APD=1), wait PUDELAY ADC clock cycles before initiating a scan to stabilize power levels within the converter. The PSTS1 bit can be polled to determine when the PUDELAY time has elapsed. Failure to follow this procedure can result in loss of accuracy of the first two samples.

28.5.13.10 Manual Power-Down for Converter A (PD0)—Bit 0

This bit forces ADC converter A to power-down.

• 0 = Power-up ADC converter A

• 1 = Power-down ADC converter A

Asserting PD0 powers down converter A immediately. The results of a scan using converter A will be invalid while PD0 is asserted. When PD0 is cleared, converter A is either continuously powered up (APD

= 0) or automatically powered up when needed (APD=1).

When clearing PD0 in any power mode except auto power-down (APD=1), wait PUDELAY ADC clock cycles before initiating a scan to stabilize power levels within the converter. The PSTS0 bit can be polled to determine when the PUDELAY time has elapsed.

NOTE

Failure to follow this procedure can result in loss of accuracy of the first two samples.

28.5.14 Voltage Reference Register (CAL)

In earlier series, this register supported ADC calibration and had a different name. Improvements in ADC performance have eliminated the need for on-chip calibration support, hence the new name.


Offset:

0x19_002A (CAL)

15 14

R

SEL_VREFH SEL_VREFL

W

Reset 0 0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

0 0 0 0 0 0 0 0 0

Figure 28-29. Voltage Reference (CAL) Register

4

0

0

3

0

0

2

0

0

1

0

0

0

0

0

28-42



Preliminary


28.5.14.1 Select V

REFH

Source (SEL_VREFH)—Bit 15

This bit selects the source of the V

REFH

reference for conversions.

• 0 = Internal VR

X

• 1 = AN2

28.5.14.2 Select V

REFL

Source (SEL_VREFL)—Bit 14

This bit selects the source of the V

REFL

reference for conversions.

• 0 = Internal VR

X

• 1 = AN6

28.5.14.3 Reserved—Bits 13–0




Preliminary

28-43


28-44



Preliminary

Chapter 29


29.1

Introduction

This chapter describes the configuration and operation of the pulse width modulation (PWM) module. It includes a block diagram, programming model, and functional description.

29.1.1

Overview

The PWM module shown in Figure 29-1 , generates a synchronous series of pulses having programmable

period and duty cycle. With a suitable low-pass filter, the PWM can be used as a digital-to-analog converter.

Internal Bus

Clock (f sys/2

)

Clock select

PWM Clocks

Control

Enable

Polarity

Alignment

PWM Channels

Channel 7

Period and Duty Counter

Channel 6


Channel 5


Channel 4


Channel 3


Channel 2


Channel 1


Channel 0


PWMOUT7

PWMOUT5

PWMOUT3

PWMOUT1

Figure 29-1. PWM Block Diagram



Preliminary

29-1


Main features include the following:

• Double-buffered period and duty cycle

• Left- or center-aligned outputs

• Eight independent PWM modules. Notice that only the four odd PWM channel outputs are available on the device. The even channels can be used for concatenation purposes to generate

16-bit PWM for the odd channels.

• Byte-wide registers provide programmable duty cycle and period control

• Four programmable clock sources

NOTE

The GPIO module must be configured to enable the peripheral function of the appropriate pins (refer to Chapter 11, “General Purpose I/O Module ”) prior to configuring the PWM module.

29.2


This section describes the registers and control bits in the PWM module. There are eight independent

PWM modules, each with its own control and counter registers, although only four channels have an output signal. The memory map for the PWM is shown below.

Table 29-1. PWM Memory Map

IPSBAR Offset

1,2

Register

Width

(bits)


0x001B_0000 PWM Enable Register (PWME)

0x001B_0001 PWM Polarity Register (PWMPOL)

0x001B_0002 PWM Clock Select Register (PWMCLK)

0x001B_0003 PWM Prescale Clock Select Register (PWMPRCLK)

8

8

8

8

R/W

R/W

R/W

R/W

0x00

0x00

0x00

0x00

29.2.1/29-3

29.2.2/29-3

29.2.3/29-4

29.2.4/29-5

0x001B_0004

0x001B_0005

0x001B_0008

0x001B_0009

PWM Center Align Enable Register (PWMCAE)

PWM Control Register (PWMCTL)

PWM Scale A Register (PWMSCLA)

PWM Scale B Register (PWMSCLB)

8

8

8

8

8

R/W

R/W

R/W

R/W

R/W

0x00

0x00

0x00

0x00

0x00

29.2.5/29-6

29.2.6/29-6

29.2.7/29-7

29.2.8/29-8

29.2.9/29-9

0x001B_000C + n n = 0–7

PWM Channel n Counter Register (PWMCNT n )

0x001B_0014 + n n = 0–7

PWM Channel n Period Register (PWMPER n )

0x001B_001C + n n = 0–7

PWM Channel n Duty Register (PWMDTY n )

8

8

R/W

R/W

0xFF

0xFF

29.2.10/29-10

29.2.11/29-10

0x001B_0024 PWM Shutdown Register (PWMSDN) 8 R/W 0x00

29.2.12/29-11

1

Addresses not assigned to a register and undefined register bits are reserved for expansion. Write accesses to these reserved address spaces and reserved register bits have no effect.

29-2



Preliminary


2

32-bit access to any of these registers will result in a bus transfer error (see Section 11.2.7, “SCM Interrupt Status Register

(SCMISR)” ).

29.2.1

PWM Enable Register (PWME)

Each PWM channel has an enable bit (PWME n ) to start its waveform output. While in run mode, if all four

PWM output channels are disabled (PWME[7:0] = 0), the prescaler counter shuts off for power savings.

See Section 29.3.2.1, “PWM Enable”


Address: 0x001B_0000 (PWME)

7 6

0 R

W

Reset:

PWME7

0

5

PWME5

4

0

3

PWME3

0 0 0 0

Figure 29-2. PWM Enable Register (PWME)

0

2

0

Access: User Read/Write

1 0

0

PWME1

0 0

Table 29-2. PWME Field Descriptions


7

PWME5

PWM channel 7 output enable. If enabled, the PWM signal becomes available at PWMOUT7 when its corresponding clock source begins its next cycle.

0 PWM output disabled

1 PWM output enabled


5

PWME5





3

PWME3





1

PWME1





29.2.2

PWM Polarity Register (PWMPOL)

The starting polarity of each PWM channel waveform is determined by the associated PWMPOL[PPOL n ] bit. If the polarity is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.



Preliminary

29-3


Address: 0x001B_0001 (PWMPOL)

7 6

0 R

W

Reset:

PPOL7

0

5

PPOL5

4

0

3

PPOL3

0 0 0 0

Figure 29-3. PWM Polarity Register (PWMPOL)

0

2

0


1 0

0

PPOL1

0 0

Table 29-3. PWMPOL Field Descriptions


7,5,3,1

PPOL n

PWM channel n polarity.

0 PWM channel n output is low at the beginning of the period, then goes high when the duty count is reached

1 PWM channel n output is high at the beginning of the period, then goes low when the duty count is reached

6,4,2,0 Reserved, should be cleared.

29.2.3

PWM Clock Select Register (PWMCLK)

Each PWM channel has the capability of selecting one of two clocks. For channels 1 and 5, the clock choices are clock A or SA. For channels 3 and 7, the choices are clock B or SB. The clock selection is done with the below PWMCLK[PCLK n ] control bits. If a clock select is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.

Address: 0x001B_0002 (PWMCLK)

7 6

0 R

W

Reset:

PCLK7

0

5

PCLK5

4

0

3

PCLK3

2

0

0 0 0 0 0

Figure 29-4. PWM Clock Select Register (PWMCLK)


1 0

0

PCLK1

0 0

29-4



Preliminary


Table 29-4. PWMCLK Field Descriptions


7,5,3,1

PCLK n

PWM channel n clock select. Selects between one of two clock sources for each PWM channel. See

Section 29.2.4,

“PWM Prescale Clock Select Register (PWMPRCLK)”

and Section 29.2.7, “PWM Scale A Register (PWMSCLA)”

for more information on how the different clock rates are generated. The even-numbered channels’ clock select has no effect when the corresponding PWMCTL[CON n(n+1) ] bit is set. For example, if PWMCTL[CON01] = 1 then

PWMCLK[PCLK0] has no affect.

0

1

PCLK7

(PCLK7 Clock

Source)

B

SB

PCLK5

(PWM5 Clock

Source)

A

SA

PCLK3

(PWM3 Clock

Source)

B

SB

PCLK1

(PWM1 Clock

Source)

A

SA


29.2.4

PWM Prescale Clock Select Register (PWMPRCLK)

The PWMPRCLK register selects the prescale clock source for clocks A and B independently. If the clock prescale is changed while a PWM signal is being generated, a truncated or stretched pulse can occur during the transition.

Address: 0x001B_0003 (PWMPRCLK)

6 7

0 R

W

Reset:

5

PCKB

4 3

0

2


1

PCKA

0 0 0 0 0 0

Figure 29-5. PWM Prescale Clock Select Register (PWMPRCLK)

0

0

0

Table 29-5. PWMPRCLK Field Descriptions

Field

7

6–4

PCKB

Description


Clock B prescalar select. These three bits control the rate of Clock B which can be used for PWM channels 3 and 7.

000

001

...

111

Internal bus clock

÷

2

0

Internal bus clock

÷

2

1

...

Internal bus clock

÷

2

7



Preliminary

29-5


Table 29-5. PWMPRCLK Field Descriptions (continued)

Field

3

2–0

PCKA

Description


Clock A prescalar select. These three bits control the rate of Clock A which can be used for PWM channels 1 and 5.

PCKA

000

001

...

111

Clock A Rate

Internal bus clock

÷

2

0

Internal bus clock

÷

2

1

...

Internal bus clock

÷

2

7

29.2.5

PWM Center Align Enable Register (PWMCAE)

The PWMCAE register contains four control bits for the selection of center-aligned outputs or left-aligned outputs for each PWM channel. Write these bits only when the corresponding channel is disabled. See

Section 29.3.2.5, “Left-Aligned Outputs”

and Section 29.3.2.6, “Center-Aligned Outputs”

for a more detailed description of the PWM output modes.

Address: 0x001B_0004 (PWMCAE)

7 6

0 R

W

Reset:

CAE7

0

5

CAE5

4

0

3

CAE3

2

0

0 0 0 0 0

Figure 29-6. PWM Center Align Enable Register (PWMCAE)


1

CAE1

0

0

0

0

Table 29-6. PWMCAE Field Descriptions


7,5,3,1

CAE n

Center align enable for channel n . The even-numbered channels’ center align enable has no effect when the corresponding PWMCTL[CON n(n+1) ] bit is set. For example, if PWMCTL[CON01] = 1 then PWMCAE[CAE0] has no affect.

0 Channel n operates in left-aligned output mode

1 Channel n operates in center-aligned output mode


29.2.6

PWM Control Register (PWMCTL)

The PWMCTL register provides various control of the PWM module. Change the CON n(n+1) bits only when both corresponding channels are disabled. See

Section 29.3.2.7, “PWM 16-Bit Functions”

for a more detailed description of the concatenation function.

29-6



Preliminary


Address: 0x001B_0005 (PWMCTL)

7 6

R

W

Reset:

CON67

0

CON45

5

CON23

4

CON01

3

PSWAI

2

PFRZ

0 0 0 0

Figure 29-7. PWM Control Register (PWMCTL)

0


1

0

0

0

0 0

Table 29-7. PWMCTL Field Descriptions


7

CON67

Concatenates PWM channels 6 and 7 to form one 16-bit PWM channel.

0 Channels 6 and 7 are separate 8-bit PWMs. Note that there is no PWM 6 output.

1 Concatenate PWM 6 and 7. Channel 6 becomes the high order byte and channel 6 the low order byte. PWMOUT7 is the output for this 16-bit PWM signal, and PWMOUT6 is disabled. The channel 7 clock select, polarity, center align enable, and enable bits control this concatenated output.

6

CON45




5

CON23




4

CON01




3

PSWAI

PWM stops in doze mode. Disables the input clock to the prescaler while in doze mode.

0 Allow the clock to the prescaler while in doze mode

1 Stop the input clock to the prescaler whenever the core is in doze mode

2

PFRZ

1–0

PWM counters stop in debug mode (BKPT asserted).

0 Allow PWM counters to continue while in debug mode

1 Disable PWM input clock to the prescaler when the core is in debug mode. Useful for emulation as it allows the

PWM function to be suspended.


29.2.7

PWM Scale A Register (PWMSCLA)

PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is generated with the following equation:

Clock SA = Eqn. 29-1

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).



Preliminary

29-7


Address: 0x001B_0008 (PWMSCLA)

7 6

R

W

Reset: 0

5 4

SCALEA

3 2

0 0 0 0 0

Figure 29-8. PWM Scale A Register (PWMSCLA)

Table 29-8. PWMSCLA Field Descriptions


7–0

SCALEA

Part of divisor used to form Clock SA from Clock A.

SCALEA Value

0x00

0x01

0x02

...

0xFF

256

1

2

...

255


1 0

0 0

29.2.8

PWM Scale B Register (PWMSCLB)

PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is generated according to the following equation:

Clock SB = Eqn. 29-2

Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).

Address: 0x001B_0009 (PWMSCLB)

7 6

R

W

Reset: 0

5 4

SCALEB

3 2

0 0 0 0 0

Figure 29-9. PWM Scale B Register (PWMSCLB)


1 0

0 0

29-8



Preliminary

Table 29-9. PWMSCLB Field Descriptions


7–0

SCALEB

Divisor used to form Clock SB from Clock B.

SCALEB Value

0x00

0x01

0x02

...

0xFF

256

1

2

...

255


29.2.9

PWM Channel Counter Registers (PWMCNT

n

)

Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source,

PWMCLK[PCLK n ]. The user can read the counters at any time without affecting the count or the operation of the PWM channel. In left-aligned output mode, the counter counts from 0 to the value in the period register minus 1. In center-aligned output mode, the counter counts from 0 up to the value in the period register and then back down to 0. Therefore, given the same value in the period register, center-aligned mode is twice the period of left-aligned mode.

Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up for center-aligned mode, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit.

The counter is also cleared at the end of the effective period (see

Section 29.3.2.5, “Left-Aligned Outputs”

and Section 29.3.2.6, “Center-Aligned Outputs”

for more details). When the channel is disabled

(PWME n =0), the PWMCNT n register does not count. When a channel is enabled (PWME n =1), the associated PWM counter starts at the count in the PWMCNT n register. For more detailed information on the operation of the counters, refer to

Section 29.3.2.4, “PWM Timer Counters.”

Address: 0x001B_000C (PWMCNT0)

0x001B_000D (PWMCNT1)

0x001B_000E (PWMCNT2)

0x001B_000F (PWMCNT3)

0x001B_0010 (PWMCNT4)

0x001B_0011 (PWMCNT5)

0x001B_0012 (PWMCNT6)

0x001B_0013 (PWMCNT7)

7 6

R

W

Reset: 0

5 4

COUNT

3 2

0 0 0 0 0

Figure 29-10. PWM Counter Registers (PWMCNT n )


1

0

0

0



Preliminary

29-9


Table 29-10. PWMCNT n Field Descriptions


7–0

COUNT

Current value of the PWM up counter. Resets to zero when written.

29.2.10 PWM Channel Period Registers (PWMPER

n

)

The PWM period registers determine the period of the associated PWM channel. Refer to Section 29.3.2.3,

“PWM Period and Duty”


Calculating the output period depends on the output mode (center-aligned has twice the period as left-aligned mode) as well as PWMPER n . See the below equation:

PWM n period = Channel clock period × ( PWMCAE CAE n ] + 1 ) × PWMPER n Eqn. 29-3

For boundary case programming values (e.g. PWMPER n = 0x00), please refer to

Section 29.3.2.8, “PWM

Boundary Cases

.”

Address: 0x001B_0014 (PWMPER0)

0x001B_0015 (PWMPER1)

0x001B_0016 (PWMPER2)

0x001B_0017 (PWMPER3)

0x001B_0018 (PWMPER4)

0x001B_0019 (PWMPER5)

0x001B_001A (PWMPER6)

0x001B_001B (PWMPER7)

7 6

R

W

Reset: 1

5 4

PERIOD

3 2

1 1 1 1 1

Figure 29-11. PWM Period Registers (PWMPER n )

Table 29-11. PWMPER n Field Descriptions


1

1

0

1


7–0

PERIOD

Period counter for the output PWM signal.

If PERIOD = 0x00, the PWM n output is always high (PPOL n =1) or always low (PPOL n =0). See

Section 29.3.2.8,

“PWM Boundary Cases”

for other special cases.

29.2.11 PWM Channel Duty Registers (PWMDTY

n

)

The PWM duty registers determine the duty cycle of the associated PWM channel. To calculate the output duty cycle (high time as a percentage of period) for a particular channel:

Duty Cycle = – n ] –

PWMDTY n

PWMPER n

⎞

× 100% Eqn. 29-4

29-10



Preliminary


For boundary case programming values (e.g. PWMDTY n = 0x00 or PWMDTY n > PWMPER n ), refer to

Section Section 29.3.2.8, “PWM Boundary Cases.”

Address: 0x001B_001C (PWMDTY0)

0x001B_001D (PWMDTY1)

0x001B_001E (PWMDTY2)

0x001B_001F (PWMDTY3)

0x001B_0020 (PWMDTY4)

0x001B_00241 (PWMDTY5)

0x001B_0022 (PWMDTY6)

0x001B_0023 (PWMDTY7)

7 6

R

W

Reset: 1

5 4

DUTY

3 2

1 1 1 1 1

Figure 29-12. PWM Duty Registers (PWMDTY n )


1

1

0

1

Table 29-12. PWMDTY n Field Descriptions

Field

7–0

DUTY

Description

Contains the duty value used to determine when a transition will occur on the PWM output signal. When a match occurs with the corresponding PWMCNT n register, the PWM output will toggle.

If DUTY = 0x00, the PWM n output is always low (PPOL n =1) or always high (PPOL n =0). See

Section 29.3.2.8, “PWM

Boundary Cases”

for other special cases.

29.2.12 PWM Shutdown Register (PWMSDN)

The PWM shutdown register provides emergency shutdown functionality of the PWM module. The

PWMSDN[7:1] bits are ignored if PWMSDN[SDNEN] is cleared.

Address: 0x24 (PWMSDN)

R

W

Reset:

7

IF w1c

0

6

IE

5

0

RESTART

0

4

LVL

3

0

2

PWM7IN

0 0 0 0

Figure 29-13. PWM Shutdown Register (PWMSDN)

Access: Read/Write

1 0

PWM7IL

0

SDNEN

0



Preliminary

29-11


Table 29-13. PWMSDN Field Descriptions


7

IF

6

IE

PWM interrupt flag. Any change in state of PWM7IN will be flagged by setting this bit. The flag is cleared by writing a ‘1’ to it. Writing ‘0’ has no effect.

0 No change in PWM7IN input

1 Change in PWM7IN input

PWM interrupt enable. An interrupt will be triggered to the device’s interrupt controller when PWMSDN[IF] is set.

0 Interrupt is disabled

1 Interrupt is enabled

5

RESTART

PWM restart. After setting the RESTART bit, the PWM channels start running after the corresponding counter resets to zero. Also, if emergency shutdown is cleared (after being set), the PWM outputs will restart after the corresponding counter resets to zero. This bit is self-clearing, so is always read as zero.

4

LVL

3

PWM shutdown output level. Describes the behavior of the PWM outputs when PWM7IN input is asserted and

PWMSDN[SDNEN] is set.

0 PWM outputs are forced to logic 0

1 PWM outputs are forced to logic 1


2

PWM7IN

PWM channel 7 input status. Reflects the current status of the PWMOUT7 pin. Read only.

1

PWM7IL

PWM channel 7 input polarity. If PWMSDN[SDNEN] is set, this bit sets the active level of the PWM 7 channel

0 PWM 7 input is active low

1 PWN 7 input is active high

0

SDNEN

PWM emergency shutdown enable. If set, the pin associated with PWM channel 7 is forced to input and the emergency shutdown feature is enabled.

0 Emergency shutdown is disabled

1 Emergency shutdown is enabled

29.3


29.3.1

PWM Clock Select

There are four available clocks—clock A, B, SA (scaled A), and SB (scaled B)—all based on the internal bus clock.

Clock A and B can be programmed to run at 1, 1/2,..., 1/128 times the internal bus clock. Clock SA and

SB use clock A and B respectively as an input and divides it further with a reloadable counter. The rates available for clock SA and SB are programmable to run at clock A and B divided by 2, 4,..., or 512. Each

PWM channel has the capability of selecting one of two clocks, either the prescaled clock (clock A or B)

or the scaled clock (clock SA or SB). The block diagram in Figure 29-14 shows the four different clocks

and how the scaled clocks are created.

29-12



Preliminary


Internal Bus

Clock (f sys/

)

PWMPRCLK

[PCKA]

PWMPRCLK

[PCKB]

PWMSCLB

Clock B

1

0

1

0

PCLR0

Clock to

PWM0

Clock to

PWM1

PWMSCLA

Clock SA

÷

2

PCLR1

PCLR4

1

0

Clock to

PWM4

1

0

Clock to

PWM5

Clock SB

PCLR5

PCLR2

1

÷

2 0

1

0

Clock to

PWM2

1

0

1

0

PCLR3

PCLR6

Clock to

PWM3

Clock to

PWM6

Clock to

PWM7

Figure 29-14. PWM Clock Select Block Diagram

PCLR7

29.3.1.1

Prescaled Clock (A or B)

The internal bus clock is the input clock to the PWM prescaler that can be disabled when the device is in debug mode by setting the PWMCTL[PFRZ] bit. This is useful for reducing power consumption and for emulation in order to freeze the PWM. The input clock is also disabled when all PWM channels are disabled (PWME n =0).

Clock A and B are scaled values of the input clock. The value is software selectable for both clock A and

B and has options of 1, 1/2,..., or 1/128 times the internal bus clock. The value selected for clock A and B is determined by the PWMPRCLK[PCKA n ] and PWMPRCLK[PCKB n ] bits.



Preliminary

29-13


29.3.1.2

Scaled Clock (SA or SB)

The scaled A (SA) and scaled B (SB) clocks use clock A and B respectively as inputs, divide it further with a user programmable value, then divide this by 2. The rates available for clock SA are programmable to run at clock A divided by 2, 4,..., or 512. Similar rates are available for clock SB.

Clock SA equals clock A divided by two times the value in the PWMSCLA register:

Clock SA =

Similarly, clock SB is generated according to the following equation:

Eqn. 29-5

Clock SB = Eqn. 29-6

As an example, consider the case in which the user writes 0xFF into the PWMSCLA register. Clock A for this case is selected to be internal bus clock divided by 4. A pulse will occur at a rate of once every 255 × 4 bus cycles. Passing this through the divide by two circuit produces a clock signal of the internal bus clock divided by 2040. Similarly, a value of 0x01 in the PWMSCLA register when clock A is internal bus clock divided by 4 will produce an internal bus clock divided by 8 rate.

Writing to PWMSCLA or PWMSCLB causes the associated 8-bit down counter to be re-loaded.

Otherwise, when changing rates, the counter would have to count down to 0x01 before counting at the proper rate. Forcing the associated counter to re-load the scale register value every time PWMSCLA or

PWMSCLB is written prevents this.

Writing to the scale registers while channels are operating can cause irregularities in the PWM outputs.

29.3.1.3

Clock Select

Each PWM channel has the capability of selecting one of two clocks. For channels 0, 1, 4, and 5 the clock choices are clock A or SA. For channels 2, 3, 6 and 7, the choices are clock B or SB. The clock selection is done with the PWMCLK[PCLK x ] control bits.

Changing clock control bits while channels are operating can cause irregularities in the PWM outputs.

29.3.2

PWM Channel Timers

The main part of the PWM module is the actual timers. Each of the timer channels has a counter, a period register, and a duty register (each are 8-bit). The waveform output period is controlled by a match between the period register and the value in the counter. The duty is controlled by a match between the duty register and the counter value and causes the state of the output to change during the period. The starting polarity of the output is also selectable on a per channel basis.

Figure 29-15

shows a block diagram for a PWM timer.

29-14



Preliminary


Clock Source

From

Figure 29-14

PWMCNT n PWMDTY n 0

1

PWME n

PWMOUT n

PPOL n

PWMPER n

PWMCAE = 1

PWMCAE = 0

Figure 29-15. PWM Timer Channel Block Diagram

29.3.2.1

PWM Enable

Each PWM channel has an enable bit (PWME n ) to start its waveform output. When any of the PWME n bits are set (PWME n =1), the associated PWM output signal is enabled immediately. However, the actual

PWM waveform is not available on the associated PWM output until its clock source begins its next cycle; this is due to the synchronization of PWME n and the clock source. An exception is when channels are concatenated. Refer to

Section 29.3.2.7, “PWM 16-Bit Functions”

for more detail.

Note that the first PWM cycle after enabling the channel can be irregular. When the channel is disabled

(PWME n =0), the counter for the channel does not count.

29.3.2.2

PWM Polarity

Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram as a mux select. When one of the bits in the PWMPOL register is set, the associated

PWM channel output is high at the beginning of the waveform, then goes low when the duty count is reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.

29.3.2.3

PWM Period and Duty

Dedicated period and duty registers exist for each channel and are double buffered so that if they change while the channel is enabled, the change will not take effect until one of the following occurs:

• The effective period ends

• The PWMCNT n register is written (counter resets to 0x00)

• The channel is disabled, PWME n = 0

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between. If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer.

A change in duty or period can be forced into effect immediately by writing the new value to the duty and/or period registers and then writing to the counter. This forces the counter to reset and the new duty



Preliminary

29-15

Pulse Width Modulation (PWM) Module and/or period values to be latched. In addition, because the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used to make adjustments . When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur.

Depending on the polarity bit, the duty registers will contain the count of either the high time or the low time.

29.3.2.4

PWM Timer Counters

Each channel has a dedicated 8-bit up/down counter that runs at the rate of the selected clock source (see

Figure 29-14

for the available clock sources and rates). The counter compares to two registers, a duty register and a period register, as shown in

Figure 29-15

. When the PWM counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match between the

PWM counter and the period register behaves differently depending on what output mode is selected as shown in

Figure 29-15

and described in Section 29.3.2.5, “Left-Aligned Outputs”

and

Section 29.3.2.6,

“Center-Aligned Outputs.”

Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel.

Any value written to the counter causes the counter to reset to 0x00, the counter direction to be set to up, the immediate load of both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the channel is disabled (PWME n = 0), the counter stops. When a channel becomes enabled (PWME n = 1), the associated PWM counter continues from the count in the

PWMCNT n register. This allows the waveform to continue where it left off when the channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next selected clock.

NOTE

If the user wants to start a new clean PWM waveform without any history from the old waveform, the user must write to channel counter

(PWMCNT n ) prior to enabling the PWM channel (PWME n = 1).

Generally, writes to the counter are done prior to enabling a channel in order to start from a known state.

However, writing a counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the channel is disabled, except that the new period is started immediately with the output set according to the polarity bit. Writing to the counter while the channel is enabled can cause an irregular PWM cycle to occur.

The counter is cleared at the end of the effective period (see

Section 29.3.2.5, “Left-Aligned Outputs ” and

Section 29.3.2.6, “Center-Aligned Outputs”

for more details).

Table 29-14. PWM Timer Counter Conditions

Counter Clears (0x00)

When PWMCNT n register written to any value

Effective period ends

Counter Counts Counter Stops

When PWM channel is enabled

(PWME n = 1). Counts from last value in PWMCNT n .

When PWM channel is disabled

(PWME n = 0)

29-16



Preliminary


29.3.2.5

Left-Aligned Outputs

The PWM timer provides the choice of two types of outputs: left- or center-aligned. They are selected with the PWMCAE[CAE n ] bits. If the CAE n bit is cleared, the corresponding PWM output will be left-aligned.

In left-aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two

registers, a duty register and a period register, as shown in the block diagram in Figure 29-15 . When the

PWM counter matches the duty register, the output flip-flop changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register resets the counter and the output flip-flop, as shown in

Figure 29-16

, as well as performing a load from the double buffer period and

duty register to the associated registers, as described in Figure 29.3.2.3

. The counter counts from 0 to the value in the period register minus 1.

NOTE

Changing the PWM output mode from left-aligned to center-aligned output

(or vice versa) while channels are operating can cause irregularities in the

PWM output. It is recommended to program the output mode before enabling the PWM channel.

PPOL n = 0

PPOL n = 1

PWMDTY n

Period = PWMPER n

Figure 29-16. PWM Left-Aligned Output Waveform

To calculate the output frequency in left-aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by the value in the period register for that channel.

PWM n frequency =

PWMPER n

Eqn. 29-7

The PWM n duty cycle (high time as a percentage of period) is expressed as:

Duty Cycle =

⎛

⎝

– n ] –

PWMDTY n

PWMPER n

⎞

⎠

× 100% Eqn. 29-8

29.3.2.5.1

Left-Aligned Output Example

As an example of a left-aligned output, consider the following case:

Clock source = internal bus clock, where internal bus clock = 40 MHz (2.5 ns period)

PPOL n = 0, PWMPER n = 4, PWMDTY n = 1

PWM n frequency = 40 MHz ÷ 4 = 10 MHz

PWM n period = ns

PWMn Duty Cycle = 1 –

4

×



Preliminary

29-17


The output waveform generated is below:

E = 2.5ns

DUTY CYCLE = 75%

PERIOD = ns

Figure 29-17. PWM Left-Aligned Output Example Waveform

29.3.2.6

Center-Aligned Outputs

For center-aligned output mode selection, set the PWMCAE[CAE n ] bit and the corresponding PWM output will be center-aligned.

The 8-bit counter operates as an up/down counter in this mode and is set to up whenever the counter is equal to 0x00. The counter compares to two registers, a duty register and a period register, as shown in the

block diagram in Figure 29-15 . When the PWM counter matches the duty register, the output flip-flop

changes state, causing the PWM waveform to also change state. A match between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the PWM counter decrements and matches the duty register again, the output flip-flop changes state causing the

PWM output to also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back to an up-count, and a load from the double buffer period and duty registers to the associated registers is performed as described in

Figure 29.3.2.3

. The counter counts

from 0 up to the value in the period register and then back down to 0. Thus the effective period is

PWMPER n × 2.

Changing the PWM output mode from left-aligned output to center-aligned output (or vice versa) while channels are operating can cause irregularities in the PWM output. It is recommended to program the output mode before enabling the PWM channel.

PPOL n = 0

PPOL n = 1

PWMDTY n

PWMPER n

PWMDTY n

PWMPER n

PWM n frequency =

Period = PWMPER n

×

2

Figure 29-18. PWM Center-Aligned Output Waveform

To calculate the output frequency in center-aligned output mode for a particular channel, take the selected clock source frequency for the channel (A, B, SA, or SB) and divide it by twice the value in the period register for that channel.

Eqn. 29-9

29-18



Preliminary


The PWM n duty cycle (high time as a percentage of period) is expressed as:

Duty Cycle = – n ] –

PWMDTY n

PWMPER n

× 100%

29.3.2.6.1

Center-Aligned Output Example

As an example of a center-aligned output, consider the following case:

Clock source = internal bus clock, where internal bus clock = 40 MHz (2.5 ns period)

PPOL n = 0, PWMPER n = 4, PWMDTY n = 1

PWM n frequency = 40 MHz / (2 × 4) = 5 MHz

PWM n period = ns

PWMn Duty Cycle =

⎛

⎝

1 –

4

⎞

⎠

×

Shown below is the generated output waveform.

Eqn. 29-10

E = 2.5ns

E = 2.5ns

DUTY CYCLE = 75%

PERIOD = ns

Figure 29-19. PWM Center-Aligned Output Example Waveform

29.3.2.7

PWM 16-Bit Functions

The PWM timer also has the option of generating 48-bit channels or four 16-bit channels for greater PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.

The PWMCTL register contains four concatenation control bits, each used to concatenate a pair of PWM channels into one 16-bit channel. Channels 0 and 1 are concatenated with the CON01 bit, channels 2 and

3 are concatenated with the CON23 bit, and so on. Change these bits only when both corresponding channels are disabled.

As shown in Figure 29-20 , when channels 2 and 3 are concatenated, channel 2 registers become the high

order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers become the high order bytes of the double byte channel.

When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel clock select control bits (the odd numbered channel). The resulting PWM is output to the pins of the

corresponding low order 8-bit channel, as shown in Figure 29-20 . The polarity of the resulting PWM

output is controlled by the PPOL n bit of the corresponding low order 8-bit channel as well.

Once concatenated mode is enabled (PWMCTL[CON nn ] bits set), enabling/disabling the corresponding

16-bit PWM channel is controlled by the low order PWME n bit. In this case, the high order bytes’ PWME n bits have no effect, and their corresponding PWM output is disabled.

In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to either the low or high order byte of the counter will reset the 16-bit counter. Reads of the 16-bit counter must be made by

16-bit access to maintain data coherency.



Preliminary

29-19


Clock Source 7 High

PWMCNT6

Low

PWMCNT7

Clock Source 5

Period/Duty Compare

High

PWMCNT4

Low

PWMCNT5

Period/Duty Compare

Clock Source 3 High

PWMCNT2

Low

PWMCNT3

Period/Duty Compare

Clock Source 1 High

PWMCNT0

Low

PWMCNT1

PWMOUT7

PWMOUT5

PWMOUT3

Period/Duty Compare PWMOUT1

Figure 29-20. PWM 16-Bit Mode

Either left- or center-aligned output mode can be used in concatenated mode and is controlled by the low order CAE n bit. The high order CAE n bit has no effect. The table shown below is used to summarize which channels are used to set the various control bits when in 16-bit mode.

Table 29-15. 16-bit Concatenation Mode Summary

CON nn

CON67

CON45

CON23

CON01

PWME n

PWM7

PWM5

PWME3

PWME1

PPOL n

PPOL7

PPOL5

PPOL3

PPOL1

PCLK n

PCLK7

PCLK5

PCLK3

PCLK1

CAE n

CAE7

CAE5

CAE3

CAE1

PWM n

Output

PWMOUT7

PWMOUT5

PWMOUT3

PWMOUT1

29.3.2.8

PWM Boundary Cases

The following table summarizes the boundary conditions for the PWM regardless of the output mode (left- or center-aligned) and 8-bit (normal) or 16-bit (concatenation):

29-20



Preliminary


Table 29-16. PWM Boundary Cases

PWMDTY n PWMPER n

0x00

(indicates no duty)

>0x00

0x00

(indicates no duty)

>0x00

XX

XX

0x00

1

(indicates no period)

0x00

1

(indicates no period)

≥

PWMPER n

≥

PWMPER n

1

Counter = 0x00 and does not count.

XX

XX

PPOL n

1

0

1

0

1

0

PWM n Output

Always Low

Always High

Always High

Always Low

Always High

Always Low



Preliminary

29-21


29-22



Preliminary

Chapter 30

FlexCAN

30.1

Introduction

The FlexCAN is a communication controller implementing the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbps), short distance, priority-based protocol that can communicate using a variety of mediums

(such as fiber optic cable or an unshielded twisted pair of wires). The FlexCAN supports both the standard and extended identifier (ID) message formats specified in the CAN protocol specification, revision 2.0, part B.

The CAN protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this field: real-time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness, and required bandwidth. A general working knowledge of the CAN protocol revision 2.0 is assumed in this document. For details, refer to the CAN protocol revision 2.0 specification.

30.1.1

Block Diagram

A block diagram describing the various submodules of the FlexCAN module is shown in

Figure 30-1

.

Each submodule is described in detail in subsequent sections. The message buffer architecture is shown in

Figure 30-2

.

FlexCAN

MB15

MB14

MB3

MB2

MB1

MB0

••

••

••

••

••

••

••

••

••

••

Message

Buffer

Management

Max MB #

[0:15]

CAN

Protocol

Interface

Bus Interface Unit

CANTX

CANRX

Clocks, Address and Data Buses,

Interrupt and Test Signals

Internal Bus Interface

Figure 30-1. FlexCAN Block Diagram and Pinout



FlexCAN

Tx

Rx

Serial Buffers

Tx Shifter

Rx Shifter

Transparent to User

Mask 14

Mask 15

Global Mask

Control Interrupt Request

Data

•

•

•

16 Transmit/Receive

Message Buffers •

•

•

•

Buffer 13

Buffer 0

Data

Buffer 14

Buffer 15

Data

Data Length

Time Stamp

ID

•

•

•

• •

•

•

Figure 30-2. FlexCAN Message Buffer Architecture

30.1.1.1

The CAN System

A typical CAN system is shown below in

Figure 30-3

.

CAN Station 1 CAN Station 2 CAN Station n

ColdFire Processor

CANTX

FlexCAN

CANRX

Transceiver

CAN Bus

Figure 30-3. Typical CAN System

Each CAN station is connected physically to the CAN bus through a transceiver. The transceiver provides the transmit drive, waveshaping, and receive/compare functions required for communicating on the CAN bus. It can also provide protection against damage to the FlexCAN caused by a defective CAN bus or defective stations.

30-2



FlexCAN

30.1.2

Features

Following are the main features of the FlexCAN module:

• Full implementation of the CAN protocol specification version 2.0B

— Standard data and remote frames (up to 109 bits long)

— Extended data and remote frames (up to 127 bits long)

— 0–8 bytes data length

— Programmable bit rate up to 1 Mbps

— Content-related addressing

• Up to16 flexible message buffers of zero to eight bytes data length, each configurable as Rx or Tx, all supporting standard and extended messages

• Listen-only mode capability

• Three programmable mask registers: global (for MBs 0–13), special for MB14, and special for

MB15

• Programmable transmission priority scheme: lowest ID or lowest buffer number

• Time stamp based on 16-bit, free-running timer

• Global network time, synchronized by a specific message

• Programmable I/O modes

• Maskable interrupts

• Independent of the transmission medium (an external transceiver is assumed)

• Open network architecture

• Multimaster bus

• High immunity to EMI

• Short latency time due to an arbitration scheme for high-priority messages

30.1.3


30.1.3.1

Normal Mode

In normal mode, the module operates receiving and/or transmitting message frames, errors are handled normally, and all the CAN protocol functions are enabled. User and supervisor modes differ in the access to some restricted control registers.

30.1.3.2

Freeze Mode

Freeze mode is entered by setting:

• CANMCR[FRZ], and

• CANMCR[HALT], or by asserting the BKPT signal.

Once entry into freeze mode is requested, the FlexCAN waits until an intermission or idle condition exists on the CAN bus, or until the FlexCAN enters the error passive or bus off state. Once one of these



FlexCAN conditions exists, the FlexCAN waits for the completion of all internal activity such as arbitration, matching, move-in, and move-out. When this happens, the following events occur:

• The FlexCAN stops transmitting/receiving frames.

• The prescaler is disabled, thus halting all CAN bus communication.

• The FlexCAN ignores its Rx pins and drives its Tx pins as recessive.

• The FlexCAN loses synchronization with the CAN bus and the NOTRDY and FRZACK bits in

CANMCR are set.

• The CPU is allowed to read and write the error counter registers (in other modes they are read-only).

After engaging one of the mechanisms to place the FlexCAN in freeze mode, the user must wait for the

FRZACK bit to be set before accessing any other registers in the FlexCAN; otherwise, unpredictable operation may occur. In freeze mode, all memory mapped registers are accessible.

To exit freeze mode, the BKPT line must be negated or the HALT bit in CANMCR must be cleared. Once freeze mode is exited, the FlexCAN will resynchronize with the CAN bus by waiting for 11 consecutive recessive bits before beginning to participate in CAN bus communication.

30.1.3.3

Module Disabled Mode

This mode disables the FlexCAN module; it is entered by setting CANMCR[MDIS]. If the module is disabled during freeze mode, it shuts down the system clocks, sets the LPMACK bit, and clears the

FRZACK bit.

If the module is disabled during transmission or reception, FlexCAN does the following:

• Waits to be in either idle or bus-off state, or else waits for the third bit of intermission and then checks it to be recessive

• Waits for all internal activities such as arbitration, matching, move-in, and move-out to finish

• Ignores its Rx input pin and drives its Tx pin as recessive

• Shuts down the system clocks

The bus interface unit continues to operate, enabling the CPU to access memory-mapped registers, except the free-running timer, the error counter register, and the message buffers, which cannot be accessed when the module is disabled. Exiting from this mode is done by negating the MDIS bit, which will resume the clocks and negate the LPMACK bit.

30.1.3.4

Loop-back Mode

The module enters this mode when the LPB bit in the control register is set. In this mode, FlexCAN performs an internal loop back that can be used for self test operation. The bit stream output of the transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception of its own message. Both transmit and receive interrupts are generated.

30-4



FlexCAN

30.1.3.5

Listen-only Mode

In listen-only mode, transmission is disabled, all error counters are frozen and the module operates in a

CAN error passive mode. Only messages acknowledged by another CAN station will be received. If

FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message. Because the module does not influence the CAN bus in this mode, the device is capable of functioning like a monitor or for automatic bit-rate detection.

30.2


Each FlexCAN module has two I/O signals connected to the external MPU pins: CANTX and CANRX.

CANTX transmits serial data to the CAN bus transceiver, while CANRX receives serial data from the

CAN bus transceiver.

30.3


The FlexCAN module address space is split into 128 bytes starting at the base address, and then an extra

256 bytes starting at the base address +128. The upper 256 are fully used for the message buffer structures,

as described in Section 30.3.9, “Message Buffer Structure.”

Out of the lower 128 bytes, only part is occupied by various registers.

Table 30-1. FlexCAN Memory Map

IPSBAR

OffsetAddres s

FlexCAN

Register

Width

(bits)

Affected by Hard

Reset

Affected by Soft

Reset

0x1C_0FC02_

0000

FlexCAN Module Configuration

Register (CANMCR)

Supervisor-only Access Registers

32 Y Y


32 Y N 0x1C_0FC02_

0004

FlexCAN Control Register

(CANCTRL)

0x1C_0FC02_

0008

Free Running Timer (TIMER)

0xC_0FC02_0

010

Rx Global Mask (RXGMASK)

0x1C_0FC02_

0014

Rx Buffer 14 Mask (RX14MASk)

0x1C_0FC02_

0018

Rx Buffer 15 Mask (RX15MASK)

0x1C_0FC02_

001C

Error Counter Register (ERRCNT)

0x1C_0FC02_

0020

Error and Status Register

(ERRSTAT)

32

32

32

32

32

32

Y

Y

Y

Y

Y

Y

Y

N

N

N

Y

Y


R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

0xD890_000F

0x0000_0000

0x0000_0000

0x1FFF_FFFF

0x1FFF_FFFF

0x1FFF_FFFF

0x0000_0000

0x0000_0000

30.3.1/30-6

30.3.2/30-8

30.3.3/30-10

30.3.4/30-11

30.3.4/30-11

30.3.4/30-11

30.3.6/30-14

30.3.6/30-14



FlexCAN

Table 30-1. FlexCAN Memory Map (continued)

IPSBAR

OffsetAddres s Register

FlexCAN

0x1C_0FC02_

0028

Interrupt Mask Register (IMASK)

0x1C_0FC02_

0030

Interrupt Flag Register (IFLAG)

0x1C_0FC02_

0080

Message Buffers 0–15 (MB0–15)

Width

(bits)

Affected by Hard

Reset

Affected by Soft

Reset


32

32

2048

Y

Y

N

Y

Y

N

R/W 0x0000_0000

30.3.7/30-16

R/W 0x0000_0000

30.3.8/30-16

R/W —

30.3.9/30-17

NOTE

The FlexCAN has no hard-wired protection against invalid bit/field programming within its registers. Specifically, no protection is provided if the programming does not meet CAN protocol requirements.

Programming the FlexCAN control registers is typically done during system initialization, prior to the

FlexCAN becoming synchronized with the CAN bus. The configuration registers can be changed after synchronization by halting the FlexCAN module. This is done when the user sets the CANMCR[HALT] bit. The FlexCAN responds by setting the CANMCR[NOTRDY] bit.

30.3.1

FlexCAN Configuration Register (CANMCR)

CANMCR defines global system configurations, such as the module operation mode and maximum message buffer configuration. Most of the fields in this register can be accessed at any time, except the

MAXMB field, which should only be changed while the module is in freeze mode.

Access: Supervisor read/write IPSBAR

OffsetAd dress:

0x1C_0FC02_0000 (CANMCR)

31 30

R

MDIS FRZ

W

Reset 1 1

29

0

0

28

HALT

1

27

NOT

RDY

1

26

0

0

25

SOFT

RST

24 23

FRZ

ACK SUPV

0 0 1

22

0

0

21

0

0

20

LPM

ACK

1

19

0

0

18

0

0

17

0

0

16

0

0

15

R 0

W

Reset 0

14

0

0

13

0

12

0

11

0

10

0

9

0

8

0

7

0

6

0

5

0

4

0

3 2 1

MAXMB

1 1

0

1 0 0 0 0 0 0 0 0 0 0

Figure 30-4. FlexCAN Configuration Register (CANMCR)

1

30-6



FlexCAN

Table 30-2. CANMCR Field Descriptions


31

MDIS

30

FRZ

Module disable. This bit controls whether FlexCAN is enabled or not. When disabled, FlexCAN shuts down the

FlexCAN clocks that drive the CAN interface and Message Buffer sub-module. This is the only bit in CANMCR not affected by soft reset. See

Section 30.1.3.3, “Module Disabled Mode,”


0 Enable the FlexCAN module, clocks enabled

1 Disable the FlexCAN module, clocks disabled

Freeze mode enable. When set, the FlexCAN can enter freeze mode when the BKPT line is asserted or the HALT

bit is set. Clearing this bit causes the FlexCAN to exit freeze mode. Refer to Section 30.1.3.2, “Freeze Mode,”


0 FlexCAN ignores the BKPT signal and the CANMCR[HALT] bit.

1 FlexCAN module enabled to enter debug mode.


29

28

HALT

Halt FlexCAN. Setting this bit puts the FlexCAN module into freeze mode. It has the same effect as assertion of the

BKPT signal. This bit is set after reset and should be cleared after initializing the message buffers and control registers. FlexCAN message buffer receive and transmit functions are inactive until this bit is cleared. While in

freeze mode, the CPU has write access to the error counter register (ERRCNT), that is otherwise read-only.

0 The FlexCAN operates normally

1 FlexCAN enters freeze mode if FRZ = 1

27

NOTRDY

FlexCAN not ready. This bit indicates that the FlexCAN is either in disable or freeze mode. This bit is read-only and it is cleared once the FlexCAN exits these modes.

0 FlexCAN is either in normal mode, listen-only mode, or loop-back mode.

h1FlexCAN is in disable or freeze mode.


25

SOFTRST

Soft reset. When set, the FlexCAN resets its internal state machines (sequencer, error counters, error flags, and timer) and the host interface registers (CANMCR [except the MDIS bit], TIMER, ERRCNT, ERRSTAT, IMASK, and

IFLAG).

The configuration registers that control the interface with the CAN bus are not changed (CANCTRL, RXGMASK,

RX14MASK, RX15MASK). Message buffers are also not changed. This allows SOFTRST to be used as a debug feature while the system is running.

Since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. The SOFTRST bit remains set while reset is pending and is automatically cleared when reset completes. The user should poll this bit to know when the soft reset has completed.

0 Soft reset cycle completed

1 Soft reset cycle initiated

24

FRZACK

Freeze acknowledge. Indicates that the FlexCAN module has entered freeze mode. The user should poll this bit after freeze mode has been requested, to know when the module has actually entered freeze mode. When freeze mode is exited, this bit is cleared once the FlexCAN prescaler is enabled. This is a read-only bit.

0 The FlexCAN has exited freeze mode and the prescaler is enabled.

1 The FlexCAN has entered freeze mode, and the prescaler is disabled.

23

SUPV

Supervisor/user data space. Places the FlexCAN registers in either supervisor or user data space.

0 Registers with access controlled by the SUPV bit are accessible in either user or supervisor privilege mode.

1 Registers with access controlled by the SUPV bit are restricted to supervisor mode.




FlexCAN

Table 30-2. CANMCR Field Descriptions (continued)


20

LPMACK

Low power mode acknowledge. Indicates that FlexCAN is disabled. Disabled mode cannot be entered until all current transmission or reception processes have finished, so the CPU can poll the LPMACK bit to know when the

FlexCAN has actually entered low power mode. See Section 30.1.3.3, “Module Disabled Mode,”

and Chapter 8,

“Power Management,” for more information. This bit is read-only.

0 FlexCAN not disabled.

1 FlexCAN is in disabled mode.

19–4

3–0

MAXMB


Maximum number of message buffers. Defines the maximum number of message buffers that will take part in the matching and arbitration process. The reset value (0xF) is equivalent to16 message buffer (MB) configuration. This field should be changed only while the module is in freeze mode.

Note:

Maximum MBs in Use = MAXMB + 1

30.3.2

FlexCAN Control Register (CANCTRL)

CANCTRL is defined for specific FlexCAN control features related to the CAN bus, such as bit-rate, programmable sampling point within an Rx bit, loop back mode, listen-only mode, bus off recovery behavior, and interrupt enabling. It also determines the division factor for the clock prescaler. Most of the fields in this register should only be changed while the module is disabled or in freeze mode. Exceptions are the BOFFMSK, ERRMSK, and BOFFREC bits, which can be accessed at any time.


OffsetAd dress:

0x1C_0FC02_0004 (CANCTRL)

30 29 28 27 31

R

W

Reset 0 0 0

PRESDIV

0 0

26

0

25

0

24

0

23

RJW

22

0 0

21 20

PSEG1

19

0 0 0

18

0

17

PSEG2

0

16

0

15

R BOFF

W MSK

Reset 0

14

ERR

MSK

0

13

CLK_

SRC

0

12

LPB

0

11

0

10

0

9

0

8

0

7

SMP

6

BOFF

REC

0

5

TSYN LBUF LOM

0

4

0

3

0 0 0 0 0 0

Figure 30-5. FlexCAN Control Register (CANCTRL)

2 1

PROPSEG

0

0 0 0

30-8



FlexCAN

Table 30-3. CANCTRL Field Descriptions


31–24

PRESDIV

Prescaler division factor. Defines the ratio between the clock source frequency (set by CLK_SRC bit) and the serial clock (S clock) frequency. The S clock period defines the time quantum of the CAN protocol. For the reset value, the S clock frequency is equal to the clock source frequency. The maximum value of this register is 0xFF, that gives a minimum S clock frequency equal to the clock source frequency divided by 256. For more information refer to

Section 30.4.8, “Bit Timing

.”

S clock frequency =

S clock frequency =

Eqn. 30-1

Eqn. 30-2

23–22

RJW

21–19

PSEG1

18–16

PSEG2

Resynchronization jump width. Defines the maximum number of time quanta (one time quantum is equal to the S clock period) that a bit time can be changed by one resynchronization. The valid programmable values are 0 – 3.

Resync jump width = (RJW + 1) time quanta

Phase buffer segment 1. Defines the length of phase buffer segment 1 in the bit time. The valid programmable values are 0 – 7.

Phase buffer segment 1 = (PSEG1 + 1) time quanta

Phase buffer segment 2. Defines the length of phase buffer segment 2 in the bit time. The valid programmable values are 1 – 7.

Phase buffer segment 2 = (PSEG2 + 1) time quanta

15

BOFFMSK

Bus off interrupt mask.

0 Bus off interrupt disabled

1 Bus off interrupt enabled

14

ERRMSK

Error interrupt mask.

0 Error interrupt disabled

1 Error interrupt enabled

13

CLK_SRC

Clock source. Selects the clock source for the CAN interface to be fed to the prescalar. This bit should only be changed while the module is disabled.

0 Clock source is EXTAL

1 Clock source is the internal bus clock, f sys/23

12

LPB

Loop back. Configures FlexCAN to operate in loop-back mode. In this mode, FlexCAN performs an internal loop back that can be used for self test operation. The bit stream output of the transmitter is fed back internally to the receiver input. The Rx CAN input pin is ignored and the Tx CAN output goes to the recessive state (logic 1).

FlexCAN behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. Both transmit and receive interrupts are generated.

0 Loop back disabled

1 Loop back enabled

11–8

7

SMP


Sampling mode. Determines whether the FlexCAN module will sample each received bit one time or three times to determine its value.

0 One sample, taken at the end of phase buffer segment 1, is used to determine the value of the received bit.

1 Three samples are used to determine the value of the received bit. The samples are taken at the normal sample point and at the two preceding periods of the S-clock; a majority rule is used.



FlexCAN

Table 30-3. CANCTRL Field Descriptions (continued)


6

BOFFREC

Bus off recovery mode. Defines how FlexCAN recovers from bus off state. If this bit is cleared, automatic recovering from bus off state occurs according to the CAN Specification 2.0B

. If the bit is set, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is cleared by the user. If the bit is cleared before

128 sequences of 11 recessive bits are detected on the CAN bus, then bus off recovery happens as if the

BOFFREC bit had never been set. If the bit is cleared after 128 sequences of 11 recessive bits occurred, then

FlexCAN will re-synchronize to the bus by waiting for 11 recessive bits before joining the bus. After clearing, the

BOFFREC bit can be set again during bus off, but it will only be effective the next time the module enters bus off.

If BOFFREC was cleared when the module entered bus off, setting it during bus off will not be effective for the current bus off recovery.

0 Automatic recovering from bus off state enabled, according to CAN Spec 2.0B

1 Automatic recovering from bus off state disabled

5

TSYN

Timer synchronize mode. Enables the mechanism that resets the free-running timer each time a message is received in Message Buffer 0. This feature provides the means to synchronize multiple FlexCAN stations with a special “SYNC” message (global network time).

0 Timer synchronization disabled.

1 Timer synchronization enabled.

Note: There can be a bit clock skew of four to five counts between different FlexCAN modules that are using this feature on the same network.

4

LBUF

Lowest buffer transmitted first. Defines the ordering mechanism for message buffer transmission.

0 Message buffer with lowest ID is transmitted first

1 Lowest numbered buffer is transmitted first

3

LOM

Listen-only mode. Configures FlexCAN to operate in listen-only mode. In this mode transmission is disabled, all error counters are frozen, and the module operates in a CAN error passive mode. Only messages acknowledged by another CAN station will be received. If FlexCAN detects a message that has not been acknowledged, it will flag a BIT0 error (without changing the REC), as if it was trying to acknowledge the message.

0 FlexCAN module is in normal active operation; listen-only mode is deactivated

1 FlexCAN module is in listen-only mode operation

2–0

PROPSEG

Propagation segment. Defines the length of the propagation segment in the bit time. The valid programmable values are 0 – 7.

Propagation segment time = (PROPSEG + 1) time-quanta

Note: A time-quantum = 1 S clock period.

30.3.3

FlexCAN Free Running Timer Register (TIMER)

This register represents a 16-bit free running counter that can be read and written to by the CPU. The timer starts from 0x0000 after reset, counts linearly to 0xFFFF, and wraps around.

The timer is clocked by the FlexCAN bit-clock (which defines the baud rate on the CAN bus). During a message transmission/reception, it increments by one for each bit that is received or transmitted. When there is no message on the bus, it counts using the previously programmed baud rate. During freeze mode, the timer is not incremented.

The timer value is captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message.

Writing to the timer is an indirect operation. The data is first written to an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed. All this is transparent to the user, except

30-10



FlexCAN for the fact that the data will take some time to be actually written to the register. If desired, software can poll the register to discover when the data was actually written.

IPSBAR

OffsetAd dress:

0x1C_0FC02_0008 (TIMER) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

TIMER

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 30-6. FlexCAN Timer Register (TIMER)

Table 30-4. TIMER Field Descriptions



15–0

TIMER

Free running timer. Captured at the beginning of the identifier (ID) field of any frame on the CAN bus. This captured value is written into the TIMESTAMP entry in a message buffer after a successful reception or transmission of a message.

30.3.4

Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)

These registers are used as acceptance masks for received frame IDs. Three masks are defined: a global mask (RXGMASK) used for Rx buffers 0–13 and two separate masks for buffers 14 (RX14MASK) and

15 (RX15MASK). The meaning of each mask bit is the following:

MI n bit = 0: The corresponding incoming ID bit is “don’t care”.

MI n bit = 1: The corresponding ID bit is checked against the incoming ID bit, to see if a match exists.

Note that these masks are used both for standard and extended ID formats. The value of the mask registers should not be changed while in normal operation (only while in freeze mode), as locked frames that matched a message buffer (MB) through a mask may be transferred into the MB (upon release) but may no longer match.

Table 30-5. Mask Examples for Normal/Extended Messages

IDE

Extended ID

ID17......................................ID0

Match

MB2-ID

MB3-ID

MB4-ID

MB5-ID

MB14-ID

Rx_Global_Mask

Rx_Msg in

1

Base ID

ID28.................ID18

1 1 1 1 1 1 1 1 0 0 0

1 1 1 1 1 1 1 1 0 0 0

0 0 0 0 0 0 1 1 1 1 1

0 0 0 0 0 0 1 1 1 0 1

1 1 1 1 1 1 1 1 0 0 0

1 1 1 1 1 1 1 1 1 1 0

1 1 1 1 1 1 1 1 0 0 1

0

1

0

1

1

1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 MB3

1



FlexCAN

Table 30-5. Mask Examples for Normal/Extended Messages (continued)

Base ID

ID28.................ID18

IDE

Extended ID

ID17......................................ID0

Rx_Msg in

2

Rx_Msg in

3

Rx_Msg in

4

Rx_Msg in

5

1 1 1 1 1 1 1 1 0 0 1

1 1 1 1 1 1 1 1 0 0 1

0 1 1 1 1 1 1 1 0 0 0

0 1 1 1 1 1 1 1 0 0 0

0

1

0

1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

RX14MASK

Rx_Msg in

6

0 1 1 1 1 1 1 1 1 1 1

1 0 1 1 1 1 1 1 0 0 0 1

1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Rx_Msg in

7

0 1 1 1 1 1 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

2

3

4

5

6

7

1

Match for Extended Format (MB3).

Match for Normal Format. (MB2).

Mismatch for MB3 because of ID0.

Mismatch for MB2 because of ID28.

Mismatch for MB3 because of ID28, Match for MB14 (Uses RX14MASK).

Mismatch for MB14 because of ID27 (Uses RX14MASK).

Match for MB14 (Uses RX14MASK).

Match

MB2

2

3

4

MB14

5

6

MB14

7

OffsetAd dress:

0x1C_0FC02_0010 (RXGMASK)

0x1C_0FC02_0014 (RX14MASK)

0x1C_0FC02_0018 (RX15MASK)


R 0 0 0

W

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

MI

Standard ID

MI

Extended ID

Reset 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Figure 30-7. FlexCAN Rx Mask Registers (RXGMASK, RX14MASK, RX15MASK)

Table 30-6. RX xx MASK Field Descriptions



28–18

MI28–18

Standard ID mask bits. These bits are the same mask bits for the Standard and Extended Formats.

17–0

MI17–0

Extended ID mask bits. These bits are used to mask comparison only in Extended Format.

30.3.5

FlexCAN Error Counter Register (ERRCNT)

This register has two 8-bit fields reflecting the value of two FlexCAN error counters: transmit error counter

(TXECTR) and receive error counter (RXECTR). The rules for increasing and decreasing these counters are described in the CAN protocol and are completely implemented in the FlexCAN module. Both counters are read-only, except in freeze mode, where they can be written by the CPU.

30-12



FlexCAN

Writing to the ERRCNT register while in freeze mode is an indirect operation. The data is first written to an auxiliary register, then an internal request/acknowledge procedure across clock domains is executed.

All this is transparent to the user, except for the fact that the data will take some time to be actually written to the register. If desired, software can poll the register to discover when the data was actually written.

FlexCAN responds to any bus state as described in the protocol, e.g. transmit error-active or error-passive flag, delay its transmission start time (error-passive), and avoid any influence on the bus when in bus off state. The following are the basic rules for FlexCAN bus state transitions:

• If the value of TXECTR or RXECTR increases to be greater than or equal to 128, the FLTCONF field in the error and status register (ERRSTAT) is updated to reflect error-passive state.

• If the FlexCAN state is error-passive, and either TXECTR or RXECTR decrements to a value less than or equal to 127 while the other already satisfies this condition, the ERRSTAT[FLTCONF] field is updated to reflect error-active state.

• If the value of TXECTR increases to be greater than 255, the ERRSTAT[FLTCONF] field is updated to reflect bus off state, and an interrupt may be issued. The value of TXECTR is then reset to zero.

• If FlexCAN is in bus off state, then TXECTR is cascaded together with another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. Hence, TXECTR is reset to zero and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the TXECTR. When TXECTR reaches the value of 128, the

ERRSTAT[FLTCONF] field is updated to be error-active, and both error counters are reset to zero.

At any instance of a dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to zero without affecting the TXECTR value.

• If during system start-up, only one node is operating, then its TXECTR increases in each message it is trying to transmit, as a result of acknowledge errors (indicated by the ERRSTAT[ACKERR] bit). After the transition to error-passive state, the TXECTR does not increment anymore by acknowledge errors. Therefore, the device never goes to the bus off state.

• If the RXECTR increases to a value greater than 127, it is not incremented further, even if more errors are detected while being a receiver. At the next successful message reception, the counter is set to a value between 119 and 127 to resume to error-active state.

IPSBAR

OffsetAd dress:

0x1C_0FC02_001C (ERRCNT) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

RXECTR TXECTR

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 30-8. FlexCAN Error Counter Register (ERRCNT)



FlexCAN

Table 30-7. ERRCNT Field Descriptions



15–8

RXECTR

Receive error counter. Indicates current number of receive errors.

7–0

TXECTR

Transmit error counter. Indicates current number of transmit errors.

30.3.6

FlexCAN Error and Status Register (ERRSTAT)

ERRSTAT reflects various error conditions, some general status of the device, and is the source of three interrupts to the CPU. The reported error conditions (bits 15:10) are those occurred since the last time the

CPU read this register. The read action clears bits 15-10. Bits 9–3 are status bits.

Most bits in this register are read only, except for BOFFINT and ERRINT, which are interrupt flags that

can be cleared by writing 1 to them. Writing 0 has no effect. Refer to Section 30.5.1, “Interrupts.”


OffsetAd dress:

0x1C_0FC02_0020 (CANCTRL)

31

R 0

W

Reset 0

30

0

0

29

0

0

28

0

0

27

0

0

26

0

0

25

0

0

24

0

0

23

0

0

22

0

0

21

0

0

20

0

0

19

0

0

18

0

0

17

0

0

16

0

0

15

R BIT1

ERR

W

Reset 0

14

BIT0

ERR

13

ACK

ERR

0 0

12

CRC

ERR

11

FRM

ERR

10

STF

ERR

9

TX

WRN

8

RX

WRN

7 6

IDLE TXRX

5

FLT

CONF

4

0 0 0 0 0 0 0 0 0

Figure 30-9. FlexCAN Error and Status Register (ERRSTAT)

3

0

0

2

BOFF

INT w1c

0

1

ERR

INT w1c

0

0

0

0

Table 30-8. ERRSTAT Field Descriptions



15

BIT1ERR

Bit1 error. Indicates inconsistency between the transmitted and received bit in a message.

0 No transmit bit error

1 At least one bit sent as recessive was received as dominant

Note: The transmit bit error field is not modified during the arbitration field or the ACK slot bit time of a message, or by a transmitter that detects dominant bits while sending a passive error frame.

14

BIT0ERR

Bit0 error. Indicates inconsistency between the transmitted and received bit in a message.

0 No transmit bit error

1 At least one bit sent as dominant was received as recessive

30-14



FlexCAN

Table 30-8. ERRSTAT Field Descriptions (continued)


13

ACKERR

Acknowledge error. Indicates whether an acknowledgment has been correctly received for a transmitted message.

0 No ACK error was detected since the last read of this register.

1 An ACK error was detected since the last read of this register.

12

CRCERR

Cyclic redundancy check error. Indicates whether or not a CRC error has been detected by the receiver.

0 No CRC error was detected since the last read of this register.

1 A CRC error was detected since the last read of this register.

11

FRMERR

Message form error. Indicates that a form error has been detected by the receiver node, i.e. a fixed-form bit field contains at least one illegal bit.

0 No form error was detected since the last read of this register.

1 A form error was detected since the last read of this register.

10

STFERR

Bit stuff error.

0 No bit stuffing error was detected since the last read of this register.

1 A bit stuffing error was detected since the last read of this register.

9

TXWRN

8

RXWRN

7

IDLE

Transmit error status flag. Reflects the status of the FlexCAN transmit error counter.

0 Transmit error counter

<

96

1 TXErrCounter

≥

96

Receiver error status flag. Reflects the status of the FlexCAN receive error counter.

0 Receive error counter

<

96

1 RxErrCounter

≥

96

Idle status. Indicates when there is activity on the CAN bus.

0 The CAN bus is not idle.

1 The CAN bus is idle.

6

TXRX

Transmit/receive status. Indicates when the FlexCAN module is transmitting or receiving a message. TXRX has no meaning when IDLE = 1.

0 The FlexCAN is receiving a message if IDLE = 0.

1 The FlexCAN is transmitting a message if IDLE = 0.

5–4

FLTCONF

Fault confinement state. Indicates the confinement state of the FlexCAN module, as shown below. If the

CANCTRL[LOM] bit is set, FLTCONF will indicate error-passive. Since the CANCTRL register is not affected by soft reset, the FLTCONF field will not be affected by soft reset if the LOM bit is set.

00 Error active

01 Error passive

1x Bus off


2

BOFFINT

Bus off interrupt. Used to request an interrupt when the FlexCAN enters the bus off state. The user must write a 1 to clear this bit. Writing 0 has no effect.

0 No bus off interrupt requested.

1 This bit is set when the FlexCAN state changes to bus off. If the CANCTRL[BOFFMSK] bit is set an interrupt request is generated. This interrupt is not requested after reset.

1

ERRINT

0

Error interrupt. Indicates that at least one of the ERRSTAT[15:10] bits is set. The user must write a 1 to clear this bit. Writing 0 has no effect.

0 No error interrupt request.

1 At least one of the error bits is set. If the CANCTRL[ERRMSK] bit is set, an interrupt request is generated.




FlexCAN

30.3.7

Interrupt Mask Register (IMASK)

IMASK contains one interrupt mask bit per buffer. It enables the CPU to determine which buffer will generate an interrupt after a successful transmission/reception (that is, when the corresponding IFLAG bit is set).

IPSBAR

OffsetAd dress:

0x1C_0FC02_0028 (IMASK) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BUF n M

W

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 30-10. FlexCAN Interrupt Mask Register (IMASK)

Table 30-9. IMASK Field Descriptions



15–0

BUF n M

Buffer interrupt mask. Enables the respective FlexCAN message buffer (MB0 to MB15) interrupt. These bits allow the CPU to designate which buffers will generate interrupts after successful transmission/reception.

0 The interrupt for the corresponding buffer is disabled.

1 The interrupt for the corresponding buffer is enabled.

Note: Setting or clearing an IMASK bit can assert or negate an interrupt request, if the corresponding IFLAG bit it is set.

30.3.8

Interrupt Flag Register (IFLAG)

IFLAG contains one interrupt flag bit per buffer. Each successful transmission/reception sets the corresponding IFLAG bit and, if the corresponding IMASK bit is set, will generate an interrupt.

The interrupt flag is cleared by writing a 1, while writing 0 has no effect.

IPSBAR

OffsetAd dress:

0x1C_0FC02_0030 (IFLAG) Access: User read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BUF n I

W w1c

Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Figure 30-11. FlexCAN Interrupt Flags Register (IFLAG)

30-16



FlexCAN

Table 30-10. IFLAG Field Descriptions



15–0

BUF n I

Buffer interrupt flag. Indicates a successful transmission/reception for the corresponding message buffer. If the corresponding IMASK bit is set, an interrupt request will be generated. The user must write a 1 to clear an interrupt flag; writing 0 has no effect.

0 No such occurrence.

1 The corresponding buffer has successfully completed transmission or reception.

30.3.9

Message Buffer Structure

The message buffer memory map starts at an offset of 0x80 from the FlexCAN’s base address

(0x1C_0FC02_0000). The 256-byte message buffer space is fully used by the 16 message buffer structures.

Each message buffer consists of a control and status field that configures the message buffer, an identifier field for frame identification, and up to 8 bytes of data.

FlexCAN Base

Address Offset

0x80

0x84

0x88

0x8F

0x90

Control/Status

Identifier

8 byte Data fields

Message Buffer 0

Message Buffer 1

0x9F

0xA0

Message Buffer 2

0xAF

0xB0

Message Buffer 3

0x16F

0x170

Message Buffer 14

Message Buffer 15

0x17F

Figure 30-12. FlexCAN Message Buffer Memory Map



FlexCAN

The message buffer structure used by the FlexCAN module is shown in Figure 30-13 . Both standard and

extended frames used in the CAN Specification Version 2.0, Part B are represented. A standard frame is represented by the 11-bit standard identifier, and an extended frame is represented by the combined 29-bits of the standard identifier (11 bits) and the extended identifier (18 bits).

0x0

0x4

31 30 29 28 27 26 25 24 23

CODE

22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

SRR IDE RTR LENGTH TIME STAMP

Standard ID[28:18] Extended ID[17:0]

0x8

0xC

Data Byte 0

Data Byte 4

Data Byte 1

Data Byte 5

Data Byte 2

Data Byte 6

Data Byte 3

Data Byte 7

Figure 30-13. Message Buffer Structure for Both Extended and Standard Frames

Table 30-11. Message Buffer Field Descriptions



27–24

CODE

Message buffer code. Can be accessed (read or write) by the CPU and by the FlexCAN module itself, as part of the message buffer matching and arbitration process. The encoding is shown in

Section 30.4, “Functional Overview,”

for additional information.

Table 30-12

and Table 30-13

. See

23

22

SRR

21

IDE


Substitute remote request. Fixed recessive bit, used only in extended format. It must be set by the user for transmission (Tx Buffers) and will be stored with the value received on the CAN bus for Rx receiving buffers. It can be received as either recessive or dominant. If FlexCAN receives this bit as dominant, then it is interpreted as arbitration loss.

0 Dominant is not a valid value for transmission in Extended Format frames

1 Recessive value is compulsory for transmission in Extended Format frames

ID extended bit. Identifies whether the frame format is standard or extended.

0 Standard frame format

1 Extended frame format

20

RTR

19–16

LENGTH

Remote transmission request. Used for requesting transmissions of a data frame. If FlexCAN transmits this bit as

1 (recessive) and receives it as 0 (dominant), it is interpreted as arbitration loss. If this bit is transmitted as 0

(dominant), then if it is received as 1 (recessive), the FlexCAN module treats it as bit error. If the value received matches the value transmitted, it is considered as a successful bit transmission.

0 Indicates the current MB has a data frame to be transmitted

1 Indicates the current MB has a remote frame to be transmitted

Length of data in bytes. Indicates the length (in bytes) of the Rx or Tx data; data is located in offset 0x8 through

0xF of the MB space (see

Figure 30-13

). In reception, this field is written by the FlexCAN module, copied from the

DLC (data length code) field of the received frame. DLC is defined by the CAN Specification and refers to the data length of the actual frame before it is copied into the message buffer. In transmission, this field is written by the CPU and is used as the DLC field value of the frame to be transmitted.

When RTR is set, the frame to be transmitted is a remote frame and will be transmitted without the DATA field, regardless of the LENGTH field.

15–-0

TIME

STAMP

Free-running counter time stamp. Stores the value of the free-running timer which is captured when the beginning of the identifier (ID) field appears on the CAN bus.


30-18



FlexCAN

Table 30-11. Message Buffer Field Descriptions (continued)


28–0

ID

Standard frame identifier: In standard frame format, only the 11 most significant bits (28 to 18) are used for frame identification in both receive and transmit cases. The 18 least significant bits are ignored.

Extended frame identifier: In extended frame format, all bits (both the 11 bits of the standard frame identifier and the 18 bits of the extended frame identifier) are used for frame identification in both receive and transmit cases.

31–24,

23–16,

15–8, 7–0

DATA

Data field. Up to eight bytes can be used for a data frame. For Rx frames, the data is stored as it is received from the CAN bus. For Tx frames, the CPU provides the data to be transmitted within the frame.

Table 30-12. Message Buffer Code for Rx Buffers

Rx Code

BEFORE

Rx New Frame

Description

Rx Code

AFTER

Rx New Frame

Comment

0000

0100

0010

INACTIVE: MB is not active.

EMPTY: MB is active and empty.

FULL: MB is full.

—

0010

0010

MB does not participate in the matching process.

MB participates in the matching process. When a frame is received successfully, the code is automatically updated to FULL.

The act of reading the control & status (C/S) word followed by unlocking the MB does not make the code return to EMPTY. It remains FULL. If a new frame is written to the MB after the C/S word was read and the MB was unlocked, the code still remains

FULL.

0110 OVERRUN: A frame was overwritten into a full buffer.

0110

0010

If the MB is FULL and a new frame should be written into this MB before the CPU had time to read it, the

MB is overwritten, and the code is automatically updated to OVERRUN.

If the code indicates OVERRUN but the CPU reads the C/S word and then unlocks the MB, when a new frame is written to the MB, the code returns to FULL.

0110 If the code already indicates OVERRUN, and yet another new frame must be written, the MB will be overwritten again, and the code will remain

OVERRUN.

0XY1

1

BUSY: Flexcan is updating the contents of the MB with a new receive frame.

The CPU should not try to access the MB.

0010

0110

An EMPTY buffer was written with a new frame (XY was 01).

A FULL/OVERRUN buffer was overwritten (XY was

11).

1

Note that for transmit message buffers (see Table 30-13

), the BUSY bit should be ignored upon read.



FlexCAN

MB n [RTR]

X

0

1

0

0

Initial Tx

Code

1000

1100

1100

1010

1110

Table 30-13. Message Buffer Code for Tx Buffers

Code After

Successful

Transmission

—

Description

1000

0100

1010

1010

INACTIVE: Message buffer not ready for transmit and will participate in the arbitration process.

Data frame to be transmitted once, unconditionally. After transmission, the MB automatically returns to the INACTIVE state.

Remote frame to be transmitted unconditionally once, and message buffer becomes an Rx message buffer with the same

ID for data frames.

Transmit a data frame whenever a remote request frame with the same ID is received. This message buffer participates simultaneously in both the matching and arbitration processes.

The matching process compares the ID of the incoming remote request frame with the ID of the MB. If a match occurs, this message buffer is allowed to participate in the current arbitration process and the CODE field is automatically updated to 1110 to allow the MB to participate in future arbitration runs. When the frame is eventually transmitted successfully, the code automatically returns to 1010 to restart the process again.

This is an intermediate code that is automatically written to the message buffer as a result of match to a remote request frame.

The data frame will be transmitted unconditionally once, and then the code will automatically return to 1010. The CPU can also write this code with the same effect.

30.4

Functional Overview

The FlexCAN module is flexible in that each one of its 16 message buffers (MBs) can be assigned either as a transmit buffer or a receive buffer. Each MB, which is up to 8 bytes long, is also assigned an interrupt flag bit that indicates successful completion of either transmission or reception.

An arbitration algorithm decides the prioritization of MBs to be transmitted based on either the message

ID or the MB ordering. A matching algorithm makes it possible to store received frames only into MBs that have the same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed on the MB with a range of IDs on received CAN frames. Data coherency mechanisms are implemented to guarantee data integrity during MB manipulation by the CPU.

Before proceeding with the functional description, an important concept must be explained. A message buffer is said to be active at a given time if it can participate in the matching and arbitration algorithms that

are happening at that time. An Rx MB with a 0000 code is inactive (refer to Table 30-12

). Similarly, a Tx

MB with a 1000 code is inactive (refer to

Table 30-13 ). An MB not programmed with either 0000 or 1000

will be temporarily deactivated (will not participate in the current arbitration/matching run) when the CPU writes to the C/S field of that MB.

30-20



FlexCAN

30.4.1

Transmit Process

The CPU prepares or changes an MB for transmission by writing the following:

1. Control/status word to hold Tx MB inactive (CODE = 1000)

2. ID word

3. Data bytes

4. Control/status word (active CODE, LENGTH)

NOTE

The first and last steps are mandatory.

The first write to the control/status word is important in case there was pending reception or transmission.

The write operation immediately deactivates the MB, removing it from any currently ongoing arbitration or ID matching processes, giving time for the CPU to program the rest of the MB (see

Section 30.4.5.2,

“Message Buffer Deactivation”

). Once the MB is activated in the fourth step, it will participate in the arbitration process and eventually be transmitted according to its priority. At the end of the successful transmission, the value of the free running timer (TIMER) is written into the message buffer’s time stamp field, the code field in the control and status word is updated, a status flag is set in the IFLAG register, and an interrupt is generated if allowed by the corresponding IMASK register bit. The new code field after transmission depends on the code that was used to activate the MB in step four (see

Table 30-13 ).

30.4.2

Arbitration Process

The arbitration process is an algorithm executed by the message buffer management (MBM) that scans the entire MB memory looking for the highest priority message to be transmitted. All MBs programmed as transmit buffers will be scanned to find the lowest ID or the lowest MB number, depending on the

CANCTRL[LBUF] bit.

NOTE

If CANCTRL[LBUF] is cleared, the arbitration considers not only the ID, but also the RTR and IDE bits placed inside the ID at the same positions they are transmitted in the CAN frame.

The arbitration process is triggered in the following events:

• During the CRC field of the CAN frame

• During the error delimiter field of the CAN frame

• During intermission, if the winner MB defined in a previous arbitration was deactivated, or if there was no MB to transmit, but the CPU wrote to the C/S word of any MB after the previous arbitration finished

• When MBM is in idle or bus off state and the CPU writes to the C/S word of any MB

• Upon leaving freeze mode

Once the highest priority MB is selected, it is transferred to a temporary storage space called serial message buffer (SMB), which has the same structure as a normal MB but is not user accessible. This operation is called ‘move-out.’ At the first opportunity window on the CAN bus, the message on the SMB



FlexCAN is transmitted according to the CAN protocol rules. FlexCAN transmits up to 8 data bytes, even if the data

length code (DLC) value is bigger. Refer to Section 30.4.5.1, “Serial Message Buffers (SMBs),”

for more information on serial message buffers.

30.4.3

Receive Process

The CPU prepares or changes an MB for frame reception by writing the following:

1. Control/status word to hold Rx MB inactive (CODE = 0000)

2. ID word

3. Control/status word to mark the Rx MB as active and empty (CODE = 1000)

NOTE

The first and last steps are mandatory.

The first write to the control/status word is important in case there was a pending reception or transmission.

The write operation immediately deactivates the MB, removing it from any currently ongoing arbitration or matching process, giving time for the CPU to program the rest of the MB. Once the MB is activated in the third step, it will be able to receive CAN frames that match the programmed ID. At the end of a successful reception, the value of the free running timer (TIMER) is written into the time stamp field, the received ID, data (8 bytes at most) and length fields are stored, the CODE field in the control and status word is updated (see

Table 30-12

), and a status flag is set in the IFLAG register and an interrupt is generated if allowed by the corresponding IMASK bit.

The CPU should read a receive frame from its MB by reading the following:

1. Control/status word (mandatory—activates internal lock for this buffer)

2. ID (optional—needed only if a mask was used)

3. Data field words

4. Free-running timer (Releases internal lock —optional)

Upon reading the control and status word, if the BUSY bit is set in the CODE field, then the CPU should defer the access to the MB until this bit is negated. Reading the free running timer is not mandatory. If not executed the MB remains locked, unless the CPU reads the C/S word of another MB. Note that only a single MB is locked at a time. The only mandatory CPU read operation is the one on the control and status word to assure data coherency.

The CPU should synchronize to frame reception by an IFLAG bit for the specific MB (see Section 30.3.8,

“Interrupt Flag Register (IFLAG)”

), and not by the control/status word CODE field for that MB. Polling the CODE field does not work because once a frame was received and the CPU services the MB (by reading the C/S word followed by unlocking the MB), the CODE field will not return to EMPTY. It will

remain FULL, as explained in Table 30-12

. If the CPU tries to workaround this behavior by writing to the

C/S word to force an EMPTY code after reading the MB, the MB is actually deactivated from any currently ongoing matching process. As a result, a newly received frame matching the ID of that MB may be lost.

In summary, never do polling by directly reading the C/S word of the MBs. Instead, read the IFLAG register.

30-22



FlexCAN

Note that the received identifier field is always stored in the matching MB, thus the contents of the ID field in an MB may change if the match was due to masking.

30.4.3.1

Self-Received Frames

Self-received frames are frames that are sent by the FlexCAN and received by itself. The FlexCAN sends a frame externally through the physical layer onto the CAN bus, and if the ID of the frame matches the ID of the FlexCAN MB, then the frame will be received by the FlexCAN. Such a frame is a self-received frame. Note that FlexCAN does not receive frames transmitted by itself if another device on the CAN bus has an ID that matches the FlexCAN Rx MB ID.

30.4.4

Matching Process

The matching process is an algorithm that scans the entire MB memory looking for Rx MBs programmed with the same ID as the one received from the CAN bus. Only MBs programmed to receive will participate in the matching process for received frames.

While the ID, DLC and data fields are retrieved from the CAN bus, they are stored temporarily in the serial message buffer (

Section 30.4.5.1, “Serial Message Buffers (SMBs)”

). The matching process takes place during the CRC field. If a matching ID is found in one of the MBs, the contents of the SMB will be transferred to the matched MB during the sixth bit of the end-of-frame field of the CAN protocol. This operation is called ‘move-in.’ If any protocol error (CRC, ACK, etc.) is detected, than the move-in operation does not happen.

An MB with a matching ID is free to receive a new frame if the MB is not locked (see

Section 30.4.5.3,

“Locking and Releasing Message Buffers”

). The CODE field is either EMPTY, FULL, or OVERRUN but the CPU has already serviced the MB (read the C/S word and then unlocked the MB).

Matching to a range of IDs is possible by using ID acceptance masks (RXGMASK, RX14MASK, and

RX15MASK). During the matching algorithm, if a mask bit is asserted, then the corresponding ID bit is compared. If the mask bit is negated, the corresponding ID bit is ‘don’t care.’

30.4.5

Message Buffer Handling

In order to maintain data coherency and FlexCAN proper operation, the CPU must obey the rules described

in Section 30.4.1, “Transmit Process”

and Section 30.4.3, “Receive Process.”

Any form of CPU accessing a MB structure within FlexCAN other than those specified may cause FlexCAN to behave in an unpredictable way.

30.4.5.1

Serial Message Buffers (SMBs)

To allow double buffering of messages, the FlexCAN has two shadow buffers called serial message buffers. These two buffers are used by the FlexCAN for buffering both received messages and messages to be transmitted. Only one SMB is active at a time, and its function depends upon the operation of the

FlexCAN at that time. At no time does the user have access to or visibility of these two buffers.



FlexCAN

30.4.5.2

Message Buffer Deactivation

If the CPU wants to change the function of an active MB, the recommended procedure is to put the module into freeze mode and then change the CODE field of that MB. This is a safe procedure because the

FlexCAN waits for pending CAN bus and MB moving activities to finish before entering freeze mode.

Nevertheless, a mechanism is provided to maintain data coherence when the CPU writes to the control and status word of active MBs out of freeze mode.

Any CPU write access to the C/S word of an MB causes that MB to be excluded from the transmit or receive processes during the current matching or arbitration round. This mechanism is called MB deactivation. It is temporary, affecting only for the current match/arbitration round.

The purpose of deactivation is data coherency. The match/arbitration process scans the MBs to decide which MB to transmit or receive. If the CPU updates the MB in the middle of a match or arbitration process, the data of that MB may no longer be coherent; therefore, that MB is deactivated.

Even with the coherence mechanism described above, writing to the C/S word of active MBs when not in freeze mode may produce undesirable results. Examples are:

• Matching and arbitration are one-pass processes. If MBs are deactivated after they are scanned, no re-evaluation is done to determine a new match/winner. If an Rx MB with a matching ID is deactivated during the matching process after it was scanned, then this MB is marked as invalid to receive the frame, and FlexCAN will keep looking for another matching MB within the ones it has not scanned yet. If it can not find one, then the message will be lost. Suppose, for example, that two

MBs have a matching ID to a received frame, and the user deactivated the first matching MB after

FlexCAN has scanned the second. The received frame will be lost even if the second matching MB was free to receive.

• If a Tx MB containing the lowest ID is deactivated after the FlexCAN has scanned it, then the

FlexCAN will look for another winner within the MBs that it has not yet scanned. Therefore, it may transmit an MB that may not have the lowest ID at the time because a lower ID might be present that it had already scanned before the deactivation.

• There is a point in time until which the deactivation of a Tx MB causes it not to be transmitted (end of move-out). After this point, it is transmitted, but no interrupt is issued and the CODE field is not updated.

30.4.5.3

Locking and Releasing Message Buffers

Besides message buffer deactivation, the lock/release/busy mechanism is designed to guarantee data coherency during the receive process. The following examples demonstrate how the lock/release/busy mechanism will affect FlexCAN operation:

1. Reading a control/status word of a message buffer triggers a lock for that message buffer. A new received message frame that matches the message buffer cannot be written into this message buffer while it is locked.

2. To release a locked message buffer, the CPU either locks another message buffer (by reading its control/status word) or globally releases any locked message buffer (by reading the free-running timer).

30-24



FlexCAN

3. If a receive frame with a matching ID is received during the time the message buffer is locked, the receive frame will not be immediately transferred into that message buffer, but will remain in the

SMB. There is no indication when this occurs.

4. When a locked message buffer is released, if a frame with a matching identifier exists within the

SMB, then this frame will be transferred to the matching message buffer.

5. If two or more receive frames with matching IDs are received while a message buffer with a matching ID is locked, the last received frame with that ID is kept within the serial message buffer, while all preceding ones are lost. There is no indication of lost messages when this occurs.

6. If the user reads the control/status word of a receive message buffer while a frame is being transferred from a serial message buffer, the BUSY code will be indicated. The user should wait until this code is cleared before continuing to read from the message buffer to ensure data coherency. In this situation, the read of the control/status word will not lock the message buffer.

Polling the control/status word of a receive message buffer can lock it, preventing a message from being transferred into that buffer. If the control/status word of a receive message buffer is read, it should then be followed by a read of the control/status word of another buffer, or by reading the free-running timer, to ensure that the locked buffer is unlocked.

NOTE

Deactivation takes precedence over locking. If the CPU deactivates a locked

Rx MB, then its lock status is negated, and the MB is marked as invalid for the current matching round. Any pending message on the SMB will not be transferred to the MB anymore.

30.4.6

CAN Protocol Related Frames

30.4.6.1

Remote Frames

The remote frame is a message frame that is transmitted to request a data frame. The FlexCAN can be configured to transmit a data frame automatically in response to a remote frame, or to transmit a remote frame and then wait for the responding data frame to be received.

When transmitting a remote frame, the user initializes a message buffer as a transmit message buffer with the RTR bit set. Once this remote frame is transmitted successfully, the transmit message buffer automatically becomes a receive message buffer, with the same ID as the remote frame that was transmitted.

When a remote frame is received by the FlexCAN, the remote frame ID is compared to the IDs of all transmit message buffers programmed with a CODE of 1010. If there is an exact matching ID, the data frame in that message buffer is transmitted. If the RTR bit in the matching transmit message buffer is set, the FlexCAN will transmit a remote frame as a response.

A received remote frame is not stored in a receive message buffer. It is only used to trigger the automatic transmission of a frame in response. The mask registers are not used in remote frame ID matching. All ID bits (except RTR) of the incoming received frame must match for the remote frame to trigger a response transmission. The matching message buffer immediately enters the internal arbitration process, but is



FlexCAN considered as a normal Tx MB, with no higher priority. The data length of this frame is independent of the data length code (DLC) field in the remote frame that initiated its transmission.

30.4.6.2

Overload Frames

Overload frame transmissions are not initiated by the FlexCAN unless certain conditions are detected on the CAN bus. These conditions include detection of a dominant bit in the following:

• First or second bit of intermission

• Seventh (last) bit of the end-of-frame (EOF) field in receive frames

• Eighth (last) bit of the error frame delimiter or overload frame delimiter

30.4.7

Time Stamp

The value of TIMER is sampled at the beginning of the identifier field on the CAN bus. For a message being received, the time stamp will be stored in the TIMESTAMP entry of the receive message buffer at the time the message is written into that buffer. For a message being transmitted, the TIMESTAMP entry will be written into the transmit message buffer once the transmission has completed successfully.

The free-running timer can optionally be reset upon the reception of a frame into message buffer 0. This feature allows network time synchronization to be performed. See the CANCTRL[TSYN] bit.

30.4.8

Bit Timing

The FlexCAN module CANCTRL register configures the bit timing parameters required by the CAN protocol. The CLK_SRC, PRESDIV, RJW, PSEG1, PSEG2, and the PROPSEG fields allow the user to configure the bit timing parameters.

The CANCTRL[CLK_SRC] bit defines whether the module uses the internal bus clock or the output of the crystal oscillator via the EXTAL pin. The crystal oscillator clock should be selected whenever a tight tolerance (up to 0.1%) is required for the CAN bus timing. The crystal oscillator clock has better jitter performance than PLL generated clocks. The value of this bit should not be changed, unless the module is in disable mode (CANMCR[MDIS] bit is set)

The PRESDIV field controls a prescaler that generates the serial clock (S-clock), whose period defines the time quantum used to compose the CAN waveform. A time quantum is the atomic unit of time handled by the CAN engine.

CANCTRL[CLK_SRC]

Internal Bus Clock

(f sys/23

)

1

Prescaler

(1 .. 256)

Oscillator Clock (EXTAL)

0

Figure 30-14. CAN Engine Clocking Scheme f

Tq

=

( f sys/2

or EXTAL

PRESDIV + 1 )

S clock

Eqn. 30-3

30-26



FlexCAN f

Tq

=

A bit time is subdivided into three segments f

(

1

or EXTAL

PRESDIV + 1

(see

)

Figure 30-15 and Table 30-14

):

Eqn. 30-4

• SYNC_SEG: Has a fixed length of one time quantum. Signal edges are expected to happen within this section.

• Time Segment 1: Includes the propagation segment and the phase segment 1 of the CAN standard.

It can be programmed by setting the PROPSEG and the PSEG1 fields of the CANCTRL register so that their sum (plus 2) is in the range of 4 to 16 time quanta.

• Time Segment 2: Represents the phase segment 2 of the CAN standard. It can be programmed by setting the PSEG2 field of the CANCTRL register (plus 1) to be 2 to 8 time quanta long.

Bit Rate = f

(number of Time Quanta)

Eqn. 30-5

NRZ Signal

SYNC_SEG

1

Time Segment 1

(PROP_SEG + PSEG1 + 2)

4 ... 16

8 ... 25 Time Quanta

= 1 Bit Time

Time Segment 2

(PSEG2 + 1)

2 ... 8

Transmit Point Sample Point

(single or triple sampling)

Figure 30-15. Segments within the Bit Time

Table 30-14. Time Segment Syntax

Syntax Description

SYNC_SEG

Transmit Point

Sample Point

System expects transitions to occur on the bus during this period.

A node in transmit mode transfers a new value to the CAN bus at this point.

A node samples the bus at this point. If the three samples per bit option is selected, then this point marks the position of the third sample.

Table 30-15

gives an overview of the CAN compliant segment settings and the related parameter values.

1. For further explanation of the underlying concepts please refer to ISO/DIS 11519 – 1, Section 10.3. Reference also the Bosch

CAN 2.0A/B protocol specification dated September 1991 for bit timing.



FlexCAN

NOTE

It is the user’s responsibility to ensure the bit time settings are in compliance with the CAN standard. For bit time calculations, use an IPT (Information

Processing Time) of 2, which is the value implemented in the FlexCAN module

Table 30-15. CAN Standard Compliant Bit Time Segment Settings

Time Segment 1

5 .. 10

4 .. 11

5 .. 12

6 .. 13

7 .. 14

8 .. 15

9 .. 16

Time Segment 2

6

7

8

4

5

2

3

Re-synchronization

Jump Width

1 .. 2

1 .. 3

1 .. 4

1 .. 4

1 .. 4

1 .. 4

1 .. 4

30.5

FlexCAN Initialization Sequence

Initialization of the FlexCAN includes the initial configuration of the message buffers and configuration of the CAN communication parameters following a reset, as well as any reconfiguration that may be required during operation. The FlexCAN module may be reset in three ways:

• Device level hard reset—resets all memory mapped registers asynchronously

• Device level soft reset—resets some of the memory mapped registers synchronously (refer to

Table 30-1

to see which registers are affected by soft reset)

• CANMCR[SOFT_RST] bit—has the same effect as the device level soft reset

Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. Therefore, it may take some time to fully propagate its effects. The CANMCR[SOFT_RST] bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. Also, soft reset can not be applied while clocks are shut down in any of the low power modes.

The low power mode should be exited and the clocks resumed before applying soft reset.

The clock source, CANCTRL[CLK_SRC], should be selected while the module is in disable mode. After the clock source is selected and the module is enabled (CANMCR[MDIS] bit cleared), the FlexCAN automatically enters freeze mode. In freeze mode, the FlexCAN is un-synchronized to the CAN bus, the

CANMCR register’s HALT and FRZ bits are set, the internal state machines are disabled, and the

CANMCR register’s FRZ_ACK and NOT_RDY bits are set. The CANTX pin is in recessive state and the

FlexCAN does not initiate any transmission or reception of CAN frames. Note that the message buffers are not affected by reset, so they are not automatically initialized.

30-28



FlexCAN

For any configuration change/initialization, the FlexCAN must be in freeze mode (see Section 30.1.3.2,

“Freeze Mode”

). The following is a generic initialization sequence applicable to the FlexCAN module:

1. Initialize all operation modes in the CANCTRL register.

a) Initialize the bit timing parameters PROPSEG, PSEGS1, PSEG2, and RJW.

b) Select the S-clock rate by programming the PRESDIV field.

c) Select the internal arbitration mode via the LBUF bit.

2. Initialize message buffers.

a) The control/status word of all message buffers must be written as either an active or inactive message buffer.

b) All other entries in each message buffer should be initialized as required.

3. Initialize RXGMASK, RX14MASK, and RX15MASK registers for acceptance mask as needed.

4. Initialize FlexCAN interrupt handler.

a) Initialize the interrupt controller registers for any needed interrupts. See Chapter 14, “Interrupt

Controller Modules,” for more information.

b) Set the required mask bits in the IMASK register (for all message buffer interrupts) and the

CANCTRL (for bus off and error interrupts).

5. Clear the CANMCR[HALT] bit. At this point, the FlexCAN will attempt to synchronize with the

CAN bus.

30.5.1

Interrupts

There are three interrupt sources for the FlexCAN module. A combined interrupt for all 16 MBs is generated by combining all the interrupt sources from MBs. This interrupt gets generated when any of the

16 MB interrupt sources generates a interrupt. In this case, the CPU must read the IFLAG register to determine which MB caused the interrupt. The other two interrupt sources (bus off and error) act in the same way, and are located in the ERRSTAT register. The bus off and error interrupt mask bits are located in the CANCTRL register.



FlexCAN

30-30



Chapter 31

Debug Module

31.1

Introduction

This chapter describes the Revision B+ enhanced hardware debug module.

31.1.1

Overview

The debug module is shown in

Figure 31-1

.

ColdFire CPU Core

High-speed core bus

(f sys

)

Debug Module

Control

BKPT

Trace Port

PST[3:0], DDATA[3:0]

PSTCLK

Communication Port

DSCLK, DSI, DSO

Figure 31-1. Processor/Debug Module Interface

Depending upon the package, some devices contain only the ALLPST signal and do not have the PST[3:0] and DDATA[3:0] signals. ALLPST is a logical ‘AND’ of the PST[3:0] signals, and when asserted reflects that the core is halted.

Debug support is divided into three areas:

• Real-time trace support—The ability to determine the dynamic execution path through an application is fundamental for debugging. The ColdFire solution implements an 8-bit parallel output bus that reports processor execution status and data to an external emulator system. See

Section 31.3, “Real-Time Trace Support .”

• Background debug mode (BDM)—Provides low-level debugging in the ColdFire processor complex. In BDM, the processor complex is halted and a variety of commands can be sent to the processor to access memory, registers, and peripherals. The external emulator uses a three-pin, serial, full-duplex communication port. See

Section 31.5, “Background Debug Mode (BDM)

,” and

Section 31.4, “Memory Map/Register Definition .”

• Real-time debug support—BDM requires the processor to be halted, which many real-time embedded applications cannot do. External development systems can access memory because the hardware supports concurrent operation of the processor and BDM-initiated commands. Debug interrupts let real-time systems execute a unique service routine that can quickly save the contents



Preliminary

31-1

Debug Module of key registers and variables and return the system to normal operation. See

Section 31.6,

“Real-Time Debug Support

.

31.1.1.1

The New Debug Module Hardware (Rev. B+)

The revision B+ debug module features a small enhancement over revision B: the addition of three PC breakpoint registers (PCBR1–3). These new registers are mapped to DRc[3:0] addresses 0x18, 0x1A, and

0x1B. Additional PC breakpoints enable software debugging. However, there are no masking registers associated with these new registers.

31.1.1.2

Enhancements over Revision A

The new debug hardware also contains the same enhancements that revision B has over revision A, while maintaining backwards compatibility with revision A. These enhancements are discussed below.

The revision B/B+ implementation has added registers that eliminate restrictions between BDM commands and the use of the hardware breakpoint logic. In some cases, the additional hardware is not program-visible; in other cases, there have been extensions to the debug module programming model.

The register containing the BDM memory address is not a program-visible resource. Rather, it is a register loaded automatically during the execution of a BDM command. In the Rev. B design, the execution of a

BDM command does not affect the hardware breakpoint logic unless those registers are specifically accessed.

The other register added to the debug module programming model is the BDM address attribute register

(BAAR). The BAAR is mapped to a DRc[3:0] address of 0x05. This 8-bit register is equivalent in format

of the low-order byte of the AATR register (See Section 31.4.3, “BDM Address Attribute (BAAR)”

). This register specifies the memory space attributes associated with all BDM memory-referencing commands.

Additionally, a bit was added to the CSR register (CSR[BKD]) that configures the debug module to assert or not assert an interrupt to the processor when the BKPT signal is asserted. See

Section 31.4.2,

“Configuration/Status Register (CSR).”

The level 1 and level 2 triggers are also configurable to trigger on either an AND or an OR condition. The revision A debug module only triggers on an AND condition.

31.2

E

xternal Signal Description

Table 31-1

describes debug module signals. All ColdFire debug signals are unidirectional and related to a rising edge of the processor’s clock signal. The standard 26-pin debug connector is shown in

Section 31.8,

“Freescale-Recommended BDM Pinout .”

31-2



Preliminary

Debug Module

Table 31-1. Debug Module Signals


Development Serial

Clock (DSCLK)

Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on two consecutive rising PSTCLK edges.) Clocks the serial communication port to the debug module during packet transfers. Maximum frequency is 1/5 the processor status clock (PSTCLK) speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

Development Serial

Input (DSI)

Internally synchronized input that provides data input for the serial communication port to the debug module.

Development Serial

Output (DSO)

Provides serial output communication for debug module responses. DSO is registered internally.

Breakpoint (BKPT) Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes. Halt status is reflected on processor status signals

(PST[3:0]) as the value 0xF. Also, in Rev B and B+ if the CSR[BKD] bit is set, the assertion of the

BKPT signal will generate a debug interrupt exception to the processor.

Debug Data

(DDATA[3:0])

These output signals display the register breakpoint status as a default, or optionally, captured address and operand values. The capturing of data values is controlled by the setting of the CSR.

Additionally, execution of the WDDATA instruction by the processor captures operands which are displayed on DDATA. These signals are updated each processor cycle. These signals are not implemented on packages containing fewer than 100 pins.

Processor Status

(PST[3:0])

All Processor

Status Outputs

(ALLPST)

These output signals report the processor status.

Table 31-2 shows the encoding of these

signals. These outputs indicate the current status of the processor pipeline and, as a result, are not related to the current bus transfer. The PST value is updated each processor cycle. These signals are not implemented on packages containing fewer than 100 pins.

ALLPST is a logical ‘AND’ of the four PST signals is provided on all packages. PST[3:0] and

DDATA[3:0] are not available on the low cost (less than 100 pin) packages. When asserted, reflects that the core is halted.

Figure 31-2

shows PSTCLK timing with respect to PST and DDATA.

PSTCLK

PST or DDATA

Figure 31-2. PSTCLK Timing

31.3

Real-Time Trace Support

Real-time trace, which defines the dynamic execution path, is a fundamental debug function. The ColdFire solution is to include a parallel output port providing encoded processor status and data to an external development system. This port is partitioned into two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and the other allows operand data to be displayed (debug data , DDATA).

The processor status may not be related to the current bus transfer.

External development systems can use PST outputs with an external image of the program to completely track the dynamic execution path. This tracking is complicated by any change in flow, where branch target



Preliminary

31-3

Debug Module address calculation is based on the contents of a program-visible register (variant addressing). DDATA outputs can be configured to display the target address of such instructions in sequential nibble increments across multiple processor clock cycles, as described in

Section 31.3.1, “Begin Execution of Taken Branch

(PST = 0x5)

.” Two 32-bit storage elements form a FIFO buffer connecting the processor’s high-speed local bus to the external development system through PST[3:0] and DDATA[3:0]. The buffer captures branch target addresses and certain data values for eventual display on the DDATA port, one nibble at a time starting with the least significant bit (lsb).

Execution speeds affected only when both storage elements contain valid data to be dumped to the DDATA port. The core stalls until one FIFO entry is available.

Table 31-2

shows the encoding of these signals.

Table 31-2. Processor Status Encoding

PST[3:0]

Definition

Hex Binary

0x0 0000 Continue execution. Many instructions execute in one processor cycle. If an instruction requires more processor clock cycles, subsequent clock cycles are indicated by driving PST outputs with this encoding.

0x1 0001 Begin execution of one instruction. For most instructions, this encoding signals the first processor clock cycle of an instruction’s execution. Certain change-of-flow opcodes, plus the PULSE and WDDATA instructions, generate different encodings.

0x2 0010 Reserved

0x3 0011 Entry into user-mode. Signaled after execution of the instruction that caused the ColdFire processor to enter user mode.

0x4 0100 Begin execution of PULSE and WDDATA instructions. PULSE defines logic analyzer triggers for debug and/or performance analysis. WDDATA lets the core write any operand (byte, word, or longword) directly to the DDATA port, independent of debug module configuration. When WDDATA is executed, a value of 0x4 is signaled on the PST port, followed by the appropriate marker, and then the data transfer on the DDATA port. Transfer length depends on the WDDATA operand size.

0x5 0101 Begin execution of taken branch. For some opcodes, a branch target address may be displayed on

DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, indicated by the PST marker value preceding the DDATA nibble that begins the data output. See

Section 31.3.1, “Begin Execution of Taken Branch (PST = 0x5).”

Also indicates that the SYNC_PC command has been issued.

0x6 0110 Reserved

0x7 0111 Begin execution of return from exception (RTE) instruction.

0x8–

0xB

1000–

1011

Indicates the number of bytes to be displayed on the DDATA port on subsequent processor clock cycles. The value is driven onto the PST port one PSTCLK cycle before the data is displayed on

DDATA.

0x8 Begin 1-byte transfer on DDATA.

0x9 Begin 2-byte transfer on DDATA.

0xA Begin 3-byte transfer on DDATA.

0xB Begin 4-byte transfer on DDATA.

0xC 1100 Exception processing. Exceptions that enter emulation mode (debug interrupt or optionally trace) generate a different encoding, as described below. Because the 0xC encoding defines a multiple-cycle mode, PST outputs are driven with 0xC until exception processing completes.

31-4



Preliminary

Debug Module

Table 31-2. Processor Status Encoding (continued)

PST[3:0]

Definition

Hex Binary

0xD 1101 Entry into emulator mode.

Displayed during emulation mode (debug interrupt or optionally trace).

Because this encoding defines a multiple-cycle mode, PST outputs are driven with 0xD until exception processing completes.

0xE 1110 Processor is stopped. Appears in multiple-cycle format when the processor executes a STOP instruction. The ColdFire processor remains stopped until an interrupt occurs, thus PST outputs display 0xE until the stopped mode is exited

.

0xF 1111 Processor is halted. Because this encoding defines a multiple-cycle mode, the PST outputs display

0xF until the processor is restarted or reset. (see Section 31.5.1, “CPU Halt ”)

31.3.1

Begin Execution of Taken Branch (PST = 0x5)

PST is 0x5 when a taken branch is executed. For some opcodes, a branch target address may be displayed on DDATA depending on the CSR settings. CSR also controls the number of address bytes displayed, which is indicated by the PST marker value immediately preceding the DDATA nibble that begins the data output.

Bytes are displayed in least-to-most-significant order. The processor captures only those target addresses associated with taken branches which use a variant addressing mode; that is, RTE and RTS instructions,

JMP and JSR instructions using address register indirect or indexed addressing modes, and all exception vectors.

The simplest example of a branch instruction using a variant address is the compiled code for a C language case statement. Typically, the evaluation of this statement uses the variable of an expression as an index into a table of offsets, where each offset points to a unique case within the structure. For such change-of-flow operations, the ColdFire processor uses the debug pins to output the following sequence of information on successive processor clock cycles:

1. Use PST (0x5) to identify that a taken branch was executed.

2. Using the PST pins, optionally signal the target address to be displayed sequentially on the DDATA pins. Encodings 0x9–0xB identify the number of bytes displayed .

3. The new target address is optionally available on subsequent cycles using the DDATA port. The number of bytes of the target address displayed on this port is configurable (2, 3, or 4 bytes).

Another example of a variant branch instruction would be a JMP (A0) instruction.

Figure 31-3

shows the

PST and DDATA outputs that indicate a JMP (A0) execution (assuming the CSR was programmed to display the lower 2 bytes of an address).



Preliminary

31-5

Debug Module

PSTCLK

PST 0x5 0x9 default default default default

DDATA 0x0 0x0 A[3:0] A[7:4] A[11:8] A[15:12]

Figure 31-3. Example JMP Instruction Output on PST/DDATA

PST 0x5 indicates a taken branch and the marker value 0x9 indicates a 2-byte address. Thus, the subsequent 4 nibbles of DDATA display the lower 2 bytes of address register A0 in least-to-most-significant nibble order. The PST output after the JMP instruction completes depends on the target instruction. The PST can continue with the next instruction before the address has completely displayed on DDATA because of the DDATA FIFO. If the FIFO is full and the next instruction has captured values to display on DDATA, the pipeline stalls (PST = 0x0) until space is available in the FIFO.

31.4


In addition to the existing BDM commands that provide access to the processor’s registers and the memory subsystem, the debug module contains 19 registers to support the required functionality. These registers are also accessible from the processor’s supervisor programming model by executing the WDEBUG instruction (write only). Thus, the breakpoint hardware in the debug module can be written by the external development system using the debug serial interface or by the operating system running on the processor core. Software is responsible for guaranteeing that accesses to these resources are serialized and logically consistent. Hardware provides a locking mechanism in the CSR to allow the external development system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]). BDM commands must not be issued if the ColdFire processor is using the WDEBUG instruction to access debug module registers, or the resulting behavior is undefined, while DSCLK is quiescent.

These registers, shown in Table 31-3 , are treated as 32-bit quantities, regardless of the number of

implemented bits. These registers are also accessed through the BDM port by the commands, WDMREG and RDMREG , described in

Section 31.5.3.3, “Command Set Descriptions .” These commands contain a

5-bit field, DRc, that specifies the register, as shown in

Table 31-3 .

Table 31-3. Debug Module Memory Map

DRc[4–0]

0x00

0x05

0x06

0x07

0x08

0x09

Register

Configuration/Status Register (CSR)

BDM Address Attribute Register (BAAR)

Address Attribute Trigger Register (AATR)

Trigger Definition Register (TDR)

PC Breakpoint Register 0 (PBR0)

PC Breakpoint Mask Register (PBMR)

Width

(bits)

32

32

1

32

1

32

32

32


See Note 0x0090_0000

31.4.2/31-7

See Note 0x05

31.4.3/31-9

See Note 0x0005

31.4.4/31-10

See Note 0x0000_0000

31.4.5/31-12

See Note Undefined

See Note Undefined

31.4.6/31-15

31.4.6/31-15

31-6



Preliminary

Debug Module

Table 31-3. Debug Module Memory Map (continued)

1

DRc[4–0] Register

Width

(bits)


0x0C

0x0D

0x0E

0x0F

0x18

0x1A

0x1B

Address High Breakpoint Register (ABHR)

Address Low Breakpoint Register (ABLR)

Data Breakpoint Register (DBR)

Data Breakpoint Mask Register (DBMR)




32

32

32

32

32

32

32

See Note

See Note

See Note

See Note

See Note

See Note

See Note

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Undefined

Each debug register is accessed as a 32-bit register; reserved fields are not used (don’t care).

Section/Page

31.4.7/31-15

31.4.7/31-15

31.4.8/31-16

31.4.8/31-16

31.4.6/31-15

31.4.6/31-15

31.4.6/31-15

NOTE

Debug control registers can be written by the external development system or the CPU through the WDEBUG instruction. CSR is write-only from the programming model. It can be read or written through the BDM port using the

RDMREG

and

WDMREG

commands.

31.4.1

Shared Debug Resources

The debug module implementation provides a common hardware structure for both BDM and breakpoint functionality. Certain hardware structures are used for both BDM and breakpoint purposes as shown in

Table 31-4

.

Table 31-4. Shared BDM/Breakpoint Hardware

Register

AATR

ABHR

DBR

BDM Function Breakpoint Function

Bus attributes for all memory commands Attributes for address breakpoint

Address for all memory commands Address for address breakpoint

Data for all BDM write commands Data for data breakpoint

Thus, loading a register to perform a specific function that shares hardware resources is destructive to the shared function. For example, if an operand address breakpoint is loaded into the debug module, a BDM command to access memory overwrites an address breakpoint in ABHR. If a data breakpoint is configured, a BDM write command overwrites the data breakpoint in DBR.

31.4.2

Configuration/Status Register (CSR)

The CSR defines the debug configuration for the processor and memory subsystem and contains status information from the breakpoint logic. CSR is write-only from the programming model. It can be read from and written to through the BDM port. CSR is accessible in supervisor mode as debug control register

0x00 using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG commands.



Preliminary

31-7

Debug Module

DRc[4:0]: 0x00 (CSR)

31

R

W

Reset 0

30 29

BSTAT

0 0

28 27 26 25 24

FOF TRG HALT BKPT

23

0 0 0 0 0 1

22

HRL

21

0 0

20

Access: Supervisor write-only

BDM read/write

19

0

18 17 16

BKD PCD IPW

1 0 0 0

15 14 13

R

W

MAP TRC EMU

Reset 0 0 0

12

DDC

11 10

UHE

9 8 7

0

6 5 4

NPL IPI SSM BTB

0 0 0 0 0 0 0 0

Figure 31-4. Configuration/Status Register (CSR)

0

Table 31-5. CSR Field Descriptions

3

0

0

2

0

0

1

0

0

0

0

0


27

FOF

26

TRG

25

HALT

24

BKPT

23–20

HRL

31–28

BSTAT

Breakpoint status. Provides read-only status (from the BDM port only) information concerning hardware breakpoints.

BSTAT is cleared by a TDR write or by a CSR read when either a level-2 breakpoint is triggered or a level-1 breakpoint is triggered and the level-2 breakpoint is disabled.

0000 No breakpoints enabled

0001 Waiting for level-1 breakpoint

0010 Level-1 breakpoint triggered

0101 Waiting for level-2 breakpoint

0110 Level-2 breakpoint triggered

Fault-on-fault. If FOF is set, a catastrophic halt occurred and forced entry into BDM. FOF is cleared whenever CSR is read (from the BDM port only).

Hardware breakpoint trigger. If TRG is set, a hardware breakpoint halted the processor core and forced entry into

BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) will clear TRG.

Processor halt. If HALT is set, the processor executed a HALT and forced entry into BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) will clear HALT.

Breakpoint assert. If BKPT is set, BKPT was asserted, forcing the processor into BDM. Reset, the debug GO command, or reading CSR (from the BDM port only) will clear BKPT.

Hardware revision level. Indicates, from the BDM port only, the level of debug module functionality. An emulator could use this information to identify the level of functionality supported.

1001 Revision B+ (This is the only valid value for this processor)


17

PCD

PST/DDATA Disable. Disables the PST/DDATA output signal. PSTCLK is unaffected, it remains under the control of the DISCLK bit in the SYNCR register.

0 Normal operation

1 Disables the generation of the PSTDDATA output signals, and forces these signals to remain quiescent

16

IPW

15

MAP

Inhibit processor writes. Setting IPW inhibits processor-initiated writes to the debug module’s programming model registers. IPW can be modified only by commands from the external development system.

Force processor references in emulator mode.

0 All emulator-mode references are mapped into supervisor code and data spaces.

1 The processor maps all references while in emulator mode to a special address space, TT = 10, TM = 101 or 110.

31-8



Preliminary

Debug Module

Table 31-5. CSR Field Descriptions (continued)

Field

14

TRC

13

EMU

12–11

DDC

10

UHE

9–8

BTB

7

6

NPL

5

IPI

4

SSM

3–0

Description

Force emulation mode on trace exception. If TRC = 1, the processor enters emulator mode when a trace exception occurs. If TRC=0, the processor enters supervisor mode.

Force emulation mode. If EMU = 1, the processor begins executing in emulator mode. See Section 31.6.1.1,

“Emulator Mode

.”

Debug data control. Controls operand data capture for DDATA, which displays the number of bytes defined by the operand reference size before the actual data; byte displays 8 bits, word displays 16 bits, and long displays 32 bits

(one nibble at a time across multiple PSTCLK cycles). See

Table 31-2

.

00 No operand data is displayed.

01 Capture all write data.

10 Capture all read data.

11 Capture all read and write data.

User halt enable. Selects the CPU privilege level required to execute the HALT instruction.

0 HALT is a supervisor-only instruction.

1 HALT is a supervisor/user instruction.

Branch target bytes. Defines the number of bytes of branch target address DDATA displays.

00 0 bytes

01 Lower 2 bytes of the target address

10 Lower 3 bytes of the target address

11 Entire 4-byte target address

See

Section 31.3.1, “Begin Execution of Taken Branch (PST = 0x5) .”


Non-pipelined mode. Determines whether the core operates in pipelined or mode or not.

0 Pipelined mode

1 Nonpipelined mode. The processor effectively executes one instruction at a time with no overlap. This adds at least 5 cycles to the execution time of each instruction. Given an average execution latency of 1.6 cycles/instruction, throughput in non-pipeline mode would be 6.6 cycles/instruction, approximately 25% or less of pipelined performance.

Regardless of the NPL state, a triggered PC breakpoint is always reported before the triggering instruction executes.

In normal pipeline operation, the occurrence of an address and/or data breakpoint trigger is imprecise. In non-pipeline mode, triggers are always reported before the next instruction begins execution and trigger reporting can be considered precise.

Ignore pending interrupts.

1 Core ignores any pending interrupt requests signalled while in single-instruction-step mode.

0 Core services any pending interrupt requests that were signalled while in single-step mode.

Single-step mode. Setting SSM puts the processor in single-step mode.

0 Normal mode.

1 Single-step mode. The processor halts after execution of each instruction. While halted, any BDM command can be executed. On receipt of the GO command, the processor executes the next instruction and halts again. This process continues until SSM is cleared.


31.4.3

BDM Address Attribute (BAAR)

The BAAR register defines the address space for memory-referencing BDM commands. BAAR[R, SZ] are loaded directly from the BDM command, while the low-order 5 bits can be programmed from the external development system. To maintain compatibility with the Rev. A implementation, this register is



Preliminary

31-9

Debug Module loaded any time the AATR is written. The BAAR is initialized to a value of 0x05, setting supervisor data as the default address space.

DRc[4:0]: 0x05 (BAAR)

7 6 5 4 3 2


BDM write-only

1 0

R

W

Reset:

R

0

SZ TT

0 0 0 0 1

Figure 31-5. BDM Address Attribute Register (BAAR)

Table 31-6. BAAR Field Description

TM

0 1

Field

7

R

6–5

SZ

4–3

TT

2–0

TM

Description

Read/Write.

0 Write

1 Read

Size.

00 Longword

01 Byte

10 Word

11 Reserved

Transfer type. See the TT definition in the AATR description,

Section 31.4.4, “Address Attribute Trigger Register

(AATR).”

Transfer modifier. See the TM definition in the AATR description,

Section 31.4.4, “Address Attribute Trigger Register

(AATR).”

31.4.4

Address Attribute Trigger Register (AATR)

The AATR defines address attributes and a mask to be matched in the trigger. The register value is compared with address attribute signals from the processor’s local high-speed bus, as defined by the setting of the trigger definition register (TDR). AATR is accessible in supervisor mode as debug control register 0x06 using the WDEBUG instruction and through the BDM port using the WDMREG command.

DRc[4:0]: 0x06 (AATR)

14 13 12 11 10 9 8 7 6 5 4


BDM write-only

3 2 1 0 15

R

W RM

Reset 0 0

SZM

0 0

TTM

0 0

TMM

0 0

R

0 0

SZ

0 0

Figure 31-6. Address Attribute Trigger Register (AATR)

TT

0 1

TM

0 1

31-10



Preliminary

Debug Module

Table 31-7. AATR Field Descriptions

Field

15

RM

14–13

SZM

12–11

TTM

10–8

TMM

7

R

6–5

SZ

4–3

TT

2–0

TM

Description

Read/write mask. Setting RM masks R in address comparisons.

Size mask. Setting an SZM bit masks the corresponding SZ bit in address comparisons.

Transfer type mask. Setting a TTM bit masks the corresponding TT bit in address comparisons.

Transfer modifier mask. Setting a TMM bit masks the corresponding TM bit in address comparisons.

Read/write. R is compared with the R/W signal of the processor’s local bus.

Size. Compared to the processor’s local bus size signals.

00 Longword

01 Byte

10 Word

11 Reserved

Transfer type. Compared with the local bus transfer type signals.

00 Normal processor access

01 Reserved

10 Emulator mode access

11 Acknowledge/CPU space access

These bits also define the TT encoding for BDM memory commands. In this case, the 01 encoding generates an external master or DMA access (for backward compatibility). These bits are used to decode the TM bits.

Transfer modifier. Compared with the local bus transfer modifier signals, which give supplemental information for each transfer type. These bits also define the TM encoding for BDM memory commands (for backward compatibility).

TM

000

001

010

011

100

101

110

111

TT=00

(normal mode)

Reserved

User data access

User code access

Reserved

Reserved

Supervisor data access

Supervisor code access

Reserved

TT=10

(emulator mode)

Reserved

Reserved

Reserved

Reserved

Reserved

Emulator mode access

Emulator code

Access

Reserved

TT=11

(acknowledge/CPU space transfers)

CPU space access

Interrupt ack level 1









Preliminary

31-11

Debug Module

31.4.5

Trigger Definition Register (TDR)

The TDR configures the operation of the hardware breakpoint logic that corresponds with the

ABHR/ABLR/AATR, PBR/PBMR, and DBR/DBMR registers within the debug module. The TDR controls the actions taken under the defined conditions. Breakpoint logic may be configured as a one- or two-level trigger. TDR[31–16] bits define the second-level trigger and TDR[15–0] bits define the first-level trigger.

NOTE

The debug module has no hardware interlocks, so to prevent spurious breakpoint triggers while the breakpoint registers are being loaded, disable

TDR (by clearing TDR[29,13]) before defining triggers.

A write to TDR clears the CSR trigger status bits, CSR[BSTAT]. TDR is accessible in supervisor mode as debug control register 0x07 using the WDEBUG instruction and through the BDM port using the WDMREG command.

DRc[4:0]: 0x07 (TDR) Access: Supervisor write-only

BDM write-only

28 27 26 25 24

Second Level Trigger

23 22 21 20 19 18 17 16 31 30

R

W

Reset 0

TRC

0

29

L2EBL

0 0

12

0

11

0

10

L2ED

0

9

0 0 0

First Level Trigger

L2DI

0

8 7 6 5

0

4

L2EA

0

3

0

2

L2EPC L2PCI

0 0

1 0 15 14 13

R

W L2T L1T L1EBL

Reset 0 0 0 0 0 0

L1ED

0 0 0 0

L1DI

0

Figure 31-7. Trigger Definition Register (TDR)

0

L1EA

0 0

L1EPC L1PCI

0 0

Table 31-8. TDR Field Descriptions


31–30

TRC

29

L2EBL

Trigger response control. Determines how the processor responds to a completed trigger condition. The trigger response is always displayed on DDATA.

00 Display on DDATA only

01 Processor halt

10 Debug interrupt

11 Reserved

Enable level 2 breakpoint. Global enable for the breakpoint trigger.

0 Disables all level 2 breakpoints

1 Enables all level 2 breakpoint triggers

31-12



Preliminary

Debug Module

Table 31-8. TDR Field Descriptions (continued)

Field

28–22

L2ED

Description

Enable level 2 data breakpoint. Setting an L2ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all ED bits disables data breakpoints.

TDR Bit

24

23

22

28

27

26

25

Description

Data longword. Entire processor’s local data bus.

Lower data word.

Upper data word.

Lower lower data byte. Low-order byte of the low-order word.

Lower middle data byte. High-order byte of the low-order word.

Upper middle data byte. Low-order byte of the high-order word.

Upper upper data byte. High-order byte of the high-order word.

21

L2DI

20–18

L2EA

Level 2 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents.

0 No inversion

1 Invert data breakpoint comparators.

Enable level 2 address breakpoint. Setting an L2EA bit enables the corresponding address breakpoint. Clearing all three bits disables the breakpoint.

TDR Bit

20

19

18

Description

Address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR.

Address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.

Address breakpoint low. The breakpoint is based on the address in the ABLR.

17

L2EPC

Enable level 2 PC breakpoint.

0 Disable PC breakpoint

1 Enable PC breakpoint

16

L2PCI

15

L2T

Level 2 PC breakpoint invert.

0 The PC breakpoint is defined within the region defined by PBR and PBMR.

1 The PC breakpoint is defined outside the region defined by PBR and PBMR.

Level 2 trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &

Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.

0 Level 2 trigger = PC_condition & Address_range & Data_condition

1 Level 2 trigger = PC_condition | (Address_range & Data_condition)

Note: Debug Rev A only had the ‘AND’ condition available for the triggers.



Preliminary

31-13

Debug Module

Table 31-8. TDR Field Descriptions (continued)


14

L1T

13

L1EBL

12–6

L1ED

Level 1 trigger. Determines the logic operation for the trigger between the PC_condition and the (Address_range &

Data_condition) where the inclusion of a Data_condition is optional. The ColdFire debug architecture supports the creation of single or double-level triggers.

0 Level 1 trigger = PC_condition & Address_range & Data_condition

1 Level 1 trigger = PC_condition | (Address_range & Data_condition)

Note: Debug Rev A only had the ‘AND’ condition available for the triggers.

Enable level 1 breakpoint. Global enable for the breakpoint trigger.

0 Disables all level 1 breakpoints

1 Enables all level 1 breakpoint triggers

Enable level 1 data breakpoint. Setting an L1ED bit enables the corresponding data breakpoint condition based on the size and placement on the processor’s local data bus. Clearing all L1ED bits disables data breakpoints.

TDR Bit

8

7

6

12

11

10

9

Description

Data longword. Entire processor’s local data bus.

Lower data word.

Upper data word.

Lower lower data byte. Low-order byte of the low-order word.

Lower middle data byte. High-order byte of the low-order word.

Upper middle data byte. Low-order byte of the high-order word.

Upper upper data byte. High-order byte of the high-order word.

5

L1DI

4–2

L1EA

Level 1 data breakpoint invert. Inverts the logical sense of all the data breakpoint comparators. This can develop a trigger based on the occurrence of a data value other than the DBR contents.

0 No inversion

1 Invert data breakpoint comparators.

Enable level 1 address breakpoint. Setting an L1EA bit enables the corresponding address breakpoint. Clearing all three bits disables the address breakpoint.

TDR Bit

4

3

2

Description

Enable address breakpoint inverted. Breakpoint is based outside the range between ABLR and ABHR.

Enable address breakpoint range. The breakpoint is based on the inclusive range defined by ABLR and ABHR.

Enable address breakpoint low. The breakpoint is based on the address in the ABLR.

1

L1EPC

Enable level 1 PC breakpoint.

0 Disable PC breakpoint

1 Enable PC breakpoint

0

L1PCI

Level 1 PC breakpoint invert.

0 The PC breakpoint is defined within the region defined by PBR and PBMR.

1 The PC breakpoint is defined outside the region defined by PBR and PBMR.

31-14



Preliminary

Debug Module

31.4.6

Program Counter Breakpoint/Mask Registers (PBR, PBMR)

The PBR register defines an instruction address for use as part of the trigger. This register’s contents are compared with the processor’s program counter register when TDR is configured appropriately. PBR bits are masked by setting corresponding PBMR bits. Results are compared with the processor’s program

counter register, as defined in TDR. Figure 31-8 shows the PC breakpoint register.

The PC breakpoint register is accessible in supervisor mode using the WDEBUG instruction and through the BDM port using the RDMREG and WDMREG

commands and values shown in Section 31.5.3.3,

“Command Set Descriptions .”

DRc[4:0]: 0x08 (PBR) Access: Supervisor write-only

BDM read/write

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 31-8. Program Counter Breakpoint Register (PBR)

Table 31-9. PBR Field Descriptions


31–1

Address

PC breakpoint address. The address to be compared with the PC as a breakpoint trigger.

Figure 31-8

shows PBMR. PBMR is accessible in supervisor mode as debug control register 0x09 using the WDEBUG instruction and via the BDM port using the WDMREG command. PBMR only masks PBR0.

DRc[4:0]: 0x09 (PBMR) Access: Supervisor write-only

BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W Mask

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 31-9. Program Counter Breakpoint Mask Register (PBMR)

Field

31–0

Mask

Table 31-10. PBMR Field Descriptions

Description

PC breakpoint mask. A zero in a bit position causes the corresponding PBR bit to be compared to the appropriate

PC bit. Setting a PBMR bit causes the corresponding PBR bit to be ignored.

31.4.7

Address Breakpoint Registers (ABLR, ABHR)

The ABLR and ABHR, shown in Figure 31-10 , define regions in the processor’s data address space that

can be used as part of the trigger. These register values are compared with the address for each transfer on



Preliminary

31-15

Debug Module the processor’s high-speed local bus. The trigger definition register (TDR) identifies the trigger as one of three cases:

1. Identical to the value in ABLR

2. Inside the range bound by ABLR and ABHR inclusive

3. Outside that same range

ABHR is accessible in supervisor mode as debug control register 0x0C using the WDEBUG instruction and via the BDM port using the

RDMREG

and

WDMREG

commands. ABLR is accessible in supervisor mode as debug control register 0x0D using the WDEBUG instruction and via the BDM port using the

WDMREG command.

DRc[4:0]: 0x0C (ABHR)

0x0D (ABLR)


BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W Address

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 31-10. Address Breakpoint Registers (ABLR, ABHR)

Table 31-11. ABLR Field Description


31–0

Address

Low address. Holds the 32-bit address marking the lower bound of the address breakpoint range. Breakpoints for specific addresses are programmed into ABLR.

Table 31-12. ABHR Field Description


31–0

Address

High address. Holds the 32-bit address marking the upper bound of the address breakpoint range.

31.4.8

Data Breakpoint/Mask Registers (DBR, DBMR)

The DBR specifies data patterns used as part of the trigger into debug mode. DBR bits are masked by setting the corresponding DBMR bits, as defined in TDR. DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction, and through the BDM port using the RDMREG and

WDMREG commands. DBMR is accessible in supervisor mode as debug control register 0x0F, using the

WDEBUG instruction and via the BDM port using the WDMREG command.

DRc[4:0]: 0x0E (DBR)

0x0F (DBMR)


BDM write-only

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

R

W Data (DBR); Mask (DBMR)

Reset – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – – –

Figure 31-11. Data Breakpoint & Mask Registers (DBR & DBMR)

31-16



Preliminary

Debug Module

Table 31-13. DBR Field Descriptions

Field

31–0

Data

Description

Data breakpoint value. Contains the value to be compared with the data value from the processor’s local bus as a breakpoint trigger.

Table 31-14. DBMR Field Descriptions

Field

31–0

Mask

Description

Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows the corresponding

DBR bit to be compared to the appropriate bit of the processor’s local data bus. Setting a DBMR bit causes that bit to be ignored.

The DBR supports both aligned and mis-aligned references. Table 31-15

shows relationships between processor address, access size, and location within the 32-bit data bus.

Table 31-15. Access Size and Operand Data Location

A[1:0]

0x

1x xx

00

01

10

11

Access Size

Byte

Byte

Byte

Byte

Word

Word

Longword

Operand Location

D[31:24]

D[23:16]

D[15:8]

D[7:0]

D[31:16]

D[15:0]

D[31:0]

31.5

Background Debug Mode (BDM)

The ColdFire family implements a low-level system debugger in the microprocessor in a dedicated hardware module. Communication with the development system is handled through a dedicated, high-speed serial command interface. Although some BDM operations, such as CPU register accesses, require the CPU to be halted, other BDM commands, such as memory accesses, can be executed while the processor is running.

31.5.1

CPU Halt

Although most BDM operations can occur in parallel with CPU operations, unrestricted BDM operation requires the CPU to be halted. The sources that can cause the CPU to halt are listed below in order of priority:

1. A catastrophic fault-on-fault condition automatically halts the processor.



Preliminary

31-17

Debug Module

2. A hardware breakpoint can be configured to generate a pending halt condition similar to the assertion of BKPT. This type of halt is always first made pending in the processor. Next, the processor samples for pending halt and interrupt conditions once per instruction. When a pending

condition is asserted, the processor halts execution at the next sample point. See Section 31.6.1,

“Theory of Operation .”

3. The execution of a HALT instruction immediately suspends execution. Attempting to execute

HALT in user mode while CSR[UHE] = 0 generates a privilege violation exception. If

CSR[UHE] = 1, HALT can be executed in user mode. After HALT executes, the processor can be restarted by serial shifting a

GO

command into the debug module. Execution continues at the instruction after HALT.

4. The assertion of the BKPT input is treated as a pseudo-interrupt; that is, the halt condition is postponed until the processor core samples for halts/interrupts. The processor samples for these conditions once during the execution of each instruction. If there is a pending halt condition at the sample time, the processor suspends execution and enters the halted state.

The assertion of BKPT should be considered in the following two special cases:

• After the system reset signal is negated, the processor waits for 16 processor clock cycles before beginning reset exception processing. If the BKPT input is asserted within eight cycles after RSTI is negated, the processor enters the halt state, signaling halt status (0xF) on the PST outputs. While the processor is in this state, all resources accessible through the debug module can be referenced.

This is the only chance to force the processor into emulation mode through CSR[EMU].

After system initialization, the processor’s response to the GO command depends on the set of

BDM commands performed while it is halted for a breakpoint. Specifically, if the PC register was loaded, the GO command causes the processor to exit halted state and pass control to the instruction address in the PC, bypassing normal reset exception processing. If the PC was not loaded, the GO command causes the processor to exit halted state and continue reset exception processing.

• The ColdFire architecture also handles a special case of BKPT being asserted while the processor is stopped by execution of the STOP instruction. For this case, the processor exits the stopped mode and enters the halted state, at which point, all BDM commands may be exercised. When restarted, the processor continues by executing the next sequential instruction, that is, the instruction following the STOP opcode.

The CSR[27–24] bits indicate the halt source, showing the highest priority source for multiple halt conditions.

31.5.2

BDM Serial Interface

When the CPU is halted and PST reflects the halt status, the development system can send unrestricted commands to the debug module. The debug module implements a synchronous serial protocol using two inputs (DSCLK and DSI) and one output (DSO), where DSO is specified as a delay relative to the rising edge of the processor clock. See

Table 31-1

. The development system serves as the serial communication channel master and must generate DSCLK.

The serial channel operates at a frequency from DC to 1/5 of the PSTCLK frequency. The channel uses full-duplex mode, where data is sent and received simultaneously by both master and slave devices. The

31-18



Preliminary

Debug Module transmission consists of 17-bit packets composed of a status/control bit and a 16-bit data word. As shown

in Figure 31-12 , all state transitions are enabled on a rising edge of PSTCLK when DSCLK is high; that

is, DSI is sampled and DSO is driven.

C1 C2 C3 C4

PSTCLK

DSCLK

DSI Current Next

BDM State

Machine

DSO

Current State

Past

Next State

Current

Figure 31-12. BDM Serial Interface Timing

DSCLK and DSI are synchronized inputs. DSCLK acts as a pseudo clock enable and is sampled on the rising edge of the processor clock as well as the DSI. DSO is delayed from the DSCLK-enabled CLK rising edge (registered after a BDM state machine state change). All events in the debug module’s serial state machine are based on the processor clock rising edge. DSCLK must also be sampled low (on a positive edge of CLK) between each bit exchange. The msb is transferred first. Because DSO changes state based on an internally-recognized rising edge of DSCLK, DSO cannot be used to indicate the start of a serial transfer. The development system must count clock cycles in a given transfer. C1–C4 are described as follows:

• C1—First synchronization cycle for DSI (DSCLK is high)

• C2—Second synchronization cycle for DSI (DSCLK is high)

• C3—BDM state machine changes state depending on DSI and whether the entire input data transfer has been transmitted

• C4—DSO changes to next value

NOTE

A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

31.5.2.1

Receive Packet Format

The basic receive packet, Figure 31-13 , consists of 16 data bits and 1 status bit.

15

S

15 14 13 12 11 10 9 8 7

Data Field

6

Figure 31-13. Receive BDM Packet

5 4 3 2 1 0



Preliminary

31-19

Debug Module

Table 31-16. Receive BDM Packet Field Description

Field

16

S

Description

Status. Indicates the status of CPU-generated messages listed below. The not-ready response can be ignored unless a memory-referencing cycle is in progress. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

S

0

0

1

1

1

Data xxxx

FFFF

0000

0001

FFFF

Message

Valid data transfer

Status OK

Not ready with response; come again

Error–Terminated bus cycle; data invalid

Illegal Command

15–0

Data

Data. Contains the message to be sent from the debug module to the development system. The response message is always a single word, with the data field encoded as shown above.

31.5.2.2

Transmit Packet Format

The basic transmit packet, Figure 31-14 , consists of 16 data bits and 1 reserve bit.

15

—

Field

16

15–0

Data

15 14 13 12 11 10 9 8

Data

7 6

Figure 31-14. Transmit BDM Packet

5 4 3 2

Table 31-17. Transmit BDM Packet Field Description

Description


Data bits 15–0. Contains the data to be sent from the development system to the debug module.

1 0

31.5.3

BDM Command Set

Table 31-18

summarizes the BDM command set. Subsequent paragraphs contain detailed descriptions of each command. Issuing a BDM command when the processor is accessing debug module registers using the WDEBUG instruction causes undefined behavior. See

Table 31-20 for register address encodings.

Table 31-18. BDM Command Summary

Command

Read A/D register

Write A/D register

Mnemonic

RAREG

RDREG

WAREG /

WDREG

/

Description

CPU

State

1

Section/

Page

Command

(Hex)

Read the selected address or data register and return the results through the serial interface.

Halted

31.5.3.3.1/

31-24

0x218 {A/D, Reg[2:0]}

Write the data operand to the specified address or data register.

Halted

31.5.3.3.2/

31-24

0x208 {A/D, Reg[2:0]}

31-20



Preliminary

Debug Module

Table 31-18. BDM Command Summary (continued)

Command Mnemonic Description

CPU

State

1

Section/

Page

Command

(Hex)

Read memory location

Write memory location

READ

WRITE

Read the data at the memory location specified by the longword address.

Write the operand data to the memory location specified by the longword address.

Steal

31.5.3.3.3/

31-25

0x1900 byte

0x1940 word

0x1980 longword

Steal

31.5.3.3.4/

31-26

0x1800 byte

0x1840 word

0x1880 longword

Steal

31.5.3.3.5/

31-28

0x1D00 byte

0x1D40 word

0x1D80 longword

Dump memory block

Fill memory block

DUMP

FILL

Used with READ to dump large blocks of memory.

An initial READ is executed to set up the starting address of the block and to retrieve the first result. A DUMP command retrieves subsequent operands.

Used with WRITE to fill large blocks of memory.

An initial WRITE is executed to set up the starting address of the block and to supply the first operand. A FILL command writes subsequent operands.

Steal

31.5.3.3.6/

31-30

0x1C00 byte

0x1C40 word

0x1C80 longword

Resume execution

No operation

Synchronize PC to PST/DDATA

Read control register

GO

NOP

RCREG

The pipeline is flushed and refilled before resuming instruction execution at the current PC.

Perform no operation; may be used as a null command.

SYNC _ PC Capture the current PC and display it on the

PST/DDATA outputs

Read the system control register.

Halted

31.5.3.3.7/

Parallel

31-31

31.5.3.3.8/

31-32

Parallel

31.5.3.3.9/

31-32

Halted

31.5.3.3.10

/31-33

0x0C00

0x0000

0x0001

0x2980

Write control register

Read debug module register

WCREG

RDMREG

Write the operand data to the system control register.

Read the debug module register.

Halted

31.5.3.3.11

/31-34

0x2880

Parallel

31.5.3.3.12

/31-35

0x2D {0x4

2

DRc[4:0]}

Write debug module register

WDMREG Write the operand data to the debug module register.

Parallel

1

2

General command effect and/or requirements on CPU operation:

- Halted: The CPU must be halted to perform this command.

- Steal: Command generates bus cycles that can be interleaved with bus accesses.

- Parallel: Command is executed in parallel with CPU activity.

0x4 is a three-bit field.

31.5.3.3.13

/31-36

0x2C {0x4

2

DRc[4:0]}

Unassigned command opcodes are reserved by Freescale. All unused command formats within any revision level perform a

NOP

and return the illegal command response .

31.5.3.1

ColdFire BDM Command Format

All ColdFire family BDM commands include a 16-bit operation word followed by an optional set of one or more extension words, as shown in

Figure 31-15

.



Preliminary

31-21

Debug Module

15 15 14 13

Operation

12 11 10 9

0

8

R/W

7 6

Op Size

Extension Word(s)

Figure 31-15. BDM Command Format

5

0

4

0

3

A/D

2 1

Register

0

Table 31-19. BDM Field Descriptions


15–10

Operation

Specifies the command. These values are listed in Table 31-18

.

9

8

R/W


Direction of operand transfer.

0 Data is written to the CPU or to memory from the development system.

1 The transfer is from the CPU to the development system.

7–6

Op Size

Operand data size for sized operations. Addresses are expressed as 32-bit absolute values. Note that a command performing a byte-sized memory read leaves the upper 8 bits of the response data undefined. Referenced data is returned in the lower 8 bits of the response.

00

01

10

11

Operand Size

Byte

Word

Longword

Reserved

Bit Values

8 bits

16 bits

32 bits

—

5–4

3

A/D


Address/data. Determines whether the register field specifies a data or address register.

0 Data register.

1 Address register.

2–0

Register

Contains the register number in commands that operate on processor registers. See

Table 31-20 .

31.5.3.1.1

Extension Words as Required

Some commands require extension words for addresses and/or immediate data. Addresses require two extension words because only absolute long addressing is permitted. Longword accesses are forcibly longword-aligned, and word accesses are forcibly word-aligned. Immediate data can be 1 or 2 words long.

Byte and word data each requires a single extension word, while longword data requires two extension words.

Operands and addresses are transferred most-significant word first. In the following descriptions of the

BDM command set, the optional set of extension words is defined as address, data, or operand data.

31.5.3.2

Command Sequence Diagrams

The command sequence diagram in Figure 31-16 shows serial bus traffic for commands. Each bubble

represents a 17-bit bus transfer. The top half of each bubble indicates the data the development system

31-22



Preliminary

Debug Module sends to the debug module; the bottom half indicates the debug module’s response to the previous development system commands. Command and result transactions overlap to minimize latency.

Commands transmitted to the debug module

Command code transmitted during this cycle

High-order 16 bits of memory address

Low-order 16 bits of memory address

Non-serial-related activity Sequence taken if operation has not completed

READ (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

Next

Command

Code

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

XXX

MS RESULT

NEXT CMD

LS RESULT

Data used from this transfer

XXX

BERR

NEXT CMD

’NOT READY’

Sequence taken if illegal command is received by debug module

Results from previous command

Sequence taken if bus error occurs on memory access

Responses from the debug module

Figure 31-16. Command Sequence Diagram

High- and low-order 16 bits of result

The sequence is as follows:

• In cycle 1, the development system command is issued ( READ in this example). The debug module responds with either the low-order results of the previous command or a command complete status of the previous command, if no results are required.

• In cycle 2, the development system supplies the high-order 16 address bits. The debug module returns a not-ready response unless the received command is decoded as unimplemented, which is indicated by the illegal command encoding. If this occurs, the development system should retransmit the command.

NOTE

A not-ready response can be ignored except during a memory-referencing cycle. Otherwise, the debug module can accept a new serial transfer after 32 processor clock periods.

• In cycle 3, the development system supplies the low-order 16 address bits. The debug module always returns a not-ready response.

• At the completion of cycle 3, the debug module initiates a memory read operation. Any serial transfers that begin during a memory access return a not-ready response.

• Results are returned in the two serial transfer cycles after the memory access completes. For any command performing a byte-sized memory read operation, the upper 8 bits of the response data are undefined and the referenced data is returned in the lower 8 bits. The next command’s opcode is



Preliminary

31-23

Debug Module sent to the debug module during the final transfer. If a memory or register access is terminated with a bus error, the error status (S = 1, DATA = 0x0001) is returned instead of result data.

31.5.3.3

Command Set Descriptions

The following sections describe the commands summarized in

Table 31-18 .

NOTE

The BDM status bit (S) is 0 for normally completed commands; S = 1 for illegal commands, not-ready responses, and transfers with bus-errors.

Section 31.5.2, “BDM Serial Interface

,” describes the receive packet format.

Freescale reserves unassigned command opcodes for future expansion. Unused command formats in any revision level perform a

NOP

and return an illegal command response.

31.5.3.3.1

Read A/D Register ( RAREG / RDREG )

Read the selected address or data register and return the 32-bit result. A bus error response is returned if the CPU core is not halted.

Command/Result Formats:

Command

Result

15

Command Sequence:

14

0x2

13 12 11 10

0x1

9 8 7 6

0x8

5

D[31:16]

D[15:0]

Figure 31-17. RAREG / RDREG Command Format

4

RAREG/RDREG

???

XXX

MS RESULT

NEXT CMD

LS RESULT

3

A/D

2 1

Register

0

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 31-18. RAREG / RDREG Command Sequence

None

The contents of the selected register are returned as a longword value, most-significant word first.

31.5.3.3.2

Write A/D Register ( WAREG / WDREG )

The operand longword data is written to the specified address or data register. A write alters all 32 register bits. A bus error response is returned if the CPU core is not halted.

Command Format:

31-24



Preliminary

Debug Module

15 14

0x2

13 12 11 10 9 8 7 6 5 4

0x0 0x8

D[31:16]

D[15:0]

Figure 31-19. WAREG / WDREG Command Format

3

A/D

2 1

Register

0

Command Sequence:

WAREG/WDREG

???

MS DATA

’NOT READY’

LS DATA

’NOT READY’

NEXT CMD

’CMD COMPLETE’

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 31-20. WAREG / WDREG Command Sequence

Longword data is written into the specified address or data register. The data is supplied most-significant word first.

Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete.

31.5.3.3.3

Read Memory Location ( READ )

Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.


4 3 2

0x0

1 0

Byte

Command

Result

Word Command

X

Result

Longword Command

Result

15 14

0x1

13 12 11 10

0x9

9 8 7 6

0x0

5

A[31:16]

A[15:0]

X X

0x1

X X X X

0x9

X

0x4

A[31:16]

A[15:0]

D[15:0]

0x1 0x9 0x8

A[31:16]

A[15:0]

D[31:16]

D[15:0]

Figure 31-21. READ Command/Result Formats

D[7:0]

0x0

0x0



Preliminary

31-25

Debug Module

Command Sequence:

READ (B/W)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

RESULT

XXX

BERR

NEXT CMD

’NOT READY’

READ (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

READ

MEMORY

LOCATION

XXX

’NOT READY’

XXX

MS RESULT

NEXT CMD

LS RESULT

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 31-22. READ Command Sequence

The only operand is the longword address of the requested location.

Word results return 16 bits of data; longword results return 32. Bytes are returned in the LSB of a word result; the upper byte is undefined. 0x0001 (S = 1) is returned if a bus error occurs.

31.5.3.3.4

Write Memory Location ( WRITE )

Write data to the memory location specified by the longword address. The address space is defined by

BAAR[TT,TM]. Hardware forces low-order address bits to zeros for word and longword accesses to ensure that word addresses are word-aligned and longword addresses are longword-aligned.

Command Formats:

31-26



Preliminary

Debug Module

Byte

Word

Longword

15 14

0x1

13

X X

0x1

X

0x1

12 11 10

0x8

9 8 7 6

0x0

X X X X

A[31:16]

A[15:0]

X

0x8 0x4

A[31:16]

A[15:0]

D[15:0]

0x8 0x8

A[31:16]

A[15:0]

D[31:16]

D[15:0]

Figure 31-23. WRITE Command Format

5 4

D[7:0]

3 2

0x0

1 0

0x0

0x0



Preliminary

31-27

Debug Module

Command Sequence:

WRITE (B/W)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

NEXT CMD

’NOT READY’

WRITE (LONG)

???

MS ADDR

’NOT READY’

LS ADDR

’NOT READY’

MS DATA

’NOT READY’

LS DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

Operand Data:

Result Data:

NEXT CMD

’NOT READY’

Figure 31-24. WRITE Command Sequence

This two-operand instruction requires a longword absolute address that specifies a location to which the data operand is to be written. Byte data is sent as a 16-bit word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits, respectively.

Command complete status is indicated by returning 0xFFFF (with S cleared) when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.

31.5.3.3.5

Dump Memory Block ( DUMP )

DUMP is used with the READ command to access large blocks of memory. An initial READ is executed to set up the starting address of the block and to retrieve the first result. If an initial

READ

is not executed before the first DUMP , an illegal command response is returned. The DUMP command retrieves subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register. Subsequent

DUMP

commands use this address, perform the memory read, increment it by the current operand size, and store the updated address in the temporary register.

31-28



Preliminary

Debug Module

NOTE

DUMP

does not check for a valid address; it is a valid command only when preceded by

NOP

,

READ

, or another

DUMP

command. Otherwise, an illegal command response is returned.

NOP

can be used for intercommand padding without corrupting the address pointer.

The size field is examined each time a DUMP command is processed, allowing the operand size to be dynamically altered.


15 12 11 8 7 4 3 0

Byte Command 0x1 0xD 0x0 0x0

X D[7:0]

Word

Result

Command

Result

Longword Command

Result

X X X X X X X

0x1 0xD 0x4

D[15:0]

0x1 0xD 0x8

D[31:16]

D[15:0]

Figure 31-25. DUMP Command/Result Formats

0x0

0x0

Command Sequence:

DUMP (B/W)

???

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

RESULT

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

XXX

BERR

NEXT CMD

’NOT READY’

DUMP (LONG)

???

Operand Data:

READ

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

MS RESULT

None

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Figure 31-26. DUMP Command Sequence

XXX

BERR

NEXT CMD

LS RESULT

NEXT CMD

’NOT READY’



Preliminary

31-29

Debug Module

Result Data:

Byte

Requested data is returned as either a word or longword. Byte data is returned in the least-significant byte of a word result. Word results return 16 bits of significant data; longword results return 32 bits. A value of 0x0001 (with S set) is returned if a bus error occurs.

31.5.3.3.6

Fill Memory Block ( FILL )

A

FILL

command is used with the

WRITE

command to access large blocks of memory. An initial

WRITE

is sets up the starting address of the block and to supply the first operand. The

FILL

command writes subsequent operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary register after the memory write. Subsequent

FILL

commands use this address, perform the write, increment it by the current operand size, and store the updated address in the temporary register.

If an initial WRITE is not executed preceding the first FILL command, the illegal command response is returned.

NOTE

The FILL command does not check for a valid address— FILL is a valid command only when preceded by another FILL , a NOP , or a WRITE command.

Otherwise, an illegal command response is returned. The NOP command can be used for intercommand padding without corrupting the address pointer.

The size field is examined each time a

FILL

command is processed, allowing the operand size to be altered dynamically.

Command Formats:

4 3 2

0x0

1 0

Word

Longword

15

X

14

0x1

13

X X

0x1

0x1

12

X

11

X

10

0xC

9

X X

0xC

8

X

7 6

0x0

5

0x4

D[15:0]

0xC 0x8

D[31:16]

D[15:0]

Figure 31-27. FILL Command Format

D[7:0]

0x0

0x0

31-30



Preliminary

Debug Module

Command Sequence:

FILL (LONG)

???

MS DATA

’NOT READY’

XXX

’ILLEGAL’

LS DATA

’NOT READY’

NEXT CMD

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

NEXT CMD

’NOT READY’

FILL (B/W)

???

DATA

’NOT READY’

WRITE

MEMORY

LOCATION

XXX

’NOT READY’

Operand Data:

Result Data:

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

NEXT CMD

’NOT READY’

Figure 31-28. FILL Command Sequence

A single operand is data to be written to the memory location. Byte data is sent as a 16-bit word, justified in the least-significant byte; 16- and 32-bit operands are sent as 16 and 32 bits, respectively.

Command complete status (0xFFFF) is returned when the register write is complete. A value of 0x0001 (with S set) is returned if a bus error occurs.

31.5.3.3.7

Resume Execution ( GO )

The pipeline is flushed and refilled before normal instruction execution resumes. Prefetching begins at the current address in the PC and at the current privilege level. If any register (such as the PC or SR) is altered by a BDM command while the processor is halted, the updated value is used when prefetching resumes.

If a GO command is issued and the CPU is not halted, the command is ignored.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0x0 0xC 0x0 0x0

Figure 31-29. GO Command Format

Command Sequence:

GO

???

NEXT CMD

’CMD COMPLETE’

Figure 31-30. GO Command Sequence



Preliminary

31-31

Debug Module

Operand Data:

Result Data:

None

The command-complete response (0xFFFF) is returned during the next shift operation.

31.5.3.3.8

No Operation ( NOP )

NOP

performs no operation and may be used as a null command where required.

Command Formats:

15 14

0x0

13 12 11 10 9 8 7 6 5

0x0 0x0

Figure 31-31. NOP Command Format

4 3 2

0x0

1 0

Command Sequence:

NOP

???

NEXT CMD

’CMD COMPLETE’

Operand Data:

Result Data:

Figure 31-32. NOP Command Sequence

None

The command-complete response, 0xFFFF (with S cleared), is returned during the next shift operation.

31.5.3.3.9

Synchronize PC to the PST/DDATA Lines ( SYNC _ PC )

Capture the current PC (program counter) and display it on the PST/DDATA outputs. After the debug module receives the command, it sends a signal to the ColdFire core that the current PC must be displayed.

The core then forces an instruction fetch at the next PC with the address being captured in the DDATA logic under control of the CSR[BTB] bits. The specific sequence of PST and DDATA values is defined below:

1. Debug signals a SYNC _ PC command is pending.

2. CPU completes the current instruction.

3. CPU forces an instruction fetch to the next PC, generates a PST = $5 value indicating a taken branch and signals DDATA. DDATA captures the instruction address corresponding to the PC.

DDATA generates a PST marker ($9–$B) as defined by CSR[BTB] and displays the captured PC address.

This command can be used to dynamically access the PC for performance monitoring. The execution of this command is considerably less obtrusive to the real-time operation of an application than a halt-CPU/read-PC/resume command sequence.

Format:

15 14

0x0

13 12 11 10

0x0

9 8 7 6

0x0

5 4 3 2

0x1

1 0

31-32



Preliminary

Debug Module

Command Sequence:

SYNC_PC

???

NEXT CMD

“CMD COMPLETE”

Operand Data:

Result Data:

None

The command complete response, $FFFF (with the status bit cleared), is returned during the next shift operation.

31.5.3.3.10

Read Control Register ( RCREG )

Reads the selected control register and returns the 32-bit result. Accesses to the processor/memory control registers are always 32 bits wide, regardless of register width. The second and third words of the command form a 32-bit address, which the debug module uses to generate a special bus cycle to access the specified control register. The 12-bit Rc field is the same as that used by the MOVEC instruction.


Command

Result

15 14

0x2

13

0x0

0x0

12 11 10

0x9

9

0x0

8 7 6

0x8

0x0

Rc

5

D[31:16]

D[15:0]

Figure 31-33. RCREG Command/Result Formats

4

Rc encoding:

Rc

0x800

0x801

0x804

0x805

0x806

0x80E

0x80F

0xC04

0xC05

Table 31-20. Control Register Map

Register Definition

Other Stack Pointer (OTHER_A7)

Vector Base Register (VBR)


MAC Mask Register (MASK)

MAC Accumulator 0 (ACC0)

Status Register (SR)

Program Register (PC)

Flash Base Address Register (FLASHBAR)

RAM Base Address Register (RAMBAR)

3

Command Sequence:

2

0x0

0x0

1 0



Preliminary

31-33

Debug Module

RCREG

???

MS ADDR

’NOT READY’

MS ADDR

’NOT READY’

READ

CONTROL

REGISTER

XXX

’NOT READY’

NEXT CMD

MS RESULT

NEXT CMD

LS RESULT

Operand Data:

Result Data:

XXX

BERR

NEXT CMD

’NOT READY’

Figure 31-34. RCREG Command Sequence

The only operand is the 32-bit Rc control register select field.

Control register contents are returned as a longword, most-significant word first.

The implemented portion of registers smaller than 32 bits is guaranteed correct; other bits are undefined.

BDM Accesses of the Stack Pointer Registers (A7: SSP, USP)

The V2 core supports two unique stack pointer (A7) registers: the supervisor stack pointer (SSP) and the user stack pointer (USP). The hardware implementation of these two programmable-visible, 32-bit registers does not uniquely identify one as the SSP and the other as the USP. Rather, the hardware uses one

32-bit register as the currently-active A7, and the other register is named simply the ‘other_A7.’ Thus, the contents of the two hardware registers is a function of the operating mode of the processor: if SR[S] = 1

then

else

A7 = Supervisor Stack Pointer other_A7 = User Stack Pointer

A7 = User Stack Pointer other_A7 = Supervisor Stack Pointer

The BDM programming model supports reads and writes to the A7 and other_A7 registers directly. It is the responsibility of the external development system to determine the mapping of the two hardware registers (A7, other_A7) to the two program-visible definitions (supervisor and user stack pointers), based on the supervisor bit of the status register.

31.5.3.3.11

Write Control Register ( WCREG )

The operand (longword) data is written to the specified control register. The write alters all 32 register bits.


31-34



Preliminary

Debug Module

Command

Result

15

Command Sequence:

14

0x2

13

0x0

0x0

12 11 10

0x8

9

0x0

8 7 6

0x8

5

0x0

R c

D[31:16]

D[15:0]

Figure 31-35. WCREG Command/Result Formats

4 3 2

0x0

1

0x0

0

WCREG

???

MS ADDR

’NOT READY’

MS ADDR

’NOT READY’

MS DATA

’NOT READY’

LS DATA

’NOT READY’

WRITE

CONTROL

REGISTER

XXX

’NOT READY’

NEXT CMD

’CMD COMPLETE’

XXX

BERR

Operand Data:

Result Data:

NEXT CMD

’NOT READY’

Figure 31-36. WCREG Command Sequence

This instruction requires two longword operands. The first selects the register to which the operand data is to be written; the second contains the data.

Successful write operations return 0xFFFF. Bus errors on the write cycle are indicated by the setting of bit 16 in the status message and by a data pattern of

0x0001.

31.5.3.3.12

Read Debug Module Register ( RDMREG )

Read the selected debug module register and return the 32-bit result. The only valid register selection for the RDMREG command is CSR (DRc = 0x00). Note that this read of the CSR clears CSR[FOF, TRG, HALT,

BKPT]; as well as the trigger status bits (CSR[BSTAT]) if either a level-2 breakpoint has been triggered or a level-1 breakpoint has been triggered and no level-2 breakpoint has been enabled.




Preliminary

31-35

Debug Module

Command

Result

15 14

0x2

13 12 11 10

0xD

9 8 7 6

100

5 4

D[31:16]

D[15:0]

Figure 31-37. RDMREG Command/Result Formats

3 2

DR c

1

Table 31-21

shows the definition of DRc encoding.

Table 31-21. Definition of DRc Encoding—Read

DRc[4:0]

0x00

0x01–0x1F

Debug Register Definition

Configuration/Status

Reserved

Mnemonic

CSR

—

Initial State

0x0

—

Command Sequence:

0

Page

p. 31-7

—

RDMREG

???

XXX

MS RESULT

NEXT CMD

LS RESULT

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Operand Data:

Result Data:

Figure 31-38. RDMREG Command Sequence

None

The contents of the selected debug register are returned as a longword value. The data is returned most-significant word first.

31.5.3.3.13

Write Debug Module Register ( WDMREG )

The operand (longword) data is written to the specified debug module register. All 32 bits of the register are altered by the write. DSCLK must be inactive while the debug module register writes from the CPU accesses are performed using the WDEBUG instruction.

Command Format:

0 15 14

0x2

13 12 11 10

0xC

9 8 7 6

100

5 4

D[31:16]

D[15:0]

Figure 31-39. WDMREG BDM Command Format

Table 31-3

shows the definition of the DRc write encoding.

Command Sequence:

3 2

DRc

1

31-36



Preliminary

Debug Module

WDMREG

???

MS DATA

’NOT READY’

LS DATA

’NOT READY’

NEXT CMD

’CMD COMPLETE’

Operand Data:

Result Data:

XXX

’ILLEGAL’

NEXT CMD

’NOT READY’

Figure 31-40. WDMREG Command Sequence

Longword data is written into the specified debug register. The data is supplied most-significant word first.

Command complete status (0xFFFF) is returned when register write is complete.

31.6

Real-Time Debug Support

The ColdFire family provides support debugging real-time applications. For these types of embedded systems, the processor must continue to operate during debug. The foundation of this area of debug support is that while the processor cannot be halted to allow debugging, the system can generally tolerate small intrusions into the real-time operation.

The debug module provides four types of breakpoints—PC with mask, PC without mask, operand address range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the exact trigger response also programmable. The debug module programming model can be written from either the external development system using the debug serial interface or from the processor’s supervisor programming model using the WDEBUG instruction. Only CSR is readable using the external development system.

31.6.1

Theory of Operation

Breakpoint hardware can be configured to respond to triggers in several ways. The desired response is

programmed into TDR. As shown in Table 31-22 , when a breakpoint is triggered, an indication

(CSR[BSTAT]) is provided on the DDATA output port when it is not displaying captured processor status, operands, or branch addresses.

Table 31-22. DDATA[3:0]/CSR[BSTAT] Breakpoint Response

DDATA[3:0]

1

CSR[BSTAT]

1

Breakpoint Status

0000

0010

0100

0000

0001

0010

No breakpoints enabled

Waiting for level-1 breakpoint

Level-1 breakpoint triggered

1010 0101 Waiting for level-2 breakpoint

1100 0110 Level-2 breakpoint triggered

1

Encodings not shown are reserved for future use.



Preliminary

31-37

Debug Module

The breakpoint status is also posted in the CSR. Note that CSR[BSTAT] is cleared by a CSR read when either a level-2 breakpoint is triggered, or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status is also cleared by writing to TDR.

BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates, a breakpoint trigger generates the response defined in TDR.

PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before the excepting instruction is executed. All other breakpoint events are recognized on the processor’s local bus, but are made pending to the processor and sampled like other interrupt conditions. As a result, these interrupts are imprecise.

In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] = 01, a breakpoint trigger causes the core to halt (PST = 0xF).

If the processor core cannot be halted, the debug interrupt can be used. With the configuration

TDR[TRC] = 10, the breakpoint trigger becomes a debug interrupt to the processor, which is treated higher than the nonmaskable level-7 interrupt request. As with all interrupts, it is made pending until the processor reaches a sample point, which occurs once per instruction. Again, the hardware forces the PC breakpoint to occur before the targeted instruction executes. This is possible because the PC breakpoint is enabled when interrupt sampling occurs. For address and data breakpoints, reporting is considered imprecise, because several instructions may execute after the triggering address or data is detected.

As soon as the debug interrupt is recognized, the processor aborts execution and initiates exception processing. This event is signaled externally by the assertion of a unique PST value (PST = 0xD) for multiple cycles. The core enters emulator mode when exception processing begins. After the standard

8-byte exception stack is created, the processor fetches a unique exception vector, 12, from the vector table. (Refer to the ColdFire Programmer’s Reference Manual ).

Execution continues at the instruction address in the vector corresponding to the breakpoint triggered. All interrupts are ignored while the processor is in emulator mode. The debug interrupt handler can use supervisor instructions to save the necessary context, such as the state of all program-visible registers into a reserved memory area.

When debug interrupt operations complete, the RTE instruction executes and the processor exits emulator mode. After the debug interrupt handler completes execution, the external development system can use

BDM commands to read the reserved memory locations.

If a hardware breakpoint such as a PC trigger is left unmodified by the debug interrupt service routine, another debug interrupt is generated after the completion of the RTE instruction. Therefore, the debug interrupt service routine should clear the respective TDR setting.

In the Rev. A implementation, if a hardware breakpoint (e.g., a PC trigger) is left unmodified by the debug interrupt service routine, another debug interrupt is generated after the RTE instruction completes execution. In the Rev. B design, the hardware has been modified to inhibit the generation of another debug interrupt during the first instruction after the RTE exits emulator mode. This behavior is consistent with the existing logic involving trace mode, where the execution of the first instruction occurs before another trace exception is generated. This Rev. B enhancement disables all hardware breakpoints until the first instruction after the RTE has completed execution, regardless of the programmed trigger response.

31-38



Preliminary

Debug Module

31.6.1.1

Emulator Mode

Emulator mode is used to facilitate non-intrusive emulator functionality. This mode can be entered in three different ways:

• Setting CSR[EMU] forces the processor into emulator mode. EMU is examined only if RSTI is negated and the processor begins reset exception processing. It can be set while the processor is halted before reset exception processing begins. See

Section 31.5.1, “CPU Halt .”

• A debug interrupt always puts the processor in emulation mode when debug interrupt exception processing begins.

• Setting CSR[TRC] forces the processor into emulation mode when trace exception processing begins.

While operating in emulation mode, the processor exhibits the following properties:

• All interrupts are ignored, including level-7 interrupts.

• If CSR[MAP] = 1, all caching of memory and the SRAM module are disabled. All memory accesses are forced into a specially mapped address space signaled by TT = 0x2, TM = 0x5 or 0x6.

This includes stack frame writes and the vector fetch for the exception that forced entry into this mode.

The RTE instruction exits emulation mode. The processor status output port provides a unique encoding for emulator mode entry (0xD) and exit (0x7).

31.6.2

Concurrent BDM and Processor Operation

The debug module supports concurrent operation of both the processor and most BDM commands. BDM commands may be executed while the processor is running, except those following operations that access processor/memory registers:

• Read/write address and data registers

• Read/write control registers

For BDM commands that access memory, the debug module requests the processor’s local bus. The processor responds by stalling the instruction fetch pipeline and waiting for current bus activity to complete before freeing the local bus for the debug module to perform its access. After the debug module bus cycle, the processor reclaims the bus.

Breakpoint registers must be carefully configured in a development system if the processor is executing.

The debug module contains no hardware interlocks, so TDR should be disabled while breakpoint registers are loaded, after which TDR can be written to define the exact trigger. This prevents spurious breakpoint triggers.

Because there are no hardware interlocks in the debug unit, no BDM operations are allowed while the CPU is writing the debug’s registers (DSCLK must be inactive).



Preliminary

31-39

Debug Module

31.7

Processor Status, DDATA Definition

This section specifies the ColdFire processor and debug module’s generation of the processor status (PST) and debug data (DDATA) output on an instruction basis. In general, the PST/DDATA output for an instruction is defined as follows:

PST = 0x1, {PST = [0x89B], DDATA= operand} where the {...} definition is optional operand information defined by the setting of the CSR.

The CSR provides capabilities to display operands based on reference type (read, write, or both). A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to follow on the DDATA output {1,

2, or 4 bytes}. Additionally, for certain change-of-flow branch instructions, CSR[BTB] provides the capability to display the target instruction address on the DDATA output {2, 3, or 4 bytes} using a PST value of {0x9, 0xA, or 0xB}.

Instruction asl.l

asr.l

bitrev.l

byterev.l

bcc.{b,w} bchg bchg bclr bclr add.l

add.l

addi.l

addq.l

addx.l

and.l

and.l

andi.l

31.7.1

User Instruction Set

Table 31-23

shows the PST/DDATA specification for user-mode instructions. Rn represents any {Dn, An} register. In this definition, the ‘y’ suffix generally denotes the source, and ‘x’ denotes the destination operand. For a given instruction, the optional operand data is displayed only for those effective addresses referencing memory. The ‘DD’ nomenclature refers to the DDATA outputs.

Table 31-23. PST/DDATA Specification for User-Mode Instructions

Operand Syntax

<ea>y,Rx

Dy,<ea>x

#imm,Dx

#imm,<ea>x

Dy,Dx

<ea>y,Dx

Dy,<ea>x

#imm,Dx

{Dy,#imm},Dx

{Dy,#imm},Dx

Dx

Dx

#imm,<ea>x

Dy,<ea>x

#imm,<ea>x

Dy,<ea>x

PST/DDATA

PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}

PST = 0x1


PST = 0x1



PST = 0x1

PST = 0x1

PST = 0x1

PST = 0x1

PST = 0x1 if taken, then PST = 0x5, else PST = 0x1

PST = 0x1, {PST = 0x8, DD = source}, {PST = 0x8, DD = destination}




31-40



Preliminary

lea link.w

lsl.l

lsr.l

move.b

move.l

move.w

move.w

move.w

Instruction clr.w

cmp.l

cmpi.l

divs.l

divs.w

divu.l

divu.w

eor.l

bra.{b,w} bset bset bsr.{b,w} btst btst clr.b

clr.l

eori.l

ext.l

ext.w

extb.l

ff1.l

jmp jsr

Table 31-23. PST/DDATA Specification for User-Mode Instructions (continued)

Operand Syntax PST/DDATA

#imm,<ea>x

Dy,<ea>x

#imm,<ea>x

Dy,<ea>x

<ea>x

<ea>x

<ea>x

<ea>y,Rx

#imm,Dx

<ea>y,Dx

<ea>y,Dx

<ea>y,Dx

<ea>y,Dx

Dy,<ea>x

#imm,Dx

Dx

Dx

Dx

Dx

<ea>x

<ea>x

PST = 0x5



PST = 0x5, {PST = 0xB, DD = destination operand}

PST = 0x1, {PST = 0x8, DD = source operand}


PST = 0x1, {PST = 0x8, DD = destination operand}


PST = 0x1, {PST = 0x9, DD = destination operand}


PST = 0x1






PST = 0x1

PST = 0x1

PST = 0x1

PST = 0x1

PST = 0x1

PST = 0x5, {PST = [0x9AB], DD = target address}

1

PST = 0x5, {PST = [0x9AB], DD = target address},

{PST = 0xB , DD = destination operand}

1

<ea>y,Ax

Ay,#imm

{Dy,#imm},Dx

{Dy,#imm},Dx

PST = 0x1


PST = 0x1

PST = 0x1

<ea>y,<ea>x

<ea>y,<ea>x

<ea>y,<ea>x

CCR,Dx




PST = 0x1

{Dy,#imm},CCR PST = 0x1

Debug Module



Preliminary

31-41

Debug Module scc sub.l

sub.l

subi.l

subq.l

subx.l

swap trap trapf tst.b

tst.l

tst.w

unlk

Instruction negx.l

nop not.l

or.l

or.l

ori.l

pea pulse movem.l

movem.l

moveq muls.l

muls.w

mulu.l

mulu.w

neg.l

rems.l

remu.l

rts


Operand Syntax

#list,<ea>x

<ea>y,#list

PST/DDATA

PST = 0x1, {PST = 0xB, DD = destination},...

2

PST = 0x1, {PST = 0xB, DD = source},...

2

#imm,Dx

<ea>y,Dx

PST = 0x1


<ea>y,Dx

<ea>y,Dx

<ea>y,Dx

Dx

Dx




PST = 0x1

Dx

<ea>y,Dx

Dy,<ea>x

#imm,Dx

<ea>y

PST = 0x1

PST = 0x1

PST = 0x1



PST = 0x1


PST = 0x4

<ea>y,Dx:Dw PST = 0x1, {PST = 0xB, DD = source operand}

<ea>y,Dx:Dw PST = 0x1, {PST = 0xB, DD = source operand}

PST = 0x1, {PST = 0xB, DD = source operand},

PST = 0x5, {PST = [0x9AB], DD = target address}

Dx

<ea>y,Rx

Dy,<ea>x

#imm,Dx

PST = 0x1



PST = 0x1

#imm,<ea>x

Dy,Dx

Dx

#imm

<ea>x

<ea>x

<ea>x

Ax


PST = 0x1

PST = 0x1

PST = 0x1

3

PST = 0x1





31-42



Preliminary

Debug Module


Instruction Operand Syntax PST/DDATA wddata.b

wddata.l

<ea>y

<ea>y

PST = 0x4, {PST = 0x8, DD = source operand

PST = 0x4, {PST = 0xB, DD = source operand wddata.w

<ea>y PST = 0x4, {PST = 0x9, DD = source operand

1

2

3

For JMP and JSR instructions, the optional target instruction address is displayed only for those effective address fields defining variant addressing modes. This includes the following <ea>x values: (An), (d16,An), (d8,An,Xi),

(d8,PC,Xi).

For Move Multiple instructions (MOVEM), the processor automatically generates line-sized transfers if the operand address reaches a 0-modulo-16 boundary and there are four or more registers to be transferred. For these line-sized transfers, the operand data is never captured nor displayed, regardless of the CSR value.

The automatic line-sized burst transfers are provided to maximize performance during these sequential memory access operations.

During normal exception processing, the PST output is driven to a 0xC indicating the exception processing state. The exception stack write operands, as well as the vector read and target address of the exception handler may also be displayed.

Exception ProcessingPST = 0xC,{PST = 0xB,DD = destination},// stack frame

{PST = 0xB,DD = destination},// stack frame

{PST = 0xB,DD = source},// vector read

PST = 0x5,{PST = [0x9AB],DD = target}// handler PC

The PST/DDATA specification for the reset exception is shown below:

Exception ProcessingPST = 0xC,

The initial references at address 0 and 4 are never captured nor displayed, because these accesses are treated as instruction fetches.

For all types of exception processing, the PST = 0xC value is driven at all times, unless the PST output is needed for one of the optional marker values or for the taken branch indicator (0x5).

Table 31-24

shows the PST/DDATA specification for multiply-accumulate instructions.

Table 31-24. PST/DDATA Specification for MAC Instructions

Instruction mac.l

mac.l

mac.w

mac.w

move.l

move.l

move.l

move.l

move.l

move.l


Ry,Rx,Accx PST = 0x1

RyRx,<ea>,Rw,Accx PST = 0x1, {PST = 0xB, DD = source operand}


Ry,Rx,<ea>,Rw,Accx PST = 0x1, {PST = 0xB, DD = source operand}

<ea>y,Accx PST = 0x1

Accy,Accx PST = 0x1

<ea>y,MACR PST = 0x1

<ea>y,MASK PST = 0x1

<ea>y,Accext01 PST = 0x1

<ea>y,Accext23 PST = 0x1



Preliminary

31-43

Debug Module

Instruction move.l

move.l

move.l

move.l

move.l

move.l

msac.l

msac.l

msac.w

msac.w

Table 31-24. PST/DDATA Specification for MAC Instructions (continued)


Accy,Rx PST = 0x1

MACSR,CCR PST = 0x1

MACSR,Rx PST = 0x1

MASK,Rx PST = 0x1

Accext01,Rx

Accext23,Rx

PST = 0x1

PST = 0x1





31.7.2

Supervisor Instruction Set

The supervisor instruction set has complete access to the user mode instructions plus the opcodes shown below. The PST/DDATA specification for these opcodes is shown in

Table 31-25 .

Table 31-25. PST/DDATA Specification for Supervisor-Mode Instructions

Instruction Operand Syntax cpushl halt move.w

move.w

movec rte stldsr.w

stop wdebug

PST/DDATA

SR,Dx PST = 0x1

{Dy,#imm},SR PST = 0x1, {PST = 0x3}

Ry,Rc PST = 0x1

PST = 0x7, {PST = 0xB, DD = source operand}, {PST = 3}, { PST =0xB,

DD =source operand},

PST = 0x5, {[PST = 0x9AB], DD = target address}

#imm

#imm

<ea>y

PST = 0x1

PST = 0x1,

PST = 0xF

PST = 0x1, {PST = 0xA, DD = destination operand, PST = 0x3}

PST = 0x1,

PST = 0xE

PST = 0x1, {PST = 0xB, DD = source, PST = 0xB, DD = source}

The move-to-SR, STLDSR, and RTE instructions include an optional PST = 0x3 value, indicating an entry into user mode. Additionally, if the execution of a RTE instruction returns the processor to emulator mode, a multiple-cycle status of 0xD is signaled.

Similar to the exception processing mode, the stopped state (PST = 0xE) and the halted state (PST = 0xF) display this status throughout the entire time the ColdFire processor is in the given mode.

31.8

Freescale-Recommended BDM Pinout

The ColdFire BDM connector,

Figure 31-41

, is a 26-pin Berg connector arranged 2 × 13.

31-44



Preliminary

Developer reserved

1

GND

GND

RSTI

Pad-Voltage

2

GND

PST2

PST0

DDATA2

DDATA0

Freescale reserved

GND

Core-Voltage

10

12

14

16

6

8

2

4

18

20

22

24

26

9

11

13

15

5

7

1

3

17

19

21

23

25

BKPT

DSCLK

Developer reserved

1

DSI

DSO

PST3

PST1

DDATA3

DDATA1

GND

Freescale reserved

PSTCLK

TA

1

Pins reserved for BDM developer use.

2

Supplied by target

Figure 31-41. Recommended BDM Connector

Debug Module



Preliminary

31-45

Debug Module

31-46



Preliminary

Chapter 32


32.1

Introduction

The joint test action group (JTAG) is a dedicated user-accessible test logic that complies with the IEEE

1149.1 standard for boundary-scan testability, which helps with system diagnostic and manufacturing testing.

This architecture provides access to all data and chip control pins from the board-edge connector through the standard four-pin test access port (TAP) and the JTAG reset pin, TRST.

32.1.1

Block Diagram

Figure 32-1

shows the block diagram of the JTAG module.

TDI/DSI

TAP Controller

1-bit Bypass Register

Boundary Scan Register

31

32-bit IDCODE Register

1-bit TEST_CTRL Register

0

0

5-bit TAP Instruction Decoder

4

5-bit TAP Instruction Register

0

1

0

TDO/DSO

JTAG_EN

TCLK

TMS/BKPT

TRST/DSCLK

JTAG Module

Disable DSCLK

Force BKPT = 1

DSI = 0

DSO to Debug Module

Figure 32-1. JTAG Block Diagram

DSI

BKPT

DSCLK

1

0



Preliminary

32-1


32.1.2

Features

The basic tasks of the JTAG module include the following:

• Performs boundary-scan operations to test circuit board electrical continuity

• Bypasses instruction to reduce the shift register path to a single cell

• Sets chip output pins to safety states while executing the bypass instruction

• Samples the system pins during operation and transparently shift out the result

• Selects between JTAG TAP controller and background debug module (BDM) using a dedicated

JTAG_EN pin

32.1.3


The JTAG_EN pin can select between the following modes of operation:

• JTAG mode (JTAG_EN = 1)

•

Background debug mode (BDM)—for more information, refer to Section 31.5, “Background

Debug Mode (BDM)”

; (JTAG_EN = 0).

32.2


The JTAG module has five input and one output external signals, as described in

Table 32-1 .


Name

JTAG_EN

TCLK

TMS/BKPT

TDI/DSI

TRST/DSCLK

TDO/DSO

Direction

Input

Input

Input

Input

Input

Output

Function

JTAG/BDM selector input

JTAG Test clock input

JTAG Test mode select / BDM Breakpoint

JTAG Test data input / BDM Development serial input

JTAG Test reset input / BDM Development serial clock

JTAG Test data output / BDM Development serial output

Reset State

—

—

—

—

—

Hi-Z / 0

Pull up

—

Active

Active

Active

Active

—

32.2.1

JTAG Enable (JTAG_EN)

The JTAG_EN pin selects between the debug module and JTAG. If JTAG_EN is low, the debug module is

selected; if it is high, the JTAG is selected. Table 32-2

summarizes the pin function selected depending on

JTAG_EN logic state.

32-2



Preliminary


Table 32-2. Pin Function Selected

Module selected

Pin Function

JTAG_EN = 0

BDM

—

BKPT

DSI

DSO

DSCLK

JTAG_EN = 1

JTAG

TCLK

TMS

TDI

TDO

TRST

Pin Name

—

TCLK

BKPT

DSI

DSO

DSCLK

When one module is selected, the inputs into the other module are disabled or forced to a known logic

level, as shown in Table 32-3 , in order to disable the corresponding module.

Table 32-3. Signal State to the Disable Module

Disabling JTAG

Disabling BDM

JTAG_EN = 0

TRST = 0

TMS = 1

—

JTAG_EN = 1

—

Disable DSCLK

DSI = 0

BKPT = 1

NOTE

The JTAG_EN does not support dynamic switching between JTAG and

BDM modes.

32.2.2

Test Clock Input (TCLK)

The TCLK pin is a dedicated JTAG clock input to synchronize the test logic. Pulses on TCLK shift data and instructions into the TDI pin on the rising edge and out of the TDO pin on the falling edge. TCLK is independent of the processor clock. The TCLK pin has an internal pull-up resistor, and holding TCLK high or low for an indefinite period does not cause JTAG test logic to lose state information.

32.2.3

Test Mode Select/Breakpoint (TMS/BKPT)

The TMS pin is the test mode select input that sequences the TAP state machine. TMS is sampled on the rising edge of TCLK. The TMS pin has an internal pull-up resistor.

The BKPT pin is used to request an external breakpoint. Assertion of BKPT puts the processor into a halted state after the current instruction completes.

32.2.4

Test Data Input/Development Serial Input (TDI/DSI)

The TDI pin receives serial test and data, which is sampled on the rising edge of TCLK. Register values are shifted in least significant bit (lsb) first. The TDI pin has an internal pull-up resistor.

The DSI pin provides data input for the debug module serial communication port.



Preliminary

32-3


32.2.5

Test Reset/Development Serial Clock (TRST/DSCLK)

The TRST pin is an active low asynchronous reset input with an internal pull-up resistor that forces the

TAP controller to the test-logic-reset state.

The DSCLK pin clocks the serial communication port to the debug module. Maximum frequency is 1/5 the processor clock speed. At the rising edge of DSCLK, the data input on DSI is sampled and DSO changes state.

32.2.6

Test Data Output/Development Serial Output (TDO/DSO)

The TDO pin is the lsb-first data output. Data is clocked out of TDO on the falling edge of TCLK. TDO is tri-stateable and actively driven in the shift-IR and shift-DR controller states.

The DSO pin provides serial output data in BDM mode.

32.3


The JTAG module registers are not memory mapped and are only accessible through the TDO/DSO pin.

32.3.1

Instruction Shift Register (IR)

The JTAG module uses a -bit shift register with no parity. The IR transfers its value to a parallel hold register and applies an instruction on the falling edge of TCLK when the TAP state machine is in the update-IR state. To load an instruction into the shift portion of the IR, place the serial data on the TDI pin before each rising edge of TCLK. The msb of the IR is the bit closest to the TDI pin, and the lsb is the bit

closest to the TDO pin. See Section 32.4.3, “JTAG Instructions”

for a list of possible instruction codes.

TAP state: Update-IR

R

W

Reset

4

1

3

0


2

1

Instruction Code

0

1

0

0 0 0

Figure 32-2. 5-Bit Instruction Register (IR)

0

1

1

32.3.2

IDCODE Register

The IDCODE is a read-only register; its value is chip dependent. For more information, see

Section 32.4.3.1, “IDCODE Instruction

.”

IR[4:0]: 0_0001 (IDCODE) Access: User read-only

R

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

PRN DC PIN JEDEC ID

W

Reset 0 0 0 0 0 1 1 1 0 1 Device Dependent 0 0 0 0 0 0 0 1 1 1 0 1

Figure 32-3. IDCODE Register

32-4



Preliminary


Table 32-4. IDCODE Field Descriptions


31–28

PRN

27–22

DC

21–12

PIN

Part revision number. Indicate the revision number of the device.

Freescale Design Center number.

Part identification number. Indicate the device number.

11–1

JEDEC

0

ID

Joint Electron Device Engineering Council ID bits. Indicate the reduced JEDEC ID for Freescale (0x0E).

IDCODE register ID. This bit is set to 1 to identify the register as the IDCODE register and not the bypass register according to the IEEE standard 1149.1.

32.3.3

Bypass Register

The bypass register is a single-bit shift register path from TDI to TDO when the BYPASS, CLAMP, or

HIGHZ instructions are selected. After entry into the capture-DR state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the bypass register is always a logic 0.

32.3.4

TEST_CTRL Register

The TEST_CTRL register is a 1-bit shift register path from TDI to TDO when the

ENABLE_TEST_CTRL instruction is selected. The TEST_CTRL transfers its value to a parallel hold register on the rising edge of TCLK when the TAP state machine is in the update-DR state. The DSE bit selects the drive strength used in JTAG mode.

IR[4:0]: 0_0110 Access: User read-only

R

W

Reset

0

DSE

0

Figure 32-4. 1-Bit TEST_CTRL Register

32.3.5

Boundary Scan Register

The boundary scan register is connected between TDI and TDO when the EXTEST or

SAMPLE/PRELOAD instruction is selected. It captures input pin data, forces fixed values on output pins, and selects a logic value and direction for bidirectional pins, or high impedance for tri-stated pins.

The boundary scan register contains bits for bonded-out and non bonded-out signals, excluding JTAG signals, analog signals, power supplies, compliance enable pins, device configuration pins, and clock signals.



Preliminary

32-5


32.4


32.4.1

JTAG Module

The JTAG module consists of a TAP controller state machine, which is responsible for generating all control signals that execute the JTAG instructions and read/write data registers.

32.4.2

TAP Controller

The TAP controller is a state machine that changes state based on the sequence of logical values on the

TMS pin. Figure 32-5 shows the machine’s states. The value shown next to each state is the value of the

TMS signal sampled on the rising edge of the TCLK signal.

Asserting the TRST signal asynchronously resets the TAP controller to the test-logic-reset state. As

Figure 32-5

shows, holding TMS at logic 1 while clocking TCLK through at least five rising edges also causes the state machine to enter the test-logic-reset state, whatever the initial state.

32-6



Preliminary


1 TEST-LOGIC-RESET

0

0 RUN-TEST/IDLE

1

SELECT DR-SCAN

1

0

1

CAPTURE-DR

0

SHIFT-DR

1

0

0

1

0

PAUSE-DR

1

EXIT2-DR

1

UPDATE-DR

1 0

0

1

SELECT IR-SCAN

0

1

CAPTURE-IR

0

SHIFT-IR

1

EXIT1-IR

0

0

1

0

0

PAUSE-IR

1

EXIT2-IR

1

UPDATE-IR

1 0

Figure 32-5. TAP Controller State Machine Flow

32.4.3

JTAG Instructions

Table 32-5

describes public and private instructions.

Table 32-5. JTAG Instructions

Instruction

IDCODE

SAMPLE/PRELOAD

SAMPLE

IR[4:0] Instruction Summary

00001 Selects IDCODE register for shift

00010 Selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation

00011 Selects boundary scan register for shifting and sampling without disturbing functional operation



Preliminary

32-7


Table 32-5. JTAG Instructions (continued)

Instruction IR[4:0] Instruction Summary

EXTEST

ENABLE_TEST_CTRL

HIGHZ

CLAMP

00100 Selects boundary scan register while applying preloaded values to output pins and asserting functional reset

00110 Selects TEST_CTRL register

01001 Selects bypass register while tri-stating all output pins and asserting functional reset

01100 Selects bypass while applying fixed values to output pins and asserting functional reset

BYPASS

Reserved

11111 Selects bypass register for data operations all others

1

Decoded to select bypass register

1

Freescale reserves the right to change the decoding of the unused opcodes in the future.

32.4.3.1

IDCODE Instruction

The IDCODE instruction selects the 32-bit IDCODE register for connection as a shift path between the

TDI and TDO pin. This instruction allows interrogation of the MCU to determine its version number and other part identification data. The shift register lsb is forced to logic 1 on the rising edge of TCLK following entry into the capture-DR state. Therefore, the first bit to be shifted out after selecting the

IDCODE register is always a logic 1. The remaining 31 bits are also forced to fixed values on the rising edge of TCLK following entry into the capture-DR state.

IDCODE is the default instruction placed into the instruction register when the TAP resets. Thus, after a

TAP reset, the IDCODE register is selected automatically.

32.4.3.2

SAMPLE/PRELOAD Instruction

The SAMPLE/PRELOAD instruction has two functions:

•

SAMPLE - See Section 32.4.3.3, “SAMPLE Instruction ” for description of this function.

• PRELOAD - initialize the boundary scan register update cells before selecting EXTEST or

CLAMP. This is achieved by ignoring the data shifting out on the TDO pin and shifting in initialization data. The update-DR state and the falling edge of TCLK can then transfer this data to the update cells. The data is applied to the external output pins by the EXTEST or CLAMP instruction.

32.4.3.3

SAMPLE Instruction

The SAMPLE instruction obtains a sample of the system data and control signals present at the MCU input pins and just before the boundary scan cell at the output pins. This sampling occurs on the rising edge of

TCLK in the capture-DR state when the IR contains the 0x2 opcode. The sampled data is accessible by shifting it through the boundary scan register to the TDO output by using the shift-DR state. Both the data capture and the shift operation are transparent to system operation.

32-8



Preliminary


NOTE

External synchronization is required to achieve meaningful results because there is no internal synchronization between TCLK and the system clock.

32.4.3.4

EXTEST Instruction

The external test (EXTEST) instruction selects the boundary scan register. It forces all output pins and bidirectional pins configured as outputs to the values preloaded with the SAMPLE/PRELOAD instruction and held in the boundary scan update registers. EXTEST can also configure the direction of bidirectional pins and establish high-impedance states on some pins. EXTEST asserts internal reset for the MCU system logic to force a predictable internal state while performing external boundary scan operations.

32.4.3.5

ENABLE_TEST_CTRL Instruction

The ENABLE_TEST_CTRL instruction selects a 1-bit shift register (TEST_CTRL) for connection as a shift path between the TDI and TDO pin. When the user transitions the TAP controller to the UPDATE_DR state, the register transfers its value to a parallel hold register.

32.4.3.6

HIGHZ Instruction

The HIGHZ instruction eliminates the need to backdrive the output pins during circuit-board testing.

HIGHZ turns off all output drivers, including the 2-state drivers, and selects the bypass register. HIGHZ also asserts internal reset for the MCU system logic to force a predictable internal state.

32.4.3.7

CLAMP Instruction

The CLAMP instruction selects the 1-bit bypass register and asserts internal reset while simultaneously forcing all output pins and bidirectional pins configured as outputs to the fixed values that are preloaded and held in the boundary scan update register. CLAMP enhances test efficiency by reducing the overall shift path to a single bit (the bypass register) while conducting an EXTEST type of instruction through the boundary scan register.

32.4.3.8

BYPASS Instruction

The BYPASS instruction selects the bypass register, creating a single-bit shift register path from the TDI pin to the TDO pin. BYPASS enhances test efficiency by reducing the overall shift path when a device other than the ColdFire processor is the device under test on a board design with multiple chips on the overall boundary scan chain. The shift register lsb is forced to logic 0 on the rising edge of TCLK after entry into the capture-DR state. Therefore, the first bit shifted out after selecting the bypass register is always logic 0. This differentiates parts that support an IDCODE register from parts that support only the bypass register.



Preliminary

32-9


32.5


32.5.1

Restrictions

The test logic is a static logic design, and TCLK can be stopped in either a high or low state without loss of data. However, the system clock is not synchronized to TCLK internally. Any mixed operation using both the test logic and the system functional logic requires external synchronization.

Using the EXTEST instruction requires a circuit-board test environment that avoids device-destructive configurations in which MCU output drivers are enabled into actively driven networks.

Low-power stop mode considerations:

• The TAP controller must be in the test-logic-reset state to either enter or remain in the low-power stop mode. Leaving the test-logic-reset state negates the ability to achieve low-power, but does not otherwise affect device functionality.

• The TCLK input is not blocked in low-power stop mode. To consume minimal power, the TCLK input should be externally connected to EV

DD

.

• The TMS, TDI, and TRST pins include on-chip pull-up resistors. For minimal power consumption in low-power stop mode, these three pins should be either connected to EV

DD

or left unconnected.

32.5.2

Nonscan Chain Operation

Keeping the TAP controller in the test-logic-reset state ensures that the scan chain test logic is transparent to the system logic. It is recommended that TMS, TDI, TCLK, and TRST be pulled up. TRST could be connected to ground. However, since there is a pull-up on TRST, some amount of current results. The internal power-on reset input initializes the TAP controller to the test-logic-reset state on power-up without asserting TRST.

32-10



Preliminary

Appendix A


Table A-1

summarizes the address, name, and byte assignment for registers within the MCF52235 CPU

space. Table A-2 lists an overview of the memory map for the on-chip modules, and

Table A-3 is a detailed

memory map including all of the registers for on-chip modules.

Table A-1. CPU Space Register Memory Map

Address

CPU @ 0x002

CPU @ 0x004

CPU @ 0x005

CPU @ 0x800

CPU @ 0x801

CPU @ 0x804

CPU @ 0x805

CPU @ 0x806

CPU @ 0x80E

CPU @ 0x80F

CPU @ 0xC04

CPU @ 0xC05

Name

Cache Control Register

Access Control Register 0

Access Control Register 1

Other Stack Pointer

Vector Base Register

MAC Status Register

MAC Mask Register

MAC Accumulator 0

Status Register

Program Counter

Flash Base Address Register

RAM Base Address Register

Mnemonic

CACR

ACR0

ACR1

OTHER_A7

VBR

MACSR

MASK

ACC0

SR

PC

FLASHBAR

RAMBAR

Size

32

8

16

16

32

32

32

32

16

32

32

32



Preliminary

A-1


Table A-2. Module Memory Map Overview

Address Module

0x0000_0000

IPSBAR + 0x00_0000

IPSBAR + 0x00_0040

IPSBAR + 0x00_0080

IPSBAR + 0x00_0100

IPSBAR + 0x00_0110

IPSBAR + 0x00_0120

IPSBAR + 0x00_0130

IPSBAR + 0x00_0140

IPSBAR + 0x00_0200

IPSBAR + 0x00_0240

IPSBAR + 0x00_0280

IPSBAR + 0x00_02C0

IPSBAR + 0x00_0300

IPSBAR + 0x00_0340

On-chip Flash/RAM Array

System Control Module

Reserved

Reserved

DMA (Channel 0)

DMA (Channel 1)

DMA (Channel 2)

DMA (Channel 3)

Reserved

UART0

UART1

UART2

Reserved

I

2

C

QSPI

IPSBAR + 0x00_0380

IPSBAR + 0x00_03C0

IPSBAR + 0x00_0400

IPSBAR + 0x00_0440

IPSBAR + 0x00_0480

IPSBAR + 0x00_04C0

IPSBAR + 0x00_0500

IPSBAR + 0x00_0C00

Reserved

RTC

DMA Timer 0

DMA Timer 1

DMA Timer 2

DMA Timer 3

Reserved

Interrupt Controller 0

IPSBAR + 0x00_0D00

IPSBAR + 0x00_0E00

IPSBAR + 0x00_0F00

IPSBAR + 0x00_1000

Interrupt Controller 1

Reserved

Global Interrupt Acknowledge Cycles

FEC Registers and MIB RAM

IPSBAR + 0x00_1400

IPSBAR + 0x00_1800

FEC FIFO Memory

Reserved

IPSBAR + 0x10_0000 Ports

IPSBAR + 0x11_0000 Reset Controller, Chip Configuration, and Power Management

IPSBAR + 0x12_0000

IPSBAR + 0x13_0000

IPSBAR + 0x14_0000

IPSBAR + 0x15_0000

Clock Module

Edge Port 0

Edge Port 1

Programmable Interval Timer 0

Size

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

1792

256 bytes

256 bytes

256

256 bytes

1K

1K

1M - 6K

64K

64K

64K

64K

64K

64K

1G

64 bytes

64 bytes

128 bytes

16 bytes

16 bytes

16 bytes

16 bytes

196 bytes

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

64 bytes

A-2



Preliminary

Address

IPSBAR + 0x000

IPSBAR + 0x008

IPSBAR + 0x00C

IPSBAR + 0x010

IPSBAR + 0x011

IPSBAR + 0x012

IPSBAR + 0x013

IPSBAR + 0x014

IPSBAR + 0x01C

IPSBAR + 0x020

IPSBAR + 0x024

IPSBAR + 0x025

IPSBAR + 0x026

IPSBAR + 0x027

IPSBAR + 0x028

IPSBAR + 0x8000_0000 Reserved


Table A-2. Module Memory Map Overview (continued)

Address

IPSBAR + 0x16_0000

IPSBAR + 0x17_0000

IPSBAR + 0x18_0000

IPSBAR + 0x19_0000

IPSBAR + 0x1A_0000

IPSBAR + 0x1B_0000

IPSBAR + 0x1C_0000

IPSBAR + 0x1D_0000

IPSBAR + 0x1E_0000

IPSBAR + 0x1F_0000

IPSBAR + 0x20_0000

IPSBAR + 0x400_0000

IPSBAR + 0x0408_0000

Module

Programmable Interval Timer 1

Reserved

Reserved

ADC

General Purpose Timer A

PWM

FlexCAN

CFM (Flash) Control Registers

Ethernet Physical Transceiver

Random Number Generator H/W Accelerator

Reserved

CFM (Flash) Memory for IPS Reads and Writes

Reserved

Size

64K

64K

64K

62M

256K

1G - 64M -

256K

2G

64K

64K

64K

64K

64K

64K

64K

Table A-3. Register Memory Map

Name

SCM Registers

Internal Peripheral System Base Address Register

Peripheral Power Management Register - High

Peripheral Power Management Register - Low

Core Reset Status Register

Core Watchdog Control Register

Low-Power Interrupt Control Register

Core Watchdog Service Register

DMA Request Control Register

Default Bus Master Park Register

Master Privilege Register

Peripheral Access Control Register 0





Mnemonic

IPSBAR

PPMRH

PPMRL

CRSR

CWCR

LPICR

CWSR

DMAREQC

MPARK

MPR

PACR0

PACR1

PACR2

PACR3

PACR4

Size

8

8

8

8

8

32

8

8

8

8

32

32

32

32

8



Preliminary

A-3


Address

IPSBAR + 0x02A

IPSBAR + 0x02B

IPSBAR + 0x02C

IPSBAR + 0x02E

IPSBAR + 0x030

IPSBAR + 0x031

IPSBAR + 0x100

IPSBAR + 0x104

IPSBAR + 0x108

IPSBAR + 0x10C

IPSBAR + 0x120

IPSBAR + 0x124

IPSBAR + 0x128

IPSBAR + 0x12C

IPSBAR + 0x130

IPSBAR + 0x134

IPSBAR + 0x138

IPSBAR + 0x13C

IPSBAR + 0x140

IPSBAR + 0x144

IPSBAR + 0x148

IPSBAR + 0x14C

IPSBAR + 0x200

IPSBAR + 0x204

IPSBAR + 0x208

IPSBAR + 0x20C

Table A-3. Register Memory Map (continued)

Name





Grouped Peripheral Access Control Register 0

Grouped Peripheral Access Control Register 1

DMA Registers

Source Address Register 0

Destination Address Register 0

Byte Count Register 0

DMA Status Register 0













UART Registers

UART Mode Register 0

1

Mnemonic

PACR5

PACR6

PACR7

PACR8

GPACR0

GPACR1

SAR2

DAR2

BCR2

DSR2

SAR3

DAR3

BCR3

DSR3

SAR0

DAR0

BCR0

DSR0

SAR1

DAR1

BCR1

DSR1

UMR10,

UMR20

USR0

UCSR0

(Read) UART Status Register 0

(Write) UART Clock Select Register 0

1

(Read) Reserved

(Write) UART Command Register 0

(Read) UART Receive Buffer 0

(Write) UART Transmit Buffer 0

UCR0

URB0

UTB0

Size

8

8

8

8

8

8

32

32

32

8

32

32

32

8

32

32

32

8

32

32

32

8

8

8

8

8

8

8

8

A-4



Preliminary

Address

IPSBAR + 0x210

IPSBAR + 0x214

IPSBAR + 0x218

IPSBAR + 0x21C

IPSBAR + 0x234

IPSBAR + 0x238

IPSBAR + 0x23C

IPSBAR + 0x240

IPSBAR + 0x244

IPSBAR + 0x248

IPSBAR + 0x24C

IPSBAR + 0x250

IPSBAR + 0x254

IPSBAR + 0x258

IPSBAR + 0x25C

IPSBAR + 0x274



Name

(Read) UART Input Port Change Register 0

(Write) UART Auxiliary Control Register 0

1

(Read) UART Interrupt Status Register 0

(Write) UART Interrupt Mask Register 0

(Read) Reserved

UART Baud Rate Generator Register 10

(Read) Reserved


(Read) UART Input Port Register 0

(Write) Reserved

(Read) Reserved

(Write) UART Output Port Bit Set Command Register 0

(Read) Reserved

(Write) UART Output Port Bit Reset Command Register 0

UART Mode Registers 1

1

Mnemonic

UIPCR0

UACR0

UISR0

UIMR0

UBG10

UBG20

UIP0

UOP10

UIP00

UMR11,

UMR21

USR1

UCSR1



1

(Read) Reserved


(UART/Read) UART Receive Buffer 1

(UART/Write) UART Transmit Buffer 1



1



(Read) Reserved


(Read) Reserved



(Write) Reserved

UCR1

URB1

UTB1

UIPCR1

UACR1

UISR1

UIMR1

UBG11

UBG21

UIP1 8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8



Preliminary

A-5


Address

IPSBAR + 0x278

IPSBAR + 0x27C

IPSBAR + 0x280

IPSBAR + 0x284

IPSBAR + 0x288

IPSBAR + 0x28C

IPSBAR + 0x290

IPSBAR + 0x294

IPSBAR + 0x298

IPSBAR + 0x29C

IPSBAR + 0x2B4

IPSBAR + 0x2B8

IPSBAR + 0x2BC

IPSBAR + 0x300

IPSBAR + 0x304

IPSBAR + 0x308

IPSBAR + 0x30C

IPSBAR + 0x310


Name

(Read) Reserved


(Read) Reserved


UART Mode Register 2

1

Mnemonic

UOP11

UIP01

UMR12,

UMR22

USR2

UCSR2



1

(Read) Reserved


(Read) UART Receive Buffer 2

(Write) UART Transmit Buffer 2



1



(Read) Reserved


(Read) Reserved



(Write) Reserved

(Read) Reserved


(Read) Reserved


I

2

C Registers

I

2

C Address Register

I

2

C Frequency Divider Register

I

2

C Control Register

I

2

C Status Register

I

2

C Data I/O Register

QSPI Registers

UCR2

URB2

UTB2

UIPCR2

UACR2

UISR2

UIMR2

UBG12

UBG22

UIP2

UOP12

UIP02

I2ADR

I2FDR

I2CR

I2SR

I2DR

A-6

8

8

8

8

8



Preliminary

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Address

IPSBAR + 0x340

IPSBAR + 0x344

IPSBAR + 0x348

IPSBAR + 0x34C

IPSBAR + 0x350

IPSBAR + 0x354

IPSBAR + 0x3C0

IPSBAR + 0x3C4

IPSBAR + 0x3C8

IPSBAR + 0x3CC

IPSBAR + 0x3D0

IPSBAR + 0x3D4

IPSBAR + 0x3D8

IPSBAR + 0x3DC

IPSBAR + 0x3E0

IPSBAR + 0x3E4

IPSBAR + 0x400

IPSBAR + 0x402

IPSBAR + 0x403

IPSBAR + 0x404

IPSBAR + 0x408

IPSBAR + 0x40C

IPSBAR + 0x440

IPSBAR + 0x442

IPSBAR + 0x443

IPSBAR + 0x444

IPSBAR + 0x448

IPSBAR + 0x44C

IPSBAR + 0x480

IPSBAR + 0x482


Name

QSPI Mode Register

QSPI Delay Register

QSPI Wrap Register

QSPI Interrupt Register

QSPI Address Register

QSPI Data Register

Real Time Clock Registers

RTC Hours and Minutes Register

RTC Seconds Counter Register

RTC Hours and Minutes Alarm Register

RTC Seconds Alarm Register

RTC Control Register

RTC Interrupt Status Register

RTC Interrupt Enable Register

RTC Stopwatch Minutes Register

RTC Days Counter Register

RTC Days Alarm Register

DMA Timer Registers

DMA Timer Mode Register 0

DMA Timer Extended Mode Register 0

DMA Timer Event Register 0

DMA Timer Reference Register 0

DMA Timer Capture Register 0

DMA Timer Counter Register 0










Mnemonic

QMR

QDLYR

QWR

QIR

QAR

QDR

DTMR0

DTXMR0

DTER0

DTRR0

DTCR0

DTCN0

DTMR1

DTXMR1

DTER1

DTRR1

DTCR1

DTCN1

DTMR2

DTXMR2

HOURMIN

SECONDS

ALARM_HM

ALARM_SEC

RTCCTL

RTCISR

RTCIENR

STPWCH

DAYS

ALARM_DAY



Preliminary

8

32

32

32

16

8

32

32

16

8

16

8

8

32

Size

16

16

16

16

16

16

32

32

32

32

32

32

32

32

32

32

A-7

Address

IPSBAR + 0x483

IPSBAR + 0x484

IPSBAR + 0x488

IPSBAR + 0x48C

IPSBAR + 0x4C0

IPSBAR + 0x4C2

IPSBAR + 0x4C3

IPSBAR + 0x4C4

IPSBAR + 0x4C8

IPSBAR + 0x4CC

IPSBAR + 0xC00

IPSBAR + 0xC04

IPSBAR + 0xC08

IPSBAR + 0xC0C

IPSBAR + 0xC10

IPSBAR + 0xC14

IPSBAR + 0xC18

IPSBAR + 0XC19

IPSBAR + 0xC41

IPSBAR + 0xC42

IPSBAR + 0xC43

IPSBAR + 0xC44

IPSBAR + 0xC45

IPSBAR + 0xC46

IPSBAR + 0xC47

IPSBAR + 0xC48

IPSBAR + 0xC49

IPSBAR + 0xC4A

IPSBAR + 0xC4B

IPSBAR + 0xC4C

IPSBAR + 0xC4D



Name











Interrupt Controller 0

Interrupt Pending Register High 0

Interrupt Pending Register Low 0

Interrupt Mask Register High 0

Interrupt Mask Register Low 0

Interrupt Force Register High 0

Interrupt Force Register Low 0

Interrupt Request Level Register 0

Interrupt Acknowledge Level and Priority Register 0

Interrupt Control Register 0-01













ICR001

ICR002

ICR003

ICR004

ICR005

ICR006

ICR007

ICR008

IPRH0

IPRL0

IMRH0

IMRL0

INTFRCH0

INTFRCL0

IRLR0

IACKLPR0

ICR009

ICR010

ICR011

ICR012

ICR013

Mnemonic

DTER2

DTRR2

DTCR2

DTCN2

DTMR3

DTXMR3

DTER3

DTRR3

DTCR3

DTCN3

Size

16

8

8

32

8

32

32

32

32

32

8

8

8

8

8

8

8

8

8

8

8

8

8

32

32

8

8

32

32

32

32

A-8



Preliminary


Name



































Address

IPSBAR + 0xC5F

IPSBAR + 0xC60

IPSBAR + 0xC61

ISPBAR + 0xC62

IPSBAR + 0xC63

IPSBAR + 0xC64

IPSBAR + 0xC65

IPSBAR + 0xC66

IPSBAR + 0xC67

IPSBAR + 0xC68

IPSBAR + 0xC69

IPSBAR + 0xC6A

IPSBAR + 0xC6B

IPSBAR + 0xC6C

IPSBAR + 0xC6D

IPSBAR + 0xC6E

IPSBAR + 0xC6F

IPSBAR + 0xC4E

IPSBAR + 0xC4F

IPSBAR + 0xC51

IPSBAR + 0xC52

IPSBAR +0xC53

IPSBAR + 0xC54

IPSBAR + 0xC55

IPSBAR + 0xC56

IPSBAR + 0xC57

IPSBAR + 0xC58

IPSBAR + 0xC59

IPSBAR + 0xC5A

IPSBAR + 0xC5B

IPSBAR + 0xC5C

IPSBAR + 0xC5D

IPSBAR + 0xC5E



Preliminary

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Mnemonic

ICR039

ICR040

ICR041

ICR042

ICR043

ICR044

ICR045

ICR046

ICR047

ICR031

ICR032

ICR033

ICR034

ICR035

ICR036

ICR037

ICR038

ICR023

ICR024

ICR025

ICR026

ICR027

ICR028

ICR029

ICR030

ICR014

ICR015

ICR017

ICR018

ICR019

ICR020

ICR021

ICR022

A-9

Address

IPSBAR + 0xC70

IPSBAR + 0xC71

IPSBAR + 0xC72

IPSBAR + 0xC73

IPSBAR + 0xC74

IPSBAR + 0xC75

IPSBAR + 0xC76

IPSBAR + 0xC77

IPSBAR + 0xC78

IPSBAR + 0xC79

IPSBAR + 0xC7A

IPSBAR + 0xC7B

IPSBAR + 0xC7C

IPSBAR + 0xC7D

IPSBAR + 0xC7E

IPSBAR + 0xCE0

IPSBAR + 0xCE4

IPSBAR + 0xCE8

IPSBAR + 0xCEC

IPSBAR + 0xCF0

IPSBAR + 0xCF4

IPSBAR + 0xCF8

IPSBAR + 0xCFC


IPSBAR + 0xD00

IPSBAR + 0xD04

IPSBAR + 0xD08

IPSBAR + 0xD0C

IPSBAR + 0xD10

IPSBAR + 0xD14

IPSBAR + 0xD18

IPSBAR + 0xD19


Name
















Software Interrupt Acknowledge Register 0

Level 1 Interrupt Acknowledge Register 0







Interrupt Controller 1

Interrupt Pending Register High 11

Interrupt Pending Register Low 11

Interrupt Mask Register High 11

Interrupt Mask Register Low 1

Interrupt Force Register High 1

Interrupt Force Register Low 1

Interrupt Request Level Register 1

Interrupt Acknowledge Level and Priority Register 1

Mnemonic

ICR056

ICR057

ICR058

ICR059

ICR060

ICR061

ICR062

SWACKR0

ICR048

ICR049

ICR050

ICR051

ICR052

ICR053

ICR054

ICR055

L1IACKR0

L2IACKR0

L3IACKR0

L4IACKR0

L5IACKR0

L6IACKR0

L7IACKR0

IPRH1

IPRL1

IMRH1

IMRL1

INTFRCH1

INTFRCL1

IRLR1

IACKLPR1

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

32

32

8

8

32

32

32

32

A-10



Preliminary


Name



































Address

IPSBAR + 0xD52

IPSBAR +0xC53

IPSBAR + 0xD54

IPSBAR + 0xD55

IPSBAR + 0xD56

IPSBAR + 0xD57

IPSBAR + 0xD58

IPSBAR + 0xD59

IPSBAR + 0xD5A

IPSBAR + 0xD5B

IPSBAR + 0xD5C

IPSBAR + 0xD5D

IPSBAR + 0xD5E

IPSBAR + 0xD5F

IPSBAR + 0xD61

IPSBAR + 0xD61

ISPBAR + 0xC62

IPSBAR + 0xD41

IPSBAR + 0xD42

IPSBAR + 0xD43

IPSBAR + 0xD44

IPSBAR + 0xD45

IPSBAR + 0xD46

IPSBAR + 0xD47

IPSBAR + 0xD48

IPSBAR + 0xD49

IPSBAR + 0xD4A

IPSBAR + 0xD4B

IPSBAR + 0xD4C

IPSBAR + 0xD4D

IPSBAR + 0xD4E

IPSBAR + 0xD4F

IPSBAR + 0xD51



Preliminary

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Mnemonic

ICR126

ICR127

ICR128

ICR129

ICR130

ICR131

ICR132

ICR133

ICR134

ICR118

ICR119

ICR120

ICR121

ICR122

ICR123

ICR124

ICR125

ICR109

ICR110

ICR111

ICR112

ICR113

ICR114

ICR115

ICR117

ICR101

ICR102

ICR103

ICR104

ICR105

ICR106

ICR107

ICR108

A-11


A-12

Address

IPSBAR + 0xD73

IPSBAR + 0xD74

IPSBAR + 0xD75

IPSBAR + 0xD76

IPSBAR + 0xD77

IPSBAR + 0xD78

IPSBAR + 0xD79

IPSBAR + 0xD7A

IPSBAR + 0xD7B

IPSBAR + 0xD7C

IPSBAR + 0xD7D

IPSBAR + 0xD7E

IPSBAR + 0xDE0

IPSBAR + 0xDE4

IPSBAR + 0xDE8

IPSBAR + 0xDEC

IPSBAR + 0xDF1

IPSBAR + 0xD63

IPSBAR + 0xD64

IPSBAR + 0xD65

IPSBAR + 0xD66

IPSBAR + 0xD67

IPSBAR + 0xD68

IPSBAR + 0xD69

IPSBAR + 0xD6A

IPSBAR + 0xD6B

IPSBAR + 0xD6C

IPSBAR + 0xD6D

IPSBAR + 0xD6E

IPSBAR + 0xD6F

IPSBAR + 0xD71

IPSBAR + 0xD71

IPSBAR + 0xD72


Name





























Software Interrupt Acknowledge Register 1





Mnemonic

ICR159

ICR160

ICR161

ICR162

SWACKR1

L1IACKR1

L2IACKR1

L3IACKR1

L4IACKR0

ICR151

ICR152

ICR153

ICR154

ICR155

ICR156

ICR157

ICR158

ICR143

ICR144

ICR145

ICR146

ICR147

ICR148

ICR149

ICR150

ICR135

ICR136

ICR137

ICR138

ICR139

ICR140

ICR141

ICR142

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8



Preliminary

Address

IPSBAR + 0xDF4

IPSBAR + 0xDF8

IPSBAR + 0xDFC

IPSBAR + 0xFE4

IPSBAR + 0xFE8

IPSBAR + 0xFEC

IPSBAR + 0xFF0

IPSBAR + 0xFF4

IPSBAR + 0xFF8

IPSBAR + 0xFFC

IPSBAR + 0x10_0000

IPSBAR + 0x10_0001

IPSBAR + 0x10_0002

IPSBAR + 0x10_0003

IPSBAR + 0x10_0004

IPSBAR + 0x10_0005

IPSBAR + 0x10_0006

IPSBAR + 0x10_0007

IPSBAR + 0x10_0008

IPSBAR + 0x10_0009

IPSBAR + 0x10_000A

IPSBAR + 0x10_000B

IPSBAR + 0x10_000C

IPSBAR + 0x10_000D

IPSBAR + 0x10_000E

IPSBAR + 0x10_000F

IPSBAR + 0x10_0010

IPSBAR + 0x10_0011

IPSBAR + 0x10_0012

IPSBAR + 0x10_0013



Name




Global Interrupt Acknowledge Cycle Registers

Global Level 1 Interrupt Acknowledge Register







GPIO Registers

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Port NQ Out Data Register

Reserved

Port AN Output Data Register

Port AS Output Data Register

Port QS Output Data Register

Reserved

Port TA Output Data Register

Port TC Output Data Register

Port TD Output Data Register

Port UA Output Data Register

Port UB Output Data Register

Port UC Output Data Register

Mnemonic

L5IACKR1

L6IACKR1

L7IACKR1

GL1IACKR

GL2IACKR

GL3IACKR

GL4IACKR

GL5IACKR

GL6IACKR

GL7IACKR

PORTNQ

—

PORTAN

PORTAS

PORTQS

—

PORTTA

PORTTC

—

—

—

—

—

—

—

—

PORTTD

PORTUA

PORTUB

PORTUC

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Size

8

8

8



Preliminary

A-13


A-14

Address

IPSBAR + 0x10_0014

IPSBAR + 0x10_0015

IPSBAR + 0x10_0016

IPSBAR + 0x10_0017

IPSBAR + 0x10_0018

IPSBAR + 0x10_0019

IPSBAR + 0x10_001A

IPSBAR + 0x10_001B

IPSBAR + 0x10_001C

IPSBAR + 0x10_001D

IPSBAR + 0x10_001E

IPSBAR + 0x10_001F

IPSBAR + 0x10_0020

IPSBAR + 0x10_0021

IPSBAR + 0x10_0022

IPSBAR + 0x10_0023

IPSBAR + 0x10_0024

IPSBAR + 0x10_0025

IPSBAR + 0x10_0026

IPSBAR + 0x10_0027

IPSBAR + 0x10_0028

IPSBAR + 0x10_0029

IPSBAR + 0x10_002A

IPSBAR + 0x10_002B

IPSBAR + 0x10_002C

IPSBAR + 0x10_002D

IPSBAR + 0x10_002E

IPSBAR + 0x10_002F

IPSBAR + 0x10_0030

IPSBAR + 0x10_0031

IPSBAR + 0x10_0032

IPSBAR + 0x10_0033

IPSBAR + 0x10_0034


Name

Port DD Output Data Register

Port LD Output Data Register

Port GP Output Data Register

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Port NQ Data Direction Register

Reserved

Port AN Data Direction Register

Port AS Data Direction Register

Port QS Data Direction Register

Reserved

Port TA Data Direction Register

Port TC Data Direction Register

Port TD Data Direction Register

Port UA Data Direction Register

Port UB Data Direction Register

Port UC Data Direction Register

Port DD Data Direction Register

Port LD Data Direction Register

Port GPData Direction Register

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Mnemonic

DDRDD

DDRLD

DDRGP

—

—

—

—

—

—

DDRQS

—

DDRTA

DDRTC

DDRTD

DDRUA

DDRUB

DDRUC

—

—

—

—

DDRNQ

—

DDRAN

DDRAS

PORTDD

PORTLD

PORTGP

—

—

—

—

—

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8



Preliminary

Address

IPSBAR + 0x10_0035

IPSBAR + 0x10_0036

IPSBAR + 0x10_0037

IPSBAR + 0x10_0038

IPSBAR + 0x10_0039

IPSBAR + 0x10_003A

IPSBAR + 0x10_003B

IPSBAR + 0x10_003C

IPSBAR + 0x10_003D

IPSBAR + 0x10_003E

IPSBAR + 0x10_003F

IPSBAR + 0x10_0040

IPSBAR + 0x10_0041

IPSBAR + 0x10_0042

IPSBAR + 0x10_0043

IPSBAR + 0x10_0044

IPSBAR + 0x10_0045

IPSBAR + 0x10_0046

IPSBAR + 0x10_0047

IPSBAR + 0x10_0048

IPSBAR + 0x10_0049

IPSBAR + 0x10_004A

IPSBAR + 0x10_004B

IPSBAR + 0x10_004C

IPSBAR + 0x10_004D


Name

Reserved

Reserved

Reserved

Port NQ Pin Data/Set Data Register

Reserved

Port AN Pin Data/Set Data Register

Port AS Pin Data/Set Data Register

Port QS Pin Data/Set Data Register

Reserved

Port TA Pin Data/Set Data Register

Port TC Pin Data/Set Data Register

Port TD Pin Data/Set Data Register

Port UA Pin Data/Set Data Register

Port UB Pin Data/Set Data Register

Port UC Pin Data/Set Data Register

Port DD Pin Data/Set Data Register

Port LD Pin Data/Set Data Register

Port GP Pin Data/Set Data Register

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved


Mnemonic

—

—

—

PORTNQ/

SETNQ

—

PORTDDP/

SETAN

PORTELP/

SETAS

PORTQSP/

SETQS

—

PORTSDP/

SETTA

PORTTCP/

SETTC

PORTTDP/

SETTD

PORTUAP/

SETUA

PORTUAP/

SETUB

—

—

—

—

—

—

—

PORTUAP/

SETUC

PORTDDP/

SETDD

PORTLDP/

SETLD

PORTGPP/

SETGP



Preliminary

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

A-15


A-16

Address

IPSBAR + 0x10_004E

IPSBAR + 0x10_004F

IPSBAR + 0x10_0050

IPSBAR + 0x10_0051

IPSBAR + 0x10_0052

IPSBAR + 0x10_0053

IPSBAR + 0x10_0054

IPSBAR + 0x10_0055

IPSBAR + 0x10_0056

IPSBAR + 0x10_0057

IPSBAR + 0x10_0058

IPSBAR + 0x10_0059

IPSBAR + 0x10_005A

IPSBAR + 0x10_005B

IPSBAR + 0x10_005C

IPSBAR + 0x10_005D

IPSBAR + 0x10_005E

IPSBAR + 0x10_005F

IPSBAR + 0x10_0060

IPSBAR + 0x10_0061

IPSBAR + 0x10_0062

IPSBAR + 0x10_0063

IPSBAR + 0x10_0064

IPSBAR + 0x10_0065

IPSBAR + 0x10_0066

IPSBAR + 0x10_0067

IPSBAR + 0x10_0068

IPSBAR + 0x10_006A

IPSBAR + 0x10_006B

IPSBAR + 0x10_006C

IPSBAR + 0x10_006E

IPSBAR + 0x10_006F

IPSBAR + 0x10_0070


Name

Reserved

Reserved

Port NQ Clear Output Data Register

Reserved

Port AN Clear Output Data Register

Port AS Clear Output Data Register

Port QS Clear Output Data Register

Reserved

Port TA Clear Output Data Register

Port TC Clear Output Data Register

Port TD Clear Output Data Register

Port UA Clear Output Data Register

Port UB Clear Output Data Register

Port UC Clear Output Data Register

Port DD Clear Output Data Register

Port LD Clear Output Data Register

Port GP Clear Output Data Register

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Reserved

Port NQ Pin Assignment Register

Port AN Pin Assignment Register

Port AS Pin Assignment Register

Port QS Pin Assignment Register

Port TA Pin Assignment Register

Port TC Pin Assignment Register

Port TD Pin Assignment Register

Mnemonic

—

—

PNQPAR

PANPAR

PASPAR

PQSPAR

PTAPAR

PTCPAR

PTDPAR

CLRGP

—

—

—

—

—

—

—

CLRTA

CLRTC

CLRTD

CLRUA

CLRUB

CLRUC

CLRDD

CLRLD

—

—

CLRNQ

—

CLRAN

CLRAS

CLRQS

—

Size

8

16

8

8

8

16

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8



Preliminary



Address

IPSBAR + 0x10_0071

IPSBAR + 0x10_0072

IPSBAR + 0x10_0073

IPSBAR + 0x10_0074

IPSBAR + 0x10_0075

IPSBAR + 0x10_0076

IPSBAR + 0x10_0077

IPSBAR + 0x10_0078

IPSBAR + 0x10_007A

IPSBAR + 0x10_007C

Name

Port UA Pin Assignment Register

Port UB Pin Assignment Register

Port UC Pin Assignment Register

Port DD Pin Assignment Register

Port LD Pin Assignment Register

Port GP Pin Assignment Register

Reserved

Port Wired OR Control Register

Port Drive Strength Register [47:32]

Port Drive Strength Register [31;0]

Mnemonic

Reset Control, Chip Configuration, and Power Management Registers

PUAPAR

PUBPAR

PUCPAR

PDDPAR

PLDPAR

PGPPAR

—

PWOR

PDSR

PDSR

IPSBAR + 0x11_0000

IPSBAR + 0x11_0001

IPSBAR + 0x11_0004

IPSBAR + 0x11_0007

IPSBAR + 0x11_0008

IPSBAR + 0x11_000A

IPSBAR + 0x11_000C

IPSBAR + 0x12_0000

IPSBAR + 0x12_0002

IPSBAR + 0x12_0006

IPSBAR + 0x12_0008

IPSBAR + 0x12_000C

IPSBAR + 0x13_0000

IPSBAR + 0x13_0002

IPSBAR + 0x13_0003

IPSBAR + 0x13_0004

IPSBAR + 0x13_0005

IPSBAR + 0x13_0006

IPSBAR + 0x14_0000

Reset Control Register

Reset Status Register

Chip Configuration Register

Low-Power Control Register

Reset Configuration Register

Chip Identification Register

Real Time Clock Divide Register

Clock Module Registers

Synthesizer Control Register

Synthesizer Status Register

Low Power Divider Register

Clock Control High Register

Real Time Clock Divide Register

Edge Port Registers

EPORT0 Pin Assignment Register

EPORT0 Data Direction Register

EPORT0 Interrupt Enable Register

EPORT0 Data Register

EPORT0 Pin Data Register

EPORT0 Flag Register

EPORT1 Pin Assignment Register

RCR

RSR

CCR

LPCR

RCON

CIR

RTCDF

SYNCR

SYNSR

LPDR

CCHR

RTCDR

EPPAR0

EPDDR0

EPIER0

EPDR0

EPPDR0

EPFR0

EPPAR1

Size

16

32

8

16

8

32

8

8

16

32

8

8

16

16

8

8

8

16

16

32

16

8

8

8

16

16

16

8

32



Preliminary

A-17


Address

IPSBAR + 0x14_0002

IPSBAR + 0x14_0003

IPSBAR + 0x14_0004

IPSBAR + 0x14_0005

IPSBAR + 0x14_0006

IPSBAR + 0x15_0000

IPSBAR + 0x15_0002

IPSBAR + 0x15_0004

IPSBAR + 0x16_0000

IPSBAR + 0x16_0002

IPSBAR + 0x16_0004

IPSBAR + 0x19_0000

IPSBAR + 0x19_0006

IPSBAR + 0x19_0007

IPSBAR + 0x19_0008

IPSBAR + 0x19_0009

IPSBAR + 0x19_000A

IPSBAR + 0x19_000C

IPSBAR + 0x19_000E

IPSBAR + 0x19_0010

IPSBAR + 0x19_0012

IPSBAR + 0x19_0200–

0x19_027E

IPSBAR + 0x19_0280–

0x19_02FE

IPSBAR + 0x19_0300–

0x19_037E

IPSBAR + 0x19_0380–

0x19_03FE


Name

EPORT1 Data Direction Register

EPORT1 Interrupt Enable Register

EPORT1 Data Register

EPORT1 Pin Data Register

EPORT1 Flag Register

Programmable Interrupt Timer 0 Registers

PIT Control and Status Register 0

PIT Modulus Register 0

PIT Count Register 0

Programmable Interrupt Timer 1 Registers

PIT Control and Status Register 1

PIT Modulus Register 1

PIT Count Register 1

ADC Registers

ADC Module Configuration Register

Port QA Data Register

Port QB Data Register

Port QA Data Direction Register

Port QB Data Direction Register

ADC Control Register 0



ADC Status Register 0

ADC Status Register 1

Conversion Command Word Table

Mnemonic

EPDDR1

EPIER1

EPDR1

EPPDR1

EPFR1

PCSR 0

PMR 0

PCNTR 0

PCSR 1

PMR 1

PCNTR 1

Right Justified, Unsigned Result Register

Left Justified, Signed Result Register

Left Justified, Unsigned Result Register

ADCMCR

PORTQA

PORTQB

DDRQA

DDRQB

ACR0

ACR1

ACR2

ASR0

ASR1

CCW0–

CCW63

RJURR0–

RJURR63

LJSRR0–

LJSRR63

LJURR0–

LJURR63

General Purpose Timer A Registers

16

16

16

16

16

16

8

16

16

16

16

8

8

8

16

16

64x16

64x16

64x16

64x16

Size

8

8

8

8

8

A-18



Preliminary

Address

IPSBAR + 0x1A_0000

IPSABAR + 0x1A_0001

IPSBAR + 0x1A_0002

IPSBAR + 0x1A_0003

IPSBAR + 0x1A_0004

IPSBAR + 0x1A_0006

IPSBAR + 0x1A_0008

IPSBAR + 0x1A_0009

IPSBAR + 0x1A_000B

IPSBAR + 0x1A_000C

IPSBAR + 0x1A_000D

IPSBAR + 0x1A_000E

IPSBAR + 0x1A_000F

IPSBAR + 0x1A_0010

IPSBAR + 0x1A_0012

IPSBAR + 0x1A_0014

IPSBAR + 0x1A_0016

IPSBAR + 0x1A_0018

IPSBAR + 0x1A_0019

IPSBAR + 0x1A_001a

IPSBAR + 0x1A_001D

IPSBAR + 0x1A_001E

IPSBAR + 0x1B_0000

IPSBAR + 0x1B_0001

IPSBAR + 0x1B_0002

IPSBAR + 0x1B_0003

IPSBAR + 0x1B_0004

IPSBAR + 0x1B_0005

IPSBAR + 0x1B_0008

IPSBAR + 0x1B_0009

IPSBAR + 0x1B_000C



Name

GPTA IC/OC Select Register

GPTA Compare Force Register

GPTA Output Compare 3 Mask Register

GPTA Output Compare 3 Data Register

GPTA Counter Register

GPTA System Control Register 1

GPTA Toggle-on-Overflow Register

GPTA Control Register 1

GPTA Control Register 2

GPTA Interrupt Enable Register

GPTA System Control Register 2

GPTA Flag Register 1

GPTA Flag Register 2

GPTA Channel 0 Register




Pulse Accumulator Control Register

Pulse Accumulator Flag Register

Pulse Accumulator Counter Register

GPTA Port Data Register

GPTA Port Data Direction Register

Pulse Width Modulator

PWM Enable Register

PWM Polarity Register

PWM Clock Select Register

PWM Prescale Clock Select Register

PWM Center Align Enable Register

PWM Control Register

PWM Scale A Register

PWM Scale B Register

PWM channel Counter Register 0

Mnemonic

GPTAIOS

GPTACFORC

GPTAOC3M

GPTAOC3D

GPTACNT

GPTASCR1

GPTATOV

GPTACTL1

GPTACTL2

GPTAIE

GPTASCR2

GPTAFLG1

GPTAFLG2

GPTAC0

GPTAC1

GPTAC2

GPTAC3

GPTAPACTL

GPTPAFLG

GPTAPACNT

GPTAPORT

GPTADDR

PWME

PWMPOL

PWMCLK

PWMPRCLK

PWMCAE

PWMCTL

PWMSCLA

PWMSCLB

PWMCNT0

8

8

8

8

8

8

8

8

8

Size

8

16

16

16

8

8

8

8

16

8

8

8

8

8

8

8

16

8

8

8

8

8



Preliminary

A-19


Address

IPSBAR + 0x1B_000D

IPSBAR + 0x1B_000E

IPSBAR + 0x1B_000F

IPSBAR + 0x1B_0010

IPSBAR + 0x1B_0011

IPSBAR + 0x1B_0012

IPSBAR + 0x1B_0013

IPSBAR + 0x1B_0014

IPSBAR + 0x1B_0015

IPSBAR + 0x1B_0016

IPSBAR + 0x1B_0017

IPSBAR + 0x1B_0018

IPSBAR + 0x1B_0019

IPSBAR + 0x1B_001A

IPSBAR + 0x1B_001B

IPSBAR + 0x1C_0000

IPSBAR + 0x1C_0004

IPSBAR + 0x1C_0008

IPSBAR + 0x1C_000C

IPSBAR + 0x1C_0010

IPSBAR + 0x1C_0014

IPSBAR + 0x1C_0018

IPSBAR + 0x1C_001C

IPSBAR + 0x1C_0020

IPSBAR + 0x1C_0024

IPSBAR + 0x1C_0028

IPSBAR + 0x1C_002C

IPSBAR + 0x1C_0030

IPSBAR + 0x1C_0080

IPSBAR + 0x1D_0000


Name








PWM Channel Period Register 0








FlexCAN Registers

Module Configuration Register

FlexCAN Control Register

Free Running TImer

Reserved

Rx Global Mask

Rx Buffer 14 Mask

Rx Buffer 15 Mask

Error Counter Register

Error and Status

Reserved

Interrupt Mask Register

Reserved

Interrupt Flag Register

Message Buffer 0 - Message Buffer 15

Mnemonic

PWMCNT1

PWMCNT2

PWMCNT3

PWMCNT4

PWMCNT5

PWMCNT6

PWMCNT7

PWMPER0

PWMPER1

PWMPER2

PWMPER3

PWMPER4

PWMPER5

PWMPER6

PWMPER7

CANMCR

CANCTRL

TIMER

—

RXGMASK

RX14MASK

RX15MASK

ERRCNT

ERRSTAT

—

IMASK

—

IFLAG

MBUFF0–

MBUFF15

32

32

32

32

32

16x16bytes

32

32

32

32

16

32

32

32

Size

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Flash Registers

CFM Configuration Register CFMMCR 16

A-20



Preliminary



Address

IPSBAR + 0x1D_0002

IPSBAR + 0x1D_0008

IPSBAR + 0x1D_0010

IPSBAR + 0x1D_0014

IPSBAR + 0x1D_0018

IPSBAR + 0x1D_0020

IPSBAR + 0x1D_0024

Name

CFM Clock Divider Register

CFM Security Register

CFM Protection Register

CFM Supervisor Access Register

CFM Data Access Register

CFM User Status Register

CFM Command Register

Mnemonic

CFMCLKD

CFMSEC

CFMPROT

CFMSACC

CFMDACC

CFMUSTAT

CFMCMD

Size

IPSBAR + 0x1E_0000

IPSBAR + 0x1E_0001

IPSBAR + 0x1E_0002

IPSBAR + 0x1E_0003

Ethernet Physical Transceiver Registers

Ethernet Physical Transceiver Control Register 0

Ethernet Physical Transceiver Control Register 1

Ethernet Physical Transceiver Status Register

Reserved

Random Number Generator H/W Accelerator Registers

EPHYCTL0

EPHYCTL1

EPHYSR

—

IPSBAR + 0x1F_0000

IPSBAR + 0x1F_0004

Random Number Generator Control Register

Random Number Generator Status Register 1

RNGCR

RNGSR

32

32

IPSBAR + 0x1F_0008 Random Number Generator Entropy Register RNGER 32

IPSBAR + 0x1F_000C Random Number Generator Output Register RNGOUT 32-

1

UMR1 n , UMR2 n , and UCSR n should be changed only after the receiver/transmitter is issued a software reset command. That is, if channel operation is not disabled, undesirable results may occur.

8

8

8

8

8

8

32

32

8

32

32



Preliminary

A-21


A-22



Preliminary