Dallas DS5000(T) Manual

DS5000(T)

Soft Microcontroller Module

www.maxim-ic.com

FEATURES

8-Bit 8051-Compatible Microcontroller

Adapts to Task at Hand

8 or 32 kbytes of Nonvolatile RAM for

Program and/or Data Memory Storage

Initial Downloading of Software in End

System via On-Chip Serial Port

Capable of Modifying Its Own Program and/or Data Memory in End Use

Crashproof Operation

Maintains All Nonvolatile Resources for 10

Years in the Absence of V

CC

at Room

Temperature

Power-Fail Reset

Early Warning Power-Fail Interrupt

Watchdog Timer

Software Security Feature

Executes Encrypted Software to Prevent

Unauthorized Disclosure

On-Chip, Full-Duplex Serial I/O Ports

Two On-Chip Timer/Event Counters

32 Parallel I/O Lines

Compatible with Industry Standard 8051

Instruction Set and Pinout

Optional Permanently Powered Real-Time

Clock (DS5000T)

DESCRIPTION

PIN ASSIGNMENT

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

1

2

3

4

5

6

P1.6

7

40

DS5000(T) 38

P1.7

8

39

37

36

35

34

33

RST

RXD P3.0

TXD P3.1

INT0 P3.2

INT1 P3.3

T0 P3.4

T1 P3.5

WR P3.6

RD P3.7

XTAL2

XTAL1

GND

9

10

11

12

13

14

15

16

17

18

19

20

32

31

30

29

28

27

26

25

24

23

22

21

V

CC

P0.0 AD0

P0.1 AD1

P0.2 AD2

P0.3 AD3

P0.4 AD4

P0.5 AD5

P0.6 AD6

P0.7 AD7

EA

ALE

PSEN

P2.7 A15

P2.6 A14

P2.5 A13

P2.4 A12

P2.3 A11

P2.2 A10

P2.1 A9

P2.0 A8

40-Pin Encapsulated Package

The DS5000(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of nonvolatile technology to preserve all information in the absence of system V

CC

. The internal program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile CMOS SRAM.

Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional realtime clock (RTC) gives permanently powered timekeeping. The clock keeps time to a hundredth of a second using an on-board crystal.

Note: This data sheet provides ordering information, pinout, and electrical specifications. Refer to the

Secure Microcontroller User’s Guide for operating information.

Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: www.maxim-ic.com/errata .

1 of 19 REV: 070706

DS5000(T)

ORDERING INFORMATION

PART RAM SIZE (kB)

MAX CRYSTAL

SPEED (MHz)

TIMEKEEPING?

DS5000 -32-16 32 16 No

DS5000-32-16+ 32 16 No

DS5000T -32-16 32 16 Yes

DS5000T-32-16+ 32 16 Yes

+ Denotes a lead-free package.

DS5000(T) BLOCK DIAGRAM

Figure 1

2 of 19

PIN DESCRIPTION

PIN NAME

1–8 P1.0–P1.7 General-Purpose I/O Port 1

FUNCTION

DS5000(T)

12 P3.2/ INT0 General-Purpose I/O Port Pin 3.2/Active-Low External Interrupt 0

13 P3.3/ INT1 General-Purpose I/O Port Pin 3.3/Active-Low External Interrupt 1

14

15

P3.4/T0

P3.5/T1

General-Purpose I/O Port Pin 3.4/Timer 0 Input

General-Purpose I/O Port Pin 3.5/Timer 1 Input

16 P3.6/

17 P3.7/

18, 19

WR

RD

XTAL2,

XTAL1

General-Purpose I/O Port Pin 3.6/Active-Low Write Strobe for Expanded Bus

Operation

General-Purpose I/O Port Pin 3.7/Active-Low Read Strobe for Expanded Bus

Operation

Crystal Connection. Used to connect an external crystal to the internal oscillator.

XTAL1 is the input to an inverting amplifier and XTAL2 is the output.

21–28

29

P2.0–P2.7/

A8–A15

PSEN

General-Purpose I/O Port 2/MSB of the Expanded Address Bus

Active-Low Program Store Enable. Used to enable an external program memory when using the expanded bus. It is normally an output and should be unconnected if not used. PSEN also is used to invoke the bootstrap loader. At this time, PSEN is pulled down externally. This should only be done once the DS5000(T) is already in a reset state. The device that pulls down should be open drain since it must not interfere with PSEN under normal operation.

Address Latch Enable. Used to demultiplex the multiplexed expanded address/data

31 EA

PROG function for programming pulses.

Active-Low External Access. This pin forces the DS5000(T) to behave like an

8031. No internal memory (or clock) is available when this pin is at a logic low.

Since this pin is pulled down internally, it should be connected to +5V to use NV

RAM. In a parallel programmer, this pin also serves as V

PP

for super voltage pulses.

32-39

P0.7–P0.0/

AD7–AD0

General-Purpose I/O Port 0/Multiplexed Expanded Address/Data Bus. This port is open drain and cannot drive a logic 1. It requires external pullups. When used in the multiplexed expanded address data/bus mode, this pin does not require pullups.

40 V

CC

Power

3 of 19

DS5000(T)

INSTRUCTION SET

The DS5000(T) executes an instruction set which is object code-compatible with the industry standard

8051 microcontroller. As a result, software development packages that have been written for the 8051, including cross-assemblers, high-level language compilers, and debugging tools, are compatible with the

DS5000(T).

A complete description for the DS5000(T) instruction set is available in Secure Microcontroller User’s

Guide .

MEMORY ORGANIZATION

Figure 2 illustrates the address spaces, which are accessed by the DS5000(T). As illustrated in the figure, separate address spaces exist for program and data memory. Since the basic addressing capability of the machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be accessed by the DS5000(T) CPU. The 8- or 32-kbyte RAM area inside of the DS5000(T) can be used to contain both program and data memory.

The real-time clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The

MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2 = 1, all MOVXs will be routed to this alternate memory map. The RTC is a serial device that resides in this area. A full description of the RTC access and example software is given in the Secure Microcontroller User’s Guide .

If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent memory. Software execution would not be affected otherwise.

4 of 19

DS5000(T) LOGICAL ADDRESS SPACES

Figure 2

DS5000(T)

PROGRAM LOADING

The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization may be performed in one of two ways:

1. Serial Program Loading that can perform Bootstrap Loading of the DS5000(T). This feature allows the loading of the application program to be delayed until the DS5000(T) is installed in the end system. Dallas Semiconductor strongly recommends the use of serial program loading because of its versatility and ease of use.

2. Parallel Program Load cycles that perform the initial loading from parallel address/data information presented on the I/O port pins. This mode is timing-set compatible with the 8751H microcontroller programming mode.

The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the

RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS5000(T) will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at

9600, 2400, 1200, or 300 bps over the serial port.

The hardware configurations used to select these modes of operation are illustrated in Figure 3.

5 of 19

PROGRAM LOADING CONFIGURATIONS

Figure 3

DS5000(T)

Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated with these cycles is illustrated in the electrical specs.

SERIAL BOOTSTRAP LOADER

The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of initially loading application software into the DS5000(T) nonvolatile RAM. Communication can be performed over a standard asynchronous serial communications port. A typical application would use a simple RS232C serial interface to program the DS5000(T) as a final production procedure. The hardware configuration required for the Serial Program Load mode is illustrated in Figure 3. Port pins 2.7 and 2.6 must be either open or pulled high to avoid placing the DS5000(T) in a parallel load cycle. Although an

11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a standard UART. The receive, transmit, and ground wires are all that are necessary to establish communication with the DS5000(T).

The Serial Bootstrap Loader implements an easy-to-use command line interface that allows an application program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the typical format which existing 8051 cross-assemblers output. The serial loader responds to single character commands, which are summarized below:

6 of 19

DS5000(T)

COMMAND

C

D

F

K

L

R

T

U

V

FUNCTION

Return CRC-16 checksum of embedded RAM

Dump Intel hex file

Fill embedded RAM block with constant

Load 40-bit encryption key

Load Intel hex file

Read MCON register

Trace (echo) incoming Intel hex data

Clear security lock

Verify embedded RAM with incoming Intel hex

Z

P

Set

Put a value to a port

G Get a value from a port

PARALLEL PROGRAM LOAD CYCLES

Table 1

MODE RST PROG

Security Set 1 0 0

EA P2.7 P2.6 P2.5

1 0 X

V

PP

1 1 X

Prog Expanded 1 0 0 V

PP

0 1 0

Verify 1 0 1 1 0 1 0

Prog MCON or Key registers 1 0 0 V

PP

0 1 1

Verify MCON registers 1 0 1 1 0 1 1

The Parallel Program Cycle is used to load a byte of data into a register or memory location within the

DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded value to verify proper loading. The Security Set Cycle may be used to enable and the Software Security feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption registers using the Program MCON cycle. When using this cycle, the absolute register address must be presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents can likewise be verified using the Verify MCON cycle.

When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in the Program Load Mode following a Power-On Reset, the internal hardware of the DS5000(T) is initialized so that an existing 4-kbyte program can be programmed into a DS5000(T) with little or no modification. This initialization automatically sets the Range Address for 8 kbytes and maps the lowest 4kbyte bank of Embedded RAM as program memory. The next 4 kbytes of Embedded RAM are mapped as Data Memory.

In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32-kbyte

Program/ Verify cycles take much longer than the normal 4-kbyte Program/Verify cycles.

7 of 19

DS5000(T)

A typical parallel loading session would follow this procedure. First, set the contents of the MCON register with the correct range and partition only if using expanded programming cycles. Next, the encryption registers can be loaded to enable encryption of the program/data memory (not required). Then, program the DS5000(T) using either normal or expanded program cycles and check the memory contents using Verify cycles. The last operation would be to turn on the security lock feature by either a Security

Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.

SERIAL LOADER BAUD RATES FOR

DIFFERENT CRYSTAL FREQUENCIES

Table 2

CRYSTAL FREQ

(MHz)

BAUD RATE

ADDITIONAL INFORMATION

Refer to the Secure Microcontroller User’s Guide for a complete description for all operational aspects of the DS5000(T).

DEVELOPMENT SUPPORT

The DS89C450-K00 evaluation kit ( www.maxim-ic.com/DS89C450evkit ) can be used to develop and test user code. It allows the user to download Intel hex-formatted code to the DS5000(T) from a PC.

Refer to the Secure Microcontroller User’s Guide for more information.

8 of 19

DS5000(T)

ABSOLUTE MAXIMUM RATINGS

Voltage on Any Pin Relative to Ground…………………………………………………….-0.3V to +7.0V

Operating Temperature…………………………………………………………………….….0°C to +70°C

Storage Temperature………………………………………………………………………...-40°C to +70°C

Soldering Temperature.…………………………………………See IPC/JEDEC J-STD-020 Specification

This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.

DC CHARACTERISTICS

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

PARAMETER SYMBOL MIN

Input Low Voltage -0.3 0.8 V 1

Input High Voltage

Input High Voltage RST, XTAL1

V

IL

V

IH1

V

IH2

V

OL1

2.0

CC

+0.3 V 1

V

CC

+0.3 V 1

0.15 0.45 V Output Low Voltage

@ I

OL

=1.6 mA (Ports 1, 2, 3)

Output Low Voltage

@ I

OL

=3.2 mA (Ports 0, ALE, PSEN )

V

OL2

0.15 0.45 V 1

V

OH1

2.4 4.8 V 1 Output High Voltage

@ I

OH

=-80 µ A (Ports 1, 2, 3)

Output High Voltage

@ I

OH

=-400 µ A (Ports 0, ALE, PSEN )

Input Low Current V

IN

(Ports 1, 2, 3)

= 0.45V

Transition Current; 1 to 0

V

IN

=2.0V (Ports 1, 2, 3)

Input Leakage Current

0.45 < V

IN

< V

CC

(Port 0)

RST, EA Pulldown Resistor

Stop Mode Current

Power-Fail Warning Voltage

Minimum Operating Voltage

Programming Supply Voltage

(Parallel Program Mode)

Program Supply Current

Operating Current DS5000-8k @ 8MHz

DS5000-32k @ 12 MHz

DS5000(T)-32-16 @ 16 MHz

Idle Mode Current @ 12 MHz

V

OH2

I

IL

I

TL

I

L

R

RE

I

SM

V

PFW

V

CCmin

V

PP

I

PP

I

CC

I

CC

2.4 4.8 V 1

-50 A

-500 A

± 10 µ A

40 125 k Ω

80 A 4

4.15 4.6 4.75 V 1

4.05 4.5 4.65 V 1

12.5 13 V 1

15 20 mA

25.2

35.7

45.6

43

48

54 mA 2

4.5 6.2 mA 3

9 of 19

DS5000(T)

AC CHARACTERISTICS: EXPANDED

BUS MODE TIMING SPECIFICATIONS

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

# PARAMETER SYMBOL MIN MAX UNITS

2 ALE Pulse Width

3 Address Valid to ALE Low

4 Address Hold After ALE Low

5 ALE Low to Valid Instr. In

6 ALE Low to

PSEN Low

@ 12 MHz

@ 16 MHz

1/t

CLK t

ALPW t

AVALL t

AVAAV t

ALLVI t

ALLPSL

2t

CLK

-40 t

CLK

-40 t

CLK

-35

4t

CLK

-150

4t

CLK

-90 t

CLK

-25 ns ns ns ns ns ns t

PSPW

3t

CLK

-35 ns 7

PSEN Pulse Width

8

PSEN Low to Valid Instr. In @ 12 MHz

@ 16 MHz

9 Input Instr. Hold after

PSEN Going High

10 Input Instr. Float after

PSEN Going High

11 Address Hold after

PSEN Going High

12 Address Valid to Valid Instr. In @ 12 MHz

@ 16 MHz

13

PSEN Low to Address Float

14

RD Pulse Width

15

WR Pulse Width

16

RD Low to Valid Data In

17 Data Hold after

RD High

@ 12 MHz

@ 16 MHz

18 Data Float after RD High

19 ALE Low to Valid Data In

20 Valid Addr. to Valid Data In @ 12 MHz

@ 16 MHz

21 ALE Low to

RD or WR Low

@ 12 MHz

@ 16 MHz

22 Address Valid to

RD or WR Low

23 Data Valid to

WR Going Low

24 Data Valid to

WR High

25 Data Valid after

WR High

26

RD Low to Address Float

27

RD or WR High to ALE High

@ 12 MHz

@ 16 MHz t

PSLVI t

PSIV t

PSIX t

PSAV t

AVVI t

PSLAZ t

RDPW t

WRPW t

RDLDV t

RDHDV t

RDHDZ t

ALLVD t

AVDV t

ALLRDL t

WRHDV t

RDLAZ t

RDHALH

3t

CLK

-150

3t

CLK

-90 t

CLK

-20 t

CLK

-8

5t

CLK

-150

5t

CLK

-90

6t

CLK

-100

6t

CLK

-100

5t

CLK

-165

5t

CLK

-105

2t

CLK

-70

8

CLK

-150

8t

CLK

-90

9t

CLK

9t

CLK

-165

-105

3t

CLK

-50 3t

CLK

+50 t

AVRDL

4t

CLK

-130 t

DVWRL t

DVWRH t

CLK

-60

7t

CLK

-150

7t

CLK

-90 t

CLK

-50 t

CLK

-40 t

CLK

+50 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns

10 of 19

EXPANDED PROGRAM MEMORY READ CYCLE

DS5000(T)

EXPANDED DATA MEMORY READ CYCLE

11 of 19

EXPANDED DATA MEMORY WRITE CYCLE

DS5000(T)

EXTERNAL CLOCK TIMING

12 of 19

DS5000(T)

AC CHARACTERISTICS

(cont'd)

EXTERNAL CLOCK DRIVE

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

# PARAMETER SYMBOL MIN MAX UNITS t

CLKHPW

28 External Clock High Time

29 External Clock Low Time

@ 12 MHz

@ 16 MHz

@ 12 MHz

@ 16 MHz t

CLKLPW

20

15

20

15 ns ns ns ns

30 External Clock Rise Time @ 12 MHz

@ 16 MHz t

CLKR

20

15 ns ns

31 External Clock Fall Time @ 12 MHz

@ 16 MHz t

CLKF

20

15 ns ns

AC CHARACTERISTICS

(cont'd)

SERIAL PORT TIMING - MODE 0

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

# PARAMETER SYMBOL MIN MAX UNITS

35 Serial Port Cycle Time t

SPCLK

12t

CLK

µ s

36 Output Data Setup to Rising Clock Edge

37 Output Data Hold after Rising Clock Edge

38 Clock Rising Edge to Input Data Valid

39 Input Data Hold after Rising Clock Edge

SERIAL PORT TIMING - MODE 0

t

DOCH t

CHDO t

CHDV t

CHDIV

10t

CLK

-133

2t

CLK

-117

10t

CLK

-133 ns ns ns

13 of 19

DS5000(T)

AC CHARACTERISTICS

(cont'd)

POWER CYCLING TIMING

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

# PARAMETER SYMBOL MIN MAX UNITS

32 Slew Rate from V

CCmin

to 3.3V t

F

40 µ s

33 Crystal Start-up Time t

CSU t

POR

34 Power-on Reset Delay

POWER CYCLE TIMING

14 of 19

DS5000(T)

AC CHARACTERISTICS

(cont'd)

PARALLEL PROGRAM LOAD TIMING

(t

A

=0 ° C to 70 ° C; V

CC

=5V ± 5%)

# PARAMETER SYMBOL MIN MAX UNITS

41 Address Setup to

PROG Low

1/t

CLK t

AVPRL

0

42 Address Hold after

PROG High

43 Data Setup to

PROG Low

44 Data Hold after

PROG High

45 P2.7, 2.6, 2.5 Setup to V

PP

46 V

PP

Setup to PROG Low

47 V

PP

Hold after PROG Low t t t t t t

PRHAV

DVPRL

PRHDV

P27HVP

VPHPRL

PRHVPL

0

0

0

0

0

0

48

PROG Width Low

49 Data Output from Address Valid

50 Data Output from P2.7 Low

51 Data Float after P2.7 High t t t t

PRW

AVDV

DVP27L

P27HDZ

48

1800*

48

1800* t t

CLK

CLK

0 48

1800* t

CLK

21504 t

CLK

52 Delay to Reset/

PSEN Active after Power On t

PORPV

53 Reset/

PSEN Active (or Verify Inactive) to

V

PP

High t

RAVPH

1200

54 V

PP

Inactive (Between Program Cycles)

55 Verify Active Time t

VPPPC t

VFT

1200

48

2400*

* Second set of numbers refers to expanded memory programming up to 32k bytes. t

CLK

15 of 19

PARALLEL PROGRAM LOAD TIMING

DS5000(T)

CAPACITANCE

(test frequency=1MHz; t

A

=25 ° C)

PARAMETER SYMBOL MIN

Output Capacitance

Input Capacitance

C

O

C

I

10 pF

10 pF

16 of 19

DS5000(T) TYPICAL I

CC

VS. FREQUENCY

DS5000(T)

Normal operation is measured using:

1) External crystals on XTAL1 and 2

2) All port pins disconnected

3) RST=0 volts and EA=V

CC

4) Part performing endless loop writing to internal memory

Idle mode operation is measured using:

1) External clock source at XTAL1; XTAL2 floating

2) All port pins disconnected

3) RST=0 volts and EA=V

CC

4) Part set in IDLE mode by software

17 of 19

DS5000(T)

NOTES:

1. All voltages are referenced to ground.

2. Maximum operating I

CC

is measured with all output pins disconnected; XTAL1 driven with t

CLKR

, t

CLKF

= 10 ns, V

IL

= 0.5V; XTAL2 disconnected; EA = RST = PORT0 = V

CC

.

3. Idle mode I

CC

is measured with all output pins disconnected; XTAL1 driven with t

V

IL

= 0.5V; XTAL2 disconnected; EA = PORT0 = V

CC

, RST = V

SS

.

CLKR

, t

CLKF

= 10 ns,

4. Stop mode I

CC

is measured with all output pins disconnected; connected; RST = V

SS

.

EA = PORT0 = V

CC

; XTAL2 not

5. Crystal start-up time is the time required to get the mass of the crystal into vibrational motion from the time that power is first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal vendor for the worst case spec on this time.

PACKAGE DRAWING

INCHES

DIM

MIN MAX

A IN.

B IN.

C IN.

D IN.

E IN.

F IN.

G IN.

H IN.

I IN.

2.080 2.100

0.680 0.700

0.290 0.325

0.090 0.110

0.030 0.060

0.145 0.185

0.016 0.020

0.590 0.610

0.009 0.015

18 of 19

DS5000(T)

DATA SHEET REVISION SUMMARY

REVISION DESCRIPTION

072095 to

072496

Corrected Figure 3 to show RST active high.

Added Data Sheet Revision Summary section.

112299 Converted from Interleaf to Word.

Page 1: Features

Added “at Room Temperature” to “Maintains All Nonvolatile Resources Up to 10

Years in the Absence of V

CC

” bullet.

Page 2: Ordering Information

Removed 8kB parts from list; added 32kB and lead-free packages.

070706

Page 8: Development Support

Updated paragraph to reflect availability of DS89C450-K00 evaluation kit, not

DS5000TK.

Page 9: Absolute Maximum Ratings

Changed “260 ° C for 10 seconds” to “See IPC/JEDEC J-STD-020 Specification.”

Pages 1, 4, 8: Replaced references to “User’s Guide section of Secure

Microcontroller Data Book” with “Secure Microcontroller User’s Guide.”

19 of 19

Maxim/Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim/Dallas Semiconductor product.

No circuit patent licenses are implied. Maxim/Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time.

Ma x i m I n t e g r a t e d P ro d u c t s , 1 2 0 S a n G a b r i e l D r i v e , S u n n y v a l e , C A 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0

© 2006 Maxim Integrated Products

The Maxim logo is a registered trademark of Maxim Integrated Products, Inc. The Dallas logo is a registered trademark of Dallas Semiconductor Corporation.

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